diff options
| author |   Madhavan Srinivasan <maddy@linux.ibm.com> | 2022-01-27 12:49:55 +0530 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2022-03-01 23:38:12 +1100 |
| commit | 6523dce86222451e5ca2df8a46597a217084bfdf (patch) | |
| tree | eff8f7bd95d4d150ef5ab023f986fc26d4a1734c /tools/testing/selftests/powerpc/include | |
| parent | selftests/powerpc/pmu: Add support for perf sampling tests (diff) | |
| download | linux-dev-6523dce86222451e5ca2df8a46597a217084bfdf.tar.xz linux-dev-6523dce86222451e5ca2df8a46597a217084bfdf.zip | |
selftests/powerpc/pmu: Add macros to parse event codes
Each platform has raw event encoding format which specifies the bit
positions for different fields. The fields from event code gets
translated into performance monitoring mode control register (MMCRx)
settings. Patch add macros to extract individual fields from the event
code.
Add functions for sanity checks, since testcases currently are only
supported in power9 and power10.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
[mpe: Read PVR directly rather than using /proc/cpuinfo]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220127072012.662451-4-kjain@linux.ibm.com
Diffstat (limited to 'tools/testing/selftests/powerpc/include')
| -rw-r--r-- | tools/testing/selftests/powerpc/include/reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tools/testing/selftests/powerpc/include/reg.h b/tools/testing/selftests/powerpc/include/reg.h index c0f2742a3a59..c422be8a42b2 100644 --- a/tools/testing/selftests/powerpc/include/reg.h +++ b/tools/testing/selftests/powerpc/include/reg.h @@ -52,6 +52,9 @@ #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ #define SPRN_TAR 0x32f /* Target Address Register */ +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) +#define SPRN_PVR 0x11F + #define SPRN_DSCR_PRIV 0x11 /* Privilege State DSCR */ #define SPRN_DSCR 0x03 /* Data Stream Control Register */ #define SPRN_PPR 896 /* Program Priority Register */ @@ -84,6 +87,7 @@ #define TEXASR_ROT 0x0000000002000000 /* MSR register bits */ +#define MSR_HV (1ul << 60) /* Hypervisor state */ #define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */ #define MSR_TS_T_LG 34 /* Trans Mem state: Active */ |