diff options
| author |   Björn Töpel <bjorn.topel@gmail.com> | 2019-05-22 11:23:23 +0200 |
|---|---|---|
| committer |   Daniel Borkmann <daniel@iogearbox.net> | 2019-05-23 15:55:17 +0200 |
| commit | 00d8304553de529802430799d2b2566fd32859d4 (patch) | |
| tree | 473f9c1df30dac8de3b4ada7c41cfe0a3c8e1838 /tools | |
| parent | bpf, riscv: clear target register high 32-bits for and/or/xor on ALU32 (diff) | |
| download | linux-dev-00d8304553de529802430799d2b2566fd32859d4.tar.xz linux-dev-00d8304553de529802430799d2b2566fd32859d4.zip | |
selftests: bpf: add zero extend checks for ALU32 and/or/xor
Add three tests to test_verifier/basic_instr that make sure that the
high 32-bits of the destination register is cleared after an ALU32
and/or/xor.
Signed-off-by: Björn Töpel <bjorn.topel@gmail.com>
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/testing/selftests/bpf/verifier/basic_instr.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/tools/testing/selftests/bpf/verifier/basic_instr.c b/tools/testing/selftests/bpf/verifier/basic_instr.c index ed91a7b9a456..4d844089938e 100644 --- a/tools/testing/selftests/bpf/verifier/basic_instr.c +++ b/tools/testing/selftests/bpf/verifier/basic_instr.c @@ -132,3 +132,42 @@ .prog_type = BPF_PROG_TYPE_SCHED_CLS, .result = ACCEPT, }, +{ + "and32 reg zero extend check", + .insns = { + BPF_MOV64_IMM(BPF_REG_0, -1), + BPF_MOV64_IMM(BPF_REG_2, -2), + BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2), + BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), + BPF_EXIT_INSN(), + }, + .prog_type = BPF_PROG_TYPE_SCHED_CLS, + .result = ACCEPT, + .retval = 0, +}, +{ + "or32 reg zero extend check", + .insns = { + BPF_MOV64_IMM(BPF_REG_0, -1), + BPF_MOV64_IMM(BPF_REG_2, -2), + BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2), + BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), + BPF_EXIT_INSN(), + }, + .prog_type = BPF_PROG_TYPE_SCHED_CLS, + .result = ACCEPT, + .retval = 0, +}, +{ + "xor32 reg zero extend check", + .insns = { + BPF_MOV64_IMM(BPF_REG_0, -1), + BPF_MOV64_IMM(BPF_REG_2, 0), + BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2), + BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), + BPF_EXIT_INSN(), + }, + .prog_type = BPF_PROG_TYPE_SCHED_CLS, + .result = ACCEPT, + .retval = 0, +}, |