diff options
Diffstat (limited to '')
19 files changed, 578 insertions, 108 deletions
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml index 5073e569a47f..006d33a9e0f1 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml @@ -33,6 +33,7 @@ properties: enum: - samsung,exynos7885-cmu-top - samsung,exynos7885-cmu-core + - samsung,exynos7885-cmu-fsys - samsung,exynos7885-cmu-peri clocks: @@ -92,6 +93,32 @@ allOf: properties: compatible: contains: + const: samsung,exynos7885-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS bus clock (from CMU_TOP) + - description: MMC_CARD clock (from CMU_TOP) + - description: MMC_EMBD clock (from CMU_TOP) + - description: MMC_SDIO clock (from CMU_TOP) + - description: USB30DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_fsys_bus + - const: dout_fsys_mmc_card + - const: dout_fsys_mmc_embd + - const: dout_fsys_mmc_sdio + - const: dout_fsys_usb30drd + + - if: + properties: + compatible: + contains: const: samsung,exynos7885-cmu-peri then: diff --git a/arch/arm64/boot/dts/exynos/exynos-pinctrl.h b/arch/arm64/boot/dts/exynos/exynos-pinctrl.h new file mode 100644 index 000000000000..7dd94a9b3652 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos-pinctrl.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ +#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850 + * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1) + */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5433 */ +#define EXYNOS5433_PIN_DRV_FAST_SR1 0 +#define EXYNOS5433_PIN_DRV_FAST_SR2 1 +#define EXYNOS5433_PIN_DRV_FAST_SR3 2 +#define EXYNOS5433_PIN_DRV_FAST_SR4 3 +#define EXYNOS5433_PIN_DRV_FAST_SR5 4 +#define EXYNOS5433_PIN_DRV_FAST_SR6 5 +#define EXYNOS5433_PIN_DRV_SLOW_SR1 8 +#define EXYNOS5433_PIN_DRV_SLOW_SR2 9 +#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa +#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb +#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc +#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf + +/* Drive strengths for Exynos7 (except FSYS1) */ +#define EXYNOS7_PIN_DRV_LV1 0 +#define EXYNOS7_PIN_DRV_LV2 2 +#define EXYNOS7_PIN_DRV_LV3 1 +#define EXYNOS7_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos7 FSYS1 block */ +#define EXYNOS7_FSYS1_PIN_DRV_LV1 0 +#define EXYNOS7_FSYS1_PIN_DRV_LV2 4 +#define EXYNOS7_FSYS1_PIN_DRV_LV3 2 +#define EXYNOS7_FSYS1_PIN_DRV_LV4 6 +#define EXYNOS7_FSYS1_PIN_DRV_LV5 1 +#define EXYNOS7_FSYS1_PIN_DRV_LV6 5 + +/* Drive strengths for Exynos850 GPIO_HSI block */ +#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ +#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ +#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ +#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_6 6 +#define EXYNOS_PIN_FUNC_EINT 0xf +#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT + +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */ diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 4b46af3e164d..681553577ebc 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -9,7 +9,7 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" #define PIN(_pin, _func, _pull, _drv) \ pin- ## _pin { \ diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 75b548e495a0..bd6a354b9cb5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1820,7 +1820,7 @@ }; }; - mshc_0: mshc@15540000 { + mshc_0: mmc@15540000 { compatible = "samsung,exynos7-dw-mshc-smu"; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; @@ -1833,7 +1833,7 @@ status = "disabled"; }; - mshc_1: mshc@15550000 { + mshc_1: mmc@15550000 { compatible = "samsung,exynos7-dw-mshc-smu"; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; @@ -1846,7 +1846,7 @@ status = "disabled"; }; - mshc_2: mshc@15560000 { + mshc_2: mmc@15560000 { compatible = "samsung,exynos7-dw-mshc-smu"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 0895e818d3c1..e38c59cf18dc 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -357,7 +357,7 @@ pmic_irq: pmic-irq-pins { samsung,pins = "gpa0-2"; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; }; @@ -397,14 +397,14 @@ samsung,pins = "gph1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; usb3drd_boost_en: usb3drd-boost-en-pins { samsung,pins = "gpf4-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi index be9b971f3697..ee9c24a226f3 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi @@ -9,7 +9,7 @@ * device tree nodes in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_alive { gpa0: gpa0-gpio-bank { @@ -188,161 +188,161 @@ samsung,pins = "gpb0-1", "gpb0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c11_bus: hs-i2c11-bus-pins { samsung,pins = "gpb0-3", "gpb0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpd0-3", "gpd0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart0_data: uart0-data-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart2_data: uart2-data-pins { samsung,pins = "gpd1-4", "gpd1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpd1-3", "gpd1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart1_data: uart1-data-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpd2-1", "gpd2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpd2-3", "gpd2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c9_bus: hs-i2c9-bus-pins { samsung,pins = "gpd2-7", "gpd2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; pwm0_out: pwm0-out-pins { samsung,pins = "gpd2-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; pwm1_out: pwm1-out-pins { samsung,pins = "gpd2-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; pwm2_out: pwm2-out-pins { samsung,pins = "gpd2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; pwm3_out: pwm3-out-pins { samsung,pins = "gpd2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c8_bus: hs-i2c8-bus-pins { samsung,pins = "gpd5-3", "gpd5-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart3_data: uart3-data-pins { samsung,pins = "gpd5-0", "gpd5-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; spi2_bus: spi2-bus-pins { samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; spi1_bus: spi1-bus-pins { samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpg3-1", "gpg3-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpg3-3", "gpg3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -359,7 +359,7 @@ samsung,pins = "gpj0-1", "gpj0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -376,7 +376,7 @@ samsung,pins = "gpj1-1", "gpj1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -393,7 +393,7 @@ samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -410,7 +410,7 @@ samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -427,35 +427,35 @@ samsung,pins = "gpr4-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd-pins { samsung,pins = "gpr4-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; sd2_cd: sd2-cd-pins { samsung,pins = "gpr4-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpr4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; }; @@ -683,20 +683,20 @@ samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; ufs_refclk_out: ufs-refclk-out-pins { samsung,pins = "gpg2-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV2>; }; ufs_rst_n: ufs-rst-n-pins { samsung,pins = "gph1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts index 4cf9aa25f618..5db9a81ac7bb 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts @@ -60,6 +60,26 @@ }; }; +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs + &sd0_bus1 &sd0_bus4 &sd0_bus8>; +}; + &oscclk { clock-frequency = <26000000>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi index a50c1dbd5545..34bb12191955 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi @@ -9,8 +9,8 @@ * device tree nodes in this file. */ -#include <dt-bindings/pinctrl/samsung.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include "exynos-pinctrl.h" &pinctrl_alive { etc0: etc0-gpio-bank { diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 9c233c56558c..23c2e0bb0a2c 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -240,6 +240,25 @@ clock-names = "oscclk"; }; + cmu_fsys: clock-controller@13400000 { + compatible = "samsung,exynos7885-cmu-fsys"; + reg = <0x13400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_FSYS_BUS>, + <&cmu_top CLK_DOUT_FSYS_MMC_CARD>, + <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>, + <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>, + <&cmu_top CLK_DOUT_FSYS_USB30DRD>; + clock-names = "oscclk", + "dout_fsys_bus", + "dout_fsys_mmc_card", + "dout_fsys_mmc_embd", + "dout_fsys_mmc_sdio", + "dout_fsys_usb30drd"; + }; + pinctrl_alive: pinctrl@11cb0000 { compatible = "samsung,exynos7885-pinctrl"; reg = <0x11cb0000 0x1000>; @@ -274,6 +293,19 @@ reg = <0x11c80000 0x10000>; }; + mmc_0: mmc@13500000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + reg = <0x13500000 0x2000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>, + <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + serial_0: serial@13800000 { compatible = "samsung,exynos5433-uart"; reg = <0x13800000 0x100>; diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi index f43e4a206282..424bc80bde68 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -10,7 +10,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_alive { gpa0: gpa0-gpio-bank { diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi index ef0349d1c3d0..2a616d23c09f 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi @@ -8,7 +8,7 @@ * device tree nodes in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_alive { gpa0: gpa0-gpio-bank { diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts index 17e568853eb6..2b30a7458297 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts @@ -39,6 +39,14 @@ regulator-boot-on; enable-active-high; }; + + ufs_1_fixed_vcc_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "ufs-vcc"; + gpio = <&gpg2 2 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; }; &serial_0 { @@ -49,12 +57,22 @@ status = "okay"; }; +&ufs_1_phy { + status = "okay"; +}; + &ufs_0 { status = "okay"; vcc-supply = <&ufs_0_fixed_vcc_reg>; vcc-fixed-regulator; }; +&ufs_1 { + status = "okay"; + vcc-supply = <&ufs_1_fixed_vcc_reg>; + vcc-fixed-regulator; +}; + &usi_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 0ce46ec5cdc3..00411d4c9c5a 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/samsung,exynosautov9.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/samsung,boot-mode.h> #include <dt-bindings/soc/samsung,exynos-usi.h> / { @@ -312,6 +313,22 @@ pmu_system_controller: system-controller@10460000 { compatible = "samsung,exynos7-pmu", "syscon"; reg = <0x10460000 0x10000>; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ + value = <0x2>; + mask = <0x2>; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x810>; /* SYSIP_DAT0 */ + mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>; + mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>; + mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>; + }; }; syscon_fsys2: syscon@17c20000 { @@ -352,7 +369,7 @@ }; }; - ufs_0_phy: ufs0-phy@17e04000 { + ufs_0_phy: phy@17e04000 { compatible = "samsung,exynosautov9-ufs-phy"; reg = <0x17e04000 0xc00>; reg-names = "phy-pma"; @@ -363,13 +380,13 @@ status = "disabled"; }; - ufs_0: ufs0@17e00000 { - compatible ="samsung,exynosautov9-ufs"; + ufs_0: ufs@17e00000 { + compatible = "samsung,exynosautov9-ufs"; - reg = <0x17e00000 0x100>, /* 0: HCI standard */ - <0x17e01100 0x410>, /* 1: Vendor-specific */ - <0x17e80000 0x8000>, /* 2: UNIPRO */ - <0x17dc0000 0x2200>; /* 3: UFS protector */ + reg = <0x17e00000 0x100>, + <0x17e01100 0x410>, + <0x17e80000 0x8000>, + <0x17dc0000 0x2200>; reg-names = "hci", "vs_hci", "unipro", "ufsp"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, @@ -383,6 +400,58 @@ samsung,sysreg = <&syscon_fsys2 0x710>; status = "disabled"; }; + + ufs_1_phy: phy@17f04000 { + compatible = "samsung,exynosautov9-ufs-phy"; + reg = <0x17f04000 0xc00>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller 0x72c>; + #phy-cells = <0>; + clocks = <&xtcxo>; + clock-names = "ref_clk"; + status = "disabled"; + }; + + ufs_1: ufs@17f00000 { + compatible = "samsung,exynosautov9-ufs"; + + reg = <0x17f00000 0x100>, + <0x17f01100 0x410>, + <0x17f80000 0x8000>, + <0x17de0000 0x2200>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>, + <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>; + clock-names = "core_clk", "sclk_unipro_main"; + freq-table-hz = <0 0>, <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>; + phys = <&ufs_1_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&syscon_fsys2 0x714>; + status = "disabled"; + }; + + watchdog_cl0: watchdog@10050000 { + compatible = "samsung,exynosautov9-wdt"; + reg = <0x10050000 0x100>; + interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + }; + + watchdog_cl1: watchdog@10060000 { + compatible = "samsung,exynosautov9-wdt"; + reg = <0x10060000 0x100>; + interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <1>; + }; }; }; diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 5af560c1b5e6..1db6ddf03f01 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -37,3 +37,7 @@ &serial_0 { status = "okay"; }; + +&ufs { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi index d4d0cb005712..d0abb9aa0e9e 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -8,7 +8,7 @@ * https://www.tesla.com */ -#include <dt-bindings/pinctrl/samsung.h> +#include "fsd-pinctrl.h" &pinctrl_fsys0 { gpf0: gpf0-gpio-bank { @@ -50,6 +50,20 @@ interrupt-controller; #interrupt-cells = <2>; }; + + ufs_rst_n: ufs-rst-n-pins { + samsung,pins = "gpf5-0"; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-drv = <FSD_PIN_DRV_LV2>; + }; + + ufs_refclk_out: ufs-refclk-out-pins { + samsung,pins = "gpf5-1"; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-drv = <FSD_PIN_DRV_LV2>; + }; }; &pinctrl_peric { @@ -223,107 +237,107 @@ pwm0_out: pwm0-out-pins { samsung,pins = "gpb6-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV2>; }; pwm1_out: pwm1-out-pins { samsung,pins = "gpb6-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV2>; }; hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpb0-0", "gpb0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpb0-2", "gpb0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpb0-4", "gpb0-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpb0-6", "gpb0-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpb1-2", "gpb1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c6_bus: hs-i2c6-bus-pins { samsung,pins = "gpb1-4", "gpb1-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c7_bus: hs-i2c7-bus-pins { samsung,pins = "gpb1-6", "gpb1-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; uart0_data: uart0-data-pins { samsung,pins = "gpb7-0", "gpb7-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; uart1_data: uart1-data-pins { samsung,pins = "gpb7-4", "gpb7-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; spi1_bus: spi1-bus-pins { samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; spi2_bus: spi2-bus-pins { samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; }; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h new file mode 100644 index 000000000000..6ffbda362493 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Tesla FSD DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM64_TESLA_FSD_PINCTRL_H__ +#define __DTS_ARM64_TESLA_FSD_PINCTRL_H__ + +#define FSD_PIN_PULL_NONE 0 +#define FSD_PIN_PULL_DOWN 1 +#define FSD_PIN_PULL_UP 3 + +#define FSD_PIN_DRV_LV1 0 +#define FSD_PIN_DRV_LV2 2 +#define FSD_PIN_DRV_LV3 1 +#define FSD_PIN_DRV_LV4 3 + +#define FSD_PIN_FUNC_INPUT 0 +#define FSD_PIN_FUNC_OUTPUT 1 +#define FSD_PIN_FUNC_2 2 +#define FSD_PIN_FUNC_3 3 +#define FSD_PIN_FUNC_4 4 +#define FSD_PIN_FUNC_5 5 +#define FSD_PIN_FUNC_6 6 +#define FSD_PIN_FUNC_EINT 0xf +#define FSD_PIN_FUNC_F FSD_PIN_FUNC_EINT + +#endif /* __DTS_ARM64_TESLA_FSD_PINCTRL_H__ */ diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index af39655331de..f35bc5a288c2 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -93,6 +93,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl0_1: cpu@1 { @@ -102,6 +109,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl0_2: cpu@2 { @@ -111,6 +125,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl0_3: cpu@3 { @@ -119,6 +140,13 @@ reg = <0x0 0x003>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; /* Cluster 1 */ @@ -129,6 +157,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl1_1: cpu@101 { @@ -138,6 +173,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl1_2: cpu@102 { @@ -147,6 +189,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl1_3: cpu@103 { @@ -156,6 +205,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; /* Cluster 2 */ @@ -166,6 +222,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl2_1: cpu@201 { @@ -175,6 +238,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl2_2: cpu@202 { @@ -184,6 +254,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl2_3: cpu@203 { @@ -193,6 +270,20 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; + }; + + cpucl_l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x400000>; + cache-line-size = <64>; + cache-sets = <4096>; }; idle-states { @@ -740,6 +831,35 @@ clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; clock-names = "fin_pll", "mct"; }; + + ufs: ufs@15120000 { + compatible = "tesla,fsd-ufs"; + reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ + <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */ + <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */ + <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */ + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>, + <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>; + clock-names = "core_clk", "sclk_unipro_main"; + freq-table-hz = <0 0>, <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + phys = <&ufs_phy>; + phy-names = "ufs-phy"; + status = "disabled"; + }; + + ufs_phy: ufs-phy@15124000 { + compatible = "tesla,fsd-ufs-phy"; + reg = <0x0 0x15124000 0x0 0x800>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; + clock-names = "ref_clk"; + }; }; }; diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index 1f8701691d62..8256e7430b63 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -54,17 +54,39 @@ #define CLK_GOUT_PERI_USI0 43 #define CLK_GOUT_PERI_USI1 44 #define CLK_GOUT_PERI_USI2 45 -#define TOP_NR_CLK 46 +#define CLK_MOUT_FSYS_BUS 46 +#define CLK_MOUT_FSYS_MMC_CARD 47 +#define CLK_MOUT_FSYS_MMC_EMBD 48 +#define CLK_MOUT_FSYS_MMC_SDIO 49 +#define CLK_MOUT_FSYS_USB30DRD 50 +#define CLK_DOUT_FSYS_BUS 51 +#define CLK_DOUT_FSYS_MMC_CARD 52 +#define CLK_DOUT_FSYS_MMC_EMBD 53 +#define CLK_DOUT_FSYS_MMC_SDIO 54 +#define CLK_DOUT_FSYS_USB30DRD 55 +#define CLK_GOUT_FSYS_BUS 56 +#define CLK_GOUT_FSYS_MMC_CARD 57 +#define CLK_GOUT_FSYS_MMC_EMBD 58 +#define CLK_GOUT_FSYS_MMC_SDIO 59 +#define CLK_GOUT_FSYS_USB30DRD 60 +#define TOP_NR_CLK 61 /* CMU_CORE */ -#define CLK_MOUT_CORE_BUS_USER 1 -#define CLK_MOUT_CORE_CCI_USER 2 -#define CLK_MOUT_CORE_G3D_USER 3 -#define CLK_MOUT_CORE_GIC 4 -#define CLK_DOUT_CORE_BUSP 5 -#define CLK_GOUT_CCI_ACLK 6 -#define CLK_GOUT_GIC400_CLK 7 -#define CORE_NR_CLK 8 +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_MOUT_CORE_CCI_USER 2 +#define CLK_MOUT_CORE_G3D_USER 3 +#define CLK_MOUT_CORE_GIC 4 +#define CLK_DOUT_CORE_BUSP 5 +#define CLK_GOUT_CCI_ACLK 6 +#define CLK_GOUT_GIC400_CLK 7 +#define CLK_GOUT_TREX_D_CORE_ACLK 8 +#define CLK_GOUT_TREX_D_CORE_GCLK 9 +#define CLK_GOUT_TREX_D_CORE_PCLK 10 +#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11 +#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12 +#define CLK_GOUT_TREX_P_CORE_PCLK 13 +#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14 +#define CORE_NR_CLK 15 /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 @@ -112,4 +134,18 @@ #define CLK_GOUT_WDT1_PCLK 43 #define PERI_NR_CLK 44 +/* CMU_FSYS */ +#define CLK_MOUT_FSYS_BUS_USER 1 +#define CLK_MOUT_FSYS_MMC_CARD_USER 2 +#define CLK_MOUT_FSYS_MMC_EMBD_USER 3 +#define CLK_MOUT_FSYS_MMC_SDIO_USER 4 +#define CLK_MOUT_FSYS_USB30DRD_USER 4 +#define CLK_GOUT_MMC_CARD_ACLK 5 +#define CLK_GOUT_MMC_CARD_SDCLKIN 6 +#define CLK_GOUT_MMC_EMBD_ACLK 7 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 8 +#define CLK_GOUT_MMC_SDIO_ACLK 9 +#define CLK_GOUT_MMC_SDIO_SDCLKIN 10 +#define FSYS_NR_CLK 11 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ diff --git a/include/dt-bindings/soc/samsung,boot-mode.h b/include/dt-bindings/soc/samsung,boot-mode.h new file mode 100644 index 000000000000..47ef1cdd3916 --- /dev/null +++ b/include/dt-bindings/soc/samsung,boot-mode.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Samsung Electronics Co., Ltd. + * Author: Chanho Park <chanho61.park@samsung.com> + * + * Device Tree bindings for Samsung Boot Mode. + */ + +#ifndef __DT_BINDINGS_SAMSUNG_BOOT_MODE_H +#define __DT_BINDINGS_SAMSUNG_BOOT_MODE_H + +/* Boot mode definitions for Exynos Auto v9 SoC */ + +#define EXYNOSAUTOV9_BOOT_FASTBOOT 0xfa +#define EXYNOSAUTOV9_BOOT_BOOTLOADER 0xfc +#define EXYNOSAUTOV9_BOOT_RECOVERY 0xff + +#endif /* __DT_BINDINGS_SAMSUNG_BOOT_MODE_H */ |