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-rw-r--r--drivers/gpu/drm/arm/malidp_crtc.c20
-rw-r--r--drivers/gpu/drm/arm/malidp_drv.c51
-rw-r--r--drivers/gpu/drm/arm/malidp_drv.h2
-rw-r--r--drivers/gpu/drm/arm/malidp_hw.c26
-rw-r--r--drivers/gpu/drm/arm/malidp_hw.h15
-rw-r--r--drivers/gpu/drm/arm/malidp_planes.c141
-rw-r--r--drivers/gpu/drm/arm/malidp_regs.h11
7 files changed, 189 insertions, 77 deletions
diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c
index 904fff80917b..fcc62bc60f6a 100644
--- a/drivers/gpu/drm/arm/malidp_crtc.c
+++ b/drivers/gpu/drm/arm/malidp_crtc.c
@@ -288,8 +288,14 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc,
s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||
(v_upscale_factor >> 16) >= 2);
- s->input_w = pstate->src_w >> 16;
- s->input_h = pstate->src_h >> 16;
+ if (pstate->rotation & MALIDP_ROTATED_MASK) {
+ s->input_w = pstate->src_h >> 16;
+ s->input_h = pstate->src_w >> 16;
+ } else {
+ s->input_w = pstate->src_w >> 16;
+ s->input_h = pstate->src_h >> 16;
+ }
+
s->output_w = pstate->crtc_w;
s->output_h = pstate->crtc_h;
@@ -525,14 +531,13 @@ int malidp_crtc_init(struct drm_device *drm)
if (!primary) {
DRM_ERROR("no primary plane found\n");
- ret = -EINVAL;
- goto crtc_cleanup_planes;
+ return -EINVAL;
}
ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,
&malidp_crtc_funcs, NULL);
if (ret)
- goto crtc_cleanup_planes;
+ return ret;
drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);
@@ -542,9 +547,4 @@ int malidp_crtc_init(struct drm_device *drm)
malidp_se_set_enh_coeffs(malidp->dev);
return 0;
-
-crtc_cleanup_planes:
- malidp_de_planes_destroy(drm);
-
- return ret;
}
diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c
index 3d82712d8002..8d20faa198cf 100644
--- a/drivers/gpu/drm/arm/malidp_drv.c
+++ b/drivers/gpu/drm/arm/malidp_drv.c
@@ -185,25 +185,29 @@ static int malidp_set_and_wait_config_valid(struct drm_device *drm)
static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
{
- struct drm_pending_vblank_event *event;
struct drm_device *drm = state->dev;
struct malidp_drm *malidp = drm->dev_private;
- if (malidp->crtc.enabled) {
- /* only set config_valid if the CRTC is enabled */
- if (malidp_set_and_wait_config_valid(drm))
- DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
- }
+ malidp->event = malidp->crtc.state->event;
+ malidp->crtc.state->event = NULL;
- event = malidp->crtc.state->event;
- if (event) {
- malidp->crtc.state->event = NULL;
+ if (malidp->crtc.state->active) {
+ /*
+ * if we have an event to deliver to userspace, make sure
+ * the vblank is enabled as we are sending it from the IRQ
+ * handler.
+ */
+ if (malidp->event)
+ drm_crtc_vblank_get(&malidp->crtc);
+ /* only set config_valid if the CRTC is enabled */
+ if (malidp_set_and_wait_config_valid(drm) < 0)
+ DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
+ } else if (malidp->event) {
+ /* CRTC inactive means vblank IRQ is disabled, send event directly */
spin_lock_irq(&drm->event_lock);
- if (drm_crtc_vblank_get(&malidp->crtc) == 0)
- drm_crtc_arm_vblank_event(&malidp->crtc, event);
- else
- drm_crtc_send_vblank_event(&malidp->crtc, event);
+ drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);
+ malidp->event = NULL;
spin_unlock_irq(&drm->event_lock);
}
drm_atomic_helper_commit_hw_done(state);
@@ -232,8 +236,6 @@ static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
malidp_atomic_commit_hw_done(state);
- drm_atomic_helper_wait_for_vblanks(drm, state);
-
pm_runtime_put(drm->dev);
drm_atomic_helper_cleanup_planes(drm, state);
@@ -276,7 +278,7 @@ static int malidp_init(struct drm_device *drm)
static void malidp_fini(struct drm_device *drm)
{
- malidp_de_planes_destroy(drm);
+ drm_atomic_helper_shutdown(drm);
drm_mode_config_cleanup(drm);
}
@@ -312,13 +314,26 @@ static int malidp_irq_init(struct platform_device *pdev)
DEFINE_DRM_GEM_CMA_FOPS(fops);
+static int malidp_dumb_create(struct drm_file *file_priv,
+ struct drm_device *drm,
+ struct drm_mode_create_dumb *args)
+{
+ struct malidp_drm *malidp = drm->dev_private;
+ /* allocate for the worst case scenario, i.e. rotated buffers */
+ u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 1);
+
+ args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), alignment);
+
+ return drm_gem_cma_dumb_create_internal(file_priv, drm, args);
+}
+
static struct drm_driver malidp_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
DRIVER_PRIME,
.lastclose = drm_fb_helper_lastclose,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
- .dumb_create = drm_gem_cma_dumb_create,
+ .dumb_create = malidp_dumb_create,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_export = drm_gem_prime_export,
@@ -662,8 +677,10 @@ static void malidp_unbind(struct device *dev)
drm_fb_cma_fbdev_fini(drm);
drm_kms_helper_poll_fini(drm);
pm_runtime_get_sync(dev);
+ drm_crtc_vblank_off(&malidp->crtc);
malidp_se_irq_fini(drm);
malidp_de_irq_fini(drm);
+ drm->irq_enabled = false;
component_unbind_all(dev, drm);
of_node_put(malidp->crtc.port);
malidp->crtc.port = NULL;
diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h
index e0d12c9fc6b8..c70989b93387 100644
--- a/drivers/gpu/drm/arm/malidp_drv.h
+++ b/drivers/gpu/drm/arm/malidp_drv.h
@@ -22,6 +22,7 @@ struct malidp_drm {
struct malidp_hw_device *dev;
struct drm_crtc crtc;
wait_queue_head_t wq;
+ struct drm_pending_vblank_event *event;
atomic_t config_valid;
u32 core_id;
};
@@ -59,7 +60,6 @@ struct malidp_crtc_state {
#define to_malidp_crtc_state(x) container_of(x, struct malidp_crtc_state, base)
int malidp_de_planes_init(struct drm_device *drm);
-void malidp_de_planes_destroy(struct drm_device *drm);
int malidp_crtc_init(struct drm_device *drm);
/* often used combination of rotational bits */
diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c
index 2bfb542135ac..d789b46dc817 100644
--- a/drivers/gpu/drm/arm/malidp_hw.c
+++ b/drivers/gpu/drm/arm/malidp_hw.c
@@ -75,16 +75,16 @@ static const struct malidp_format_id malidp550_de_formats[] = {
};
static const struct malidp_layer malidp500_layers[] = {
- { DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE, MALIDP_DE_LV_STRIDE0 },
- { DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE, MALIDP_DE_LG_STRIDE },
- { DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE, MALIDP_DE_LG_STRIDE },
+ { DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP500_LV_YUV2RGB },
+ { DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },
+ { DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },
};
static const struct malidp_layer malidp550_layers[] = {
- { DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0 },
- { DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE },
- { DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0 },
- { DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, MALIDP550_DE_LS_R1_STRIDE },
+ { DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB },
+ { DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },
+ { DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB },
+ { DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, MALIDP550_DE_LS_R1_STRIDE, 0 },
};
#define SE_N_SCALING_COEFFS 96
@@ -782,9 +782,15 @@ static irqreturn_t malidp_de_irq(int irq, void *arg)
/* first handle the config valid IRQ */
dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);
if (dc_status & hw->map.dc_irq_map.vsync_irq) {
- /* we have a page flip event */
- atomic_set(&malidp->config_valid, 1);
malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
+ /* do we have a page flip event? */
+ if (malidp->event != NULL) {
+ spin_lock(&drm->event_lock);
+ drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);
+ malidp->event = NULL;
+ spin_unlock(&drm->event_lock);
+ }
+ atomic_set(&malidp->config_valid, 1);
ret = IRQ_WAKE_THREAD;
}
@@ -794,7 +800,7 @@ static irqreturn_t malidp_de_irq(int irq, void *arg)
mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);
status &= mask;
- if (status & de->vsync_irq)
+ if ((status & de->vsync_irq) && malidp->crtc.enabled)
drm_crtc_handle_vblank(&malidp->crtc);
malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);
diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h
index b0690ebb3565..b5dd6c73ec9f 100644
--- a/drivers/gpu/drm/arm/malidp_hw.h
+++ b/drivers/gpu/drm/arm/malidp_hw.h
@@ -58,7 +58,8 @@ struct malidp_layer {
u16 id; /* layer ID */
u16 base; /* address offset for the register bank */
u16 ptr; /* address offset for the pointer register */
- u16 stride_offset; /* Offset to the first stride register. */
+ u16 stride_offset; /* offset to the first stride register. */
+ s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */
};
enum malidp_scaling_coeff_set {
@@ -285,10 +286,16 @@ void malidp_se_irq_fini(struct drm_device *drm);
u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
u8 layer_id, u32 format);
-static inline bool malidp_hw_pitch_valid(struct malidp_hw_device *hwdev,
- unsigned int pitch)
+static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated)
{
- return !(pitch & (hwdev->hw->map.bus_align_bytes - 1));
+ /*
+ * only hardware that cannot do 8 bytes bus alignments have further
+ * constraints on rotated planes
+ */
+ if (hwdev->hw->map.bus_align_bytes == 8)
+ return 8;
+ else
+ return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0);
}
/* U16.16 */
diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c
index ee32361c87ac..7a44897c50fe 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -35,6 +35,9 @@
#define LAYER_COMP_MASK (0x3 << 12)
#define LAYER_COMP_PIXEL (0x3 << 12)
#define LAYER_COMP_PLANE (0x2 << 12)
+#define LAYER_ALPHA_OFFSET (16)
+#define LAYER_ALPHA_MASK (0xff)
+#define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET)
#define MALIDP_LAYER_COMPOSE 0x008
#define MALIDP_LAYER_SIZE 0x00c
#define LAYER_H_VAL(x) (((x) & 0x1fff) << 0)
@@ -56,12 +59,8 @@ static void malidp_de_plane_destroy(struct drm_plane *plane)
{
struct malidp_plane *mp = to_malidp_plane(plane);
- if (mp->base.fb)
- drm_framebuffer_put(mp->base.fb);
-
- drm_plane_helper_disable(plane);
drm_plane_cleanup(plane);
- devm_kfree(plane->dev->dev, mp);
+ kfree(mp);
}
/*
@@ -147,13 +146,21 @@ static int malidp_se_check_scaling(struct malidp_plane *mp,
if (!crtc_state)
return -EINVAL;
+ mc = to_malidp_crtc_state(crtc_state);
+
ret = drm_atomic_helper_check_plane_state(state, crtc_state,
0, INT_MAX, true, true);
if (ret)
return ret;
- src_w = state->src_w >> 16;
- src_h = state->src_h >> 16;
+ if (state->rotation & MALIDP_ROTATED_MASK) {
+ src_w = state->src_h >> 16;
+ src_h = state->src_w >> 16;
+ } else {
+ src_w = state->src_w >> 16;
+ src_h = state->src_h >> 16;
+ }
+
if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) {
/* Scaling not necessary for this plane. */
mc->scaled_planes_mask &= ~(mp->layer->id);
@@ -163,8 +170,6 @@ static int malidp_se_check_scaling(struct malidp_plane *mp,
if (mp->layer->id & (DE_SMART | DE_GRAPHICS2))
return -EINVAL;
- mc = to_malidp_crtc_state(crtc_state);
-
mc->scaled_planes_mask |= mp->layer->id;
/* Defer scaling requirements calculation to the crtc check. */
return 0;
@@ -175,6 +180,7 @@ static int malidp_de_plane_check(struct drm_plane *plane,
{
struct malidp_plane *mp = to_malidp_plane(plane);
struct malidp_plane_state *ms = to_malidp_plane_state(state);
+ bool rotated = state->rotation & MALIDP_ROTATED_MASK;
struct drm_framebuffer *fb;
int i, ret;
@@ -191,7 +197,8 @@ static int malidp_de_plane_check(struct drm_plane *plane,
ms->n_planes = fb->format->num_planes;
for (i = 0; i < ms->n_planes; i++) {
- if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) {
+ u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated);
+ if (fb->pitches[i] & (alignment - 1)) {
DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
fb->pitches[i], i);
return -EINVAL;
@@ -259,6 +266,60 @@ static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
mp->layer->stride_offset + i * 4);
}
+static const s16
+malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = {
+ [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+ 1192, 0, 1634,
+ 1192, -401, -832,
+ 1192, 2066, 0,
+ 64, 512, 512
+ },
+ [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = {
+ 1024, 0, 1436,
+ 1024, -352, -731,
+ 1024, 1815, 0,
+ 0, 512, 512
+ },
+ [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+ 1192, 0, 1836,
+ 1192, -218, -546,
+ 1192, 2163, 0,
+ 64, 512, 512
+ },
+ [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = {
+ 1024, 0, 1613,
+ 1024, -192, -479,
+ 1024, 1900, 0,
+ 0, 512, 512
+ },
+ [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+ 1024, 0, 1476,
+ 1024, -165, -572,
+ 1024, 1884, 0,
+ 0, 512, 512
+ },
+ [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = {
+ 1024, 0, 1510,
+ 1024, -168, -585,
+ 1024, 1927, 0,
+ 0, 512, 512
+ }
+};
+
+static void malidp_de_set_color_encoding(struct malidp_plane *plane,
+ enum drm_color_encoding enc,
+ enum drm_color_range range)
+{
+ unsigned int i;
+
+ for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) {
+ /* coefficients are signed, two's complement values */
+ malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i],
+ plane->layer->base + plane->layer->yuv2rgb_offset +
+ i * 4);
+ }
+}
+
static void malidp_de_plane_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
@@ -266,6 +327,7 @@ static void malidp_de_plane_update(struct drm_plane *plane,
struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
u32 src_w, src_h, dest_w, dest_h, val;
int i;
+ bool format_has_alpha = plane->state->fb->format->has_alpha;
mp = to_malidp_plane(plane);
@@ -289,6 +351,11 @@ static void malidp_de_plane_update(struct drm_plane *plane,
malidp_de_set_plane_pitches(mp, ms->n_planes,
plane->state->fb->pitches);
+ if ((plane->state->color_encoding != old_state->color_encoding) ||
+ (plane->state->color_range != old_state->color_range))
+ malidp_de_set_color_encoding(mp, plane->state->color_encoding,
+ plane->state->color_range);
+
malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
mp->layer->base + MALIDP_LAYER_SIZE);
@@ -317,12 +384,25 @@ static void malidp_de_plane_update(struct drm_plane *plane,
if (plane->state->rotation & DRM_MODE_REFLECT_Y)
val |= LAYER_V_FLIP;
- /*
- * always enable pixel alpha blending until we have a way to change
- * blend modes
- */
val &= ~LAYER_COMP_MASK;
- val |= LAYER_COMP_PIXEL;
+ if (format_has_alpha) {
+
+ /*
+ * always enable pixel alpha blending until we have a way
+ * to change blend modes
+ */
+ val |= LAYER_COMP_PIXEL;
+ } else {
+
+ /*
+ * do not enable pixel alpha blending as the color channel
+ * does not have any alpha information
+ */
+ val |= LAYER_COMP_PLANE;
+
+ /* Set layer alpha coefficient to 0xff ie fully opaque */
+ val |= LAYER_ALPHA(0xff);
+ }
val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
if (plane->state->crtc) {
@@ -417,6 +497,26 @@ int malidp_de_planes_init(struct drm_device *drm)
drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags);
malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
plane->layer->base + MALIDP_LAYER_COMPOSE);
+
+ /* Attach the YUV->RGB property only to video layers */
+ if (id & (DE_VIDEO1 | DE_VIDEO2)) {
+ /* default encoding for YUV->RGB is BT601 NARROW */
+ enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601;
+ enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE;
+
+ ret = drm_plane_create_color_properties(&plane->base,
+ BIT(DRM_COLOR_YCBCR_BT601) | \
+ BIT(DRM_COLOR_YCBCR_BT709) | \
+ BIT(DRM_COLOR_YCBCR_BT2020),
+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \
+ BIT(DRM_COLOR_YCBCR_FULL_RANGE),
+ enc, range);
+ if (!ret)
+ /* program the HW registers */
+ malidp_de_set_color_encoding(plane, enc, range);
+ else
+ DRM_WARN("Failed to create video layer %d color properties\n", id);
+ }
}
kfree(formats);
@@ -424,18 +524,7 @@ int malidp_de_planes_init(struct drm_device *drm)
return 0;
cleanup:
- malidp_de_planes_destroy(drm);
kfree(formats);
return ret;
}
-
-void malidp_de_planes_destroy(struct drm_device *drm)
-{
- struct drm_plane *p, *pt;
-
- list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) {
- drm_plane_cleanup(p);
- kfree(p);
- }
-}
diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h
index 2039f857f77d..149024fb4432 100644
--- a/drivers/gpu/drm/arm/malidp_regs.h
+++ b/drivers/gpu/drm/arm/malidp_regs.h
@@ -170,10 +170,7 @@
#define MALIDP500_CONFIG_3D 0x00038
#define MALIDP500_BGND_COLOR 0x0003c
#define MALIDP500_OUTPUT_DEPTH 0x00044
-#define MALIDP500_YUV_RGB_COEF 0x00048
-#define MALIDP500_COLOR_ADJ_COEF 0x00078
-#define MALIDP500_COEF_TABLE_ADDR 0x000a8
-#define MALIDP500_COEF_TABLE_DATA 0x000ac
+#define MALIDP500_COEFFS_BASE 0x00078
/*
* The YUV2RGB coefficients on the DP500 are not in the video layer's register
@@ -181,11 +178,6 @@
* the negative offset.
*/
#define MALIDP500_LV_YUV2RGB ((s16)(-0xB8))
-/*
- * To match DP550/650, the start of the coeffs registers is
- * at COLORADJ_COEFF0 instead of at YUV_RGB_COEF1.
- */
-#define MALIDP500_COEFFS_BASE 0x00078
#define MALIDP500_DE_LV_BASE 0x00100
#define MALIDP500_DE_LV_PTR_BASE 0x00124
#define MALIDP500_DE_LG1_BASE 0x00200
@@ -213,6 +205,7 @@
#define MALIDP550_DE_BGND_COLOR 0x00044
#define MALIDP550_DE_OUTPUT_DEPTH 0x0004c
#define MALIDP550_COEFFS_BASE 0x00050
+#define MALIDP550_LV_YUV2RGB 0x00084
#define MALIDP550_DE_LV1_BASE 0x00100
#define MALIDP550_DE_LV1_PTR_BASE 0x00124
#define MALIDP550_DE_LV2_BASE 0x00200
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