diff options
Diffstat (limited to '')
| -rw-r--r-- | arch/blackfin/mach-bf527/head.S | 19 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf533/head.S | 18 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/head.S | 39 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/head.S | 17 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/Makefile | 2 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/cacheinit.S | 77 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-common/cdef_LPBlackfin.h | 8 |
7 files changed, 2 insertions, 178 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S index fe05cc1ef174..a16a26575280 100644 --- a/arch/blackfin/mach-bf527/head.S +++ b/arch/blackfin/mach-bf527/head.S @@ -105,17 +105,8 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; - - /* Anomaly 05000125 */ -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif /* Turn off the dcache */ p0.l = LO(DMEM_CONTROL); @@ -123,18 +114,8 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; - - /* Anomaly 05000125 */ -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif - #if defined(CONFIG_BF527) p0.h = hi(EMAC_SYSTAT); diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index c671e8549b17..fb49169c0e7b 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S @@ -116,17 +116,8 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; - - /* Anomaly 05000125 */ -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif /* Turn off the dcache */ p0.l = LO(DMEM_CONTROL); @@ -134,17 +125,8 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; - - /* Anomaly 05000125 */ -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif /* Initialise UART - when booting from u-boot, the UART is not disabled * so if we dont initalize here, our serial console gets hosed */ diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 6b019eaee0b6..5bc89bbb89d0 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -105,17 +105,8 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; - - /* Anomaly 05000125 */ -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif /* Turn off the dcache */ p0.l = LO(DMEM_CONTROL); @@ -123,48 +114,20 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; - - /* Anomaly 05000125 */ -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif /* Initialise General-Purpose I/O Modules on BF537 */ - /* Rev 0.0 Anomaly 05000212 - PORTx_FER, - * PORT_MUX Registers Do Not accept "writes" correctly: - */ p0.h = hi(BFIN_PORT_MUX); p0.l = lo(BFIN_PORT_MUX); -#if ANOMALY_05000212 - R0.L = W[P0]; /* Read */ - SSYNC; -#endif R0 = (PGDE_UART | PFTE_UART)(Z); -#if ANOMALY_05000212 - W[P0] = R0.L; /* Write */ - SSYNC; -#endif W[P0] = R0.L; /* Enable both UARTS */ SSYNC; + /* Enable peripheral function of PORTF for UART0 and UART1 */ p0.h = hi(PORTF_FER); p0.l = lo(PORTF_FER); -#if ANOMALY_05000212 - R0.L = W[P0]; /* Read */ - SSYNC; -#endif R0 = 0x000F(Z); -#if ANOMALY_05000212 - W[P0] = R0.L; /* Write */ - SSYNC; -#endif - /* Enable peripheral function of PORTF for UART0 and UART1 */ W[P0] = R0.L; SSYNC; diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index cf1a2dff01e7..0a1443b6b462 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S @@ -105,16 +105,8 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; - -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif /* Turn off the dcache */ p0.l = LO(DMEM_CONTROL); @@ -122,17 +114,8 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; - - /* Anomaly 05000125 */ -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif /* Initialise UART - when booting from u-boot, the UART is not disabled * so if we dont initalize here, our serial console gets hosed */ diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index 422bfee34adc..5e6b20e423d6 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile @@ -3,7 +3,7 @@ # obj-y := \ - cache.o cacheinit.o entry.o \ + cache.o entry.o \ interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o obj-$(CONFIG_PM) += pm.o dpmc_modes.o diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S deleted file mode 100644 index 22fada0c1cb3..000000000000 --- a/arch/blackfin/mach-common/cacheinit.S +++ /dev/null @@ -1,77 +0,0 @@ -/* - * File: arch/blackfin/mach-common/cacheinit.S - * Based on: - * Author: LG Soft India - * - * Created: ? - * Description: cache initialization - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This function sets up the data and instruction cache. The - * tables like icplb table, dcplb table and Page Descriptor table - * are defined in cplbtab.h. You can configure those tables for - * your suitable requirements - */ - -#include <linux/linkage.h> -#include <asm/blackfin.h> - -.text - -#if ANOMALY_05000125 -#if defined(CONFIG_BFIN_ICACHE) -ENTRY(_bfin_write_IMEM_CONTROL) - - /* Enable Instruction Cache */ - P0.l = LO(IMEM_CONTROL); - P0.h = HI(IMEM_CONTROL); - - /* Anomaly 05000125 */ - CLI R1; - SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ - .align 8; - [P0] = R0; - SSYNC; - STI R1; - RTS; - -ENDPROC(_bfin_write_IMEM_CONTROL) -#endif - -#if defined(CONFIG_BFIN_DCACHE) -ENTRY(_bfin_write_DMEM_CONTROL) - P0.l = LO(DMEM_CONTROL); - P0.h = HI(DMEM_CONTROL); - - CLI R1; - SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ - .align 8; - [P0] = R0; - SSYNC; - STI R1; - RTS; - -ENDPROC(_bfin_write_DMEM_CONTROL) -#endif - -#endif diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h index ede210eca4ec..d39c396f850d 100644 --- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h @@ -39,11 +39,7 @@ #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#if ANOMALY_05000125 -extern void bfin_write_DMEM_CONTROL(unsigned int val); -#else #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) -#endif #define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) #define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) @@ -129,11 +125,7 @@ extern void bfin_write_DMEM_CONTROL(unsigned int val); #define DTEST_DATA3 0xFFE0040C */ #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#if ANOMALY_05000125 -extern void bfin_write_IMEM_CONTROL(unsigned int val); -#else #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) -#endif #define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) #define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val) #define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) |