diff options
40 files changed, 1580 insertions, 1651 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 233a222752c0..3bf3d48ddbf0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -308,10 +308,9 @@ config ARCH_MXC bool "Freescale MXC/iMX-based" select GENERIC_TIME select GENERIC_CLOCKEVENTS - select ARCH_MTD_XIP - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB select HAVE_CLK + select COMMON_CLKDEV help Support for Freescale MXC/iMX-based family of processors diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c index 69831aa274ff..51f3cfd83db2 100644 --- a/arch/arm/mach-mx1/mach-mx1ads.c +++ b/arch/arm/mach-mx1/mach-mx1ads.c @@ -27,7 +27,7 @@ #include <mach/hardware.h> #include <mach/i2c.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx1.h> #include <mach/irqs.h> #include "devices.h" diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c index b9530d76e99d..7587a7a12460 100644 --- a/arch/arm/mach-mx1/mach-scb9328.c +++ b/arch/arm/mach-mx1/mach-scb9328.c @@ -23,7 +23,7 @@ #include <mach/hardware.h> #include <mach/irqs.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx1.h> #include "devices.h" diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index e8910903b24f..e3254faac828 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -4,14 +4,12 @@ # Object file lists. -obj-y := generic.o devices.o serial.o -CFLAGS_generic.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +obj-y := devices.o serial.o -obj-$(CONFIG_MACH_MX21) += clock_imx21.o +obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o obj-$(CONFIG_MACH_MX27) += cpu_imx27.o -obj-$(CONFIG_MACH_MX27) += clock_imx27.o +obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 3d398ce09b31..a4b809b82fa3 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -46,65 +46,31 @@ * - i.MX21: 2 channel * - i.MX27: 3 channel */ -static struct resource mxc_spi_resources0[] = { - { - .start = CSPI1_BASE_ADDR, - .end = CSPI1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI1, - .end = MXC_INT_CSPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxc_spi_resources1[] = { - { - .start = CSPI2_BASE_ADDR, - .end = CSPI2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI2, - .end = MXC_INT_CSPI2, - .flags = IORESOURCE_IRQ, - }, -}; - -#ifdef CONFIG_MACH_MX27 -static struct resource mxc_spi_resources2[] = { - { - .start = CSPI3_BASE_ADDR, - .end = CSPI3_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI3, - .end = MXC_INT_CSPI3, - .flags = IORESOURCE_IRQ, - }, -}; -#endif - -struct platform_device mxc_spi_device0 = { - .name = "spi_imx", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_spi_resources0), - .resource = mxc_spi_resources0, -}; +#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_spi_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device mxc_spi_device ## n = { \ + .name = "spi_imx", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ + .resource = mxc_spi_resources ## n, \ + } -struct platform_device mxc_spi_device1 = { - .name = "spi_imx", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_spi_resources1), - .resource = mxc_spi_resources1, -}; +DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); +DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2); #ifdef CONFIG_MACH_MX27 -struct platform_device mxc_spi_device2 = { - .name = "spi_imx", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_spi_resources2), - .resource = mxc_spi_resources2, -}; +DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); #endif /* @@ -112,104 +78,34 @@ struct platform_device mxc_spi_device2 = { * - i.MX21: 3 timers * - i.MX27: 6 timers */ - -/* We use gpt0 as system timer, so do not add a device for this one */ - -static struct resource timer1_resources[] = { - { - .start = GPT2_BASE_ADDR, - .end = GPT2_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT2, - .end = MXC_INT_GPT2, - .flags = IORESOURCE_IRQ, +#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \ + static struct resource timer ## n ##_resources[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + } \ + }; \ + \ + struct platform_device mxc_gpt ## n = { \ + .name = "imx_gpt", \ + .id = n, \ + .num_resources = ARRAY_SIZE(timer ## n ## _resources), \ + .resource = timer ## n ## _resources, \ } -}; - -struct platform_device mxc_gpt1 = { - .name = "imx_gpt", - .id = 1, - .num_resources = ARRAY_SIZE(timer1_resources), - .resource = timer1_resources, -}; -static struct resource timer2_resources[] = { - { - .start = GPT3_BASE_ADDR, - .end = GPT3_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT3, - .end = MXC_INT_GPT3, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt2 = { - .name = "imx_gpt", - .id = 2, - .num_resources = ARRAY_SIZE(timer2_resources), - .resource = timer2_resources, -}; +/* We use gpt1 as system timer, so do not add a device for this one */ +DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2); +DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3); #ifdef CONFIG_MACH_MX27 -static struct resource timer3_resources[] = { - { - .start = GPT4_BASE_ADDR, - .end = GPT4_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT4, - .end = MXC_INT_GPT4, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt3 = { - .name = "imx_gpt", - .id = 3, - .num_resources = ARRAY_SIZE(timer3_resources), - .resource = timer3_resources, -}; - -static struct resource timer4_resources[] = { - { - .start = GPT5_BASE_ADDR, - .end = GPT5_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT5, - .end = MXC_INT_GPT5, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt4 = { - .name = "imx_gpt", - .id = 4, - .num_resources = ARRAY_SIZE(timer4_resources), - .resource = timer4_resources, -}; - -static struct resource timer5_resources[] = { - { - .start = GPT6_BASE_ADDR, - .end = GPT6_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT6, - .end = MXC_INT_GPT6, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt5 = { - .name = "imx_gpt", - .id = 5, - .num_resources = ARRAY_SIZE(timer5_resources), - .resource = timer5_resources, -}; +DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4); +DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); +DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); #endif /* @@ -220,9 +116,9 @@ struct platform_device mxc_gpt5 = { */ static struct resource mxc_wdt_resources[] = { { - .start = WDOG_BASE_ADDR, - .end = WDOG_BASE_ADDR + 0x30, - .flags = IORESOURCE_MEM, + .start = MX2x_WDOG_BASE_ADDR, + .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, }; @@ -235,8 +131,8 @@ struct platform_device mxc_wdt = { static struct resource mxc_w1_master_resources[] = { { - .start = OWIRE_BASE_ADDR, - .end = OWIRE_BASE_ADDR + SZ_4K - 1, + .start = MX2x_OWIRE_BASE_ADDR, + .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -248,24 +144,33 @@ struct platform_device mxc_w1_master_device = { .resource = mxc_w1_master_resources, }; -static struct resource mxc_nand_resources[] = { - { - .start = NFC_BASE_ADDR, - .end = NFC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_NANDFC, - .end = MXC_INT_NANDFC, - .flags = IORESOURCE_IRQ, - }, -}; +#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \ + static struct resource pfx ## _nand_resources[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device pfx ## _nand_device = { \ + .name = "mxc_nand", \ + .id = 0, \ + .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \ + .resource = pfx ## _nand_resources, \ + } -struct platform_device mxc_nand_device = { - .name = "mxc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_nand_resources), - .resource = mxc_nand_resources, -}; +#ifdef CONFIG_MACH_MX21 +DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC); +#endif + +#ifdef CONFIG_MACH_MX27 +DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC); +#endif /* * lcdc: @@ -275,12 +180,12 @@ struct platform_device mxc_nand_device = { */ static struct resource mxc_fb[] = { { - .start = LCDC_BASE_ADDR, - .end = LCDC_BASE_ADDR + 0xFFF, + .start = MX2x_LCDC_BASE_ADDR, + .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_LCDC, - .end = MXC_INT_LCDC, + .start = MX2x_INT_LCDC, + .end = MX2x_INT_LCDC, .flags = IORESOURCE_IRQ, } }; @@ -299,13 +204,13 @@ struct platform_device mxc_fb_device = { #ifdef CONFIG_MACH_MX27 static struct resource mxc_fec_resources[] = { { - .start = FEC_BASE_ADDR, - .end = FEC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, + .start = MX27_FEC_BASE_ADDR, + .end = MX27_FEC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_FEC, - .end = MXC_INT_FEC, - .flags = IORESOURCE_IRQ, + .start = MX27_INT_FEC, + .end = MX27_INT_FEC, + .flags = IORESOURCE_IRQ, }, }; @@ -317,55 +222,41 @@ struct platform_device mxc_fec_device = { }; #endif -static struct resource mxc_i2c_1_resources[] = { - { - .start = I2C_BASE_ADDR, - .end = I2C_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C, - .end = MXC_INT_I2C, - .flags = IORESOURCE_IRQ, +#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_i2c_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + } \ + }; \ + \ + struct platform_device mxc_i2c_device ## n = { \ + .name = "imx-i2c", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \ + .resource = mxc_i2c_resources ## n, \ } -}; -struct platform_device mxc_i2c_device0 = { - .name = "imx-i2c", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), - .resource = mxc_i2c_1_resources, -}; +DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C); #ifdef CONFIG_MACH_MX27 -static struct resource mxc_i2c_2_resources[] = { - { - .start = I2C2_BASE_ADDR, - .end = I2C2_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C2, - .end = MXC_INT_I2C2, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device1 = { - .name = "imx-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), - .resource = mxc_i2c_2_resources, -}; +DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); #endif static struct resource mxc_pwm_resources[] = { { - .start = PWM_BASE_ADDR, - .end = PWM_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, + .start = MX2x_PWM_BASE_ADDR, + .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_PWM, - .end = MXC_INT_PWM, - .flags = IORESOURCE_IRQ, + .start = MX2x_INT_PWM, + .end = MX2x_INT_PWM, + .flags = IORESOURCE_IRQ, } }; @@ -379,74 +270,49 @@ struct platform_device mxc_pwm_device = { /* * Resource definition for the MXC SDHC */ -static struct resource mxc_sdhc1_resources[] = { - { - .start = SDHC1_BASE_ADDR, - .end = SDHC1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SDHC1, - .end = MXC_INT_SDHC1, - .flags = IORESOURCE_IRQ, - }, { - .start = DMA_REQ_SDHC1, - .end = DMA_REQ_SDHC1, - .flags = IORESOURCE_DMA, - }, -}; - -static u64 mxc_sdhc1_dmamask = 0xffffffffUL; - -struct platform_device mxc_sdhc_device0 = { - .name = "mxc-mmc", - .id = 0, - .dev = { - .dma_mask = &mxc_sdhc1_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), - .resource = mxc_sdhc1_resources, -}; - -static struct resource mxc_sdhc2_resources[] = { - { - .start = SDHC2_BASE_ADDR, - .end = SDHC2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SDHC2, - .end = MXC_INT_SDHC2, - .flags = IORESOURCE_IRQ, - }, { - .start = DMA_REQ_SDHC2, - .end = DMA_REQ_SDHC2, - .flags = IORESOURCE_DMA, - }, -}; +#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \ + static struct resource mxc_sdhc_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, { \ + .start = dmareq, \ + .end = dmareq, \ + .flags = IORESOURCE_DMA, \ + }, \ + }; \ + \ + static u64 mxc_sdhc ## n ## _dmamask = 0xffffffffUL; \ + \ + struct platform_device mxc_sdhc_device ## n = { \ + .name = "mxc-mmc", \ + .id = n, \ + .dev = { \ + .dma_mask = &mxc_sdhc ## n ## _dmamask, \ + .coherent_dma_mask = 0xffffffff, \ + }, \ + .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \ + .resource = mxc_sdhc_resources ## n, \ + } -static u64 mxc_sdhc2_dmamask = 0xffffffffUL; - -struct platform_device mxc_sdhc_device1 = { - .name = "mxc-mmc", - .id = 1, - .dev = { - .dma_mask = &mxc_sdhc2_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mxc_sdhc2_resources), - .resource = mxc_sdhc2_resources, -}; +DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1); +DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2); #ifdef CONFIG_MACH_MX27 static struct resource otg_resources[] = { { - .start = OTG_BASE_ADDR, - .end = OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, + .start = MX27_USBOTG_BASE_ADDR, + .end = MX27_USBOTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB3, - .end = MXC_INT_USB3, - .flags = IORESOURCE_IRQ, + .start = MX27_INT_USB3, + .end = MX27_INT_USB3, + .flags = IORESOURCE_IRQ, }, }; @@ -454,14 +320,14 @@ static u64 otg_dmamask = 0xffffffffUL; /* OTG gadget device */ struct platform_device mxc_otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = 0xffffffffUL, + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .dma_mask = &otg_dmamask, + .coherent_dma_mask = 0xffffffffUL, }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), }; /* OTG host */ @@ -482,12 +348,12 @@ static u64 usbh1_dmamask = 0xffffffffUL; static struct resource mxc_usbh1_resources[] = { { - .start = OTG_BASE_ADDR + 0x200, - .end = OTG_BASE_ADDR + 0x3ff, + .start = MX27_USBOTG_BASE_ADDR + 0x200, + .end = MX27_USBOTG_BASE_ADDR + 0x3ff, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB1, - .end = MXC_INT_USB1, + .start = MX27_INT_USB1, + .end = MX27_INT_USB1, .flags = IORESOURCE_IRQ, }, }; @@ -508,12 +374,12 @@ static u64 usbh2_dmamask = 0xffffffffUL; static struct resource mxc_usbh2_resources[] = { { - .start = OTG_BASE_ADDR + 0x400, - .end = OTG_BASE_ADDR + 0x5ff, + .start = MX27_USBOTG_BASE_ADDR + 0x400, + .end = MX27_USBOTG_BASE_ADDR + 0x5ff, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB2, - .end = MXC_INT_USB2, + .start = MX27_INT_USB2, + .end = MX27_INT_USB2, .flags = IORESOURCE_IRQ, }, }; @@ -530,115 +396,88 @@ struct platform_device mxc_usbh2 = { }; #endif -static struct resource imx_ssi_resources0[] = { - { - .start = SSI1_BASE_ADDR, - .end = SSI1_BASE_ADDR + 0x6F, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SSI1, - .end = MXC_INT_SSI1, - .flags = IORESOURCE_IRQ, - }, { - .name = "tx0", - .start = DMA_REQ_SSI1_TX0, - .end = DMA_REQ_SSI1_TX0, - .flags = IORESOURCE_DMA, - }, { - .name = "rx0", - .start = DMA_REQ_SSI1_RX0, - .end = DMA_REQ_SSI1_RX0, - .flags = IORESOURCE_DMA, - }, { - .name = "tx1", - .start = DMA_REQ_SSI1_TX1, - .end = DMA_REQ_SSI1_TX1, - .flags = IORESOURCE_DMA, - }, { - .name = "rx1", - .start = DMA_REQ_SSI1_RX1, - .end = DMA_REQ_SSI1_RX1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct resource imx_ssi_resources1[] = { - { - .start = SSI2_BASE_ADDR, - .end = SSI2_BASE_ADDR + 0x6F, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SSI2, - .end = MXC_INT_SSI2, - .flags = IORESOURCE_IRQ, - }, { - .name = "tx0", - .start = DMA_REQ_SSI2_TX0, - .end = DMA_REQ_SSI2_TX0, - .flags = IORESOURCE_DMA, - }, { - .name = "rx0", - .start = DMA_REQ_SSI2_RX0, - .end = DMA_REQ_SSI2_RX0, - .flags = IORESOURCE_DMA, - }, { - .name = "tx1", - .start = DMA_REQ_SSI2_TX1, - .end = DMA_REQ_SSI2_TX1, - .flags = IORESOURCE_DMA, - }, { - .name = "rx1", - .start = DMA_REQ_SSI2_RX1, - .end = DMA_REQ_SSI2_RX1, - .flags = IORESOURCE_DMA, - }, -}; +#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \ + { \ + .name = _name, \ + .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .flags = IORESOURCE_DMA, \ + } -struct platform_device imx_ssi_device0 = { - .name = "imx-ssi", - .id = 0, - .num_resources = ARRAY_SIZE(imx_ssi_resources0), - .resource = imx_ssi_resources0, -}; +#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \ + static struct resource imx_ssi_resources ## n[] = { \ + { \ + .start = MX2x_SSI ## ssin ## _BASE_ADDR, \ + .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = MX2x_INT_SSI1, \ + .end = MX2x_INT_SSI1, \ + .flags = IORESOURCE_IRQ, \ + }, \ + DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \ + DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \ + DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \ + DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \ + }; \ + \ + struct platform_device imx_ssi_device ## n = { \ + .name = "imx-ssi", \ + .id = n, \ + .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \ + .resource = imx_ssi_resources ## n, \ + } -struct platform_device imx_ssi_device1 = { - .name = "imx-ssi", - .id = 1, - .num_resources = ARRAY_SIZE(imx_ssi_resources1), - .resource = imx_ssi_resources1, -}; +DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); +DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); /* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .irq = MXC_INT_GPIO, - .base = IO_ADDRESS(GPIO_BASE_ADDR), - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - }, { - .chip.label = "gpio-4", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), - .virtual_irq_start = MXC_GPIO_IRQ_START + 128, - }, { - .chip.label = "gpio-5", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), - .virtual_irq_start = MXC_GPIO_IRQ_START + 160, +#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ + { \ + .chip.label = "gpio-" #n, \ + .irq = _irq, \ + .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ + n * 0x100), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ } -}; + +#define DEFINE_MXC_GPIO_PORT(SOC, n) \ + { \ + .chip.label = "gpio-" #n, \ + .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ + n * 0x100), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ + } + +#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \ + static struct mxc_gpio_port pfx ## _gpio_ports[] = { \ + DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \ + DEFINE_MXC_GPIO_PORT(SOC, 1), \ + DEFINE_MXC_GPIO_PORT(SOC, 2), \ + DEFINE_MXC_GPIO_PORT(SOC, 3), \ + DEFINE_MXC_GPIO_PORT(SOC, 4), \ + DEFINE_MXC_GPIO_PORT(SOC, 5), \ + } + +#ifdef CONFIG_MACH_MX21 +DEFINE_MXC_GPIO_PORTS(MX21, imx21); +#endif + +#ifdef CONFIG_MACH_MX27 +DEFINE_MXC_GPIO_PORTS(MX27, imx27); +#endif int __init mxc_register_gpios(void) { - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) + return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); + else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); + else +#endif + return 0; } diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index 97306aa18f1c..f15df2aaae4d 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h @@ -1,8 +1,10 @@ extern struct platform_device mxc_gpt1; extern struct platform_device mxc_gpt2; +#ifdef CONFIG_MACH_MX27 extern struct platform_device mxc_gpt3; extern struct platform_device mxc_gpt4; extern struct platform_device mxc_gpt5; +#endif extern struct platform_device mxc_wdt; extern struct platform_device mxc_uart_device0; extern struct platform_device mxc_uart_device1; @@ -11,12 +13,19 @@ extern struct platform_device mxc_uart_device3; extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_uart_device5; extern struct platform_device mxc_w1_master_device; -extern struct platform_device mxc_nand_device; +#ifdef CONFIG_MACH_MX21 +extern struct platform_device imx21_nand_device; +#endif +#ifdef CONFIG_MACH_MX27 +extern struct platform_device imx27_nand_device; +#endif extern struct platform_device mxc_fb_device; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_pwm_device; extern struct platform_device mxc_i2c_device0; +#ifdef CONFIG_MACH_MX27 extern struct platform_device mxc_i2c_device1; +#endif extern struct platform_device mxc_sdhc_device0; extern struct platform_device mxc_sdhc_device1; extern struct platform_device mxc_otg_udc_device; @@ -25,6 +34,8 @@ extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; extern struct platform_device mxc_spi_device0; extern struct platform_device mxc_spi_device1; +#ifdef CONFIG_MACH_MX27 extern struct platform_device mxc_spi_device2; +#endif extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c index 7382b6d27ee1..f3b169d5245f 100644 --- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c @@ -28,7 +28,7 @@ #include <asm/mach/arch.h> #include <mach/common.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/imxfb.h> #include <mach/hardware.h> #include <mach/mmc.h> diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c index 92fd1bf7a638..1f616dcaabc9 100644 --- a/arch/arm/mach-mx2/mach-cpuimx27.c +++ b/arch/arm/mach-mx2/mach-cpuimx27.c @@ -36,7 +36,7 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/i2c.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/imx-uart.h> #include <mach/mxc_nand.h> @@ -189,7 +189,8 @@ static void __init eukrea_cpuimx27_init(void) mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); - mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info); + mxc_register_device(&imx27_nand_device, + &eukrea_cpuimx27_nand_board_info); i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c index 621c2c1046ea..b5710bf18b96 100644 --- a/arch/arm/mach-mx2/mach-imx27lite.c +++ b/arch/arm/mach-mx2/mach-imx27lite.c @@ -27,7 +27,7 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/board-mx27lite.h> #include "devices.h" diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c index d5eb8065df3e..113e58d7cb40 100644 --- a/arch/arm/mach-mx2/mach-mx21ads.c +++ b/arch/arm/mach-mx2/mach-mx21ads.c @@ -30,7 +30,7 @@ #include <asm/mach/map.h> #include <mach/imx-uart.h> #include <mach/imxfb.h> -#include <mach/iomux.h> +#include <mach/iomux-mx21.h> #include <mach/mxc_nand.h> #include <mach/mmc.h> #include <mach/board-mx21ads.h> @@ -268,7 +268,7 @@ static void __init mx21ads_board_init(void) mxc_register_device(&mxc_uart_device3, &uart_pdata); mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); - mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info); + mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-mx2/mach-mx27_3ds.c index 8c975f6514ad..b2f4e0db3fb3 100644 --- a/arch/arm/mach-mx2/mach-mx27_3ds.c +++ b/arch/arm/mach-mx2/mach-mx27_3ds.c @@ -26,7 +26,7 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/board-mx27pdk.h> #include "devices.h" diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c index 808ca271a829..6ce323669e58 100644 --- a/arch/arm/mach-mx2/mach-mx27ads.c +++ b/arch/arm/mach-mx2/mach-mx27ads.c @@ -33,7 +33,7 @@ #include <asm/mach/map.h> #include <mach/gpio.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/board-mx27ads.h> #include <mach/mxc_nand.h> #include <mach/i2c.h> @@ -290,7 +290,7 @@ static void __init mx27ads_board_init(void) mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); - mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info); + mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, mx27ads_i2c_devices, diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-mx2/mach-mxt_td60.c index df954d879cc3..bc3855992677 100644 --- a/arch/arm/mach-mx2/mach-mxt_td60.c +++ b/arch/arm/mach-mx2/mach-mxt_td60.c @@ -33,7 +33,7 @@ #include <asm/mach/map.h> #include <linux/gpio.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> #include <mach/i2c.h> #include <linux/i2c/pca953x.h> @@ -257,7 +257,7 @@ static void __init mxt_td60_board_init(void) mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); - mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info); + mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info); i2c_register_board_info(0, mxt_td60_i2c_devices, ARRAY_SIZE(mxt_td60_i2c_devices)); diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c index d12bdb1fcabb..778fff230918 100644 --- a/arch/arm/mach-mx2/mach-pca100.c +++ b/arch/arm/mach-mx2/mach-pca100.c @@ -35,7 +35,7 @@ #include <asm/mach-types.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/i2c.h> #include <asm/mach/time.h> #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) @@ -324,7 +324,7 @@ static void __init pca100_init(void) mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN); mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); - mxc_register_device(&mxc_nand_device, &pca100_nand_board_info); + mxc_register_device(&imx27_nand_device, &pca100_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pca100_i2c_devices, diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c index 5a0169cff20f..035fbe046ec0 100644 --- a/arch/arm/mach-mx2/mach-pcm038.c +++ b/arch/arm/mach-mx2/mach-pcm038.c @@ -36,7 +36,7 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/i2c.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/imx-uart.h> #include <mach/mxc_nand.h> #include <mach/spi.h> @@ -309,7 +309,7 @@ static void __init pcm038_init(void) mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); mxc_gpio_mode(PE16_AF_OWIRE); - mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); + mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pcm038_i2c_devices, diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-mx2/mm-imx21.c new file mode 100644 index 000000000000..64134314d012 --- /dev/null +++ b/arch/arm/mach-mx2/mm-imx21.c @@ -0,0 +1,83 @@ +/* + * arch/arm/mach-mx2/mm-imx21.c + * + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/mm.h> +#include <linux/init.h> +#include <mach/hardware.h> +#include <mach/common.h> +#include <asm/pgtable.h> +#include <asm/mach/map.h> + +/* MX21 memory map definition */ +static struct map_desc imx21_io_desc[] __initdata = { + /* + * this fixed mapping covers: + * - AIPI1 + * - AIPI2 + * - AITC + * - ROM Patch + * - and some reserved space + */ + { + .virtual = MX21_AIPI_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR), + .length = MX21_AIPI_SIZE, + .type = MT_DEVICE + }, + /* + * this fixed mapping covers: + * - CSI + * - ATA + */ + { + .virtual = MX21_SAHB1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR), + .length = MX21_SAHB1_SIZE, + .type = MT_DEVICE + }, + /* + * this fixed mapping covers: + * - EMI + */ + { + .virtual = MX21_X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR), + .length = MX21_X_MEMC_SIZE, + .type = MT_DEVICE + }, +}; + +/* + * Initialize the memory map. It is called during the + * system startup to create static physical to virtual + * memory map for the IO modules. + */ +void __init mx21_map_io(void) +{ + mxc_set_cpu_type(MXC_CPU_MX21); + mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); + + iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); +} + +void __init mx21_init_irq(void) +{ + mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); +} diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/mm-imx27.c index ae8f759134d1..3366ed44cfd5 100644 --- a/arch/arm/mach-mx2/generic.c +++ b/arch/arm/mach-mx2/mm-imx27.c @@ -1,5 +1,5 @@ /* - * generic.c + * arch/arm/mach-mx2/mm-imx27.c * * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) * @@ -26,7 +26,7 @@ #include <asm/mach/map.h> /* MX27 memory map definition */ -static struct map_desc mxc_io_desc[] __initdata = { +static struct map_desc imx27_io_desc[] __initdata = { /* * this fixed mapping covers: * - AIPI1 @@ -36,9 +36,9 @@ static struct map_desc mxc_io_desc[] __initdata = { * - and some reserved space */ { - .virtual = AIPI_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AIPI_BASE_ADDR), - .length = AIPI_SIZE, + .virtual = MX27_AIPI_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR), + .length = MX27_AIPI_SIZE, .type = MT_DEVICE }, /* @@ -47,9 +47,9 @@ static struct map_desc mxc_io_desc[] __initdata = { * - ATA */ { - .virtual = SAHB1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(SAHB1_BASE_ADDR), - .length = SAHB1_SIZE, + .virtual = MX27_SAHB1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR), + .length = MX27_SAHB1_SIZE, .type = MT_DEVICE }, /* @@ -57,11 +57,11 @@ static struct map_desc mxc_io_desc[] __initdata = { * - EMI */ { - .virtual = X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), - .length = X_MEMC_SIZE, + .virtual = MX27_X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR), + .length = MX27_X_MEMC_SIZE, .type = MT_DEVICE - } + }, }; /* @@ -69,29 +69,15 @@ static struct map_desc mxc_io_desc[] __initdata = { * system startup to create static physical to virtual * memory map for the IO modules. */ -void __init mx21_map_io(void) -{ - mxc_set_cpu_type(MXC_CPU_MX21); - mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); - - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); -} - void __init mx27_map_io(void) { mxc_set_cpu_type(MXC_CPU_MX27); - mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); + mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); } void __init mx27_init_irq(void) { - mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); + mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); } - -void __init mx21_init_irq(void) -{ - mx27_init_irq(); -} - diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c index 60d54465ada1..4aafd5b8b85b 100644 --- a/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/arch/arm/mach-mx2/pcm970-baseboard.c @@ -24,7 +24,7 @@ #include <asm/mach/arch.h> #include <mach/common.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/imxfb.h> #include <mach/hardware.h> #include <mach/mmc.h> diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25pdk.c index 99b9463ca154..83d74109e7d8 100644 --- a/arch/arm/mach-mx25/mach-mx25pdk.c +++ b/arch/arm/mach-mx25/mach-mx25pdk.c @@ -37,7 +37,7 @@ #include <mach/mxc_nand.h> #include <mach/imxfb.h> #include "devices.h" -#include <mach/iomux.h> +#include <mach/iomux-mx25.h> static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 44f3a805ae56..7f7ad6f289bd 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -9,21 +9,20 @@ choice config ARCH_MX1 bool "MX1-based" select CPU_ARM920T - select COMMON_CLKDEV + select IMX_HAVE_IOMUX_V1 help This enables support for systems based on the Freescale i.MX1 family config ARCH_MX2 bool "MX2-based" select CPU_ARM926T - select COMMON_CLKDEV + select IMX_HAVE_IOMUX_V1 help This enables support for systems based on the Freescale i.MX2 family config ARCH_MX25 bool "MX25-based" select CPU_ARM926T - select COMMON_CLKDEV select ARCH_MXC_IOMUX_V3 select HAVE_FB_IMX help @@ -32,21 +31,18 @@ config ARCH_MX25 config ARCH_MX3 bool "MX3-based" select CPU_V6 - select COMMON_CLKDEV help This enables support for systems based on the Freescale i.MX3 family config ARCH_MXC91231 bool "MXC91231-based" select CPU_V6 - select COMMON_CLKDEV help This enables support for systems based on the Freescale MXC91231 family config ARCH_MX5 bool "MX5-based" select CPU_V7 - select COMMON_CLKDEV help This enables support for systems based on the Freescale i.MX51 family @@ -63,7 +59,6 @@ endmenu config MXC_IRQ_PRIOR bool "Use IRQ priority" - depends on ARCH_MXC help Select this if you want to use prioritized IRQ handling. This feature prevents higher priority ISR to be interrupted @@ -82,7 +77,6 @@ config MXC_TZIC config MXC_PWM tristate "Enable PWM driver" - depends on ARCH_MXC select HAVE_PWM help Enable support for the i.MX PWM controller(s). @@ -92,7 +86,9 @@ config MXC_ULPI config ARCH_HAS_RNGA bool - depends on ARCH_MXC + +config IMX_HAVE_IOMUX_V1 + bool config ARCH_MXC_IOMUX_V3 bool diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index a4bc6cb26aa4..a72a5e4ca20e 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -8,15 +8,12 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) obj-$(CONFIG_MXC_TZIC) += tzic.o -obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o -obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o -CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -CFLAGS_dma-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o +obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o +obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o -CFLAGS_audmux-v1.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o -CFLAGS_audmux-v2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c index da6387dcdf21..b62917ca3f95 100644 --- a/arch/arm/plat-mxc/audmux-v1.c +++ b/arch/arm/plat-mxc/audmux-v1.c @@ -50,8 +50,18 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port); static int mxc_audmux_v1_init(void) { - if (cpu_is_mx27() || cpu_is_mx21()) - audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) + audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR); + else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR); + else +#endif + (void)0; + return 0; } diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index b06954a84436..d983cd6c788c 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -190,7 +190,10 @@ static int mxc_audmux_v2_init(void) { int ret; - if (cpu_is_mx35()) { + if (cpu_is_mx31()) + audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); + + else if (cpu_is_mx35()) { audmux_clk = clk_get(NULL, "audmux"); if (IS_ERR(audmux_clk)) { ret = PTR_ERR(audmux_clk); @@ -198,11 +201,9 @@ static int mxc_audmux_v2_init(void) ret); return ret; } + audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); } - if (cpu_is_mx31() || cpu_is_mx35()) - audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); - audmux_debugfs_init(); return 0; diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c index 9c1b3f9c4f4d..e16014b0d13c 100644 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ b/arch/arm/plat-mxc/dma-mx1-mx2.c @@ -128,6 +128,18 @@ struct imx_dma_channel { int hw_chaining; }; +static void __iomem *imx_dmav1_baseaddr; + +static void imx_dmav1_writel(unsigned val, unsigned offset) +{ + __raw_writel(val, imx_dmav1_baseaddr + offset); +} + +static unsigned imx_dmav1_readl(unsigned offset) +{ + return __raw_readl(imx_dmav1_baseaddr + offset); +} + static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; static struct clk *dma_clk; @@ -140,7 +152,6 @@ static int imx_dma_hw_chain(struct imx_dma_channel *imxdma) return 0; } - /* * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation */ @@ -160,17 +171,17 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg) imxdma->resbytes -= now; if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) - __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel)); + imx_dmav1_writel(sg->dma_address, DMA_DAR(channel)); else - __raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel)); + imx_dmav1_writel(sg->dma_address, DMA_SAR(channel)); - __raw_writel(now, DMA_BASE + DMA_CNTR(channel)); + imx_dmav1_writel(now, DMA_CNTR(channel)); pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " "size 0x%08x\n", channel, - __raw_readl(DMA_BASE + DMA_DAR(channel)), - __raw_readl(DMA_BASE + DMA_SAR(channel)), - __raw_readl(DMA_BASE + DMA_CNTR(channel))); + imx_dmav1_readl(DMA_DAR(channel)), + imx_dmav1_readl(DMA_SAR(channel)), + imx_dmav1_readl(DMA_CNTR(channel))); return now; } @@ -218,27 +229,26 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address, channel, __func__, (unsigned int)dma_address, dma_length, dev_addr); - __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); - __raw_writel(dma_address, DMA_BASE + DMA_DAR(channel)); - __raw_writel(imxdma->ccr_from_device, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(dev_addr, DMA_SAR(channel)); + imx_dmav1_writel(dma_address, DMA_DAR(channel)); + imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel)); } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d " "dev_addr=0x%08x for write\n", channel, __func__, (unsigned int)dma_address, dma_length, dev_addr); - __raw_writel(dma_address, DMA_BASE + DMA_SAR(channel)); - __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); - __raw_writel(imxdma->ccr_to_device, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(dma_address, DMA_SAR(channel)); + imx_dmav1_writel(dev_addr, DMA_DAR(channel)); + imx_dmav1_writel(imxdma->ccr_to_device, + DMA_CCR(channel)); } else { printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", channel); return -EINVAL; } - __raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel)); + imx_dmav1_writel(dma_length, DMA_CNTR(channel)); return 0; } @@ -316,17 +326,15 @@ imx_dma_setup_sg(int channel, "dev_addr=0x%08x for read\n", channel, __func__, sg, sgcount, dma_length, dev_addr); - __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); - __raw_writel(imxdma->ccr_from_device, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(dev_addr, DMA_SAR(channel)); + imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel)); } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d " "dev_addr=0x%08x for write\n", channel, __func__, sg, sgcount, dma_length, dev_addr); - __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); - __raw_writel(imxdma->ccr_to_device, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(dev_addr, DMA_DAR(channel)); + imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel)); } else { printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", channel); @@ -360,7 +368,7 @@ imx_dma_config_channel(int channel, unsigned int config_port, imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq; imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq; - __raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel)); + imx_dmav1_writel(dmareq, DMA_RSSR(channel)); return 0; } @@ -368,7 +376,7 @@ EXPORT_SYMBOL(imx_dma_config_channel); void imx_dma_config_burstlen(int channel, unsigned int burstlen) { - __raw_writel(burstlen, DMA_BASE + DMA_BLR(channel)); + imx_dmav1_writel(burstlen, DMA_BLR(channel)); } EXPORT_SYMBOL(imx_dma_config_burstlen); @@ -398,7 +406,7 @@ imx_dma_setup_handlers(int channel, } local_irq_save(flags); - __raw_writel(1 << channel, DMA_BASE + DMA_DISR); + imx_dmav1_writel(1 << channel, DMA_DISR); imxdma->irq_handler = irq_handler; imxdma->err_handler = err_handler; imxdma->data = data; @@ -462,22 +470,21 @@ void imx_dma_enable(int channel) local_irq_save(flags); - __raw_writel(1 << channel, DMA_BASE + DMA_DISR); - __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel), - DMA_BASE + DMA_DIMR); - __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN | - CCR_ACRPT, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(1 << channel, DMA_DISR); + imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR); + imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN | + CCR_ACRPT, DMA_CCR(channel)); #ifdef CONFIG_ARCH_MX2 - if (imxdma->sg && imx_dma_hw_chain(imxdma)) { + if ((cpu_is_mx21() || cpu_is_mx27()) && + imxdma->sg && imx_dma_hw_chain(imxdma)) { imxdma->sg = sg_next(imxdma->sg); if (imxdma->sg) { u32 tmp; imx_dma_sg_next(channel, imxdma->sg); - tmp = __raw_readl(DMA_BASE + DMA_CCR(channel)); - __raw_writel(tmp | CCR_RPT | CCR_ACRPT, - DMA_BASE + DMA_CCR(channel)); + tmp = imx_dmav1_readl(DMA_CCR(channel)); + imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT, + DMA_CCR(channel)); } } #endif @@ -502,11 +509,10 @@ void imx_dma_disable(int channel) del_timer(&imxdma->watchdog); local_irq_save(flags); - __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel), - DMA_BASE + DMA_DIMR); - __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN, - DMA_BASE + DMA_CCR(channel)); - __raw_writel(1 << channel, DMA_BASE + DMA_DISR); + imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR); + imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN, + DMA_CCR(channel)); + imx_dmav1_writel(1 << channel, DMA_DISR); imxdma->in_use = 0; local_irq_restore(flags); } @@ -517,7 +523,7 @@ static void imx_dma_watchdog(unsigned long chno) { struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; - __raw_writel(0, DMA_BASE + DMA_CCR(chno)); + imx_dmav1_writel(0, DMA_CCR(chno)); imxdma->in_use = 0; imxdma->sg = NULL; @@ -533,17 +539,17 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id) unsigned int err_mask; int errcode; - disr = __raw_readl(DMA_BASE + DMA_DISR); + disr = imx_dmav1_readl(DMA_DISR); - err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) | - __raw_readl(DMA_BASE + DMA_DRTOSR) | - __raw_readl(DMA_BASE + DMA_DSESR) | - __raw_readl(DMA_BASE + DMA_DBOSR); + err_mask = imx_dmav1_readl(DMA_DBTOSR) | + imx_dmav1_readl(DMA_DRTOSR) | + imx_dmav1_readl(DMA_DSESR) | + imx_dmav1_readl(DMA_DBOSR); if (!err_mask) return IRQ_HANDLED; - __raw_writel(disr & err_mask, DMA_BASE + DMA_DISR); + imx_dmav1_writel(disr & err_mask, DMA_DISR); for (i = 0; i < IMX_DMA_CHANNELS; i++) { if (!(err_mask & (1 << i))) @@ -551,20 +557,20 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id) imxdma = &imx_dma_channels[i]; errcode = 0; - if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) { - __raw_writel(1 << i, DMA_BASE + DMA_DBTOSR); + if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) { + imx_dmav1_writel(1 << i, DMA_DBTOSR); errcode |= IMX_DMA_ERR_BURST; } - if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) { - __raw_writel(1 << i, DMA_BASE + DMA_DRTOSR); + if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) { + imx_dmav1_writel(1 << i, DMA_DRTOSR); errcode |= IMX_DMA_ERR_REQUEST; } - if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) { - __raw_writel(1 << i, DMA_BASE + DMA_DSESR); + if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) { + imx_dmav1_writel(1 << i, DMA_DSESR); errcode |= IMX_DMA_ERR_TRANSFER; } - if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) { - __raw_writel(1 << i, DMA_BASE + DMA_DBOSR); + if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) { + imx_dmav1_writel(1 << i, DMA_DBOSR); errcode |= IMX_DMA_ERR_BUFFER; } if (imxdma->name && imxdma->err_handler) { @@ -607,7 +613,7 @@ static void dma_irq_handle_channel(int chno) if (imxdma->sg) { imx_dma_sg_next(chno, imxdma->sg); - tmp = __raw_readl(DMA_BASE + DMA_CCR(chno)); + tmp = imx_dmav1_readl(DMA_CCR(chno)); if (imx_dma_hw_chain(imxdma)) { /* FIXME: The timeout should probably be @@ -617,15 +623,13 @@ static void dma_irq_handle_channel(int chno) jiffies + msecs_to_jiffies(500)); tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; - __raw_writel(tmp, DMA_BASE + - DMA_CCR(chno)); + imx_dmav1_writel(tmp, DMA_CCR(chno)); } else { - __raw_writel(tmp & ~CCR_CEN, DMA_BASE + - DMA_CCR(chno)); + imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno)); tmp |= CCR_CEN; } - __raw_writel(tmp, DMA_BASE + DMA_CCR(chno)); + imx_dmav1_writel(tmp, DMA_CCR(chno)); if (imxdma->prog_handler) imxdma->prog_handler(chno, imxdma->data, @@ -640,7 +644,7 @@ static void dma_irq_handle_channel(int chno) } } - __raw_writel(0, DMA_BASE + DMA_CCR(chno)); + imx_dmav1_writel(0, DMA_CCR(chno)); imxdma->in_use = 0; if (imxdma->irq_handler) imxdma->irq_handler(chno, imxdma->data); @@ -651,15 +655,16 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) int i, disr; #ifdef CONFIG_ARCH_MX2 - dma_err_handler(irq, dev_id); + if (cpu_is_mx21() || cpu_is_mx27()) + dma_err_handler(irq, dev_id); #endif - disr = __raw_readl(DMA_BASE + DMA_DISR); + disr = imx_dmav1_readl(DMA_DISR); pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", disr); - __raw_writel(disr, DMA_BASE + DMA_DISR); + imx_dmav1_writel(disr, DMA_DISR); for (i = 0; i < IMX_DMA_CHANNELS; i++) { if (disr & (1 << i)) dma_irq_handle_channel(i); @@ -699,17 +704,19 @@ int imx_dma_request(int channel, const char *name) local_irq_restore(flags); /* request_irq() can block */ #ifdef CONFIG_ARCH_MX2 - ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA", - NULL); - if (ret) { - imxdma->name = NULL; - printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n", - MXC_INT_DMACH0 + channel, channel); - return ret; + if (cpu_is_mx21() || cpu_is_mx27()) { + ret = request_irq(MX2x_INT_DMACH0 + channel, + dma_irq_handler, 0, "DMA", NULL); + if (ret) { + imxdma->name = NULL; + pr_crit("Can't register IRQ %d for DMA channel %d\n", + MX2x_INT_DMACH0 + channel, channel); + return ret; + } + init_timer(&imxdma->watchdog); + imxdma->watchdog.function = &imx_dma_watchdog; + imxdma->watchdog.data = channel; } - init_timer(&imxdma->watchdog); - imxdma->watchdog.function = &imx_dma_watchdog; - imxdma->watchdog.data = channel; #endif return ret; @@ -738,7 +745,8 @@ void imx_dma_free(int channel) imxdma->name = NULL; #ifdef CONFIG_ARCH_MX2 - free_irq(MXC_INT_DMACH0 + channel, NULL); + if (cpu_is_mx21() || cpu_is_mx27()) + free_irq(MX2x_INT_DMACH0 + channel, NULL); #endif local_irq_restore(flags); @@ -796,34 +804,53 @@ static int __init imx_dma_init(void) int ret = 0; int i; +#ifdef CONFIG_ARCH_MX1 + if (cpu_is_mx1()) + imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); + else +#endif +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) + imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); + else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); + else +#endif + BUG(); + dma_clk = clk_get(NULL, "dma"); clk_enable(dma_clk); /* reset DMA module */ - __raw_writel(DCR_DRST, DMA_BASE + DMA_DCR); + imx_dmav1_writel(DCR_DRST, DMA_DCR); #ifdef CONFIG_ARCH_MX1 - ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); - if (ret) { - printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); - return ret; - } + if (cpu_is_mx1()) { + ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL); + if (ret) { + pr_crit("Wow! Can't register IRQ for DMA\n"); + return ret; + } - ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL); - if (ret) { - printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n"); - free_irq(DMA_INT, NULL); - return ret; + ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL); + if (ret) { + pr_crit("Wow! Can't register ERRIRQ for DMA\n"); + free_irq(MX1_DMA_INT, NULL); + return ret; + } } #endif /* enable DMA module */ - __raw_writel(DCR_DEN, DMA_BASE + DMA_DCR); + imx_dmav1_writel(DCR_DEN, DMA_DCR); /* clear all interrupts */ - __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR); + imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); /* disable interrupts */ - __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR); + imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); for (i = 0; i < IMX_DMA_CHANNELS; i++) { imx_dma_channels[i].sg = NULL; diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index d65ebe303b9f..70b23893f094 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -140,16 +140,13 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) val = __raw_readl(reg); edge = (val >> (bit << 1)) & 3; val &= ~(0x3 << (bit << 1)); - switch (edge) { - case GPIO_INT_HIGH_LEV: + if (edge == GPIO_INT_HIGH_LEV) { edge = GPIO_INT_LOW_LEV; pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); - break; - case GPIO_INT_LOW_LEV: + } else if (edge == GPIO_INT_LOW_LEV) { edge = GPIO_INT_HIGH_LEV; pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); - break; - default: + } else { pr_err("mxc: invalid configuration for GPIO %d: %x\n", gpio, edge); return; @@ -157,25 +154,20 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) __raw_writel(val | (edge << (bit << 1)), reg); } -/* handle n interrupts in one status register */ +/* handle 32 interrupts in one status register */ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) { - u32 gpio_irq_no; + u32 gpio_irq_no_base = port->virtual_irq_start; - gpio_irq_no = port->virtual_irq_start; - for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) { - u32 gpio = irq_to_gpio(gpio_irq_no); - - if ((irq_stat & 1) == 0) - continue; + while (irq_stat != 0) { + int irqoffset = fls(irq_stat) - 1; - BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); + if (port->both_edges & (1 << irqoffset)) + mxc_flip_edge(port, irqoffset); - if (port->both_edges & (1 << (gpio & 31))) - mxc_flip_edge(port, gpio); + generic_handle_irq(gpio_irq_no_base + irqoffset); - irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, - &irq_desc[gpio_irq_no]); + irq_stat &= ~(1 << irqoffset); } } diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index 43a82d0c534d..753a5988d85c 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h @@ -26,13 +26,6 @@ struct module; struct clk { -#ifndef CONFIG_COMMON_CLKDEV - /* As soon as i.MX1 and i.MX31 switched to clkdev, this - * block can go away */ - struct list_head node; - struct module *owner; - const char *name; -#endif int id; /* Source clock this clk depends on */ struct clk *parent; diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h index bf23305c19cc..6b1507cf378e 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h @@ -1,166 +1,155 @@ /* -* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX1_H__ +#define __MACH_IOMUX_MX1_H__ -#ifndef _MXC_IOMUX_MX1_H -#define _MXC_IOMUX_MX1_H +#include <mach/iomux-v1.h> -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif +#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) +#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) +#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1) +#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) +#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2) +#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) +#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) +#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) +#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) +#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) +#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) +#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) +#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) +#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) +#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) +#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) +#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) +#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) +#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) +#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) +#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) +#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) +#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) +#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) +#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) +#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) +#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) +#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) +#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) +#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) +#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) +#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) +#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) +#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) +#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) +#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) +#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) +#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) +#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) +#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) +#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) +#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) +#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) +#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) +#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) +#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) +#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) +#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) +#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) +#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) +#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) +#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) +#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) +#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) +#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) +#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) +#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) +#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16) +#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17) +#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) +#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) +#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) +#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) +#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22) +#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) +#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) +#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) +#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) +#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) +#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28) +#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29) +#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30) +#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31) +#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) +#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) +#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) +#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6) +#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) +#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) +#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) +#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10) +#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) +#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12) +#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) +#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) +#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) +#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) +#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) +#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24) +#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25) +#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26) +#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27) +#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28) +#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29) +#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) +#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31) +#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6) +#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) +#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7) +#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) +#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) +#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8) +#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) +#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) +#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9) +#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9) +#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10) +#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10) +#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10) +#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11) +#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12) +#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13) +#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14) +#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15) +#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16) +#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) +#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) +#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) +#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) +#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) +#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) +#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23) +#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) +#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) +#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) +#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) +#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) +#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) +#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30) +#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) +#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) -/* FIXME: This list is not completed. The correct directions are -* missing on some (many) pins -*/ - - -/* Primary GPIO pin functions */ - -#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) -#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) -#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1) -#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) -#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2) -#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) -#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) -#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) -#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) -#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) -#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) -#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) -#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) -#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) -#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) -#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) -#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) -#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) -#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) -#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) -#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) -#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) -#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) -#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) -#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) -#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) -#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) -#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) -#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) -#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) -#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) -#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) -#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) -#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) -#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) -#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) -#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) -#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) -#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) -#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) -#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) -#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) -#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) -#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) -#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) -#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) -#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) -#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) -#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) -#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) -#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) -#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) -#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) -#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) -#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) -#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) -#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) -#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16) -#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17) -#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) -#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) -#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) -#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) -#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22) -#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) -#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) -#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) -#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) -#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) -#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28) -#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29) -#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30) -#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31) -#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) -#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) -#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) -#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6) -#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) -#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) -#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) -#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10) -#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) -#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12) -#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) -#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) -#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) -#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) -#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) -#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24) -#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25) -#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26) -#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27) -#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28) -#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29) -#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) -#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31) -#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6) -#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) -#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7) -#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) -#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) -#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8) -#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) -#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) -#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9) -#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9) -#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10) -#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10) -#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10) -#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11) -#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12) -#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13) -#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14) -#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15) -#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16) -#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) -#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) -#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) -#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) -#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) -#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23) -#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) -#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) -#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) -#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) -#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) -#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) -#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30) -#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) -#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) - - -#endif +#endif /* ifndef __MACH_IOMUX_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h index 63aaa972e275..1495dfda7834 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx21.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h @@ -1,126 +1,122 @@ /* -* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ - -#ifndef _MXC_IOMUX_MX21_H -#define _MXC_IOMUX_MX21_H - -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif - + * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX21_H__ +#define __MACH_IOMUX_MX21_H__ + +#include <mach/iomux-mx2x.h> +#include <mach/iomux-v1.h> /* Primary GPIO pin functions */ -#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) -#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) -#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) -#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) -#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) -#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) -#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) -#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) -#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) -#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) -#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) -#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) -#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) -#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) -#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) -#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) -#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) +#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) +#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) +#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) +#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) +#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) +#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) +#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) +#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) +#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) +#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) +#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) +#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) +#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) +#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) +#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) +#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) +#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) +#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) +#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) +#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) +#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) +#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) +#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) +#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) +#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) +#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) +#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) +#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) +#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) /* Alternate GPIO pin functions */ -#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) -#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) -#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) -#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) -#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) -#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) -#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) -#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) -#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) -#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) -#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) -#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) -#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) -#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) -#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) -#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) -#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) -#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) -#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) -#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) -#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) +#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) +#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) +#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) +#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) +#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) +#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) +#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) +#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) +#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) +#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) +#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) +#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) +#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) +#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) +#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) +#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) +#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) +#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) +#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) +#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) +#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) /* AIN GPIO pin functions */ -#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) -#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) -#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) -#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) -#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) -#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) -#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) -#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) -#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) -#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) -#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) +#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) +#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) +#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) +#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) +#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) +#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) +#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) +#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) +#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) +#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) +#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) +#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) /* BIN GPIO pin functions */ -#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) -#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) +#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) +#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) /* CIN GPIO pin functions */ -#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) +#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) /* AOUT GPIO pin functions */ -#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) -#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) -#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) -#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) -#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) -#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) -#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) -#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) -#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) -#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) -#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) -#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) -#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) -#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) -#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) - - -#endif +#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) +#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) +#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) +#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) +#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) +#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) +#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) +#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) +#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) +#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) +#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) +#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) +#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) +#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) +#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) + +#endif /* ifndef __MACH_IOMUX_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h index 5418d52c4a9d..f39220d1b67a 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -7,7 +7,7 @@ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. * and * arch/arm/plat-mxc/include/mach/iomux-mx35.h - * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -16,24 +16,11 @@ * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ -#ifndef __IOMUX_MX25_H__ -#define __IOMUX_MX25_H__ +#ifndef __MACH_IOMUX_MX25_H__ +#define __MACH_IOMUX_MX25_H__ #include <mach/iomux-v3.h> -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif - -/* - * - * @brief MX25 I/O Pin List - * - * @ingroup GPIO_MX25 - */ - -#ifndef __ASSEMBLY__ - /* * IOMUX/PAD Bit field definitions */ @@ -515,5 +502,4 @@ #define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#endif // __ASSEMBLY__ -#endif // __IOMUX_MX25_H__ +#endif /* __MACH_IOMUX_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h index 5ac158b70f61..d9f9a6e32d80 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx27.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h @@ -1,207 +1,205 @@ /* -* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> -* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ - -#ifndef _MXC_IOMUX_MX27_H -#define _MXC_IOMUX_MX27_H - -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif - + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX27_H__ +#define __MACH_IOMUX_MX27_H__ + +#include <mach/iomux-mx2x.h> +#include <mach/iomux-v1.h> /* Primary GPIO pin functions */ -#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) -#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) -#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) -#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) -#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) -#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) -#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) -#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) -#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) -#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) -#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) -#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) -#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) -#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) -#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) -#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) -#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) -#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) -#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) -#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) -#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) -#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) -#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) -#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) -#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) -#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) -#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) -#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) -#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) -#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) -#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) -#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) -#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) -#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) -#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) -#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) +#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) +#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) +#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) +#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) +#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) +#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) +#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) +#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) +#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) +#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) +#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) +#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) +#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) +#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) +#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) +#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) +#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) +#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) +#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) +#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) +#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) +#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) +#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) +#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) +#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) +#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) +#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) +#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) +#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) +#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) +#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) +#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) +#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) +#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) +#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) +#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) +#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) +#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) +#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) +#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) +#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) +#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) +#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) +#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) +#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) +#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) +#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) +#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) +#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) +#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) +#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) +#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) +#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) +#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) +#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) +#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) +#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) +#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) /* Alternate GPIO pin functions */ -#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) -#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) -#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) -#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) -#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) -#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) -#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) -#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) -#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) -#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) -#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) -#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) -#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) -#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) -#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) -#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) -#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) -#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) -#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) -#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) -#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) -#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) -#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) -#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) -#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) -#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) -#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) -#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) -#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) -#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) -#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) -#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) -#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) -#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) -#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) -#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) -#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) -#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) -#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) -#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) -#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) -#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) -#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) -#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) -#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) -#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) -#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) -#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) -#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) -#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) -#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) +#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) +#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) +#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) +#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) +#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) +#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) +#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) +#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) +#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) +#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) +#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) +#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) +#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) +#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) +#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) +#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) +#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) +#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) +#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) +#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) +#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) +#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) +#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) +#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) +#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) +#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) +#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) +#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) +#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) +#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) +#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) +#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) +#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) +#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) +#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) +#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) +#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) +#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) +#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) +#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) +#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) +#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) +#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) +#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) +#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) +#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) +#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) +#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) +#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) +#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) +#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) +#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) +#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) +#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) /* AIN GPIO pin functions */ -#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) -#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) +#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) +#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) +#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) +#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) +#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) +#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) +#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) +#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) +#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) +#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) /* BIN GPIO pin functions */ -#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) +#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) /* CIN GPIO pin functions */ -#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) -#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) -#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) -#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) -#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) -#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) -#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) -#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) -#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) -#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) -#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) -#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) -#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) -#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) -#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) -#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) -#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) +#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) +#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) +#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) +#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) +#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) +#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) +#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) +#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) +#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) +#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) +#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) +#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) +#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) +#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) +#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) +#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) +#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) /* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ /* AOUT GPIO pin functions */ -#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) -#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) - -#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) -#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) -#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) -#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) -#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) -#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) -#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) - - -#endif /* _MXC_GPIO_MX1_MX2_H */ +#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) +#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) +#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) +#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) +#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) +#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) +#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) +#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) +#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) +#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) +#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) + +/* BOUT GPIO pin functions */ + +#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) +#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) +#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) +#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) +#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) +#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) +#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) + +#endif /* __MACH_IOMUX_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h index fb5ae638e79f..c4f116d214f2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h @@ -1,237 +1,230 @@ /* -* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> -* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ - -#ifndef _MXC_IOMUX_MX2x_H -#define _MXC_IOMUX_MX2x_H - -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif - + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX2x_H__ +#define __MACH_IOMUX_MX2x_H__ /* Primary GPIO pin functions */ -#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) -#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) -#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) -#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) -#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) -#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) -#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) -#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) -#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) -#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) -#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) -#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) -#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) -#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) -#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) -#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) -#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) -#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) -#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) -#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) -#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) -#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) -#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) -#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) -#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) -#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) -#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) -#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) -#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) -#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) -#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) -#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) -#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) -#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) -#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) -#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) -#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) -#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) -#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) -#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) -#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) -#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) -#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) -#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) -#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) -#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) -#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) -#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) -#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) -#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) -#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) -#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) -#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) -#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) -#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) -#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) -#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) -#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) -#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) -#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) -#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) -#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) -#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) -#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) -#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) -#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) -#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) -#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) -#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) -#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) -#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) -#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) -#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) -#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) -#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) -#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) -#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) -#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) -#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) -#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) -#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) -#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) -#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) -#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) -#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) -#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) -#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) -#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) -#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) -#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) +#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) +#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) +#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) +#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) +#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) +#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) +#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) +#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) +#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) +#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) +#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) +#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) +#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) +#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) +#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) +#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) +#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) +#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) +#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) +#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) +#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) +#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) +#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) +#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) +#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) +#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) +#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) +#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) +#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) +#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) +#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) +#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) +#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) +#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) +#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) +#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) +#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) +#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) +#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) +#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) +#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) +#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) +#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) +#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) +#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) +#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) +#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) +#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) +#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) +#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) +#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) +#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) +#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) +#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) +#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) +#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) +#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) +#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) +#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) +#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) +#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) +#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) +#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) +#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) +#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) +#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) +#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) +#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) +#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) +#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) +#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) +#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) +#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) +#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) +#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) +#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) +#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) +#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) +#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) +#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) +#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) +#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) +#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) +#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) +#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) +#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) +#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) +#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) +#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) +#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) +#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) +#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) +#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) +#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) +#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) +#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) +#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) +#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) +#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) +#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) +#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) +#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) +#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) +#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) +#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) +#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) +#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) +#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) +#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) +#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) +#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) /* Alternate GPIO pin functions */ -#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) -#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) -#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) -#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) -#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) -#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) -#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) -#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) -#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) -#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) -#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) -#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) -#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) -#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) -#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) -#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) -#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) -#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) -#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) -#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) -#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) -#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) -#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) -#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) -#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) -#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) -#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) +#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) +#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) +#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) +#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) +#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) +#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) +#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) +#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) +#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) +#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) +#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) +#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) +#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) +#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) +#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) +#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) +#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) +#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) +#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) +#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) +#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) +#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) +#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) +#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) +#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) +#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) +#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) /* AIN GPIO pin functions */ -#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) -#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) -#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) -#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) -#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) -#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) -#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) -#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) -#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) -#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) -#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) -#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) -#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) -#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) -#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) -#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) -#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) -#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) -#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) -#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) -#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) -#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) -#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) -#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) -#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) -#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) -#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) -#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) -#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) -#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) -#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) -#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) -#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) -#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) -#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) -#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) +#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) +#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) +#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) +#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) +#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) +#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) +#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) +#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) +#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) +#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) +#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) +#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) +#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) +#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) +#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) +#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) +#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) +#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) +#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) +#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) +#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) +#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) +#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) +#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) +#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) +#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) +#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) +#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) +#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) +#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) +#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) +#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) +#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) +#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) +#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) +#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) /* BIN GPIO pin functions */ -#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) +#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) /* CIN GPIO pin functions */ -#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) -#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) -#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) -#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) -#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) -#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) -#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) -#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) -#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) -#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) +#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) +#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) +#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) +#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) +#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) +#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) +#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) +#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) +#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) +#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) /* AOUT GPIO pin functions */ -#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) -#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) +#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) +#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) #define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) -#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) -#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) - +#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) +#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) -#endif +#endif /* ifndef __MACH_IOMUX_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index e1fc6da1cd10..e51465d7b224 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -16,12 +16,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * MA 02110-1301, USA. */ - -#ifndef __MACH_MX31_IOMUX_H__ -#define __MACH_MX31_IOMUX_H__ +#ifndef __MACH_IOMUX_MX3_H__ +#define __MACH_IOMUX_MX3_H__ #include <linux/types.h> - /* * various IOMUX output functions */ @@ -34,7 +32,7 @@ #define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ #define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ #define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ +#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ #define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ #define IOMUX_ICONFIG_FUNC 2 /* used as function */ #define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ @@ -167,11 +165,6 @@ int mxc_iomux_mode(unsigned int pin_mode); MXC_GPIO_IRQ_START) /* - * The number of gpio devices among the pads - */ -#define GPIO_PORT_MAX 3 - -/* * This enumeration is constructed based on the Section * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated * value is constructed based on the rules described above. @@ -633,40 +626,40 @@ enum iomux_pins { #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) #define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) #define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) #define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) #define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) #define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) #define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) #define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) #define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) #define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) #define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) #define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) #define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) #define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) #define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) @@ -711,8 +704,8 @@ enum iomux_pins { #define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) #define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) #define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) #define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) #define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) @@ -727,13 +720,14 @@ enum iomux_pins { #define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) #define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) -/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 - * cspi1_ss1*/ +/* + * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, + * cspi2_ss1, cspi1_ss0 cspi1_ss1 + */ /* * This function configures the pad value for a IOMUX pin. */ void mxc_iomux_set_pad(enum iomux_pins, u32); -#endif - +#endif /* ifndef __MACH_IOMUX_MX3_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h index c88d40795f7a..2a24bae1b878 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h @@ -1,5 +1,5 @@ /* - * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h new file mode 100644 index 000000000000..884f5753f279 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_V1_H__ +#define __MACH_IOMUX_V1_H__ + +/* +* GPIO Module and I/O Multiplexer +* x = 0..3 for reg_A, reg_B, reg_C, reg_D +*/ +#define MXC_DDIR(x) (0x00 + ((x) << 8)) +#define MXC_OCR1(x) (0x04 + ((x) << 8)) +#define MXC_OCR2(x) (0x08 + ((x) << 8)) +#define MXC_ICONFA1(x) (0x0c + ((x) << 8)) +#define MXC_ICONFA2(x) (0x10 + ((x) << 8)) +#define MXC_ICONFB1(x) (0x14 + ((x) << 8)) +#define MXC_ICONFB2(x) (0x18 + ((x) << 8)) +#define MXC_DR(x) (0x1c + ((x) << 8)) +#define MXC_GIUS(x) (0x20 + ((x) << 8)) +#define MXC_SSR(x) (0x24 + ((x) << 8)) +#define MXC_ICR1(x) (0x28 + ((x) << 8)) +#define MXC_ICR2(x) (0x2c + ((x) << 8)) +#define MXC_IMR(x) (0x30 + ((x) << 8)) +#define MXC_ISR(x) (0x34 + ((x) << 8)) +#define MXC_GPR(x) (0x38 + ((x) << 8)) +#define MXC_SWR(x) (0x3c + ((x) << 8)) +#define MXC_PUEN(x) (0x40 + ((x) << 8)) + +#define MX1_NUM_GPIO_PORT 4 +#define MX21_NUM_GPIO_PORT 6 +#define MX27_NUM_GPIO_PORT 6 + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + +#define GPIO_OUT (1 << 8) +#define GPIO_IN (0 << 8) +#define GPIO_PUEN (1 << 9) + +#define GPIO_PF (1 << 10) +#define GPIO_AF (1 << 11) + +#define GPIO_OCR_SHIFT 12 +#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) +#define GPIO_AIN (0 << GPIO_OCR_SHIFT) +#define GPIO_BIN (1 << GPIO_OCR_SHIFT) +#define GPIO_CIN (2 << GPIO_OCR_SHIFT) +#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) + +#define GPIO_AOUT_SHIFT 14 +#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) + +#define GPIO_BOUT_SHIFT 16 +#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + +/* decode irq number to use with IMR(x), ISR(x) and friends */ +#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) + +#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) +#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) +#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) +#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) +#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) +#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x) + +extern int mxc_gpio_mode(int gpio_mode); +extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + const char *label); +extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); + +#endif /* __MACH_IOMUX_V1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h index 011cfcd8b820..3d226d7e7be2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux.h +++ b/arch/arm/plat-mxc/include/mach/iomux.h @@ -1,102 +1,14 @@ /* -* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> -* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ - -#ifndef _MXC_IOMUX_H -#define _MXC_IOMUX_H - -/* -* GPIO Module and I/O Multiplexer -* x = 0..3 for reg_A, reg_B, reg_C, reg_D -*/ -#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR) -#define MXC_DDIR(x) (0x00 + ((x) << 8)) -#define MXC_OCR1(x) (0x04 + ((x) << 8)) -#define MXC_OCR2(x) (0x08 + ((x) << 8)) -#define MXC_ICONFA1(x) (0x0c + ((x) << 8)) -#define MXC_ICONFA2(x) (0x10 + ((x) << 8)) -#define MXC_ICONFB1(x) (0x14 + ((x) << 8)) -#define MXC_ICONFB2(x) (0x18 + ((x) << 8)) -#define MXC_DR(x) (0x1c + ((x) << 8)) -#define MXC_GIUS(x) (0x20 + ((x) << 8)) -#define MXC_SSR(x) (0x24 + ((x) << 8)) -#define MXC_ICR1(x) (0x28 + ((x) << 8)) -#define MXC_ICR2(x) (0x2c + ((x) << 8)) -#define MXC_IMR(x) (0x30 + ((x) << 8)) -#define MXC_ISR(x) (0x34 + ((x) << 8)) -#define MXC_GPR(x) (0x38 + ((x) << 8)) -#define MXC_SWR(x) (0x3c + ((x) << 8)) -#define MXC_PUEN(x) (0x40 + ((x) << 8)) - -#ifdef CONFIG_ARCH_MX1 -# define GPIO_PORT_MAX 3 -#endif -#ifdef CONFIG_ARCH_MX2 -# define GPIO_PORT_MAX 5 -#endif -#ifdef CONFIG_ARCH_MX25 -# define GPIO_PORT_MAX 3 -#endif - -#ifndef GPIO_PORT_MAX -# error "GPIO config port count unknown!" -#endif - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef __MACH_IOMUX_H__ +#define __MACH_IOMUX_H__ +/* This file will go away, please include mach/iomux-mx... directly */ #ifdef CONFIG_ARCH_MX1 #include <mach/iomux-mx1.h> @@ -110,25 +22,5 @@ #include <mach/iomux-mx27.h> #endif #endif -#ifdef CONFIG_ARCH_MX25 -#include <mach/iomux-mx25.h> -#endif - -/* decode irq number to use with IMR(x), ISR(x) and friends */ -#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) - -#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) -#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) -#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) -#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) -#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) -#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x) - - -extern void mxc_gpio_mode(int gpio_mode); -extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - const char *label); -extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); - -#endif +#endif /* __MACH_IOMUX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index a3ad643de5a1..86781f7b0c0c 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -22,18 +22,19 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS -#if defined CONFIG_ARCH_MX1 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX2 +/* these are ordered by size to support multi-SoC kernels */ +#if defined CONFIG_ARCH_MX2 #define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_ARCH_MX3 -#define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_MX1 +#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX5 #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MXC91231 #define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX3 +#define MXC_GPIO_IRQS (32 * 3) #endif /* diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 7cae9cb6208d..c4b40c35a6a1 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -37,20 +37,19 @@ # endif #endif -#if defined(CONFIG_MX1_VIDEO) +#if defined(CONFIG_MX3_VIDEO) /* * Increase size of DMA-consistent memory region. - * This is required for i.MX camera driver to capture at least four VGA frames. + * This is required for mx3 camera driver to capture at least two QXGA frames. */ -#define CONSISTENT_DMA_SIZE SZ_4M -#endif /* CONFIG_MX1_VIDEO */ +#define CONSISTENT_DMA_SIZE SZ_8M -#if defined(CONFIG_MX3_VIDEO) +#elif defined(CONFIG_MX1_VIDEO) /* * Increase size of DMA-consistent memory region. - * This is required for mx3 camera driver to capture at least two QXGA frames. + * This is required for i.MX camera driver to capture at least four VGA frames. */ -#define CONSISTENT_DMA_SIZE SZ_8M -#endif /* CONFIG_MX3_VIDEO */ +#define CONSISTENT_DMA_SIZE SZ_4M +#endif /* CONFIG_MX1_VIDEO */ #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mtd-xip.h b/arch/arm/plat-mxc/include/mach/mtd-xip.h deleted file mode 100644 index 1ab1bba5688d..000000000000 --- a/arch/arm/plat-mxc/include/mach/mtd-xip.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * MTD primitives for XIP support. Architecture specific functions - * - * Do not include this file directly. It's included from linux/mtd/xip.h - * - * Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>, Teltonika, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <mach/mxc_timer.h> - -#ifndef __ARCH_IMX_MTD_XIP_H__ -#define __ARCH_IMX_MTD_XIP_H__ - -#ifdef CONFIG_ARCH_MX1 -/* AITC registers */ -#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR) -#define NIPNDH (AITC_BASE + 0x58) -#define NIPNDL (AITC_BASE + 0x5C) -#define INTENABLEH (AITC_BASE + 0x10) -#define INTENABLEL (AITC_BASE + 0x14) -/* MTD macros */ -#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \ - || (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL))) -#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN)) -#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96) -#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0)) -#endif /* CONFIG_ARCH_MX1 */ - -#endif /* __ARCH_IMX_MTD_XIP_H__ */ diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c deleted file mode 100644 index 25023ac2f53b..000000000000 --- a/arch/arm/plat-mxc/iomux-mx1-mx2.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * arch/arm/mach-mxc/generic.c - * - * author: Sascha Hauer - * Created: april 20th, 2004 - * Copyright: Synertronixx GmbH - * - * Common code for i.MX machines - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> -#include <linux/gpio.h> - -#include <mach/hardware.h> -#include <asm/mach/map.h> -#include <mach/iomux.h> - -void mxc_gpio_mode(int gpio_mode) -{ - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; - unsigned int tmp; - - /* Pullup enable */ - tmp = __raw_readl(VA_GPIO_BASE + MXC_PUEN(port)); - if (gpio_mode & GPIO_PUEN) - tmp |= (1 << pin); - else - tmp &= ~(1 << pin); - __raw_writel(tmp, VA_GPIO_BASE + MXC_PUEN(port)); - - /* Data direction */ - tmp = __raw_readl(VA_GPIO_BASE + MXC_DDIR(port)); - if (gpio_mode & GPIO_OUT) - tmp |= 1 << pin; - else - tmp &= ~(1 << pin); - __raw_writel(tmp, VA_GPIO_BASE + MXC_DDIR(port)); - - /* Primary / alternate function */ - tmp = __raw_readl(VA_GPIO_BASE + MXC_GPR(port)); - if (gpio_mode & GPIO_AF) - tmp |= (1 << pin); - else - tmp &= ~(1 << pin); - __raw_writel(tmp, VA_GPIO_BASE + MXC_GPR(port)); - - /* use as gpio? */ - tmp = __raw_readl(VA_GPIO_BASE + MXC_GIUS(port)); - if (gpio_mode & (GPIO_PF | GPIO_AF)) - tmp &= ~(1 << pin); - else - tmp |= (1 << pin); - __raw_writel(tmp, VA_GPIO_BASE + MXC_GIUS(port)); - - if (pin < 16) { - tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR1(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR1(port)); - - tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA1(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2); - __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA1(port)); - - tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB1(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2); - __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB1(port)); - } else { - pin -= 16; - - tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR2(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR2(port)); - - tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA2(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2); - __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA2(port)); - - tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB2(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2); - __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB2(port)); - } -} -EXPORT_SYMBOL(mxc_gpio_mode); - -int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - const char *label) -{ - const int *p = pin_list; - int i; - unsigned gpio; - unsigned mode; - int ret; - - for (i = 0; i < count; i++) { - gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); - mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK); - - if (gpio >= (GPIO_PORT_MAX + 1) * 32) { - ret = -EINVAL; - goto setup_error; - } - - ret = gpio_request(gpio, label); - if (ret) - goto setup_error; - - mxc_gpio_mode(gpio | mode); - - p++; - } - return 0; - -setup_error: - mxc_gpio_release_multiple_pins(pin_list, i); - return ret; -} -EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); - -void mxc_gpio_release_multiple_pins(const int *pin_list, int count) -{ - const int *p = pin_list; - int i; - - for (i = 0; i < count; i++) { - unsigned gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); - gpio_free(gpio); - p++; - } - -} -EXPORT_SYMBOL(mxc_gpio_release_multiple_pins); - diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c new file mode 100644 index 000000000000..960a02cbcbaf --- /dev/null +++ b/arch/arm/plat-mxc/iomux-v1.c @@ -0,0 +1,238 @@ +/* + * arch/arm/plat-mxc/iomux-v1.c + * + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH + * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix + * + * Common code for i.MX1, i.MX21 and i.MX27 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> +#include <linux/gpio.h> + +#include <mach/hardware.h> +#include <asm/mach/map.h> +#include <mach/iomux-v1.h> + +static void __iomem *imx_iomuxv1_baseaddr; +static unsigned imx_iomuxv1_numports; + +static inline unsigned long imx_iomuxv1_readl(unsigned offset) +{ + return __raw_readl(imx_iomuxv1_baseaddr + offset); +} + +static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset) +{ + __raw_writel(val, imx_iomuxv1_baseaddr + offset); +} + +static inline void imx_iomuxv1_rmwl(unsigned offset, + unsigned long mask, unsigned long value) +{ + unsigned long reg = imx_iomuxv1_readl(offset); + + reg &= ~mask; + reg |= value; + + imx_iomuxv1_writel(reg, offset); +} + +static inline void imx_iomuxv1_set_puen( + unsigned int port, unsigned int pin, int on) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0); +} + +static inline void imx_iomuxv1_set_ddir( + unsigned int port, unsigned int pin, int out) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0); +} + +static inline void imx_iomuxv1_set_gpr( + unsigned int port, unsigned int pin, int af) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0); +} + +static inline void imx_iomuxv1_set_gius( + unsigned int port, unsigned int pin, int inuse) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0); +} + +static inline void imx_iomuxv1_set_ocr( + unsigned int port, unsigned int pin, unsigned int ocr) +{ + unsigned long shift = (pin & 0xf) << 1; + unsigned long mask = 3 << shift; + unsigned long value = ocr << shift; + unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port); + + imx_iomuxv1_rmwl(offset, mask, value); +} + +static inline void imx_iomuxv1_set_iconfa( + unsigned int port, unsigned int pin, unsigned int aout) +{ + unsigned long shift = (pin & 0xf) << 1; + unsigned long mask = 3 << shift; + unsigned long value = aout << shift; + unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port); + + imx_iomuxv1_rmwl(offset, mask, value); +} + +static inline void imx_iomuxv1_set_iconfb( + unsigned int port, unsigned int pin, unsigned int bout) +{ + unsigned long shift = (pin & 0xf) << 1; + unsigned long mask = 3 << shift; + unsigned long value = bout << shift; + unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port); + + imx_iomuxv1_rmwl(offset, mask, value); +} + +int mxc_gpio_mode(int gpio_mode) +{ + unsigned int pin = gpio_mode & GPIO_PIN_MASK; + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; + unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3; + unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3; + + if (port >= imx_iomuxv1_numports) + return -EINVAL; + + /* Pullup enable */ + imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN); + + /* Data direction */ + imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT); + + /* Primary / alternate function */ + imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF); + + /* use as gpio? */ + imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF))); + + imx_iomuxv1_set_ocr(port, pin, ocr); + + imx_iomuxv1_set_iconfa(port, pin, aout); + + imx_iomuxv1_set_iconfb(port, pin, bout); + + return 0; +} +EXPORT_SYMBOL(mxc_gpio_mode); + +static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) +{ + size_t i; + int ret; + + for (i = 0; i < count; ++i) { + ret = mxc_gpio_mode(list[i]); + + if (ret) + return ret; + } + + return ret; +} + +int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + const char *label) +{ + size_t i; + int ret; + + for (i = 0; i < count; ++i) { + unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK); + + ret = gpio_request(gpio, label); + if (ret) + goto err_gpio_request; + } + + ret = imx_iomuxv1_setup_multiple(pin_list, count); + if (ret) + goto err_setup; + + return 0; + +err_setup: + BUG_ON(i != count); + +err_gpio_request: + mxc_gpio_release_multiple_pins(pin_list, i); + + return ret; +} +EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); + +void mxc_gpio_release_multiple_pins(const int *pin_list, int count) +{ + size_t i; + + for (i = 0; i < count; ++i) { + unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK); + + gpio_free(gpio); + } +} +EXPORT_SYMBOL(mxc_gpio_release_multiple_pins); + +static int imx_iomuxv1_init(void) +{ +#ifdef CONFIG_ARCH_MX1 + if (cpu_is_mx1()) { + imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR); + imx_iomuxv1_numports = MX1_NUM_GPIO_PORT; + } else +#endif +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) { + imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR); + imx_iomuxv1_numports = MX21_NUM_GPIO_PORT; + } else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) { + imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR); + imx_iomuxv1_numports = MX27_NUM_GPIO_PORT; + } else +#endif + return -ENODEV; + + return 0; +} +pure_initcall(imx_iomuxv1_init); |