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-rw-r--r--arch/blackfin/kernel/cplbinit.c42
-rw-r--r--include/asm-blackfin/mach-bf527/mem_map.h1
-rw-r--r--include/asm-blackfin/mach-bf533/mem_map.h2
-rw-r--r--include/asm-blackfin/mach-bf537/mem_map.h1
-rw-r--r--include/asm-blackfin/mach-bf548/mem_map.h11
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h19
-rw-r--r--include/asm-blackfin/mach-bf561/mem_map.h5
7 files changed, 45 insertions, 36 deletions
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c
index 959b510c5ffb..6320bc45fbba 100644
--- a/arch/blackfin/kernel/cplbinit.c
+++ b/arch/blackfin/kernel/cplbinit.c
@@ -64,7 +64,7 @@ static struct cplb_desc cplb_data[] = {
#else
.valid = 0,
#endif
- .name = "ZERO Pointer Saveguard",
+ .name = "Zero Pointer Guard Page",
},
{
.start = L1_CODE_START,
@@ -95,20 +95,20 @@ static struct cplb_desc cplb_data[] = {
.end = 0, /* dynamic */
.psize = 0,
.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
- .i_conf = SDRAM_IGENERIC,
- .d_conf = SDRAM_DGENERIC,
+ .i_conf = SDRAM_IGENERIC,
+ .d_conf = SDRAM_DGENERIC,
.valid = 1,
- .name = "SDRAM Kernel",
+ .name = "Kernel Memory",
},
{
.start = 0, /* dynamic */
.end = 0, /* dynamic */
.psize = 0,
.attr = INITIAL_T | SWITCH_T | D_CPLB,
- .i_conf = SDRAM_IGENERIC,
- .d_conf = SDRAM_DNON_CHBL,
+ .i_conf = SDRAM_IGENERIC,
+ .d_conf = SDRAM_DNON_CHBL,
.valid = 1,
- .name = "SDRAM RAM MTD",
+ .name = "uClinux MTD Memory",
},
{
.start = 0, /* dynamic */
@@ -117,7 +117,7 @@ static struct cplb_desc cplb_data[] = {
.attr = INITIAL_T | SWITCH_T | D_CPLB,
.d_conf = SDRAM_DNON_CHBL,
.valid = 1,
- .name = "SDRAM Uncached DMA ZONE",
+ .name = "Uncached DMA Zone",
},
{
.start = 0, /* dynamic */
@@ -127,7 +127,7 @@ static struct cplb_desc cplb_data[] = {
.i_conf = 0, /* dynamic */
.d_conf = 0, /* dynamic */
.valid = 1,
- .name = "SDRAM Reserved Memory",
+ .name = "Reserved Memory",
},
{
.start = ASYNC_BANK0_BASE,
@@ -136,14 +136,14 @@ static struct cplb_desc cplb_data[] = {
.attr = SWITCH_T | D_CPLB,
.d_conf = SDRAM_EBIU,
.valid = 1,
- .name = "ASYNC Memory",
+ .name = "Asynchronous Memory Banks",
},
{
-#if defined(CONFIG_BF561)
- .start = L2_SRAM,
- .end = L2_SRAM_END,
+#ifdef L2_START
+ .start = L2_START,
+ .end = L2_START + L2_LENGTH,
.psize = SIZE_1M,
- .attr = SWITCH_T | D_CPLB,
+ .attr = SWITCH_T | I_CPLB | D_CPLB,
.i_conf = L2_MEMORY,
.d_conf = L2_MEMORY,
.valid = 1,
@@ -151,7 +151,17 @@ static struct cplb_desc cplb_data[] = {
.valid = 0,
#endif
.name = "L2 Memory",
- }
+ },
+ {
+ .start = BOOT_ROM_START,
+ .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
+ .psize = SIZE_1M,
+ .attr = SWITCH_T | I_CPLB | D_CPLB,
+ .i_conf = SDRAM_IGENERIC,
+ .d_conf = SDRAM_DGENERIC,
+ .valid = 1,
+ .name = "On-Chip BootROM",
+ },
};
static u16 __init lock_kernel_check(u32 start, u32 end)
@@ -343,7 +353,7 @@ void __init generate_cpl_tables(void)
else
cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
- for (i = ZERO_P; i <= L2_MEM; i++) {
+ for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
if (!cplb_data[i].valid)
continue;
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
index bb046984231e..193082deaa4e 100644
--- a/include/asm-blackfin/mach-bf527/mem_map.h
+++ b/include/asm-blackfin/mach-bf527/mem_map.h
@@ -47,6 +47,7 @@
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x8000
/* Level 1 Memory */
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
index 8daf6d4bf093..bd30b6f3be00 100644
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -1,4 +1,3 @@
-
/*
* File: include/asm-blackfin/mach-bf533/mem_map.h
* Based on:
@@ -48,6 +47,7 @@
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x400
/* Level 1 Memory */
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index f5facdad4442..5c6726d6f3b1 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -47,6 +47,7 @@
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x800
/* Level 1 Memory */
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
index bacec3455898..00752f774986 100644
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -47,6 +47,7 @@
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x1000
/* Level 1 Memory */
@@ -87,6 +88,16 @@
#define BFIN_DSUPBANKS 0
#endif /*CONFIG_BFIN_DCACHE*/
+/* Level 2 Memory */
+#if !defined(CONFIG_BF542)
+# define L2_START 0xFEB00000
+# if defined(CONFIG_BF544)
+# define L2_LENGTH 0x10000
+# else
+# define L2_LENGTH 0x20000
+# endif
+#endif
+
/* Scratch Pad Memory */
#define L1_SCRATCH_START 0xFFB00000
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 17e1d5dcef02..3ef9e5f36136 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -33,25 +33,6 @@
#define SUPPORTED_REVID 0x3
#define OFFSET_(x) ((x) & 0x0000FFFF)
-#define L1_ISRAM 0xFFA00000
-#define L1_ISRAM_END 0xFFA04000
-#define DATA_BANKA_SRAM 0xFF800000
-#define DATA_BANKA_SRAM_END 0xFF804000
-#define DATA_BANKB_SRAM 0xFF900000
-#define DATA_BANKB_SRAM_END 0xFF904000
-#define L1_DSRAMA 0xFF800000
-#define L1_DSRAMA_END 0xFF804000
-#define L1_DSRAMB 0xFF900000
-#define L1_DSRAMB_END 0xFF904000
-#define L2_SRAM 0xFEB00000
-#define L2_SRAM_END 0xFEB20000
-#define AMB_FLASH 0x20000000
-#define AMB_FLASH_END 0x21000000
-#define AMB_FLASH_LENGTH 0x01000000
-#define L1_ISRAM_LENGTH 0x4000
-#define L1_DSRAMA_LENGTH 0x4000
-#define L1_DSRAMB_LENGTH 0x4000
-#define L2_SRAM_LENGTH 0x20000
/*some misc defines*/
#define IMASK_IVG15 0x8000
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
index 300a3a90d61c..c26d8486cc4b 100644
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -19,6 +19,11 @@
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
+/* Boot ROM Memory */
+
+#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x800
+
/* Level 1 Memory */
#ifdef CONFIG_BFIN_ICACHE
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