diff options
1355 files changed, 32689 insertions, 26086 deletions
@@ -51,6 +51,7 @@ Greg Kroah-Hartman <gregkh@suse.de> Greg Kroah-Hartman <greg@kroah.com> Henk Vergonet <Henk.Vergonet@gmail.com> Henrik Kretzschmar <henne@nachtwindheim.de> +Henrik Rydberg <rydberg@bitmath.org> Herbert Xu <herbert@gondor.apana.org.au> Jacob Shin <Jacob.Shin@amd.com> James Bottomley <jejb@mulgrave.(none)> diff --git a/Documentation/ABI/testing/sysfs-class-mei b/Documentation/ABI/testing/sysfs-class-mei index 0ec8b8178c41..80d9888a8ece 100644 --- a/Documentation/ABI/testing/sysfs-class-mei +++ b/Documentation/ABI/testing/sysfs-class-mei @@ -14,3 +14,18 @@ Description: The /sys/class/mei/meiN directory is created for each probed mei device +What: /sys/class/mei/meiN/fw_status +Date: Nov 2014 +KernelVersion: 3.19 +Contact: Tomas Winkler <tomas.winkler@intel.com> +Description: Display fw status registers content + + The ME FW writes its status information into fw status + registers for BIOS and OS to monitor fw health. + + The register contains running state, power management + state, error codes, and others. The way the registers + are decoded depends on PCH or SoC generation. + Also number of registers varies between 1 and 6 + depending on generation. + diff --git a/Documentation/devicetree/bindings/drm/atmel/hlcdc-dc.txt b/Documentation/devicetree/bindings/drm/atmel/hlcdc-dc.txt new file mode 100644 index 000000000000..ebc1a914bda3 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/atmel/hlcdc-dc.txt @@ -0,0 +1,53 @@ +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver + +The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device. +See ../mfd/atmel-hlcdc.txt for more details. + +Required properties: + - compatible: value should be "atmel,hlcdc-display-controller" + - pinctrl-names: the pin control state names. Should contain "default". + - pinctrl-0: should contain the default pinctrl states. + - #address-cells: should be set to 1. + - #size-cells: should be set to 0. + +Required children nodes: + Children nodes are encoding available output ports and their connections + to external devices using the OF graph reprensentation (see ../graph.txt). + At least one port node is required. + +Example: + + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt index c99eb34e640b..6b1d75f1a529 100644 --- a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt +++ b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt @@ -83,6 +83,22 @@ sti-hda: - clock-names: names of the clocks listed in clocks property in the same order. +sti-dvo: + Required properties: + must be a child of sti-tvout + - compatible: "st,stih<chip>-dvo" + - reg: Physical base address of the IP registers and length of memory mapped region. + - reg-names: names of the mapped memory regions listed in regs property in + the same order. + - clocks: from common clock binding: handle hardware IP needed clocks, the + number of clocks may depend of the SoC type. + See ../clocks/clock-bindings.txt for details. + - clock-names: names of the clocks listed in clocks property in the same + order. + - pinctrl-0: pin control handle + - pinctrl-name: names of the pin control to use + - sti,panel: phandle of the panel connected to the DVO output + sti-hqvdp: must be a child of sti-display-subsystem Required properties: @@ -198,6 +214,19 @@ Example: clock-names = "pix", "hddac"; clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>; }; + + sti-dvo@8d00400 { + compatible = "st,stih407-dvo"; + reg = <0x8d00400 0x200>; + reg-names = "dvo-reg"; + clock-names = "dvo_pix", "dvo", + "main_parent", "aux_parent"; + clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>, + <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvo>; + sti,panel = <&panel_dvo>; + }; }; sti-hqvdp@9c000000 { diff --git a/Documentation/devicetree/bindings/net/davinci_emac.txt b/Documentation/devicetree/bindings/net/davinci_emac.txt index 032808843f90..24c5cdaba8d2 100644 --- a/Documentation/devicetree/bindings/net/davinci_emac.txt +++ b/Documentation/devicetree/bindings/net/davinci_emac.txt @@ -4,7 +4,8 @@ This file provides information, what the device node for the davinci_emac interface contains. Required properties: -- compatible: "ti,davinci-dm6467-emac" or "ti,am3517-emac" +- compatible: "ti,davinci-dm6467-emac", "ti,am3517-emac" or + "ti,dm816-emac" - reg: Offset and length of the register set for the device - ti,davinci-ctrl-reg-offset: offset to control register - ti,davinci-ctrl-mod-reg-offset: offset to control module register diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 4df73da11adc..176d4fe4f076 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1277,6 +1277,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. i8042.notimeout [HW] Ignore timeout condition signalled by controller i8042.reset [HW] Reset the controller during init and cleanup i8042.unlock [HW] Unlock (ignore) the keylock + i8042.kbdreset [HW] Reset device connected to KBD port i810= [HW,DRM] diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index 9bffdfc648dc..85b022179104 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -66,6 +66,8 @@ fwmark_reflect - BOOLEAN route/max_size - INTEGER Maximum number of routes allowed in the kernel. Increase this when using large numbers of interfaces and/or routes. + From linux kernel 3.6 onwards, this is deprecated for ipv4 + as route cache is no longer used. neigh/default/gc_thresh1 - INTEGER Minimum number of entries to keep. Garbage collector will not diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 230ce71f4d75..2b47704f75cb 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -389,9 +389,6 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " .release_cmd = " + fabric_mod_name + "_release_cmd,\n" buf += " .shutdown_session = " + fabric_mod_name + "_shutdown_session,\n" buf += " .close_session = " + fabric_mod_name + "_close_session,\n" - buf += " .stop_session = " + fabric_mod_name + "_stop_session,\n" - buf += " .fall_back_to_erl0 = " + fabric_mod_name + "_reset_nexus,\n" - buf += " .sess_logged_in = " + fabric_mod_name + "_sess_logged_in,\n" buf += " .sess_get_index = " + fabric_mod_name + "_sess_get_index,\n" buf += " .sess_get_initiator_sid = NULL,\n" buf += " .write_pending = " + fabric_mod_name + "_write_pending,\n" @@ -402,7 +399,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " .queue_data_in = " + fabric_mod_name + "_queue_data_in,\n" buf += " .queue_status = " + fabric_mod_name + "_queue_status,\n" buf += " .queue_tm_rsp = " + fabric_mod_name + "_queue_tm_rsp,\n" - buf += " .is_state_remove = " + fabric_mod_name + "_is_state_remove,\n" + buf += " .aborted_task = " + fabric_mod_name + "_aborted_task,\n" buf += " /*\n" buf += " * Setup function pointers for generic logic in target_core_fabric_configfs.c\n" buf += " */\n" @@ -428,7 +425,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " /*\n" buf += " * Register the top level struct config_item_type with TCM core\n" buf += " */\n" - buf += " fabric = target_fabric_configfs_init(THIS_MODULE, \"" + fabric_mod_name[4:] + "\");\n" + buf += " fabric = target_fabric_configfs_init(THIS_MODULE, \"" + fabric_mod_name + "\");\n" buf += " if (IS_ERR(fabric)) {\n" buf += " printk(KERN_ERR \"target_fabric_configfs_init() failed\\n\");\n" buf += " return PTR_ERR(fabric);\n" @@ -595,7 +592,7 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): if re.search('get_fabric_name', fo): buf += "char *" + fabric_mod_name + "_get_fabric_name(void)\n" buf += "{\n" - buf += " return \"" + fabric_mod_name[4:] + "\";\n" + buf += " return \"" + fabric_mod_name + "\";\n" buf += "}\n\n" bufi += "char *" + fabric_mod_name + "_get_fabric_name(void);\n" continue @@ -820,27 +817,6 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "}\n\n" bufi += "void " + fabric_mod_name + "_close_session(struct se_session *);\n" - if re.search('stop_session\)\(', fo): - buf += "void " + fabric_mod_name + "_stop_session(struct se_session *se_sess, int sess_sleep , int conn_sleep)\n" - buf += "{\n" - buf += " return;\n" - buf += "}\n\n" - bufi += "void " + fabric_mod_name + "_stop_session(struct se_session *, int, int);\n" - - if re.search('fall_back_to_erl0\)\(', fo): - buf += "void " + fabric_mod_name + "_reset_nexus(struct se_session *se_sess)\n" - buf += "{\n" - buf += " return;\n" - buf += "}\n\n" - bufi += "void " + fabric_mod_name + "_reset_nexus(struct se_session *);\n" - - if re.search('sess_logged_in\)\(', fo): - buf += "int " + fabric_mod_name + "_sess_logged_in(struct se_session *se_sess)\n" - buf += "{\n" - buf += " return 0;\n" - buf += "}\n\n" - bufi += "int " + fabric_mod_name + "_sess_logged_in(struct se_session *);\n" - if re.search('sess_get_index\)\(', fo): buf += "u32 " + fabric_mod_name + "_sess_get_index(struct se_session *se_sess)\n" buf += "{\n" @@ -898,19 +874,18 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): bufi += "int " + fabric_mod_name + "_queue_status(struct se_cmd *);\n" if re.search('queue_tm_rsp\)\(', fo): - buf += "int " + fabric_mod_name + "_queue_tm_rsp(struct se_cmd *se_cmd)\n" + buf += "void " + fabric_mod_name + "_queue_tm_rsp(struct se_cmd *se_cmd)\n" buf += "{\n" - buf += " return 0;\n" + buf += " return;\n" buf += "}\n\n" - bufi += "int " + fabric_mod_name + "_queue_tm_rsp(struct se_cmd *);\n" + bufi += "void " + fabric_mod_name + "_queue_tm_rsp(struct se_cmd *);\n" - if re.search('is_state_remove\)\(', fo): - buf += "int " + fabric_mod_name + "_is_state_remove(struct se_cmd *se_cmd)\n" + if re.search('aborted_task\)\(', fo): + buf += "void " + fabric_mod_name + "_aborted_task(struct se_cmd *se_cmd)\n" buf += "{\n" - buf += " return 0;\n" + buf += " return;\n" buf += "}\n\n" - bufi += "int " + fabric_mod_name + "_is_state_remove(struct se_cmd *);\n" - + bufi += "void " + fabric_mod_name + "_aborted_task(struct se_cmd *);\n" ret = p.write(buf) if ret: @@ -1018,11 +993,11 @@ def main(modname, proto_ident): tcm_mod_build_kbuild(fabric_mod_dir, fabric_mod_name) tcm_mod_build_kconfig(fabric_mod_dir, fabric_mod_name) - input = raw_input("Would you like to add " + fabric_mod_name + "to drivers/target/Makefile..? [yes,no]: ") + input = raw_input("Would you like to add " + fabric_mod_name + " to drivers/target/Makefile..? [yes,no]: ") if input == "yes" or input == "y": tcm_mod_add_kbuild(tcm_dir, fabric_mod_name) - input = raw_input("Would you like to add " + fabric_mod_name + "to drivers/target/Kconfig..? [yes,no]: ") + input = raw_input("Would you like to add " + fabric_mod_name + " to drivers/target/Kconfig..? [yes,no]: ") if input == "yes" or input == "y": tcm_mod_add_kconfig(tcm_dir, fabric_mod_name) diff --git a/Documentation/thermal/cpu-cooling-api.txt b/Documentation/thermal/cpu-cooling-api.txt index fca24c931ec8..753e47cc2e20 100644 --- a/Documentation/thermal/cpu-cooling-api.txt +++ b/Documentation/thermal/cpu-cooling-api.txt @@ -3,7 +3,7 @@ CPU cooling APIs How To Written by Amit Daniel Kachhap <amit.kachhap@linaro.org> -Updated: 12 May 2012 +Updated: 6 Jan 2015 Copyright (c) 2012 Samsung Electronics Co., Ltd(http://www.samsung.com) @@ -25,7 +25,18 @@ the user. The registration APIs returns the cooling device pointer. clip_cpus: cpumask of cpus where the frequency constraints will happen. -1.1.2 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev) +1.1.2 struct thermal_cooling_device *of_cpufreq_cooling_register( + struct device_node *np, const struct cpumask *clip_cpus) + + This interface function registers the cpufreq cooling device with + the name "thermal-cpufreq-%x" linking it with a device tree node, in + order to bind it via the thermal DT code. This api can support multiple + instances of cpufreq cooling devices. + + np: pointer to the cooling device device tree node + clip_cpus: cpumask of cpus where the frequency constraints will happen. + +1.1.3 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev) This interface function unregisters the "thermal-cpufreq-%x" cooling device. diff --git a/MAINTAINERS b/MAINTAINERS index ddb9ac8d32b3..aa97dffe59e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -624,6 +624,8 @@ L: dri-devel@lists.freedesktop.org T: git git://people.freedesktop.org/~gabbayo/linux.git S: Supported F: drivers/gpu/drm/amd/amdkfd/ +F: drivers/gpu/drm/amd/include/cik_structs.h +F: drivers/gpu/drm/amd/include/kgd_kfd_interface.h F: drivers/gpu/drm/radeon/radeon_kfd.c F: drivers/gpu/drm/radeon/radeon_kfd.h F: include/uapi/linux/kfd_ioctl.h @@ -724,15 +726,15 @@ F: include/uapi/linux/apm_bios.h F: drivers/char/apm-emulation.c APPLE BCM5974 MULTITOUCH DRIVER -M: Henrik Rydberg <rydberg@euromail.se> +M: Henrik Rydberg <rydberg@bitmath.org> L: linux-input@vger.kernel.org -S: Maintained +S: Odd fixes F: drivers/input/mouse/bcm5974.c APPLE SMC DRIVER -M: Henrik Rydberg <rydberg@euromail.se> +M: Henrik Rydberg <rydberg@bitmath.org> L: lm-sensors@lm-sensors.org -S: Maintained +S: Odd fixes F: drivers/hwmon/applesmc.c APPLETALK NETWORK LAYER @@ -754,13 +756,6 @@ L: linux-media@vger.kernel.org S: Maintained F: drivers/media/i2c/aptina-pll.* -ARASAN COMPACT FLASH PATA CONTROLLER -M: Viresh Kumar <viresh.linux@gmail.com> -L: linux-ide@vger.kernel.org -S: Maintained -F: include/linux/pata_arasan_cf_data.h -F: drivers/ata/pata_arasan_cf.c - ARC FRAMEBUFFER DRIVER M: Jaya Kumar <jayalk@intworks.biz> S: Maintained @@ -2259,6 +2254,7 @@ F: drivers/gpio/gpio-bt8xx.c BTRFS FILE SYSTEM M: Chris Mason <clm@fb.com> M: Josef Bacik <jbacik@fb.com> +M: David Sterba <dsterba@suse.cz> L: linux-btrfs@vger.kernel.org W: http://btrfs.wiki.kernel.org/ Q: http://patchwork.kernel.org/project/linux-btrfs/list/ @@ -2345,7 +2341,8 @@ CAN NETWORK LAYER M: Oliver Hartkopp <socketcan@hartkopp.net> L: linux-can@vger.kernel.org W: http://gitorious.org/linux-can -T: git git://gitorious.org/linux-can/linux-can-next.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next.git S: Maintained F: Documentation/networking/can.txt F: net/can/ @@ -2360,7 +2357,8 @@ M: Wolfgang Grandegger <wg@grandegger.com> M: Marc Kleine-Budde <mkl@pengutronix.de> L: linux-can@vger.kernel.org W: http://gitorious.org/linux-can -T: git git://gitorious.org/linux-can/linux-can-next.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next.git S: Maintained F: drivers/net/can/ F: include/linux/can/dev.h @@ -3182,7 +3180,7 @@ L: dmaengine@vger.kernel.org Q: https://patchwork.kernel.org/project/linux-dmaengine/list/ S: Maintained F: drivers/dma/ -F: include/linux/dma* +F: include/linux/dmaengine.h F: Documentation/dmaengine/ T: git git://git.infradead.org/users/vkoul/slave-dma.git @@ -4748,7 +4746,7 @@ S: Supported F: drivers/scsi/ipr.* IBM Power Virtual Ethernet Device Driver -M: Santiago Leon <santil@linux.vnet.ibm.com> +M: Thomas Falcon <tlfalcon@linux.vnet.ibm.com> L: netdev@vger.kernel.org S: Supported F: drivers/net/ethernet/ibm/ibmveth.* @@ -4929,7 +4927,6 @@ F: include/uapi/linux/inotify.h INPUT (KEYBOARD, MOUSE, JOYSTICK, TOUCHSCREEN) DRIVERS M: Dmitry Torokhov <dmitry.torokhov@gmail.com> -M: Dmitry Torokhov <dtor@mail.ru> L: linux-input@vger.kernel.org Q: http://patchwork.kernel.org/project/linux-input/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git @@ -4940,10 +4937,10 @@ F: include/uapi/linux/input.h F: include/linux/input/ INPUT MULTITOUCH (MT) PROTOCOL -M: Henrik Rydberg <rydberg@euromail.se> +M: Henrik Rydberg <rydberg@bitmath.org> L: linux-input@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/rydberg/input-mt.git -S: Maintained +S: Odd fixes F: Documentation/input/multi-touch-protocol.txt F: drivers/input/input-mt.c K: \b(ABS|SYN)_MT_ @@ -5279,6 +5276,15 @@ W: www.open-iscsi.org Q: http://patchwork.kernel.org/project/linux-rdma/list/ F: drivers/infiniband/ulp/iser/ +ISCSI EXTENSIONS FOR RDMA (ISER) TARGET +M: Sagi Grimberg <sagig@mellanox.com> +T: git git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending.git master +L: linux-rdma@vger.kernel.org +L: target-devel@vger.kernel.org +S: Supported +W: http://www.linux-iscsi.org +F: drivers/infiniband/ulp/isert + ISDN SUBSYSTEM M: Karsten Keil <isdn@linux-pingi.de> L: isdn4linux@listserv.isdn4linux.de (subscribers-only) @@ -5693,6 +5699,49 @@ F: drivers/lguest/ F: include/linux/lguest*.h F: tools/lguest/ +LIBATA SUBSYSTEM (Serial and Parallel ATA drivers) +M: Tejun Heo <tj@kernel.org> +L: linux-ide@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git +S: Maintained +F: drivers/ata/ +F: include/linux/ata.h +F: include/linux/libata.h + +LIBATA PATA ARASAN COMPACT FLASH CONTROLLER +M: Viresh Kumar <viresh.linux@gmail.com> +L: linux-ide@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git +S: Maintained +F: include/linux/pata_arasan_cf_data.h +F: drivers/ata/pata_arasan_cf.c + +LIBATA PATA DRIVERS +M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> +M: Tejun Heo <tj@kernel.org> +L: linux-ide@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git +S: Maintained +F: drivers/ata/pata_*.c +F: drivers/ata/ata_generic.c + +LIBATA SATA AHCI PLATFORM devices support +M: Hans de Goede <hdegoede@redhat.com> +M: Tejun Heo <tj@kernel.org> +L: linux-ide@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git +S: Maintained +F: drivers/ata/ahci_platform.c +F: drivers/ata/libahci_platform.c +F: include/linux/ahci_platform.h + +LIBATA SATA PROMISE TX2/TX4 CONTROLLER DRIVER +M: Mikael Pettersson <mikpelinux@gmail.com> +L: linux-ide@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git +S: Maintained +F: drivers/ata/sata_promise.* + LIBLOCKDEP M: Sasha Levin <sasha.levin@oracle.com> S: Maintained @@ -7399,6 +7448,7 @@ F: drivers/crypto/picoxcell* PIN CONTROL SUBSYSTEM M: Linus Walleij <linus.walleij@linaro.org> L: linux-gpio@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git S: Maintained F: drivers/pinctrl/ F: include/linux/pinctrl/ @@ -7566,12 +7616,6 @@ W: http://wireless.kernel.org/en/users/Drivers/p54 S: Obsolete F: drivers/net/wireless/prism54/ -PROMISE SATA TX2/TX4 CONTROLLER LIBATA DRIVER -M: Mikael Pettersson <mikpelinux@gmail.com> -L: linux-ide@vger.kernel.org -S: Maintained -F: drivers/ata/sata_promise.* - PS3 NETWORK SUPPORT M: Geoff Levand <geoff@infradead.org> L: netdev@vger.kernel.org @@ -7737,8 +7781,7 @@ F: Documentation/scsi/LICENSE.qla2xxx F: drivers/scsi/qla2xxx/ QLOGIC QLA4XXX iSCSI DRIVER -M: Vikas Chaudhary <vikas.chaudhary@qlogic.com> -M: iscsi-driver@qlogic.com +M: QLogic-Storage-Upstream@qlogic.com L: linux-scsi@vger.kernel.org S: Supported F: Documentation/scsi/LICENSE.qla4xxx @@ -8546,25 +8589,6 @@ S: Maintained F: drivers/misc/phantom.c F: include/uapi/linux/phantom.h -SERIAL ATA (SATA) SUBSYSTEM -M: Tejun Heo <tj@kernel.org> -L: linux-ide@vger.kernel.org -T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git -S: Supported -F: drivers/ata/ -F: include/linux/ata.h -F: include/linux/libata.h - -SERIAL ATA AHCI PLATFORM devices support -M: Hans de Goede <hdegoede@redhat.com> -M: Tejun Heo <tj@kernel.org> -L: linux-ide@vger.kernel.org -T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git -S: Supported -F: drivers/ata/ahci_platform.c -F: drivers/ata/libahci_platform.c -F: include/linux/ahci_platform.h - SERVER ENGINES 10Gbps iSCSI - BladeEngine 2 DRIVER M: Jayamohan Kallickal <jayamohan.kallickal@emulex.com> L: linux-scsi@vger.kernel.org @@ -9533,7 +9557,8 @@ F: drivers/platform/x86/thinkpad_acpi.c TI BANDGAP AND THERMAL DRIVER M: Eduardo Valentin <edubezval@gmail.com> L: linux-pm@vger.kernel.org -S: Supported +L: linux-omap@vger.kernel.org +S: Maintained F: drivers/thermal/ti-soc-thermal/ TI CLOCK DRIVER @@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 19 SUBLEVEL = 0 -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc5 NAME = Diseased Newt # *DOCUMENTATION* @@ -391,6 +391,7 @@ USERINCLUDE := \ # Needed to be compatible with the O= option LINUXINCLUDE := \ -I$(srctree)/arch/$(hdr-arch)/include \ + -Iarch/$(hdr-arch)/include/generated/uapi \ -Iarch/$(hdr-arch)/include/generated \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ -Iinclude \ diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 1467750e3377..e8c6c600a5b6 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -953,6 +953,8 @@ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fb>; + clocks = <&lcd_clk>, <&lcd_clk>; + clock-names = "lcdc_clk", "hclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts index 28e7e2060c33..a98ac1bd8f65 100644 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -65,6 +65,8 @@ }; &sdhci2 { + broken-cd; + bus-width = <8>; non-removable; status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 35253c947a7c..e2f61f27944e 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -83,7 +83,8 @@ compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&chip CLKID_SDIO1XIN>; + clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; + clock-names = "io", "core"; status = "disabled"; }; @@ -348,36 +349,6 @@ interrupt-parent = <&gic>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; }; - - gpio4: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - gpio5: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; }; chip: chip-control@ea0000 { @@ -466,6 +437,21 @@ ranges = <0 0xfc0000 0x10000>; interrupt-parent = <&sic>; + sm_gpio1: gpio@5000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-port@5 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + }; + }; + i2c2: i2c@7000 { compatible = "snps,designware-i2c"; #address-cells = <1>; @@ -516,6 +502,21 @@ status = "disabled"; }; + sm_gpio0: gpio@c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xc000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-port@4 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + }; + }; + sysctrl: pin-controller@d000 { compatible = "marvell,berlin2q-system-ctrl"; reg = <0xd000 0x100>; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 10b725c7bfc0..ad4118f7e1a6 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -499,23 +499,23 @@ }; partition@5 { label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00010000>; + reg = <0x00140000 0x00080000>; }; partition@6 { label = "QSPI.u-boot-env"; - reg = <0x00150000 0x00010000>; + reg = <0x001c0000 0x00010000>; }; partition@7 { label = "QSPI.u-boot-env.backup1"; - reg = <0x00160000 0x0010000>; + reg = <0x001d0000 0x0010000>; }; partition@8 { label = "QSPI.kernel"; - reg = <0x00170000 0x0800000>; + reg = <0x001e0000 0x0800000>; }; partition@9 { label = "QSPI.file-system"; - reg = <0x00970000 0x01690000>; + reg = <0x009e0000 0x01620000>; }; }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 0a229fcd7acf..d75c89d7666a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -736,7 +736,7 @@ dp_phy: video-phy@10040720 { compatible = "samsung,exynos5250-dp-video-phy"; - reg = <0x10040720 4>; + samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; }; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index aa7a7d727a7e..db2c1c4cd900 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -372,3 +372,7 @@ &usbdrd_dwc3_1 { dr_mode = "host"; }; + +&cci { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 517e50f6760b..6d38f8bfd0e6 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -120,7 +120,7 @@ }; }; - cci@10d20000 { + cci: cci@10d20000 { compatible = "arm,cci-400"; #address-cells = <1>; #size-cells = <1>; @@ -503,8 +503,8 @@ }; dp_phy: video-phy@10040728 { - compatible = "samsung,exynos5250-dp-video-phy"; - reg = <0x10040728 4>; + compatible = "samsung,exynos5420-dp-video-phy"; + samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; }; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 58d3c3cf2923..d238676a9107 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -162,7 +162,7 @@ #size-cells = <0>; compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x43fa4000 0x4000>; - clocks = <&clks 62>, <&clks 62>; + clocks = <&clks 78>, <&clks 78>; clock-names = "ipg", "per"; interrupts = <14>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 56569cecaa78..649befeb2cf9 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -127,24 +127,12 @@ #address-cells = <1>; #size-cells = <0>; - reg_usbh1_vbus: regulator@0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1reg>; - reg = <0>; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator@1 { + reg_hub_reset: regulator@0 { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotgreg>; - reg = <1>; - regulator-name = "usbotg_vbus"; + reg = <0>; + regulator-name = "hub_reset"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; @@ -176,6 +164,7 @@ reg = <0>; clocks = <&clks IMX5_CLK_DUMMY>; clock-names = "main_clk"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; }; }; }; @@ -419,7 +408,7 @@ &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usbh1_vbus>; + vbus-supply = <®_hub_reset>; fsl,usbphy = <&usbh1phy>; phy_type = "ulpi"; status = "okay"; @@ -429,7 +418,6 @@ dr_mode = "otg"; disable-over-current; phy_type = "utmi_wide"; - vbus-supply = <®_usbotg_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 4fc03b7f1cee..2109d0763c1b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -335,8 +335,8 @@ vpu: vpu@02040000 { compatible = "cnm,coda960"; reg = <0x02040000 0x3c000>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, - <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "bit", "jpeg"; clocks = <&clks IMX6QDL_CLK_VPU_AXI>, <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 1e6e5cc1c14c..8c1febd7e3f2 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -159,13 +159,28 @@ pinctrl-0 = <&pinctrl_enet1>; phy-supply = <®_enet_3v3>; phy-mode = "rgmii"; + phy-handle = <ðphy1>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + + ethphy2: ethernet-phy@1 { + reg = <1>; + }; + }; }; &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rgmii"; + phy-handle = <ðphy2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 657da14cb4b5..c70bb27ac65a 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -142,6 +142,7 @@ scfg: scfg@1570000 { compatible = "fsl,ls1021a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; + big-endian; }; clockgen: clocking@1ee1000 { diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 53f3ca064140..b550c41b46f1 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -700,11 +700,9 @@ }; }; + /* Ethernet is on some early development boards and qemu */ ethernet@gpmc { compatible = "smsc,lan91c94"; - - status = "disabled"; - interrupt-parent = <&gpio2>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 3e067dd65d0c..6194d673e80b 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -155,6 +155,15 @@ }; &pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + backlight { bl_en: bl-en { rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -173,6 +182,27 @@ }; }; + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on EVB board so bump up to 8ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + }; + usb { host_vbus_drv: host-vbus-drv { rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 49c10d33df30..77e03655aca3 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -176,7 +176,7 @@ "Headphone Jack", "HPOUTR", "IN2L", "Line In Jack", "IN2R", "Line In Jack", - "MICBIAS", "IN1L", + "Mic", "MICBIAS", "IN1L", "Mic"; atmel,ssc-controller = <&ssc0>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 1b0f30c2c4a5..b94995d1889f 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1008,7 +1008,7 @@ pit: timer@fc068630 { compatible = "atmel,at91sam9260-pit"; - reg = <0xfc068630 0xf>; + reg = <0xfc068630 0x10>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; clocks = <&h32ck>; }; diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index a8c00ee7522a..3d0b8755caee 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -25,11 +25,11 @@ stmpe2401_1 { stmpe2401_1_nhk_mode: stmpe2401_1_nhk { nhk_cfg1 { - ste,pins = "GPIO76_B20"; // IRQ line + pins = "GPIO76_B20"; // IRQ line ste,input = <0>; }; nhk_cfg2 { - ste,pins = "GPIO77_B8"; // reset line + pins = "GPIO77_B8"; // reset line ste,output = <1>; }; }; @@ -37,11 +37,11 @@ stmpe2401_2 { stmpe2401_2_nhk_mode: stmpe2401_2_nhk { nhk_cfg1 { - ste,pins = "GPIO78_A8"; // IRQ line + pins = "GPIO78_A8"; // IRQ line ste,input = <0>; }; nhk_cfg2 { - ste,pins = "GPIO79_C9"; // reset line + pins = "GPIO79_C9"; // reset line ste,output = <1>; }; }; diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index a0f762159cb2..f2b64b1b00fa 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -129,13 +129,28 @@ &fec0 { phy-mode = "rmii"; + phy-handle = <ðphy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec0>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + }; }; &fec1 { phy-mode = "rmii"; + phy-handle = <ðphy1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; status = "okay"; diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 5ef14de00a29..3d0c5d65c741 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -84,7 +84,8 @@ CONFIG_DEBUG_GPIO=y CONFIG_POWER_SUPPLY=y CONFIG_BATTERY_SBS=y CONFIG_CHARGER_TPS65090=y -# CONFIG_HWMON is not set +CONFIG_HWMON=y +CONFIG_SENSORS_LM90=y CONFIG_THERMAL=y CONFIG_EXYNOS_THERMAL=y CONFIG_EXYNOS_THERMAL_CORE=y @@ -109,11 +110,26 @@ CONFIG_REGULATOR_S2MPA01=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y +CONFIG_DRM=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PTN3460=y +CONFIG_DRM_PS8622=y +CONFIG_DRM_EXYNOS=y +CONFIG_DRM_EXYNOS_FIMD=y +CONFIG_DRM_EXYNOS_DP=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_SIMPLE=y CONFIG_FB=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_SIMPLE=y CONFIG_EXYNOS_VIDEO=y CONFIG_EXYNOS_MIPI_DSI=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FONTS=y CONFIG_FONT_7x14=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c2c3a852af9f..667d9d52aa01 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -68,7 +68,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_GENERIC_CPUFREQ_CPU0=y +CONFIG_CPUFREQ_DT=y # CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set CONFIG_CPU_IDLE=y CONFIG_BINFMT_MISC=y diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h index 705bb7620673..0c3f5a0dafd3 100644 --- a/arch/arm/include/uapi/asm/unistd.h +++ b/arch/arm/include/uapi/asm/unistd.h @@ -413,6 +413,7 @@ #define __NR_getrandom (__NR_SYSCALL_BASE+384) #define __NR_memfd_create (__NR_SYSCALL_BASE+385) #define __NR_bpf (__NR_SYSCALL_BASE+386) +#define __NR_execveat (__NR_SYSCALL_BASE+387) /* * The following SWIs are ARM private. diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index e51833f8cc38..05745eb838c5 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -396,6 +396,7 @@ CALL(sys_getrandom) /* 385 */ CALL(sys_memfd_create) CALL(sys_bpf) + CALL(sys_execveat) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/perf_regs.c b/arch/arm/kernel/perf_regs.c index 6e4379c67cbc..592dda3f21ff 100644 --- a/arch/arm/kernel/perf_regs.c +++ b/arch/arm/kernel/perf_regs.c @@ -28,3 +28,11 @@ u64 perf_reg_abi(struct task_struct *task) { return PERF_SAMPLE_REGS_ABI_32; } + +void perf_get_regs_user(struct perf_regs *regs_user, + struct pt_regs *regs, + struct pt_regs *regs_user_copy) +{ + regs_user->regs = task_pt_regs(current); + regs_user->abi = perf_reg_abi(current); +} diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c index 8fb9ef5333f1..97f7367d32b8 100644 --- a/arch/arm/mach-at91/board-dt-sama5.c +++ b/arch/arm/mach-at91/board-dt-sama5.c @@ -17,6 +17,7 @@ #include <linux/of_platform.h> #include <linux/phy.h> #include <linux/clk-provider.h> +#include <linux/phy.h> #include <asm/setup.h> #include <asm/irq.h> @@ -26,8 +27,25 @@ #include "generic.h" +static int ksz8081_phy_fixup(struct phy_device *phy) +{ + int value; + + value = phy_read(phy, 0x16); + value &= ~0x20; + phy_write(phy, 0x16, value); + + return 0; +} + static void __init sama5_dt_device_init(void) { + if (of_machine_is_compatible("atmel,sama5d4ek") && + IS_ENABLED(CONFIG_PHYLIB)) { + phy_register_fixup_for_id("fc028000.etherne:00", + ksz8081_phy_fixup); + } + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 5951660d1bd2..2daef619d053 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) post_div_table[1].div = 1; post_div_table[2].div = 1; video_div_table[1].div = 1; - video_div_table[2].div = 1; + video_div_table[3].div = 1; } clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 17354a11356f..5a3e5a159e70 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); + clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); } diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 608079a1aba6..b61c049f92d6 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -77,6 +77,24 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP3 +/* Some boards need board name for legacy userspace in /proc/cpuinfo */ +static const char *const n900_boards_compat[] __initconst = { + "nokia,omap3-n900", + NULL, +}; + +DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board") + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3430_init_early, + .init_machine = omap_generic_init, + .init_late = omap3_init_late, + .init_time = omap3_sync32k_timer_init, + .dt_compat = n900_boards_compat, + .restart = omap3xxx_restart, +MACHINE_END + +/* Generic omap3 boards, most boards can use these */ static const char *const omap3_boards_compat[] __initconst = { "ti,omap3430", "ti,omap3", diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 377eea849e7b..db57741c9c8a 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -249,6 +249,7 @@ extern void omap4_cpu_die(unsigned int cpu); extern struct smp_operations omap4_smp_ops; extern void omap5_secondary_startup(void); +extern void omap5_secondary_hyp_startup(void); #endif #if defined(CONFIG_SMP) && defined(CONFIG_PM) diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index a3c013345c45..a80ac2d70bb1 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -286,6 +286,10 @@ #define OMAP5XXX_CONTROL_STATUS 0x134 #define OMAP5_DEVICETYPE_MASK (0x7 << 6) +/* DRA7XX CONTROL CORE BOOTSTRAP */ +#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4 +#define DRA7_SPEEDSELECT_MASK (0x3 << 8) + /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 4993d4bfe9b2..6d1dffca6c7b 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -22,6 +22,7 @@ /* Physical address needed since MMU not enabled yet on secondary core */ #define AUX_CORE_BOOT0_PA 0x48281800 +#define API_HYP_ENTRY 0x102 /* * OMAP5 specific entry point for secondary CPU to jump from ROM @@ -41,6 +42,26 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 b secondary_startup ENDPROC(omap5_secondary_startup) /* + * Same as omap5_secondary_startup except we call into the ROM to + * enable HYP mode first. This is called instead of + * omap5_secondary_startup if the primary CPU was put into HYP mode by + * the boot loader. + */ +ENTRY(omap5_secondary_hyp_startup) +wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 + ldr r0, [r2] + mov r0, r0, lsr #5 + mrc p15, 0, r4, c0, c0, 5 + and r4, r4, #0x0f + cmp r0, r4 + bne wait_2 + ldr r12, =API_HYP_ENTRY + adr r0, hyp_boot + smc #0 +hyp_boot: + b secondary_startup +ENDPROC(omap5_secondary_hyp_startup) +/* * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which * secondary core is held until we're ready for it to initialise. diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 256e84ef0f67..5305ec7341ec 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -22,6 +22,7 @@ #include <linux/irqchip/arm-gic.h> #include <asm/smp_scu.h> +#include <asm/virt.h> #include "omap-secure.h" #include "omap-wakeupgen.h" @@ -227,8 +228,16 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) if (omap_secure_apis_support()) omap_auxcoreboot_addr(virt_to_phys(startup_addr)); else - writel_relaxed(virt_to_phys(omap5_secondary_startup), - base + OMAP_AUX_CORE_BOOT_1); + /* + * If the boot CPU is in HYP mode then start secondary + * CPU in HYP mode as well. + */ + if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE) + writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup), + base + OMAP_AUX_CORE_BOOT_1); + else + writel_relaxed(virt_to_phys(omap5_secondary_startup), + base + OMAP_AUX_CORE_BOOT_1); } diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 4f61148ec168..7d45c84c69ba 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -54,6 +54,7 @@ #include "soc.h" #include "common.h" +#include "control.h" #include "powerdomain.h" #include "omap-secure.h" @@ -496,7 +497,8 @@ static void __init realtime_counter_init(void) void __iomem *base; static struct clk *sys_clk; unsigned long rate; - unsigned int reg, num, den; + unsigned int reg; + unsigned long long num, den; base = ioremap(REALTIME_COUNTER_BASE, SZ_32); if (!base) { @@ -511,13 +513,42 @@ static void __init realtime_counter_init(void) } rate = clk_get_rate(sys_clk); + + if (soc_is_dra7xx()) { + /* + * Errata i856 says the 32.768KHz crystal does not start at + * power on, so the CPU falls back to an emulated 32KHz clock + * based on sysclk / 610 instead. This causes the master counter + * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 + * (OR sysclk * 75 / 244) + * + * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. + * Of course any board built without a populated 32.768KHz + * crystal would also need this fix even if the CPU is fixed + * later. + * + * Either case can be detected by using the two speedselect bits + * If they are not 0, then the 32.768KHz clock driving the + * coarse counter that corrects the fine counter every time it + * ticks is actually rate/610 rather than 32.768KHz and we + * should compensate to avoid the 570ppm (at 20MHz, much worse + * at other rates) too fast system time. + */ + reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); + if (reg & DRA7_SPEEDSELECT_MASK) { + num = 75; + den = 244; + goto sysclk1_based; + } + } + /* Numerator/denumerator values refer TRM Realtime Counter section */ switch (rate) { - case 1200000: + case 12000000: num = 64; den = 125; break; - case 1300000: + case 13000000: num = 768; den = 1625; break; @@ -529,11 +560,11 @@ static void __init realtime_counter_init(void) num = 192; den = 625; break; - case 2600000: + case 26000000: num = 384; den = 1625; break; - case 2700000: + case 27000000: num = 256; den = 1125; break; @@ -545,6 +576,7 @@ static void __init realtime_counter_init(void) break; } +sysclk1_based: /* Program numerator and denumerator registers */ reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & NUMERATOR_DENUMERATOR_MASK; @@ -556,7 +588,7 @@ static void __init realtime_counter_init(void) reg |= den; writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); - arch_timer_freq = (rate / den) * num; + arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); set_cntfreq(); iounmap(base); diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index d226b71d21d5..a611f4852582 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -19,11 +19,37 @@ #include <linux/init.h> #include <linux/of_platform.h> #include <linux/irqchip.h> +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/hardware/cache-l2x0.h> #include "core.h" +#define RK3288_GRF_SOC_CON0 0x244 + +static void __init rockchip_timer_init(void) +{ + if (of_machine_is_compatible("rockchip,rk3288")) { + struct regmap *grf; + + /* + * Disable auto jtag/sdmmc switching that causes issues + * with the mmc controllers making them unreliable + */ + grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf"); + if (!IS_ERR(grf)) + regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000); + else + pr_err("rockchip: could not get grf syscon\n"); + } + + of_clk_init(NULL); + clocksource_of_init(); +} + static void __init rockchip_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -42,6 +68,7 @@ static const char * const rockchip_board_dt_compat[] = { DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, + .init_time = rockchip_timer_init, .dt_compat = rockchip_board_dt_compat, .init_machine = rockchip_dt_init, MACHINE_END diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 79ad93dfdae4..d191cf419731 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -800,7 +800,14 @@ void __init r8a7740_init_irq_of(void) void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); +#ifdef CONFIG_ARCH_SHMOBILE_LEGACY + void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); + void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); + + gic_init(0, 29, gic_dist_base, gic_cpu_base); +#else irqchip_init(); +#endif /* route signals to GIC */ iowrite32(0x0, pfc_inta_ctrl); diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 93ebe3430bfe..fb5e1bb34be8 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -595,6 +595,7 @@ static struct platform_device ipmmu_device = { static struct renesas_intc_irqpin_config irqpin0_platform_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ + .control_parent = true, }; static struct resource irqpin0_resources[] = { @@ -656,6 +657,7 @@ static struct platform_device irqpin1_device = { static struct renesas_intc_irqpin_config irqpin2_platform_data = { .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ + .control_parent = true, }; static struct resource irqpin2_resources[] = { @@ -686,6 +688,7 @@ static struct platform_device irqpin2_device = { static struct renesas_intc_irqpin_config irqpin3_platform_data = { .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ + .control_parent = true, }; static struct resource irqpin3_resources[] = { diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c index 59424937e52b..9fe8e241335c 100644 --- a/arch/arm/mm/dump.c +++ b/arch/arm/mm/dump.c @@ -220,9 +220,6 @@ static void note_page(struct pg_state *st, unsigned long addr, unsigned level, u static const char units[] = "KMGTPE"; u64 prot = val & pg_level[level].mask; - if (addr < USER_PGTABLES_CEILING) - return; - if (!st->level) { st->level = level; st->current_prot = prot; @@ -308,15 +305,13 @@ static void walk_pgd(struct seq_file *m) pgd_t *pgd = swapper_pg_dir; struct pg_state st; unsigned long addr; - unsigned i, pgdoff = USER_PGTABLES_CEILING / PGDIR_SIZE; + unsigned i; memset(&st, 0, sizeof(st)); st.seq = m; st.marker = address_markers; - pgd += pgdoff; - - for (i = pgdoff; i < PTRS_PER_PGD; i++, pgd++) { + for (i = 0; i < PTRS_PER_PGD; i++, pgd++) { addr = i * PGDIR_SIZE; if (!pgd_none(*pgd)) { walk_pud(&st, pgd, addr); diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 98ad9c79ea0e..2495c8cb47ba 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -658,8 +658,8 @@ static struct section_perm ro_perms[] = { .start = (unsigned long)_stext, .end = (unsigned long)__init_begin, #ifdef CONFIG_ARM_LPAE - .mask = ~PMD_SECT_RDONLY, - .prot = PMD_SECT_RDONLY, + .mask = ~L_PMD_SECT_RDONLY, + .prot = L_PMD_SECT_RDONLY, #else .mask = ~(PMD_SECT_APX | PMD_SECT_AP_WRITE), .prot = PMD_SECT_APX | PMD_SECT_AP_WRITE, diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index cda7c40999b6..4e6ef896c619 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -1329,8 +1329,8 @@ static void __init kmap_init(void) static void __init map_lowmem(void) { struct memblock_region *reg; - unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE); - unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); + phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE); + phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); /* Map all the lowmem memory banks. */ for_each_memblock(memory, reg) { diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index b1fa4e614718..fbe0ca31a99c 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -21,6 +21,7 @@ #include <asm/barrier.h> +#include <linux/bug.h> #include <linux/init.h> #include <linux/types.h> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index ace70682499b..8e797b2fcc01 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -39,6 +39,7 @@ struct cpuinfo_arm64 { u64 reg_id_aa64pfr0; u64 reg_id_aa64pfr1; + u32 reg_id_dfr0; u32 reg_id_isar0; u32 reg_id_isar1; u32 reg_id_isar2; @@ -51,6 +52,10 @@ struct cpuinfo_arm64 { u32 reg_id_mmfr3; u32 reg_id_pfr0; u32 reg_id_pfr1; + + u32 reg_mvfr0; + u32 reg_mvfr1; + u32 reg_mvfr2; }; DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data); diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index 8127e45e2637..865a7e28ea2d 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -41,6 +41,8 @@ void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) { vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; + if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) + vcpu->arch.hcr_el2 &= ~HCR_RW; } static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 286b1bec547c..f9be30ea1cbd 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -31,6 +31,7 @@ #include <asm/fpsimd.h> #include <asm/hw_breakpoint.h> +#include <asm/pgtable-hwdef.h> #include <asm/ptrace.h> #include <asm/types.h> @@ -123,9 +124,6 @@ struct task_struct; /* Free all resources held by a thread. */ extern void release_thread(struct task_struct *); -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while (0) - unsigned long get_wchan(struct task_struct *p); #define cpu_relax() barrier() diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h index 49c9aefd24a5..23e9432ac112 100644 --- a/arch/arm64/include/asm/unistd.h +++ b/arch/arm64/include/asm/unistd.h @@ -44,7 +44,7 @@ #define __ARM_NR_compat_cacheflush (__ARM_NR_COMPAT_BASE+2) #define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE+5) -#define __NR_compat_syscalls 386 +#define __NR_compat_syscalls 388 #endif #define __ARCH_WANT_SYS_CLONE diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h index 8893cebcea5b..27224426e0bf 100644 --- a/arch/arm64/include/asm/unistd32.h +++ b/arch/arm64/include/asm/unistd32.h @@ -795,3 +795,5 @@ __SYSCALL(__NR_getrandom, sys_getrandom) __SYSCALL(__NR_memfd_create, sys_memfd_create) #define __NR_bpf 386 __SYSCALL(__NR_bpf, sys_bpf) +#define __NR_execveat 387 +__SYSCALL(__NR_execveat, compat_sys_execveat) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 57b641747534..07d435cf2eea 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -147,6 +147,7 @@ static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur) * If we have AArch32, we care about 32-bit features for compat. These * registers should be RES0 otherwise. */ + diff |= CHECK(id_dfr0, boot, cur, cpu); diff |= CHECK(id_isar0, boot, cur, cpu); diff |= CHECK(id_isar1, boot, cur, cpu); diff |= CHECK(id_isar2, boot, cur, cpu); @@ -165,6 +166,10 @@ static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur) diff |= CHECK(id_pfr0, boot, cur, cpu); diff |= CHECK(id_pfr1, boot, cur, cpu); + diff |= CHECK(mvfr0, boot, cur, cpu); + diff |= CHECK(mvfr1, boot, cur, cpu); + diff |= CHECK(mvfr2, boot, cur, cpu); + /* * Mismatched CPU features are a recipe for disaster. Don't even * pretend to support them. @@ -189,6 +194,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); + info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); @@ -202,6 +208,10 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); + info->reg_mvfr0 = read_cpuid(MVFR0_EL1); + info->reg_mvfr1 = read_cpuid(MVFR1_EL1); + info->reg_mvfr2 = read_cpuid(MVFR2_EL1); + cpuinfo_detect_icache_policy(info); check_local_cpu_errata(); diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c index 6fac253bc783..2bb4347d0edf 100644 --- a/arch/arm64/kernel/efi.c +++ b/arch/arm64/kernel/efi.c @@ -326,6 +326,7 @@ void __init efi_idmap_init(void) /* boot time idmap_pg_dir is incomplete, so fill in missing parts */ efi_setup_idmap(); + early_memunmap(memmap.map, memmap.map_end - memmap.map); } static int __init remap_region(efi_memory_desc_t *md, void **new) @@ -380,7 +381,6 @@ static int __init arm64_enter_virtual_mode(void) } mapsize = memmap.map_end - memmap.map; - early_memunmap(memmap.map, mapsize); if (efi_runtime_disabled()) { pr_info("EFI runtime services will be disabled.\n"); diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c index fd027b101de5..9b6f71db2709 100644 --- a/arch/arm64/kernel/module.c +++ b/arch/arm64/kernel/module.c @@ -25,6 +25,7 @@ #include <linux/mm.h> #include <linux/moduleloader.h> #include <linux/vmalloc.h> +#include <asm/alternative.h> #include <asm/insn.h> #include <asm/sections.h> diff --git a/arch/arm64/kernel/perf_regs.c b/arch/arm64/kernel/perf_regs.c index 6762ad705587..3f62b35fb6f1 100644 --- a/arch/arm64/kernel/perf_regs.c +++ b/arch/arm64/kernel/perf_regs.c @@ -50,3 +50,11 @@ u64 perf_reg_abi(struct task_struct *task) else return PERF_SAMPLE_REGS_ABI_64; } + +void perf_get_regs_user(struct perf_regs *regs_user, + struct pt_regs *regs, + struct pt_regs *regs_user_copy) +{ + regs_user->regs = task_pt_regs(current); + regs_user->abi = perf_reg_abi(current); +} diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index b80991166754..20fe2932ad0c 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -402,6 +402,7 @@ void __init setup_arch(char **cmdline_p) request_standard_resources(); efi_idmap_init(); + early_ioremap_reset(); unflatten_device_tree(); diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c index 4f93c67e63de..14944e5b28da 100644 --- a/arch/arm64/kernel/smp_spin_table.c +++ b/arch/arm64/kernel/smp_spin_table.c @@ -25,6 +25,7 @@ #include <asm/cacheflush.h> #include <asm/cpu_ops.h> #include <asm/cputype.h> +#include <asm/io.h> #include <asm/smp_plat.h> extern void secondary_holding_pen(void); diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index fbe909fb0a1a..c3ca89c27c6b 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.S @@ -1014,6 +1014,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa) * Instead, we invalidate Stage-2 for this IPA, and the * whole of Stage-1. Weep... */ + lsr x1, x1, #12 tlbi ipas2e1is, x1 /* * We have to ensure completion of the invalidation at Stage-2, diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 70a7816535cd..0b4326578985 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -90,7 +90,6 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) if (!cpu_has_32bit_el1()) return -EINVAL; cpu_reset = &default_regs_reset32; - vcpu->arch.hcr_el2 &= ~HCR_RW; } else { cpu_reset = &default_regs_reset; } diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index bac492c12fcc..c95464a33f36 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -335,14 +335,8 @@ static int keep_initrd; void free_initrd_mem(unsigned long start, unsigned long end) { - if (!keep_initrd) { - if (start == initrd_start) - start = round_down(start, PAGE_SIZE); - if (end == initrd_end) - end = round_up(end, PAGE_SIZE); - + if (!keep_initrd) free_reserved_area((void *)start, (void *)end, 0, "initrd"); - } } static int __init keepinitrd_setup(char *__unused) diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 6f4bac969bf7..23eada79439c 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -7,6 +7,7 @@ */ #include <linux/device.h> +#include <linux/delay.h> #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c index 615ef81def49..e795cb848154 100644 --- a/arch/ia64/kernel/acpi.c +++ b/arch/ia64/kernel/acpi.c @@ -893,13 +893,13 @@ static int _acpi_map_lsapic(acpi_handle handle, int physid, int *pcpu) } /* wrapper to silence section mismatch warning */ -int __ref acpi_map_lsapic(acpi_handle handle, int physid, int *pcpu) +int __ref acpi_map_cpu(acpi_handle handle, int physid, int *pcpu) { return _acpi_map_lsapic(handle, physid, pcpu); } -EXPORT_SYMBOL(acpi_map_lsapic); +EXPORT_SYMBOL(acpi_map_cpu); -int acpi_unmap_lsapic(int cpu) +int acpi_unmap_cpu(int cpu) { ia64_cpu_to_sapicid[cpu] = -1; set_cpu_present(cpu, false); @@ -910,8 +910,7 @@ int acpi_unmap_lsapic(int cpu) return (0); } - -EXPORT_SYMBOL(acpi_unmap_lsapic); +EXPORT_SYMBOL(acpi_unmap_cpu); #endif /* CONFIG_ACPI_HOTPLUG_CPU */ #ifdef CONFIG_ACPI_NUMA diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h index 75e75d7b1702..244e0dbe45db 100644 --- a/arch/m68k/include/asm/unistd.h +++ b/arch/m68k/include/asm/unistd.h @@ -4,7 +4,7 @@ #include <uapi/asm/unistd.h> -#define NR_syscalls 355 +#define NR_syscalls 356 #define __ARCH_WANT_OLD_READDIR #define __ARCH_WANT_OLD_STAT diff --git a/arch/m68k/include/uapi/asm/unistd.h b/arch/m68k/include/uapi/asm/unistd.h index 2c1bec9a14b6..61fb6cb9d2ae 100644 --- a/arch/m68k/include/uapi/asm/unistd.h +++ b/arch/m68k/include/uapi/asm/unistd.h @@ -360,5 +360,6 @@ #define __NR_getrandom 352 #define __NR_memfd_create 353 #define __NR_bpf 354 +#define __NR_execveat 355 #endif /* _UAPI_ASM_M68K_UNISTD_H_ */ diff --git a/arch/m68k/kernel/syscalltable.S b/arch/m68k/kernel/syscalltable.S index 2ca219e184cd..a0ec4303f2c8 100644 --- a/arch/m68k/kernel/syscalltable.S +++ b/arch/m68k/kernel/syscalltable.S @@ -375,4 +375,5 @@ ENTRY(sys_call_table) .long sys_getrandom .long sys_memfd_create .long sys_bpf + .long sys_execveat /* 355 */ diff --git a/arch/powerpc/crypto/sha1.c b/arch/powerpc/crypto/sha1.c index d3feba5a275f..c154cebc1041 100644 --- a/arch/powerpc/crypto/sha1.c +++ b/arch/powerpc/crypto/sha1.c @@ -154,4 +154,5 @@ module_exit(sha1_powerpc_mod_fini); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm"); +MODULE_ALIAS_CRYPTO("sha1"); MODULE_ALIAS_CRYPTO("sha1-powerpc"); diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index ebc4f165690a..0be6c681cab1 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -23,9 +23,9 @@ #define THREAD_SIZE (1 << THREAD_SHIFT) #ifdef CONFIG_PPC64 -#define CURRENT_THREAD_INFO(dest, sp) clrrdi dest, sp, THREAD_SHIFT +#define CURRENT_THREAD_INFO(dest, sp) stringify_in_c(clrrdi dest, sp, THREAD_SHIFT) #else -#define CURRENT_THREAD_INFO(dest, sp) rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT +#define CURRENT_THREAD_INFO(dest, sp) stringify_in_c(rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT) #endif #ifndef __ASSEMBLY__ @@ -71,12 +71,13 @@ struct thread_info { #define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT) /* how to get the thread information struct from C */ -register unsigned long __current_r1 asm("r1"); static inline struct thread_info *current_thread_info(void) { - /* gcc4, at least, is smart enough to turn this into a single - * rlwinm for ppc32 and clrrdi for ppc64 */ - return (struct thread_info *)(__current_r1 & ~(THREAD_SIZE-1)); + unsigned long val; + + asm (CURRENT_THREAD_INFO(%0,1) : "=r" (val)); + + return (struct thread_info *)val; } #endif /* __ASSEMBLY__ */ diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S index 54eca8b3b288..0509bca5e830 100644 --- a/arch/powerpc/platforms/powernv/opal-wrappers.S +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S @@ -40,7 +40,6 @@ BEGIN_FTR_SECTION; \ b 1f; \ END_FTR_SECTION(0, 1); \ ld r12,opal_tracepoint_refcount@toc(r2); \ - std r12,32(r1); \ cmpdi r12,0; \ bne- LABEL; \ 1: diff --git a/arch/s390/hypfs/hypfs_vm.c b/arch/s390/hypfs/hypfs_vm.c index 32040ace00ea..afbe07907c10 100644 --- a/arch/s390/hypfs/hypfs_vm.c +++ b/arch/s390/hypfs/hypfs_vm.c @@ -231,7 +231,7 @@ failed: struct dbfs_d2fc_hdr { u64 len; /* Length of d2fc buffer without header */ u16 version; /* Version of header */ - char tod_ext[16]; /* TOD clock for d2fc */ + char tod_ext[STORE_CLOCK_EXT_SIZE]; /* TOD clock for d2fc */ u64 count; /* Number of VM guests in d2fc buffer */ char reserved[30]; } __attribute__ ((packed)); diff --git a/arch/s390/include/asm/irqflags.h b/arch/s390/include/asm/irqflags.h index 37b9091ab8c0..16aa0c779e07 100644 --- a/arch/s390/include/asm/irqflags.h +++ b/arch/s390/include/asm/irqflags.h @@ -36,7 +36,7 @@ static inline notrace void __arch_local_irq_ssm(unsigned long flags) static inline notrace unsigned long arch_local_save_flags(void) { - return __arch_local_irq_stosm(0x00); + return __arch_local_irq_stnsm(0xff); } static inline notrace unsigned long arch_local_irq_save(void) diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h index 8beee1cceba4..98eb2a579223 100644 --- a/arch/s390/include/asm/timex.h +++ b/arch/s390/include/asm/timex.h @@ -67,20 +67,22 @@ static inline void local_tick_enable(unsigned long long comp) set_clock_comparator(S390_lowcore.clock_comparator); } -#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ +#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ +#define STORE_CLOCK_EXT_SIZE 16 /* stcke writes 16 bytes */ typedef unsigned long long cycles_t; -static inline void get_tod_clock_ext(char clk[16]) +static inline void get_tod_clock_ext(char *clk) { - typedef struct { char _[sizeof(clk)]; } addrtype; + typedef struct { char _[STORE_CLOCK_EXT_SIZE]; } addrtype; asm volatile("stcke %0" : "=Q" (*(addrtype *) clk) : : "cc"); } static inline unsigned long long get_tod_clock(void) { - unsigned char clk[16]; + unsigned char clk[STORE_CLOCK_EXT_SIZE]; + get_tod_clock_ext(clk); return *((unsigned long long *)&clk[1]); } diff --git a/arch/s390/include/uapi/asm/unistd.h b/arch/s390/include/uapi/asm/unistd.h index 2b446cf0cc65..67878af257a0 100644 --- a/arch/s390/include/uapi/asm/unistd.h +++ b/arch/s390/include/uapi/asm/unistd.h @@ -289,7 +289,8 @@ #define __NR_bpf 351 #define __NR_s390_pci_mmio_write 352 #define __NR_s390_pci_mmio_read 353 -#define NR_syscalls 354 +#define __NR_execveat 354 +#define NR_syscalls 355 /* * There are some system calls that are not present on 64 bit, some diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S index a2987243bc76..939ec474b1dd 100644 --- a/arch/s390/kernel/syscalls.S +++ b/arch/s390/kernel/syscalls.S @@ -362,3 +362,4 @@ SYSCALL(sys_memfd_create,sys_memfd_create,compat_sys_memfd_create) /* 350 */ SYSCALL(sys_bpf,sys_bpf,compat_sys_bpf) SYSCALL(sys_ni_syscall,sys_s390_pci_mmio_write,compat_sys_s390_pci_mmio_write) SYSCALL(sys_ni_syscall,sys_s390_pci_mmio_read,compat_sys_s390_pci_mmio_read) +SYSCALL(sys_execveat,sys_execveat,compat_sys_execveat) diff --git a/arch/s390/kernel/uprobes.c b/arch/s390/kernel/uprobes.c index f6b3cd056ec2..cc7328080b60 100644 --- a/arch/s390/kernel/uprobes.c +++ b/arch/s390/kernel/uprobes.c @@ -48,6 +48,30 @@ bool arch_uprobe_xol_was_trapped(struct task_struct *tsk) return false; } +static int check_per_event(unsigned short cause, unsigned long control, + struct pt_regs *regs) +{ + if (!(regs->psw.mask & PSW_MASK_PER)) + return 0; + /* user space single step */ + if (control == 0) + return 1; + /* over indication for storage alteration */ + if ((control & 0x20200000) && (cause & 0x2000)) + return 1; + if (cause & 0x8000) { + /* all branches */ + if ((control & 0x80800000) == 0x80000000) + return 1; + /* branch into selected range */ + if (((control & 0x80800000) == 0x80800000) && + regs->psw.addr >= current->thread.per_user.start && + regs->psw.addr <= current->thread.per_user.end) + return 1; + } + return 0; +} + int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) { int fixup = probe_get_fixup_type(auprobe->insn); @@ -71,9 +95,13 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) if (regs->psw.addr - utask->xol_vaddr == ilen) regs->psw.addr = utask->vaddr + ilen; } - /* If per tracing was active generate trap */ - if (regs->psw.mask & PSW_MASK_PER) - do_per_trap(regs); + if (check_per_event(current->thread.per_event.cause, + current->thread.per_user.control, regs)) { + /* fix per address */ + current->thread.per_event.address = utask->vaddr; + /* trigger per event */ + set_pt_regs_flag(regs, PIF_PER_TRAP); + } return 0; } @@ -106,6 +134,7 @@ void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) clear_thread_flag(TIF_UPROBE_SINGLESTEP); regs->int_code = auprobe->saved_int_code; regs->psw.addr = current->utask->vaddr; + current->thread.per_event.address = current->utask->vaddr; } unsigned long arch_uretprobe_hijack_return_addr(unsigned long trampoline, @@ -146,17 +175,20 @@ static void adjust_psw_addr(psw_t *psw, unsigned long len) __rc; \ }) -#define emu_store_ril(ptr, input) \ +#define emu_store_ril(regs, ptr, input) \ ({ \ unsigned int mask = sizeof(*(ptr)) - 1; \ + __typeof__(ptr) __ptr = (ptr); \ int __rc = 0; \ \ if (!test_facility(34)) \ __rc = EMU_ILLEGAL_OP; \ - else if ((u64 __force)ptr & mask) \ + else if ((u64 __force)__ptr & mask) \ __rc = EMU_SPECIFICATION; \ - else if (put_user(*(input), ptr)) \ + else if (put_user(*(input), __ptr)) \ __rc = EMU_ADDRESSING; \ + if (__rc == 0) \ + sim_stor_event(regs, __ptr, mask + 1); \ __rc; \ }) @@ -198,6 +230,25 @@ union split_register { }; /* + * If user per registers are setup to trace storage alterations and an + * emulated store took place on a fitting address a user trap is generated. + */ +static void sim_stor_event(struct pt_regs *regs, void *addr, int len) +{ + if (!(regs->psw.mask & PSW_MASK_PER)) + return; + if (!(current->thread.per_user.control & PER_EVENT_STORE)) + return; + if ((void *)current->thread.per_user.start > (addr + len)) + return; + if ((void *)current->thread.per_user.end < addr) + return; + current->thread.per_event.address = regs->psw.addr; + current->thread.per_event.cause = PER_EVENT_STORE >> 16; + set_pt_regs_flag(regs, PIF_PER_TRAP); +} + +/* * pc relative instructions are emulated, since parameters may not be * accessible from the xol area due to range limitations. */ @@ -249,13 +300,13 @@ static void handle_insn_ril(struct arch_uprobe *auprobe, struct pt_regs *regs) rc = emu_load_ril((u32 __user *)uptr, &rx->u64); break; case 0x07: /* sthrl */ - rc = emu_store_ril((u16 __user *)uptr, &rx->u16[3]); + rc = emu_store_ril(regs, (u16 __user *)uptr, &rx->u16[3]); break; case 0x0b: /* stgrl */ - rc = emu_store_ril((u64 __user *)uptr, &rx->u64); + rc = emu_store_ril(regs, (u64 __user *)uptr, &rx->u64); break; case 0x0f: /* strl */ - rc = emu_store_ril((u32 __user *)uptr, &rx->u32[1]); + rc = emu_store_ril(regs, (u32 __user *)uptr, &rx->u32[1]); break; } break; diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c index 7f0089d9a4aa..e34122e539a1 100644 --- a/arch/s390/kernel/vtime.c +++ b/arch/s390/kernel/vtime.c @@ -128,8 +128,6 @@ void vtime_account_irq_enter(struct task_struct *tsk) struct thread_info *ti = task_thread_info(tsk); u64 timer, system; - WARN_ON_ONCE(!irqs_disabled()); - timer = S390_lowcore.last_update_timer; S390_lowcore.last_update_timer = get_vtimer(); S390_lowcore.system_timer += timer - S390_lowcore.last_update_timer; diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index be99357d238c..3cf8cc03fff6 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -322,11 +322,12 @@ static int gmap_alloc_table(struct gmap *gmap, unsigned long *table, static unsigned long __gmap_segment_gaddr(unsigned long *entry) { struct page *page; - unsigned long offset; + unsigned long offset, mask; offset = (unsigned long) entry / sizeof(unsigned long); offset = (offset & (PTRS_PER_PMD - 1)) * PMD_SIZE; - page = pmd_to_page((pmd_t *) entry); + mask = ~(PTRS_PER_PMD * sizeof(pmd_t) - 1); + page = virt_to_page((void *)((unsigned long) entry & mask)); return page->index + offset; } diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c index c52ac77408ca..524496d47ef5 100644 --- a/arch/s390/net/bpf_jit_comp.c +++ b/arch/s390/net/bpf_jit_comp.c @@ -431,8 +431,8 @@ static int bpf_jit_insn(struct bpf_jit *jit, struct sock_filter *filter, EMIT4_DISP(0x88500000, K); break; case BPF_ALU | BPF_NEG: /* A = -A */ - /* lnr %r5,%r5 */ - EMIT2(0x1155); + /* lcr %r5,%r5 */ + EMIT2(0x1355); break; case BPF_JMP | BPF_JA: /* ip += K */ offset = addrs[i + K] + jit->start - jit->prg; @@ -502,8 +502,8 @@ branch: if (filter->jt == filter->jf) { xbranch: /* Emit compare if the branch targets are different */ if (filter->jt != filter->jf) { jit->seen |= SEEN_XREG; - /* cr %r5,%r12 */ - EMIT2(0x195c); + /* clr %r5,%r12 */ + EMIT2(0x155c); } goto branch; case BPF_JMP | BPF_JSET | BPF_X: /* ip += (A & X) ? jt : jf */ diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile index 5b016e2498f3..3db07f30636f 100644 --- a/arch/x86/boot/Makefile +++ b/arch/x86/boot/Makefile @@ -51,6 +51,7 @@ targets += cpustr.h $(obj)/cpustr.h: $(obj)/mkcpustr FORCE $(call if_changed,cpustr) endif +clean-files += cpustr.h # --------------------------------------------------------------------------- diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile index fd0f848938cc..5a4a089e8b1f 100644 --- a/arch/x86/crypto/Makefile +++ b/arch/x86/crypto/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o obj-$(CONFIG_CRYPTO_CRC32C_INTEL) += crc32c-intel.o obj-$(CONFIG_CRYPTO_SHA1_SSSE3) += sha1-ssse3.o -obj-$(CONFIG_CRYPTO_SHA1_MB) += sha-mb/ obj-$(CONFIG_CRYPTO_CRC32_PCLMUL) += crc32-pclmul.o obj-$(CONFIG_CRYPTO_SHA256_SSSE3) += sha256-ssse3.o obj-$(CONFIG_CRYPTO_SHA512_SSSE3) += sha512-ssse3.o @@ -46,6 +45,7 @@ endif ifeq ($(avx2_supported),yes) obj-$(CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64) += camellia-aesni-avx2.o obj-$(CONFIG_CRYPTO_SERPENT_AVX2_X86_64) += serpent-avx2.o + obj-$(CONFIG_CRYPTO_SHA1_MB) += sha-mb/ endif aes-i586-y := aes-i586-asm_32.o aes_glue.o diff --git a/arch/x86/crypto/aes_ctrby8_avx-x86_64.S b/arch/x86/crypto/aes_ctrby8_avx-x86_64.S index 2df2a0298f5a..a916c4a61165 100644 --- a/arch/x86/crypto/aes_ctrby8_avx-x86_64.S +++ b/arch/x86/crypto/aes_ctrby8_avx-x86_64.S @@ -208,7 +208,7 @@ ddq_add_8: .if (klen == KEY_128) .if (load_keys) - vmovdqa 3*16(p_keys), xkeyA + vmovdqa 3*16(p_keys), xkey4 .endif .else vmovdqa 3*16(p_keys), xkeyA @@ -224,7 +224,7 @@ ddq_add_8: add $(16*by), p_in .if (klen == KEY_128) - vmovdqa 4*16(p_keys), xkey4 + vmovdqa 4*16(p_keys), xkeyB .else .if (load_keys) vmovdqa 4*16(p_keys), xkey4 @@ -234,7 +234,12 @@ ddq_add_8: .set i, 0 .rept by club XDATA, i - vaesenc xkeyA, var_xdata, var_xdata /* key 3 */ + /* key 3 */ + .if (klen == KEY_128) + vaesenc xkey4, var_xdata, var_xdata + .else + vaesenc xkeyA, var_xdata, var_xdata + .endif .set i, (i +1) .endr @@ -243,13 +248,18 @@ ddq_add_8: .set i, 0 .rept by club XDATA, i - vaesenc xkey4, var_xdata, var_xdata /* key 4 */ + /* key 4 */ + .if (klen == KEY_128) + vaesenc xkeyB, var_xdata, var_xdata + .else + vaesenc xkey4, var_xdata, var_xdata + .endif .set i, (i +1) .endr .if (klen == KEY_128) .if (load_keys) - vmovdqa 6*16(p_keys), xkeyB + vmovdqa 6*16(p_keys), xkey8 .endif .else vmovdqa 6*16(p_keys), xkeyB @@ -267,12 +277,17 @@ ddq_add_8: .set i, 0 .rept by club XDATA, i - vaesenc xkeyB, var_xdata, var_xdata /* key 6 */ + /* key 6 */ + .if (klen == KEY_128) + vaesenc xkey8, var_xdata, var_xdata + .else + vaesenc xkeyB, var_xdata, var_xdata + .endif .set i, (i +1) .endr .if (klen == KEY_128) - vmovdqa 8*16(p_keys), xkey8 + vmovdqa 8*16(p_keys), xkeyB .else .if (load_keys) vmovdqa 8*16(p_keys), xkey8 @@ -288,7 +303,7 @@ ddq_add_8: .if (klen == KEY_128) .if (load_keys) - vmovdqa 9*16(p_keys), xkeyA + vmovdqa 9*16(p_keys), xkey12 .endif .else vmovdqa 9*16(p_keys), xkeyA @@ -297,7 +312,12 @@ ddq_add_8: .set i, 0 .rept by club XDATA, i - vaesenc xkey8, var_xdata, var_xdata /* key 8 */ + /* key 8 */ + .if (klen == KEY_128) + vaesenc xkeyB, var_xdata, var_xdata + .else + vaesenc xkey8, var_xdata, var_xdata + .endif .set i, (i +1) .endr @@ -306,7 +326,12 @@ ddq_add_8: .set i, 0 .rept by club XDATA, i - vaesenc xkeyA, var_xdata, var_xdata /* key 9 */ + /* key 9 */ + .if (klen == KEY_128) + vaesenc xkey12, var_xdata, var_xdata + .else + vaesenc xkeyA, var_xdata, var_xdata + .endif .set i, (i +1) .endr @@ -412,7 +437,6 @@ ddq_add_8: /* main body of aes ctr load */ .macro do_aes_ctrmain key_len - cmp $16, num_bytes jb .Ldo_return2\key_len diff --git a/arch/x86/crypto/sha-mb/sha1_mb.c b/arch/x86/crypto/sha-mb/sha1_mb.c index a225a5ca1037..fd9f6b035b16 100644 --- a/arch/x86/crypto/sha-mb/sha1_mb.c +++ b/arch/x86/crypto/sha-mb/sha1_mb.c @@ -931,4 +931,4 @@ module_exit(sha1_mb_mod_fini); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, multi buffer accelerated"); -MODULE_ALIAS("sha1"); +MODULE_ALIAS_CRYPTO("sha1"); diff --git a/arch/x86/include/asm/vgtod.h b/arch/x86/include/asm/vgtod.h index e7e9682a33e9..f556c4843aa1 100644 --- a/arch/x86/include/asm/vgtod.h +++ b/arch/x86/include/asm/vgtod.h @@ -80,9 +80,11 @@ static inline unsigned int __getcpu(void) /* * Load per CPU data from GDT. LSL is faster than RDTSCP and - * works on all CPUs. + * works on all CPUs. This is volatile so that it orders + * correctly wrt barrier() and to keep gcc from cleverly + * hoisting it out of the calling function. */ - asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG)); + asm volatile ("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG)); return p; } diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 4433a4be8171..d1626364a28a 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -750,13 +750,13 @@ static int _acpi_map_lsapic(acpi_handle handle, int physid, int *pcpu) } /* wrapper to silence section mismatch warning */ -int __ref acpi_map_lsapic(acpi_handle handle, int physid, int *pcpu) +int __ref acpi_map_cpu(acpi_handle handle, int physid, int *pcpu) { return _acpi_map_lsapic(handle, physid, pcpu); } -EXPORT_SYMBOL(acpi_map_lsapic); +EXPORT_SYMBOL(acpi_map_cpu); -int acpi_unmap_lsapic(int cpu) +int acpi_unmap_cpu(int cpu) { #ifdef CONFIG_ACPI_NUMA set_apicid_to_node(per_cpu(x86_cpu_to_apicid, cpu), NUMA_NO_NODE); @@ -768,8 +768,7 @@ int acpi_unmap_lsapic(int cpu) return (0); } - -EXPORT_SYMBOL(acpi_unmap_lsapic); +EXPORT_SYMBOL(acpi_unmap_cpu); #endif /* CONFIG_ACPI_HOTPLUG_CPU */ int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base) diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index e27b49d7c922..80091ae54c2b 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -66,3 +66,4 @@ targets += capflags.c $(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.sh FORCE $(call if_changed,mkcapflags) endif +clean-files += capflags.c diff --git a/arch/x86/kernel/cpu/mkcapflags.sh b/arch/x86/kernel/cpu/mkcapflags.sh index e2b22df964cd..36d99a337b49 100644 --- a/arch/x86/kernel/cpu/mkcapflags.sh +++ b/arch/x86/kernel/cpu/mkcapflags.sh @@ -28,7 +28,7 @@ function dump_array() # If the /* comment */ starts with a quote string, grab that. VALUE="$(echo "$i" | sed -n 's@.*/\* *\("[^"]*"\).*\*/@\1@p')" [ -z "$VALUE" ] && VALUE="\"$NAME\"" - [ "$VALUE" == '""' ] && continue + [ "$VALUE" = '""' ] && continue # Name is uppercase, VALUE is all lowercase VALUE="$(echo "$VALUE" | tr A-Z a-z)" diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 3c895d480cd7..073983398364 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -568,8 +568,8 @@ struct event_constraint intel_atom_pebs_event_constraints[] = { }; struct event_constraint intel_slm_pebs_event_constraints[] = { - /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ - INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), + /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ + INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1), /* Allow all events as PEBS with no flags */ INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), EVENT_CONSTRAINT_END diff --git a/arch/x86/kernel/cpu/perf_event_intel_rapl.c b/arch/x86/kernel/cpu/perf_event_intel_rapl.c index 673f930c700f..6e434f8e5fc8 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_rapl.c +++ b/arch/x86/kernel/cpu/perf_event_intel_rapl.c @@ -103,6 +103,13 @@ static struct kobj_attribute format_attr_##_var = \ #define RAPL_CNTR_WIDTH 32 /* 32-bit rapl counters */ +#define RAPL_EVENT_ATTR_STR(_name, v, str) \ +static struct perf_pmu_events_attr event_attr_##v = { \ + .attr = __ATTR(_name, 0444, rapl_sysfs_show, NULL), \ + .id = 0, \ + .event_str = str, \ +}; + struct rapl_pmu { spinlock_t lock; int hw_unit; /* 1/2^hw_unit Joule */ @@ -379,23 +386,36 @@ static struct attribute_group rapl_pmu_attr_group = { .attrs = rapl_pmu_attrs, }; -EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); -EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02"); -EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03"); -EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04"); +static ssize_t rapl_sysfs_show(struct device *dev, + struct device_attribute *attr, + char *page) +{ + struct perf_pmu_events_attr *pmu_attr = \ + container_of(attr, struct perf_pmu_events_attr, attr); + + if (pmu_attr->event_str) + return sprintf(page, "%s", pmu_attr->event_str); + + return 0; +} + +RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); +RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02"); +RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03"); +RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04"); -EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules"); -EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules"); -EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules"); -EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules"); +RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules"); +RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules"); +RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules"); +RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules"); /* * we compute in 0.23 nJ increments regardless of MSR */ -EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10"); -EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10"); -EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10"); -EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10"); +RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10"); +RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10"); +RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10"); +RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10"); static struct attribute *rapl_events_srv_attr[] = { EVENT_PTR(rapl_cores), diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h index 18eb78bbdd10..863d9b02563e 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h @@ -17,7 +17,7 @@ #define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff) #define UNCORE_PCI_DEV_IDX(data) (data & 0xff) #define UNCORE_EXTRA_PCI_DEV 0xff -#define UNCORE_EXTRA_PCI_DEV_MAX 2 +#define UNCORE_EXTRA_PCI_DEV_MAX 3 /* support up to 8 sockets */ #define UNCORE_SOCKET_MAX 8 diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c index 745b158e9a65..21af6149edf2 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c @@ -891,6 +891,7 @@ void snbep_uncore_cpu_init(void) enum { SNBEP_PCI_QPI_PORT0_FILTER, SNBEP_PCI_QPI_PORT1_FILTER, + HSWEP_PCI_PCU_3, }; static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event) @@ -2026,6 +2027,17 @@ void hswep_uncore_cpu_init(void) { if (hswep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) hswep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; + + /* Detect 6-8 core systems with only two SBOXes */ + if (uncore_extra_pci_dev[0][HSWEP_PCI_PCU_3]) { + u32 capid4; + + pci_read_config_dword(uncore_extra_pci_dev[0][HSWEP_PCI_PCU_3], + 0x94, &capid4); + if (((capid4 >> 6) & 0x3) == 0) + hswep_uncore_sbox.num_boxes = 2; + } + uncore_msr_uncores = hswep_msr_uncores; } @@ -2287,6 +2299,11 @@ static DEFINE_PCI_DEVICE_TABLE(hswep_uncore_pci_ids) = { .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, SNBEP_PCI_QPI_PORT1_FILTER), }, + { /* PCU.3 (for Capability registers) */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fc0), + .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, + HSWEP_PCI_PCU_3), + }, { /* end: all zeroes */ } }; diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c index f7e3cd50ece0..98f654d466e5 100644 --- a/arch/x86/kernel/kprobes/core.c +++ b/arch/x86/kernel/kprobes/core.c @@ -1020,6 +1020,15 @@ int setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs) regs->flags &= ~X86_EFLAGS_IF; trace_hardirqs_off(); regs->ip = (unsigned long)(jp->entry); + + /* + * jprobes use jprobe_return() which skips the normal return + * path of the function, and this messes up the accounting of the + * function graph tracer to get messed up. + * + * Pause function graph tracing while performing the jprobe function. + */ + pause_graph_tracing(); return 1; } NOKPROBE_SYMBOL(setjmp_pre_handler); @@ -1048,24 +1057,25 @@ int longjmp_break_handler(struct kprobe *p, struct pt_regs *regs) struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); u8 *addr = (u8 *) (regs->ip - 1); struct jprobe *jp = container_of(p, struct jprobe, kp); + void *saved_sp = kcb->jprobe_saved_sp; if ((addr > (u8 *) jprobe_return) && (addr < (u8 *) jprobe_return_end)) { - if (stack_addr(regs) != kcb->jprobe_saved_sp) { + if (stack_addr(regs) != saved_sp) { struct pt_regs *saved_regs = &kcb->jprobe_saved_regs; printk(KERN_ERR "current sp %p does not match saved sp %p\n", - stack_addr(regs), kcb->jprobe_saved_sp); + stack_addr(regs), saved_sp); printk(KERN_ERR "Saved registers for jprobe %p\n", jp); show_regs(saved_regs); printk(KERN_ERR "Current registers\n"); show_regs(regs); BUG(); } + /* It's OK to start function graph tracing again */ + unpause_graph_tracing(); *regs = kcb->jprobe_saved_regs; - memcpy((kprobe_opcode_t *)(kcb->jprobe_saved_sp), - kcb->jprobes_stack, - MIN_STACK_SIZE(kcb->jprobe_saved_sp)); + memcpy(saved_sp, kcb->jprobes_stack, MIN_STACK_SIZE(saved_sp)); preempt_enable_no_resched(); return 1; } diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c index e309cc5c276e..781861cc5ee8 100644 --- a/arch/x86/kernel/perf_regs.c +++ b/arch/x86/kernel/perf_regs.c @@ -78,6 +78,14 @@ u64 perf_reg_abi(struct task_struct *task) { return PERF_SAMPLE_REGS_ABI_32; } + +void perf_get_regs_user(struct perf_regs *regs_user, + struct pt_regs *regs, + struct pt_regs *regs_user_copy) +{ + regs_user->regs = task_pt_regs(current); + regs_user->abi = perf_reg_abi(current); +} #else /* CONFIG_X86_64 */ #define REG_NOSUPPORT ((1ULL << PERF_REG_X86_DS) | \ (1ULL << PERF_REG_X86_ES) | \ @@ -102,4 +110,86 @@ u64 perf_reg_abi(struct task_struct *task) else return PERF_SAMPLE_REGS_ABI_64; } + +void perf_get_regs_user(struct perf_regs *regs_user, + struct pt_regs *regs, + struct pt_regs *regs_user_copy) +{ + struct pt_regs *user_regs = task_pt_regs(current); + + /* + * If we're in an NMI that interrupted task_pt_regs setup, then + * we can't sample user regs at all. This check isn't really + * sufficient, though, as we could be in an NMI inside an interrupt + * that happened during task_pt_regs setup. + */ + if (regs->sp > (unsigned long)&user_regs->r11 && + regs->sp <= (unsigned long)(user_regs + 1)) { + regs_user->abi = PERF_SAMPLE_REGS_ABI_NONE; + regs_user->regs = NULL; + return; + } + + /* + * RIP, flags, and the argument registers are usually saved. + * orig_ax is probably okay, too. + */ + regs_user_copy->ip = user_regs->ip; + regs_user_copy->cx = user_regs->cx; + regs_user_copy->dx = user_regs->dx; + regs_user_copy->si = user_regs->si; + regs_user_copy->di = user_regs->di; + regs_user_copy->r8 = user_regs->r8; + regs_user_copy->r9 = user_regs->r9; + regs_user_copy->r10 = user_regs->r10; + regs_user_copy->r11 = user_regs->r11; + regs_user_copy->orig_ax = user_regs->orig_ax; + regs_user_copy->flags = user_regs->flags; + + /* + * Don't even try to report the "rest" regs. + */ + regs_user_copy->bx = -1; + regs_user_copy->bp = -1; + regs_user_copy->r12 = -1; + regs_user_copy->r13 = -1; + regs_user_copy->r14 = -1; + regs_user_copy->r15 = -1; + + /* + * For this to be at all useful, we need a reasonable guess for + * sp and the ABI. Be careful: we're in NMI context, and we're + * considering current to be the current task, so we should + * be careful not to look at any other percpu variables that might + * change during context switches. + */ + if (IS_ENABLED(CONFIG_IA32_EMULATION) && + task_thread_info(current)->status & TS_COMPAT) { + /* Easy case: we're in a compat syscall. */ + regs_user->abi = PERF_SAMPLE_REGS_ABI_32; + regs_user_copy->sp = user_regs->sp; + regs_user_copy->cs = user_regs->cs; + regs_user_copy->ss = user_regs->ss; + } else if (user_regs->orig_ax != -1) { + /* + * We're probably in a 64-bit syscall. + * Warning: this code is severely racy. At least it's better + * than just blindly copying user_regs. + */ + regs_user->abi = PERF_SAMPLE_REGS_ABI_64; + regs_user_copy->sp = this_cpu_read(old_rsp); + regs_user_copy->cs = __USER_CS; + regs_user_copy->ss = __USER_DS; + regs_user_copy->cx = -1; /* usually contains garbage */ + } else { + /* We're probably in an interrupt or exception. */ + regs_user->abi = user_64bit_mode(user_regs) ? + PERF_SAMPLE_REGS_ABI_64 : PERF_SAMPLE_REGS_ABI_32; + regs_user_copy->sp = user_regs->sp; + regs_user_copy->cs = user_regs->cs; + regs_user_copy->ss = user_regs->ss; + } + + regs_user->regs = regs_user_copy; +} #endif /* CONFIG_X86_32 */ diff --git a/arch/x86/lib/insn.c b/arch/x86/lib/insn.c index 2480978b31cc..1313ae6b478b 100644 --- a/arch/x86/lib/insn.c +++ b/arch/x86/lib/insn.c @@ -28,7 +28,7 @@ /* Verify next sizeof(t) bytes can be on the same instruction */ #define validate_next(t, insn, n) \ - ((insn)->next_byte + sizeof(t) + n < (insn)->end_kaddr) + ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr) #define __get_next(t, insn) \ ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); r; }) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index a97ee0801475..08a7d313538a 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -438,20 +438,20 @@ static unsigned long __init init_range_memory_mapping( static unsigned long __init get_new_step_size(unsigned long step_size) { /* - * Explain why we shift by 5 and why we don't have to worry about - * 'step_size << 5' overflowing: - * - * initial mapped size is PMD_SIZE (2M). + * Initial mapped size is PMD_SIZE (2M). * We can not set step_size to be PUD_SIZE (1G) yet. * In worse case, when we cross the 1G boundary, and * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k) - * to map 1G range with PTE. Use 5 as shift for now. + * to map 1G range with PTE. Hence we use one less than the + * difference of page table level shifts. * - * Don't need to worry about overflow, on 32bit, when step_size - * is 0, round_down() returns 0 for start, and that turns it - * into 0x100000000ULL. + * Don't need to worry about overflow in the top-down case, on 32bit, + * when step_size is 0, round_down() returns 0 for start, and that + * turns it into 0x100000000ULL. + * In the bottom-up case, round_up(x, 0) returns 0 though too, which + * needs to be taken into consideration by the code below. */ - return step_size << 5; + return step_size << (PMD_SHIFT - PAGE_SHIFT - 1); } /** @@ -471,7 +471,6 @@ static void __init memory_map_top_down(unsigned long map_start, unsigned long step_size; unsigned long addr; unsigned long mapped_ram_size = 0; - unsigned long new_mapped_ram_size; /* xen has big range in reserved near end of ram, skip it at first.*/ addr = memblock_find_in_range(map_start, map_end, PMD_SIZE, PMD_SIZE); @@ -496,14 +495,12 @@ static void __init memory_map_top_down(unsigned long map_start, start = map_start; } else start = map_start; - new_mapped_ram_size = init_range_memory_mapping(start, + mapped_ram_size += init_range_memory_mapping(start, last_start); last_start = start; min_pfn_mapped = last_start >> PAGE_SHIFT; - /* only increase step_size after big range get mapped */ - if (new_mapped_ram_size > mapped_ram_size) + if (mapped_ram_size >= step_size) step_size = get_new_step_size(step_size); - mapped_ram_size += new_mapped_ram_size; } if (real_end < map_end) @@ -524,7 +521,7 @@ static void __init memory_map_top_down(unsigned long map_start, static void __init memory_map_bottom_up(unsigned long map_start, unsigned long map_end) { - unsigned long next, new_mapped_ram_size, start; + unsigned long next, start; unsigned long mapped_ram_size = 0; /* step_size need to be small so pgt_buf from BRK could cover it */ unsigned long step_size = PMD_SIZE; @@ -539,19 +536,19 @@ static void __init memory_map_bottom_up(unsigned long map_start, * for page table. */ while (start < map_end) { - if (map_end - start > step_size) { + if (step_size && map_end - start > step_size) { next = round_up(start + 1, step_size); if (next > map_end) next = map_end; - } else + } else { next = map_end; + } - new_mapped_ram_size = init_range_memory_mapping(start, next); + mapped_ram_size += init_range_memory_mapping(start, next); start = next; - if (new_mapped_ram_size > mapped_ram_size) + if (mapped_ram_size >= step_size) step_size = get_new_step_size(step_size); - mapped_ram_size += new_mapped_ram_size; } } diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c index 009495b9ab4b..1c9f750c3859 100644 --- a/arch/x86/vdso/vma.c +++ b/arch/x86/vdso/vma.c @@ -41,12 +41,17 @@ void __init init_vdso_image(const struct vdso_image *image) struct linux_binprm; -/* Put the vdso above the (randomized) stack with another randomized offset. - This way there is no hole in the middle of address space. - To save memory make sure it is still in the same PTE as the stack top. - This doesn't give that many random bits. - - Only used for the 64-bit and x32 vdsos. */ +/* + * Put the vdso above the (randomized) stack with another randomized + * offset. This way there is no hole in the middle of address space. + * To save memory make sure it is still in the same PTE as the stack + * top. This doesn't give that many random bits. + * + * Note that this algorithm is imperfect: the distribution of the vdso + * start address within a PMD is biased toward the end. + * + * Only used for the 64-bit and x32 vdsos. + */ static unsigned long vdso_addr(unsigned long start, unsigned len) { #ifdef CONFIG_X86_32 @@ -54,22 +59,30 @@ static unsigned long vdso_addr(unsigned long start, unsigned len) #else unsigned long addr, end; unsigned offset; - end = (start + PMD_SIZE - 1) & PMD_MASK; + + /* + * Round up the start address. It can start out unaligned as a result + * of stack start randomization. + */ + start = PAGE_ALIGN(start); + + /* Round the lowest possible end address up to a PMD boundary. */ + end = (start + len + PMD_SIZE - 1) & PMD_MASK; if (end >= TASK_SIZE_MAX) end = TASK_SIZE_MAX; end -= len; - /* This loses some more bits than a modulo, but is cheaper */ - offset = get_random_int() & (PTRS_PER_PTE - 1); - addr = start + (offset << PAGE_SHIFT); - if (addr >= end) - addr = end; + + if (end > start) { + offset = get_random_int() % (((end - start) >> PAGE_SHIFT) + 1); + addr = start + (offset << PAGE_SHIFT); + } else { + addr = start; + } /* - * page-align it here so that get_unmapped_area doesn't - * align it wrongfully again to the next page. addr can come in 4K - * unaligned here as a result of stack start randomization. + * Forcibly align the final address in case we have a hardware + * issue that requires alignment for performance reasons. */ - addr = PAGE_ALIGN(addr); addr = align_vdso_addr(addr); return addr; diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 6bf3a13e3e0f..78a881b7fc41 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -40,6 +40,7 @@ #include <xen/interface/physdev.h> #include <xen/interface/vcpu.h> #include <xen/interface/memory.h> +#include <xen/interface/nmi.h> #include <xen/interface/xen-mca.h> #include <xen/features.h> #include <xen/page.h> @@ -66,6 +67,7 @@ #include <asm/reboot.h> #include <asm/stackprotector.h> #include <asm/hypervisor.h> +#include <asm/mach_traps.h> #include <asm/mwait.h> #include <asm/pci_x86.h> #include <asm/pat.h> @@ -1351,6 +1353,21 @@ static const struct machine_ops xen_machine_ops __initconst = { .emergency_restart = xen_emergency_restart, }; +static unsigned char xen_get_nmi_reason(void) +{ + unsigned char reason = 0; + + /* Construct a value which looks like it came from port 0x61. */ + if (test_bit(_XEN_NMIREASON_io_error, + &HYPERVISOR_shared_info->arch.nmi_reason)) + reason |= NMI_REASON_IOCHK; + if (test_bit(_XEN_NMIREASON_pci_serr, + &HYPERVISOR_shared_info->arch.nmi_reason)) + reason |= NMI_REASON_SERR; + + return reason; +} + static void __init xen_boot_params_init_edd(void) { #if IS_ENABLED(CONFIG_EDD) @@ -1535,9 +1552,12 @@ asmlinkage __visible void __init xen_start_kernel(void) pv_info = xen_info; pv_init_ops = xen_init_ops; pv_apic_ops = xen_apic_ops; - if (!xen_pvh_domain()) + if (!xen_pvh_domain()) { pv_cpu_ops = xen_cpu_ops; + x86_platform.get_nmi_reason = xen_get_nmi_reason; + } + if (xen_feature(XENFEAT_auto_translated_physmap)) x86_init.resources.memory_setup = xen_auto_xlated_memory_setup; else diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c index edbc7a63fd73..70fb5075c901 100644 --- a/arch/x86/xen/p2m.c +++ b/arch/x86/xen/p2m.c @@ -167,10 +167,13 @@ static void * __ref alloc_p2m_page(void) return (void *)__get_free_page(GFP_KERNEL | __GFP_REPEAT); } -/* Only to be called in case of a race for a page just allocated! */ -static void free_p2m_page(void *p) +static void __ref free_p2m_page(void *p) { - BUG_ON(!slab_is_available()); + if (unlikely(!slab_is_available())) { + free_bootmem((unsigned long)p, PAGE_SIZE); + return; + } + free_page((unsigned long)p); } @@ -375,7 +378,7 @@ static void __init xen_rebuild_p2m_list(unsigned long *p2m) p2m_missing_pte : p2m_identity_pte; for (i = 0; i < PMDS_PER_MID_PAGE; i++) { pmdp = populate_extra_pmd( - (unsigned long)(p2m + pfn + i * PTRS_PER_PTE)); + (unsigned long)(p2m + pfn) + i * PMD_SIZE); set_pmd(pmdp, __pmd(__pa(ptep) | _KERNPG_TABLE)); } } @@ -436,10 +439,9 @@ EXPORT_SYMBOL_GPL(get_phys_to_machine); * a new pmd is to replace p2m_missing_pte or p2m_identity_pte by a individual * pmd. In case of PAE/x86-32 there are multiple pmds to allocate! */ -static pte_t *alloc_p2m_pmd(unsigned long addr, pte_t *ptep, pte_t *pte_pg) +static pte_t *alloc_p2m_pmd(unsigned long addr, pte_t *pte_pg) { pte_t *ptechk; - pte_t *pteret = ptep; pte_t *pte_newpg[PMDS_PER_MID_PAGE]; pmd_t *pmdp; unsigned int level; @@ -473,8 +475,6 @@ static pte_t *alloc_p2m_pmd(unsigned long addr, pte_t *ptep, pte_t *pte_pg) if (ptechk == pte_pg) { set_pmd(pmdp, __pmd(__pa(pte_newpg[i]) | _KERNPG_TABLE)); - if (vaddr == (addr & ~(PMD_SIZE - 1))) - pteret = pte_offset_kernel(pmdp, addr); pte_newpg[i] = NULL; } @@ -488,7 +488,7 @@ static pte_t *alloc_p2m_pmd(unsigned long addr, pte_t *ptep, pte_t *pte_pg) vaddr += PMD_SIZE; } - return pteret; + return lookup_address(addr, &level); } /* @@ -517,7 +517,7 @@ static bool alloc_p2m(unsigned long pfn) if (pte_pg == p2m_missing_pte || pte_pg == p2m_identity_pte) { /* PMD level is missing, allocate a new one */ - ptep = alloc_p2m_pmd(addr, ptep, pte_pg); + ptep = alloc_p2m_pmd(addr, pte_pg); if (!ptep) return false; } diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index dfd77dec8e2b..865e56cea7a0 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -140,7 +140,7 @@ static void __init xen_del_extra_mem(u64 start, u64 size) unsigned long __ref xen_chk_extra_mem(unsigned long pfn) { int i; - unsigned long addr = PFN_PHYS(pfn); + phys_addr_t addr = PFN_PHYS(pfn); for (i = 0; i < XEN_EXTRA_MEM_MAX_REGIONS; i++) { if (addr >= xen_extra_mem[i].start && @@ -160,6 +160,8 @@ void __init xen_inv_extra_mem(void) int i; for (i = 0; i < XEN_EXTRA_MEM_MAX_REGIONS; i++) { + if (!xen_extra_mem[i].size) + continue; pfn_s = PFN_DOWN(xen_extra_mem[i].start); pfn_e = PFN_UP(xen_extra_mem[i].start + xen_extra_mem[i].size); for (pfn = pfn_s; pfn < pfn_e; pfn++) @@ -229,15 +231,14 @@ static int __init xen_free_mfn(unsigned long mfn) * as a fallback if the remapping fails. */ static void __init xen_set_identity_and_release_chunk(unsigned long start_pfn, - unsigned long end_pfn, unsigned long nr_pages, unsigned long *identity, - unsigned long *released) + unsigned long end_pfn, unsigned long nr_pages, unsigned long *released) { - unsigned long len = 0; unsigned long pfn, end; int ret; WARN_ON(start_pfn > end_pfn); + /* Release pages first. */ end = min(end_pfn, nr_pages); for (pfn = start_pfn; pfn < end; pfn++) { unsigned long mfn = pfn_to_mfn(pfn); @@ -250,16 +251,14 @@ static void __init xen_set_identity_and_release_chunk(unsigned long start_pfn, WARN(ret != 1, "Failed to release pfn %lx err=%d\n", pfn, ret); if (ret == 1) { + (*released)++; if (!__set_phys_to_machine(pfn, INVALID_P2M_ENTRY)) break; - len++; } else break; } - /* Need to release pages first */ - *released += len; - *identity += set_phys_range_identity(start_pfn, end_pfn); + set_phys_range_identity(start_pfn, end_pfn); } /* @@ -287,7 +286,7 @@ static void __init xen_update_mem_tables(unsigned long pfn, unsigned long mfn) } /* Update kernel mapping, but not for highmem. */ - if ((pfn << PAGE_SHIFT) >= __pa(high_memory)) + if (pfn >= PFN_UP(__pa(high_memory - 1))) return; if (HYPERVISOR_update_va_mapping((unsigned long)__va(pfn << PAGE_SHIFT), @@ -318,7 +317,6 @@ static void __init xen_do_set_identity_and_remap_chunk( unsigned long ident_pfn_iter, remap_pfn_iter; unsigned long ident_end_pfn = start_pfn + size; unsigned long left = size; - unsigned long ident_cnt = 0; unsigned int i, chunk; WARN_ON(size == 0); @@ -347,8 +345,7 @@ static void __init xen_do_set_identity_and_remap_chunk( xen_remap_mfn = mfn; /* Set identity map */ - ident_cnt += set_phys_range_identity(ident_pfn_iter, - ident_pfn_iter + chunk); + set_phys_range_identity(ident_pfn_iter, ident_pfn_iter + chunk); left -= chunk; } @@ -371,7 +368,7 @@ static void __init xen_do_set_identity_and_remap_chunk( static unsigned long __init xen_set_identity_and_remap_chunk( const struct e820entry *list, size_t map_size, unsigned long start_pfn, unsigned long end_pfn, unsigned long nr_pages, unsigned long remap_pfn, - unsigned long *identity, unsigned long *released) + unsigned long *released, unsigned long *remapped) { unsigned long pfn; unsigned long i = 0; @@ -386,8 +383,7 @@ static unsigned long __init xen_set_identity_and_remap_chunk( /* Do not remap pages beyond the current allocation */ if (cur_pfn >= nr_pages) { /* Identity map remaining pages */ - *identity += set_phys_range_identity(cur_pfn, - cur_pfn + size); + set_phys_range_identity(cur_pfn, cur_pfn + size); break; } if (cur_pfn + size > nr_pages) @@ -398,7 +394,7 @@ static unsigned long __init xen_set_identity_and_remap_chunk( if (!remap_range_size) { pr_warning("Unable to find available pfn range, not remapping identity pages\n"); xen_set_identity_and_release_chunk(cur_pfn, - cur_pfn + left, nr_pages, identity, released); + cur_pfn + left, nr_pages, released); break; } /* Adjust size to fit in current e820 RAM region */ @@ -410,7 +406,7 @@ static unsigned long __init xen_set_identity_and_remap_chunk( /* Update variables to reflect new mappings. */ i += size; remap_pfn += size; - *identity += size; + *remapped += size; } /* @@ -427,13 +423,13 @@ static unsigned long __init xen_set_identity_and_remap_chunk( static void __init xen_set_identity_and_remap( const struct e820entry *list, size_t map_size, unsigned long nr_pages, - unsigned long *released) + unsigned long *released, unsigned long *remapped) { phys_addr_t start = 0; - unsigned long identity = 0; unsigned long last_pfn = nr_pages; const struct e820entry *entry; unsigned long num_released = 0; + unsigned long num_remapped = 0; int i; /* @@ -460,14 +456,14 @@ static void __init xen_set_identity_and_remap( last_pfn = xen_set_identity_and_remap_chunk( list, map_size, start_pfn, end_pfn, nr_pages, last_pfn, - &identity, &num_released); + &num_released, &num_remapped); start = end; } } *released = num_released; + *remapped = num_remapped; - pr_info("Set %ld page(s) to 1-1 mapping\n", identity); pr_info("Released %ld page(s)\n", num_released); } @@ -586,6 +582,7 @@ char * __init xen_memory_setup(void) struct xen_memory_map memmap; unsigned long max_pages; unsigned long extra_pages = 0; + unsigned long remapped_pages; int i; int op; @@ -635,9 +632,10 @@ char * __init xen_memory_setup(void) * underlying RAM. */ xen_set_identity_and_remap(map, memmap.nr_entries, max_pfn, - &xen_released_pages); + &xen_released_pages, &remapped_pages); extra_pages += xen_released_pages; + extra_pages += remapped_pages; /* * Clamp the amount of extra memory to a EXTRA_MEM_RATIO diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c index f473d268d387..69087341d9ae 100644 --- a/arch/x86/xen/time.c +++ b/arch/x86/xen/time.c @@ -391,7 +391,7 @@ static const struct clock_event_device *xen_clockevent = struct xen_clock_event_device { struct clock_event_device evt; - char *name; + char name[16]; }; static DEFINE_PER_CPU(struct xen_clock_event_device, xen_clock_events) = { .evt.irq = -1 }; @@ -420,46 +420,38 @@ void xen_teardown_timer(int cpu) if (evt->irq >= 0) { unbind_from_irqhandler(evt->irq, NULL); evt->irq = -1; - kfree(per_cpu(xen_clock_events, cpu).name); - per_cpu(xen_clock_events, cpu).name = NULL; } } void xen_setup_timer(int cpu) { - char *name; - struct clock_event_device *evt; + struct xen_clock_event_device *xevt = &per_cpu(xen_clock_events, cpu); + struct clock_event_device *evt = &xevt->evt; int irq; - evt = &per_cpu(xen_clock_events, cpu).evt; WARN(evt->irq >= 0, "IRQ%d for CPU%d is already allocated\n", evt->irq, cpu); if (evt->irq >= 0) xen_teardown_timer(cpu); printk(KERN_INFO "installing Xen timer for CPU %d\n", cpu); - name = kasprintf(GFP_KERNEL, "timer%d", cpu); - if (!name) - name = "<timer kasprintf failed>"; + snprintf(xevt->name, sizeof(xevt->name), "timer%d", cpu); irq = bind_virq_to_irqhandler(VIRQ_TIMER, cpu, xen_timer_interrupt, IRQF_PERCPU|IRQF_NOBALANCING|IRQF_TIMER| IRQF_FORCE_RESUME|IRQF_EARLY_RESUME, - name, NULL); + xevt->name, NULL); (void)xen_set_irq_priority(irq, XEN_IRQ_PRIORITY_MAX); memcpy(evt, xen_clockevent, sizeof(*evt)); evt->cpumask = cpumask_of(cpu); evt->irq = irq; - per_cpu(xen_clock_events, cpu).name = name; } void xen_setup_cpu_clockevents(void) { - BUG_ON(preemptible()); - clockevents_register_device(this_cpu_ptr(&xen_clock_events.evt)); } diff --git a/block/blk-core.c b/block/blk-core.c index 30f6153a40c2..3ad405571dcc 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -473,6 +473,25 @@ void blk_queue_bypass_end(struct request_queue *q) } EXPORT_SYMBOL_GPL(blk_queue_bypass_end); +void blk_set_queue_dying(struct request_queue *q) +{ + queue_flag_set_unlocked(QUEUE_FLAG_DYING, q); + + if (q->mq_ops) + blk_mq_wake_waiters(q); + else { + struct request_list *rl; + + blk_queue_for_each_rl(rl, q) { + if (rl->rq_pool) { + wake_up(&rl->wait[BLK_RW_SYNC]); + wake_up(&rl->wait[BLK_RW_ASYNC]); + } + } + } +} +EXPORT_SYMBOL_GPL(blk_set_queue_dying); + /** * blk_cleanup_queue - shutdown a request queue * @q: request queue to shutdown @@ -486,7 +505,7 @@ void blk_cleanup_queue(struct request_queue *q) /* mark @q DYING, no new request or merges will be allowed afterwards */ mutex_lock(&q->sysfs_lock); - queue_flag_set_unlocked(QUEUE_FLAG_DYING, q); + blk_set_queue_dying(q); spin_lock_irq(lock); /* diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c index 32e8dbb9ad1c..60c9d4a93fe4 100644 --- a/block/blk-mq-tag.c +++ b/block/blk-mq-tag.c @@ -68,9 +68,9 @@ bool __blk_mq_tag_busy(struct blk_mq_hw_ctx *hctx) } /* - * Wakeup all potentially sleeping on normal (non-reserved) tags + * Wakeup all potentially sleeping on tags */ -static void blk_mq_tag_wakeup_all(struct blk_mq_tags *tags) +void blk_mq_tag_wakeup_all(struct blk_mq_tags *tags, bool include_reserve) { struct blk_mq_bitmap_tags *bt; int i, wake_index; @@ -85,6 +85,12 @@ static void blk_mq_tag_wakeup_all(struct blk_mq_tags *tags) wake_index = bt_index_inc(wake_index); } + + if (include_reserve) { + bt = &tags->breserved_tags; + if (waitqueue_active(&bt->bs[0].wait)) + wake_up(&bt->bs[0].wait); + } } /* @@ -100,7 +106,7 @@ void __blk_mq_tag_idle(struct blk_mq_hw_ctx *hctx) atomic_dec(&tags->active_queues); - blk_mq_tag_wakeup_all(tags); + blk_mq_tag_wakeup_all(tags, false); } /* @@ -584,7 +590,7 @@ int blk_mq_tag_update_depth(struct blk_mq_tags *tags, unsigned int tdepth) * static and should never need resizing. */ bt_update_count(&tags->bitmap_tags, tdepth); - blk_mq_tag_wakeup_all(tags); + blk_mq_tag_wakeup_all(tags, false); return 0; } diff --git a/block/blk-mq-tag.h b/block/blk-mq-tag.h index 6206ed17ef76..a6fa0fc9d41a 100644 --- a/block/blk-mq-tag.h +++ b/block/blk-mq-tag.h @@ -54,6 +54,7 @@ extern bool blk_mq_has_free_tags(struct blk_mq_tags *tags); extern ssize_t blk_mq_tag_sysfs_show(struct blk_mq_tags *tags, char *page); extern void blk_mq_tag_init_last_tag(struct blk_mq_tags *tags, unsigned int *last_tag); extern int blk_mq_tag_update_depth(struct blk_mq_tags *tags, unsigned int depth); +extern void blk_mq_tag_wakeup_all(struct blk_mq_tags *tags, bool); enum { BLK_MQ_TAG_CACHE_MIN = 1, diff --git a/block/blk-mq.c b/block/blk-mq.c index da1ab5641227..2f95747c287e 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -107,7 +107,7 @@ static void blk_mq_usage_counter_release(struct percpu_ref *ref) wake_up_all(&q->mq_freeze_wq); } -static void blk_mq_freeze_queue_start(struct request_queue *q) +void blk_mq_freeze_queue_start(struct request_queue *q) { bool freeze; @@ -120,6 +120,7 @@ static void blk_mq_freeze_queue_start(struct request_queue *q) blk_mq_run_queues(q, false); } } +EXPORT_SYMBOL_GPL(blk_mq_freeze_queue_start); static void blk_mq_freeze_queue_wait(struct request_queue *q) { @@ -136,7 +137,7 @@ void blk_mq_freeze_queue(struct request_queue *q) blk_mq_freeze_queue_wait(q); } -static void blk_mq_unfreeze_queue(struct request_queue *q) +void blk_mq_unfreeze_queue(struct request_queue *q) { bool wake; @@ -149,6 +150,24 @@ static void blk_mq_unfreeze_queue(struct request_queue *q) wake_up_all(&q->mq_freeze_wq); } } +EXPORT_SYMBOL_GPL(blk_mq_unfreeze_queue); + +void blk_mq_wake_waiters(struct request_queue *q) +{ + struct blk_mq_hw_ctx *hctx; + unsigned int i; + + queue_for_each_hw_ctx(q, hctx, i) + if (blk_mq_hw_queue_mapped(hctx)) + blk_mq_tag_wakeup_all(hctx->tags, true); + + /* + * If we are called because the queue has now been marked as + * dying, we need to ensure that processes currently waiting on + * the queue are notified as well. + */ + wake_up_all(&q->mq_freeze_wq); +} bool blk_mq_can_queue(struct blk_mq_hw_ctx *hctx) { @@ -258,8 +277,10 @@ struct request *blk_mq_alloc_request(struct request_queue *q, int rw, gfp_t gfp, ctx = alloc_data.ctx; } blk_mq_put_ctx(ctx); - if (!rq) + if (!rq) { + blk_mq_queue_exit(q); return ERR_PTR(-EWOULDBLOCK); + } return rq; } EXPORT_SYMBOL(blk_mq_alloc_request); @@ -383,6 +404,12 @@ void blk_mq_complete_request(struct request *rq) } EXPORT_SYMBOL(blk_mq_complete_request); +int blk_mq_request_started(struct request *rq) +{ + return test_bit(REQ_ATOM_STARTED, &rq->atomic_flags); +} +EXPORT_SYMBOL_GPL(blk_mq_request_started); + void blk_mq_start_request(struct request *rq) { struct request_queue *q = rq->q; @@ -500,12 +527,38 @@ void blk_mq_add_to_requeue_list(struct request *rq, bool at_head) } EXPORT_SYMBOL(blk_mq_add_to_requeue_list); +void blk_mq_cancel_requeue_work(struct request_queue *q) +{ + cancel_work_sync(&q->requeue_work); +} +EXPORT_SYMBOL_GPL(blk_mq_cancel_requeue_work); + void blk_mq_kick_requeue_list(struct request_queue *q) { kblockd_schedule_work(&q->requeue_work); } EXPORT_SYMBOL(blk_mq_kick_requeue_list); +void blk_mq_abort_requeue_list(struct request_queue *q) +{ + unsigned long flags; + LIST_HEAD(rq_list); + + spin_lock_irqsave(&q->requeue_lock, flags); + list_splice_init(&q->requeue_list, &rq_list); + spin_unlock_irqrestore(&q->requeue_lock, flags); + + while (!list_empty(&rq_list)) { + struct request *rq; + + rq = list_first_entry(&rq_list, struct request, queuelist); + list_del_init(&rq->queuelist); + rq->errors = -EIO; + blk_mq_end_request(rq, rq->errors); + } +} +EXPORT_SYMBOL(blk_mq_abort_requeue_list); + static inline bool is_flush_request(struct request *rq, struct blk_flush_queue *fq, unsigned int tag) { @@ -566,13 +619,24 @@ void blk_mq_rq_timed_out(struct request *req, bool reserved) break; } } - + static void blk_mq_check_expired(struct blk_mq_hw_ctx *hctx, struct request *rq, void *priv, bool reserved) { struct blk_mq_timeout_data *data = priv; - if (!test_bit(REQ_ATOM_STARTED, &rq->atomic_flags)) + if (!test_bit(REQ_ATOM_STARTED, &rq->atomic_flags)) { + /* + * If a request wasn't started before the queue was + * marked dying, kill it here or it'll go unnoticed. + */ + if (unlikely(blk_queue_dying(rq->q))) { + rq->errors = -EIO; + blk_mq_complete_request(rq); + } + return; + } + if (rq->cmd_flags & REQ_NO_TIMEOUT) return; if (time_after_eq(jiffies, rq->deadline)) { @@ -1601,7 +1665,6 @@ static int blk_mq_init_hctx(struct request_queue *q, hctx->queue = q; hctx->queue_num = hctx_idx; hctx->flags = set->flags; - hctx->cmd_size = set->cmd_size; blk_mq_init_cpu_notifier(&hctx->cpu_notifier, blk_mq_hctx_notify, hctx); diff --git a/block/blk-mq.h b/block/blk-mq.h index 206230e64f79..4f4f943c22c3 100644 --- a/block/blk-mq.h +++ b/block/blk-mq.h @@ -32,6 +32,7 @@ void blk_mq_free_queue(struct request_queue *q); void blk_mq_clone_flush_request(struct request *flush_rq, struct request *orig_rq); int blk_mq_update_nr_requests(struct request_queue *q, unsigned int nr); +void blk_mq_wake_waiters(struct request_queue *q); /* * CPU hotplug helpers diff --git a/block/blk-timeout.c b/block/blk-timeout.c index 56c025894cdf..246dfb16c3d9 100644 --- a/block/blk-timeout.c +++ b/block/blk-timeout.c @@ -190,6 +190,9 @@ void blk_add_timer(struct request *req) struct request_queue *q = req->q; unsigned long expiry; + if (req->cmd_flags & REQ_NO_TIMEOUT) + return; + /* blk-mq has its own handler, so we don't need ->rq_timed_out_fn */ if (!q->mq_ops && !q->rq_timed_out_fn) return; diff --git a/crypto/aes_generic.c b/crypto/aes_generic.c index 9b3c54c1cbe8..3dd101144a58 100644 --- a/crypto/aes_generic.c +++ b/crypto/aes_generic.c @@ -1475,3 +1475,4 @@ module_exit(aes_fini); MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm"); MODULE_LICENSE("Dual BSD/GPL"); MODULE_ALIAS_CRYPTO("aes"); +MODULE_ALIAS_CRYPTO("aes-generic"); diff --git a/crypto/ansi_cprng.c b/crypto/ansi_cprng.c index b4485a108389..6f5bebc9bf01 100644 --- a/crypto/ansi_cprng.c +++ b/crypto/ansi_cprng.c @@ -477,3 +477,4 @@ MODULE_PARM_DESC(dbg, "Boolean to enable debugging (0/1 == off/on)"); module_init(prng_mod_init); module_exit(prng_mod_fini); MODULE_ALIAS_CRYPTO("stdrng"); +MODULE_ALIAS_CRYPTO("ansi_cprng"); diff --git a/crypto/blowfish_generic.c b/crypto/blowfish_generic.c index 7bd71f02d0dd..87b392a77a93 100644 --- a/crypto/blowfish_generic.c +++ b/crypto/blowfish_generic.c @@ -139,3 +139,4 @@ module_exit(blowfish_mod_fini); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Blowfish Cipher Algorithm"); MODULE_ALIAS_CRYPTO("blowfish"); +MODULE_ALIAS_CRYPTO("blowfish-generic"); diff --git a/crypto/camellia_generic.c b/crypto/camellia_generic.c index 1b74c5a3e891..a02286bf319e 100644 --- a/crypto/camellia_generic.c +++ b/crypto/camellia_generic.c @@ -1099,3 +1099,4 @@ module_exit(camellia_fini); MODULE_DESCRIPTION("Camellia Cipher Algorithm"); MODULE_LICENSE("GPL"); MODULE_ALIAS_CRYPTO("camellia"); +MODULE_ALIAS_CRYPTO("camellia-generic"); diff --git a/crypto/cast5_generic.c b/crypto/cast5_generic.c index 84c86db67ec7..df5c72629383 100644 --- a/crypto/cast5_generic.c +++ b/crypto/cast5_generic.c @@ -550,3 +550,4 @@ module_exit(cast5_mod_fini); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Cast5 Cipher Algorithm"); MODULE_ALIAS_CRYPTO("cast5"); +MODULE_ALIAS_CRYPTO("cast5-generic"); diff --git a/crypto/cast6_generic.c b/crypto/cast6_generic.c index f408f0bd8de2..058c8d755d03 100644 --- a/crypto/cast6_generic.c +++ b/crypto/cast6_generic.c @@ -292,3 +292,4 @@ module_exit(cast6_mod_fini); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Cast6 Cipher Algorithm"); MODULE_ALIAS_CRYPTO("cast6"); +MODULE_ALIAS_CRYPTO("cast6-generic"); diff --git a/crypto/crc32c_generic.c b/crypto/crc32c_generic.c index 2a062025749d..06f1b60f02b2 100644 --- a/crypto/crc32c_generic.c +++ b/crypto/crc32c_generic.c @@ -171,4 +171,5 @@ MODULE_AUTHOR("Clay Haapala <chaapala@cisco.com>"); MODULE_DESCRIPTION("CRC32c (Castagnoli) calculations wrapper for lib/crc32c"); MODULE_LICENSE("GPL"); MODULE_ALIAS_CRYPTO("crc32c"); +MODULE_ALIAS_CRYPTO("crc32c-generic"); MODULE_SOFTDEP("pre: crc32c"); diff --git a/crypto/crct10dif_generic.c b/crypto/crct10dif_generic.c index 08bb4f504520..c1229614c7e3 100644 --- a/crypto/crct10dif_generic.c +++ b/crypto/crct10dif_generic.c @@ -125,3 +125,4 @@ MODULE_AUTHOR("Tim Chen <tim.c.chen@linux.intel.com>"); MODULE_DESCRIPTION("T10 DIF CRC calculation."); MODULE_LICENSE("GPL"); MODULE_ALIAS_CRYPTO("crct10dif"); +MODULE_ALIAS_CRYPTO("crct10dif-generic"); diff --git a/crypto/des_generic.c b/crypto/des_generic.c index 42912948776b..a71720544d11 100644 --- a/crypto/des_generic.c +++ b/crypto/des_generic.c @@ -983,8 +983,6 @@ static struct crypto_alg des_algs[2] = { { .cia_decrypt = des3_ede_decrypt } } } }; -MODULE_ALIAS_CRYPTO("des3_ede"); - static int __init des_generic_mod_init(void) { return crypto_register_algs(des_algs, ARRAY_SIZE(des_algs)); @@ -1001,4 +999,7 @@ module_exit(des_generic_mod_fini); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms"); MODULE_AUTHOR("Dag Arne Osvik <da@osvik.no>"); -MODULE_ALIAS("des"); +MODULE_ALIAS_CRYPTO("des"); +MODULE_ALIAS_CRYPTO("des-generic"); +MODULE_ALIAS_CRYPTO("des3_ede"); +MODULE_ALIAS_CRYPTO("des3_ede-generic"); diff --git a/crypto/ghash-generic.c b/crypto/ghash-generic.c index 4e97fae9666f..bac70995e064 100644 --- a/crypto/ghash-generic.c +++ b/crypto/ghash-generic.c @@ -173,3 +173,4 @@ module_exit(ghash_mod_exit); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("GHASH Message Digest Algorithm"); MODULE_ALIAS_CRYPTO("ghash"); +MODULE_ALIAS_CRYPTO("ghash-generic"); diff --git a/crypto/krng.c b/crypto/krng.c index 67c88b331210..0224841b6579 100644 --- a/crypto/krng.c +++ b/crypto/krng.c @@ -63,3 +63,4 @@ module_exit(krng_mod_fini); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Kernel Random Number Generator"); MODULE_ALIAS_CRYPTO("stdrng"); +MODULE_ALIAS_CRYPTO("krng"); diff --git a/crypto/salsa20_generic.c b/crypto/salsa20_generic.c index 3d0f9df30ac9..f550b5d94630 100644 --- a/crypto/salsa20_generic.c +++ b/crypto/salsa20_generic.c @@ -249,3 +249,4 @@ module_exit(salsa20_generic_mod_fini); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION ("Salsa20 stream cipher algorithm"); MODULE_ALIAS_CRYPTO("salsa20"); +MODULE_ALIAS_CRYPTO("salsa20-generic"); diff --git a/crypto/serpent_generic.c b/crypto/serpent_generic.c index a53b5e2af335..94970a794975 100644 --- a/crypto/serpent_generic.c +++ b/crypto/serpent_generic.c @@ -667,3 +667,4 @@ MODULE_DESCRIPTION("Serpent and tnepres (kerneli compatible serpent reversed) Ci MODULE_AUTHOR("Dag Arne Osvik <osvik@ii.uib.no>"); MODULE_ALIAS_CRYPTO("tnepres"); MODULE_ALIAS_CRYPTO("serpent"); +MODULE_ALIAS_CRYPTO("serpent-generic"); diff --git a/crypto/sha1_generic.c b/crypto/sha1_generic.c index 039e58cfa155..a3e50c37eb6f 100644 --- a/crypto/sha1_generic.c +++ b/crypto/sha1_generic.c @@ -154,3 +154,4 @@ MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm"); MODULE_ALIAS_CRYPTO("sha1"); +MODULE_ALIAS_CRYPTO("sha1-generic"); diff --git a/crypto/sha256_generic.c b/crypto/sha256_generic.c index 5eb21b120033..b001ff5c2efc 100644 --- a/crypto/sha256_generic.c +++ b/crypto/sha256_generic.c @@ -385,4 +385,6 @@ MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("SHA-224 and SHA-256 Secure Hash Algorithm"); MODULE_ALIAS_CRYPTO("sha224"); +MODULE_ALIAS_CRYPTO("sha224-generic"); MODULE_ALIAS_CRYPTO("sha256"); +MODULE_ALIAS_CRYPTO("sha256-generic"); diff --git a/crypto/sha512_generic.c b/crypto/sha512_generic.c index 8d0b19ed4f4b..1c3c3767e079 100644 --- a/crypto/sha512_generic.c +++ b/crypto/sha512_generic.c @@ -289,4 +289,6 @@ MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("SHA-512 and SHA-384 Secure Hash Algorithms"); MODULE_ALIAS_CRYPTO("sha384"); +MODULE_ALIAS_CRYPTO("sha384-generic"); MODULE_ALIAS_CRYPTO("sha512"); +MODULE_ALIAS_CRYPTO("sha512-generic"); diff --git a/crypto/tea.c b/crypto/tea.c index 495be2d0077d..b70b441c7d1e 100644 --- a/crypto/tea.c +++ b/crypto/tea.c @@ -270,6 +270,7 @@ static void __exit tea_mod_fini(void) crypto_unregister_algs(tea_algs, ARRAY_SIZE(tea_algs)); } +MODULE_ALIAS_CRYPTO("tea"); MODULE_ALIAS_CRYPTO("xtea"); MODULE_ALIAS_CRYPTO("xeta"); diff --git a/crypto/tgr192.c b/crypto/tgr192.c index 6e5651c66cf8..321bc6ff2a9d 100644 --- a/crypto/tgr192.c +++ b/crypto/tgr192.c @@ -676,6 +676,7 @@ static void __exit tgr192_mod_fini(void) crypto_unregister_shashes(tgr_algs, ARRAY_SIZE(tgr_algs)); } +MODULE_ALIAS_CRYPTO("tgr192"); MODULE_ALIAS_CRYPTO("tgr160"); MODULE_ALIAS_CRYPTO("tgr128"); diff --git a/crypto/twofish_generic.c b/crypto/twofish_generic.c index 523ad8c4e359..ebf7a3efb572 100644 --- a/crypto/twofish_generic.c +++ b/crypto/twofish_generic.c @@ -212,3 +212,4 @@ module_exit(twofish_mod_fini); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION ("Twofish Cipher Algorithm"); MODULE_ALIAS_CRYPTO("twofish"); +MODULE_ALIAS_CRYPTO("twofish-generic"); diff --git a/crypto/wp512.c b/crypto/wp512.c index 0de42eb3d040..7ee5a043a988 100644 --- a/crypto/wp512.c +++ b/crypto/wp512.c @@ -1167,6 +1167,7 @@ static void __exit wp512_mod_fini(void) crypto_unregister_shashes(wp_algs, ARRAY_SIZE(wp_algs)); } +MODULE_ALIAS_CRYPTO("wp512"); MODULE_ALIAS_CRYPTO("wp384"); MODULE_ALIAS_CRYPTO("wp256"); diff --git a/drivers/Makefile b/drivers/Makefile index 67d2334dc41e..527a6da8d539 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -50,7 +50,10 @@ obj-$(CONFIG_RESET_CONTROLLER) += reset/ obj-y += tty/ obj-y += char/ -# gpu/ comes after char for AGP vs DRM startup +# iommu/ comes before gpu as gpu are using iommu controllers +obj-$(CONFIG_IOMMU_SUPPORT) += iommu/ + +# gpu/ comes after char for AGP vs DRM startup and after iommu obj-y += gpu/ obj-$(CONFIG_CONNECTOR) += connector/ @@ -141,7 +144,6 @@ obj-y += clk/ obj-$(CONFIG_MAILBOX) += mailbox/ obj-$(CONFIG_HWSPINLOCK) += hwspinlock/ -obj-$(CONFIG_IOMMU_SUPPORT) += iommu/ obj-$(CONFIG_REMOTEPROC) += remoteproc/ obj-$(CONFIG_RPMSG) += rpmsg/ diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c index 1fdf5e07a1c7..1020b1b53a17 100644 --- a/drivers/acpi/acpi_processor.c +++ b/drivers/acpi/acpi_processor.c @@ -170,7 +170,7 @@ static int acpi_processor_hotadd_init(struct acpi_processor *pr) acpi_status status; int ret; - if (pr->apic_id == -1) + if (pr->phys_id == -1) return -ENODEV; status = acpi_evaluate_integer(pr->handle, "_STA", NULL, &sta); @@ -180,13 +180,13 @@ static int acpi_processor_hotadd_init(struct acpi_processor *pr) cpu_maps_update_begin(); cpu_hotplug_begin(); - ret = acpi_map_lsapic(pr->handle, pr->apic_id, &pr->id); + ret = acpi_map_cpu(pr->handle, pr->phys_id, &pr->id); if (ret) goto out; ret = arch_register_cpu(pr->id); if (ret) { - acpi_unmap_lsapic(pr->id); + acpi_unmap_cpu(pr->id); goto out; } @@ -215,7 +215,7 @@ static int acpi_processor_get_info(struct acpi_device *device) union acpi_object object = { 0 }; struct acpi_buffer buffer = { sizeof(union acpi_object), &object }; struct acpi_processor *pr = acpi_driver_data(device); - int apic_id, cpu_index, device_declaration = 0; + int phys_id, cpu_index, device_declaration = 0; acpi_status status = AE_OK; static int cpu0_initialized; unsigned long long value; @@ -262,15 +262,18 @@ static int acpi_processor_get_info(struct acpi_device *device) pr->acpi_id = value; } - apic_id = acpi_get_apicid(pr->handle, device_declaration, pr->acpi_id); - if (apic_id < 0) - acpi_handle_debug(pr->handle, "failed to get CPU APIC ID.\n"); - pr->apic_id = apic_id; + phys_id = acpi_get_phys_id(pr->handle, device_declaration, pr->acpi_id); + if (phys_id < 0) + acpi_handle_debug(pr->handle, "failed to get CPU physical ID.\n"); + pr->phys_id = phys_id; - cpu_index = acpi_map_cpuid(pr->apic_id, pr->acpi_id); + cpu_index = acpi_map_cpuid(pr->phys_id, pr->acpi_id); if (!cpu0_initialized && !acpi_has_cpu_in_madt()) { cpu0_initialized = 1; - /* Handle UP system running SMP kernel, with no LAPIC in MADT */ + /* + * Handle UP system running SMP kernel, with no CPU + * entry in MADT + */ if ((cpu_index == -1) && (num_online_cpus() == 1)) cpu_index = 0; } @@ -458,7 +461,7 @@ static void acpi_processor_remove(struct acpi_device *device) /* Remove the CPU. */ arch_unregister_cpu(pr->id); - acpi_unmap_lsapic(pr->id); + acpi_unmap_cpu(pr->id); cpu_hotplug_done(); cpu_maps_update_done(); diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c index c2daa85fc9f7..c0d44d394ca3 100644 --- a/drivers/acpi/device_pm.c +++ b/drivers/acpi/device_pm.c @@ -257,7 +257,7 @@ int acpi_bus_init_power(struct acpi_device *device) device->power.state = ACPI_STATE_UNKNOWN; if (!acpi_device_is_present(device)) - return 0; + return -ENXIO; result = acpi_device_get_power(device, &state); if (result) diff --git a/drivers/acpi/int340x_thermal.c b/drivers/acpi/int340x_thermal.c index a27d31d1ba24..9dcf83682e36 100644 --- a/drivers/acpi/int340x_thermal.c +++ b/drivers/acpi/int340x_thermal.c @@ -14,10 +14,10 @@ #include "internal.h" -#define DO_ENUMERATION 0x01 +#define INT3401_DEVICE 0X01 static const struct acpi_device_id int340x_thermal_device_ids[] = { - {"INT3400", DO_ENUMERATION }, - {"INT3401"}, + {"INT3400"}, + {"INT3401", INT3401_DEVICE}, {"INT3402"}, {"INT3403"}, {"INT3404"}, @@ -34,7 +34,10 @@ static int int340x_thermal_handler_attach(struct acpi_device *adev, const struct acpi_device_id *id) { #if defined(CONFIG_INT340X_THERMAL) || defined(CONFIG_INT340X_THERMAL_MODULE) - if (id->driver_data == DO_ENUMERATION) + acpi_create_platform_device(adev); +#elif defined(INTEL_SOC_DTS_THERMAL) || defined(INTEL_SOC_DTS_THERMAL_MODULE) + /* Intel SoC DTS thermal driver needs INT3401 to set IRQ descriptor */ + if (id->driver_data == INT3401_DEVICE) acpi_create_platform_device(adev); #endif return 1; diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 342942f90a10..02e48394276c 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -69,7 +69,7 @@ static int map_madt_entry(int type, u32 acpi_id) unsigned long madt_end, entry; static struct acpi_table_madt *madt; static int read_madt; - int apic_id = -1; + int phys_id = -1; /* CPU hardware ID */ if (!read_madt) { if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_MADT, 0, @@ -79,7 +79,7 @@ static int map_madt_entry(int type, u32 acpi_id) } if (!madt) - return apic_id; + return phys_id; entry = (unsigned long)madt; madt_end = entry + madt->header.length; @@ -91,18 +91,18 @@ static int map_madt_entry(int type, u32 acpi_id) struct acpi_subtable_header *header = (struct acpi_subtable_header *)entry; if (header->type == ACPI_MADT_TYPE_LOCAL_APIC) { - if (!map_lapic_id(header, acpi_id, &apic_id)) + if (!map_lapic_id(header, acpi_id, &phys_id)) break; } else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) { - if (!map_x2apic_id(header, type, acpi_id, &apic_id)) + if (!map_x2apic_id(header, type, acpi_id, &phys_id)) break; } else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) { - if (!map_lsapic_id(header, type, acpi_id, &apic_id)) + if (!map_lsapic_id(header, type, acpi_id, &phys_id)) break; } entry += header->length; } - return apic_id; + return phys_id; } static int map_mat_entry(acpi_handle handle, int type, u32 acpi_id) @@ -110,7 +110,7 @@ static int map_mat_entry(acpi_handle handle, int type, u32 acpi_id) struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; union acpi_object *obj; struct acpi_subtable_header *header; - int apic_id = -1; + int phys_id = -1; if (ACPI_FAILURE(acpi_evaluate_object(handle, "_MAT", NULL, &buffer))) goto exit; @@ -126,38 +126,38 @@ static int map_mat_entry(acpi_handle handle, int type, u32 acpi_id) header = (struct acpi_subtable_header *)obj->buffer.pointer; if (header->type == ACPI_MADT_TYPE_LOCAL_APIC) - map_lapic_id(header, acpi_id, &apic_id); + map_lapic_id(header, acpi_id, &phys_id); else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) - map_lsapic_id(header, type, acpi_id, &apic_id); + map_lsapic_id(header, type, acpi_id, &phys_id); else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) - map_x2apic_id(header, type, acpi_id, &apic_id); + map_x2apic_id(header, type, acpi_id, &phys_id); exit: kfree(buffer.pointer); - return apic_id; + return phys_id; } -int acpi_get_apicid(acpi_handle handle, int type, u32 acpi_id) +int acpi_get_phys_id(acpi_handle handle, int type, u32 acpi_id) { - int apic_id; + int phys_id; - apic_id = map_mat_entry(handle, type, acpi_id); - if (apic_id == -1) - apic_id = map_madt_entry(type, acpi_id); + phys_id = map_mat_entry(handle, type, acpi_id); + if (phys_id == -1) + phys_id = map_madt_entry(type, acpi_id); - return apic_id; + return phys_id; } -int acpi_map_cpuid(int apic_id, u32 acpi_id) +int acpi_map_cpuid(int phys_id, u32 acpi_id) { #ifdef CONFIG_SMP int i; #endif - if (apic_id == -1) { + if (phys_id == -1) { /* * On UP processor, there is no _MAT or MADT table. - * So above apic_id is always set to -1. + * So above phys_id is always set to -1. * * BIOS may define multiple CPU handles even for UP processor. * For example, @@ -170,7 +170,7 @@ int acpi_map_cpuid(int apic_id, u32 acpi_id) * Processor (CPU3, 0x03, 0x00000410, 0x06) {} * } * - * Ignores apic_id and always returns 0 for the processor + * Ignores phys_id and always returns 0 for the processor * handle with acpi id 0 if nr_cpu_ids is 1. * This should be the case if SMP tables are not found. * Return -1 for other CPU's handle. @@ -178,28 +178,28 @@ int acpi_map_cpuid(int apic_id, u32 acpi_id) if (nr_cpu_ids <= 1 && acpi_id == 0) return acpi_id; else - return apic_id; + return phys_id; } #ifdef CONFIG_SMP for_each_possible_cpu(i) { - if (cpu_physical_id(i) == apic_id) + if (cpu_physical_id(i) == phys_id) return i; } #else /* In UP kernel, only processor 0 is valid */ - if (apic_id == 0) - return apic_id; + if (phys_id == 0) + return phys_id; #endif return -1; } int acpi_get_cpuid(acpi_handle handle, int type, u32 acpi_id) { - int apic_id; + int phys_id; - apic_id = acpi_get_apicid(handle, type, acpi_id); + phys_id = acpi_get_phys_id(handle, type, acpi_id); - return acpi_map_cpuid(apic_id, acpi_id); + return acpi_map_cpuid(phys_id, acpi_id); } EXPORT_SYMBOL_GPL(acpi_get_cpuid); diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 16914cc30882..dc4d8960684a 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1001,7 +1001,7 @@ static void acpi_free_power_resources_lists(struct acpi_device *device) if (device->wakeup.flags.valid) acpi_power_resources_list_free(&device->wakeup.resources); - if (!device->flags.power_manageable) + if (!device->power.flags.power_resources) return; for (i = ACPI_STATE_D0; i <= ACPI_STATE_D3_HOT; i++) { @@ -1744,10 +1744,8 @@ static void acpi_bus_get_power_flags(struct acpi_device *device) device->power.flags.power_resources) device->power.states[ACPI_STATE_D3_COLD].flags.os_accessible = 1; - if (acpi_bus_init_power(device)) { - acpi_free_power_resources_lists(device); + if (acpi_bus_init_power(device)) device->flags.power_manageable = 0; - } } static void acpi_bus_get_flags(struct acpi_device *device) @@ -2371,13 +2369,18 @@ static void acpi_bus_attach(struct acpi_device *device) /* Skip devices that are not present. */ if (!acpi_device_is_present(device)) { device->flags.visited = false; + device->flags.power_manageable = 0; return; } if (device->handler) goto ok; if (!device->flags.initialized) { - acpi_bus_update_power(device, NULL); + device->flags.power_manageable = + device->power.states[ACPI_STATE_D0].flags.valid; + if (acpi_bus_init_power(device)) + device->flags.power_manageable = 0; + device->flags.initialized = true; } device->flags.visited = false; diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index c72e79d2c5ad..032db459370f 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c @@ -522,6 +522,16 @@ static struct dmi_system_id video_dmi_table[] __initdata = { DMI_MATCH(DMI_PRODUCT_NAME, "370R4E/370R4V/370R5E/3570RE/370R5V"), }, }, + + { + /* https://bugzilla.redhat.com/show_bug.cgi?id=1163574 */ + .callback = video_disable_native_backlight, + .ident = "Dell XPS15 L521X", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "XPS L521X"), + }, + }, {} }; diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index a3a13605a9c4..5f601553b9b0 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -835,6 +835,7 @@ config PATA_AT32 config PATA_AT91 tristate "PATA support for AT91SAM9260" depends on ARM && SOC_AT91SAM9 + depends on !ARCH_MULTIPLATFORM help This option enables support for IDE devices on the Atmel AT91SAM9260 SoC. diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 49f1e6890587..33bb06e006c9 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -325,7 +325,6 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */ { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */ { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */ - { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */ { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */ { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c index feeb8f1e2fe8..cbcd20810355 100644 --- a/drivers/ata/ahci_xgene.c +++ b/drivers/ata/ahci_xgene.c @@ -125,10 +125,11 @@ static int xgene_ahci_restart_engine(struct ata_port *ap) * xgene_ahci_qc_issue - Issue commands to the device * @qc: Command to issue * - * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot - * clear the BSY bit after receiving the PIO setup FIS. This results in the dma - * state machine goes into the CMFatalErrorUpdate state and locks up. By - * restarting the dma engine, it removes the controller out of lock up state. + * Due to Hardware errata for IDENTIFY DEVICE command and PACKET + * command of ATAPI protocol set, the controller cannot clear the BSY bit + * after receiving the PIO setup FIS. This results in the DMA state machine + * going into the CMFatalErrorUpdate state and locks up. By restarting the + * DMA engine, it removes the controller out of lock up state. */ static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc) { @@ -137,7 +138,8 @@ static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc) struct xgene_ahci_context *ctx = hpriv->plat_data; int rc = 0; - if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA)) + if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) || + (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET))) xgene_ahci_restart_engine(ap); rc = ahci_qc_issue(qc); @@ -188,7 +190,7 @@ static unsigned int xgene_ahci_read_id(struct ata_device *dev, * * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP */ - id[ATA_ID_FEATURE_SUPP] &= ~(1 << 8); + id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8)); return 0; } diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index 97683e45ab04..61a9c07e0dff 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -2003,7 +2003,7 @@ static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) devslp = readl(port_mmio + PORT_DEVSLP); if (!(devslp & PORT_DEVSLP_DSP)) { - dev_err(ap->host->dev, "port does not support device sleep\n"); + dev_info(ap->host->dev, "port does not support device sleep\n"); return; } diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 5c84fb5c3372..d1a05f9bb91f 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -4233,10 +4233,33 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { { "PIONEER DVD-RW DVR-216D", NULL, ATA_HORKAGE_NOSETXFER }, /* devices that don't properly handle queued TRIM commands */ - { "Micron_M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, }, - { "Crucial_CT???M500SSD*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, }, - { "Micron_M550*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, }, - { "Crucial_CT*M550SSD*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, }, + { "Micron_M[56]*", NULL, ATA_HORKAGE_NO_NCQ_TRIM | + ATA_HORKAGE_ZERO_AFTER_TRIM, }, + { "Crucial_CT*SSD*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, }, + + /* + * As defined, the DRAT (Deterministic Read After Trim) and RZAT + * (Return Zero After Trim) flags in the ATA Command Set are + * unreliable in the sense that they only define what happens if + * the device successfully executed the DSM TRIM command. TRIM + * is only advisory, however, and the device is free to silently + * ignore all or parts of the request. + * + * Whitelist drives that are known to reliably return zeroes + * after TRIM. + */ + + /* + * The intel 510 drive has buggy DRAT/RZAT. Explicitly exclude + * that model before whitelisting all other intel SSDs. + */ + { "INTEL*SSDSC2MH*", NULL, 0, }, + + { "INTEL*SSD*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, + { "SSD*INTEL*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, + { "Samsung*SSD*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, + { "SAMSUNG*SSD*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, + { "ST[1248][0248]0[FH]*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, /* * Some WD SATA-I drives spin up and down erratically when the link @@ -4748,7 +4771,10 @@ static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap) return NULL; for (i = 0, tag = ap->last_tag + 1; i < max_queue; i++, tag++) { - tag = tag < max_queue ? tag : 0; + if (ap->flags & ATA_FLAG_LOWTAG) + tag = i; + else + tag = tag < max_queue ? tag : 0; /* the last tag is reserved for internal command. */ if (tag == ATA_TAG_INTERNAL) diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index 3dbec8954c86..8d00c2638bed 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c @@ -2389,6 +2389,7 @@ const char *ata_get_cmd_descript(u8 command) return NULL; } +EXPORT_SYMBOL_GPL(ata_get_cmd_descript); /** * ata_eh_link_report - report error handling to user diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index e364e86e84d7..6abd17a85b13 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -2532,13 +2532,15 @@ static unsigned int ata_scsiop_read_cap(struct ata_scsi_args *args, u8 *rbuf) rbuf[15] = lowest_aligned; if (ata_id_has_trim(args->id)) { - rbuf[14] |= 0x80; /* TPE */ + rbuf[14] |= 0x80; /* LBPME */ - if (ata_id_has_zero_after_trim(args->id)) - rbuf[14] |= 0x40; /* TPRZ */ + if (ata_id_has_zero_after_trim(args->id) && + dev->horkage & ATA_HORKAGE_ZERO_AFTER_TRIM) { + ata_dev_info(dev, "Enabling discard_zeroes_data\n"); + rbuf[14] |= 0x40; /* LBPRZ */ + } } } - return 0; } diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c index db90aa35cb71..2e86e3b85266 100644 --- a/drivers/ata/libata-sff.c +++ b/drivers/ata/libata-sff.c @@ -1333,7 +1333,19 @@ void ata_sff_flush_pio_task(struct ata_port *ap) DPRINTK("ENTER\n"); cancel_delayed_work_sync(&ap->sff_pio_task); + + /* + * We wanna reset the HSM state to IDLE. If we do so without + * grabbing the port lock, critical sections protected by it which + * expect the HSM state to stay stable may get surprised. For + * example, we may set IDLE in between the time + * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls + * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG(). + */ + spin_lock_irq(ap->lock); ap->hsm_task_state = HSM_ST_IDLE; + spin_unlock_irq(ap->lock); + ap->sff_pio_task_link = NULL; if (ata_msg_ctl(ap)) diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c index c7ddef89e7b0..8e8248179d20 100644 --- a/drivers/ata/sata_dwc_460ex.c +++ b/drivers/ata/sata_dwc_460ex.c @@ -797,7 +797,7 @@ static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq) if (err) { dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns" " %d\n", __func__, err); - goto error_out; + return err; } /* Enabe DMA */ @@ -808,11 +808,6 @@ static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq) sata_dma_regs); return 0; - -error_out: - dma_dwc_exit(hsdev); - - return err; } static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val) @@ -1662,7 +1657,7 @@ static int sata_dwc_probe(struct platform_device *ofdev) char *ver = (char *)&versionr; u8 *base = NULL; int err = 0; - int irq, rc; + int irq; struct ata_host *host; struct ata_port_info pi = sata_dwc_port_info[0]; const struct ata_port_info *ppi[] = { &pi, NULL }; @@ -1725,7 +1720,7 @@ static int sata_dwc_probe(struct platform_device *ofdev) if (irq == NO_IRQ) { dev_err(&ofdev->dev, "no SATA DMA irq\n"); err = -ENODEV; - goto error_out; + goto error_iomap; } /* Get physical SATA DMA register base address */ @@ -1734,14 +1729,16 @@ static int sata_dwc_probe(struct platform_device *ofdev) dev_err(&ofdev->dev, "ioremap failed for AHBDMA register" " address\n"); err = -ENODEV; - goto error_out; + goto error_iomap; } /* Save dev for later use in dev_xxx() routines */ host_pvt.dwc_dev = &ofdev->dev; /* Initialize AHB DMAC */ - dma_dwc_init(hsdev, irq); + err = dma_dwc_init(hsdev, irq); + if (err) + goto error_dma_iomap; /* Enable SATA Interrupts */ sata_dwc_enable_interrupts(hsdev); @@ -1759,9 +1756,8 @@ static int sata_dwc_probe(struct platform_device *ofdev) * device discovery process, invoking our port_start() handler & * error_handler() to execute a dummy Softreset EH session */ - rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht); - - if (rc != 0) + err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht); + if (err) dev_err(&ofdev->dev, "failed to activate host"); dev_set_drvdata(&ofdev->dev, host); @@ -1770,7 +1766,8 @@ static int sata_dwc_probe(struct platform_device *ofdev) error_out: /* Free SATA DMA resources */ dma_dwc_exit(hsdev); - +error_dma_iomap: + iounmap((void __iomem *)host_pvt.sata_dma_regs); error_iomap: iounmap(base); error_kmalloc: @@ -1791,6 +1788,7 @@ static int sata_dwc_remove(struct platform_device *ofdev) /* Free SATA DMA resources */ dma_dwc_exit(hsdev); + iounmap((void __iomem *)host_pvt.sata_dma_regs); iounmap(hsdev->reg_base); kfree(hsdev); kfree(host); diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c index d81b20ddb527..ea655949023f 100644 --- a/drivers/ata/sata_sil24.c +++ b/drivers/ata/sata_sil24.c @@ -246,7 +246,7 @@ enum { /* host flags */ SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA | - ATA_FLAG_AN | ATA_FLAG_PMP, + ATA_FLAG_AN | ATA_FLAG_PMP | ATA_FLAG_LOWTAG, SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ IRQ_STAT_4PORTS = 0xf, diff --git a/drivers/block/null_blk.c b/drivers/block/null_blk.c index ae9f615382f6..aa2224aa7caa 100644 --- a/drivers/block/null_blk.c +++ b/drivers/block/null_blk.c @@ -530,7 +530,7 @@ static int null_add_dev(void) goto out_cleanup_queues; nullb->q = blk_mq_init_queue(&nullb->tag_set); - if (!nullb->q) { + if (IS_ERR(nullb->q)) { rv = -ENOMEM; goto out_cleanup_tags; } diff --git a/drivers/block/nvme-core.c b/drivers/block/nvme-core.c index b1d5d8797315..cb529e9a82dd 100644 --- a/drivers/block/nvme-core.c +++ b/drivers/block/nvme-core.c @@ -215,6 +215,7 @@ static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, cmd->fn = handler; cmd->ctx = ctx; cmd->aborted = 0; + blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); } /* Special values must be less than 0x1000 */ @@ -431,8 +432,13 @@ static void req_completion(struct nvme_queue *nvmeq, void *ctx, if (unlikely(status)) { if (!(status & NVME_SC_DNR || blk_noretry_request(req)) && (jiffies - req->start_time) < req->timeout) { + unsigned long flags; + blk_mq_requeue_request(req); - blk_mq_kick_requeue_list(req->q); + spin_lock_irqsave(req->q->queue_lock, flags); + if (!blk_queue_stopped(req->q)) + blk_mq_kick_requeue_list(req->q); + spin_unlock_irqrestore(req->q->queue_lock, flags); return; } req->errors = nvme_error_status(status); @@ -664,8 +670,6 @@ static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, } } - blk_mq_start_request(req); - nvme_set_info(cmd, iod, req_completion); spin_lock_irq(&nvmeq->q_lock); if (req->cmd_flags & REQ_DISCARD) @@ -835,6 +839,7 @@ static int nvme_submit_async_admin_req(struct nvme_dev *dev) if (IS_ERR(req)) return PTR_ERR(req); + req->cmd_flags |= REQ_NO_TIMEOUT; cmd_info = blk_mq_rq_to_pdu(req); nvme_set_info(cmd_info, req, async_req_completion); @@ -1016,14 +1021,19 @@ static void nvme_abort_req(struct request *req) struct nvme_command cmd; if (!nvmeq->qid || cmd_rq->aborted) { + unsigned long flags; + + spin_lock_irqsave(&dev_list_lock, flags); if (work_busy(&dev->reset_work)) - return; + goto out; list_del_init(&dev->node); dev_warn(&dev->pci_dev->dev, "I/O %d QID %d timeout, reset controller\n", req->tag, nvmeq->qid); dev->reset_workfn = nvme_reset_failed_dev; queue_work(nvme_workq, &dev->reset_work); + out: + spin_unlock_irqrestore(&dev_list_lock, flags); return; } @@ -1064,15 +1074,22 @@ static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx, void *ctx; nvme_completion_fn fn; struct nvme_cmd_info *cmd; - static struct nvme_completion cqe = { - .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1), - }; + struct nvme_completion cqe; + + if (!blk_mq_request_started(req)) + return; cmd = blk_mq_rq_to_pdu(req); if (cmd->ctx == CMD_CTX_CANCELLED) return; + if (blk_queue_dying(req->q)) + cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); + else + cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); + + dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid); ctx = cancel_cmd_info(cmd, &fn); @@ -1084,17 +1101,29 @@ static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); struct nvme_queue *nvmeq = cmd->nvmeq; - dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, - nvmeq->qid); - if (nvmeq->dev->initialized) - nvme_abort_req(req); - /* * The aborted req will be completed on receiving the abort req. * We enable the timer again. If hit twice, it'll cause a device reset, * as the device then is in a faulty state. */ - return BLK_EH_RESET_TIMER; + int ret = BLK_EH_RESET_TIMER; + + dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, + nvmeq->qid); + + spin_lock_irq(&nvmeq->q_lock); + if (!nvmeq->dev->initialized) { + /* + * Force cancelled command frees the request, which requires we + * return BLK_EH_NOT_HANDLED. + */ + nvme_cancel_queue_ios(nvmeq->hctx, req, nvmeq, reserved); + ret = BLK_EH_NOT_HANDLED; + } else + nvme_abort_req(req); + spin_unlock_irq(&nvmeq->q_lock); + + return ret; } static void nvme_free_queue(struct nvme_queue *nvmeq) @@ -1131,10 +1160,16 @@ static void nvme_free_queues(struct nvme_dev *dev, int lowest) */ static int nvme_suspend_queue(struct nvme_queue *nvmeq) { - int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; + int vector; spin_lock_irq(&nvmeq->q_lock); + if (nvmeq->cq_vector == -1) { + spin_unlock_irq(&nvmeq->q_lock); + return 1; + } + vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; nvmeq->dev->online_queues--; + nvmeq->cq_vector = -1; spin_unlock_irq(&nvmeq->q_lock); irq_set_affinity_hint(vector, NULL); @@ -1169,11 +1204,13 @@ static void nvme_disable_queue(struct nvme_dev *dev, int qid) adapter_delete_sq(dev, qid); adapter_delete_cq(dev, qid); } + if (!qid && dev->admin_q) + blk_mq_freeze_queue_start(dev->admin_q); nvme_clear_queue(nvmeq); } static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, - int depth, int vector) + int depth) { struct device *dmadev = &dev->pci_dev->dev; struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); @@ -1199,7 +1236,6 @@ static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, nvmeq->cq_phase = 1; nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; nvmeq->q_depth = depth; - nvmeq->cq_vector = vector; nvmeq->qid = qid; dev->queue_count++; dev->queues[qid] = nvmeq; @@ -1244,6 +1280,7 @@ static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) struct nvme_dev *dev = nvmeq->dev; int result; + nvmeq->cq_vector = qid - 1; result = adapter_alloc_cq(dev, qid, nvmeq); if (result < 0) return result; @@ -1355,6 +1392,14 @@ static struct blk_mq_ops nvme_mq_ops = { .timeout = nvme_timeout, }; +static void nvme_dev_remove_admin(struct nvme_dev *dev) +{ + if (dev->admin_q && !blk_queue_dying(dev->admin_q)) { + blk_cleanup_queue(dev->admin_q); + blk_mq_free_tag_set(&dev->admin_tagset); + } +} + static int nvme_alloc_admin_tags(struct nvme_dev *dev) { if (!dev->admin_q) { @@ -1370,21 +1415,20 @@ static int nvme_alloc_admin_tags(struct nvme_dev *dev) return -ENOMEM; dev->admin_q = blk_mq_init_queue(&dev->admin_tagset); - if (!dev->admin_q) { + if (IS_ERR(dev->admin_q)) { blk_mq_free_tag_set(&dev->admin_tagset); return -ENOMEM; } - } + if (!blk_get_queue(dev->admin_q)) { + nvme_dev_remove_admin(dev); + return -ENODEV; + } + } else + blk_mq_unfreeze_queue(dev->admin_q); return 0; } -static void nvme_free_admin_tags(struct nvme_dev *dev) -{ - if (dev->admin_q) - blk_mq_free_tag_set(&dev->admin_tagset); -} - static int nvme_configure_admin_queue(struct nvme_dev *dev) { int result; @@ -1416,7 +1460,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) nvmeq = dev->queues[0]; if (!nvmeq) { - nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 0); + nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); if (!nvmeq) return -ENOMEM; } @@ -1439,18 +1483,13 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) if (result) goto free_nvmeq; - result = nvme_alloc_admin_tags(dev); - if (result) - goto free_nvmeq; - + nvmeq->cq_vector = 0; result = queue_request_irq(dev, nvmeq, nvmeq->irqname); if (result) - goto free_tags; + goto free_nvmeq; return result; - free_tags: - nvme_free_admin_tags(dev); free_nvmeq: nvme_free_queues(dev, 0); return result; @@ -1944,7 +1983,7 @@ static void nvme_create_io_queues(struct nvme_dev *dev) unsigned i; for (i = dev->queue_count; i <= dev->max_qid; i++) - if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1)) + if (!nvme_alloc_queue(dev, i, dev->q_depth)) break; for (i = dev->online_queues; i <= dev->queue_count - 1; i++) @@ -2235,13 +2274,18 @@ static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) break; if (!schedule_timeout(ADMIN_TIMEOUT) || fatal_signal_pending(current)) { + /* + * Disable the controller first since we can't trust it + * at this point, but leave the admin queue enabled + * until all queue deletion requests are flushed. + * FIXME: This may take a while if there are more h/w + * queues than admin tags. + */ set_current_state(TASK_RUNNING); - nvme_disable_ctrl(dev, readq(&dev->bar->cap)); - nvme_disable_queue(dev, 0); - - send_sig(SIGKILL, dq->worker->task, 1); + nvme_clear_queue(dev->queues[0]); flush_kthread_worker(dq->worker); + nvme_disable_queue(dev, 0); return; } } @@ -2318,7 +2362,6 @@ static void nvme_del_queue_start(struct kthread_work *work) { struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, cmdinfo.work); - allow_signal(SIGKILL); if (nvme_delete_sq(nvmeq)) nvme_del_queue_end(nvmeq); } @@ -2376,6 +2419,34 @@ static void nvme_dev_list_remove(struct nvme_dev *dev) kthread_stop(tmp); } +static void nvme_freeze_queues(struct nvme_dev *dev) +{ + struct nvme_ns *ns; + + list_for_each_entry(ns, &dev->namespaces, list) { + blk_mq_freeze_queue_start(ns->queue); + + spin_lock(ns->queue->queue_lock); + queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); + spin_unlock(ns->queue->queue_lock); + + blk_mq_cancel_requeue_work(ns->queue); + blk_mq_stop_hw_queues(ns->queue); + } +} + +static void nvme_unfreeze_queues(struct nvme_dev *dev) +{ + struct nvme_ns *ns; + + list_for_each_entry(ns, &dev->namespaces, list) { + queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); + blk_mq_unfreeze_queue(ns->queue); + blk_mq_start_stopped_hw_queues(ns->queue, true); + blk_mq_kick_requeue_list(ns->queue); + } +} + static void nvme_dev_shutdown(struct nvme_dev *dev) { int i; @@ -2384,8 +2455,10 @@ static void nvme_dev_shutdown(struct nvme_dev *dev) dev->initialized = 0; nvme_dev_list_remove(dev); - if (dev->bar) + if (dev->bar) { + nvme_freeze_queues(dev); csts = readl(&dev->bar->csts); + } if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { for (i = dev->queue_count - 1; i >= 0; i--) { struct nvme_queue *nvmeq = dev->queues[i]; @@ -2400,12 +2473,6 @@ static void nvme_dev_shutdown(struct nvme_dev *dev) nvme_dev_unmap(dev); } -static void nvme_dev_remove_admin(struct nvme_dev *dev) -{ - if (dev->admin_q && !blk_queue_dying(dev->admin_q)) - blk_cleanup_queue(dev->admin_q); -} - static void nvme_dev_remove(struct nvme_dev *dev) { struct nvme_ns *ns; @@ -2413,8 +2480,10 @@ static void nvme_dev_remove(struct nvme_dev *dev) list_for_each_entry(ns, &dev->namespaces, list) { if (ns->disk->flags & GENHD_FL_UP) del_gendisk(ns->disk); - if (!blk_queue_dying(ns->queue)) + if (!blk_queue_dying(ns->queue)) { + blk_mq_abort_requeue_list(ns->queue); blk_cleanup_queue(ns->queue); + } } } @@ -2495,6 +2564,7 @@ static void nvme_free_dev(struct kref *kref) nvme_free_namespaces(dev); nvme_release_instance(dev); blk_mq_free_tag_set(&dev->tagset); + blk_put_queue(dev->admin_q); kfree(dev->queues); kfree(dev->entry); kfree(dev); @@ -2591,15 +2661,20 @@ static int nvme_dev_start(struct nvme_dev *dev) } nvme_init_queue(dev->queues[0], 0); + result = nvme_alloc_admin_tags(dev); + if (result) + goto disable; result = nvme_setup_io_queues(dev); if (result) - goto disable; + goto free_tags; nvme_set_irq_hints(dev); return result; + free_tags: + nvme_dev_remove_admin(dev); disable: nvme_disable_queue(dev, 0); nvme_dev_list_remove(dev); @@ -2639,6 +2714,9 @@ static int nvme_dev_resume(struct nvme_dev *dev) dev->reset_workfn = nvme_remove_disks; queue_work(nvme_workq, &dev->reset_work); spin_unlock(&dev_list_lock); + } else { + nvme_unfreeze_queues(dev); + nvme_set_irq_hints(dev); } dev->initialized = 1; return 0; @@ -2776,11 +2854,10 @@ static void nvme_remove(struct pci_dev *pdev) pci_set_drvdata(pdev, NULL); flush_work(&dev->reset_work); misc_deregister(&dev->miscdev); - nvme_dev_remove(dev); nvme_dev_shutdown(dev); + nvme_dev_remove(dev); nvme_dev_remove_admin(dev); nvme_free_queues(dev, 0); - nvme_free_admin_tags(dev); nvme_release_prp_pools(dev); kref_put(&dev->kref, nvme_free_dev); } diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c index 7ef7c098708f..cdfbd21e3597 100644 --- a/drivers/block/virtio_blk.c +++ b/drivers/block/virtio_blk.c @@ -638,7 +638,7 @@ static int virtblk_probe(struct virtio_device *vdev) goto out_put_disk; q = vblk->disk->queue = blk_mq_init_queue(&vblk->tag_set); - if (!q) { + if (IS_ERR(q)) { err = -ENOMEM; goto out_free_tags; } diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 860da40b78ef..0ce5e2d65a06 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -1312,6 +1312,9 @@ static int cci_probe(void) if (!np) return -ENODEV; + if (!of_device_is_available(np)) + return -ENODEV; + cci_config = of_match_node(arm_cci_matches, np)->data; if (!cci_config) return -ENODEV; diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c index fd5a5e85d7dc..982b96323f82 100644 --- a/drivers/char/ipmi/ipmi_ssif.c +++ b/drivers/char/ipmi/ipmi_ssif.c @@ -969,7 +969,8 @@ static void sender(void *send_info, do_gettimeofday(&t); pr_info("**Enqueue %02x %02x: %ld.%6.6ld\n", - msg->data[0], msg->data[1], t.tv_sec, t.tv_usec); + msg->data[0], msg->data[1], + (long) t.tv_sec, (long) t.tv_usec); } } diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index 32f7c1b36204..2f13bd5246b5 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -70,6 +70,7 @@ struct clk_sam9x5_slow { #define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw) +static struct clk *slow_clk; static int clk_slow_osc_prepare(struct clk_hw *hw) { @@ -357,6 +358,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, clk = clk_register(NULL, &slowck->hw); if (IS_ERR(clk)) kfree(slowck); + else + slow_clk = clk; return clk; } @@ -433,6 +436,8 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc, clk = clk_register(NULL, &slowck->hw); if (IS_ERR(clk)) kfree(slowck); + else + slow_clk = clk; return clk; } @@ -465,3 +470,25 @@ void __init of_at91sam9260_clk_slow_setup(struct device_node *np, of_clk_add_provider(np, of_clk_src_simple_get, clk); } + +/* + * FIXME: All slow clk users are not properly claiming it (get + prepare + + * enable) before using it. + * If all users properly claiming this clock decide that they don't need it + * anymore (or are removed), it is disabled while faulty users are still + * requiring it, and the system hangs. + * Prevent this clock from being disabled until all users are properly + * requesting it. + * Once this is done we should remove this function and the slow_clk variable. + */ +static int __init of_at91_clk_slow_retain(void) +{ + if (!slow_clk) + return 0; + + __clk_get(slow_clk); + clk_prepare_enable(slow_clk); + + return 0; +} +arch_initcall(of_at91_clk_slow_retain); diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c index 21784e4eb3f0..440ef81ab15c 100644 --- a/drivers/clk/berlin/bg2q.c +++ b/drivers/clk/berlin/bg2q.c @@ -285,7 +285,6 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = { { "pbridge", "perif", 15, CLK_IGNORE_UNUSED }, { "sdio", "perif", 16, CLK_IGNORE_UNUSED }, { "nfc", "perif", 18 }, - { "smemc", "perif", 19 }, { "pcie", "perif", 22 }, }; diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c index b6e6c85507a5..0a47d6f49cd6 100644 --- a/drivers/clk/clk-ppc-corenet.c +++ b/drivers/clk/clk-ppc-corenet.c @@ -291,7 +291,7 @@ static const struct of_device_id ppc_clk_ids[] __initconst = { {} }; -static struct platform_driver ppc_corenet_clk_driver __initdata = { +static struct platform_driver ppc_corenet_clk_driver = { .driver = { .name = "ppc_corenet_clock", .of_match_table = ppc_clk_ids, diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index f4963b7d4e17..d48ac71c6c8b 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1366,7 +1366,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate) new_rate = clk->ops->determine_rate(clk->hw, rate, &best_parent_rate, &parent_hw); - parent = parent_hw->clk; + parent = parent_hw ? parent_hw->clk : NULL; } else if (clk->ops->round_rate) { new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate); diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 75c8c45ef728..8539c4fd34cc 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -124,10 +124,11 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, { const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; unsigned long alt_prate, alt_div; + unsigned long flags; alt_prate = clk_get_rate(cpuclk->alt_parent); - spin_lock(cpuclk->lock); + spin_lock_irqsave(cpuclk->lock, flags); /* * If the old parent clock speed is less than the clock speed @@ -164,7 +165,7 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, cpuclk->reg_base + reg_data->core_reg); } - spin_unlock(cpuclk->lock); + spin_unlock_irqrestore(cpuclk->lock, flags); return 0; } @@ -173,6 +174,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, { const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; const struct rockchip_cpuclk_rate_table *rate; + unsigned long flags; rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate); if (!rate) { @@ -181,7 +183,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, return -EINVAL; } - spin_lock(cpuclk->lock); + spin_lock_irqsave(cpuclk->lock, flags); if (ndata->old_rate < ndata->new_rate) rockchip_cpuclk_set_dividers(cpuclk, rate); @@ -201,7 +203,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, if (ndata->old_rate > ndata->new_rate) rockchip_cpuclk_set_dividers(cpuclk, rate); - spin_unlock(cpuclk->lock); + spin_unlock_irqrestore(cpuclk->lock, flags); return 0; } diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index c54078960847..7eb684c50d42 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -210,6 +210,17 @@ PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" }; PNAME(mux_mac_p) = { "gpll", "dpll" }; PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" }; +static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), + RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates), + [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), + RK2928_MODE_CON, 4, 4, 0, NULL), + [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), + RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), + [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), + RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), +}; + static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates), @@ -427,11 +438,11 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { /* hclk_peri gates */ GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS), - GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS), + GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS), GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), - GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 5, GFLAGS), - GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS), + GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS), + GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS), GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS), GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), @@ -592,7 +603,8 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), - GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), + GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(5), 14, GFLAGS), GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), @@ -680,7 +692,8 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), - GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), + GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), @@ -735,8 +748,8 @@ static void __init rk3188_common_clk_init(struct device_node *np) static void __init rk3066a_clk_init(struct device_node *np) { rk3188_common_clk_init(np); - rockchip_clk_register_plls(rk3188_pll_clks, - ARRAY_SIZE(rk3188_pll_clks), + rockchip_clk_register_plls(rk3066_pll_clks, + ARRAY_SIZE(rk3066_pll_clks), RK3066_GRF_SOC_STATUS); rockchip_clk_register_branches(rk3066a_clk_branches, ARRAY_SIZE(rk3066a_clk_branches)); diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index ac6be7c0132d..11194b8329fe 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -145,20 +145,20 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = { } static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = { - RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4), - RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4), + RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3), + RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3), }; static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = { diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 380478562b7d..5c062548957c 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -1505,7 +1505,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) dw->regs = chip->regs; chip->dw = dw; - pm_runtime_enable(chip->dev); pm_runtime_get_sync(chip->dev); dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); @@ -1703,7 +1702,6 @@ int dw_dma_remove(struct dw_dma_chip *chip) } pm_runtime_put_sync_suspend(chip->dev); - pm_runtime_disable(chip->dev); return 0; } EXPORT_SYMBOL_GPL(dw_dma_remove); diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c index a630161473a4..32ea1aca7a0e 100644 --- a/drivers/dma/dw/platform.c +++ b/drivers/dma/dw/platform.c @@ -15,6 +15,7 @@ #include <linux/module.h> #include <linux/device.h> #include <linux/clk.h> +#include <linux/pm_runtime.h> #include <linux/platform_device.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> @@ -185,6 +186,8 @@ static int dw_probe(struct platform_device *pdev) if (err) return err; + pm_runtime_enable(&pdev->dev); + err = dw_dma_probe(chip, pdata); if (err) goto err_dw_dma_probe; @@ -205,6 +208,7 @@ static int dw_probe(struct platform_device *pdev) return 0; err_dw_dma_probe: + pm_runtime_disable(&pdev->dev); clk_disable_unprepare(chip->clk); return err; } @@ -217,6 +221,7 @@ static int dw_remove(struct platform_device *pdev) of_dma_controller_free(pdev->dev.of_node); dw_dma_remove(chip); + pm_runtime_disable(&pdev->dev); clk_disable_unprepare(chip->clk); return 0; diff --git a/drivers/gpio/gpio-crystalcove.c b/drivers/gpio/gpio-crystalcove.c index 55d4803d71b0..3d9e08f7e823 100644 --- a/drivers/gpio/gpio-crystalcove.c +++ b/drivers/gpio/gpio-crystalcove.c @@ -272,7 +272,7 @@ static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data) for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) { if (pending & BIT(gpio)) { virq = irq_find_mapping(cg->chip.irqdomain, gpio); - generic_handle_irq(virq); + handle_nested_irq(virq); } } diff --git a/drivers/gpio/gpio-dln2.c b/drivers/gpio/gpio-dln2.c index 978b51eae2ec..ce3c1558cb0a 100644 --- a/drivers/gpio/gpio-dln2.c +++ b/drivers/gpio/gpio-dln2.c @@ -47,13 +47,6 @@ #define DLN2_GPIO_MAX_PINS 32 -struct dln2_irq_work { - struct work_struct work; - struct dln2_gpio *dln2; - int pin; - int type; -}; - struct dln2_gpio { struct platform_device *pdev; struct gpio_chip gpio; @@ -64,10 +57,12 @@ struct dln2_gpio { */ DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS); - DECLARE_BITMAP(irqs_masked, DLN2_GPIO_MAX_PINS); - DECLARE_BITMAP(irqs_enabled, DLN2_GPIO_MAX_PINS); - DECLARE_BITMAP(irqs_pending, DLN2_GPIO_MAX_PINS); - struct dln2_irq_work *irq_work; + /* active IRQs - not synced to hardware */ + DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS); + /* active IRQS - synced to hardware */ + DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS); + int irq_type[DLN2_GPIO_MAX_PINS]; + struct mutex irq_lock; }; struct dln2_gpio_pin { @@ -141,16 +136,16 @@ static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin) return !!ret; } -static void dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2, - unsigned int pin, int value) +static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2, + unsigned int pin, int value) { struct dln2_gpio_pin_val req = { .pin = cpu_to_le16(pin), .value = value, }; - dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req, - sizeof(req)); + return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req, + sizeof(req)); } #define DLN2_GPIO_DIRECTION_IN 0 @@ -267,6 +262,13 @@ static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset) static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { + struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio); + int ret; + + ret = dln2_gpio_pin_set_out_val(dln2, offset, value); + if (ret < 0) + return ret; + return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT); } @@ -297,36 +299,13 @@ static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin, &req, sizeof(req)); } -static void dln2_irq_work(struct work_struct *w) -{ - struct dln2_irq_work *iw = container_of(w, struct dln2_irq_work, work); - struct dln2_gpio *dln2 = iw->dln2; - u8 type = iw->type & DLN2_GPIO_EVENT_MASK; - - if (test_bit(iw->pin, dln2->irqs_enabled)) - dln2_gpio_set_event_cfg(dln2, iw->pin, type, 0); - else - dln2_gpio_set_event_cfg(dln2, iw->pin, DLN2_GPIO_EVENT_NONE, 0); -} - -static void dln2_irq_enable(struct irq_data *irqd) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); - struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); - int pin = irqd_to_hwirq(irqd); - - set_bit(pin, dln2->irqs_enabled); - schedule_work(&dln2->irq_work[pin].work); -} - -static void dln2_irq_disable(struct irq_data *irqd) +static void dln2_irq_unmask(struct irq_data *irqd) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); int pin = irqd_to_hwirq(irqd); - clear_bit(pin, dln2->irqs_enabled); - schedule_work(&dln2->irq_work[pin].work); + set_bit(pin, dln2->unmasked_irqs); } static void dln2_irq_mask(struct irq_data *irqd) @@ -335,27 +314,7 @@ static void dln2_irq_mask(struct irq_data *irqd) struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); int pin = irqd_to_hwirq(irqd); - set_bit(pin, dln2->irqs_masked); -} - -static void dln2_irq_unmask(struct irq_data *irqd) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); - struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); - struct device *dev = dln2->gpio.dev; - int pin = irqd_to_hwirq(irqd); - - if (test_and_clear_bit(pin, dln2->irqs_pending)) { - int irq; - - irq = irq_find_mapping(dln2->gpio.irqdomain, pin); - if (!irq) { - dev_err(dev, "pin %d not mapped to IRQ\n", pin); - return; - } - - generic_handle_irq(irq); - } + clear_bit(pin, dln2->unmasked_irqs); } static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) @@ -366,19 +325,19 @@ static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) switch (type) { case IRQ_TYPE_LEVEL_HIGH: - dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_HIGH; + dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH; break; case IRQ_TYPE_LEVEL_LOW: - dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_LOW; + dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW; break; case IRQ_TYPE_EDGE_BOTH: - dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE; + dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE; break; case IRQ_TYPE_EDGE_RISING: - dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_RISING; + dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING; break; case IRQ_TYPE_EDGE_FALLING: - dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_FALLING; + dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING; break; default: return -EINVAL; @@ -387,13 +346,50 @@ static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) return 0; } +static void dln2_irq_bus_lock(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); + + mutex_lock(&dln2->irq_lock); +} + +static void dln2_irq_bus_unlock(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); + int pin = irqd_to_hwirq(irqd); + int enabled, unmasked; + unsigned type; + int ret; + + enabled = test_bit(pin, dln2->enabled_irqs); + unmasked = test_bit(pin, dln2->unmasked_irqs); + + if (enabled != unmasked) { + if (unmasked) { + type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK; + set_bit(pin, dln2->enabled_irqs); + } else { + type = DLN2_GPIO_EVENT_NONE; + clear_bit(pin, dln2->enabled_irqs); + } + + ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0); + if (ret) + dev_err(dln2->gpio.dev, "failed to set event\n"); + } + + mutex_unlock(&dln2->irq_lock); +} + static struct irq_chip dln2_gpio_irqchip = { .name = "dln2-irq", - .irq_enable = dln2_irq_enable, - .irq_disable = dln2_irq_disable, .irq_mask = dln2_irq_mask, .irq_unmask = dln2_irq_unmask, .irq_set_type = dln2_irq_set_type, + .irq_bus_lock = dln2_irq_bus_lock, + .irq_bus_sync_unlock = dln2_irq_bus_unlock, }; static void dln2_gpio_event(struct platform_device *pdev, u16 echo, @@ -425,14 +421,7 @@ static void dln2_gpio_event(struct platform_device *pdev, u16 echo, return; } - if (!test_bit(pin, dln2->irqs_enabled)) - return; - if (test_bit(pin, dln2->irqs_masked)) { - set_bit(pin, dln2->irqs_pending); - return; - } - - switch (dln2->irq_work[pin].type) { + switch (dln2->irq_type[pin]) { case DLN2_GPIO_EVENT_CHANGE_RISING: if (event->value) generic_handle_irq(irq); @@ -451,7 +440,7 @@ static int dln2_gpio_probe(struct platform_device *pdev) struct dln2_gpio *dln2; struct device *dev = &pdev->dev; int pins; - int i, ret; + int ret; pins = dln2_gpio_get_pin_count(pdev); if (pins < 0) { @@ -467,15 +456,7 @@ static int dln2_gpio_probe(struct platform_device *pdev) if (!dln2) return -ENOMEM; - dln2->irq_work = devm_kcalloc(&pdev->dev, pins, - sizeof(struct dln2_irq_work), GFP_KERNEL); - if (!dln2->irq_work) - return -ENOMEM; - for (i = 0; i < pins; i++) { - INIT_WORK(&dln2->irq_work[i].work, dln2_irq_work); - dln2->irq_work[i].pin = i; - dln2->irq_work[i].dln2 = dln2; - } + mutex_init(&dln2->irq_lock); dln2->pdev = pdev; @@ -529,11 +510,8 @@ out: static int dln2_gpio_remove(struct platform_device *pdev) { struct dln2_gpio *dln2 = platform_get_drvdata(pdev); - int i; dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV); - for (i = 0; i < dln2->gpio.ngpio; i++) - flush_work(&dln2->irq_work[i].work); gpiochip_remove(&dln2->gpio); return 0; diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c index 09daaf2aeb56..3a5a71050559 100644 --- a/drivers/gpio/gpio-grgpio.c +++ b/drivers/gpio/gpio-grgpio.c @@ -441,7 +441,8 @@ static int grgpio_probe(struct platform_device *ofdev) err = gpiochip_add(gc); if (err) { dev_err(&ofdev->dev, "Could not add gpiochip\n"); - irq_domain_remove(priv->domain); + if (priv->domain) + irq_domain_remove(priv->domain); return err; } diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index 604dbe60bdee..08261f2b3a82 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -45,8 +45,14 @@ static int of_gpiochip_find_and_xlate(struct gpio_chip *gc, void *data) return false; ret = gc->of_xlate(gc, &gg_data->gpiospec, gg_data->flags); - if (ret < 0) - return false; + if (ret < 0) { + /* We've found the gpio chip, but the translation failed. + * Return true to stop looking and return the translation + * error via out_gpio + */ + gg_data->out_gpio = ERR_PTR(ret); + return true; + } gg_data->out_gpio = gpiochip_get_desc(gc, ret); return true; diff --git a/drivers/gpio/gpiolib-sysfs.c b/drivers/gpio/gpiolib-sysfs.c index 2ac1800b58bb..f62aa115d79a 100644 --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c @@ -128,7 +128,7 @@ static ssize_t gpio_value_store(struct device *dev, return status; } -static const DEVICE_ATTR(value, 0644, +static DEVICE_ATTR(value, 0644, gpio_value_show, gpio_value_store); static irqreturn_t gpio_sysfs_irq(int irq, void *priv) @@ -353,17 +353,46 @@ static ssize_t gpio_active_low_store(struct device *dev, return status ? : size; } -static const DEVICE_ATTR(active_low, 0644, +static DEVICE_ATTR(active_low, 0644, gpio_active_low_show, gpio_active_low_store); -static const struct attribute *gpio_attrs[] = { +static umode_t gpio_is_visible(struct kobject *kobj, struct attribute *attr, + int n) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct gpio_desc *desc = dev_get_drvdata(dev); + umode_t mode = attr->mode; + bool show_direction = test_bit(FLAG_SYSFS_DIR, &desc->flags); + + if (attr == &dev_attr_direction.attr) { + if (!show_direction) + mode = 0; + } else if (attr == &dev_attr_edge.attr) { + if (gpiod_to_irq(desc) < 0) + mode = 0; + if (!show_direction && test_bit(FLAG_IS_OUT, &desc->flags)) + mode = 0; + } + + return mode; +} + +static struct attribute *gpio_attrs[] = { + &dev_attr_direction.attr, + &dev_attr_edge.attr, &dev_attr_value.attr, &dev_attr_active_low.attr, NULL, }; -static const struct attribute_group gpio_attr_group = { - .attrs = (struct attribute **) gpio_attrs, +static const struct attribute_group gpio_group = { + .attrs = gpio_attrs, + .is_visible = gpio_is_visible, +}; + +static const struct attribute_group *gpio_groups[] = { + &gpio_group, + NULL }; /* @@ -400,16 +429,13 @@ static ssize_t chip_ngpio_show(struct device *dev, } static DEVICE_ATTR(ngpio, 0444, chip_ngpio_show, NULL); -static const struct attribute *gpiochip_attrs[] = { +static struct attribute *gpiochip_attrs[] = { &dev_attr_base.attr, &dev_attr_label.attr, &dev_attr_ngpio.attr, NULL, }; - -static const struct attribute_group gpiochip_attr_group = { - .attrs = (struct attribute **) gpiochip_attrs, -}; +ATTRIBUTE_GROUPS(gpiochip); /* * /sys/class/gpio/export ... write-only @@ -556,45 +582,30 @@ int gpiod_export(struct gpio_desc *desc, bool direction_may_change) goto fail_unlock; } - if (!desc->chip->direction_input || !desc->chip->direction_output) - direction_may_change = false; + if (desc->chip->direction_input && desc->chip->direction_output && + direction_may_change) { + set_bit(FLAG_SYSFS_DIR, &desc->flags); + } + spin_unlock_irqrestore(&gpio_lock, flags); offset = gpio_chip_hwgpio(desc); if (desc->chip->names && desc->chip->names[offset]) ioname = desc->chip->names[offset]; - dev = device_create(&gpio_class, desc->chip->dev, MKDEV(0, 0), - desc, ioname ? ioname : "gpio%u", - desc_to_gpio(desc)); + dev = device_create_with_groups(&gpio_class, desc->chip->dev, + MKDEV(0, 0), desc, gpio_groups, + ioname ? ioname : "gpio%u", + desc_to_gpio(desc)); if (IS_ERR(dev)) { status = PTR_ERR(dev); goto fail_unlock; } - status = sysfs_create_group(&dev->kobj, &gpio_attr_group); - if (status) - goto fail_unregister_device; - - if (direction_may_change) { - status = device_create_file(dev, &dev_attr_direction); - if (status) - goto fail_unregister_device; - } - - if (gpiod_to_irq(desc) >= 0 && (direction_may_change || - !test_bit(FLAG_IS_OUT, &desc->flags))) { - status = device_create_file(dev, &dev_attr_edge); - if (status) - goto fail_unregister_device; - } - set_bit(FLAG_EXPORT, &desc->flags); mutex_unlock(&sysfs_lock); return 0; -fail_unregister_device: - device_unregister(dev); fail_unlock: mutex_unlock(&sysfs_lock); gpiod_dbg(desc, "%s: status %d\n", __func__, status); @@ -718,6 +729,7 @@ void gpiod_unexport(struct gpio_desc *desc) dev = class_find_device(&gpio_class, NULL, desc, match_export); if (dev) { gpio_setup_irq(desc, dev, 0); + clear_bit(FLAG_SYSFS_DIR, &desc->flags); clear_bit(FLAG_EXPORT, &desc->flags); } else status = -ENODEV; @@ -750,13 +762,13 @@ int gpiochip_export(struct gpio_chip *chip) /* use chip->base for the ID; it's already known to be unique */ mutex_lock(&sysfs_lock); - dev = device_create(&gpio_class, chip->dev, MKDEV(0, 0), chip, - "gpiochip%d", chip->base); - if (!IS_ERR(dev)) { - status = sysfs_create_group(&dev->kobj, - &gpiochip_attr_group); - } else + dev = device_create_with_groups(&gpio_class, chip->dev, MKDEV(0, 0), + chip, gpiochip_groups, + "gpiochip%d", chip->base); + if (IS_ERR(dev)) status = PTR_ERR(dev); + else + status = 0; chip->exported = (status == 0); mutex_unlock(&sysfs_lock); diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 487afe6f22fc..568aa2b6bdb0 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -248,29 +248,30 @@ int gpiochip_add(struct gpio_chip *chip) base = gpiochip_find_base(chip->ngpio); if (base < 0) { status = base; - goto unlock; + spin_unlock_irqrestore(&gpio_lock, flags); + goto err_free_descs; } chip->base = base; } status = gpiochip_add_to_list(chip); + if (status) { + spin_unlock_irqrestore(&gpio_lock, flags); + goto err_free_descs; + } - if (status == 0) { - for (id = 0; id < chip->ngpio; id++) { - struct gpio_desc *desc = &descs[id]; - desc->chip = chip; - - /* REVISIT: most hardware initializes GPIOs as - * inputs (often with pullups enabled) so power - * usage is minimized. Linux code should set the - * gpio direction first thing; but until it does, - * and in case chip->get_direction is not set, - * we may expose the wrong direction in sysfs. - */ - desc->flags = !chip->direction_input - ? (1 << FLAG_IS_OUT) - : 0; - } + for (id = 0; id < chip->ngpio; id++) { + struct gpio_desc *desc = &descs[id]; + + desc->chip = chip; + + /* REVISIT: most hardware initializes GPIOs as inputs (often + * with pullups enabled) so power usage is minimized. Linux + * code should set the gpio direction first thing; but until + * it does, and in case chip->get_direction is not set, we may + * expose the wrong direction in sysfs. + */ + desc->flags = !chip->direction_input ? (1 << FLAG_IS_OUT) : 0; } chip->desc = descs; @@ -284,12 +285,9 @@ int gpiochip_add(struct gpio_chip *chip) of_gpiochip_add(chip); acpi_gpiochip_add(chip); - if (status) - goto fail; - status = gpiochip_export(chip); if (status) - goto fail; + goto err_remove_chip; pr_debug("%s: registered GPIOs %d to %d on device: %s\n", __func__, chip->base, chip->base + chip->ngpio - 1, @@ -297,11 +295,15 @@ int gpiochip_add(struct gpio_chip *chip) return 0; -unlock: +err_remove_chip: + acpi_gpiochip_remove(chip); + of_gpiochip_remove(chip); + spin_lock_irqsave(&gpio_lock, flags); + list_del(&chip->list); spin_unlock_irqrestore(&gpio_lock, flags); -fail: - kfree(descs); chip->desc = NULL; +err_free_descs: + kfree(descs); /* failures here can mean systems won't boot... */ pr_err("%s: GPIOs %d..%d (%s) failed to register\n", __func__, @@ -325,14 +327,15 @@ void gpiochip_remove(struct gpio_chip *chip) unsigned long flags; unsigned id; - acpi_gpiochip_remove(chip); - - spin_lock_irqsave(&gpio_lock, flags); + gpiochip_unexport(chip); gpiochip_irqchip_remove(chip); + + acpi_gpiochip_remove(chip); gpiochip_remove_pin_ranges(chip); of_gpiochip_remove(chip); + spin_lock_irqsave(&gpio_lock, flags); for (id = 0; id < chip->ngpio; id++) { if (test_bit(FLAG_REQUESTED, &chip->desc[id].flags)) dev_crit(chip->dev, "REMOVING GPIOCHIP WITH GPIOS STILL REQUESTED\n"); @@ -342,7 +345,6 @@ void gpiochip_remove(struct gpio_chip *chip) list_del(&chip->list); spin_unlock_irqrestore(&gpio_lock, flags); - gpiochip_unexport(chip); kfree(chip->desc); chip->desc = NULL; diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h index e3a52113a541..550a5eafbd38 100644 --- a/drivers/gpio/gpiolib.h +++ b/drivers/gpio/gpiolib.h @@ -77,6 +77,7 @@ struct gpio_desc { #define FLAG_OPEN_DRAIN 7 /* Gpio is open drain type */ #define FLAG_OPEN_SOURCE 8 /* Gpio is open source type */ #define FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */ +#define FLAG_SYSFS_DIR 10 /* show sysfs direction attribute */ #define ID_SHIFT 16 /* add new flags before this one */ diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index c3413b6adb17..ea283894a12a 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -183,6 +183,8 @@ source "drivers/gpu/drm/cirrus/Kconfig" source "drivers/gpu/drm/armada/Kconfig" +source "drivers/gpu/drm/atmel-hlcdc/Kconfig" + source "drivers/gpu/drm/rcar-du/Kconfig" source "drivers/gpu/drm/shmobile/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 66e40398b3d3..cf0eed8208b5 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o obj-$(CONFIG_DRM_TTM) += ttm/ obj-$(CONFIG_DRM_TDFX) += tdfx/ obj-$(CONFIG_DRM_R128) += r128/ +obj-$(CONFIG_HSA_AMD) += amd/amdkfd/ obj-$(CONFIG_DRM_RADEON)+= radeon/ obj-$(CONFIG_DRM_MGA) += mga/ obj-$(CONFIG_DRM_I810) += i810/ @@ -54,6 +55,7 @@ obj-$(CONFIG_DRM_GMA500) += gma500/ obj-$(CONFIG_DRM_UDL) += udl/ obj-$(CONFIG_DRM_AST) += ast/ obj-$(CONFIG_DRM_ARMADA) += armada/ +obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc/ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/ obj-$(CONFIG_DRM_OMAP) += omapdrm/ @@ -67,4 +69,3 @@ obj-$(CONFIG_DRM_IMX) += imx/ obj-y += i2c/ obj-y += panel/ obj-y += bridge/ -obj-$(CONFIG_HSA_AMD) += amd/amdkfd/ diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index be6246de5091..0f4960148126 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -7,8 +7,10 @@ ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ kfd_pasid.o kfd_doorbell.o kfd_flat_memory.o \ kfd_process.o kfd_queue.o kfd_mqd_manager.o \ - kfd_kernel_queue.o kfd_packet_manager.o \ + kfd_mqd_manager_cik.o kfd_mqd_manager_vi.o \ + kfd_kernel_queue.o kfd_kernel_queue_cik.o \ + kfd_kernel_queue_vi.o kfd_packet_manager.o \ kfd_process_queue_manager.o kfd_device_queue_manager.o \ - kfd_interrupt.o + kfd_device_queue_manager_cik.o kfd_device_queue_manager_vi.o \ obj-$(CONFIG_HSA_AMD) += amdkfd.o diff --git a/drivers/gpu/drm/amd/amdkfd/cik_regs.h b/drivers/gpu/drm/amd/amdkfd/cik_regs.h index 607fc5ceadbe..01ff332fabd4 100644 --- a/drivers/gpu/drm/amd/amdkfd/cik_regs.h +++ b/drivers/gpu/drm/amd/amdkfd/cik_regs.h @@ -168,6 +168,8 @@ #define IB_ATC_EN (1U << 23) #define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20) +#define AQL_ENABLE 1 + #define CP_HQD_DEQUEUE_REQUEST 0xC974 #define DEQUEUE_REQUEST_DRAIN 1 #define DEQUEUE_REQUEST_RESET 2 @@ -188,6 +190,17 @@ #define MQD_VMID_MASK (0xf << 0) #define MQD_CONTROL_PRIV_STATE_EN (1U << 8) +#define SDMA_RB_VMID(x) (x << 24) +#define SDMA_RB_ENABLE (1 << 0) +#define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ +#define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) +#define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ +#define SDMA_OFFSET(x) (x << 0) +#define SDMA_DB_ENABLE (1 << 28) +#define SDMA_ATC (1 << 0) +#define SDMA_VA_PTR32 (1 << 4) +#define SDMA_VA_SHARED_BASE(x) (x << 8) + #define GRBM_GFX_INDEX 0x30800 #define INSTANCE_INDEX(x) ((x) << 0) #define SH_INDEX(x) ((x) << 8) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 4c0b1e42e405..732087dcac91 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -31,7 +31,6 @@ #include <uapi/linux/kfd_ioctl.h> #include <linux/time.h> #include <linux/mm.h> -#include <linux/uaccess.h> #include <uapi/asm-generic/mman-common.h> #include <asm/processor.h> #include "kfd_priv.h" @@ -127,17 +126,14 @@ static int kfd_open(struct inode *inode, struct file *filep) return 0; } -static long kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, - void __user *arg) +static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, + void *data) { - struct kfd_ioctl_get_version_args args; + struct kfd_ioctl_get_version_args *args = data; int err = 0; - args.major_version = KFD_IOCTL_MAJOR_VERSION; - args.minor_version = KFD_IOCTL_MINOR_VERSION; - - if (copy_to_user(arg, &args, sizeof(args))) - err = -EFAULT; + args->major_version = KFD_IOCTL_MAJOR_VERSION; + args->minor_version = KFD_IOCTL_MINOR_VERSION; return err; } @@ -145,6 +141,8 @@ static long kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, static int set_queue_properties_from_user(struct queue_properties *q_properties, struct kfd_ioctl_create_queue_args *args) { + void *tmp; + if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); return -EINVAL; @@ -182,6 +180,20 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, return -EFAULT; } + tmp = (void *)(uintptr_t)args->eop_buffer_address; + if (tmp != NULL && + !access_ok(VERIFY_WRITE, tmp, sizeof(uint32_t))) { + pr_debug("kfd: can't access eop buffer"); + return -EFAULT; + } + + tmp = (void *)(uintptr_t)args->ctx_save_restore_address; + if (tmp != NULL && + !access_ok(VERIFY_WRITE, tmp, sizeof(uint32_t))) { + pr_debug("kfd: can't access ctx save restore buffer"); + return -EFAULT; + } + q_properties->is_interop = false; q_properties->queue_percent = args->queue_percentage; q_properties->priority = args->queue_priority; @@ -189,6 +201,11 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, q_properties->queue_size = args->ring_size; q_properties->read_ptr = (uint32_t *) args->read_pointer_address; q_properties->write_ptr = (uint32_t *) args->write_pointer_address; + q_properties->eop_ring_buffer_address = args->eop_buffer_address; + q_properties->eop_ring_buffer_size = args->eop_buffer_size; + q_properties->ctx_save_restore_area_address = + args->ctx_save_restore_address; + q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size; if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE || args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) q_properties->type = KFD_QUEUE_TYPE_COMPUTE; @@ -220,13 +237,18 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, pr_debug("Queue Format (%d)\n", q_properties->format); + pr_debug("Queue EOP (0x%llX)\n", q_properties->eop_ring_buffer_address); + + pr_debug("Queue CTX save arex (0x%llX)\n", + q_properties->ctx_save_restore_area_address); + return 0; } -static long kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, - void __user *arg) +static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, + void *data) { - struct kfd_ioctl_create_queue_args args; + struct kfd_ioctl_create_queue_args *args = data; struct kfd_dev *dev; int err = 0; unsigned int queue_id; @@ -235,24 +257,24 @@ static long kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, memset(&q_properties, 0, sizeof(struct queue_properties)); - if (copy_from_user(&args, arg, sizeof(args))) - return -EFAULT; - pr_debug("kfd: creating queue ioctl\n"); - err = set_queue_properties_from_user(&q_properties, &args); + err = set_queue_properties_from_user(&q_properties, args); if (err) return err; - dev = kfd_device_by_id(args.gpu_id); - if (dev == NULL) + pr_debug("kfd: looking for gpu id 0x%x\n", args->gpu_id); + dev = kfd_device_by_id(args->gpu_id); + if (dev == NULL) { + pr_debug("kfd: gpu id 0x%x was not found\n", args->gpu_id); return -EINVAL; + } mutex_lock(&p->mutex); pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { - err = PTR_ERR(pdd); + err = -ESRCH; goto err_bind_process; } @@ -265,33 +287,26 @@ static long kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, if (err != 0) goto err_create_queue; - args.queue_id = queue_id; + args->queue_id = queue_id; /* Return gpu_id as doorbell offset for mmap usage */ - args.doorbell_offset = args.gpu_id << PAGE_SHIFT; - - if (copy_to_user(arg, &args, sizeof(args))) { - err = -EFAULT; - goto err_copy_args_out; - } + args->doorbell_offset = args->gpu_id << PAGE_SHIFT; mutex_unlock(&p->mutex); - pr_debug("kfd: queue id %d was created successfully\n", args.queue_id); + pr_debug("kfd: queue id %d was created successfully\n", args->queue_id); pr_debug("ring buffer address == 0x%016llX\n", - args.ring_base_address); + args->ring_base_address); pr_debug("read ptr address == 0x%016llX\n", - args.read_pointer_address); + args->read_pointer_address); pr_debug("write ptr address == 0x%016llX\n", - args.write_pointer_address); + args->write_pointer_address); return 0; -err_copy_args_out: - pqm_destroy_queue(&p->pqm, queue_id); err_create_queue: err_bind_process: mutex_unlock(&p->mutex); @@ -299,99 +314,90 @@ err_bind_process: } static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, - void __user *arg) + void *data) { int retval; - struct kfd_ioctl_destroy_queue_args args; - - if (copy_from_user(&args, arg, sizeof(args))) - return -EFAULT; + struct kfd_ioctl_destroy_queue_args *args = data; pr_debug("kfd: destroying queue id %d for PASID %d\n", - args.queue_id, + args->queue_id, p->pasid); mutex_lock(&p->mutex); - retval = pqm_destroy_queue(&p->pqm, args.queue_id); + retval = pqm_destroy_queue(&p->pqm, args->queue_id); mutex_unlock(&p->mutex); return retval; } static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, - void __user *arg) + void *data) { int retval; - struct kfd_ioctl_update_queue_args args; + struct kfd_ioctl_update_queue_args *args = data; struct queue_properties properties; - if (copy_from_user(&args, arg, sizeof(args))) - return -EFAULT; - - if (args.queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { + if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); return -EINVAL; } - if (args.queue_priority > KFD_MAX_QUEUE_PRIORITY) { + if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { pr_err("kfd: queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); return -EINVAL; } - if ((args.ring_base_address) && + if ((args->ring_base_address) && (!access_ok(VERIFY_WRITE, - (const void __user *) args.ring_base_address, + (const void __user *) args->ring_base_address, sizeof(uint64_t)))) { pr_err("kfd: can't access ring base address\n"); return -EFAULT; } - if (!is_power_of_2(args.ring_size) && (args.ring_size != 0)) { + if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { pr_err("kfd: ring size must be a power of 2 or 0\n"); return -EINVAL; } - properties.queue_address = args.ring_base_address; - properties.queue_size = args.ring_size; - properties.queue_percent = args.queue_percentage; - properties.priority = args.queue_priority; + properties.queue_address = args->ring_base_address; + properties.queue_size = args->ring_size; + properties.queue_percent = args->queue_percentage; + properties.priority = args->queue_priority; pr_debug("kfd: updating queue id %d for PASID %d\n", - args.queue_id, p->pasid); + args->queue_id, p->pasid); mutex_lock(&p->mutex); - retval = pqm_update_queue(&p->pqm, args.queue_id, &properties); + retval = pqm_update_queue(&p->pqm, args->queue_id, &properties); mutex_unlock(&p->mutex); return retval; } -static long kfd_ioctl_set_memory_policy(struct file *filep, - struct kfd_process *p, void __user *arg) +static int kfd_ioctl_set_memory_policy(struct file *filep, + struct kfd_process *p, void *data) { - struct kfd_ioctl_set_memory_policy_args args; + struct kfd_ioctl_set_memory_policy_args *args = data; struct kfd_dev *dev; int err = 0; struct kfd_process_device *pdd; enum cache_policy default_policy, alternate_policy; - if (copy_from_user(&args, arg, sizeof(args))) - return -EFAULT; - - if (args.default_policy != KFD_IOC_CACHE_POLICY_COHERENT - && args.default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { + if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT + && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { return -EINVAL; } - if (args.alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT - && args.alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { + if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT + && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { return -EINVAL; } - dev = kfd_device_by_id(args.gpu_id); + dev = kfd_device_by_id(args->gpu_id); if (dev == NULL) return -EINVAL; @@ -399,23 +405,23 @@ static long kfd_ioctl_set_memory_policy(struct file *filep, pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { - err = PTR_ERR(pdd); + err = -ESRCH; goto out; } - default_policy = (args.default_policy == KFD_IOC_CACHE_POLICY_COHERENT) + default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT) ? cache_policy_coherent : cache_policy_noncoherent; alternate_policy = - (args.alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT) + (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT) ? cache_policy_coherent : cache_policy_noncoherent; - if (!dev->dqm->set_cache_memory_policy(dev->dqm, + if (!dev->dqm->ops.set_cache_memory_policy(dev->dqm, &pdd->qpd, default_policy, alternate_policy, - (void __user *)args.alternate_aperture_base, - args.alternate_aperture_size)) + (void __user *)args->alternate_aperture_base, + args->alternate_aperture_size)) err = -EINVAL; out: @@ -424,53 +430,44 @@ out: return err; } -static long kfd_ioctl_get_clock_counters(struct file *filep, - struct kfd_process *p, void __user *arg) +static int kfd_ioctl_get_clock_counters(struct file *filep, + struct kfd_process *p, void *data) { - struct kfd_ioctl_get_clock_counters_args args; + struct kfd_ioctl_get_clock_counters_args *args = data; struct kfd_dev *dev; struct timespec time; - if (copy_from_user(&args, arg, sizeof(args))) - return -EFAULT; - - dev = kfd_device_by_id(args.gpu_id); + dev = kfd_device_by_id(args->gpu_id); if (dev == NULL) return -EINVAL; /* Reading GPU clock counter from KGD */ - args.gpu_clock_counter = kfd2kgd->get_gpu_clock_counter(dev->kgd); + args->gpu_clock_counter = kfd2kgd->get_gpu_clock_counter(dev->kgd); /* No access to rdtsc. Using raw monotonic time */ getrawmonotonic(&time); - args.cpu_clock_counter = (uint64_t)timespec_to_ns(&time); + args->cpu_clock_counter = (uint64_t)timespec_to_ns(&time); get_monotonic_boottime(&time); - args.system_clock_counter = (uint64_t)timespec_to_ns(&time); + args->system_clock_counter = (uint64_t)timespec_to_ns(&time); /* Since the counter is in nano-seconds we use 1GHz frequency */ - args.system_clock_freq = 1000000000; - - if (copy_to_user(arg, &args, sizeof(args))) - return -EFAULT; + args->system_clock_freq = 1000000000; return 0; } static int kfd_ioctl_get_process_apertures(struct file *filp, - struct kfd_process *p, void __user *arg) + struct kfd_process *p, void *data) { - struct kfd_ioctl_get_process_apertures_args args; + struct kfd_ioctl_get_process_apertures_args *args = data; struct kfd_process_device_apertures *pAperture; struct kfd_process_device *pdd; dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid); - if (copy_from_user(&args, arg, sizeof(args))) - return -EFAULT; - - args.num_of_nodes = 0; + args->num_of_nodes = 0; mutex_lock(&p->mutex); @@ -479,7 +476,8 @@ static int kfd_ioctl_get_process_apertures(struct file *filp, /* Run over all pdd of the process */ pdd = kfd_get_first_process_device_data(p); do { - pAperture = &args.process_apertures[args.num_of_nodes]; + pAperture = + &args->process_apertures[args->num_of_nodes]; pAperture->gpu_id = pdd->dev->id; pAperture->lds_base = pdd->lds_base; pAperture->lds_limit = pdd->lds_limit; @@ -489,7 +487,7 @@ static int kfd_ioctl_get_process_apertures(struct file *filp, pAperture->scratch_limit = pdd->scratch_limit; dev_dbg(kfd_device, - "node id %u\n", args.num_of_nodes); + "node id %u\n", args->num_of_nodes); dev_dbg(kfd_device, "gpu id %u\n", pdd->dev->id); dev_dbg(kfd_device, @@ -505,80 +503,131 @@ static int kfd_ioctl_get_process_apertures(struct file *filp, dev_dbg(kfd_device, "scratch_limit %llX\n", pdd->scratch_limit); - args.num_of_nodes++; + args->num_of_nodes++; } while ((pdd = kfd_get_next_process_device_data(p, pdd)) != NULL && - (args.num_of_nodes < NUM_OF_SUPPORTED_GPUS)); + (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS)); } mutex_unlock(&p->mutex); - if (copy_to_user(arg, &args, sizeof(args))) - return -EFAULT; - return 0; } +#define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ + [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0, .name = #ioctl} + +/** Ioctl table */ +static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { + AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION, + kfd_ioctl_get_version, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE, + kfd_ioctl_create_queue, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE, + kfd_ioctl_destroy_queue, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY, + kfd_ioctl_set_memory_policy, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS, + kfd_ioctl_get_clock_counters, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES, + kfd_ioctl_get_process_apertures, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE, + kfd_ioctl_update_queue, 0), +}; + +#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) + static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) { struct kfd_process *process; - long err = -EINVAL; + amdkfd_ioctl_t *func; + const struct amdkfd_ioctl_desc *ioctl = NULL; + unsigned int nr = _IOC_NR(cmd); + char stack_kdata[128]; + char *kdata = NULL; + unsigned int usize, asize; + int retcode = -EINVAL; + + if (nr >= AMDKFD_CORE_IOCTL_COUNT) + goto err_i1; + + if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { + u32 amdkfd_size; + + ioctl = &amdkfd_ioctls[nr]; + + amdkfd_size = _IOC_SIZE(ioctl->cmd); + usize = asize = _IOC_SIZE(cmd); + if (amdkfd_size > asize) + asize = amdkfd_size; - dev_dbg(kfd_device, - "ioctl cmd 0x%x (#%d), arg 0x%lx\n", - cmd, _IOC_NR(cmd), arg); + cmd = ioctl->cmd; + } else + goto err_i1; + + dev_dbg(kfd_device, "ioctl cmd 0x%x (#%d), arg 0x%lx\n", cmd, nr, arg); process = kfd_get_process(current); - if (IS_ERR(process)) - return PTR_ERR(process); + if (IS_ERR(process)) { + dev_dbg(kfd_device, "no process\n"); + goto err_i1; + } - switch (cmd) { - case KFD_IOC_GET_VERSION: - err = kfd_ioctl_get_version(filep, process, (void __user *)arg); - break; - case KFD_IOC_CREATE_QUEUE: - err = kfd_ioctl_create_queue(filep, process, - (void __user *)arg); - break; - - case KFD_IOC_DESTROY_QUEUE: - err = kfd_ioctl_destroy_queue(filep, process, - (void __user *)arg); - break; - - case KFD_IOC_SET_MEMORY_POLICY: - err = kfd_ioctl_set_memory_policy(filep, process, - (void __user *)arg); - break; - - case KFD_IOC_GET_CLOCK_COUNTERS: - err = kfd_ioctl_get_clock_counters(filep, process, - (void __user *)arg); - break; - - case KFD_IOC_GET_PROCESS_APERTURES: - err = kfd_ioctl_get_process_apertures(filep, process, - (void __user *)arg); - break; - - case KFD_IOC_UPDATE_QUEUE: - err = kfd_ioctl_update_queue(filep, process, - (void __user *)arg); - break; - - default: - dev_err(kfd_device, - "unknown ioctl cmd 0x%x, arg 0x%lx)\n", - cmd, arg); - err = -EINVAL; - break; + /* Do not trust userspace, use our own definition */ + func = ioctl->func; + + if (unlikely(!func)) { + dev_dbg(kfd_device, "no function\n"); + retcode = -EINVAL; + goto err_i1; } - if (err < 0) - dev_err(kfd_device, - "ioctl error %ld for ioctl cmd 0x%x (#%d)\n", - err, cmd, _IOC_NR(cmd)); + if (cmd & (IOC_IN | IOC_OUT)) { + if (asize <= sizeof(stack_kdata)) { + kdata = stack_kdata; + } else { + kdata = kmalloc(asize, GFP_KERNEL); + if (!kdata) { + retcode = -ENOMEM; + goto err_i1; + } + } + if (asize > usize) + memset(kdata + usize, 0, asize - usize); + } - return err; + if (cmd & IOC_IN) { + if (copy_from_user(kdata, (void __user *)arg, usize) != 0) { + retcode = -EFAULT; + goto err_i1; + } + } else if (cmd & IOC_OUT) { + memset(kdata, 0, usize); + } + + retcode = func(filep, process, kdata); + + if (cmd & IOC_OUT) + if (copy_to_user((void __user *)arg, kdata, usize) != 0) + retcode = -EFAULT; + +err_i1: + if (!ioctl) + dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n", + task_pid_nr(current), cmd, nr); + + if (kdata != stack_kdata) + kfree(kdata); + + if (retcode) + dev_dbg(kfd_device, "ret = %d\n", retcode); + + return retcode; } static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 994a9c1bdd04..1ba8332419fa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -31,6 +31,14 @@ #define MQD_SIZE_ALIGNED 768 static const struct kfd_device_info kaveri_device_info = { + .asic_family = CHIP_KAVERI, + .max_pasid_bits = 16, + .ih_ring_entry_size = 4 * sizeof(uint32_t), + .mqd_size_aligned = MQD_SIZE_ALIGNED +}; + +static const struct kfd_device_info carrizo_device_info = { + .asic_family = CHIP_CARRIZO, .max_pasid_bits = 16, .ih_ring_entry_size = 4 * sizeof(uint32_t), .num_of_watch_points = 4, @@ -65,7 +73,7 @@ static const struct kfd_deviceid supported_devices[] = { { 0x1318, &kaveri_device_info }, /* Kaveri */ { 0x131B, &kaveri_device_info }, /* Kaveri */ { 0x131C, &kaveri_device_info }, /* Kaveri */ - { 0x131D, &kaveri_device_info }, /* Kaveri */ + { 0x131D, &kaveri_device_info } /* Kaveri */ }; static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, @@ -221,13 +229,6 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, goto kfd_topology_add_device_error; } - if (kfd_interrupt_init(kfd)) { - dev_err(kfd_device, - "Error initializing interrupts for device (%x:%x)\n", - kfd->pdev->vendor, kfd->pdev->device); - goto kfd_interrupt_error; - } - if (!device_iommu_pasid_init(kfd)) { dev_err(kfd_device, "Error initializing iommuv2 for device (%x:%x)\n", @@ -245,7 +246,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, goto device_queue_manager_error; } - if (kfd->dqm->start(kfd->dqm) != 0) { + if (kfd->dqm->ops.start(kfd->dqm) != 0) { dev_err(kfd_device, "Error starting queuen manager for device (%x:%x)\n", kfd->pdev->vendor, kfd->pdev->device); @@ -266,8 +267,6 @@ dqm_start_error: device_queue_manager_error: amd_iommu_free_device(kfd->pdev); device_iommu_pasid_error: - kfd_interrupt_exit(kfd); -kfd_interrupt_error: kfd_topology_remove_device(kfd); kfd_topology_add_device_error: kfd_gtt_sa_fini(kfd); @@ -285,7 +284,6 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) if (kfd->init_complete) { device_queue_manager_uninit(kfd->dqm); amd_iommu_free_device(kfd->pdev); - kfd_interrupt_exit(kfd); kfd_topology_remove_device(kfd); kfd_gtt_sa_fini(kfd); kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); @@ -299,7 +297,7 @@ void kgd2kfd_suspend(struct kfd_dev *kfd) BUG_ON(kfd == NULL); if (kfd->init_complete) { - kfd->dqm->stop(kfd->dqm); + kfd->dqm->ops.stop(kfd->dqm); amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL); amd_iommu_free_device(kfd->pdev); } @@ -320,7 +318,7 @@ int kgd2kfd_resume(struct kfd_dev *kfd) return -ENXIO; amd_iommu_set_invalidate_ctx_cb(kfd->pdev, iommu_pasid_shutdown_callback); - kfd->dqm->start(kfd->dqm); + kfd->dqm->ops.start(kfd->dqm); } return 0; @@ -329,15 +327,7 @@ int kgd2kfd_resume(struct kfd_dev *kfd) /* This is called directly from KGD at ISR. */ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) { - if (kfd->init_complete) { - spin_lock(&kfd->interrupt_lock); - - if (kfd->interrupts_active - && enqueue_ih_ring_entry(kfd, ih_ring_entry)) - schedule_work(&kfd->interrupt_work); - - spin_unlock(&kfd->interrupt_lock); - } + /* Process interrupts / schedule work as necessary */ } static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, @@ -503,7 +493,10 @@ int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) unsigned int bit; BUG_ON(!kfd); - BUG_ON(!mem_obj); + + /* Act like kfree when trying to free a NULL object */ + if (!mem_obj) + return 0; pr_debug("kfd: free mem_obj = %p, range_start = %d, range_end = %d\n", mem_obj, mem_obj->range_start, mem_obj->range_end); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 6806e64c5ffd..a5c69e96ba6f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -26,20 +26,17 @@ #include <linux/types.h> #include <linux/printk.h> #include <linux/bitops.h> +#include <linux/sched.h> #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_mqd_manager.h" #include "cik_regs.h" #include "kfd_kernel_queue.h" -#include "../../radeon/cik_reg.h" /* Size of the per-pipe EOP queue */ #define CIK_HPD_EOP_BYTES_LOG2 11 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) -static bool is_mem_initialized; - -static int init_memory(struct device_queue_manager *dqm); static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid, unsigned int vmid); @@ -61,11 +58,11 @@ static inline enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) { if (type == KFD_QUEUE_TYPE_SDMA) - return KFD_MQD_TYPE_CIK_SDMA; - return KFD_MQD_TYPE_CIK_CP; + return KFD_MQD_TYPE_SDMA; + return KFD_MQD_TYPE_CP; } -static inline unsigned int get_pipes_num(struct device_queue_manager *dqm) +inline unsigned int get_pipes_num(struct device_queue_manager *dqm) { BUG_ON(!dqm || !dqm->dev); return dqm->dev->shared_resources.compute_pipe_count; @@ -82,7 +79,7 @@ static inline unsigned int get_pipes_num_cpsch(void) return PIPE_PER_ME_CP_SCHEDULING; } -static inline unsigned int +inline unsigned int get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd) { uint32_t nybble; @@ -92,7 +89,7 @@ get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd) return nybble; } -static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) +inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) { unsigned int shared_base; @@ -101,41 +98,7 @@ static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) return shared_base; } -static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble); -static void init_process_memory(struct device_queue_manager *dqm, - struct qcm_process_device *qpd) -{ - struct kfd_process_device *pdd; - unsigned int temp; - - BUG_ON(!dqm || !qpd); - - pdd = qpd_to_pdd(qpd); - - /* check if sh_mem_config register already configured */ - if (qpd->sh_mem_config == 0) { - qpd->sh_mem_config = - ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) | - DEFAULT_MTYPE(MTYPE_NONCACHED) | - APE1_MTYPE(MTYPE_NONCACHED); - qpd->sh_mem_ape1_limit = 0; - qpd->sh_mem_ape1_base = 0; - } - - if (qpd->pqm->process->is_32bit_user_mode) { - temp = get_sh_mem_bases_32(pdd); - qpd->sh_mem_bases = SHARED_BASE(temp); - qpd->sh_mem_config |= PTR32; - } else { - temp = get_sh_mem_bases_nybble_64(pdd); - qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); - } - - pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", - qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); -} - -static void program_sh_mem_settings(struct device_queue_manager *dqm, +void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { return kfd2kgd->program_sh_mem_settings(dqm->dev->kgd, qpd->vmid, @@ -175,6 +138,9 @@ static void deallocate_vmid(struct device_queue_manager *dqm, { int bit = qpd->vmid - KFD_VMID_START_OFFSET; + /* Release the vmid mapping */ + set_pasid_vmid_mapping(dqm, 0, qpd->vmid); + set_bit(bit, (unsigned long *)&dqm->vmid_bitmap); qpd->vmid = 0; q->properties.vmid = 0; @@ -229,12 +195,12 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) { bool set; - int pipe, bit; + int pipe, bit, i; set = false; - for (pipe = dqm->next_pipe_to_allocate; pipe < get_pipes_num(dqm); - pipe = (pipe + 1) % get_pipes_num(dqm)) { + for (pipe = dqm->next_pipe_to_allocate, i = 0; i < get_pipes_num(dqm); + pipe = ((pipe + 1) % get_pipes_num(dqm)), ++i) { if (dqm->allocated_queues[pipe] != 0) { bit = find_first_bit( (unsigned long *)&dqm->allocated_queues[pipe], @@ -275,7 +241,7 @@ static int create_compute_queue_nocpsch(struct device_queue_manager *dqm, BUG_ON(!dqm || !q || !qpd); - mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_CIK_COMPUTE); + mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE); if (mqd == NULL) return -ENOMEM; @@ -290,6 +256,18 @@ static int create_compute_queue_nocpsch(struct device_queue_manager *dqm, return retval; } + pr_debug("kfd: loading mqd to hqd on pipe (%d) queue (%d)\n", + q->pipe, + q->queue); + + retval = mqd->load_mqd(mqd, q->mqd, q->pipe, + q->queue, (uint32_t __user *) q->properties.write_ptr); + if (retval != 0) { + deallocate_hqd(dqm, q); + mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); + return retval; + } + return 0; } @@ -298,7 +276,8 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, struct queue *q) { int retval; - struct mqd_manager *mqd, *mqd_sdma; + struct mqd_manager *mqd; + BUG_ON(!dqm || !q || !q->mqd || !qpd); retval = 0; @@ -306,33 +285,32 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, pr_debug("kfd: In Func %s\n", __func__); mutex_lock(&dqm->lock); - mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_CIK_COMPUTE); - if (mqd == NULL) { - retval = -ENOMEM; - goto out; - } - mqd_sdma = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_CIK_SDMA); - if (mqd_sdma == NULL) { - mutex_unlock(&dqm->lock); - return -ENOMEM; + if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { + mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE); + if (mqd == NULL) { + retval = -ENOMEM; + goto out; + } + deallocate_hqd(dqm, q); + } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { + mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA); + if (mqd == NULL) { + retval = -ENOMEM; + goto out; + } + dqm->sdma_queue_count--; + deallocate_sdma_queue(dqm, q->sdma_id); } retval = mqd->destroy_mqd(mqd, q->mqd, - KFD_PREEMPT_TYPE_WAVEFRONT, + KFD_PREEMPT_TYPE_WAVEFRONT_RESET, QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS, q->pipe, q->queue); if (retval != 0) goto out; - if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) - deallocate_hqd(dqm, q); - else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { - dqm->sdma_queue_count--; - deallocate_sdma_queue(dqm, q->sdma_id); - } - mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); list_del(&q->list); @@ -348,20 +326,29 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q) { int retval; struct mqd_manager *mqd; + bool prev_active = false; BUG_ON(!dqm || !q || !q->mqd); mutex_lock(&dqm->lock); - mqd = dqm->get_mqd_manager(dqm, q->properties.type); + mqd = dqm->ops.get_mqd_manager(dqm, q->properties.type); if (mqd == NULL) { mutex_unlock(&dqm->lock); return -ENOMEM; } - retval = mqd->update_mqd(mqd, q->mqd, &q->properties); if (q->properties.is_active == true) + prev_active = true; + + /* + * + * check active state vs. the previous state + * and modify counter accordingly + */ + retval = mqd->update_mqd(mqd, q->mqd, &q->properties); + if ((q->properties.is_active == true) && (prev_active == false)) dqm->queue_count++; - else + else if ((q->properties.is_active == false) && (prev_active == true)) dqm->queue_count--; if (sched_policy != KFD_SCHED_POLICY_NO_HWS) @@ -395,6 +382,7 @@ static int register_process_nocpsch(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { struct device_process_node *n; + int retval; BUG_ON(!dqm || !qpd); @@ -409,12 +397,13 @@ static int register_process_nocpsch(struct device_queue_manager *dqm, mutex_lock(&dqm->lock); list_add(&n->list, &dqm->queues); - init_process_memory(dqm, qpd); + retval = dqm->ops_asic_specific.register_process(dqm, qpd); + dqm->processes_count++; mutex_unlock(&dqm->lock); - return 0; + return retval; } static int unregister_process_nocpsch(struct device_queue_manager *dqm, @@ -459,48 +448,7 @@ set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid, vmid); } -static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) -{ - /* In 64-bit mode, we can only control the top 3 bits of the LDS, - * scratch and GPUVM apertures. - * The hardware fills in the remaining 59 bits according to the - * following pattern: - * LDS: X0000000'00000000 - X0000001'00000000 (4GB) - * Scratch: X0000001'00000000 - X0000002'00000000 (4GB) - * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB) - * - * (where X/Y is the configurable nybble with the low-bit 0) - * - * LDS and scratch will have the same top nybble programmed in the - * top 3 bits of SH_MEM_BASES.PRIVATE_BASE. - * GPUVM can have a different top nybble programmed in the - * top 3 bits of SH_MEM_BASES.SHARED_BASE. - * We don't bother to support different top nybbles - * for LDS/Scratch and GPUVM. - */ - - BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE || - top_address_nybble == 0); - - return PRIVATE_BASE(top_address_nybble << 12) | - SHARED_BASE(top_address_nybble << 12); -} - -static int init_memory(struct device_queue_manager *dqm) -{ - int i, retval; - - for (i = 8; i < 16; i++) - set_pasid_vmid_mapping(dqm, 0, i); - - retval = kfd2kgd->init_memory(dqm->dev->kgd); - if (retval == 0) - is_mem_initialized = true; - return retval; -} - - -static int init_pipelines(struct device_queue_manager *dqm, +int init_pipelines(struct device_queue_manager *dqm, unsigned int pipes_num, unsigned int first_pipe) { void *hpdptr; @@ -533,7 +481,7 @@ static int init_pipelines(struct device_queue_manager *dqm, memset(hpdptr, 0, CIK_HPD_EOP_BYTES * pipes_num); - mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_CIK_COMPUTE); + mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE); if (mqd == NULL) { kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem); return -ENOMEM; @@ -560,10 +508,6 @@ static int init_scheduler(struct device_queue_manager *dqm) pr_debug("kfd: In %s\n", __func__); retval = init_pipelines(dqm, get_pipes_num(dqm), KFD_DQM_FIRST_PIPE); - if (retval != 0) - return retval; - - retval = init_memory(dqm); return retval; } @@ -668,7 +612,7 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, struct mqd_manager *mqd; int retval; - mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_CIK_SDMA); + mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA); if (!mqd) return -ENOMEM; @@ -737,7 +681,7 @@ static int initialize_cpsch(struct device_queue_manager *dqm) dqm->queue_count = dqm->processes_count = 0; dqm->sdma_queue_count = 0; dqm->active_runlist = false; - retval = init_pipelines(dqm, get_pipes_num(dqm), 0); + retval = dqm->ops_asic_specific.initialize(dqm); if (retval != 0) goto fail_init_pipelines; @@ -871,7 +815,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, if (q->properties.type == KFD_QUEUE_TYPE_SDMA) select_sdma_engine_id(q); - mqd = dqm->get_mqd_manager(dqm, + mqd = dqm->ops.get_mqd_manager(dqm, get_mqd_type_from_queue_type(q->properties.type)); if (mqd == NULL) { @@ -910,7 +854,7 @@ static int fence_wait_timeout(unsigned int *fence_addr, pr_err("kfd: qcm fence wait loop timeout expired\n"); return -ETIME; } - cpu_relax(); + schedule(); } return 0; @@ -1016,7 +960,7 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, /* remove queue from list to prevent rescheduling after preemption */ mutex_lock(&dqm->lock); - mqd = dqm->get_mqd_manager(dqm, + mqd = dqm->ops.get_mqd_manager(dqm, get_mqd_type_from_queue_type(q->properties.type)); if (!mqd) { retval = -ENOMEM; @@ -1057,8 +1001,7 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, void __user *alternate_aperture_base, uint64_t alternate_aperture_size) { - uint32_t default_mtype; - uint32_t ape1_mtype; + bool retval; pr_debug("kfd: In func %s\n", __func__); @@ -1095,18 +1038,13 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, qpd->sh_mem_ape1_limit = limit >> 16; } - default_mtype = (default_policy == cache_policy_coherent) ? - MTYPE_NONCACHED : - MTYPE_CACHED; - - ape1_mtype = (alternate_policy == cache_policy_coherent) ? - MTYPE_NONCACHED : - MTYPE_CACHED; - - qpd->sh_mem_config = (qpd->sh_mem_config & PTR32) - | ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) - | DEFAULT_MTYPE(default_mtype) - | APE1_MTYPE(ape1_mtype); + retval = dqm->ops_asic_specific.set_cache_memory_policy( + dqm, + qpd, + default_policy, + alternate_policy, + alternate_aperture_base, + alternate_aperture_size); if ((sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) program_sh_mem_settings(dqm, qpd); @@ -1116,7 +1054,7 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, qpd->sh_mem_ape1_limit); mutex_unlock(&dqm->lock); - return true; + return retval; out: mutex_unlock(&dqm->lock); @@ -1129,6 +1067,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) BUG_ON(!dev); + pr_debug("kfd: loading device queue manager\n"); + dqm = kzalloc(sizeof(struct device_queue_manager), GFP_KERNEL); if (!dqm) return NULL; @@ -1138,40 +1078,47 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) case KFD_SCHED_POLICY_HWS: case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: /* initialize dqm for cp scheduling */ - dqm->create_queue = create_queue_cpsch; - dqm->initialize = initialize_cpsch; - dqm->start = start_cpsch; - dqm->stop = stop_cpsch; - dqm->destroy_queue = destroy_queue_cpsch; - dqm->update_queue = update_queue; - dqm->get_mqd_manager = get_mqd_manager_nocpsch; - dqm->register_process = register_process_nocpsch; - dqm->unregister_process = unregister_process_nocpsch; - dqm->uninitialize = uninitialize_nocpsch; - dqm->create_kernel_queue = create_kernel_queue_cpsch; - dqm->destroy_kernel_queue = destroy_kernel_queue_cpsch; - dqm->set_cache_memory_policy = set_cache_memory_policy; + dqm->ops.create_queue = create_queue_cpsch; + dqm->ops.initialize = initialize_cpsch; + dqm->ops.start = start_cpsch; + dqm->ops.stop = stop_cpsch; + dqm->ops.destroy_queue = destroy_queue_cpsch; + dqm->ops.update_queue = update_queue; + dqm->ops.get_mqd_manager = get_mqd_manager_nocpsch; + dqm->ops.register_process = register_process_nocpsch; + dqm->ops.unregister_process = unregister_process_nocpsch; + dqm->ops.uninitialize = uninitialize_nocpsch; + dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; + dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; + dqm->ops.set_cache_memory_policy = set_cache_memory_policy; break; case KFD_SCHED_POLICY_NO_HWS: /* initialize dqm for no cp scheduling */ - dqm->start = start_nocpsch; - dqm->stop = stop_nocpsch; - dqm->create_queue = create_queue_nocpsch; - dqm->destroy_queue = destroy_queue_nocpsch; - dqm->update_queue = update_queue; - dqm->get_mqd_manager = get_mqd_manager_nocpsch; - dqm->register_process = register_process_nocpsch; - dqm->unregister_process = unregister_process_nocpsch; - dqm->initialize = initialize_nocpsch; - dqm->uninitialize = uninitialize_nocpsch; - dqm->set_cache_memory_policy = set_cache_memory_policy; + dqm->ops.start = start_nocpsch; + dqm->ops.stop = stop_nocpsch; + dqm->ops.create_queue = create_queue_nocpsch; + dqm->ops.destroy_queue = destroy_queue_nocpsch; + dqm->ops.update_queue = update_queue; + dqm->ops.get_mqd_manager = get_mqd_manager_nocpsch; + dqm->ops.register_process = register_process_nocpsch; + dqm->ops.unregister_process = unregister_process_nocpsch; + dqm->ops.initialize = initialize_nocpsch; + dqm->ops.uninitialize = uninitialize_nocpsch; + dqm->ops.set_cache_memory_policy = set_cache_memory_policy; break; default: BUG(); break; } - if (dqm->initialize(dqm) != 0) { + switch (dev->device_info->asic_family) { + case CHIP_CARRIZO: + device_queue_manager_init_vi(&dqm->ops_asic_specific); + case CHIP_KAVERI: + device_queue_manager_init_cik(&dqm->ops_asic_specific); + } + + if (dqm->ops.initialize(dqm) != 0) { kfree(dqm); return NULL; } @@ -1183,7 +1130,6 @@ void device_queue_manager_uninit(struct device_queue_manager *dqm) { BUG_ON(!dqm); - dqm->uninitialize(dqm); + dqm->ops.uninitialize(dqm); kfree(dqm); } - diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 554c06ee8892..19347956eeb9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -46,7 +46,7 @@ struct device_process_node { }; /** - * struct device_queue_manager + * struct device_queue_manager_ops * * @create_queue: Queue creation routine. * @@ -81,15 +81,9 @@ struct device_process_node { * @set_cache_memory_policy: Sets memory policy (cached/ non cached) for the * memory apertures. * - * This struct is a base class for the kfd queues scheduler in the - * device level. The device base class should expose the basic operations - * for queue creation and queue destruction. This base class hides the - * scheduling mode of the driver and the specific implementation of the - * concrete device. This class is the only class in the queues scheduler - * that configures the H/W. */ -struct device_queue_manager { +struct device_queue_manager_ops { int (*create_queue)(struct device_queue_manager *dqm, struct queue *q, struct qcm_process_device *qpd, @@ -124,7 +118,23 @@ struct device_queue_manager { enum cache_policy alternate_policy, void __user *alternate_aperture_base, uint64_t alternate_aperture_size); +}; + +/** + * struct device_queue_manager + * + * This struct is a base class for the kfd queues scheduler in the + * device level. The device base class should expose the basic operations + * for queue creation and queue destruction. This base class hides the + * scheduling mode of the driver and the specific implementation of the + * concrete device. This class is the only class in the queues scheduler + * that configures the H/W. + * + */ +struct device_queue_manager { + struct device_queue_manager_ops ops; + struct device_queue_manager_ops ops_asic_specific; struct mqd_manager *mqds[KFD_MQD_TYPE_MAX]; struct packet_manager packets; @@ -146,6 +156,14 @@ struct device_queue_manager { bool active_runlist; }; - +void device_queue_manager_init_cik(struct device_queue_manager_ops *ops); +void device_queue_manager_init_vi(struct device_queue_manager_ops *ops); +void program_sh_mem_settings(struct device_queue_manager *dqm, + struct qcm_process_device *qpd); +inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *qpd); +inline unsigned int get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd); +int init_pipelines(struct device_queue_manager *dqm, + unsigned int pipes_num, unsigned int first_pipe); +inline unsigned int get_pipes_num(struct device_queue_manager *dqm); #endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c new file mode 100644 index 000000000000..6b072466e2a6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c @@ -0,0 +1,135 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "kfd_device_queue_manager.h" +#include "cik_regs.h" + +static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, + struct qcm_process_device *qpd, + enum cache_policy default_policy, + enum cache_policy alternate_policy, + void __user *alternate_aperture_base, + uint64_t alternate_aperture_size); +static int register_process_cik(struct device_queue_manager *dqm, + struct qcm_process_device *qpd); +static int initialize_cpsch_cik(struct device_queue_manager *dqm); + +void device_queue_manager_init_cik(struct device_queue_manager_ops *ops) +{ + ops->set_cache_memory_policy = set_cache_memory_policy_cik; + ops->register_process = register_process_cik; + ops->initialize = initialize_cpsch_cik; +} + +static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) +{ + /* In 64-bit mode, we can only control the top 3 bits of the LDS, + * scratch and GPUVM apertures. + * The hardware fills in the remaining 59 bits according to the + * following pattern: + * LDS: X0000000'00000000 - X0000001'00000000 (4GB) + * Scratch: X0000001'00000000 - X0000002'00000000 (4GB) + * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB) + * + * (where X/Y is the configurable nybble with the low-bit 0) + * + * LDS and scratch will have the same top nybble programmed in the + * top 3 bits of SH_MEM_BASES.PRIVATE_BASE. + * GPUVM can have a different top nybble programmed in the + * top 3 bits of SH_MEM_BASES.SHARED_BASE. + * We don't bother to support different top nybbles + * for LDS/Scratch and GPUVM. + */ + + BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE || + top_address_nybble == 0); + + return PRIVATE_BASE(top_address_nybble << 12) | + SHARED_BASE(top_address_nybble << 12); +} + +static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, + struct qcm_process_device *qpd, + enum cache_policy default_policy, + enum cache_policy alternate_policy, + void __user *alternate_aperture_base, + uint64_t alternate_aperture_size) +{ + uint32_t default_mtype; + uint32_t ape1_mtype; + + default_mtype = (default_policy == cache_policy_coherent) ? + MTYPE_NONCACHED : + MTYPE_CACHED; + + ape1_mtype = (alternate_policy == cache_policy_coherent) ? + MTYPE_NONCACHED : + MTYPE_CACHED; + + qpd->sh_mem_config = (qpd->sh_mem_config & PTR32) + | ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) + | DEFAULT_MTYPE(default_mtype) + | APE1_MTYPE(ape1_mtype); + + return true; +} + +static int register_process_cik(struct device_queue_manager *dqm, + struct qcm_process_device *qpd) +{ + struct kfd_process_device *pdd; + unsigned int temp; + + BUG_ON(!dqm || !qpd); + + pdd = qpd_to_pdd(qpd); + + /* check if sh_mem_config register already configured */ + if (qpd->sh_mem_config == 0) { + qpd->sh_mem_config = + ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) | + DEFAULT_MTYPE(MTYPE_NONCACHED) | + APE1_MTYPE(MTYPE_NONCACHED); + qpd->sh_mem_ape1_limit = 0; + qpd->sh_mem_ape1_base = 0; + } + + if (qpd->pqm->process->is_32bit_user_mode) { + temp = get_sh_mem_bases_32(pdd); + qpd->sh_mem_bases = SHARED_BASE(temp); + qpd->sh_mem_config |= PTR32; + } else { + temp = get_sh_mem_bases_nybble_64(pdd); + qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); + } + + pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", + qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); + + return 0; +} + +static int initialize_cpsch_cik(struct device_queue_manager *dqm) +{ + return init_pipelines(dqm, get_pipes_num(dqm), 0); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c new file mode 100644 index 000000000000..20553dcd257d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c @@ -0,0 +1,64 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "kfd_device_queue_manager.h" + +static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, + struct qcm_process_device *qpd, + enum cache_policy default_policy, + enum cache_policy alternate_policy, + void __user *alternate_aperture_base, + uint64_t alternate_aperture_size); +static int register_process_vi(struct device_queue_manager *dqm, + struct qcm_process_device *qpd); +static int initialize_cpsch_vi(struct device_queue_manager *dqm); + +void device_queue_manager_init_vi(struct device_queue_manager_ops *ops) +{ + pr_warn("amdkfd: VI DQM is not currently supported\n"); + + ops->set_cache_memory_policy = set_cache_memory_policy_vi; + ops->register_process = register_process_vi; + ops->initialize = initialize_cpsch_vi; +} + +static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, + struct qcm_process_device *qpd, + enum cache_policy default_policy, + enum cache_policy alternate_policy, + void __user *alternate_aperture_base, + uint64_t alternate_aperture_size) +{ + return false; +} + +static int register_process_vi(struct device_queue_manager *dqm, + struct qcm_process_device *qpd) +{ + return -1; +} + +static int initialize_cpsch_vi(struct device_queue_manager *dqm) +{ + return 0; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c deleted file mode 100644 index 5b999095a1f7..000000000000 --- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * KFD Interrupts. - * - * AMD GPUs deliver interrupts by pushing an interrupt description onto the - * interrupt ring and then sending an interrupt. KGD receives the interrupt - * in ISR and sends us a pointer to each new entry on the interrupt ring. - * - * We generally can't process interrupt-signaled events from ISR, so we call - * out to each interrupt client module (currently only the scheduler) to ask if - * each interrupt is interesting. If they return true, then it requires further - * processing so we copy it to an internal interrupt ring and call each - * interrupt client again from a work-queue. - * - * There's no acknowledgment for the interrupts we use. The hardware simply - * queues a new interrupt each time without waiting. - * - * The fixed-size internal queue means that it's possible for us to lose - * interrupts because we have no back-pressure to the hardware. - */ - -#include <linux/slab.h> -#include <linux/device.h> -#include "kfd_priv.h" - -#define KFD_INTERRUPT_RING_SIZE 256 - -static void interrupt_wq(struct work_struct *); - -int kfd_interrupt_init(struct kfd_dev *kfd) -{ - void *interrupt_ring = kmalloc_array(KFD_INTERRUPT_RING_SIZE, - kfd->device_info->ih_ring_entry_size, - GFP_KERNEL); - if (!interrupt_ring) - return -ENOMEM; - - kfd->interrupt_ring = interrupt_ring; - kfd->interrupt_ring_size = - KFD_INTERRUPT_RING_SIZE * kfd->device_info->ih_ring_entry_size; - atomic_set(&kfd->interrupt_ring_wptr, 0); - atomic_set(&kfd->interrupt_ring_rptr, 0); - - spin_lock_init(&kfd->interrupt_lock); - - INIT_WORK(&kfd->interrupt_work, interrupt_wq); - - kfd->interrupts_active = true; - - /* - * After this function returns, the interrupt will be enabled. This - * barrier ensures that the interrupt running on a different processor - * sees all the above writes. - */ - smp_wmb(); - - return 0; -} - -void kfd_interrupt_exit(struct kfd_dev *kfd) -{ - /* - * Stop the interrupt handler from writing to the ring and scheduling - * workqueue items. The spinlock ensures that any interrupt running - * after we have unlocked sees interrupts_active = false. - */ - unsigned long flags; - - spin_lock_irqsave(&kfd->interrupt_lock, flags); - kfd->interrupts_active = false; - spin_unlock_irqrestore(&kfd->interrupt_lock, flags); - - /* - * Flush_scheduled_work ensures that there are no outstanding - * work-queue items that will access interrupt_ring. New work items - * can't be created because we stopped interrupt handling above. - */ - flush_scheduled_work(); - - kfree(kfd->interrupt_ring); -} - -/* - * This assumes that it can't be called concurrently with itself - * but only with dequeue_ih_ring_entry. - */ -bool enqueue_ih_ring_entry(struct kfd_dev *kfd, const void *ih_ring_entry) -{ - unsigned int rptr = atomic_read(&kfd->interrupt_ring_rptr); - unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); - - if ((rptr - wptr) % kfd->interrupt_ring_size == - kfd->device_info->ih_ring_entry_size) { - /* This is very bad, the system is likely to hang. */ - dev_err_ratelimited(kfd_chardev(), - "Interrupt ring overflow, dropping interrupt.\n"); - return false; - } - - memcpy(kfd->interrupt_ring + wptr, ih_ring_entry, - kfd->device_info->ih_ring_entry_size); - - wptr = (wptr + kfd->device_info->ih_ring_entry_size) % - kfd->interrupt_ring_size; - smp_wmb(); /* Ensure memcpy'd data is visible before wptr update. */ - atomic_set(&kfd->interrupt_ring_wptr, wptr); - - return true; -} - -/* - * This assumes that it can't be called concurrently with itself - * but only with enqueue_ih_ring_entry. - */ -static bool dequeue_ih_ring_entry(struct kfd_dev *kfd, void *ih_ring_entry) -{ - /* - * Assume that wait queues have an implicit barrier, i.e. anything that - * happened in the ISR before it queued work is visible. - */ - - unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); - unsigned int rptr = atomic_read(&kfd->interrupt_ring_rptr); - - if (rptr == wptr) - return false; - - memcpy(ih_ring_entry, kfd->interrupt_ring + rptr, - kfd->device_info->ih_ring_entry_size); - - rptr = (rptr + kfd->device_info->ih_ring_entry_size) % - kfd->interrupt_ring_size; - - /* - * Ensure the rptr write update is not visible until - * memcpy has finished reading. - */ - smp_mb(); - atomic_set(&kfd->interrupt_ring_rptr, rptr); - - return true; -} - -static void interrupt_wq(struct work_struct *work) -{ - struct kfd_dev *dev = container_of(work, struct kfd_dev, - interrupt_work); - - uint32_t ih_ring_entry[DIV_ROUND_UP( - dev->device_info->ih_ring_entry_size, - sizeof(uint32_t))]; - - while (dequeue_ih_ring_entry(dev, ih_ring_entry)) - ; -} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index 0fd8bb7c863e..c04b1ac60bd9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -56,8 +56,8 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, switch (type) { case KFD_QUEUE_TYPE_DIQ: case KFD_QUEUE_TYPE_HIQ: - kq->mqd = dev->dqm->get_mqd_manager(dev->dqm, - KFD_MQD_TYPE_CIK_HIQ); + kq->mqd = dev->dqm->ops.get_mqd_manager(dev->dqm, + KFD_MQD_TYPE_HIQ); break; default: BUG(); @@ -73,13 +73,16 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, goto err_get_kernel_doorbell; retval = kfd_gtt_sa_allocate(dev, queue_size, &kq->pq); - if (retval != 0) goto err_pq_allocate_vidmem; kq->pq_kernel_addr = kq->pq->cpu_ptr; kq->pq_gpu_addr = kq->pq->gpu_addr; + retval = kq->ops_asic_specific.initialize(kq, dev, type, queue_size); + if (retval == false) + goto err_eop_allocate_vidmem; + retval = kfd_gtt_sa_allocate(dev, sizeof(*kq->rptr_kernel), &kq->rptr_mem); @@ -111,6 +114,8 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, prop.queue_address = kq->pq_gpu_addr; prop.read_ptr = (uint32_t *) kq->rptr_gpu_addr; prop.write_ptr = (uint32_t *) kq->wptr_gpu_addr; + prop.eop_ring_buffer_address = kq->eop_gpu_addr; + prop.eop_ring_buffer_size = PAGE_SIZE; if (init_queue(&kq->queue, prop) != 0) goto err_init_queue; @@ -156,6 +161,8 @@ err_init_queue: err_wptr_allocate_vidmem: kfd_gtt_sa_free(dev, kq->rptr_mem); err_rptr_allocate_vidmem: + kfd_gtt_sa_free(dev, kq->eop_mem); +err_eop_allocate_vidmem: kfd_gtt_sa_free(dev, kq->pq); err_pq_allocate_vidmem: pr_err("kfd: error init pq\n"); @@ -182,6 +189,7 @@ static void uninitialize(struct kernel_queue *kq) kfd_gtt_sa_free(kq->dev, kq->rptr_mem); kfd_gtt_sa_free(kq->dev, kq->wptr_mem); + kq->ops_asic_specific.uninitialize(kq); kfd_gtt_sa_free(kq->dev, kq->pq); kfd_release_kernel_doorbell(kq->dev, kq->queue->properties.doorbell_ptr); @@ -254,28 +262,6 @@ static void submit_packet(struct kernel_queue *kq) kq->pending_wptr); } -static int sync_with_hw(struct kernel_queue *kq, unsigned long timeout_ms) -{ - unsigned long org_timeout_ms; - - BUG_ON(!kq); - - org_timeout_ms = timeout_ms; - timeout_ms += jiffies * 1000 / HZ; - while (*kq->wptr_kernel != *kq->rptr_kernel) { - if (time_after(jiffies * 1000 / HZ, timeout_ms)) { - pr_err("kfd: kernel_queue %s timeout expired %lu\n", - __func__, org_timeout_ms); - pr_err("kfd: wptr: %d rptr: %d\n", - *kq->wptr_kernel, *kq->rptr_kernel); - return -ETIME; - } - schedule(); - } - - return 0; -} - static void rollback_packet(struct kernel_queue *kq) { BUG_ON(!kq); @@ -293,14 +279,20 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, if (!kq) return NULL; - kq->initialize = initialize; - kq->uninitialize = uninitialize; - kq->acquire_packet_buffer = acquire_packet_buffer; - kq->submit_packet = submit_packet; - kq->sync_with_hw = sync_with_hw; - kq->rollback_packet = rollback_packet; + kq->ops.initialize = initialize; + kq->ops.uninitialize = uninitialize; + kq->ops.acquire_packet_buffer = acquire_packet_buffer; + kq->ops.submit_packet = submit_packet; + kq->ops.rollback_packet = rollback_packet; + + switch (dev->device_info->asic_family) { + case CHIP_CARRIZO: + kernel_queue_init_vi(&kq->ops_asic_specific); + case CHIP_KAVERI: + kernel_queue_init_cik(&kq->ops_asic_specific); + } - if (kq->initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE) == false) { + if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE) == false) { pr_err("kfd: failed to init kernel queue\n"); kfree(kq); return NULL; @@ -312,7 +304,7 @@ void kernel_queue_uninit(struct kernel_queue *kq) { BUG_ON(!kq); - kq->uninitialize(kq); + kq->ops.uninitialize(kq); kfree(kq); } @@ -324,19 +316,18 @@ static __attribute__((unused)) void test_kq(struct kfd_dev *dev) BUG_ON(!dev); - pr_debug("kfd: starting kernel queue test\n"); + pr_err("kfd: starting kernel queue test\n"); kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_HIQ); BUG_ON(!kq); - retval = kq->acquire_packet_buffer(kq, 5, &buffer); + retval = kq->ops.acquire_packet_buffer(kq, 5, &buffer); BUG_ON(retval != 0); for (i = 0; i < 5; i++) buffer[i] = kq->nop_packet; - kq->submit_packet(kq); - kq->sync_with_hw(kq, 1000); + kq->ops.submit_packet(kq); - pr_debug("kfd: ending kernel queue test\n"); + pr_err("kfd: ending kernel queue test\n"); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h index dcd2bdb68d44..594053136ee4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h @@ -28,8 +28,31 @@ #include <linux/types.h> #include "kfd_priv.h" -struct kernel_queue { - /* interface */ +/** + * struct kernel_queue_ops + * + * @initialize: Initialize a kernel queue, including allocations of GART memory + * needed for the queue. + * + * @uninitialize: Uninitialize a kernel queue and free all its memory usages. + * + * @acquire_packet_buffer: Returns a pointer to the location in the kernel + * queue ring buffer where the calling function can write its packet. It is + * Guaranteed that there is enough space for that packet. It also updates the + * pending write pointer to that location so subsequent calls to + * acquire_packet_buffer will get a correct write pointer + * + * @submit_packet: Update the write pointer and doorbell of a kernel queue. + * + * @sync_with_hw: Wait until the write pointer and the read pointer of a kernel + * queue are equal, which means the CP has read all the submitted packets. + * + * @rollback_packet: This routine is called if we failed to build an acquired + * packet for some reason. It just overwrites the pending wptr with the current + * one + * + */ +struct kernel_queue_ops { bool (*initialize)(struct kernel_queue *kq, struct kfd_dev *dev, enum kfd_queue_type type, unsigned int queue_size); void (*uninitialize)(struct kernel_queue *kq); @@ -38,9 +61,12 @@ struct kernel_queue { unsigned int **buffer_ptr); void (*submit_packet)(struct kernel_queue *kq); - int (*sync_with_hw)(struct kernel_queue *kq, - unsigned long timeout_ms); void (*rollback_packet)(struct kernel_queue *kq); +}; + +struct kernel_queue { + struct kernel_queue_ops ops; + struct kernel_queue_ops ops_asic_specific; /* data */ struct kfd_dev *dev; @@ -58,6 +84,9 @@ struct kernel_queue { struct kfd_mem_obj *pq; uint64_t pq_gpu_addr; uint32_t *pq_kernel_addr; + struct kfd_mem_obj *eop_mem; + uint64_t eop_gpu_addr; + uint32_t *eop_kernel_addr; struct kfd_mem_obj *fence_mem_obj; uint64_t fence_gpu_addr; @@ -66,4 +95,7 @@ struct kernel_queue { struct list_head list; }; +void kernel_queue_init_cik(struct kernel_queue_ops *ops); +void kernel_queue_init_vi(struct kernel_queue_ops *ops); + #endif /* KFD_KERNEL_QUEUE_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c new file mode 100644 index 000000000000..a90eb440b1fb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c @@ -0,0 +1,44 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "kfd_kernel_queue.h" + +static bool initialize_cik(struct kernel_queue *kq, struct kfd_dev *dev, + enum kfd_queue_type type, unsigned int queue_size); +static void uninitialize_cik(struct kernel_queue *kq); + +void kernel_queue_init_cik(struct kernel_queue_ops *ops) +{ + ops->initialize = initialize_cik; + ops->uninitialize = uninitialize_cik; +} + +static bool initialize_cik(struct kernel_queue *kq, struct kfd_dev *dev, + enum kfd_queue_type type, unsigned int queue_size) +{ + return true; +} + +static void uninitialize_cik(struct kernel_queue *kq) +{ +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c new file mode 100644 index 000000000000..f1d48281e322 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c @@ -0,0 +1,56 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "kfd_kernel_queue.h" + +static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev, + enum kfd_queue_type type, unsigned int queue_size); +static void uninitialize_vi(struct kernel_queue *kq); + +void kernel_queue_init_vi(struct kernel_queue_ops *ops) +{ + ops->initialize = initialize_vi; + ops->uninitialize = uninitialize_vi; +} + +static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev, + enum kfd_queue_type type, unsigned int queue_size) +{ + int retval; + + retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem); + if (retval != 0) + return false; + + kq->eop_gpu_addr = kq->eop_mem->gpu_addr; + kq->eop_kernel_addr = kq->eop_mem->cpu_ptr; + + memset(kq->eop_kernel_addr, 0, PAGE_SIZE); + + return true; +} + +static void uninitialize_vi(struct kernel_queue *kq) +{ + kfd_gtt_sa_free(kq->dev, kq->eop_mem); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 95d5af138e6e..14c4115c4ae1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -48,7 +48,7 @@ static const struct kgd2kfd_calls kgd2kfd = { int sched_policy = KFD_SCHED_POLICY_HWS; module_param(sched_policy, int, 0444); MODULE_PARM_DESC(sched_policy, - "Kernel cmdline parameter that defines the amdkfd scheduling policy"); + "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); int max_num_of_processes = KFD_MAX_NUM_OF_PROCESSES_DEFAULT; module_param(max_num_of_processes, int, 0444); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c index 678c33f0a1b8..b1ef1368c3bb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c @@ -21,440 +21,17 @@ * */ -#include <linux/printk.h> -#include <linux/slab.h> #include "kfd_priv.h" -#include "kfd_mqd_manager.h" -#include "cik_regs.h" -#include "../../radeon/cikd.h" -#include "../../radeon/cik_reg.h" - -inline void busy_wait(unsigned long ms) -{ - while (time_before(jiffies, ms)) - cpu_relax(); -} - -static inline struct cik_mqd *get_mqd(void *mqd) -{ - return (struct cik_mqd *)mqd; -} - -static int init_mqd(struct mqd_manager *mm, void **mqd, - struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, - struct queue_properties *q) -{ - uint64_t addr; - struct cik_mqd *m; - int retval; - - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - - retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), - mqd_mem_obj); - - if (retval != 0) - return -ENOMEM; - - m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr; - addr = (*mqd_mem_obj)->gpu_addr; - - memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); - - m->header = 0xC0310800; - m->compute_pipelinestat_enable = 1; - m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; - m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; - m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; - m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; - - /* - * Make sure to use the last queue state saved on mqd when the cp - * reassigns the queue, so when queue is switched on/off (e.g over - * subscription or quantum timeout) the context will be consistent - */ - m->cp_hqd_persistent_state = - DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ; - - m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; - m->cp_mqd_base_addr_lo = lower_32_bits(addr); - m->cp_mqd_base_addr_hi = upper_32_bits(addr); - - m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE | IB_ATC_EN; - /* Although WinKFD writes this, I suspect it should not be necessary */ - m->cp_hqd_ib_control = IB_ATC_EN | DEFAULT_MIN_IB_AVAIL_SIZE; - - m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | - QUANTUM_DURATION(10); - - /* - * Pipe Priority - * Identifies the pipe relative priority when this queue is connected - * to the pipeline. The pipe priority is against the GFX pipe and HP3D. - * In KFD we are using a fixed pipe priority set to CS_MEDIUM. - * 0 = CS_LOW (typically below GFX) - * 1 = CS_MEDIUM (typically between HP3D and GFX - * 2 = CS_HIGH (typically above HP3D) - */ - m->cp_hqd_pipe_priority = 1; - m->cp_hqd_queue_priority = 15; - - *mqd = m; - if (gart_addr != NULL) - *gart_addr = addr; - retval = mm->update_mqd(mm, m, q); - - return retval; -} - -static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, - struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, - struct queue_properties *q) -{ - int retval; - struct cik_sdma_rlc_registers *m; - - BUG_ON(!mm || !mqd || !mqd_mem_obj); - - retval = kfd_gtt_sa_allocate(mm->dev, - sizeof(struct cik_sdma_rlc_registers), - mqd_mem_obj); - - if (retval != 0) - return -ENOMEM; - - m = (struct cik_sdma_rlc_registers *) (*mqd_mem_obj)->cpu_ptr; - - memset(m, 0, sizeof(struct cik_sdma_rlc_registers)); - - *mqd = m; - if (gart_addr != NULL) - *gart_addr = (*mqd_mem_obj)->gpu_addr; - - retval = mm->update_mqd(mm, m, q); - - return retval; -} - -static void uninit_mqd(struct mqd_manager *mm, void *mqd, - struct kfd_mem_obj *mqd_mem_obj) -{ - BUG_ON(!mm || !mqd); - kfd_gtt_sa_free(mm->dev, mqd_mem_obj); -} - -static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd, - struct kfd_mem_obj *mqd_mem_obj) -{ - BUG_ON(!mm || !mqd); - kfd_gtt_sa_free(mm->dev, mqd_mem_obj); -} - -static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr) -{ - return kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, wptr); -} - -static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, - uint32_t pipe_id, uint32_t queue_id, - uint32_t __user *wptr) -{ - return kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd); -} - -static int update_mqd(struct mqd_manager *mm, void *mqd, - struct queue_properties *q) -{ - struct cik_mqd *m; - - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - - m = get_mqd(mqd); - m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | - DEFAULT_MIN_AVAIL_SIZE | PQ_ATC_EN; - - /* - * Calculating queue size which is log base 2 of actual queue size -1 - * dwords and another -1 for ffs - */ - m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - - 1 - 1; - m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); - m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); - m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); - m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); - m->cp_hqd_pq_doorbell_control = DOORBELL_EN | - DOORBELL_OFFSET(q->doorbell_off); - - m->cp_hqd_vmid = q->vmid; - - if (q->format == KFD_QUEUE_FORMAT_AQL) { - m->cp_hqd_iq_rptr = AQL_ENABLE; - m->cp_hqd_pq_control |= NO_UPDATE_RPTR; - } - - m->cp_hqd_active = 0; - q->is_active = false; - if (q->queue_size > 0 && - q->queue_address != 0 && - q->queue_percent > 0) { - m->cp_hqd_active = 1; - q->is_active = true; - } - - return 0; -} - -static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, - struct queue_properties *q) -{ - struct cik_sdma_rlc_registers *m; - - BUG_ON(!mm || !mqd || !q); - - m = get_sdma_mqd(mqd); - m->sdma_rlc_rb_cntl = - SDMA_RB_SIZE((ffs(q->queue_size / sizeof(unsigned int)))) | - SDMA_RB_VMID(q->vmid) | - SDMA_RPTR_WRITEBACK_ENABLE | - SDMA_RPTR_WRITEBACK_TIMER(6); - - m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); - m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); - m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); - m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); - m->sdma_rlc_doorbell = SDMA_OFFSET(q->doorbell_off) | SDMA_DB_ENABLE; - m->sdma_rlc_virtual_addr = q->sdma_vm_addr; - - m->sdma_engine_id = q->sdma_engine_id; - m->sdma_queue_id = q->sdma_queue_id; - - q->is_active = false; - if (q->queue_size > 0 && - q->queue_address != 0 && - q->queue_percent > 0) { - m->sdma_rlc_rb_cntl |= SDMA_RB_ENABLE; - q->is_active = true; - } - - return 0; -} - -static int destroy_mqd(struct mqd_manager *mm, void *mqd, - enum kfd_preempt_type type, - unsigned int timeout, uint32_t pipe_id, - uint32_t queue_id) -{ - return kfd2kgd->hqd_destroy(mm->dev->kgd, type, timeout, - pipe_id, queue_id); -} - -/* - * preempt type here is ignored because there is only one way - * to preempt sdma queue - */ -static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, - enum kfd_preempt_type type, - unsigned int timeout, uint32_t pipe_id, - uint32_t queue_id) -{ - return kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); -} - -static bool is_occupied(struct mqd_manager *mm, void *mqd, - uint64_t queue_address, uint32_t pipe_id, - uint32_t queue_id) -{ - - return kfd2kgd->hqd_is_occupies(mm->dev->kgd, queue_address, - pipe_id, queue_id); - -} - -static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, - uint64_t queue_address, uint32_t pipe_id, - uint32_t queue_id) -{ - return kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); -} - -/* - * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation. - * The HIQ queue in Kaveri is using the same MQD structure as all the user mode - * queues but with different initial values. - */ - -static int init_mqd_hiq(struct mqd_manager *mm, void **mqd, - struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, - struct queue_properties *q) -{ - uint64_t addr; - struct cik_mqd *m; - int retval; - - BUG_ON(!mm || !q || !mqd || !mqd_mem_obj); - - pr_debug("kfd: In func %s\n", __func__); - - retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), - mqd_mem_obj); - - if (retval != 0) - return -ENOMEM; - - m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr; - addr = (*mqd_mem_obj)->gpu_addr; - - memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); - - m->header = 0xC0310800; - m->compute_pipelinestat_enable = 1; - m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; - m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; - m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; - m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; - - m->cp_hqd_persistent_state = DEFAULT_CP_HQD_PERSISTENT_STATE | - PRELOAD_REQ; - m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | - QUANTUM_DURATION(10); - - m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; - m->cp_mqd_base_addr_lo = lower_32_bits(addr); - m->cp_mqd_base_addr_hi = upper_32_bits(addr); - - m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE; - - /* - * Pipe Priority - * Identifies the pipe relative priority when this queue is connected - * to the pipeline. The pipe priority is against the GFX pipe and HP3D. - * In KFD we are using a fixed pipe priority set to CS_MEDIUM. - * 0 = CS_LOW (typically below GFX) - * 1 = CS_MEDIUM (typically between HP3D and GFX - * 2 = CS_HIGH (typically above HP3D) - */ - m->cp_hqd_pipe_priority = 1; - m->cp_hqd_queue_priority = 15; - - *mqd = m; - if (gart_addr) - *gart_addr = addr; - retval = mm->update_mqd(mm, m, q); - - return retval; -} - -static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, - struct queue_properties *q) -{ - struct cik_mqd *m; - - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - - m = get_mqd(mqd); - m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | - DEFAULT_MIN_AVAIL_SIZE | - PRIV_STATE | - KMD_QUEUE; - - /* - * Calculating queue size which is log base 2 of actual queue - * size -1 dwords - */ - m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - - 1 - 1; - m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); - m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); - m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); - m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); - m->cp_hqd_pq_doorbell_control = DOORBELL_EN | - DOORBELL_OFFSET(q->doorbell_off); - - m->cp_hqd_vmid = q->vmid; - - m->cp_hqd_active = 0; - q->is_active = false; - if (q->queue_size > 0 && - q->queue_address != 0 && - q->queue_percent > 0) { - m->cp_hqd_active = 1; - q->is_active = true; - } - - return 0; -} - -/* - * SDMA MQD Implementation - */ - -struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) -{ - struct cik_sdma_rlc_registers *m; - - BUG_ON(!mqd); - - m = (struct cik_sdma_rlc_registers *)mqd; - - return m; -} struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type, struct kfd_dev *dev) { - struct mqd_manager *mqd; - - BUG_ON(!dev); - BUG_ON(type >= KFD_MQD_TYPE_MAX); - - pr_debug("kfd: In func %s\n", __func__); - - mqd = kzalloc(sizeof(struct mqd_manager), GFP_KERNEL); - if (!mqd) - return NULL; - - mqd->dev = dev; - - switch (type) { - case KFD_MQD_TYPE_CIK_CP: - case KFD_MQD_TYPE_CIK_COMPUTE: - mqd->init_mqd = init_mqd; - mqd->uninit_mqd = uninit_mqd; - mqd->load_mqd = load_mqd; - mqd->update_mqd = update_mqd; - mqd->destroy_mqd = destroy_mqd; - mqd->is_occupied = is_occupied; - break; - case KFD_MQD_TYPE_CIK_HIQ: - mqd->init_mqd = init_mqd_hiq; - mqd->uninit_mqd = uninit_mqd; - mqd->load_mqd = load_mqd; - mqd->update_mqd = update_mqd_hiq; - mqd->destroy_mqd = destroy_mqd; - mqd->is_occupied = is_occupied; - break; - case KFD_MQD_TYPE_CIK_SDMA: - mqd->init_mqd = init_mqd_sdma; - mqd->uninit_mqd = uninit_mqd_sdma; - mqd->load_mqd = load_mqd_sdma; - mqd->update_mqd = update_mqd_sdma; - mqd->destroy_mqd = destroy_mqd_sdma; - mqd->is_occupied = is_occupied_sdma; - break; - default: - kfree(mqd); - return NULL; + switch (dev->device_info->asic_family) { + case CHIP_KAVERI: + return mqd_manager_init_cik(type, dev); + case CHIP_CARRIZO: + return mqd_manager_init_vi(type, dev); } - return mqd; + return NULL; } - -/* SDMA queues should be implemented here when the cp will supports them */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c new file mode 100644 index 000000000000..a318743cdcc2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -0,0 +1,448 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include <linux/printk.h> +#include <linux/slab.h> +#include "kfd_priv.h" +#include "kfd_mqd_manager.h" +#include "cik_regs.h" +#include "cik_structs.h" + +static inline struct cik_mqd *get_mqd(void *mqd) +{ + return (struct cik_mqd *)mqd; +} + +static int init_mqd(struct mqd_manager *mm, void **mqd, + struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, + struct queue_properties *q) +{ + uint64_t addr; + struct cik_mqd *m; + int retval; + + BUG_ON(!mm || !q || !mqd); + + pr_debug("kfd: In func %s\n", __func__); + + retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), + mqd_mem_obj); + + if (retval != 0) + return -ENOMEM; + + m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr; + addr = (*mqd_mem_obj)->gpu_addr; + + memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); + + m->header = 0xC0310800; + m->compute_pipelinestat_enable = 1; + m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; + + /* + * Make sure to use the last queue state saved on mqd when the cp + * reassigns the queue, so when queue is switched on/off (e.g over + * subscription or quantum timeout) the context will be consistent + */ + m->cp_hqd_persistent_state = + DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ; + + m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; + m->cp_mqd_base_addr_lo = lower_32_bits(addr); + m->cp_mqd_base_addr_hi = upper_32_bits(addr); + + m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE | IB_ATC_EN; + /* Although WinKFD writes this, I suspect it should not be necessary */ + m->cp_hqd_ib_control = IB_ATC_EN | DEFAULT_MIN_IB_AVAIL_SIZE; + + m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | + QUANTUM_DURATION(10); + + /* + * Pipe Priority + * Identifies the pipe relative priority when this queue is connected + * to the pipeline. The pipe priority is against the GFX pipe and HP3D. + * In KFD we are using a fixed pipe priority set to CS_MEDIUM. + * 0 = CS_LOW (typically below GFX) + * 1 = CS_MEDIUM (typically between HP3D and GFX + * 2 = CS_HIGH (typically above HP3D) + */ + m->cp_hqd_pipe_priority = 1; + m->cp_hqd_queue_priority = 15; + + *mqd = m; + if (gart_addr != NULL) + *gart_addr = addr; + retval = mm->update_mqd(mm, m, q); + + return retval; +} + +static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, + struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, + struct queue_properties *q) +{ + int retval; + struct cik_sdma_rlc_registers *m; + + BUG_ON(!mm || !mqd || !mqd_mem_obj); + + retval = kfd_gtt_sa_allocate(mm->dev, + sizeof(struct cik_sdma_rlc_registers), + mqd_mem_obj); + + if (retval != 0) + return -ENOMEM; + + m = (struct cik_sdma_rlc_registers *) (*mqd_mem_obj)->cpu_ptr; + + memset(m, 0, sizeof(struct cik_sdma_rlc_registers)); + + *mqd = m; + if (gart_addr != NULL) + *gart_addr = (*mqd_mem_obj)->gpu_addr; + + retval = mm->update_mqd(mm, m, q); + + return retval; +} + +static void uninit_mqd(struct mqd_manager *mm, void *mqd, + struct kfd_mem_obj *mqd_mem_obj) +{ + BUG_ON(!mm || !mqd); + kfd_gtt_sa_free(mm->dev, mqd_mem_obj); +} + +static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd, + struct kfd_mem_obj *mqd_mem_obj) +{ + BUG_ON(!mm || !mqd); + kfd_gtt_sa_free(mm->dev, mqd_mem_obj); +} + +static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, + uint32_t queue_id, uint32_t __user *wptr) +{ + return kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, wptr); +} + +static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, + uint32_t pipe_id, uint32_t queue_id, + uint32_t __user *wptr) +{ + return kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd); +} + +static int update_mqd(struct mqd_manager *mm, void *mqd, + struct queue_properties *q) +{ + struct cik_mqd *m; + + BUG_ON(!mm || !q || !mqd); + + pr_debug("kfd: In func %s\n", __func__); + + m = get_mqd(mqd); + m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | + DEFAULT_MIN_AVAIL_SIZE | PQ_ATC_EN; + + /* + * Calculating queue size which is log base 2 of actual queue size -1 + * dwords and another -1 for ffs + */ + m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) + - 1 - 1; + m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); + m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); + m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); + m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); + m->cp_hqd_pq_doorbell_control = DOORBELL_EN | + DOORBELL_OFFSET(q->doorbell_off); + + m->cp_hqd_vmid = q->vmid; + + if (q->format == KFD_QUEUE_FORMAT_AQL) { + m->cp_hqd_iq_rptr = AQL_ENABLE; + m->cp_hqd_pq_control |= NO_UPDATE_RPTR; + } + + m->cp_hqd_active = 0; + q->is_active = false; + if (q->queue_size > 0 && + q->queue_address != 0 && + q->queue_percent > 0) { + m->cp_hqd_active = 1; + q->is_active = true; + } + + return 0; +} + +static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, + struct queue_properties *q) +{ + struct cik_sdma_rlc_registers *m; + + BUG_ON(!mm || !mqd || !q); + + m = get_sdma_mqd(mqd); + m->sdma_rlc_rb_cntl = + SDMA_RB_SIZE((ffs(q->queue_size / sizeof(unsigned int)))) | + SDMA_RB_VMID(q->vmid) | + SDMA_RPTR_WRITEBACK_ENABLE | + SDMA_RPTR_WRITEBACK_TIMER(6); + + m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); + m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); + m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); + m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); + m->sdma_rlc_doorbell = SDMA_OFFSET(q->doorbell_off) | SDMA_DB_ENABLE; + m->sdma_rlc_virtual_addr = q->sdma_vm_addr; + + m->sdma_engine_id = q->sdma_engine_id; + m->sdma_queue_id = q->sdma_queue_id; + + q->is_active = false; + if (q->queue_size > 0 && + q->queue_address != 0 && + q->queue_percent > 0) { + m->sdma_rlc_rb_cntl |= SDMA_RB_ENABLE; + q->is_active = true; + } + + return 0; +} + +static int destroy_mqd(struct mqd_manager *mm, void *mqd, + enum kfd_preempt_type type, + unsigned int timeout, uint32_t pipe_id, + uint32_t queue_id) +{ + return kfd2kgd->hqd_destroy(mm->dev->kgd, type, timeout, + pipe_id, queue_id); +} + +/* + * preempt type here is ignored because there is only one way + * to preempt sdma queue + */ +static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, + enum kfd_preempt_type type, + unsigned int timeout, uint32_t pipe_id, + uint32_t queue_id) +{ + return kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); +} + +static bool is_occupied(struct mqd_manager *mm, void *mqd, + uint64_t queue_address, uint32_t pipe_id, + uint32_t queue_id) +{ + + return kfd2kgd->hqd_is_occupied(mm->dev->kgd, queue_address, + pipe_id, queue_id); + +} + +static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, + uint64_t queue_address, uint32_t pipe_id, + uint32_t queue_id) +{ + return kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); +} + +/* + * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation. + * The HIQ queue in Kaveri is using the same MQD structure as all the user mode + * queues but with different initial values. + */ + +static int init_mqd_hiq(struct mqd_manager *mm, void **mqd, + struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, + struct queue_properties *q) +{ + uint64_t addr; + struct cik_mqd *m; + int retval; + + BUG_ON(!mm || !q || !mqd || !mqd_mem_obj); + + pr_debug("kfd: In func %s\n", __func__); + + retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), + mqd_mem_obj); + + if (retval != 0) + return -ENOMEM; + + m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr; + addr = (*mqd_mem_obj)->gpu_addr; + + memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); + + m->header = 0xC0310800; + m->compute_pipelinestat_enable = 1; + m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; + + m->cp_hqd_persistent_state = DEFAULT_CP_HQD_PERSISTENT_STATE | + PRELOAD_REQ; + m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | + QUANTUM_DURATION(10); + + m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; + m->cp_mqd_base_addr_lo = lower_32_bits(addr); + m->cp_mqd_base_addr_hi = upper_32_bits(addr); + + m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE; + + /* + * Pipe Priority + * Identifies the pipe relative priority when this queue is connected + * to the pipeline. The pipe priority is against the GFX pipe and HP3D. + * In KFD we are using a fixed pipe priority set to CS_MEDIUM. + * 0 = CS_LOW (typically below GFX) + * 1 = CS_MEDIUM (typically between HP3D and GFX + * 2 = CS_HIGH (typically above HP3D) + */ + m->cp_hqd_pipe_priority = 1; + m->cp_hqd_queue_priority = 15; + + *mqd = m; + if (gart_addr) + *gart_addr = addr; + retval = mm->update_mqd(mm, m, q); + + return retval; +} + +static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, + struct queue_properties *q) +{ + struct cik_mqd *m; + + BUG_ON(!mm || !q || !mqd); + + pr_debug("kfd: In func %s\n", __func__); + + m = get_mqd(mqd); + m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | + DEFAULT_MIN_AVAIL_SIZE | + PRIV_STATE | + KMD_QUEUE; + + /* + * Calculating queue size which is log base 2 of actual queue + * size -1 dwords + */ + m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) + - 1 - 1; + m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); + m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); + m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); + m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); + m->cp_hqd_pq_doorbell_control = DOORBELL_EN | + DOORBELL_OFFSET(q->doorbell_off); + + m->cp_hqd_vmid = q->vmid; + + m->cp_hqd_active = 0; + q->is_active = false; + if (q->queue_size > 0 && + q->queue_address != 0 && + q->queue_percent > 0) { + m->cp_hqd_active = 1; + q->is_active = true; + } + + return 0; +} + +struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) +{ + struct cik_sdma_rlc_registers *m; + + BUG_ON(!mqd); + + m = (struct cik_sdma_rlc_registers *)mqd; + + return m; +} + +struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, + struct kfd_dev *dev) +{ + struct mqd_manager *mqd; + + BUG_ON(!dev); + BUG_ON(type >= KFD_MQD_TYPE_MAX); + + pr_debug("kfd: In func %s\n", __func__); + + mqd = kzalloc(sizeof(struct mqd_manager), GFP_KERNEL); + if (!mqd) + return NULL; + + mqd->dev = dev; + + switch (type) { + case KFD_MQD_TYPE_CP: + case KFD_MQD_TYPE_COMPUTE: + mqd->init_mqd = init_mqd; + mqd->uninit_mqd = uninit_mqd; + mqd->load_mqd = load_mqd; + mqd->update_mqd = update_mqd; + mqd->destroy_mqd = destroy_mqd; + mqd->is_occupied = is_occupied; + break; + case KFD_MQD_TYPE_HIQ: + mqd->init_mqd = init_mqd_hiq; + mqd->uninit_mqd = uninit_mqd; + mqd->load_mqd = load_mqd; + mqd->update_mqd = update_mqd_hiq; + mqd->destroy_mqd = destroy_mqd; + mqd->is_occupied = is_occupied; + break; + case KFD_MQD_TYPE_SDMA: + mqd->init_mqd = init_mqd_sdma; + mqd->uninit_mqd = uninit_mqd_sdma; + mqd->load_mqd = load_mqd_sdma; + mqd->update_mqd = update_mqd_sdma; + mqd->destroy_mqd = destroy_mqd_sdma; + mqd->is_occupied = is_occupied_sdma; + break; + default: + kfree(mqd); + return NULL; + } + + return mqd; +} + diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c new file mode 100644 index 000000000000..b3a7e3ba1e38 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include <linux/printk.h> +#include "kfd_priv.h" +#include "kfd_mqd_manager.h" + +struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, + struct kfd_dev *dev) +{ + pr_warn("amdkfd: VI MQD is not currently supported\n"); + return NULL; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index 3cda952ac2f8..e2533d875f43 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -348,7 +348,7 @@ int pm_send_set_resources(struct packet_manager *pm, pr_debug("kfd: In func %s\n", __func__); mutex_lock(&pm->lock); - pm->priv_queue->acquire_packet_buffer(pm->priv_queue, + pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue, sizeof(*packet) / sizeof(uint32_t), (unsigned int **)&packet); if (packet == NULL) { @@ -375,8 +375,7 @@ int pm_send_set_resources(struct packet_manager *pm, packet->queue_mask_lo = lower_32_bits(res->queue_mask); packet->queue_mask_hi = upper_32_bits(res->queue_mask); - pm->priv_queue->submit_packet(pm->priv_queue); - pm->priv_queue->sync_with_hw(pm->priv_queue, KFD_HIQ_TIMEOUT); + pm->priv_queue->ops.submit_packet(pm->priv_queue); mutex_unlock(&pm->lock); @@ -402,7 +401,7 @@ int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues) packet_size_dwords = sizeof(struct pm4_runlist) / sizeof(uint32_t); mutex_lock(&pm->lock); - retval = pm->priv_queue->acquire_packet_buffer(pm->priv_queue, + retval = pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue, packet_size_dwords, &rl_buffer); if (retval != 0) goto fail_acquire_packet_buffer; @@ -412,15 +411,14 @@ int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues) if (retval != 0) goto fail_create_runlist; - pm->priv_queue->submit_packet(pm->priv_queue); - pm->priv_queue->sync_with_hw(pm->priv_queue, KFD_HIQ_TIMEOUT); + pm->priv_queue->ops.submit_packet(pm->priv_queue); mutex_unlock(&pm->lock); return retval; fail_create_runlist: - pm->priv_queue->rollback_packet(pm->priv_queue); + pm->priv_queue->ops.rollback_packet(pm->priv_queue); fail_acquire_packet_buffer: mutex_unlock(&pm->lock); fail_create_runlist_ib: @@ -438,7 +436,7 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, BUG_ON(!pm || !fence_address); mutex_lock(&pm->lock); - retval = pm->priv_queue->acquire_packet_buffer( + retval = pm->priv_queue->ops.acquire_packet_buffer( pm->priv_queue, sizeof(struct pm4_query_status) / sizeof(uint32_t), (unsigned int **)&packet); @@ -459,8 +457,7 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, packet->data_hi = upper_32_bits((uint64_t)fence_value); packet->data_lo = lower_32_bits((uint64_t)fence_value); - pm->priv_queue->submit_packet(pm->priv_queue); - pm->priv_queue->sync_with_hw(pm->priv_queue, KFD_HIQ_TIMEOUT); + pm->priv_queue->ops.submit_packet(pm->priv_queue); mutex_unlock(&pm->lock); return 0; @@ -482,7 +479,7 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, BUG_ON(!pm); mutex_lock(&pm->lock); - retval = pm->priv_queue->acquire_packet_buffer( + retval = pm->priv_queue->ops.acquire_packet_buffer( pm->priv_queue, sizeof(struct pm4_unmap_queues) / sizeof(uint32_t), &buffer); @@ -537,8 +534,7 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, break; }; - pm->priv_queue->submit_packet(pm->priv_queue); - pm->priv_queue->sync_with_hw(pm->priv_queue, KFD_HIQ_TIMEOUT); + pm->priv_queue->ops.submit_packet(pm->priv_queue); mutex_unlock(&pm->lock); return 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c index 71699ad97d74..4c25ef504f79 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c @@ -32,7 +32,7 @@ int kfd_pasid_init(void) { pasid_limit = max_num_of_processes; - pasid_bitmap = kzalloc(BITS_TO_LONGS(pasid_limit), GFP_KERNEL); + pasid_bitmap = kcalloc(BITS_TO_LONGS(pasid_limit), sizeof(long), GFP_KERNEL); if (!pasid_bitmap) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index a79c21781d3b..1b35a9c87437 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -104,7 +104,13 @@ enum cache_policy { cache_policy_noncoherent }; +enum asic_family_type { + CHIP_KAVERI = 0, + CHIP_CARRIZO +}; + struct kfd_device_info { + unsigned int asic_family; unsigned int max_pasid_bits; size_t ih_ring_entry_size; uint8_t num_of_watch_points; @@ -151,22 +157,10 @@ struct kfd_dev { unsigned int gtt_sa_chunk_size; unsigned int gtt_sa_num_of_chunks; - void *interrupt_ring; - size_t interrupt_ring_size; - atomic_t interrupt_ring_rptr; - atomic_t interrupt_ring_wptr; - struct work_struct interrupt_work; - spinlock_t interrupt_lock; - /* QCM Device instance */ struct device_queue_manager *dqm; bool init_complete; - /* - * Interrupts of interest to KFD are copied - * from the HW ring into a SW ring. - */ - bool interrupts_active; }; /* KGD2KFD callbacks */ @@ -299,6 +293,11 @@ struct queue_properties { uint32_t sdma_engine_id; uint32_t sdma_queue_id; uint32_t sdma_vm_addr; + /* Relevant only for VI */ + uint64_t eop_ring_buffer_address; + uint32_t eop_ring_buffer_size; + uint64_t ctx_save_restore_area_address; + uint32_t ctx_save_restore_area_size; }; /** @@ -351,10 +350,10 @@ struct queue { * Please read the kfd_mqd_manager.h description. */ enum KFD_MQD_TYPE { - KFD_MQD_TYPE_CIK_COMPUTE = 0, /* for no cp scheduling */ - KFD_MQD_TYPE_CIK_HIQ, /* for hiq */ - KFD_MQD_TYPE_CIK_CP, /* for cp queues and diq */ - KFD_MQD_TYPE_CIK_SDMA, /* for sdma queues */ + KFD_MQD_TYPE_COMPUTE = 0, /* for no cp scheduling */ + KFD_MQD_TYPE_HIQ, /* for hiq */ + KFD_MQD_TYPE_CP, /* for cp queues and diq */ + KFD_MQD_TYPE_SDMA, /* for sdma queues */ KFD_MQD_TYPE_MAX }; @@ -479,6 +478,24 @@ struct kfd_process { bool is_32bit_user_mode; }; +/** + * Ioctl function type. + * + * \param filep pointer to file structure. + * \param p amdkfd process pointer. + * \param data pointer to arg that was copied from user. + */ +typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, + void *data); + +struct amdkfd_ioctl_desc { + unsigned int cmd; + int flags; + amdkfd_ioctl_t *func; + unsigned int cmd_drv; + const char *name; +}; + void kfd_process_create_wq(void); void kfd_process_destroy_wq(void); struct kfd_process *kfd_create_process(const struct task_struct *); @@ -537,10 +554,7 @@ struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev); struct kfd_dev *kfd_topology_enum_kfd_devices(uint8_t idx); /* Interrupts */ -int kfd_interrupt_init(struct kfd_dev *dev); -void kfd_interrupt_exit(struct kfd_dev *dev); void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); -bool enqueue_ih_ring_entry(struct kfd_dev *kfd, const void *ih_ring_entry); /* Power Management */ void kgd2kfd_suspend(struct kfd_dev *kfd); @@ -562,6 +576,10 @@ void print_queue(struct queue *q); struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type, struct kfd_dev *dev); +struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, + struct kfd_dev *dev); +struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, + struct kfd_dev *dev); struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev); void device_queue_manager_uninit(struct device_queue_manager *dqm); struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 948b1ca8e7a2..513eeb6e402a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -178,7 +178,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, if (list_empty(&pqm->queues)) { pdd->qpd.pqm = pqm; - dev->dqm->register_process(dev->dqm, &pdd->qpd); + dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); } pqn = kzalloc(sizeof(struct process_queue_node), GFP_KERNEL); @@ -204,7 +204,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, goto err_create_queue; pqn->q = q; pqn->kq = NULL; - retval = dev->dqm->create_queue(dev->dqm, q, &pdd->qpd, + retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, &q->properties.vmid); print_queue(q); break; @@ -217,7 +217,8 @@ int pqm_create_queue(struct process_queue_manager *pqm, kq->queue->properties.queue_id = *qid; pqn->kq = kq; pqn->q = NULL; - retval = dev->dqm->create_kernel_queue(dev->dqm, kq, &pdd->qpd); + retval = dev->dqm->ops.create_kernel_queue(dev->dqm, + kq, &pdd->qpd); break; default: BUG(); @@ -285,13 +286,13 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) if (pqn->kq) { /* destroy kernel queue (DIQ) */ dqm = pqn->kq->dev->dqm; - dqm->destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd); + dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd); kernel_queue_uninit(pqn->kq); } if (pqn->q) { dqm = pqn->q->device->dqm; - retval = dqm->destroy_queue(dqm, &pdd->qpd, pqn->q); + retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); if (retval != 0) return retval; @@ -303,7 +304,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) clear_bit(qid, pqm->queue_slot_bitmap); if (list_empty(&pqm->queues)) - dqm->unregister_process(dqm, &pdd->qpd); + dqm->ops.unregister_process(dqm, &pdd->qpd); return retval; } @@ -324,7 +325,8 @@ int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid, pqn->q->properties.queue_percent = p->queue_percent; pqn->q->properties.priority = p->priority; - retval = pqn->q->device->dqm->update_queue(pqn->q->device->dqm, pqn->q); + retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, + pqn->q); if (retval != 0) return retval; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 4886dde7d1fb..498399323a8c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -934,7 +934,7 @@ static int kfd_build_sysfs_node_tree(void) uint32_t i = 0; list_for_each_entry(dev, &topology_device_list, list) { - ret = kfd_build_sysfs_node_entry(dev, 0); + ret = kfd_build_sysfs_node_entry(dev, i); if (ret < 0) return ret; i++; diff --git a/drivers/gpu/drm/amd/include/cik_structs.h b/drivers/gpu/drm/amd/include/cik_structs.h new file mode 100644 index 000000000000..749eab94e335 --- /dev/null +++ b/drivers/gpu/drm/amd/include/cik_structs.h @@ -0,0 +1,293 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef CIK_STRUCTS_H_ +#define CIK_STRUCTS_H_ + +struct cik_mqd { + uint32_t header; + uint32_t compute_dispatch_initiator; + uint32_t compute_dim_x; + uint32_t compute_dim_y; + uint32_t compute_dim_z; + uint32_t compute_start_x; + uint32_t compute_start_y; + uint32_t compute_start_z; + uint32_t compute_num_thread_x; + uint32_t compute_num_thread_y; + uint32_t compute_num_thread_z; + uint32_t compute_pipelinestat_enable; + uint32_t compute_perfcount_enable; + uint32_t compute_pgm_lo; + uint32_t compute_pgm_hi; + uint32_t compute_tba_lo; + uint32_t compute_tba_hi; + uint32_t compute_tma_lo; + uint32_t compute_tma_hi; + uint32_t compute_pgm_rsrc1; + uint32_t compute_pgm_rsrc2; + uint32_t compute_vmid; + uint32_t compute_resource_limits; + uint32_t compute_static_thread_mgmt_se0; + uint32_t compute_static_thread_mgmt_se1; + uint32_t compute_tmpring_size; + uint32_t compute_static_thread_mgmt_se2; + uint32_t compute_static_thread_mgmt_se3; + uint32_t compute_restart_x; + uint32_t compute_restart_y; + uint32_t compute_restart_z; + uint32_t compute_thread_trace_enable; + uint32_t compute_misc_reserved; + uint32_t compute_user_data_0; + uint32_t compute_user_data_1; + uint32_t compute_user_data_2; + uint32_t compute_user_data_3; + uint32_t compute_user_data_4; + uint32_t compute_user_data_5; + uint32_t compute_user_data_6; + uint32_t compute_user_data_7; + uint32_t compute_user_data_8; + uint32_t compute_user_data_9; + uint32_t compute_user_data_10; + uint32_t compute_user_data_11; + uint32_t compute_user_data_12; + uint32_t compute_user_data_13; + uint32_t compute_user_data_14; + uint32_t compute_user_data_15; + uint32_t cp_compute_csinvoc_count_lo; + uint32_t cp_compute_csinvoc_count_hi; + uint32_t cp_mqd_base_addr_lo; + uint32_t cp_mqd_base_addr_hi; + uint32_t cp_hqd_active; + uint32_t cp_hqd_vmid; + uint32_t cp_hqd_persistent_state; + uint32_t cp_hqd_pipe_priority; + uint32_t cp_hqd_queue_priority; + uint32_t cp_hqd_quantum; + uint32_t cp_hqd_pq_base_lo; + uint32_t cp_hqd_pq_base_hi; + uint32_t cp_hqd_pq_rptr; + uint32_t cp_hqd_pq_rptr_report_addr_lo; + uint32_t cp_hqd_pq_rptr_report_addr_hi; + uint32_t cp_hqd_pq_wptr_poll_addr_lo; + uint32_t cp_hqd_pq_wptr_poll_addr_hi; + uint32_t cp_hqd_pq_doorbell_control; + uint32_t cp_hqd_pq_wptr; + uint32_t cp_hqd_pq_control; + uint32_t cp_hqd_ib_base_addr_lo; + uint32_t cp_hqd_ib_base_addr_hi; + uint32_t cp_hqd_ib_rptr; + uint32_t cp_hqd_ib_control; + uint32_t cp_hqd_iq_timer; + uint32_t cp_hqd_iq_rptr; + uint32_t cp_hqd_dequeue_request; + uint32_t cp_hqd_dma_offload; + uint32_t cp_hqd_sema_cmd; + uint32_t cp_hqd_msg_type; + uint32_t cp_hqd_atomic0_preop_lo; + uint32_t cp_hqd_atomic0_preop_hi; + uint32_t cp_hqd_atomic1_preop_lo; + uint32_t cp_hqd_atomic1_preop_hi; + uint32_t cp_hqd_hq_status0; + uint32_t cp_hqd_hq_control0; + uint32_t cp_mqd_control; + uint32_t cp_mqd_query_time_lo; + uint32_t cp_mqd_query_time_hi; + uint32_t cp_mqd_connect_start_time_lo; + uint32_t cp_mqd_connect_start_time_hi; + uint32_t cp_mqd_connect_end_time_lo; + uint32_t cp_mqd_connect_end_time_hi; + uint32_t cp_mqd_connect_end_wf_count; + uint32_t cp_mqd_connect_end_pq_rptr; + uint32_t cp_mqd_connect_end_pq_wptr; + uint32_t cp_mqd_connect_end_ib_rptr; + uint32_t reserved_96; + uint32_t reserved_97; + uint32_t reserved_98; + uint32_t reserved_99; + uint32_t iqtimer_pkt_header; + uint32_t iqtimer_pkt_dw0; + uint32_t iqtimer_pkt_dw1; + uint32_t iqtimer_pkt_dw2; + uint32_t iqtimer_pkt_dw3; + uint32_t iqtimer_pkt_dw4; + uint32_t iqtimer_pkt_dw5; + uint32_t iqtimer_pkt_dw6; + uint32_t reserved_108; + uint32_t reserved_109; + uint32_t reserved_110; + uint32_t reserved_111; + uint32_t queue_doorbell_id0; + uint32_t queue_doorbell_id1; + uint32_t queue_doorbell_id2; + uint32_t queue_doorbell_id3; + uint32_t queue_doorbell_id4; + uint32_t queue_doorbell_id5; + uint32_t queue_doorbell_id6; + uint32_t queue_doorbell_id7; + uint32_t queue_doorbell_id8; + uint32_t queue_doorbell_id9; + uint32_t queue_doorbell_id10; + uint32_t queue_doorbell_id11; + uint32_t queue_doorbell_id12; + uint32_t queue_doorbell_id13; + uint32_t queue_doorbell_id14; + uint32_t queue_doorbell_id15; +}; + +struct cik_sdma_rlc_registers { + uint32_t sdma_rlc_rb_cntl; + uint32_t sdma_rlc_rb_base; + uint32_t sdma_rlc_rb_base_hi; + uint32_t sdma_rlc_rb_rptr; + uint32_t sdma_rlc_rb_wptr; + uint32_t sdma_rlc_rb_wptr_poll_cntl; + uint32_t sdma_rlc_rb_wptr_poll_addr_hi; + uint32_t sdma_rlc_rb_wptr_poll_addr_lo; + uint32_t sdma_rlc_rb_rptr_addr_hi; + uint32_t sdma_rlc_rb_rptr_addr_lo; + uint32_t sdma_rlc_ib_cntl; + uint32_t sdma_rlc_ib_rptr; + uint32_t sdma_rlc_ib_offset; + uint32_t sdma_rlc_ib_base_lo; + uint32_t sdma_rlc_ib_base_hi; + uint32_t sdma_rlc_ib_size; + uint32_t sdma_rlc_skip_cntl; + uint32_t sdma_rlc_context_status; + uint32_t sdma_rlc_doorbell; + uint32_t sdma_rlc_virtual_addr; + uint32_t sdma_rlc_ape1_cntl; + uint32_t sdma_rlc_doorbell_log; + uint32_t reserved_22; + uint32_t reserved_23; + uint32_t reserved_24; + uint32_t reserved_25; + uint32_t reserved_26; + uint32_t reserved_27; + uint32_t reserved_28; + uint32_t reserved_29; + uint32_t reserved_30; + uint32_t reserved_31; + uint32_t reserved_32; + uint32_t reserved_33; + uint32_t reserved_34; + uint32_t reserved_35; + uint32_t reserved_36; + uint32_t reserved_37; + uint32_t reserved_38; + uint32_t reserved_39; + uint32_t reserved_40; + uint32_t reserved_41; + uint32_t reserved_42; + uint32_t reserved_43; + uint32_t reserved_44; + uint32_t reserved_45; + uint32_t reserved_46; + uint32_t reserved_47; + uint32_t reserved_48; + uint32_t reserved_49; + uint32_t reserved_50; + uint32_t reserved_51; + uint32_t reserved_52; + uint32_t reserved_53; + uint32_t reserved_54; + uint32_t reserved_55; + uint32_t reserved_56; + uint32_t reserved_57; + uint32_t reserved_58; + uint32_t reserved_59; + uint32_t reserved_60; + uint32_t reserved_61; + uint32_t reserved_62; + uint32_t reserved_63; + uint32_t reserved_64; + uint32_t reserved_65; + uint32_t reserved_66; + uint32_t reserved_67; + uint32_t reserved_68; + uint32_t reserved_69; + uint32_t reserved_70; + uint32_t reserved_71; + uint32_t reserved_72; + uint32_t reserved_73; + uint32_t reserved_74; + uint32_t reserved_75; + uint32_t reserved_76; + uint32_t reserved_77; + uint32_t reserved_78; + uint32_t reserved_79; + uint32_t reserved_80; + uint32_t reserved_81; + uint32_t reserved_82; + uint32_t reserved_83; + uint32_t reserved_84; + uint32_t reserved_85; + uint32_t reserved_86; + uint32_t reserved_87; + uint32_t reserved_88; + uint32_t reserved_89; + uint32_t reserved_90; + uint32_t reserved_91; + uint32_t reserved_92; + uint32_t reserved_93; + uint32_t reserved_94; + uint32_t reserved_95; + uint32_t reserved_96; + uint32_t reserved_97; + uint32_t reserved_98; + uint32_t reserved_99; + uint32_t reserved_100; + uint32_t reserved_101; + uint32_t reserved_102; + uint32_t reserved_103; + uint32_t reserved_104; + uint32_t reserved_105; + uint32_t reserved_106; + uint32_t reserved_107; + uint32_t reserved_108; + uint32_t reserved_109; + uint32_t reserved_110; + uint32_t reserved_111; + uint32_t reserved_112; + uint32_t reserved_113; + uint32_t reserved_114; + uint32_t reserved_115; + uint32_t reserved_116; + uint32_t reserved_117; + uint32_t reserved_118; + uint32_t reserved_119; + uint32_t reserved_120; + uint32_t reserved_121; + uint32_t reserved_122; + uint32_t reserved_123; + uint32_t reserved_124; + uint32_t reserved_125; + uint32_t reserved_126; + uint32_t reserved_127; + uint32_t sdma_engine_id; + uint32_t sdma_queue_id; +}; + + + +#endif /* CIK_STRUCTS_H_ */ diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index cd3878fe6f77..239bc16a1ddd 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -129,9 +129,6 @@ struct kgd2kfd_calls { * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp * scheduling mode. Only used for no cp scheduling mode. * - * @init_memory: Initializes memory apertures to fixed base/limit address - * and non cached memory types. - * * @init_pipeline: Initialized the compute pipelines. * * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp @@ -175,7 +172,6 @@ struct kfd2kgd_calls { int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid, unsigned int vmid); - int (*init_memory)(struct kgd_dev *kgd); int (*init_pipeline)(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); @@ -184,7 +180,7 @@ struct kfd2kgd_calls { int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd); - bool (*hqd_is_occupies)(struct kgd_dev *kgd, uint64_t queue_address, + bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); int (*hqd_destroy)(struct kgd_dev *kgd, uint32_t reset_type, diff --git a/drivers/gpu/drm/atmel-hlcdc/Kconfig b/drivers/gpu/drm/atmel-hlcdc/Kconfig new file mode 100644 index 000000000000..1a085625538a --- /dev/null +++ b/drivers/gpu/drm/atmel-hlcdc/Kconfig @@ -0,0 +1,11 @@ +config DRM_ATMEL_HLCDC + tristate "DRM Support for ATMEL HLCDC Display Controller" + depends on DRM && OF && COMMON_CLK && MFD_ATMEL_HLCDC + select DRM_GEM_CMA_HELPER + select DRM_KMS_HELPER + select DRM_KMS_FB_HELPER + select DRM_KMS_CMA_HELPER + select DRM_PANEL + help + Choose this option if you have an ATMEL SoC with an HLCDC display + controller (i.e. at91sam9n12, at91sam9x5 family or sama5d3 family). diff --git a/drivers/gpu/drm/atmel-hlcdc/Makefile b/drivers/gpu/drm/atmel-hlcdc/Makefile new file mode 100644 index 000000000000..10ae426e60bd --- /dev/null +++ b/drivers/gpu/drm/atmel-hlcdc/Makefile @@ -0,0 +1,7 @@ +atmel-hlcdc-dc-y := atmel_hlcdc_crtc.o \ + atmel_hlcdc_dc.o \ + atmel_hlcdc_layer.o \ + atmel_hlcdc_output.o \ + atmel_hlcdc_plane.o + +obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc-dc.o diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c new file mode 100644 index 000000000000..0409b907de5d --- /dev/null +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -0,0 +1,406 @@ +/* + * Copyright (C) 2014 Traphandler + * Copyright (C) 2014 Free Electrons + * + * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com> + * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/clk.h> +#include <linux/pm.h> +#include <linux/pm_runtime.h> + +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drmP.h> + +#include <video/videomode.h> + +#include "atmel_hlcdc_dc.h" + +/** + * Atmel HLCDC CRTC structure + * + * @base: base DRM CRTC structure + * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device + * @event: pointer to the current page flip event + * @id: CRTC id (returned by drm_crtc_index) + * @dpms: DPMS mode + */ +struct atmel_hlcdc_crtc { + struct drm_crtc base; + struct atmel_hlcdc_dc *dc; + struct drm_pending_vblank_event *event; + int id; + int dpms; +}; + +static inline struct atmel_hlcdc_crtc * +drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc) +{ + return container_of(crtc, struct atmel_hlcdc_crtc, base); +} + +static void atmel_hlcdc_crtc_dpms(struct drm_crtc *c, int mode) +{ + struct drm_device *dev = c->dev; + struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + struct regmap *regmap = crtc->dc->hlcdc->regmap; + unsigned int status; + + if (mode != DRM_MODE_DPMS_ON) + mode = DRM_MODE_DPMS_OFF; + + if (crtc->dpms == mode) + return; + + pm_runtime_get_sync(dev->dev); + + if (mode != DRM_MODE_DPMS_ON) { + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + (status & ATMEL_HLCDC_DISP)) + cpu_relax(); + + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + (status & ATMEL_HLCDC_SYNC)) + cpu_relax(); + + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + (status & ATMEL_HLCDC_PIXEL_CLK)) + cpu_relax(); + + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + + pm_runtime_allow(dev->dev); + } else { + pm_runtime_forbid(dev->dev); + + clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + !(status & ATMEL_HLCDC_PIXEL_CLK)) + cpu_relax(); + + + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + !(status & ATMEL_HLCDC_SYNC)) + cpu_relax(); + + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + !(status & ATMEL_HLCDC_DISP)) + cpu_relax(); + } + + pm_runtime_put_sync(dev->dev); + + crtc->dpms = mode; +} + +static int atmel_hlcdc_crtc_mode_set(struct drm_crtc *c, + struct drm_display_mode *mode, + struct drm_display_mode *adj, + int x, int y, + struct drm_framebuffer *old_fb) +{ + struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + struct regmap *regmap = crtc->dc->hlcdc->regmap; + struct drm_plane *plane = c->primary; + struct drm_framebuffer *fb; + unsigned long mode_rate; + struct videomode vm; + unsigned long prate; + unsigned int cfg; + int div; + + if (atmel_hlcdc_dc_mode_valid(crtc->dc, adj) != MODE_OK) + return -EINVAL; + + vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay; + vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end; + vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start; + vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay; + vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end; + vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start; + + regmap_write(regmap, ATMEL_HLCDC_CFG(1), + (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16)); + + regmap_write(regmap, ATMEL_HLCDC_CFG(2), + (vm.vfront_porch - 1) | (vm.vback_porch << 16)); + + regmap_write(regmap, ATMEL_HLCDC_CFG(3), + (vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16)); + + regmap_write(regmap, ATMEL_HLCDC_CFG(4), + (adj->crtc_hdisplay - 1) | + ((adj->crtc_vdisplay - 1) << 16)); + + cfg = ATMEL_HLCDC_CLKPOL; + + prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); + mode_rate = mode->crtc_clock * 1000; + if ((prate / 2) < mode_rate) { + prate *= 2; + cfg |= ATMEL_HLCDC_CLKSEL; + } + + div = DIV_ROUND_UP(prate, mode_rate); + if (div < 2) + div = 2; + + cfg |= ATMEL_HLCDC_CLKDIV(div); + + regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), + ATMEL_HLCDC_CLKSEL | ATMEL_HLCDC_CLKDIV_MASK | + ATMEL_HLCDC_CLKPOL, cfg); + + cfg = 0; + + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + cfg |= ATMEL_HLCDC_VSPOL; + + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + cfg |= ATMEL_HLCDC_HSPOL; + + regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5), + ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL | + ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE | + ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY | + ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO | + ATMEL_HLCDC_GUARDTIME_MASK, + cfg); + + fb = plane->fb; + plane->fb = old_fb; + + return atmel_hlcdc_plane_update_with_mode(plane, c, fb, 0, 0, + adj->hdisplay, adj->vdisplay, + x << 16, y << 16, + adj->hdisplay << 16, + adj->vdisplay << 16, + adj); +} + +int atmel_hlcdc_crtc_mode_set_base(struct drm_crtc *c, int x, int y, + struct drm_framebuffer *old_fb) +{ + struct drm_plane *plane = c->primary; + struct drm_framebuffer *fb = plane->fb; + struct drm_display_mode *mode = &c->hwmode; + + plane->fb = old_fb; + + return plane->funcs->update_plane(plane, c, fb, + 0, 0, + mode->hdisplay, + mode->vdisplay, + x << 16, y << 16, + mode->hdisplay << 16, + mode->vdisplay << 16); +} + +static void atmel_hlcdc_crtc_prepare(struct drm_crtc *crtc) +{ + atmel_hlcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); +} + +static void atmel_hlcdc_crtc_commit(struct drm_crtc *crtc) +{ + atmel_hlcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); +} + +static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static void atmel_hlcdc_crtc_disable(struct drm_crtc *crtc) +{ + struct drm_plane *plane; + + atmel_hlcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); + crtc->primary->funcs->disable_plane(crtc->primary); + + drm_for_each_legacy_plane(plane, &crtc->dev->mode_config.plane_list) { + if (plane->crtc != crtc) + continue; + + plane->funcs->disable_plane(crtc->primary); + plane->crtc = NULL; + } +} + +static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = { + .mode_fixup = atmel_hlcdc_crtc_mode_fixup, + .dpms = atmel_hlcdc_crtc_dpms, + .mode_set = atmel_hlcdc_crtc_mode_set, + .mode_set_base = atmel_hlcdc_crtc_mode_set_base, + .prepare = atmel_hlcdc_crtc_prepare, + .commit = atmel_hlcdc_crtc_commit, + .disable = atmel_hlcdc_crtc_disable, +}; + +static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c) +{ + struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + + drm_crtc_cleanup(c); + kfree(crtc); +} + +void atmel_hlcdc_crtc_cancel_page_flip(struct drm_crtc *c, + struct drm_file *file) +{ + struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + struct drm_pending_vblank_event *event; + struct drm_device *dev = c->dev; + unsigned long flags; + + spin_lock_irqsave(&dev->event_lock, flags); + event = crtc->event; + if (event && event->base.file_priv == file) { + event->base.destroy(&event->base); + drm_vblank_put(dev, crtc->id); + crtc->event = NULL; + } + spin_unlock_irqrestore(&dev->event_lock, flags); +} + +static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc) +{ + struct drm_device *dev = crtc->base.dev; + unsigned long flags; + + spin_lock_irqsave(&dev->event_lock, flags); + if (crtc->event) { + drm_send_vblank_event(dev, crtc->id, crtc->event); + drm_vblank_put(dev, crtc->id); + crtc->event = NULL; + } + spin_unlock_irqrestore(&dev->event_lock, flags); +} + +void atmel_hlcdc_crtc_irq(struct drm_crtc *c) +{ + drm_handle_vblank(c->dev, 0); + atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c)); +} + +static int atmel_hlcdc_crtc_page_flip(struct drm_crtc *c, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags) +{ + struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + struct atmel_hlcdc_plane_update_req req; + struct drm_plane *plane = c->primary; + struct drm_device *dev = c->dev; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&dev->event_lock, flags); + if (crtc->event) + ret = -EBUSY; + spin_unlock_irqrestore(&dev->event_lock, flags); + + if (ret) + return ret; + + memset(&req, 0, sizeof(req)); + req.crtc_x = 0; + req.crtc_y = 0; + req.crtc_h = c->mode.crtc_vdisplay; + req.crtc_w = c->mode.crtc_hdisplay; + req.src_x = c->x << 16; + req.src_y = c->y << 16; + req.src_w = req.crtc_w << 16; + req.src_h = req.crtc_h << 16; + req.fb = fb; + + ret = atmel_hlcdc_plane_prepare_update_req(plane, &req, &c->hwmode); + if (ret) + return ret; + + if (event) { + drm_vblank_get(c->dev, crtc->id); + spin_lock_irqsave(&dev->event_lock, flags); + crtc->event = event; + spin_unlock_irqrestore(&dev->event_lock, flags); + } + + ret = atmel_hlcdc_plane_apply_update_req(plane, &req); + if (ret) + crtc->event = NULL; + else + plane->fb = fb; + + return ret; +} + +static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = { + .page_flip = atmel_hlcdc_crtc_page_flip, + .set_config = drm_crtc_helper_set_config, + .destroy = atmel_hlcdc_crtc_destroy, +}; + +int atmel_hlcdc_crtc_create(struct drm_device *dev) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + struct atmel_hlcdc_planes *planes = dc->planes; + struct atmel_hlcdc_crtc *crtc; + int ret; + int i; + + crtc = kzalloc(sizeof(*crtc), GFP_KERNEL); + if (!crtc) + return -ENOMEM; + + crtc->dpms = DRM_MODE_DPMS_OFF; + crtc->dc = dc; + + ret = drm_crtc_init_with_planes(dev, &crtc->base, + &planes->primary->base, + planes->cursor ? &planes->cursor->base : NULL, + &atmel_hlcdc_crtc_funcs); + if (ret < 0) + goto fail; + + crtc->id = drm_crtc_index(&crtc->base); + + if (planes->cursor) + planes->cursor->base.possible_crtcs = 1 << crtc->id; + + for (i = 0; i < planes->noverlays; i++) + planes->overlays[i]->base.possible_crtcs = 1 << crtc->id; + + drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); + + dc->crtc = &crtc->base; + + return 0; + +fail: + atmel_hlcdc_crtc_destroy(&crtc->base); + return ret; +} + diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c new file mode 100644 index 000000000000..7320a6c6613f --- /dev/null +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -0,0 +1,579 @@ +/* + * Copyright (C) 2014 Traphandler + * Copyright (C) 2014 Free Electrons + * Copyright (C) 2014 Atmel + * + * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com> + * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/clk.h> +#include <linux/irq.h> +#include <linux/irqchip.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> + +#include "atmel_hlcdc_dc.h" + +#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8 + +static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { + { + .name = "base", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x40, + .id = 0, + .type = ATMEL_HLCDC_BASE_LAYER, + .nconfigs = 7, + .layout = { + .xstride = { 2 }, + .default_color = 3, + .general_config = 4, + .disc_pos = 5, + .disc_size = 6, + }, + }, + { + .name = "overlay1", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x140, + .id = 1, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .nconfigs = 10, + .layout = { + .pos = 2, + .size = 3, + .xstride = { 4 }, + .pstride = { 5 }, + .default_color = 6, + .chroma_key = 7, + .chroma_key_mask = 8, + .general_config = 9, + }, + }, + { + .name = "overlay2", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x240, + .id = 2, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .nconfigs = 10, + .layout = { + .pos = 2, + .size = 3, + .xstride = { 4 }, + .pstride = { 5 }, + .default_color = 6, + .chroma_key = 7, + .chroma_key_mask = 8, + .general_config = 9, + }, + }, + { + .name = "high-end-overlay", + .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats, + .regs_offset = 0x340, + .id = 3, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .nconfigs = 42, + .layout = { + .pos = 2, + .size = 3, + .memsize = 4, + .xstride = { 5, 7 }, + .pstride = { 6, 8 }, + .default_color = 9, + .chroma_key = 10, + .chroma_key_mask = 11, + .general_config = 12, + .csc = 14, + }, + }, + { + .name = "cursor", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x440, + .id = 4, + .type = ATMEL_HLCDC_CURSOR_LAYER, + .nconfigs = 10, + .max_width = 128, + .max_height = 128, + .layout = { + .pos = 2, + .size = 3, + .xstride = { 4 }, + .pstride = { 5 }, + .default_color = 6, + .chroma_key = 7, + .chroma_key_mask = 8, + .general_config = 9, + }, + }, +}; + +static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = { + .min_width = 0, + .min_height = 0, + .max_width = 2048, + .max_height = 2048, + .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers), + .layers = atmel_hlcdc_sama5d3_layers, +}; + +static const struct of_device_id atmel_hlcdc_of_match[] = { + { + .compatible = "atmel,sama5d3-hlcdc", + .data = &atmel_hlcdc_dc_sama5d3, + }, + { /* sentinel */ }, +}; + +int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc, + struct drm_display_mode *mode) +{ + int vfront_porch = mode->vsync_start - mode->vdisplay; + int vback_porch = mode->vtotal - mode->vsync_end; + int vsync_len = mode->vsync_end - mode->vsync_start; + int hfront_porch = mode->hsync_start - mode->hdisplay; + int hback_porch = mode->htotal - mode->hsync_end; + int hsync_len = mode->hsync_end - mode->hsync_start; + + if (hsync_len > 0x40 || hsync_len < 1) + return MODE_HSYNC; + + if (vsync_len > 0x40 || vsync_len < 1) + return MODE_VSYNC; + + if (hfront_porch > 0x200 || hfront_porch < 1 || + hback_porch > 0x200 || hback_porch < 1 || + mode->hdisplay < 1) + return MODE_H_ILLEGAL; + + if (vfront_porch > 0x40 || vfront_porch < 1 || + vback_porch > 0x40 || vback_porch < 0 || + mode->vdisplay < 1) + return MODE_V_ILLEGAL; + + return MODE_OK; +} + +static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data) +{ + struct drm_device *dev = data; + struct atmel_hlcdc_dc *dc = dev->dev_private; + unsigned long status; + unsigned int imr, isr; + int i; + + regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr); + regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr); + status = imr & isr; + if (!status) + return IRQ_NONE; + + if (status & ATMEL_HLCDC_SOF) + atmel_hlcdc_crtc_irq(dc->crtc); + + for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) { + struct atmel_hlcdc_layer *layer = dc->layers[i]; + + if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer) + continue; + + atmel_hlcdc_layer_irq(layer); + } + + return IRQ_HANDLED; +} + +static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev, + struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd) +{ + return drm_fb_cma_create(dev, file_priv, mode_cmd); +} + +static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + + if (dc->fbdev) { + drm_fbdev_cma_hotplug_event(dc->fbdev); + } else { + dc->fbdev = drm_fbdev_cma_init(dev, 24, + dev->mode_config.num_crtc, + dev->mode_config.num_connector); + if (IS_ERR(dc->fbdev)) + dc->fbdev = NULL; + } +} + +static const struct drm_mode_config_funcs mode_config_funcs = { + .fb_create = atmel_hlcdc_fb_create, + .output_poll_changed = atmel_hlcdc_fb_output_poll_changed, +}; + +static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + struct atmel_hlcdc_planes *planes; + int ret; + int i; + + drm_mode_config_init(dev); + + ret = atmel_hlcdc_create_outputs(dev); + if (ret) { + dev_err(dev->dev, "failed to create panel: %d\n", ret); + return ret; + } + + planes = atmel_hlcdc_create_planes(dev); + if (IS_ERR(planes)) { + dev_err(dev->dev, "failed to create planes\n"); + return PTR_ERR(planes); + } + + dc->planes = planes; + + dc->layers[planes->primary->layer.desc->id] = + &planes->primary->layer; + + if (planes->cursor) + dc->layers[planes->cursor->layer.desc->id] = + &planes->cursor->layer; + + for (i = 0; i < planes->noverlays; i++) + dc->layers[planes->overlays[i]->layer.desc->id] = + &planes->overlays[i]->layer; + + ret = atmel_hlcdc_crtc_create(dev); + if (ret) { + dev_err(dev->dev, "failed to create crtc\n"); + return ret; + } + + dev->mode_config.min_width = dc->desc->min_width; + dev->mode_config.min_height = dc->desc->min_height; + dev->mode_config.max_width = dc->desc->max_width; + dev->mode_config.max_height = dc->desc->max_height; + dev->mode_config.funcs = &mode_config_funcs; + + return 0; +} + +static int atmel_hlcdc_dc_load(struct drm_device *dev) +{ + struct platform_device *pdev = to_platform_device(dev->dev); + const struct of_device_id *match; + struct atmel_hlcdc_dc *dc; + int ret; + + match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node); + if (!match) { + dev_err(&pdev->dev, "invalid compatible string\n"); + return -ENODEV; + } + + if (!match->data) { + dev_err(&pdev->dev, "invalid hlcdc description\n"); + return -EINVAL; + } + + dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL); + if (!dc) + return -ENOMEM; + + dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0); + if (!dc->wq) + return -ENOMEM; + + dc->desc = match->data; + dc->hlcdc = dev_get_drvdata(dev->dev->parent); + dev->dev_private = dc; + + ret = clk_prepare_enable(dc->hlcdc->periph_clk); + if (ret) { + dev_err(dev->dev, "failed to enable periph_clk\n"); + goto err_destroy_wq; + } + + pm_runtime_enable(dev->dev); + + pm_runtime_put_sync(dev->dev); + + ret = atmel_hlcdc_dc_modeset_init(dev); + if (ret < 0) { + dev_err(dev->dev, "failed to initialize mode setting\n"); + goto err_periph_clk_disable; + } + + ret = drm_vblank_init(dev, 1); + if (ret < 0) { + dev_err(dev->dev, "failed to initialize vblank\n"); + goto err_periph_clk_disable; + } + + pm_runtime_get_sync(dev->dev); + ret = drm_irq_install(dev, dc->hlcdc->irq); + pm_runtime_put_sync(dev->dev); + if (ret < 0) { + dev_err(dev->dev, "failed to install IRQ handler\n"); + goto err_periph_clk_disable; + } + + platform_set_drvdata(pdev, dev); + + drm_kms_helper_poll_init(dev); + + /* force connectors detection */ + drm_helper_hpd_irq_event(dev); + + return 0; + +err_periph_clk_disable: + pm_runtime_disable(dev->dev); + clk_disable_unprepare(dc->hlcdc->periph_clk); + +err_destroy_wq: + destroy_workqueue(dc->wq); + + return ret; +} + +static void atmel_hlcdc_dc_unload(struct drm_device *dev) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + + if (dc->fbdev) + drm_fbdev_cma_fini(dc->fbdev); + flush_workqueue(dc->wq); + drm_kms_helper_poll_fini(dev); + drm_mode_config_cleanup(dev); + drm_vblank_cleanup(dev); + + pm_runtime_get_sync(dev->dev); + drm_irq_uninstall(dev); + pm_runtime_put_sync(dev->dev); + + dev->dev_private = NULL; + + pm_runtime_disable(dev->dev); + clk_disable_unprepare(dc->hlcdc->periph_clk); + destroy_workqueue(dc->wq); +} + +static int atmel_hlcdc_dc_connector_plug_all(struct drm_device *dev) +{ + struct drm_connector *connector, *failed; + int ret; + + mutex_lock(&dev->mode_config.mutex); + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + ret = drm_connector_register(connector); + if (ret) { + failed = connector; + goto err; + } + } + mutex_unlock(&dev->mode_config.mutex); + return 0; + +err: + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (failed == connector) + break; + + drm_connector_unregister(connector); + } + mutex_unlock(&dev->mode_config.mutex); + + return ret; +} + +static void atmel_hlcdc_dc_connector_unplug_all(struct drm_device *dev) +{ + mutex_lock(&dev->mode_config.mutex); + drm_connector_unplug_all(dev); + mutex_unlock(&dev->mode_config.mutex); +} + +static void atmel_hlcdc_dc_preclose(struct drm_device *dev, + struct drm_file *file) +{ + struct drm_crtc *crtc; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) + atmel_hlcdc_crtc_cancel_page_flip(crtc, file); +} + +static void atmel_hlcdc_dc_lastclose(struct drm_device *dev) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + + drm_fbdev_cma_restore_mode(dc->fbdev); +} + +static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + unsigned int cfg = 0; + int i; + + /* Enable interrupts on activated layers */ + for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) { + if (dc->layers[i]) + cfg |= ATMEL_HLCDC_LAYER_STATUS(i); + } + + regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg); + + return 0; +} + +static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + unsigned int isr; + + regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff); + regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr); +} + +static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev, int crtc) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + + /* Enable SOF (Start Of Frame) interrupt for vblank counting */ + regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF); + + return 0; +} + +static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev, int crtc) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + + regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF); +} + +static const struct file_operations fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .unlocked_ioctl = drm_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = drm_compat_ioctl, +#endif + .poll = drm_poll, + .read = drm_read, + .llseek = no_llseek, + .mmap = drm_gem_cma_mmap, +}; + +static struct drm_driver atmel_hlcdc_dc_driver = { + .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET, + .preclose = atmel_hlcdc_dc_preclose, + .lastclose = atmel_hlcdc_dc_lastclose, + .irq_handler = atmel_hlcdc_dc_irq_handler, + .irq_preinstall = atmel_hlcdc_dc_irq_uninstall, + .irq_postinstall = atmel_hlcdc_dc_irq_postinstall, + .irq_uninstall = atmel_hlcdc_dc_irq_uninstall, + .get_vblank_counter = drm_vblank_count, + .enable_vblank = atmel_hlcdc_dc_enable_vblank, + .disable_vblank = atmel_hlcdc_dc_disable_vblank, + .gem_free_object = drm_gem_cma_free_object, + .gem_vm_ops = &drm_gem_cma_vm_ops, + .dumb_create = drm_gem_cma_dumb_create, + .dumb_map_offset = drm_gem_cma_dumb_map_offset, + .dumb_destroy = drm_gem_dumb_destroy, + .fops = &fops, + .name = "atmel-hlcdc", + .desc = "Atmel HLCD Controller DRM", + .date = "20141504", + .major = 1, + .minor = 0, +}; + +static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev) +{ + struct drm_device *ddev; + int ret; + + ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev); + if (!ddev) + return -ENOMEM; + + ret = drm_dev_set_unique(ddev, dev_name(ddev->dev)); + if (ret) + goto err_unref; + + ret = atmel_hlcdc_dc_load(ddev); + if (ret) + goto err_unref; + + ret = drm_dev_register(ddev, 0); + if (ret) + goto err_unload; + + ret = atmel_hlcdc_dc_connector_plug_all(ddev); + if (ret) + goto err_unregister; + + return 0; + +err_unregister: + drm_dev_unregister(ddev); + +err_unload: + atmel_hlcdc_dc_unload(ddev); + +err_unref: + drm_dev_unref(ddev); + + return ret; +} + +static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev) +{ + struct drm_device *ddev = platform_get_drvdata(pdev); + + atmel_hlcdc_dc_connector_unplug_all(ddev); + drm_dev_unregister(ddev); + atmel_hlcdc_dc_unload(ddev); + drm_dev_unref(ddev); + + return 0; +} + +static const struct of_device_id atmel_hlcdc_dc_of_match[] = { + { .compatible = "atmel,hlcdc-display-controller" }, + { }, +}; + +static struct platform_driver atmel_hlcdc_dc_platform_driver = { + .probe = atmel_hlcdc_dc_drm_probe, + .remove = atmel_hlcdc_dc_drm_remove, + .driver = { + .name = "atmel-hlcdc-display-controller", + .of_match_table = atmel_hlcdc_dc_of_match, + }, +}; +module_platform_driver(atmel_hlcdc_dc_platform_driver); + +MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>"); +MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>"); +MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:atmel-hlcdc-dc"); diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h new file mode 100644 index 000000000000..7bc96af3397a --- /dev/null +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2014 Traphandler + * Copyright (C) 2014 Free Electrons + * Copyright (C) 2014 Atmel + * + * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com> + * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef DRM_ATMEL_HLCDC_H +#define DRM_ATMEL_HLCDC_H + +#include <linux/clk.h> +#include <linux/irqdomain.h> +#include <linux/pwm.h> + +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_panel.h> +#include <drm/drmP.h> + +#include "atmel_hlcdc_layer.h" + +#define ATMEL_HLCDC_MAX_LAYERS 5 + +/** + * Atmel HLCDC Display Controller description structure. + * + * This structure describe the HLCDC IP capabilities and depends on the + * HLCDC IP version (or Atmel SoC family). + * + * @min_width: minimum width supported by the Display Controller + * @min_height: minimum height supported by the Display Controller + * @max_width: maximum width supported by the Display Controller + * @max_height: maximum height supported by the Display Controller + * @layers: a layer description table describing available layers + * @nlayers: layer description table size + */ +struct atmel_hlcdc_dc_desc { + int min_width; + int min_height; + int max_width; + int max_height; + const struct atmel_hlcdc_layer_desc *layers; + int nlayers; +}; + +/** + * Atmel HLCDC Plane properties. + * + * This structure stores plane property definitions. + * + * @alpha: alpha blending (or transparency) property + * @rotation: rotation property + */ +struct atmel_hlcdc_plane_properties { + struct drm_property *alpha; + struct drm_property *rotation; +}; + +/** + * Atmel HLCDC Plane. + * + * @base: base DRM plane structure + * @layer: HLCDC layer structure + * @properties: pointer to the property definitions structure + * @rotation: current rotation status + */ +struct atmel_hlcdc_plane { + struct drm_plane base; + struct atmel_hlcdc_layer layer; + struct atmel_hlcdc_plane_properties *properties; + unsigned int rotation; +}; + +static inline struct atmel_hlcdc_plane * +drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p) +{ + return container_of(p, struct atmel_hlcdc_plane, base); +} + +static inline struct atmel_hlcdc_plane * +atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *l) +{ + return container_of(l, struct atmel_hlcdc_plane, layer); +} + +/** + * Atmel HLCDC Plane update request structure. + * + * @crtc_x: x position of the plane relative to the CRTC + * @crtc_y: y position of the plane relative to the CRTC + * @crtc_w: visible width of the plane + * @crtc_h: visible height of the plane + * @src_x: x buffer position + * @src_y: y buffer position + * @src_w: buffer width + * @src_h: buffer height + * @fb: framebuffer object object + * @bpp: bytes per pixel deduced from pixel_format + * @offsets: offsets to apply to the GEM buffers + * @xstride: value to add to the pixel pointer between each line + * @pstride: value to add to the pixel pointer between each pixel + * @nplanes: number of planes (deduced from pixel_format) + */ +struct atmel_hlcdc_plane_update_req { + int crtc_x; + int crtc_y; + unsigned int crtc_w; + unsigned int crtc_h; + uint32_t src_x; + uint32_t src_y; + uint32_t src_w; + uint32_t src_h; + struct drm_framebuffer *fb; + + /* These fields are private and should not be touched */ + int bpp[ATMEL_HLCDC_MAX_PLANES]; + unsigned int offsets[ATMEL_HLCDC_MAX_PLANES]; + int xstride[ATMEL_HLCDC_MAX_PLANES]; + int pstride[ATMEL_HLCDC_MAX_PLANES]; + int nplanes; +}; + +/** + * Atmel HLCDC Planes. + * + * This structure stores the instantiated HLCDC Planes and can be accessed by + * the HLCDC Display Controller or the HLCDC CRTC. + * + * @primary: primary plane + * @cursor: hardware cursor plane + * @overlays: overlay plane table + * @noverlays: number of overlay planes + */ +struct atmel_hlcdc_planes { + struct atmel_hlcdc_plane *primary; + struct atmel_hlcdc_plane *cursor; + struct atmel_hlcdc_plane **overlays; + int noverlays; +}; + +/** + * Atmel HLCDC Display Controller. + * + * @desc: HLCDC Display Controller description + * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device + * @fbdev: framebuffer device attached to the Display Controller + * @crtc: CRTC provided by the display controller + * @planes: instantiated planes + * @layers: active HLCDC layer + * @wq: display controller workqueue + */ +struct atmel_hlcdc_dc { + const struct atmel_hlcdc_dc_desc *desc; + struct atmel_hlcdc *hlcdc; + struct drm_fbdev_cma *fbdev; + struct drm_crtc *crtc; + struct atmel_hlcdc_planes *planes; + struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; + struct workqueue_struct *wq; +}; + +extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; +extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats; + +int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc, + struct drm_display_mode *mode); + +struct atmel_hlcdc_planes * +atmel_hlcdc_create_planes(struct drm_device *dev); + +int atmel_hlcdc_plane_prepare_update_req(struct drm_plane *p, + struct atmel_hlcdc_plane_update_req *req, + const struct drm_display_mode *mode); + +int atmel_hlcdc_plane_apply_update_req(struct drm_plane *p, + struct atmel_hlcdc_plane_update_req *req); + +int atmel_hlcdc_plane_update_with_mode(struct drm_plane *p, + struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int crtc_x, int crtc_y, + unsigned int crtc_w, + unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h, + const struct drm_display_mode *mode); + +void atmel_hlcdc_crtc_irq(struct drm_crtc *c); + +void atmel_hlcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, + struct drm_file *file); + +int atmel_hlcdc_crtc_create(struct drm_device *dev); + +int atmel_hlcdc_create_outputs(struct drm_device *dev); + +#endif /* DRM_ATMEL_HLCDC_H */ diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c new file mode 100644 index 000000000000..063d2a7b941f --- /dev/null +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c @@ -0,0 +1,667 @@ +/* + * Copyright (C) 2014 Free Electrons + * Copyright (C) 2014 Atmel + * + * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/dma-mapping.h> +#include <linux/interrupt.h> + +#include "atmel_hlcdc_dc.h" + +static void +atmel_hlcdc_layer_fb_flip_release(struct drm_flip_work *work, void *val) +{ + struct atmel_hlcdc_layer_fb_flip *flip = val; + + if (flip->fb) + drm_framebuffer_unreference(flip->fb); + kfree(flip); +} + +static void +atmel_hlcdc_layer_fb_flip_destroy(struct atmel_hlcdc_layer_fb_flip *flip) +{ + if (flip->fb) + drm_framebuffer_unreference(flip->fb); + kfree(flip->task); + kfree(flip); +} + +static void +atmel_hlcdc_layer_fb_flip_release_queue(struct atmel_hlcdc_layer *layer, + struct atmel_hlcdc_layer_fb_flip *flip) +{ + int i; + + if (!flip) + return; + + for (i = 0; i < layer->max_planes; i++) { + if (!flip->dscrs[i]) + break; + + flip->dscrs[i]->status = 0; + flip->dscrs[i] = NULL; + } + + drm_flip_work_queue_task(&layer->gc, flip->task); + drm_flip_work_commit(&layer->gc, layer->wq); +} + +static void atmel_hlcdc_layer_update_reset(struct atmel_hlcdc_layer *layer, + int id) +{ + struct atmel_hlcdc_layer_update *upd = &layer->update; + struct atmel_hlcdc_layer_update_slot *slot; + + if (id < 0 || id > 1) + return; + + slot = &upd->slots[id]; + bitmap_clear(slot->updated_configs, 0, layer->desc->nconfigs); + memset(slot->configs, 0, + sizeof(*slot->configs) * layer->desc->nconfigs); + + if (slot->fb_flip) { + atmel_hlcdc_layer_fb_flip_release_queue(layer, slot->fb_flip); + slot->fb_flip = NULL; + } +} + +static void atmel_hlcdc_layer_update_apply(struct atmel_hlcdc_layer *layer) +{ + struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma; + const struct atmel_hlcdc_layer_desc *desc = layer->desc; + struct atmel_hlcdc_layer_update *upd = &layer->update; + struct regmap *regmap = layer->hlcdc->regmap; + struct atmel_hlcdc_layer_update_slot *slot; + struct atmel_hlcdc_layer_fb_flip *fb_flip; + struct atmel_hlcdc_dma_channel_dscr *dscr; + unsigned int cfg; + u32 action = 0; + int i = 0; + + if (upd->pending < 0 || upd->pending > 1) + return; + + slot = &upd->slots[upd->pending]; + + for_each_set_bit(cfg, slot->updated_configs, layer->desc->nconfigs) { + regmap_write(regmap, + desc->regs_offset + + ATMEL_HLCDC_LAYER_CFG(layer, cfg), + slot->configs[cfg]); + action |= ATMEL_HLCDC_LAYER_UPDATE; + } + + fb_flip = slot->fb_flip; + + if (!fb_flip->fb) + goto apply; + + if (dma->status == ATMEL_HLCDC_LAYER_DISABLED) { + for (i = 0; i < fb_flip->ngems; i++) { + dscr = fb_flip->dscrs[i]; + dscr->ctrl = ATMEL_HLCDC_LAYER_DFETCH | + ATMEL_HLCDC_LAYER_DMA_IRQ | + ATMEL_HLCDC_LAYER_ADD_IRQ | + ATMEL_HLCDC_LAYER_DONE_IRQ; + + regmap_write(regmap, + desc->regs_offset + + ATMEL_HLCDC_LAYER_PLANE_ADDR(i), + dscr->addr); + regmap_write(regmap, + desc->regs_offset + + ATMEL_HLCDC_LAYER_PLANE_CTRL(i), + dscr->ctrl); + regmap_write(regmap, + desc->regs_offset + + ATMEL_HLCDC_LAYER_PLANE_NEXT(i), + dscr->next); + } + + action |= ATMEL_HLCDC_LAYER_DMA_CHAN; + dma->status = ATMEL_HLCDC_LAYER_ENABLED; + } else { + for (i = 0; i < fb_flip->ngems; i++) { + dscr = fb_flip->dscrs[i]; + dscr->ctrl = ATMEL_HLCDC_LAYER_DFETCH | + ATMEL_HLCDC_LAYER_DMA_IRQ | + ATMEL_HLCDC_LAYER_DSCR_IRQ | + ATMEL_HLCDC_LAYER_DONE_IRQ; + + regmap_write(regmap, + desc->regs_offset + + ATMEL_HLCDC_LAYER_PLANE_HEAD(i), + dscr->next); + } + + action |= ATMEL_HLCDC_LAYER_A2Q; + } + + /* Release unneeded descriptors */ + for (i = fb_flip->ngems; i < layer->max_planes; i++) { + fb_flip->dscrs[i]->status = 0; + fb_flip->dscrs[i] = NULL; + } + + dma->queue = fb_flip; + slot->fb_flip = NULL; + +apply: + if (action) + regmap_write(regmap, + desc->regs_offset + ATMEL_HLCDC_LAYER_CHER, + action); + + atmel_hlcdc_layer_update_reset(layer, upd->pending); + + upd->pending = -1; +} + +void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer) +{ + struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma; + const struct atmel_hlcdc_layer_desc *desc = layer->desc; + struct regmap *regmap = layer->hlcdc->regmap; + struct atmel_hlcdc_layer_fb_flip *flip; + unsigned long flags; + unsigned int isr, imr; + unsigned int status; + unsigned int plane_status; + u32 flip_status; + + int i; + + regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_IMR, &imr); + regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR, &isr); + status = imr & isr; + if (!status) + return; + + spin_lock_irqsave(&layer->lock, flags); + + flip = dma->queue ? dma->queue : dma->cur; + + if (!flip) { + spin_unlock_irqrestore(&layer->lock, flags); + return; + } + + /* + * Set LOADED and DONE flags: they'll be cleared if at least one + * memory plane is not LOADED or DONE. + */ + flip_status = ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED | + ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE; + for (i = 0; i < flip->ngems; i++) { + plane_status = (status >> (8 * i)); + + if (plane_status & + (ATMEL_HLCDC_LAYER_ADD_IRQ | + ATMEL_HLCDC_LAYER_DSCR_IRQ) & + ~flip->dscrs[i]->ctrl) { + flip->dscrs[i]->status |= + ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED; + flip->dscrs[i]->ctrl |= + ATMEL_HLCDC_LAYER_ADD_IRQ | + ATMEL_HLCDC_LAYER_DSCR_IRQ; + } + + if (plane_status & + ATMEL_HLCDC_LAYER_DONE_IRQ & + ~flip->dscrs[i]->ctrl) { + flip->dscrs[i]->status |= + ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE; + flip->dscrs[i]->ctrl |= + ATMEL_HLCDC_LAYER_DONE_IRQ; + } + + if (plane_status & ATMEL_HLCDC_LAYER_OVR_IRQ) + flip->dscrs[i]->status |= + ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN; + + /* + * Clear LOADED and DONE flags if the memory plane is either + * not LOADED or not DONE. + */ + if (!(flip->dscrs[i]->status & + ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED)) + flip_status &= ~ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED; + + if (!(flip->dscrs[i]->status & + ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE)) + flip_status &= ~ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE; + + /* + * An overrun on one memory plane impact the whole framebuffer + * transfer, hence we set the OVERRUN flag as soon as there's + * one memory plane reporting such an overrun. + */ + flip_status |= flip->dscrs[i]->status & + ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN; + } + + /* Get changed bits */ + flip_status ^= flip->status; + flip->status |= flip_status; + + if (flip_status & ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED) { + atmel_hlcdc_layer_fb_flip_release_queue(layer, dma->cur); + dma->cur = dma->queue; + dma->queue = NULL; + } + + if (flip_status & ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE) { + atmel_hlcdc_layer_fb_flip_release_queue(layer, dma->cur); + dma->cur = NULL; + } + + if (flip_status & ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN) { + regmap_write(regmap, + desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR, + ATMEL_HLCDC_LAYER_RST); + if (dma->queue) + atmel_hlcdc_layer_fb_flip_release_queue(layer, + dma->queue); + + if (dma->cur) + atmel_hlcdc_layer_fb_flip_release_queue(layer, + dma->cur); + + dma->cur = NULL; + dma->queue = NULL; + } + + if (!dma->queue) { + atmel_hlcdc_layer_update_apply(layer); + + if (!dma->cur) + dma->status = ATMEL_HLCDC_LAYER_DISABLED; + } + + spin_unlock_irqrestore(&layer->lock, flags); +} + +int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer) +{ + struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma; + struct atmel_hlcdc_layer_update *upd = &layer->update; + struct regmap *regmap = layer->hlcdc->regmap; + const struct atmel_hlcdc_layer_desc *desc = layer->desc; + unsigned long flags; + unsigned int isr; + + spin_lock_irqsave(&layer->lock, flags); + + /* Disable the layer */ + regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR, + ATMEL_HLCDC_LAYER_RST); + + /* Clear all pending interrupts */ + regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR, &isr); + + /* Discard current and queued framebuffer transfers. */ + if (dma->cur) { + atmel_hlcdc_layer_fb_flip_release_queue(layer, dma->cur); + dma->cur = NULL; + } + + if (dma->queue) { + atmel_hlcdc_layer_fb_flip_release_queue(layer, dma->queue); + dma->queue = NULL; + } + + /* + * Then discard the pending update request (if any) to prevent + * DMA irq handler from restarting the DMA channel after it has + * been disabled. + */ + if (upd->pending >= 0) { + atmel_hlcdc_layer_update_reset(layer, upd->pending); + upd->pending = -1; + } + + dma->status = ATMEL_HLCDC_LAYER_DISABLED; + + spin_unlock_irqrestore(&layer->lock, flags); + + return 0; +} + +int atmel_hlcdc_layer_update_start(struct atmel_hlcdc_layer *layer) +{ + struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma; + struct atmel_hlcdc_layer_update *upd = &layer->update; + struct regmap *regmap = layer->hlcdc->regmap; + struct atmel_hlcdc_layer_fb_flip *fb_flip; + struct atmel_hlcdc_layer_update_slot *slot; + unsigned long flags; + int i, j = 0; + + fb_flip = kzalloc(sizeof(*fb_flip), GFP_KERNEL); + if (!fb_flip) + return -ENOMEM; + + fb_flip->task = drm_flip_work_allocate_task(fb_flip, GFP_KERNEL); + if (!fb_flip->task) { + kfree(fb_flip); + return -ENOMEM; + } + + spin_lock_irqsave(&layer->lock, flags); + + upd->next = upd->pending ? 0 : 1; + + slot = &upd->slots[upd->next]; + + for (i = 0; i < layer->max_planes * 4; i++) { + if (!dma->dscrs[i].status) { + fb_flip->dscrs[j++] = &dma->dscrs[i]; + dma->dscrs[i].status = + ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED; + if (j == layer->max_planes) + break; + } + } + + if (j < layer->max_planes) { + for (i = 0; i < j; i++) + fb_flip->dscrs[i]->status = 0; + } + + if (j < layer->max_planes) { + spin_unlock_irqrestore(&layer->lock, flags); + atmel_hlcdc_layer_fb_flip_destroy(fb_flip); + return -EBUSY; + } + + slot->fb_flip = fb_flip; + + if (upd->pending >= 0) { + memcpy(slot->configs, + upd->slots[upd->pending].configs, + layer->desc->nconfigs * sizeof(u32)); + memcpy(slot->updated_configs, + upd->slots[upd->pending].updated_configs, + DIV_ROUND_UP(layer->desc->nconfigs, + BITS_PER_BYTE * sizeof(unsigned long)) * + sizeof(unsigned long)); + slot->fb_flip->fb = upd->slots[upd->pending].fb_flip->fb; + if (upd->slots[upd->pending].fb_flip->fb) { + slot->fb_flip->fb = + upd->slots[upd->pending].fb_flip->fb; + slot->fb_flip->ngems = + upd->slots[upd->pending].fb_flip->ngems; + drm_framebuffer_reference(slot->fb_flip->fb); + } + } else { + regmap_bulk_read(regmap, + layer->desc->regs_offset + + ATMEL_HLCDC_LAYER_CFG(layer, 0), + upd->slots[upd->next].configs, + layer->desc->nconfigs); + } + + spin_unlock_irqrestore(&layer->lock, flags); + + return 0; +} + +void atmel_hlcdc_layer_update_rollback(struct atmel_hlcdc_layer *layer) +{ + struct atmel_hlcdc_layer_update *upd = &layer->update; + + atmel_hlcdc_layer_update_reset(layer, upd->next); + upd->next = -1; +} + +void atmel_hlcdc_layer_update_set_fb(struct atmel_hlcdc_layer *layer, + struct drm_framebuffer *fb, + unsigned int *offsets) +{ + struct atmel_hlcdc_layer_update *upd = &layer->update; + struct atmel_hlcdc_layer_fb_flip *fb_flip; + struct atmel_hlcdc_layer_update_slot *slot; + struct atmel_hlcdc_dma_channel_dscr *dscr; + struct drm_framebuffer *old_fb; + int nplanes = 0; + int i; + + if (upd->next < 0 || upd->next > 1) + return; + + if (fb) + nplanes = drm_format_num_planes(fb->pixel_format); + + if (nplanes > layer->max_planes) + return; + + slot = &upd->slots[upd->next]; + + fb_flip = slot->fb_flip; + old_fb = slot->fb_flip->fb; + + for (i = 0; i < nplanes; i++) { + struct drm_gem_cma_object *gem; + + dscr = slot->fb_flip->dscrs[i]; + gem = drm_fb_cma_get_gem_obj(fb, i); + dscr->addr = gem->paddr + offsets[i]; + } + + fb_flip->ngems = nplanes; + fb_flip->fb = fb; + + if (fb) + drm_framebuffer_reference(fb); + + if (old_fb) + drm_framebuffer_unreference(old_fb); +} + +void atmel_hlcdc_layer_update_cfg(struct atmel_hlcdc_layer *layer, int cfg, + u32 mask, u32 val) +{ + struct atmel_hlcdc_layer_update *upd = &layer->update; + struct atmel_hlcdc_layer_update_slot *slot; + + if (upd->next < 0 || upd->next > 1) + return; + + if (cfg >= layer->desc->nconfigs) + return; + + slot = &upd->slots[upd->next]; + slot->configs[cfg] &= ~mask; + slot->configs[cfg] |= (val & mask); + set_bit(cfg, slot->updated_configs); +} + +void atmel_hlcdc_layer_update_commit(struct atmel_hlcdc_layer *layer) +{ + struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma; + struct atmel_hlcdc_layer_update *upd = &layer->update; + struct atmel_hlcdc_layer_update_slot *slot; + unsigned long flags; + + if (upd->next < 0 || upd->next > 1) + return; + + slot = &upd->slots[upd->next]; + + spin_lock_irqsave(&layer->lock, flags); + + /* + * Release pending update request and replace it by the new one. + */ + if (upd->pending >= 0) + atmel_hlcdc_layer_update_reset(layer, upd->pending); + + upd->pending = upd->next; + upd->next = -1; + + if (!dma->queue) + atmel_hlcdc_layer_update_apply(layer); + + spin_unlock_irqrestore(&layer->lock, flags); + + + upd->next = -1; +} + +static int atmel_hlcdc_layer_dma_init(struct drm_device *dev, + struct atmel_hlcdc_layer *layer) +{ + struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma; + dma_addr_t dma_addr; + int i; + + dma->dscrs = dma_alloc_coherent(dev->dev, + layer->max_planes * 4 * + sizeof(*dma->dscrs), + &dma_addr, GFP_KERNEL); + if (!dma->dscrs) + return -ENOMEM; + + for (i = 0; i < layer->max_planes * 4; i++) { + struct atmel_hlcdc_dma_channel_dscr *dscr = &dma->dscrs[i]; + + dscr->next = dma_addr + (i * sizeof(*dscr)); + } + + return 0; +} + +static void atmel_hlcdc_layer_dma_cleanup(struct drm_device *dev, + struct atmel_hlcdc_layer *layer) +{ + struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma; + int i; + + for (i = 0; i < layer->max_planes * 4; i++) { + struct atmel_hlcdc_dma_channel_dscr *dscr = &dma->dscrs[i]; + + dscr->status = 0; + } + + dma_free_coherent(dev->dev, layer->max_planes * 4 * + sizeof(*dma->dscrs), dma->dscrs, + dma->dscrs[0].next); +} + +static int atmel_hlcdc_layer_update_init(struct drm_device *dev, + struct atmel_hlcdc_layer *layer, + const struct atmel_hlcdc_layer_desc *desc) +{ + struct atmel_hlcdc_layer_update *upd = &layer->update; + int updated_size; + void *buffer; + int i; + + updated_size = DIV_ROUND_UP(desc->nconfigs, + BITS_PER_BYTE * + sizeof(unsigned long)); + + buffer = devm_kzalloc(dev->dev, + ((desc->nconfigs * sizeof(u32)) + + (updated_size * sizeof(unsigned long))) * 2, + GFP_KERNEL); + if (!buffer) + return -ENOMEM; + + for (i = 0; i < 2; i++) { + upd->slots[i].updated_configs = buffer; + buffer += updated_size * sizeof(unsigned long); + upd->slots[i].configs = buffer; + buffer += desc->nconfigs * sizeof(u32); + } + + upd->pending = -1; + upd->next = -1; + + return 0; +} + +int atmel_hlcdc_layer_init(struct drm_device *dev, + struct atmel_hlcdc_layer *layer, + const struct atmel_hlcdc_layer_desc *desc) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + struct regmap *regmap = dc->hlcdc->regmap; + unsigned int tmp; + int ret; + int i; + + layer->hlcdc = dc->hlcdc; + layer->wq = dc->wq; + layer->desc = desc; + + regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR, + ATMEL_HLCDC_LAYER_RST); + for (i = 0; i < desc->formats->nformats; i++) { + int nplanes = drm_format_num_planes(desc->formats->formats[i]); + + if (nplanes > layer->max_planes) + layer->max_planes = nplanes; + } + + spin_lock_init(&layer->lock); + drm_flip_work_init(&layer->gc, desc->name, + atmel_hlcdc_layer_fb_flip_release); + ret = atmel_hlcdc_layer_dma_init(dev, layer); + if (ret) + return ret; + + ret = atmel_hlcdc_layer_update_init(dev, layer, desc); + if (ret) + return ret; + + /* Flush Status Register */ + regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_IDR, + 0xffffffff); + regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR, + &tmp); + + tmp = 0; + for (i = 0; i < layer->max_planes; i++) + tmp |= (ATMEL_HLCDC_LAYER_DMA_IRQ | + ATMEL_HLCDC_LAYER_DSCR_IRQ | + ATMEL_HLCDC_LAYER_ADD_IRQ | + ATMEL_HLCDC_LAYER_DONE_IRQ | + ATMEL_HLCDC_LAYER_OVR_IRQ) << (8 * i); + + regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_IER, tmp); + + return 0; +} + +void atmel_hlcdc_layer_cleanup(struct drm_device *dev, + struct atmel_hlcdc_layer *layer) +{ + const struct atmel_hlcdc_layer_desc *desc = layer->desc; + struct regmap *regmap = layer->hlcdc->regmap; + + regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_IDR, + 0xffffffff); + regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR, + ATMEL_HLCDC_LAYER_RST); + + atmel_hlcdc_layer_dma_cleanup(dev, layer); + drm_flip_work_cleanup(&layer->gc); +} diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h new file mode 100644 index 000000000000..27e56c0862ec --- /dev/null +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2014 Free Electrons + * Copyright (C) 2014 Atmel + * + * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef DRM_ATMEL_HLCDC_LAYER_H +#define DRM_ATMEL_HLCDC_LAYER_H + +#include <linux/mfd/atmel-hlcdc.h> + +#include <drm/drm_crtc.h> +#include <drm/drm_flip_work.h> +#include <drm/drmP.h> + +#define ATMEL_HLCDC_LAYER_CHER 0x0 +#define ATMEL_HLCDC_LAYER_CHDR 0x4 +#define ATMEL_HLCDC_LAYER_CHSR 0x8 +#define ATMEL_HLCDC_LAYER_DMA_CHAN BIT(0) +#define ATMEL_HLCDC_LAYER_UPDATE BIT(1) +#define ATMEL_HLCDC_LAYER_A2Q BIT(2) +#define ATMEL_HLCDC_LAYER_RST BIT(8) + +#define ATMEL_HLCDC_LAYER_IER 0xc +#define ATMEL_HLCDC_LAYER_IDR 0x10 +#define ATMEL_HLCDC_LAYER_IMR 0x14 +#define ATMEL_HLCDC_LAYER_ISR 0x18 +#define ATMEL_HLCDC_LAYER_DFETCH BIT(0) +#define ATMEL_HLCDC_LAYER_LFETCH BIT(1) +#define ATMEL_HLCDC_LAYER_DMA_IRQ BIT(2) +#define ATMEL_HLCDC_LAYER_DSCR_IRQ BIT(3) +#define ATMEL_HLCDC_LAYER_ADD_IRQ BIT(4) +#define ATMEL_HLCDC_LAYER_DONE_IRQ BIT(5) +#define ATMEL_HLCDC_LAYER_OVR_IRQ BIT(6) + +#define ATMEL_HLCDC_LAYER_PLANE_HEAD(n) (((n) * 0x10) + 0x1c) +#define ATMEL_HLCDC_LAYER_PLANE_ADDR(n) (((n) * 0x10) + 0x20) +#define ATMEL_HLCDC_LAYER_PLANE_CTRL(n) (((n) * 0x10) + 0x24) +#define ATMEL_HLCDC_LAYER_PLANE_NEXT(n) (((n) * 0x10) + 0x28) +#define ATMEL_HLCDC_LAYER_CFG(p, c) (((c) * 4) + ((p)->max_planes * 0x10) + 0x1c) + +#define ATMEL_HLCDC_LAYER_DMA_CFG_ID 0 +#define ATMEL_HLCDC_LAYER_DMA_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, ATMEL_HLCDC_LAYER_DMA_CFG_ID) +#define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0) +#define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4) +#define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4) +#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4) +#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4) +#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4) +#define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8) +#define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12) +#define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13) + +#define ATMEL_HLCDC_LAYER_FORMAT_CFG_ID 1 +#define ATMEL_HLCDC_LAYER_FORMAT_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, ATMEL_HLCDC_LAYER_FORMAT_CFG_ID) +#define ATMEL_HLCDC_LAYER_RGB (0 << 0) +#define ATMEL_HLCDC_LAYER_CLUT (1 << 0) +#define ATMEL_HLCDC_LAYER_YUV (2 << 0) +#define ATMEL_HLCDC_RGB_MODE(m) (((m) & 0xf) << 4) +#define ATMEL_HLCDC_CLUT_MODE(m) (((m) & 0x3) << 8) +#define ATMEL_HLCDC_YUV_MODE(m) (((m) & 0xf) << 12) +#define ATMEL_HLCDC_YUV422ROT BIT(16) +#define ATMEL_HLCDC_YUV422SWP BIT(17) +#define ATMEL_HLCDC_DSCALEOPT BIT(20) + +#define ATMEL_HLCDC_XRGB4444_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(0)) +#define ATMEL_HLCDC_ARGB4444_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(1)) +#define ATMEL_HLCDC_RGBA4444_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(2)) +#define ATMEL_HLCDC_RGB565_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(3)) +#define ATMEL_HLCDC_ARGB1555_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(4)) +#define ATMEL_HLCDC_XRGB8888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(9)) +#define ATMEL_HLCDC_RGB888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(10)) +#define ATMEL_HLCDC_ARGB8888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(12)) +#define ATMEL_HLCDC_RGBA8888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(13)) + +#define ATMEL_HLCDC_AYUV_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(0)) +#define ATMEL_HLCDC_YUYV_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(1)) +#define ATMEL_HLCDC_UYVY_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(2)) +#define ATMEL_HLCDC_YVYU_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(3)) +#define ATMEL_HLCDC_VYUY_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(4)) +#define ATMEL_HLCDC_NV61_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(5)) +#define ATMEL_HLCDC_YUV422_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(6)) +#define ATMEL_HLCDC_NV21_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(7)) +#define ATMEL_HLCDC_YUV420_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(8)) + +#define ATMEL_HLCDC_LAYER_POS_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.pos) +#define ATMEL_HLCDC_LAYER_SIZE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.size) +#define ATMEL_HLCDC_LAYER_MEMSIZE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.memsize) +#define ATMEL_HLCDC_LAYER_XSTRIDE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.xstride) +#define ATMEL_HLCDC_LAYER_PSTRIDE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.pstride) +#define ATMEL_HLCDC_LAYER_DFLTCOLOR_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.default_color) +#define ATMEL_HLCDC_LAYER_CRKEY_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.chroma_key) +#define ATMEL_HLCDC_LAYER_CRKEY_MASK_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.chroma_key_mask) + +#define ATMEL_HLCDC_LAYER_GENERAL_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.general_config) +#define ATMEL_HLCDC_LAYER_CRKEY BIT(0) +#define ATMEL_HLCDC_LAYER_INV BIT(1) +#define ATMEL_HLCDC_LAYER_ITER2BL BIT(2) +#define ATMEL_HLCDC_LAYER_ITER BIT(3) +#define ATMEL_HLCDC_LAYER_REVALPHA BIT(4) +#define ATMEL_HLCDC_LAYER_GAEN BIT(5) +#define ATMEL_HLCDC_LAYER_LAEN BIT(6) +#define ATMEL_HLCDC_LAYER_OVR BIT(7) +#define ATMEL_HLCDC_LAYER_DMA BIT(8) +#define ATMEL_HLCDC_LAYER_REP BIT(9) +#define ATMEL_HLCDC_LAYER_DSTKEY BIT(10) +#define ATMEL_HLCDC_LAYER_DISCEN BIT(11) +#define ATMEL_HLCDC_LAYER_GA_SHIFT 16 +#define ATMEL_HLCDC_LAYER_GA_MASK GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT) + +#define ATMEL_HLCDC_LAYER_CSC_CFG(p, o) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.csc + o) + +#define ATMEL_HLCDC_LAYER_DISC_POS_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.disc_pos) + +#define ATMEL_HLCDC_LAYER_DISC_SIZE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.disc_size) + +#define ATMEL_HLCDC_MAX_PLANES 3 + +#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0) +#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1) +#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2) +#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3) + +/** + * Atmel HLCDC Layer registers layout structure + * + * Each HLCDC layer has its own register organization and a given register + * can be placed differently on 2 different layers depending on its + * capabilities. + * This structure stores common registers layout for a given layer and is + * used by HLCDC layer code to choose the appropriate register to write to + * or to read from. + * + * For all fields, a value of zero means "unsupported". + * + * See Atmel's datasheet for a detailled description of these registers. + * + * @xstride: xstride registers + * @pstride: pstride registers + * @pos: position register + * @size: displayed size register + * @memsize: memory size register + * @default_color: default color register + * @chroma_key: chroma key register + * @chroma_key_mask: chroma key mask register + * @general_config: general layer config register + * @disc_pos: discard area position register + * @disc_size: discard area size register + * @csc: color space conversion register + */ +struct atmel_hlcdc_layer_cfg_layout { + int xstride[ATMEL_HLCDC_MAX_PLANES]; + int pstride[ATMEL_HLCDC_MAX_PLANES]; + int pos; + int size; + int memsize; + int default_color; + int chroma_key; + int chroma_key_mask; + int general_config; + int disc_pos; + int disc_size; + int csc; +}; + +/** + * Atmel HLCDC framebuffer flip structure + * + * This structure is allocated when someone asked for a layer update (most + * likely a DRM plane update, either primary, overlay or cursor plane) and + * released when the layer do not need to reference the framebuffer object + * anymore (i.e. the layer was disabled or updated). + * + * @dscrs: DMA descriptors + * @fb: the referenced framebuffer object + * @ngems: number of GEM objects referenced by the fb element + * @status: fb flip operation status + */ +struct atmel_hlcdc_layer_fb_flip { + struct atmel_hlcdc_dma_channel_dscr *dscrs[ATMEL_HLCDC_MAX_PLANES]; + struct drm_flip_task *task; + struct drm_framebuffer *fb; + int ngems; + u32 status; +}; + +/** + * Atmel HLCDC DMA descriptor structure + * + * This structure is used by the HLCDC DMA engine to schedule a DMA transfer. + * + * The structure fields must remain in this specific order, because they're + * used by the HLCDC DMA engine, which expect them in this order. + * HLCDC DMA descriptors must be aligned on 64 bits. + * + * @addr: buffer DMA address + * @ctrl: DMA transfer options + * @next: next DMA descriptor to fetch + * @gem_flip: the attached gem_flip operation + */ +struct atmel_hlcdc_dma_channel_dscr { + dma_addr_t addr; + u32 ctrl; + dma_addr_t next; + u32 status; +} __aligned(sizeof(u64)); + +/** + * Atmel HLCDC layer types + */ +enum atmel_hlcdc_layer_type { + ATMEL_HLCDC_BASE_LAYER, + ATMEL_HLCDC_OVERLAY_LAYER, + ATMEL_HLCDC_CURSOR_LAYER, + ATMEL_HLCDC_PP_LAYER, +}; + +/** + * Atmel HLCDC Supported formats structure + * + * This structure list all the formats supported by a given layer. + * + * @nformats: number of supported formats + * @formats: supported formats + */ +struct atmel_hlcdc_formats { + int nformats; + uint32_t *formats; +}; + +/** + * Atmel HLCDC Layer description structure + * + * This structure describe the capabilities provided by a given layer. + * + * @name: layer name + * @type: layer type + * @id: layer id + * @regs_offset: offset of the layer registers from the HLCDC registers base + * @nconfigs: number of config registers provided by this layer + * @formats: supported formats + * @layout: config registers layout + * @max_width: maximum width supported by this layer (0 means unlimited) + * @max_height: maximum height supported by this layer (0 means unlimited) + */ +struct atmel_hlcdc_layer_desc { + const char *name; + enum atmel_hlcdc_layer_type type; + int id; + int regs_offset; + int nconfigs; + struct atmel_hlcdc_formats *formats; + struct atmel_hlcdc_layer_cfg_layout layout; + int max_width; + int max_height; +}; + +/** + * Atmel HLCDC Layer Update Slot structure + * + * This structure stores layer update requests to be applied on next frame. + * This is the base structure behind the atomic layer update infrastructure. + * + * Atomic layer update provides a way to update all layer's parameters + * simultaneously. This is needed to avoid incompatible sequential updates + * like this one: + * 1) update layer format from RGB888 (1 plane/buffer) to YUV422 + * (2 planes/buffers) + * 2) the format update is applied but the DMA channel for the second + * plane/buffer is not enabled + * 3) enable the DMA channel for the second plane + * + * @fb_flip: fb_flip object + * @updated_configs: bitmask used to record modified configs + * @configs: new config values + */ +struct atmel_hlcdc_layer_update_slot { + struct atmel_hlcdc_layer_fb_flip *fb_flip; + unsigned long *updated_configs; + u32 *configs; +}; + +/** + * Atmel HLCDC Layer Update structure + * + * This structure provides a way to queue layer update requests. + * + * At a given time there is at most: + * - one pending update request, which means the update request has been + * committed (or validated) and is waiting for the DMA channel(s) to be + * available + * - one request being prepared, which means someone started a layer update + * but has not committed it yet. There cannot be more than one started + * request, because the update lock is taken when starting a layer update + * and release when committing or rolling back the request. + * + * @slots: update slots. One is used for pending request and the other one + * for started update request + * @pending: the pending slot index or -1 if no request is pending + * @next: the started update slot index or -1 no update has been started + */ +struct atmel_hlcdc_layer_update { + struct atmel_hlcdc_layer_update_slot slots[2]; + int pending; + int next; +}; + +enum atmel_hlcdc_layer_dma_channel_status { + ATMEL_HLCDC_LAYER_DISABLED, + ATMEL_HLCDC_LAYER_ENABLED, + ATMEL_HLCDC_LAYER_DISABLING, +}; + +/** + * Atmel HLCDC Layer DMA channel structure + * + * This structure stores information on the DMA channel associated to a + * given layer. + * + * @status: DMA channel status + * @cur: current framebuffer + * @queue: next framebuffer + * @dscrs: allocated DMA descriptors + */ +struct atmel_hlcdc_layer_dma_channel { + enum atmel_hlcdc_layer_dma_channel_status status; + struct atmel_hlcdc_layer_fb_flip *cur; + struct atmel_hlcdc_layer_fb_flip *queue; + struct atmel_hlcdc_dma_channel_dscr *dscrs; +}; + +/** + * Atmel HLCDC Layer structure + * + * This structure stores information on the layer instance. + * + * @desc: layer description + * @max_planes: maximum planes/buffers that can be associated with this layer. + * This depends on the supported formats. + * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device + * @dma: dma channel + * @gc: fb flip garbage collector + * @update: update handler + * @lock: layer lock + */ +struct atmel_hlcdc_layer { + const struct atmel_hlcdc_layer_desc *desc; + int max_planes; + struct atmel_hlcdc *hlcdc; + struct workqueue_struct *wq; + struct drm_flip_work gc; + struct atmel_hlcdc_layer_dma_channel dma; + struct atmel_hlcdc_layer_update update; + spinlock_t lock; +}; + +void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer); + +int atmel_hlcdc_layer_init(struct drm_device *dev, + struct atmel_hlcdc_layer *layer, + const struct atmel_hlcdc_layer_desc *desc); + +void atmel_hlcdc_layer_cleanup(struct drm_device *dev, + struct atmel_hlcdc_layer *layer); + +int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer); + +int atmel_hlcdc_layer_update_start(struct atmel_hlcdc_layer *layer); + +void atmel_hlcdc_layer_update_cfg(struct atmel_hlcdc_layer *layer, int cfg, + u32 mask, u32 val); + +void atmel_hlcdc_layer_update_set_fb(struct atmel_hlcdc_layer *layer, + struct drm_framebuffer *fb, + unsigned int *offsets); + +void atmel_hlcdc_layer_update_set_finished(struct atmel_hlcdc_layer *layer, + void (*finished)(void *data), + void *finished_data); + +void atmel_hlcdc_layer_update_rollback(struct atmel_hlcdc_layer *layer); + +void atmel_hlcdc_layer_update_commit(struct atmel_hlcdc_layer *layer); + +#endif /* DRM_ATMEL_HLCDC_LAYER_H */ diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c new file mode 100644 index 000000000000..c402192362c5 --- /dev/null +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2014 Traphandler + * Copyright (C) 2014 Free Electrons + * Copyright (C) 2014 Atmel + * + * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com> + * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/of_graph.h> + +#include <drm/drmP.h> +#include <drm/drm_panel.h> + +#include "atmel_hlcdc_dc.h" + +/** + * Atmel HLCDC RGB output mode + */ +enum atmel_hlcdc_connector_rgb_mode { + ATMEL_HLCDC_CONNECTOR_RGB444, + ATMEL_HLCDC_CONNECTOR_RGB565, + ATMEL_HLCDC_CONNECTOR_RGB666, + ATMEL_HLCDC_CONNECTOR_RGB888, +}; + +/** + * Atmel HLCDC RGB connector structure + * + * This structure stores RGB slave device information. + * + * @connector: DRM connector + * @encoder: DRM encoder + * @dc: pointer to the atmel_hlcdc_dc structure + * @dpms: current DPMS mode + */ +struct atmel_hlcdc_rgb_output { + struct drm_connector connector; + struct drm_encoder encoder; + struct atmel_hlcdc_dc *dc; + int dpms; +}; + +static inline struct atmel_hlcdc_rgb_output * +drm_connector_to_atmel_hlcdc_rgb_output(struct drm_connector *connector) +{ + return container_of(connector, struct atmel_hlcdc_rgb_output, + connector); +} + +static inline struct atmel_hlcdc_rgb_output * +drm_encoder_to_atmel_hlcdc_rgb_output(struct drm_encoder *encoder) +{ + return container_of(encoder, struct atmel_hlcdc_rgb_output, encoder); +} + +/** + * Atmel HLCDC Panel device structure + * + * This structure is specialization of the slave device structure to + * interface with drm panels. + * + * @base: base slave device fields + * @panel: drm panel attached to this slave device + */ +struct atmel_hlcdc_panel { + struct atmel_hlcdc_rgb_output base; + struct drm_panel *panel; +}; + +static inline struct atmel_hlcdc_panel * +atmel_hlcdc_rgb_output_to_panel(struct atmel_hlcdc_rgb_output *output) +{ + return container_of(output, struct atmel_hlcdc_panel, base); +} + +static void atmel_hlcdc_panel_encoder_dpms(struct drm_encoder *encoder, + int mode) +{ + struct atmel_hlcdc_rgb_output *rgb = + drm_encoder_to_atmel_hlcdc_rgb_output(encoder); + struct atmel_hlcdc_panel *panel = atmel_hlcdc_rgb_output_to_panel(rgb); + + if (mode != DRM_MODE_DPMS_ON) + mode = DRM_MODE_DPMS_OFF; + + if (mode == rgb->dpms) + return; + + if (mode != DRM_MODE_DPMS_ON) + drm_panel_disable(panel->panel); + else + drm_panel_enable(panel->panel); + + rgb->dpms = mode; +} + +static bool +atmel_hlcdc_panel_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted) +{ + return true; +} + +static void atmel_hlcdc_panel_encoder_prepare(struct drm_encoder *encoder) +{ + atmel_hlcdc_panel_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); +} + +static void atmel_hlcdc_panel_encoder_commit(struct drm_encoder *encoder) +{ + atmel_hlcdc_panel_encoder_dpms(encoder, DRM_MODE_DPMS_ON); +} + +static void +atmel_hlcdc_rgb_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted) +{ + struct atmel_hlcdc_rgb_output *rgb = + drm_encoder_to_atmel_hlcdc_rgb_output(encoder); + struct drm_display_info *info = &rgb->connector.display_info; + unsigned int cfg; + + cfg = 0; + + if (info->num_bus_formats) { + switch (info->bus_formats[0]) { + case MEDIA_BUS_FMT_RGB666_1X18: + cfg |= ATMEL_HLCDC_CONNECTOR_RGB666 << 8; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + cfg |= ATMEL_HLCDC_CONNECTOR_RGB888 << 8; + break; + default: + break; + } + } + + regmap_update_bits(rgb->dc->hlcdc->regmap, ATMEL_HLCDC_CFG(5), + ATMEL_HLCDC_MODE_MASK, + cfg); +} + +static struct drm_encoder_helper_funcs atmel_hlcdc_panel_encoder_helper_funcs = { + .dpms = atmel_hlcdc_panel_encoder_dpms, + .mode_fixup = atmel_hlcdc_panel_encoder_mode_fixup, + .prepare = atmel_hlcdc_panel_encoder_prepare, + .commit = atmel_hlcdc_panel_encoder_commit, + .mode_set = atmel_hlcdc_rgb_encoder_mode_set, +}; + +static void atmel_hlcdc_rgb_encoder_destroy(struct drm_encoder *encoder) +{ + drm_encoder_cleanup(encoder); + memset(encoder, 0, sizeof(*encoder)); +} + +static const struct drm_encoder_funcs atmel_hlcdc_panel_encoder_funcs = { + .destroy = atmel_hlcdc_rgb_encoder_destroy, +}; + +static int atmel_hlcdc_panel_get_modes(struct drm_connector *connector) +{ + struct atmel_hlcdc_rgb_output *rgb = + drm_connector_to_atmel_hlcdc_rgb_output(connector); + struct atmel_hlcdc_panel *panel = atmel_hlcdc_rgb_output_to_panel(rgb); + + return panel->panel->funcs->get_modes(panel->panel); +} + +static int atmel_hlcdc_rgb_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct atmel_hlcdc_rgb_output *rgb = + drm_connector_to_atmel_hlcdc_rgb_output(connector); + + return atmel_hlcdc_dc_mode_valid(rgb->dc, mode); +} + + + +static struct drm_encoder * +atmel_hlcdc_rgb_best_encoder(struct drm_connector *connector) +{ + struct atmel_hlcdc_rgb_output *rgb = + drm_connector_to_atmel_hlcdc_rgb_output(connector); + + return &rgb->encoder; +} + +static struct drm_connector_helper_funcs atmel_hlcdc_panel_connector_helper_funcs = { + .get_modes = atmel_hlcdc_panel_get_modes, + .mode_valid = atmel_hlcdc_rgb_mode_valid, + .best_encoder = atmel_hlcdc_rgb_best_encoder, +}; + +static enum drm_connector_status +atmel_hlcdc_panel_connector_detect(struct drm_connector *connector, bool force) +{ + return connector_status_connected; +} + +static void +atmel_hlcdc_panel_connector_destroy(struct drm_connector *connector) +{ + struct atmel_hlcdc_rgb_output *rgb = + drm_connector_to_atmel_hlcdc_rgb_output(connector); + struct atmel_hlcdc_panel *panel = atmel_hlcdc_rgb_output_to_panel(rgb); + + drm_panel_detach(panel->panel); + drm_connector_cleanup(connector); +} + +static const struct drm_connector_funcs atmel_hlcdc_panel_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .detect = atmel_hlcdc_panel_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = atmel_hlcdc_panel_connector_destroy, +}; + +static int atmel_hlcdc_create_panel_output(struct drm_device *dev, + struct of_endpoint *ep) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + struct device_node *np; + struct drm_panel *p = NULL; + struct atmel_hlcdc_panel *panel; + int ret; + + np = of_graph_get_remote_port_parent(ep->local_node); + if (!np) + return -EINVAL; + + p = of_drm_find_panel(np); + of_node_put(np); + + if (!p) + return -EPROBE_DEFER; + + panel = devm_kzalloc(dev->dev, sizeof(*panel), GFP_KERNEL); + if (!panel) + return -EINVAL; + + panel->base.dpms = DRM_MODE_DPMS_OFF; + + panel->base.dc = dc; + + drm_encoder_helper_add(&panel->base.encoder, + &atmel_hlcdc_panel_encoder_helper_funcs); + ret = drm_encoder_init(dev, &panel->base.encoder, + &atmel_hlcdc_panel_encoder_funcs, + DRM_MODE_ENCODER_LVDS); + if (ret) + return ret; + + panel->base.connector.dpms = DRM_MODE_DPMS_OFF; + panel->base.connector.polled = DRM_CONNECTOR_POLL_CONNECT; + drm_connector_helper_add(&panel->base.connector, + &atmel_hlcdc_panel_connector_helper_funcs); + ret = drm_connector_init(dev, &panel->base.connector, + &atmel_hlcdc_panel_connector_funcs, + DRM_MODE_CONNECTOR_LVDS); + if (ret) + goto err_encoder_cleanup; + + drm_mode_connector_attach_encoder(&panel->base.connector, + &panel->base.encoder); + panel->base.encoder.possible_crtcs = 0x1; + + drm_panel_attach(p, &panel->base.connector); + panel->panel = p; + + return 0; + +err_encoder_cleanup: + drm_encoder_cleanup(&panel->base.encoder); + + return ret; +} + +int atmel_hlcdc_create_outputs(struct drm_device *dev) +{ + struct device_node *port_np, *np; + struct of_endpoint ep; + int ret; + + port_np = of_get_child_by_name(dev->dev->of_node, "port"); + if (!port_np) + return -EINVAL; + + np = of_get_child_by_name(port_np, "endpoint"); + of_node_put(port_np); + + if (!np) + return -EINVAL; + + ret = of_graph_parse_endpoint(np, &ep); + of_node_put(port_np); + + if (ret) + return ret; + + /* We currently only support panel output */ + return atmel_hlcdc_create_panel_output(dev, &ep); +} diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c new file mode 100644 index 000000000000..c5892dcfd745 --- /dev/null +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -0,0 +1,856 @@ +/* + * Copyright (C) 2014 Free Electrons + * Copyright (C) 2014 Atmel + * + * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "atmel_hlcdc_dc.h" + +#define SUBPIXEL_MASK 0xffff + +static uint32_t rgb_formats[] = { + DRM_FORMAT_XRGB4444, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_RGBA4444, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGB565, + DRM_FORMAT_RGB888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGBA8888, +}; + +struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats = { + .formats = rgb_formats, + .nformats = ARRAY_SIZE(rgb_formats), +}; + +static uint32_t rgb_and_yuv_formats[] = { + DRM_FORMAT_XRGB4444, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_RGBA4444, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGB565, + DRM_FORMAT_RGB888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_AYUV, + DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY, + DRM_FORMAT_YVYU, + DRM_FORMAT_VYUY, + DRM_FORMAT_NV21, + DRM_FORMAT_NV61, + DRM_FORMAT_YUV422, + DRM_FORMAT_YUV420, +}; + +struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats = { + .formats = rgb_and_yuv_formats, + .nformats = ARRAY_SIZE(rgb_and_yuv_formats), +}; + +static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode) +{ + switch (format) { + case DRM_FORMAT_XRGB4444: + *mode = ATMEL_HLCDC_XRGB4444_MODE; + break; + case DRM_FORMAT_ARGB4444: + *mode = ATMEL_HLCDC_ARGB4444_MODE; + break; + case DRM_FORMAT_RGBA4444: + *mode = ATMEL_HLCDC_RGBA4444_MODE; + break; + case DRM_FORMAT_RGB565: + *mode = ATMEL_HLCDC_RGB565_MODE; + break; + case DRM_FORMAT_RGB888: + *mode = ATMEL_HLCDC_RGB888_MODE; + break; + case DRM_FORMAT_ARGB1555: + *mode = ATMEL_HLCDC_ARGB1555_MODE; + break; + case DRM_FORMAT_XRGB8888: + *mode = ATMEL_HLCDC_XRGB8888_MODE; + break; + case DRM_FORMAT_ARGB8888: + *mode = ATMEL_HLCDC_ARGB8888_MODE; + break; + case DRM_FORMAT_RGBA8888: + *mode = ATMEL_HLCDC_RGBA8888_MODE; + break; + case DRM_FORMAT_AYUV: + *mode = ATMEL_HLCDC_AYUV_MODE; + break; + case DRM_FORMAT_YUYV: + *mode = ATMEL_HLCDC_YUYV_MODE; + break; + case DRM_FORMAT_UYVY: + *mode = ATMEL_HLCDC_UYVY_MODE; + break; + case DRM_FORMAT_YVYU: + *mode = ATMEL_HLCDC_YVYU_MODE; + break; + case DRM_FORMAT_VYUY: + *mode = ATMEL_HLCDC_VYUY_MODE; + break; + case DRM_FORMAT_NV21: + *mode = ATMEL_HLCDC_NV21_MODE; + break; + case DRM_FORMAT_NV61: + *mode = ATMEL_HLCDC_NV61_MODE; + break; + case DRM_FORMAT_YUV420: + *mode = ATMEL_HLCDC_YUV420_MODE; + break; + case DRM_FORMAT_YUV422: + *mode = ATMEL_HLCDC_YUV422_MODE; + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static bool atmel_hlcdc_format_embedds_alpha(u32 format) +{ + int i; + + for (i = 0; i < sizeof(format); i++) { + char tmp = (format >> (8 * i)) & 0xff; + + if (tmp == 'A') + return true; + } + + return false; +} + +static u32 heo_downscaling_xcoef[] = { + 0x11343311, + 0x000000f7, + 0x1635300c, + 0x000000f9, + 0x1b362c08, + 0x000000fb, + 0x1f372804, + 0x000000fe, + 0x24382400, + 0x00000000, + 0x28371ffe, + 0x00000004, + 0x2c361bfb, + 0x00000008, + 0x303516f9, + 0x0000000c, +}; + +static u32 heo_downscaling_ycoef[] = { + 0x00123737, + 0x00173732, + 0x001b382d, + 0x001f3928, + 0x00243824, + 0x0028391f, + 0x002d381b, + 0x00323717, +}; + +static u32 heo_upscaling_xcoef[] = { + 0xf74949f7, + 0x00000000, + 0xf55f33fb, + 0x000000fe, + 0xf5701efe, + 0x000000ff, + 0xf87c0dff, + 0x00000000, + 0x00800000, + 0x00000000, + 0x0d7cf800, + 0x000000ff, + 0x1e70f5ff, + 0x000000fe, + 0x335ff5fe, + 0x000000fb, +}; + +static u32 heo_upscaling_ycoef[] = { + 0x00004040, + 0x00075920, + 0x00056f0c, + 0x00027b03, + 0x00008000, + 0x00037b02, + 0x000c6f05, + 0x00205907, +}; + +static void +atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_update_req *req) +{ + const struct atmel_hlcdc_layer_cfg_layout *layout = + &plane->layer.desc->layout; + + if (layout->size) + atmel_hlcdc_layer_update_cfg(&plane->layer, + layout->size, + 0xffffffff, + (req->crtc_w - 1) | + ((req->crtc_h - 1) << 16)); + + if (layout->memsize) + atmel_hlcdc_layer_update_cfg(&plane->layer, + layout->memsize, + 0xffffffff, + (req->src_w - 1) | + ((req->src_h - 1) << 16)); + + if (layout->pos) + atmel_hlcdc_layer_update_cfg(&plane->layer, + layout->pos, + 0xffffffff, + req->crtc_x | + (req->crtc_y << 16)); + + /* TODO: rework the rescaling part */ + if (req->crtc_w != req->src_w || req->crtc_h != req->src_h) { + u32 factor_reg = 0; + + if (req->crtc_w != req->src_w) { + int i; + u32 factor; + u32 *coeff_tab = heo_upscaling_xcoef; + u32 max_memsize; + + if (req->crtc_w < req->src_w) + coeff_tab = heo_downscaling_xcoef; + for (i = 0; i < ARRAY_SIZE(heo_upscaling_xcoef); i++) + atmel_hlcdc_layer_update_cfg(&plane->layer, + 17 + i, + 0xffffffff, + coeff_tab[i]); + factor = ((8 * 256 * req->src_w) - (256 * 4)) / + req->crtc_w; + factor++; + max_memsize = ((factor * req->crtc_w) + (256 * 4)) / + 2048; + if (max_memsize > req->src_w) + factor--; + factor_reg |= factor | 0x80000000; + } + + if (req->crtc_h != req->src_h) { + int i; + u32 factor; + u32 *coeff_tab = heo_upscaling_ycoef; + u32 max_memsize; + + if (req->crtc_w < req->src_w) + coeff_tab = heo_downscaling_ycoef; + for (i = 0; i < ARRAY_SIZE(heo_upscaling_ycoef); i++) + atmel_hlcdc_layer_update_cfg(&plane->layer, + 33 + i, + 0xffffffff, + coeff_tab[i]); + factor = ((8 * 256 * req->src_w) - (256 * 4)) / + req->crtc_w; + factor++; + max_memsize = ((factor * req->crtc_w) + (256 * 4)) / + 2048; + if (max_memsize > req->src_w) + factor--; + factor_reg |= (factor << 16) | 0x80000000; + } + + atmel_hlcdc_layer_update_cfg(&plane->layer, 13, 0xffffffff, + factor_reg); + } +} + +static void +atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_update_req *req) +{ + const struct atmel_hlcdc_layer_cfg_layout *layout = + &plane->layer.desc->layout; + unsigned int cfg = ATMEL_HLCDC_LAYER_DMA; + + if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) { + cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL | + ATMEL_HLCDC_LAYER_ITER; + + if (atmel_hlcdc_format_embedds_alpha(req->fb->pixel_format)) + cfg |= ATMEL_HLCDC_LAYER_LAEN; + else + cfg |= ATMEL_HLCDC_LAYER_GAEN; + } + + atmel_hlcdc_layer_update_cfg(&plane->layer, + ATMEL_HLCDC_LAYER_DMA_CFG_ID, + ATMEL_HLCDC_LAYER_DMA_BLEN_MASK, + ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16); + + atmel_hlcdc_layer_update_cfg(&plane->layer, layout->general_config, + ATMEL_HLCDC_LAYER_ITER2BL | + ATMEL_HLCDC_LAYER_ITER | + ATMEL_HLCDC_LAYER_GAEN | + ATMEL_HLCDC_LAYER_LAEN | + ATMEL_HLCDC_LAYER_OVR | + ATMEL_HLCDC_LAYER_DMA, cfg); +} + +static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_update_req *req) +{ + u32 cfg; + int ret; + + ret = atmel_hlcdc_format_to_plane_mode(req->fb->pixel_format, &cfg); + if (ret) + return; + + if ((req->fb->pixel_format == DRM_FORMAT_YUV422 || + req->fb->pixel_format == DRM_FORMAT_NV61) && + (plane->rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)))) + cfg |= ATMEL_HLCDC_YUV422ROT; + + atmel_hlcdc_layer_update_cfg(&plane->layer, + ATMEL_HLCDC_LAYER_FORMAT_CFG_ID, + 0xffffffff, + cfg); + + /* + * Rotation optimization is not working on RGB888 (rotation is still + * working but without any optimization). + */ + if (req->fb->pixel_format == DRM_FORMAT_RGB888) + cfg = ATMEL_HLCDC_LAYER_DMA_ROTDIS; + else + cfg = 0; + + atmel_hlcdc_layer_update_cfg(&plane->layer, + ATMEL_HLCDC_LAYER_DMA_CFG_ID, + ATMEL_HLCDC_LAYER_DMA_ROTDIS, cfg); +} + +static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_update_req *req) +{ + struct atmel_hlcdc_layer *layer = &plane->layer; + const struct atmel_hlcdc_layer_cfg_layout *layout = + &layer->desc->layout; + int i; + + atmel_hlcdc_layer_update_set_fb(&plane->layer, req->fb, req->offsets); + + for (i = 0; i < req->nplanes; i++) { + if (layout->xstride[i]) { + atmel_hlcdc_layer_update_cfg(&plane->layer, + layout->xstride[i], + 0xffffffff, + req->xstride[i]); + } + + if (layout->pstride[i]) { + atmel_hlcdc_layer_update_cfg(&plane->layer, + layout->pstride[i], + 0xffffffff, + req->pstride[i]); + } + } +} + +static int atmel_hlcdc_plane_check_update_req(struct drm_plane *p, + struct atmel_hlcdc_plane_update_req *req, + const struct drm_display_mode *mode) +{ + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + const struct atmel_hlcdc_layer_cfg_layout *layout = + &plane->layer.desc->layout; + + if (!layout->size && + (mode->hdisplay != req->crtc_w || + mode->vdisplay != req->crtc_h)) + return -EINVAL; + + if (plane->layer.desc->max_height && + req->crtc_h > plane->layer.desc->max_height) + return -EINVAL; + + if (plane->layer.desc->max_width && + req->crtc_w > plane->layer.desc->max_width) + return -EINVAL; + + if ((req->crtc_h != req->src_h || req->crtc_w != req->src_w) && + (!layout->memsize || + atmel_hlcdc_format_embedds_alpha(req->fb->pixel_format))) + return -EINVAL; + + if (req->crtc_x < 0 || req->crtc_y < 0) + return -EINVAL; + + if (req->crtc_w + req->crtc_x > mode->hdisplay || + req->crtc_h + req->crtc_y > mode->vdisplay) + return -EINVAL; + + return 0; +} + +int atmel_hlcdc_plane_prepare_update_req(struct drm_plane *p, + struct atmel_hlcdc_plane_update_req *req, + const struct drm_display_mode *mode) +{ + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + unsigned int patched_crtc_w; + unsigned int patched_crtc_h; + unsigned int patched_src_w; + unsigned int patched_src_h; + unsigned int tmp; + int x_offset = 0; + int y_offset = 0; + int hsub = 1; + int vsub = 1; + int i; + + if ((req->src_x | req->src_y | req->src_w | req->src_h) & + SUBPIXEL_MASK) + return -EINVAL; + + req->src_x >>= 16; + req->src_y >>= 16; + req->src_w >>= 16; + req->src_h >>= 16; + + req->nplanes = drm_format_num_planes(req->fb->pixel_format); + if (req->nplanes > ATMEL_HLCDC_MAX_PLANES) + return -EINVAL; + + /* + * Swap width and size in case of 90 or 270 degrees rotation + */ + if (plane->rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))) { + tmp = req->crtc_w; + req->crtc_w = req->crtc_h; + req->crtc_h = tmp; + tmp = req->src_w; + req->src_w = req->src_h; + req->src_h = tmp; + } + + if (req->crtc_x + req->crtc_w > mode->hdisplay) + patched_crtc_w = mode->hdisplay - req->crtc_x; + else + patched_crtc_w = req->crtc_w; + + if (req->crtc_x < 0) { + patched_crtc_w += req->crtc_x; + x_offset = -req->crtc_x; + req->crtc_x = 0; + } + + if (req->crtc_y + req->crtc_h > mode->vdisplay) + patched_crtc_h = mode->vdisplay - req->crtc_y; + else + patched_crtc_h = req->crtc_h; + + if (req->crtc_y < 0) { + patched_crtc_h += req->crtc_y; + y_offset = -req->crtc_y; + req->crtc_y = 0; + } + + patched_src_w = DIV_ROUND_CLOSEST(patched_crtc_w * req->src_w, + req->crtc_w); + patched_src_h = DIV_ROUND_CLOSEST(patched_crtc_h * req->src_h, + req->crtc_h); + + hsub = drm_format_horz_chroma_subsampling(req->fb->pixel_format); + vsub = drm_format_vert_chroma_subsampling(req->fb->pixel_format); + + for (i = 0; i < req->nplanes; i++) { + unsigned int offset = 0; + int xdiv = i ? hsub : 1; + int ydiv = i ? vsub : 1; + + req->bpp[i] = drm_format_plane_cpp(req->fb->pixel_format, i); + if (!req->bpp[i]) + return -EINVAL; + + switch (plane->rotation & 0xf) { + case BIT(DRM_ROTATE_90): + offset = ((y_offset + req->src_y + patched_src_w - 1) / + ydiv) * req->fb->pitches[i]; + offset += ((x_offset + req->src_x) / xdiv) * + req->bpp[i]; + req->xstride[i] = ((patched_src_w - 1) / ydiv) * + req->fb->pitches[i]; + req->pstride[i] = -req->fb->pitches[i] - req->bpp[i]; + break; + case BIT(DRM_ROTATE_180): + offset = ((y_offset + req->src_y + patched_src_h - 1) / + ydiv) * req->fb->pitches[i]; + offset += ((x_offset + req->src_x + patched_src_w - 1) / + xdiv) * req->bpp[i]; + req->xstride[i] = ((((patched_src_w - 1) / xdiv) - 1) * + req->bpp[i]) - req->fb->pitches[i]; + req->pstride[i] = -2 * req->bpp[i]; + break; + case BIT(DRM_ROTATE_270): + offset = ((y_offset + req->src_y) / ydiv) * + req->fb->pitches[i]; + offset += ((x_offset + req->src_x + patched_src_h - 1) / + xdiv) * req->bpp[i]; + req->xstride[i] = -(((patched_src_w - 1) / ydiv) * + req->fb->pitches[i]) - + (2 * req->bpp[i]); + req->pstride[i] = req->fb->pitches[i] - req->bpp[i]; + break; + case BIT(DRM_ROTATE_0): + default: + offset = ((y_offset + req->src_y) / ydiv) * + req->fb->pitches[i]; + offset += ((x_offset + req->src_x) / xdiv) * + req->bpp[i]; + req->xstride[i] = req->fb->pitches[i] - + ((patched_src_w / xdiv) * + req->bpp[i]); + req->pstride[i] = 0; + break; + } + + req->offsets[i] = offset + req->fb->offsets[i]; + } + + req->src_w = patched_src_w; + req->src_h = patched_src_h; + req->crtc_w = patched_crtc_w; + req->crtc_h = patched_crtc_h; + + return atmel_hlcdc_plane_check_update_req(p, req, mode); +} + +int atmel_hlcdc_plane_apply_update_req(struct drm_plane *p, + struct atmel_hlcdc_plane_update_req *req) +{ + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + int ret; + + ret = atmel_hlcdc_layer_update_start(&plane->layer); + if (ret) + return ret; + + atmel_hlcdc_plane_update_pos_and_size(plane, req); + atmel_hlcdc_plane_update_general_settings(plane, req); + atmel_hlcdc_plane_update_format(plane, req); + atmel_hlcdc_plane_update_buffers(plane, req); + + atmel_hlcdc_layer_update_commit(&plane->layer); + + return 0; +} + +int atmel_hlcdc_plane_update_with_mode(struct drm_plane *p, + struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int crtc_x, int crtc_y, + unsigned int crtc_w, + unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h, + const struct drm_display_mode *mode) +{ + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + struct atmel_hlcdc_plane_update_req req; + int ret = 0; + + memset(&req, 0, sizeof(req)); + req.crtc_x = crtc_x; + req.crtc_y = crtc_y; + req.crtc_w = crtc_w; + req.crtc_h = crtc_h; + req.src_x = src_x; + req.src_y = src_y; + req.src_w = src_w; + req.src_h = src_h; + req.fb = fb; + + ret = atmel_hlcdc_plane_prepare_update_req(&plane->base, &req, mode); + if (ret) + return ret; + + if (!req.crtc_h || !req.crtc_w) + return atmel_hlcdc_layer_disable(&plane->layer); + + return atmel_hlcdc_plane_apply_update_req(&plane->base, &req); +} + +static int atmel_hlcdc_plane_update(struct drm_plane *p, + struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int crtc_x, int crtc_y, + unsigned int crtc_w, unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h) +{ + return atmel_hlcdc_plane_update_with_mode(p, crtc, fb, crtc_x, crtc_y, + crtc_w, crtc_h, src_x, src_y, + src_w, src_h, &crtc->hwmode); +} + +static int atmel_hlcdc_plane_disable(struct drm_plane *p) +{ + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + + return atmel_hlcdc_layer_disable(&plane->layer); +} + +static void atmel_hlcdc_plane_destroy(struct drm_plane *p) +{ + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + + if (plane->base.fb) + drm_framebuffer_unreference(plane->base.fb); + + atmel_hlcdc_layer_cleanup(p->dev, &plane->layer); + + drm_plane_cleanup(p); + devm_kfree(p->dev->dev, plane); +} + +static int atmel_hlcdc_plane_set_alpha(struct atmel_hlcdc_plane *plane, + u8 alpha) +{ + atmel_hlcdc_layer_update_start(&plane->layer); + atmel_hlcdc_layer_update_cfg(&plane->layer, + plane->layer.desc->layout.general_config, + ATMEL_HLCDC_LAYER_GA_MASK, + alpha << ATMEL_HLCDC_LAYER_GA_SHIFT); + atmel_hlcdc_layer_update_commit(&plane->layer); + + return 0; +} + +static int atmel_hlcdc_plane_set_rotation(struct atmel_hlcdc_plane *plane, + unsigned int rotation) +{ + plane->rotation = rotation; + + return 0; +} + +static int atmel_hlcdc_plane_set_property(struct drm_plane *p, + struct drm_property *property, + uint64_t value) +{ + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + struct atmel_hlcdc_plane_properties *props = plane->properties; + + if (property == props->alpha) + atmel_hlcdc_plane_set_alpha(plane, value); + else if (property == props->rotation) + atmel_hlcdc_plane_set_rotation(plane, value); + else + return -EINVAL; + + return 0; +} + +static void atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane, + const struct atmel_hlcdc_layer_desc *desc, + struct atmel_hlcdc_plane_properties *props) +{ + struct regmap *regmap = plane->layer.hlcdc->regmap; + + if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER || + desc->type == ATMEL_HLCDC_CURSOR_LAYER) { + drm_object_attach_property(&plane->base.base, + props->alpha, 255); + + /* Set default alpha value */ + regmap_update_bits(regmap, + desc->regs_offset + + ATMEL_HLCDC_LAYER_GENERAL_CFG(&plane->layer), + ATMEL_HLCDC_LAYER_GA_MASK, + ATMEL_HLCDC_LAYER_GA_MASK); + } + + if (desc->layout.xstride && desc->layout.pstride) + drm_object_attach_property(&plane->base.base, + props->rotation, + BIT(DRM_ROTATE_0)); + + if (desc->layout.csc) { + /* + * TODO: decare a "yuv-to-rgb-conv-factors" property to let + * userspace modify these factors (using a BLOB property ?). + */ + regmap_write(regmap, + desc->regs_offset + + ATMEL_HLCDC_LAYER_CSC_CFG(&plane->layer, 0), + 0x4c900091); + regmap_write(regmap, + desc->regs_offset + + ATMEL_HLCDC_LAYER_CSC_CFG(&plane->layer, 1), + 0x7a5f5090); + regmap_write(regmap, + desc->regs_offset + + ATMEL_HLCDC_LAYER_CSC_CFG(&plane->layer, 2), + 0x40040890); + } +} + +static struct drm_plane_funcs layer_plane_funcs = { + .update_plane = atmel_hlcdc_plane_update, + .disable_plane = atmel_hlcdc_plane_disable, + .set_property = atmel_hlcdc_plane_set_property, + .destroy = atmel_hlcdc_plane_destroy, +}; + +static struct atmel_hlcdc_plane * +atmel_hlcdc_plane_create(struct drm_device *dev, + const struct atmel_hlcdc_layer_desc *desc, + struct atmel_hlcdc_plane_properties *props) +{ + struct atmel_hlcdc_plane *plane; + enum drm_plane_type type; + int ret; + + plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL); + if (!plane) + return ERR_PTR(-ENOMEM); + + ret = atmel_hlcdc_layer_init(dev, &plane->layer, desc); + if (ret) + return ERR_PTR(ret); + + if (desc->type == ATMEL_HLCDC_BASE_LAYER) + type = DRM_PLANE_TYPE_PRIMARY; + else if (desc->type == ATMEL_HLCDC_CURSOR_LAYER) + type = DRM_PLANE_TYPE_CURSOR; + else + type = DRM_PLANE_TYPE_OVERLAY; + + ret = drm_universal_plane_init(dev, &plane->base, 0, + &layer_plane_funcs, + desc->formats->formats, + desc->formats->nformats, type); + if (ret) + return ERR_PTR(ret); + + /* Set default property values*/ + atmel_hlcdc_plane_init_properties(plane, desc, props); + + return plane; +} + +static struct atmel_hlcdc_plane_properties * +atmel_hlcdc_plane_create_properties(struct drm_device *dev) +{ + struct atmel_hlcdc_plane_properties *props; + + props = devm_kzalloc(dev->dev, sizeof(*props), GFP_KERNEL); + if (!props) + return ERR_PTR(-ENOMEM); + + props->alpha = drm_property_create_range(dev, 0, "alpha", 0, 255); + if (!props->alpha) + return ERR_PTR(-ENOMEM); + + props->rotation = drm_mode_create_rotation_property(dev, + BIT(DRM_ROTATE_0) | + BIT(DRM_ROTATE_90) | + BIT(DRM_ROTATE_180) | + BIT(DRM_ROTATE_270)); + if (!props->rotation) + return ERR_PTR(-ENOMEM); + + return props; +} + +struct atmel_hlcdc_planes * +atmel_hlcdc_create_planes(struct drm_device *dev) +{ + struct atmel_hlcdc_dc *dc = dev->dev_private; + struct atmel_hlcdc_plane_properties *props; + struct atmel_hlcdc_planes *planes; + const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers; + int nlayers = dc->desc->nlayers; + int i; + + planes = devm_kzalloc(dev->dev, sizeof(*planes), GFP_KERNEL); + if (!planes) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < nlayers; i++) { + if (descs[i].type == ATMEL_HLCDC_OVERLAY_LAYER) + planes->noverlays++; + } + + if (planes->noverlays) { + planes->overlays = devm_kzalloc(dev->dev, + planes->noverlays * + sizeof(*planes->overlays), + GFP_KERNEL); + if (!planes->overlays) + return ERR_PTR(-ENOMEM); + } + + props = atmel_hlcdc_plane_create_properties(dev); + if (IS_ERR(props)) + return ERR_CAST(props); + + planes->noverlays = 0; + for (i = 0; i < nlayers; i++) { + struct atmel_hlcdc_plane *plane; + + if (descs[i].type == ATMEL_HLCDC_PP_LAYER) + continue; + + plane = atmel_hlcdc_plane_create(dev, &descs[i], props); + if (IS_ERR(plane)) + return ERR_CAST(plane); + + plane->properties = props; + + switch (descs[i].type) { + case ATMEL_HLCDC_BASE_LAYER: + if (planes->primary) + return ERR_PTR(-EINVAL); + planes->primary = plane; + break; + + case ATMEL_HLCDC_OVERLAY_LAYER: + planes->overlays[planes->noverlays++] = plane; + break; + + case ATMEL_HLCDC_CURSOR_LAYER: + if (planes->cursor) + return ERR_PTR(-EINVAL); + planes->cursor = plane; + break; + + default: + break; + } + } + + return planes; +} diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index caec5c3634bb..df90048de92e 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -762,6 +762,40 @@ static void drm_mode_remove(struct drm_connector *connector, } /** + * drm_display_info_set_bus_formats - set the supported bus formats + * @info: display info to store bus formats in + * @fmts: array containing the supported bus formats + * @nfmts: the number of entries in the fmts array + * + * Store the supported bus formats in display info structure. + * See MEDIA_BUS_FMT_* definitions in include/uapi/linux/media-bus-format.h for + * a full list of available formats. + */ +int drm_display_info_set_bus_formats(struct drm_display_info *info, + const u32 *formats, + unsigned int num_formats) +{ + u32 *fmts = NULL; + + if (!formats && num_formats) + return -EINVAL; + + if (formats && num_formats) { + fmts = kmemdup(formats, sizeof(*formats) * num_formats, + GFP_KERNEL); + if (!formats) + return -ENOMEM; + } + + kfree(info->bus_formats); + info->bus_formats = fmts; + info->num_bus_formats = num_formats; + + return 0; +} +EXPORT_SYMBOL(drm_display_info_set_bus_formats); + +/** * drm_connector_get_cmdline_mode - reads the user's cmdline mode * @connector: connector to quwery * @@ -923,6 +957,7 @@ void drm_connector_cleanup(struct drm_connector *connector) ida_remove(&drm_connector_enum_list[connector->connector_type].ida, connector->connector_type_id); + kfree(connector->display_info.bus_formats); drm_mode_object_put(dev, &connector->base); kfree(connector->name); connector->name = NULL; diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 876f1ef0acd1..d5c1db55abf7 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -741,7 +741,9 @@ int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info) int i, j, rc = 0; int start; - drm_modeset_lock_all(dev); + if (__drm_modeset_lock_all(dev, !!oops_in_progress)) { + return -EBUSY; + } if (!drm_fb_helper_is_bound(fb_helper)) { drm_modeset_unlock_all(dev); return -EBUSY; @@ -915,7 +917,9 @@ int drm_fb_helper_pan_display(struct fb_var_screeninfo *var, int ret = 0; int i; - drm_modeset_lock_all(dev); + if (__drm_modeset_lock_all(dev, !!oops_in_progress)) { + return -EBUSY; + } if (!drm_fb_helper_is_bound(fb_helper)) { drm_modeset_unlock_all(dev); return -EBUSY; diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index 121470a83d1a..1bcbe07cecfc 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -645,18 +645,6 @@ static int exynos_drm_init(void) if (!is_exynos) return -ENODEV; - /* - * Register device object only in case of Exynos SoC. - * - * Below codes resolves temporarily infinite loop issue incurred - * by Exynos drm driver when using multi-platform kernel. - * So these codes will be replaced with more generic way later. - */ - if (!of_machine_is_compatible("samsung,exynos3") && - !of_machine_is_compatible("samsung,exynos4") && - !of_machine_is_compatible("samsung,exynos5")) - return -ENODEV; - exynos_drm_pdev = platform_device_register_simple("exynos-drm", -1, NULL, 0); if (IS_ERR(exynos_drm_pdev)) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 5765a161abdd..98051e8e855a 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1669,7 +1669,6 @@ static void hdmi_mode_apply(struct hdmi_context *hdata) static void hdmiphy_conf_reset(struct hdmi_context *hdata) { - u8 buffer[2]; u32 reg; clk_disable_unprepare(hdata->res.sclk_hdmi); @@ -1677,11 +1676,8 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata) clk_prepare_enable(hdata->res.sclk_hdmi); /* operation mode */ - buffer[0] = 0x1f; - buffer[1] = 0x00; - - if (hdata->hdmiphy_port) - i2c_master_send(hdata->hdmiphy_port, buffer, 2); + hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, + HDMI_PHY_ENABLE_MODE_SET); if (hdata->type == HDMI_TYPE13) reg = HDMI_V13_PHY_RSTOUT; diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 820b76234ef4..064ed6597def 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -1026,6 +1026,7 @@ static void mixer_win_disable(struct exynos_drm_manager *mgr, int zpos) static void mixer_wait_for_vblank(struct exynos_drm_manager *mgr) { struct mixer_context *mixer_ctx = mgr_to_mixer(mgr); + int err; mutex_lock(&mixer_ctx->mixer_mutex); if (!mixer_ctx->powered) { @@ -1034,7 +1035,11 @@ static void mixer_wait_for_vblank(struct exynos_drm_manager *mgr) } mutex_unlock(&mixer_ctx->mixer_mutex); - drm_vblank_get(mgr->crtc->dev, mixer_ctx->pipe); + err = drm_vblank_get(mgr->crtc->dev, mixer_ctx->pipe); + if (err < 0) { + DRM_DEBUG_KMS("failed to acquire vblank counter\n"); + return; + } atomic_set(&mixer_ctx->wait_vsync_event, 1); @@ -1262,8 +1267,6 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) return ret; } - pm_runtime_enable(dev); - return 0; } @@ -1272,8 +1275,6 @@ static void mixer_unbind(struct device *dev, struct device *master, void *data) struct mixer_context *ctx = dev_get_drvdata(dev); mixer_mgr_remove(&ctx->manager); - - pm_runtime_disable(dev); } static const struct component_ops mixer_component_ops = { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fd7a493df0de..54f2a275dba6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1826,8 +1826,6 @@ struct drm_i915_private { */ struct workqueue_struct *dp_wq; - uint32_t bios_vgacntr; - /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ struct { int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3044fb324c8e..4e4d969d3b28 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1048,6 +1048,7 @@ int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { + struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_pwrite *args = data; struct drm_i915_gem_object *obj; int ret; @@ -1067,9 +1068,11 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, return -EFAULT; } + intel_runtime_pm_get(dev_priv); + ret = i915_mutex_lock_interruptible(dev); if (ret) - return ret; + goto put_rpm; obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); if (&obj->base == NULL) { @@ -1121,6 +1124,9 @@ out: drm_gem_object_unreference(&obj->base); unlock: mutex_unlock(&dev->struct_mutex); +put_rpm: + intel_runtime_pm_put(dev_priv); + return ret; } @@ -5090,7 +5096,7 @@ static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) if (!mutex_is_locked(mutex)) return false; -#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) +#if defined(CONFIG_SMP) && !defined(CONFIG_DEBUG_MUTEXES) return mutex->owner == task; #else /* Since UP may be pre-empted, we cannot assume that we own the lock */ diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 5d837735a3c2..818ab4e9dabc 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -296,6 +296,23 @@ void gen6_enable_rps_interrupts(struct drm_device *dev) spin_unlock_irq(&dev_priv->irq_lock); } +u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) +{ + /* + * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer + * if GEN6_PM_UP_EI_EXPIRED is masked. + * + * TODO: verify if this can be reproduced on VLV,CHV. + */ + if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) + mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; + + if (INTEL_INFO(dev_priv)->gen >= 8) + mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; + + return mask; +} + void gen6_disable_rps_interrupts(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -308,8 +325,7 @@ void gen6_disable_rps_interrupts(struct drm_device *dev) spin_lock_irq(&dev_priv->irq_lock); - I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ? - ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0); + I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & @@ -3731,8 +3747,6 @@ static bool i8xx_handle_vblank(struct drm_device *dev, if ((iir & flip_pending) == 0) goto check_page_flip; - intel_prepare_page_flip(dev, plane); - /* We detect FlipDone by looking for the change in PendingFlip from '1' * to '0' on the following vblank, i.e. IIR has the Pendingflip * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence @@ -3742,6 +3756,7 @@ static bool i8xx_handle_vblank(struct drm_device *dev, if (I915_READ16(ISR) & flip_pending) goto check_page_flip; + intel_prepare_page_flip(dev, plane); intel_finish_page_flip(dev, pipe); return true; @@ -3913,8 +3928,6 @@ static bool i915_handle_vblank(struct drm_device *dev, if ((iir & flip_pending) == 0) goto check_page_flip; - intel_prepare_page_flip(dev, plane); - /* We detect FlipDone by looking for the change in PendingFlip from '1' * to '0' on the following vblank, i.e. IIR has the Pendingflip * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence @@ -3924,6 +3937,7 @@ static bool i915_handle_vblank(struct drm_device *dev, if (I915_READ(ISR) & flip_pending) goto check_page_flip; + intel_prepare_page_flip(dev, plane); intel_finish_page_flip(dev, pipe); return true; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d01db1b82869..dc266e772340 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9703,7 +9703,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, if (obj->tiling_mode != work->old_fb_obj->tiling_mode) /* vlv: DISPLAY_FLIP fails to change tiling */ ring = NULL; - } else if (IS_IVYBRIDGE(dev)) { + } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { ring = &dev_priv->ring[BCS]; } else if (INTEL_INFO(dev)->gen >= 7) { ring = i915_gem_request_get_ring(obj->last_read_req); @@ -12956,11 +12956,7 @@ static void i915_disable_vga(struct drm_device *dev) vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); udelay(300); - /* - * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming - * from S3 without preserving (some of?) the other bits. - */ - I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE); + I915_WRITE(vga_reg, VGA_DISP_DISABLE); POSTING_READ(vga_reg); } @@ -13045,8 +13041,6 @@ void intel_modeset_init(struct drm_device *dev) intel_shared_dpll_init(dev); - /* save the BIOS value before clobbering it */ - dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev)); /* Just disable it once at startup */ i915_disable_vga(dev); intel_setup_outputs(dev); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 588b618ab668..bb871f3cfe2e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -795,6 +795,7 @@ void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_reset_rps_interrupts(struct drm_device *dev); void gen6_enable_rps_interrupts(struct drm_device *dev); void gen6_disable_rps_interrupts(struct drm_device *dev); +u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a3ebaa873107..7d99a9c4e49b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3745,16 +3745,7 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED); mask &= dev_priv->pm_rps_events; - /* IVB and SNB hard hangs on looping batchbuffer - * if GEN6_PM_UP_EI_EXPIRED is masked. - */ - if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev)) - mask |= GEN6_PM_RP_UP_EI_EXPIRED; - - if (IS_GEN8(dev_priv->dev)) - mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP; - - return ~mask; + return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); } /* gen6_set_rps is called to update the frequency request, but should also be @@ -3823,7 +3814,8 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) return; /* Mask turbo interrupt so that they will not come in between */ - I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); + I915_WRITE(GEN6_PMINTRMSK, + gen6_sanitize_rps_pm_mask(dev_priv, ~0)); vlv_force_gfx_clock(dev_priv, true); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 6aa3a81df485..39e1b071765d 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -615,29 +615,6 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, vlv_power_sequencer_reset(dev_priv); } -static void check_power_well_state(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - bool enabled = power_well->ops->is_enabled(dev_priv, power_well); - - if (power_well->always_on || !i915.disable_power_well) { - if (!enabled) - goto mismatch; - - return; - } - - if (enabled != (power_well->count > 0)) - goto mismatch; - - return; - -mismatch: - I915_STATE_WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n", - power_well->name, power_well->always_on, enabled, - power_well->count, i915.disable_power_well); -} - /** * intel_display_power_get - grab a power domain reference * @dev_priv: i915 device instance @@ -669,8 +646,6 @@ void intel_display_power_get(struct drm_i915_private *dev_priv, power_well->ops->enable(dev_priv, power_well); power_well->hw_enabled = true; } - - check_power_well_state(dev_priv, power_well); } power_domains->domain_use_count[domain]++; @@ -709,8 +684,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, power_well->hw_enabled = false; power_well->ops->disable(dev_priv, power_well); } - - check_power_well_state(dev_priv, power_well); } mutex_unlock(&power_domains->lock); diff --git a/drivers/gpu/drm/nouveau/Kbuild b/drivers/gpu/drm/nouveau/Kbuild new file mode 100644 index 000000000000..2b765663c1a3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/Kbuild @@ -0,0 +1,66 @@ +ccflags-y := -Iinclude/drm +ccflags-y += -I$(src)/include +ccflags-y += -I$(src)/include/nvkm +ccflags-y += -I$(src)/nvkm +ccflags-y += -I$(src) + +# NVKM - HW resource manager +#- code also used by various userspace tools/tests +include $(src)/nvif/Kbuild +nouveau-y := $(nvif-y) + +# NVIF - NVKM interface library (NVKM user interface also defined here) +#- code also used by various userspace tools/tests +include $(src)/nvkm/Kbuild +nouveau-y += $(nvkm-y) + +# DRM - general +ifdef CONFIG_X86 +nouveau-$(CONFIG_ACPI) += nouveau_acpi.o +endif +nouveau-y += nouveau_agp.o +nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o +nouveau-y += nouveau_drm.o +nouveau-y += nouveau_hwmon.o +nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o +nouveau-y += nouveau_nvif.o +nouveau-$(CONFIG_NOUVEAU_PLATFORM_DRIVER) += nouveau_platform.o +nouveau-y += nouveau_sysfs.o +nouveau-y += nouveau_usif.o # userspace <-> nvif +nouveau-y += nouveau_vga.o + +# DRM - memory management +nouveau-y += nouveau_bo.o +nouveau-y += nouveau_gem.o +nouveau-y += nouveau_prime.o +nouveau-y += nouveau_sgdma.o +nouveau-y += nouveau_ttm.o + +# DRM - modesetting +nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o +nouveau-y += nouveau_connector.o +nouveau-y += nouveau_display.o +nouveau-y += nv50_display.o +nouveau-y += nouveau_dp.o +nouveau-y += nouveau_fbcon.o +nouveau-y += nv04_fbcon.o +nouveau-y += nv50_fbcon.o +nouveau-y += nvc0_fbcon.o + +# DRM - command submission +nouveau-y += nouveau_abi16.o +nouveau-y += nouveau_chan.o +nouveau-y += nouveau_dma.o +nouveau-y += nouveau_fence.o +nouveau-y += nv04_fence.o +nouveau-y += nv10_fence.o +nouveau-y += nv17_fence.o +nouveau-y += nv50_fence.o +nouveau-y += nv84_fence.o +nouveau-y += nvc0_fence.o + +# DRM - prehistoric modesetting (NV04-G7x) +nouveau-y += nouveau_bios.o +include $(src)/dispnv04/Kbuild + +obj-$(CONFIG_DRM_NOUVEAU) += nouveau.o diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig index 40afc69a3778..5ab13e7939db 100644 --- a/drivers/gpu/drm/nouveau/Kconfig +++ b/drivers/gpu/drm/nouveau/Kconfig @@ -26,7 +26,7 @@ config DRM_NOUVEAU Choose this option for open-source NVIDIA support. config NOUVEAU_PLATFORM_DRIVER - tristate "Nouveau (NVIDIA) SoC GPUs" + bool "Nouveau (NVIDIA) SoC GPUs" depends on DRM_NOUVEAU && ARCH_TEGRA default y help diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile deleted file mode 100644 index 6461e3565afe..000000000000 --- a/drivers/gpu/drm/nouveau/Makefile +++ /dev/null @@ -1,400 +0,0 @@ -# -# Makefile for the drm device driver. This driver provides support for the -# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. - -ccflags-y := -Iinclude/drm -ccflags-y += -I$(src)/core/include -ccflags-y += -I$(src)/core -ccflags-y += -I$(src) - -nouveau-y := core/core/client.o -nouveau-y += core/core/engctx.o -nouveau-y += core/core/engine.o -nouveau-y += core/core/enum.o -nouveau-y += core/core/event.o -nouveau-y += core/core/gpuobj.o -nouveau-y += core/core/handle.o -nouveau-y += core/core/ioctl.o -nouveau-y += core/core/mm.o -nouveau-y += core/core/namedb.o -nouveau-y += core/core/notify.o -nouveau-y += core/core/object.o -nouveau-y += core/core/option.o -nouveau-y += core/core/parent.o -nouveau-y += core/core/printk.o -nouveau-y += core/core/ramht.o -nouveau-y += core/core/subdev.o - -nouveau-y += core/subdev/bar/base.o -nouveau-y += core/subdev/bar/nv50.o -nouveau-y += core/subdev/bar/nvc0.o -nouveau-y += core/subdev/bar/gk20a.o -nouveau-y += core/subdev/bios/base.o -nouveau-y += core/subdev/bios/bit.o -nouveau-y += core/subdev/bios/boost.o -nouveau-y += core/subdev/bios/conn.o -nouveau-y += core/subdev/bios/cstep.o -nouveau-y += core/subdev/bios/dcb.o -nouveau-y += core/subdev/bios/disp.o -nouveau-y += core/subdev/bios/dp.o -nouveau-y += core/subdev/bios/extdev.o -nouveau-y += core/subdev/bios/fan.o -nouveau-y += core/subdev/bios/gpio.o -nouveau-y += core/subdev/bios/i2c.o -nouveau-y += core/subdev/bios/image.o -nouveau-y += core/subdev/bios/init.o -nouveau-y += core/subdev/bios/mxm.o -nouveau-y += core/subdev/bios/npde.o -nouveau-y += core/subdev/bios/pcir.o -nouveau-y += core/subdev/bios/perf.o -nouveau-y += core/subdev/bios/pll.o -nouveau-y += core/subdev/bios/pmu.o -nouveau-y += core/subdev/bios/ramcfg.o -nouveau-y += core/subdev/bios/rammap.o -nouveau-y += core/subdev/bios/shadow.o -nouveau-y += core/subdev/bios/shadowacpi.o -nouveau-y += core/subdev/bios/shadowof.o -nouveau-y += core/subdev/bios/shadowpci.o -nouveau-y += core/subdev/bios/shadowramin.o -nouveau-y += core/subdev/bios/shadowrom.o -nouveau-y += core/subdev/bios/timing.o -nouveau-y += core/subdev/bios/therm.o -nouveau-y += core/subdev/bios/vmap.o -nouveau-y += core/subdev/bios/volt.o -nouveau-y += core/subdev/bios/xpio.o -nouveau-y += core/subdev/bios/M0203.o -nouveau-y += core/subdev/bios/M0205.o -nouveau-y += core/subdev/bios/M0209.o -nouveau-y += core/subdev/bios/P0260.o -nouveau-y += core/subdev/bus/hwsq.o -nouveau-y += core/subdev/bus/nv04.o -nouveau-y += core/subdev/bus/nv31.o -nouveau-y += core/subdev/bus/nv50.o -nouveau-y += core/subdev/bus/nv94.o -nouveau-y += core/subdev/bus/nvc0.o -nouveau-y += core/subdev/clock/base.o -nouveau-y += core/subdev/clock/nv04.o -nouveau-y += core/subdev/clock/nv40.o -nouveau-y += core/subdev/clock/nv50.o -nouveau-y += core/subdev/clock/nv84.o -nouveau-y += core/subdev/clock/nva3.o -nouveau-y += core/subdev/clock/nvaa.o -nouveau-y += core/subdev/clock/nvc0.o -nouveau-y += core/subdev/clock/nve0.o -nouveau-y += core/subdev/clock/gk20a.o -nouveau-y += core/subdev/clock/pllnv04.o -nouveau-y += core/subdev/clock/pllnva3.o -nouveau-y += core/subdev/devinit/base.o -nouveau-y += core/subdev/devinit/nv04.o -nouveau-y += core/subdev/devinit/nv05.o -nouveau-y += core/subdev/devinit/nv10.o -nouveau-y += core/subdev/devinit/nv1a.o -nouveau-y += core/subdev/devinit/nv20.o -nouveau-y += core/subdev/devinit/nv50.o -nouveau-y += core/subdev/devinit/nv84.o -nouveau-y += core/subdev/devinit/nv98.o -nouveau-y += core/subdev/devinit/nva3.o -nouveau-y += core/subdev/devinit/nvaf.o -nouveau-y += core/subdev/devinit/nvc0.o -nouveau-y += core/subdev/devinit/gm107.o -nouveau-y += core/subdev/devinit/gm204.o -nouveau-y += core/subdev/fb/base.o -nouveau-y += core/subdev/fb/nv04.o -nouveau-y += core/subdev/fb/nv10.o -nouveau-y += core/subdev/fb/nv1a.o -nouveau-y += core/subdev/fb/nv20.o -nouveau-y += core/subdev/fb/nv25.o -nouveau-y += core/subdev/fb/nv30.o -nouveau-y += core/subdev/fb/nv35.o -nouveau-y += core/subdev/fb/nv36.o -nouveau-y += core/subdev/fb/nv40.o -nouveau-y += core/subdev/fb/nv41.o -nouveau-y += core/subdev/fb/nv44.o -nouveau-y += core/subdev/fb/nv46.o -nouveau-y += core/subdev/fb/nv47.o -nouveau-y += core/subdev/fb/nv49.o -nouveau-y += core/subdev/fb/nv4e.o -nouveau-y += core/subdev/fb/nv50.o -nouveau-y += core/subdev/fb/nv84.o -nouveau-y += core/subdev/fb/nva3.o -nouveau-y += core/subdev/fb/nvaa.o -nouveau-y += core/subdev/fb/nvaf.o -nouveau-y += core/subdev/fb/nvc0.o -nouveau-y += core/subdev/fb/nve0.o -nouveau-y += core/subdev/fb/gk20a.o -nouveau-y += core/subdev/fb/gm107.o -nouveau-y += core/subdev/fb/ramnv04.o -nouveau-y += core/subdev/fb/ramnv10.o -nouveau-y += core/subdev/fb/ramnv1a.o -nouveau-y += core/subdev/fb/ramnv20.o -nouveau-y += core/subdev/fb/ramnv40.o -nouveau-y += core/subdev/fb/ramnv41.o -nouveau-y += core/subdev/fb/ramnv44.o -nouveau-y += core/subdev/fb/ramnv49.o -nouveau-y += core/subdev/fb/ramnv4e.o -nouveau-y += core/subdev/fb/ramnv50.o -nouveau-y += core/subdev/fb/ramnva3.o -nouveau-y += core/subdev/fb/ramnvaa.o -nouveau-y += core/subdev/fb/ramnvc0.o -nouveau-y += core/subdev/fb/ramnve0.o -nouveau-y += core/subdev/fb/ramgk20a.o -nouveau-y += core/subdev/fb/ramgm107.o -nouveau-y += core/subdev/fb/sddr2.o -nouveau-y += core/subdev/fb/sddr3.o -nouveau-y += core/subdev/fb/gddr3.o -nouveau-y += core/subdev/fb/gddr5.o -nouveau-y += core/subdev/fuse/base.o -nouveau-y += core/subdev/fuse/g80.o -nouveau-y += core/subdev/fuse/gf100.o -nouveau-y += core/subdev/fuse/gm107.o -nouveau-y += core/subdev/gpio/base.o -nouveau-y += core/subdev/gpio/nv10.o -nouveau-y += core/subdev/gpio/nv50.o -nouveau-y += core/subdev/gpio/nv94.o -nouveau-y += core/subdev/gpio/nvd0.o -nouveau-y += core/subdev/gpio/nve0.o -nouveau-y += core/subdev/i2c/base.o -nouveau-y += core/subdev/i2c/anx9805.o -nouveau-y += core/subdev/i2c/aux.o -nouveau-y += core/subdev/i2c/bit.o -nouveau-y += core/subdev/i2c/pad.o -nouveau-y += core/subdev/i2c/padnv04.o -nouveau-y += core/subdev/i2c/padnv94.o -nouveau-y += core/subdev/i2c/padgm204.o -nouveau-y += core/subdev/i2c/nv04.o -nouveau-y += core/subdev/i2c/nv4e.o -nouveau-y += core/subdev/i2c/nv50.o -nouveau-y += core/subdev/i2c/nv94.o -nouveau-y += core/subdev/i2c/nvd0.o -nouveau-y += core/subdev/i2c/gf117.o -nouveau-y += core/subdev/i2c/nve0.o -nouveau-y += core/subdev/i2c/gm204.o -nouveau-y += core/subdev/ibus/nvc0.o -nouveau-y += core/subdev/ibus/nve0.o -nouveau-y += core/subdev/ibus/gk20a.o -nouveau-y += core/subdev/instmem/base.o -nouveau-y += core/subdev/instmem/nv04.o -nouveau-y += core/subdev/instmem/nv40.o -nouveau-y += core/subdev/instmem/nv50.o -nouveau-y += core/subdev/ltc/base.o -nouveau-y += core/subdev/ltc/gf100.o -nouveau-y += core/subdev/ltc/gk104.o -nouveau-y += core/subdev/ltc/gm107.o -nouveau-y += core/subdev/mc/base.o -nouveau-y += core/subdev/mc/nv04.o -nouveau-y += core/subdev/mc/nv40.o -nouveau-y += core/subdev/mc/nv44.o -nouveau-y += core/subdev/mc/nv4c.o -nouveau-y += core/subdev/mc/nv50.o -nouveau-y += core/subdev/mc/nv94.o -nouveau-y += core/subdev/mc/nv98.o -nouveau-y += core/subdev/mc/nvc0.o -nouveau-y += core/subdev/mc/nvc3.o -nouveau-y += core/subdev/mc/gk20a.o -nouveau-y += core/subdev/mxm/base.o -nouveau-y += core/subdev/mxm/mxms.o -nouveau-y += core/subdev/mxm/nv50.o -nouveau-y += core/subdev/pwr/base.o -nouveau-y += core/subdev/pwr/memx.o -nouveau-y += core/subdev/pwr/nva3.o -nouveau-y += core/subdev/pwr/nvc0.o -nouveau-y += core/subdev/pwr/nvd0.o -nouveau-y += core/subdev/pwr/gk104.o -nouveau-y += core/subdev/pwr/nv108.o -nouveau-y += core/subdev/therm/base.o -nouveau-y += core/subdev/therm/fan.o -nouveau-y += core/subdev/therm/fannil.o -nouveau-y += core/subdev/therm/fanpwm.o -nouveau-y += core/subdev/therm/fantog.o -nouveau-y += core/subdev/therm/ic.o -nouveau-y += core/subdev/therm/temp.o -nouveau-y += core/subdev/therm/nv40.o -nouveau-y += core/subdev/therm/nv50.o -nouveau-y += core/subdev/therm/nv84.o -nouveau-y += core/subdev/therm/nva3.o -nouveau-y += core/subdev/therm/nvd0.o -nouveau-y += core/subdev/therm/gm107.o -nouveau-y += core/subdev/timer/base.o -nouveau-y += core/subdev/timer/nv04.o -nouveau-y += core/subdev/timer/gk20a.o -nouveau-y += core/subdev/vm/base.o -nouveau-y += core/subdev/vm/nv04.o -nouveau-y += core/subdev/vm/nv41.o -nouveau-y += core/subdev/vm/nv44.o -nouveau-y += core/subdev/vm/nv50.o -nouveau-y += core/subdev/vm/nvc0.o -nouveau-y += core/subdev/volt/base.o -nouveau-y += core/subdev/volt/gpio.o -nouveau-y += core/subdev/volt/nv40.o -nouveau-y += core/subdev/volt/gk20a.o - -nouveau-y += core/engine/falcon.o -nouveau-y += core/engine/xtensa.o -nouveau-y += core/engine/dmaobj/base.o -nouveau-y += core/engine/dmaobj/nv04.o -nouveau-y += core/engine/dmaobj/nv50.o -nouveau-y += core/engine/dmaobj/nvc0.o -nouveau-y += core/engine/dmaobj/nvd0.o -nouveau-y += core/engine/bsp/nv84.o -nouveau-y += core/engine/bsp/nv98.o -nouveau-y += core/engine/bsp/nvc0.o -nouveau-y += core/engine/bsp/nve0.o -nouveau-y += core/engine/copy/nva3.o -nouveau-y += core/engine/copy/nvc0.o -nouveau-y += core/engine/copy/nve0.o -nouveau-y += core/engine/crypt/nv84.o -nouveau-y += core/engine/crypt/nv98.o -nouveau-y += core/engine/device/acpi.o -nouveau-y += core/engine/device/base.o -nouveau-y += core/engine/device/ctrl.o -nouveau-y += core/engine/device/nv04.o -nouveau-y += core/engine/device/nv10.o -nouveau-y += core/engine/device/nv20.o -nouveau-y += core/engine/device/nv30.o -nouveau-y += core/engine/device/nv40.o -nouveau-y += core/engine/device/nv50.o -nouveau-y += core/engine/device/nvc0.o -nouveau-y += core/engine/device/nve0.o -nouveau-y += core/engine/device/gm100.o -nouveau-y += core/engine/disp/base.o -nouveau-y += core/engine/disp/conn.o -nouveau-y += core/engine/disp/outp.o -nouveau-y += core/engine/disp/outpdp.o -nouveau-y += core/engine/disp/nv04.o -nouveau-y += core/engine/disp/nv50.o -nouveau-y += core/engine/disp/nv84.o -nouveau-y += core/engine/disp/nv94.o -nouveau-y += core/engine/disp/nva0.o -nouveau-y += core/engine/disp/nva3.o -nouveau-y += core/engine/disp/nvd0.o -nouveau-y += core/engine/disp/nve0.o -nouveau-y += core/engine/disp/nvf0.o -nouveau-y += core/engine/disp/gm107.o -nouveau-y += core/engine/disp/gm204.o -nouveau-y += core/engine/disp/dacnv50.o -nouveau-y += core/engine/disp/dport.o -nouveau-y += core/engine/disp/hdanva3.o -nouveau-y += core/engine/disp/hdanvd0.o -nouveau-y += core/engine/disp/hdminv84.o -nouveau-y += core/engine/disp/hdminva3.o -nouveau-y += core/engine/disp/hdminvd0.o -nouveau-y += core/engine/disp/hdminve0.o -nouveau-y += core/engine/disp/piornv50.o -nouveau-y += core/engine/disp/sornv50.o -nouveau-y += core/engine/disp/sornv94.o -nouveau-y += core/engine/disp/sornvd0.o -nouveau-y += core/engine/disp/sorgm204.o -nouveau-y += core/engine/disp/vga.o -nouveau-y += core/engine/fifo/base.o -nouveau-y += core/engine/fifo/nv04.o -nouveau-y += core/engine/fifo/nv10.o -nouveau-y += core/engine/fifo/nv17.o -nouveau-y += core/engine/fifo/nv40.o -nouveau-y += core/engine/fifo/nv50.o -nouveau-y += core/engine/fifo/nv84.o -nouveau-y += core/engine/fifo/nvc0.o -nouveau-y += core/engine/fifo/nve0.o -nouveau-y += core/engine/fifo/gk20a.o -nouveau-y += core/engine/fifo/nv108.o -nouveau-y += core/engine/graph/ctxnv40.o -nouveau-y += core/engine/graph/ctxnv50.o -nouveau-y += core/engine/graph/ctxnvc0.o -nouveau-y += core/engine/graph/ctxnvc1.o -nouveau-y += core/engine/graph/ctxnvc4.o -nouveau-y += core/engine/graph/ctxnvc8.o -nouveau-y += core/engine/graph/ctxnvd7.o -nouveau-y += core/engine/graph/ctxnvd9.o -nouveau-y += core/engine/graph/ctxnve4.o -nouveau-y += core/engine/graph/ctxgk20a.o -nouveau-y += core/engine/graph/ctxnvf0.o -nouveau-y += core/engine/graph/ctxgk110b.o -nouveau-y += core/engine/graph/ctxnv108.o -nouveau-y += core/engine/graph/ctxgm107.o -nouveau-y += core/engine/graph/nv04.o -nouveau-y += core/engine/graph/nv10.o -nouveau-y += core/engine/graph/nv20.o -nouveau-y += core/engine/graph/nv25.o -nouveau-y += core/engine/graph/nv2a.o -nouveau-y += core/engine/graph/nv30.o -nouveau-y += core/engine/graph/nv34.o -nouveau-y += core/engine/graph/nv35.o -nouveau-y += core/engine/graph/nv40.o -nouveau-y += core/engine/graph/nv50.o -nouveau-y += core/engine/graph/nvc0.o -nouveau-y += core/engine/graph/nvc1.o -nouveau-y += core/engine/graph/nvc4.o -nouveau-y += core/engine/graph/nvc8.o -nouveau-y += core/engine/graph/nvd7.o -nouveau-y += core/engine/graph/nvd9.o -nouveau-y += core/engine/graph/nve4.o -nouveau-y += core/engine/graph/gk20a.o -nouveau-y += core/engine/graph/nvf0.o -nouveau-y += core/engine/graph/gk110b.o -nouveau-y += core/engine/graph/nv108.o -nouveau-y += core/engine/graph/gm107.o -nouveau-y += core/engine/mpeg/nv31.o -nouveau-y += core/engine/mpeg/nv40.o -nouveau-y += core/engine/mpeg/nv44.o -nouveau-y += core/engine/mpeg/nv50.o -nouveau-y += core/engine/mpeg/nv84.o -nouveau-y += core/engine/perfmon/base.o -nouveau-y += core/engine/perfmon/daemon.o -nouveau-y += core/engine/perfmon/nv40.o -nouveau-y += core/engine/perfmon/nv50.o -nouveau-y += core/engine/perfmon/nv84.o -nouveau-y += core/engine/perfmon/nva3.o -nouveau-y += core/engine/perfmon/nvc0.o -nouveau-y += core/engine/perfmon/nve0.o -nouveau-y += core/engine/perfmon/nvf0.o -nouveau-y += core/engine/ppp/nv98.o -nouveau-y += core/engine/ppp/nvc0.o -nouveau-y += core/engine/software/nv04.o -nouveau-y += core/engine/software/nv10.o -nouveau-y += core/engine/software/nv50.o -nouveau-y += core/engine/software/nvc0.o -nouveau-y += core/engine/vp/nv84.o -nouveau-y += core/engine/vp/nv98.o -nouveau-y += core/engine/vp/nvc0.o -nouveau-y += core/engine/vp/nve0.o - -# nvif -nouveau-y += nvif/object.o -nouveau-y += nvif/client.o -nouveau-y += nvif/device.o -nouveau-y += nvif/notify.o - -# drm/core -nouveau-y += nouveau_drm.o nouveau_chan.o nouveau_dma.o nouveau_fence.o -nouveau-y += nouveau_vga.o nouveau_agp.o -nouveau-y += nouveau_ttm.o nouveau_sgdma.o nouveau_bo.o nouveau_gem.o -nouveau-y += nouveau_prime.o nouveau_abi16.o -nouveau-y += nouveau_nvif.o nouveau_usif.o -nouveau-y += nv04_fence.o nv10_fence.o nv17_fence.o -nouveau-y += nv50_fence.o nv84_fence.o nvc0_fence.o - -# drm/kms -nouveau-y += nouveau_bios.o nouveau_fbcon.o nouveau_display.o -nouveau-y += nouveau_connector.o nouveau_dp.o -nouveau-y += nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o - -# drm/kms/nv04:nv50 -include $(src)/dispnv04/Makefile - -# drm/kms/nv50- -nouveau-y += nv50_display.o - -# drm/pm -nouveau-y += nouveau_hwmon.o nouveau_sysfs.o - -# other random bits -nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o -ifdef CONFIG_X86 -nouveau-$(CONFIG_ACPI) += nouveau_acpi.o -endif -nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o -nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o - -obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o - -# platform driver -obj-$(CONFIG_NOUVEAU_PLATFORM_DRIVER) += nouveau_platform.o diff --git a/drivers/gpu/drm/nouveau/core/core/gpuobj.c b/drivers/gpu/drm/nouveau/core/core/gpuobj.c deleted file mode 100644 index daee87702502..000000000000 --- a/drivers/gpu/drm/nouveau/core/core/gpuobj.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <core/object.h> -#include <core/gpuobj.h> - -#include <subdev/instmem.h> -#include <subdev/bar.h> -#include <subdev/vm.h> - -void -nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj) -{ - int i; - - if (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE) { - for (i = 0; i < gpuobj->size; i += 4) - nv_wo32(gpuobj, i, 0x00000000); - } - - if (gpuobj->node) { - nouveau_mm_free(&nv_gpuobj(gpuobj->parent)->heap, - &gpuobj->node); - } - - if (gpuobj->heap.block_size) - nouveau_mm_fini(&gpuobj->heap); - - nouveau_object_destroy(&gpuobj->base); -} - -int -nouveau_gpuobj_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 pclass, - struct nouveau_object *pargpu, - u32 size, u32 align, u32 flags, - int length, void **pobject) -{ - struct nouveau_instmem *imem = nouveau_instmem(parent); - struct nouveau_bar *bar = nouveau_bar(parent); - struct nouveau_gpuobj *gpuobj; - struct nouveau_mm *heap = NULL; - int ret, i; - u64 addr; - - *pobject = NULL; - - if (pargpu) { - while ((pargpu = nv_pclass(pargpu, NV_GPUOBJ_CLASS))) { - if (nv_gpuobj(pargpu)->heap.block_size) - break; - pargpu = pargpu->parent; - } - - if (unlikely(pargpu == NULL)) { - nv_error(parent, "no gpuobj heap\n"); - return -EINVAL; - } - - addr = nv_gpuobj(pargpu)->addr; - heap = &nv_gpuobj(pargpu)->heap; - atomic_inc(&parent->refcount); - } else { - ret = imem->alloc(imem, parent, size, align, &parent); - pargpu = parent; - if (ret) - return ret; - - addr = nv_memobj(pargpu)->addr; - size = nv_memobj(pargpu)->size; - - if (bar && bar->alloc) { - struct nouveau_instobj *iobj = (void *)parent; - struct nouveau_mem **mem = (void *)(iobj + 1); - struct nouveau_mem *node = *mem; - if (!bar->alloc(bar, parent, node, &pargpu)) { - nouveau_object_ref(NULL, &parent); - parent = pargpu; - } - } - } - - ret = nouveau_object_create_(parent, engine, oclass, pclass | - NV_GPUOBJ_CLASS, length, pobject); - nouveau_object_ref(NULL, &parent); - gpuobj = *pobject; - if (ret) - return ret; - - gpuobj->parent = pargpu; - gpuobj->flags = flags; - gpuobj->addr = addr; - gpuobj->size = size; - - if (heap) { - ret = nouveau_mm_head(heap, 0, 1, size, size, - max(align, (u32)1), &gpuobj->node); - if (ret) - return ret; - - gpuobj->addr += gpuobj->node->offset; - } - - if (gpuobj->flags & NVOBJ_FLAG_HEAP) { - ret = nouveau_mm_init(&gpuobj->heap, 0, gpuobj->size, 1); - if (ret) - return ret; - } - - if (flags & NVOBJ_FLAG_ZERO_ALLOC) { - for (i = 0; i < gpuobj->size; i += 4) - nv_wo32(gpuobj, i, 0x00000000); - } - - return ret; -} - -struct nouveau_gpuobj_class { - struct nouveau_object *pargpu; - u64 size; - u32 align; - u32 flags; -}; - -static int -_nouveau_gpuobj_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_gpuobj_class *args = data; - struct nouveau_gpuobj *object; - int ret; - - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, args->pargpu, - args->size, args->align, args->flags, - &object); - *pobject = nv_object(object); - if (ret) - return ret; - - return 0; -} - -void -_nouveau_gpuobj_dtor(struct nouveau_object *object) -{ - nouveau_gpuobj_destroy(nv_gpuobj(object)); -} - -int -_nouveau_gpuobj_init(struct nouveau_object *object) -{ - return nouveau_gpuobj_init(nv_gpuobj(object)); -} - -int -_nouveau_gpuobj_fini(struct nouveau_object *object, bool suspend) -{ - return nouveau_gpuobj_fini(nv_gpuobj(object), suspend); -} - -u32 -_nouveau_gpuobj_rd32(struct nouveau_object *object, u64 addr) -{ - struct nouveau_gpuobj *gpuobj = nv_gpuobj(object); - struct nouveau_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent); - if (gpuobj->node) - addr += gpuobj->node->offset; - return pfuncs->rd32(gpuobj->parent, addr); -} - -void -_nouveau_gpuobj_wr32(struct nouveau_object *object, u64 addr, u32 data) -{ - struct nouveau_gpuobj *gpuobj = nv_gpuobj(object); - struct nouveau_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent); - if (gpuobj->node) - addr += gpuobj->node->offset; - pfuncs->wr32(gpuobj->parent, addr, data); -} - -static struct nouveau_oclass -_nouveau_gpuobj_oclass = { - .handle = 0x00000000, - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_gpuobj_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, - }, -}; - -int -nouveau_gpuobj_new(struct nouveau_object *parent, struct nouveau_object *pargpu, - u32 size, u32 align, u32 flags, - struct nouveau_gpuobj **pgpuobj) -{ - struct nouveau_object *engine = parent; - struct nouveau_gpuobj_class args = { - .pargpu = pargpu, - .size = size, - .align = align, - .flags = flags, - }; - - if (!nv_iclass(engine, NV_SUBDEV_CLASS)) - engine = engine->engine; - BUG_ON(engine == NULL); - - return nouveau_object_ctor(parent, engine, &_nouveau_gpuobj_oclass, - &args, sizeof(args), - (struct nouveau_object **)pgpuobj); -} - -int -nouveau_gpuobj_map(struct nouveau_gpuobj *gpuobj, u32 access, - struct nouveau_vma *vma) -{ - struct nouveau_bar *bar = nouveau_bar(gpuobj); - int ret = -EINVAL; - - if (bar && bar->umap) { - struct nouveau_instobj *iobj = (void *) - nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS); - struct nouveau_mem **mem = (void *)(iobj + 1); - ret = bar->umap(bar, *mem, access, vma); - } - - return ret; -} - -int -nouveau_gpuobj_map_vm(struct nouveau_gpuobj *gpuobj, struct nouveau_vm *vm, - u32 access, struct nouveau_vma *vma) -{ - struct nouveau_instobj *iobj = (void *) - nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS); - struct nouveau_mem **mem = (void *)(iobj + 1); - int ret; - - ret = nouveau_vm_get(vm, gpuobj->size, 12, access, vma); - if (ret) - return ret; - - nouveau_vm_map(vma, *mem); - return 0; -} - -void -nouveau_gpuobj_unmap(struct nouveau_vma *vma) -{ - if (vma->node) { - nouveau_vm_unmap(vma); - nouveau_vm_put(vma); - } -} - -/* the below is basically only here to support sharing the paged dma object - * for PCI(E)GART on <=nv4x chipsets, and should *not* be expected to work - * anywhere else. - */ - -static void -nouveau_gpudup_dtor(struct nouveau_object *object) -{ - struct nouveau_gpuobj *gpuobj = (void *)object; - nouveau_object_ref(NULL, &gpuobj->parent); - nouveau_object_destroy(&gpuobj->base); -} - -static struct nouveau_oclass -nouveau_gpudup_oclass = { - .handle = NV_GPUOBJ_CLASS, - .ofuncs = &(struct nouveau_ofuncs) { - .dtor = nouveau_gpudup_dtor, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - }, -}; - -int -nouveau_gpuobj_dup(struct nouveau_object *parent, struct nouveau_gpuobj *base, - struct nouveau_gpuobj **pgpuobj) -{ - struct nouveau_gpuobj *gpuobj; - int ret; - - ret = nouveau_object_create(parent, parent->engine, - &nouveau_gpudup_oclass, 0, &gpuobj); - *pgpuobj = gpuobj; - if (ret) - return ret; - - nouveau_object_ref(nv_object(base), &gpuobj->parent); - gpuobj->addr = base->addr; - gpuobj->size = base->size; - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c deleted file mode 100644 index 9261694d0d35..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <engine/falcon.h> -#include <engine/fifo.h> -#include <engine/copy.h> - -#include <core/enum.h> -#include <core/enum.h> - -#include "fuc/nvc0.fuc.h" - -struct nvc0_copy_priv { - struct nouveau_falcon base; -}; - -/******************************************************************************* - * Copy object classes - ******************************************************************************/ - -static struct nouveau_oclass -nvc0_copy0_sclass[] = { - { 0x90b5, &nouveau_object_ofuncs }, - {}, -}; - -static struct nouveau_oclass -nvc0_copy1_sclass[] = { - { 0x90b8, &nouveau_object_ofuncs }, - {}, -}; - -/******************************************************************************* - * PCOPY context - ******************************************************************************/ - -static struct nouveau_ofuncs -nvc0_copy_context_ofuncs = { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, -}; - -static struct nouveau_oclass -nvc0_copy0_cclass = { - .handle = NV_ENGCTX(COPY0, 0xc0), - .ofuncs = &nvc0_copy_context_ofuncs, -}; - -static struct nouveau_oclass -nvc0_copy1_cclass = { - .handle = NV_ENGCTX(COPY1, 0xc0), - .ofuncs = &nvc0_copy_context_ofuncs, -}; - -/******************************************************************************* - * PCOPY engine/subdev functions - ******************************************************************************/ - -static int -nvc0_copy_init(struct nouveau_object *object) -{ - struct nvc0_copy_priv *priv = (void *)object; - int ret; - - ret = nouveau_falcon_init(&priv->base); - if (ret) - return ret; - - nv_wo32(priv, 0x084, nv_engidx(object) - NVDEV_ENGINE_COPY0); - return 0; -} - -static int -nvc0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_copy_priv *priv; - int ret; - - ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true, - "PCE0", "copy0", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000040; - nv_subdev(priv)->intr = nva3_copy_intr; - nv_engine(priv)->cclass = &nvc0_copy0_cclass; - nv_engine(priv)->sclass = nvc0_copy0_sclass; - nv_falcon(priv)->code.data = nvc0_pcopy_code; - nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code); - nv_falcon(priv)->data.data = nvc0_pcopy_data; - nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data); - return 0; -} - -static int -nvc0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_copy_priv *priv; - int ret; - - ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true, - "PCE1", "copy1", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000080; - nv_subdev(priv)->intr = nva3_copy_intr; - nv_engine(priv)->cclass = &nvc0_copy1_cclass; - nv_engine(priv)->sclass = nvc0_copy1_sclass; - nv_falcon(priv)->code.data = nvc0_pcopy_code; - nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code); - nv_falcon(priv)->data.data = nvc0_pcopy_data; - nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data); - return 0; -} - -struct nouveau_oclass -nvc0_copy0_oclass = { - .handle = NV_ENGINE(COPY0, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_copy0_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_copy_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, - }, -}; - -struct nouveau_oclass -nvc0_copy1_oclass = { - .handle = NV_ENGINE(COPY1, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_copy1_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_copy_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, - }, -}; diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c deleted file mode 100644 index c7194b354605..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <core/os.h> -#include <core/enum.h> -#include <core/engctx.h> - -#include <engine/copy.h> - -struct nve0_copy_priv { - struct nouveau_engine base; -}; - -/******************************************************************************* - * Copy object classes - ******************************************************************************/ - -static struct nouveau_oclass -nve0_copy_sclass[] = { - { 0xa0b5, &nouveau_object_ofuncs }, - {}, -}; - -/******************************************************************************* - * PCOPY context - ******************************************************************************/ - -static struct nouveau_ofuncs -nve0_copy_context_ofuncs = { - .ctor = _nouveau_engctx_ctor, - .dtor = _nouveau_engctx_dtor, - .init = _nouveau_engctx_init, - .fini = _nouveau_engctx_fini, - .rd32 = _nouveau_engctx_rd32, - .wr32 = _nouveau_engctx_wr32, -}; - -static struct nouveau_oclass -nve0_copy_cclass = { - .handle = NV_ENGCTX(COPY0, 0xc0), - .ofuncs = &nve0_copy_context_ofuncs, -}; - -/******************************************************************************* - * PCOPY engine/subdev functions - ******************************************************************************/ - -static void -nve0_copy_intr(struct nouveau_subdev *subdev) -{ - const int ce = nv_subidx(nv_object(subdev)) - NVDEV_ENGINE_COPY0; - struct nve0_copy_priv *priv = (void *)subdev; - u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000)); - - if (stat) { - nv_warn(priv, "unhandled intr 0x%08x\n", stat); - nv_wr32(priv, 0x104908 + (ce * 0x1000), stat); - } -} - -static int -nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nve0_copy_priv *priv; - int ret; - - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCE0", "copy0", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000040; - nv_subdev(priv)->intr = nve0_copy_intr; - nv_engine(priv)->cclass = &nve0_copy_cclass; - nv_engine(priv)->sclass = nve0_copy_sclass; - return 0; -} - -static int -nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nve0_copy_priv *priv; - int ret; - - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCE1", "copy1", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000080; - nv_subdev(priv)->intr = nve0_copy_intr; - nv_engine(priv)->cclass = &nve0_copy_cclass; - nv_engine(priv)->sclass = nve0_copy_sclass; - return 0; -} - -static int -nve0_copy2_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nve0_copy_priv *priv; - int ret; - - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCE2", "copy2", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00200000; - nv_subdev(priv)->intr = nve0_copy_intr; - nv_engine(priv)->cclass = &nve0_copy_cclass; - nv_engine(priv)->sclass = nve0_copy_sclass; - return 0; -} - -struct nouveau_oclass -nve0_copy0_oclass = { - .handle = NV_ENGINE(COPY0, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_copy0_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, - }, -}; - -struct nouveau_oclass -nve0_copy1_oclass = { - .handle = NV_ENGINE(COPY1, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_copy1_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, - }, -}; - -struct nouveau_oclass -nve0_copy2_oclass = { - .handle = NV_ENGINE(COPY2, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_copy2_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.h b/drivers/gpu/drm/nouveau/core/engine/device/acpi.h deleted file mode 100644 index cc49f4f568cd..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/acpi.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __NVKM_DEVICE_ACPI_H__ -#define __NVKM_DEVICE_ACPI_H__ - -#include <engine/device.h> - -int nvkm_acpi_init(struct nouveau_device *); -int nvkm_acpi_fini(struct nouveau_device *, bool); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c deleted file mode 100644 index 96f568d1321b..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c +++ /dev/null @@ -1,475 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/fuse.h> -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/mxm.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/pwr.h> -#include <subdev/volt.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/mpeg.h> -#include <engine/vp.h> -#include <engine/crypt.h> -#include <engine/bsp.h> -#include <engine/ppp.h> -#include <engine/copy.h> -#include <engine/disp.h> -#include <engine/perfmon.h> - -int -nv50_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0x50: - device->cname = "G80"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass; - break; - case 0x84: - device->cname = "G84"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x86: - device->cname = "G86"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x92: - device->cname = "G92"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x94: - device->cname = "G94"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x96: - device->cname = "G96"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0x98: - device->cname = "G98"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0xa0: - device->cname = "G200"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0xaa: - device->cname = "MCP77/MCP78"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0xac: - device->cname = "MCP79/MCP7A"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; - break; - case 0xa3: - device->cname = "GT215"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; - break; - case 0xa5: - device->cname = "GT216"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; - break; - case 0xa8: - device->cname = "GT218"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; - break; - case 0xaf: - device->cname = "MCP89"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; - break; - default: - nv_fatal(device, "unknown Tesla chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c deleted file mode 100644 index 72a40f95d048..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/fuse.h> -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/mxm.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/ltc.h> -#include <subdev/ibus.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/pwr.h> -#include <subdev/volt.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/vp.h> -#include <engine/bsp.h> -#include <engine/ppp.h> -#include <engine/copy.h> -#include <engine/disp.h> -#include <engine/perfmon.h> - -int -nvc0_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0xc0: - device->cname = "GF100"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xc4: - device->cname = "GF104"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xc3: - device->cname = "GF106"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xce: - device->cname = "GF114"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xcf: - device->cname = "GF116"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xc1: - device->cname = "GF108"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xc8: - device->cname = "GF110"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xd9: - device->cname = "GF119"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - case 0xd7: - device->cname = "GF117"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; - break; - default: - nv_fatal(device, "unknown Fermi chipset\n"); - return -EINVAL; - } - - return 0; - } diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c deleted file mode 100644 index 674da1f095b2..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/bios.h> -#include <subdev/bus.h> -#include <subdev/gpio.h> -#include <subdev/i2c.h> -#include <subdev/fuse.h> -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/mxm.h> -#include <subdev/devinit.h> -#include <subdev/mc.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/ltc.h> -#include <subdev/ibus.h> -#include <subdev/instmem.h> -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/pwr.h> -#include <subdev/volt.h> - -#include <engine/device.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> -#include <engine/disp.h> -#include <engine/copy.h> -#include <engine/bsp.h> -#include <engine/vp.h> -#include <engine/ppp.h> -#include <engine/perfmon.h> - -int -nve0_identify(struct nouveau_device *device) -{ - switch (device->chipset) { - case 0xe4: - device->cname = "GK104"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = gk104_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; - break; - case 0xe7: - device->cname = "GK107"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; - break; - case 0xe6: - device->cname = "GK106"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = gk104_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; - break; - case 0xea: - device->cname = "GK20A"; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk20a_graph_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; - break; - case 0xf0: - device->cname = "GK110"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; - break; - case 0xf1: - device->cname = "GK110B"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk110b_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; - break; - case 0x108: - device->cname = "GK208"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; - device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; - device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; - device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; - device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - break; - default: - nv_fatal(device, "unknown Kepler chipset\n"); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/priv.h b/drivers/gpu/drm/nouveau/core/engine/device/priv.h deleted file mode 100644 index 035fd5b9cfc3..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/device/priv.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __NVKM_DEVICE_PRIV_H__ -#define __NVKM_DEVICE_PRIV_H__ - -#include <engine/device.h> - -extern struct nouveau_oclass nouveau_control_oclass[]; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h deleted file mode 100644 index 7f08078ee925..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +++ /dev/null @@ -1,252 +0,0 @@ -#ifndef __NV50_DISP_H__ -#define __NV50_DISP_H__ - -#include <core/parent.h> -#include <core/namedb.h> -#include <core/engctx.h> -#include <core/ramht.h> -#include <core/event.h> - -#include <engine/dmaobj.h> - -#include "dport.h" -#include "priv.h" -#include "outp.h" -#include "outpdp.h" - -#define NV50_DISP_MTHD_ struct nouveau_object *object, \ - struct nv50_disp_priv *priv, void *data, u32 size -#define NV50_DISP_MTHD_V0 NV50_DISP_MTHD_, int head -#define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp - -struct nv50_disp_priv { - struct nouveau_disp base; - struct nouveau_oclass *sclass; - - struct work_struct supervisor; - u32 super; - - struct nvkm_event uevent; - - struct { - int nr; - } head; - struct { - int nr; - int (*power)(NV50_DISP_MTHD_V1); - int (*sense)(NV50_DISP_MTHD_V1); - } dac; - struct { - int nr; - int (*power)(NV50_DISP_MTHD_V1); - int (*hda_eld)(NV50_DISP_MTHD_V1); - int (*hdmi)(NV50_DISP_MTHD_V1); - u32 lvdsconf; - void (*magic)(struct nvkm_output *); - } sor; - struct { - int nr; - int (*power)(NV50_DISP_MTHD_V1); - u8 type[3]; - } pior; -}; - -struct nv50_disp_impl { - struct nouveau_disp_impl base; - struct { - const struct nv50_disp_mthd_chan *core; - const struct nv50_disp_mthd_chan *base; - const struct nv50_disp_mthd_chan *ovly; - int prev; - } mthd; - struct { - int (*scanoutpos)(NV50_DISP_MTHD_V0); - } head; -}; - -int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0); -int nv50_disp_main_mthd(struct nouveau_object *, u32, void *, u32); - -int nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0); - -int nv50_dac_power(NV50_DISP_MTHD_V1); -int nv50_dac_sense(NV50_DISP_MTHD_V1); - -int nva3_hda_eld(NV50_DISP_MTHD_V1); -int nvd0_hda_eld(NV50_DISP_MTHD_V1); - -int nv84_hdmi_ctrl(NV50_DISP_MTHD_V1); -int nva3_hdmi_ctrl(NV50_DISP_MTHD_V1); -int nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1); -int nve0_hdmi_ctrl(NV50_DISP_MTHD_V1); - -int nv50_sor_power(NV50_DISP_MTHD_V1); - -int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16, - u32, struct dcb_output *); -int nv94_sor_dp_train_fini(struct nv50_disp_priv *, int, int, int, u16, u16, - u32, struct dcb_output *); -int nv94_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32, - struct dcb_output *); -int nv94_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, - struct dcb_output *); -int nv94_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, - struct dcb_output *); - -int nvd0_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32, - struct dcb_output *); -int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, - struct dcb_output *); -int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, - struct dcb_output *); - -int nv50_pior_power(NV50_DISP_MTHD_V1); - -struct nv50_disp_base { - struct nouveau_parent base; - struct nouveau_ramht *ramht; - u32 chan; -}; - -struct nv50_disp_chan_impl { - struct nouveau_ofuncs base; - int chid; - int (*attach)(struct nouveau_object *, struct nouveau_object *, u32); - void (*detach)(struct nouveau_object *, int); -}; - -struct nv50_disp_chan { - struct nouveau_namedb base; - int chid; -}; - -int nv50_disp_chan_ntfy(struct nouveau_object *, u32, struct nvkm_event **); -int nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *); -u32 nv50_disp_chan_rd32(struct nouveau_object *, u64); -void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32); -extern const struct nvkm_event_func nv50_disp_chan_uevent; -int nv50_disp_chan_uevent_ctor(struct nouveau_object *, void *, u32, - struct nvkm_notify *); -void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int); - -extern const struct nvkm_event_func nvd0_disp_chan_uevent; - -#define nv50_disp_chan_init(a) \ - nouveau_namedb_init(&(a)->base) -#define nv50_disp_chan_fini(a,b) \ - nouveau_namedb_fini(&(a)->base, (b)) - -struct nv50_disp_dmac { - struct nv50_disp_chan base; - struct nouveau_dmaobj *pushdma; - u32 push; -}; - -void nv50_disp_dmac_dtor(struct nouveau_object *); - -struct nv50_disp_pioc { - struct nv50_disp_chan base; -}; - -void nv50_disp_pioc_dtor(struct nouveau_object *); - -struct nv50_disp_mthd_list { - u32 mthd; - u32 addr; - struct { - u32 mthd; - u32 addr; - const char *name; - } data[]; -}; - -struct nv50_disp_mthd_chan { - const char *name; - u32 addr; - struct { - const char *name; - int nr; - const struct nv50_disp_mthd_list *mthd; - } data[]; -}; - -extern struct nv50_disp_chan_impl nv50_disp_core_ofuncs; -int nv50_disp_core_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base; -extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor; -extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior; -extern struct nv50_disp_chan_impl nv50_disp_base_ofuncs; -int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image; -extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs; -int nv50_disp_ovly_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base; -extern struct nv50_disp_chan_impl nv50_disp_oimm_ofuncs; -int nv50_disp_oimm_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs; -int nv50_disp_curs_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -extern struct nouveau_ofuncs nv50_disp_main_ofuncs; -int nv50_disp_main_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nv50_disp_main_dtor(struct nouveau_object *); -extern struct nouveau_omthds nv50_disp_main_omthds[]; -extern struct nouveau_oclass nv50_disp_cclass; -void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head, - const struct nv50_disp_mthd_chan *); -void nv50_disp_intr_supervisor(struct work_struct *); -void nv50_disp_intr(struct nouveau_subdev *); -extern const struct nvkm_event_func nv50_disp_vblank_func; - -extern const struct nv50_disp_mthd_chan nv84_disp_core_mthd_chan; -extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_dac; -extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_head; -extern const struct nv50_disp_mthd_chan nv84_disp_base_mthd_chan; -extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan; - -extern const struct nv50_disp_mthd_chan nv94_disp_core_mthd_chan; - -extern struct nv50_disp_chan_impl nvd0_disp_core_ofuncs; -extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_base; -extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_dac; -extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_sor; -extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_pior; -extern struct nv50_disp_chan_impl nvd0_disp_base_ofuncs; -extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs; -extern const struct nv50_disp_mthd_chan nvd0_disp_base_mthd_chan; -extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs; -extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs; -extern struct nouveau_ofuncs nvd0_disp_main_ofuncs; -extern struct nouveau_oclass nvd0_disp_cclass; -void nvd0_disp_intr_supervisor(struct work_struct *); -void nvd0_disp_intr(struct nouveau_subdev *); -extern const struct nvkm_event_func nvd0_disp_vblank_func; - -extern const struct nv50_disp_mthd_chan nve0_disp_core_mthd_chan; -extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan; - -extern struct nvkm_output_dp_impl nv50_pior_dp_impl; -extern struct nouveau_oclass *nv50_disp_outp_sclass[]; - -extern struct nvkm_output_dp_impl nv94_sor_dp_impl; -int nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int); -extern struct nouveau_oclass *nv94_disp_outp_sclass[]; - -extern struct nvkm_output_dp_impl nvd0_sor_dp_impl; -int nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool); -extern struct nouveau_oclass *nvd0_disp_outp_sclass[]; - -void gm204_sor_magic(struct nvkm_output *outp); -extern struct nvkm_output_dp_impl gm204_sor_dp_impl; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/priv.h b/drivers/gpu/drm/nouveau/core/engine/disp/priv.h deleted file mode 100644 index 6a0511d54ce6..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/disp/priv.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef __NVKM_DISP_PRIV_H__ -#define __NVKM_DISP_PRIV_H__ - -#include <subdev/bios.h> -#include <subdev/bios/dcb.h> -#include <subdev/bios/conn.h> - -#include <engine/disp.h> - -struct nouveau_disp_impl { - struct nouveau_oclass base; - struct nouveau_oclass **outp; - struct nouveau_oclass **conn; - const struct nvkm_event_func *vblank; -}; - -#define nouveau_disp_create(p,e,c,h,i,x,d) \ - nouveau_disp_create_((p), (e), (c), (h), (i), (x), \ - sizeof(**d), (void **)d) -#define nouveau_disp_destroy(d) ({ \ - struct nouveau_disp *disp = (d); \ - _nouveau_disp_dtor(nv_object(disp)); \ -}) -#define nouveau_disp_init(d) ({ \ - struct nouveau_disp *disp = (d); \ - _nouveau_disp_init(nv_object(disp)); \ -}) -#define nouveau_disp_fini(d,s) ({ \ - struct nouveau_disp *disp = (d); \ - _nouveau_disp_fini(nv_object(disp), (s)); \ -}) - -int nouveau_disp_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int heads, - const char *, const char *, int, void **); -void _nouveau_disp_dtor(struct nouveau_object *); -int _nouveau_disp_init(struct nouveau_object *); -int _nouveau_disp_fini(struct nouveau_object *, bool); - -extern struct nouveau_oclass *nvkm_output_oclass; -extern struct nouveau_oclass *nvkm_connector_oclass; - -int nouveau_disp_vblank_ctor(struct nouveau_object *, void *data, u32 size, - struct nvkm_notify *); -void nouveau_disp_vblank(struct nouveau_disp *, int head); -int nouveau_disp_ntfy(struct nouveau_object *, u32, struct nvkm_event **); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h b/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h deleted file mode 100644 index 36f743866937..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __NVKM_DMAOBJ_PRIV_H__ -#define __NVKM_DMAOBJ_PRIV_H__ - -#include <engine/dmaobj.h> - -#define nvkm_dmaobj_create(p,e,c,pa,sa,d) \ - nvkm_dmaobj_create_((p), (e), (c), (pa), (sa), sizeof(**d), (void **)d) - -int nvkm_dmaobj_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void **, u32 *, - int, void **); -#define _nvkm_dmaobj_dtor nouveau_object_destroy -#define _nvkm_dmaobj_init nouveau_object_init -#define _nvkm_dmaobj_fini nouveau_object_fini - -int _nvkm_dmaeng_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -#define _nvkm_dmaeng_dtor _nouveau_engine_dtor -#define _nvkm_dmaeng_init _nouveau_engine_init -#define _nvkm_dmaeng_fini _nouveau_engine_fini - -struct nvkm_dmaeng_impl { - struct nouveau_oclass base; - struct nouveau_oclass *sclass; - int (*bind)(struct nouveau_dmaobj *, struct nouveau_object *, - struct nouveau_gpuobj **); -}; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h deleted file mode 100644 index 3a9ceb315c20..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef __NV50_FIFO_H__ -#define __NV50_FIFO_H__ - -struct nv50_fifo_priv { - struct nouveau_fifo base; - struct nouveau_gpuobj *playlist[2]; - int cur_playlist; -}; - -struct nv50_fifo_base { - struct nouveau_fifo_base base; - struct nouveau_gpuobj *ramfc; - struct nouveau_gpuobj *cache; - struct nouveau_gpuobj *eng; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *vm; -}; - -struct nv50_fifo_chan { - struct nouveau_fifo_chan base; - u32 subc[8]; - struct nouveau_ramht *ramht; -}; - -void nv50_fifo_playlist_update(struct nv50_fifo_priv *); - -void nv50_fifo_object_detach(struct nouveau_object *, int); -void nv50_fifo_chan_dtor(struct nouveau_object *); -int nv50_fifo_chan_fini(struct nouveau_object *, bool); - -void nv50_fifo_context_dtor(struct nouveau_object *); - -void nv50_fifo_dtor(struct nouveau_object *); -int nv50_fifo_init(struct nouveau_object *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h deleted file mode 100644 index e96b32bb1bbc..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __NVKM_FIFO_NVE0_H__ -#define __NVKM_FIFO_NVE0_H__ - -#include <engine/fifo.h> - -int nve0_fifo_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nve0_fifo_dtor(struct nouveau_object *); -int nve0_fifo_init(struct nouveau_object *); -int nve0_fifo_fini(struct nouveau_object *, bool); - -struct nve0_fifo_impl { - struct nouveau_oclass base; - u32 channels; -}; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h deleted file mode 100644 index c776cd715e33..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h +++ /dev/null @@ -1,202 +0,0 @@ -#ifndef __NVKM_GRCTX_NVC0_H__ -#define __NVKM_GRCTX_NVC0_H__ - -#include "nvc0.h" - -struct nvc0_grctx { - struct nvc0_graph_priv *priv; - struct nvc0_graph_data *data; - struct nvc0_graph_mmio *mmio; - int buffer_nr; - u64 buffer[4]; - u64 addr; -}; - -int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access); -void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int); - -#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d)) -#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e)) -#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1) -#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1) - -struct nvc0_grctx_oclass { - struct nouveau_oclass base; - /* main context generation function */ - void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *); - /* context-specific modify-on-first-load list generation function */ - void (*unkn)(struct nvc0_graph_priv *); - /* mmio context data */ - const struct nvc0_graph_pack *hub; - const struct nvc0_graph_pack *gpc; - const struct nvc0_graph_pack *zcull; - const struct nvc0_graph_pack *tpc; - const struct nvc0_graph_pack *ppc; - /* indirect context data, generated with icmds/mthds */ - const struct nvc0_graph_pack *icmd; - const struct nvc0_graph_pack *mthd; - /* bundle circular buffer */ - void (*bundle)(struct nvc0_grctx *); - u32 bundle_size; - u32 bundle_min_gpm_fifo_depth; - u32 bundle_token_limit; - /* pagepool */ - void (*pagepool)(struct nvc0_grctx *); - u32 pagepool_size; - /* attribute(/alpha) circular buffer */ - void (*attrib)(struct nvc0_grctx *); - u32 attrib_nr_max; - u32 attrib_nr; - u32 alpha_nr_max; - u32 alpha_nr; -}; - -static inline const struct nvc0_grctx_oclass * -nvc0_grctx_impl(struct nvc0_graph_priv *priv) -{ - return (void *)nv_engine(priv)->cclass; -} - -extern struct nouveau_oclass *nvc0_grctx_oclass; -int nvc0_grctx_generate(struct nvc0_graph_priv *); -void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); -void nvc0_grctx_generate_bundle(struct nvc0_grctx *); -void nvc0_grctx_generate_pagepool(struct nvc0_grctx *); -void nvc0_grctx_generate_attrib(struct nvc0_grctx *); -void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *); -void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *); -void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *); -void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *); -void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *); -void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *); - -extern struct nouveau_oclass *nvc1_grctx_oclass; -void nvc1_grctx_generate_attrib(struct nvc0_grctx *); -void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *); - -extern struct nouveau_oclass *nvc4_grctx_oclass; -extern struct nouveau_oclass *nvc8_grctx_oclass; - -extern struct nouveau_oclass *nvd7_grctx_oclass; -void nvd7_grctx_generate_attrib(struct nvc0_grctx *); - -extern struct nouveau_oclass *nvd9_grctx_oclass; - -extern struct nouveau_oclass *nve4_grctx_oclass; -extern struct nouveau_oclass *gk20a_grctx_oclass; -void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); -void nve4_grctx_generate_bundle(struct nvc0_grctx *); -void nve4_grctx_generate_pagepool(struct nvc0_grctx *); -void nve4_grctx_generate_unkn(struct nvc0_graph_priv *); -void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *); - -extern struct nouveau_oclass *nvf0_grctx_oclass; -extern struct nouveau_oclass *gk110b_grctx_oclass; -extern struct nouveau_oclass *nv108_grctx_oclass; -extern struct nouveau_oclass *gm107_grctx_oclass; - -/* context init value lists */ - -extern const struct nvc0_graph_pack nvc0_grctx_pack_icmd[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_mthd[]; -extern const struct nvc0_graph_init nvc0_grctx_init_902d_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_9039_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_90c0_0[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_hub[]; -extern const struct nvc0_graph_init nvc0_grctx_init_main_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_fe_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_pri_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_memfmt_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_scc_0[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_gpc[]; -extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_prop_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvc0_grctx_init_zcull_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_crstr_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_gpm_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_gcc_0[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[]; - -extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[]; -extern const struct nvc0_graph_init nvc0_grctx_init_pe_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_wwdx_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_mpc_0[]; -extern const struct nvc0_graph_init nvc0_grctx_init_tpccs_0[]; - -extern const struct nvc0_graph_init nvc4_grctx_init_tex_0[]; -extern const struct nvc0_graph_init nvc4_grctx_init_l1c_0[]; -extern const struct nvc0_graph_init nvc4_grctx_init_sm_0[]; - -extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[]; - -extern const struct nvc0_graph_init nvc1_grctx_init_gpm_0[]; - -extern const struct nvc0_graph_init nvc1_grctx_init_pe_0[]; -extern const struct nvc0_graph_init nvc1_grctx_init_wwdx_0[]; -extern const struct nvc0_graph_init nvc1_grctx_init_tpccs_0[]; - -extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[]; -extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[]; - -extern const struct nvc0_graph_pack nvd9_grctx_pack_icmd[]; - -extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[]; - -extern const struct nvc0_graph_init nvd9_grctx_init_fe_0[]; -extern const struct nvc0_graph_init nvd9_grctx_init_be_0[]; - -extern const struct nvc0_graph_init nvd9_grctx_init_prop_0[]; -extern const struct nvc0_graph_init nvd9_grctx_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvd9_grctx_init_crstr_0[]; - -extern const struct nvc0_graph_init nvd9_grctx_init_sm_0[]; - -extern const struct nvc0_graph_init nvd7_grctx_init_pe_0[]; - -extern const struct nvc0_graph_init nvd7_grctx_init_wwdx_0[]; - -extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[]; -extern const struct nvc0_graph_init nve4_grctx_init_ds_0[]; -extern const struct nvc0_graph_init nve4_grctx_init_scc_0[]; - -extern const struct nvc0_graph_init nve4_grctx_init_gpm_0[]; - -extern const struct nvc0_graph_init nve4_grctx_init_pes_0[]; - -extern const struct nvc0_graph_pack nve4_grctx_pack_hub[]; -extern const struct nvc0_graph_pack nve4_grctx_pack_gpc[]; -extern const struct nvc0_graph_pack nve4_grctx_pack_tpc[]; -extern const struct nvc0_graph_pack nve4_grctx_pack_ppc[]; -extern const struct nvc0_graph_pack nve4_grctx_pack_icmd[]; -extern const struct nvc0_graph_init nve4_grctx_init_a097_0[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_icmd[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_hub[]; -extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[]; -extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_gpc[]; -extern const struct nvc0_graph_init nvf0_grctx_init_gpc_unk_2[]; - -extern const struct nvc0_graph_init nvf0_grctx_init_tex_0[]; -extern const struct nvc0_graph_init nvf0_grctx_init_mpc_0[]; -extern const struct nvc0_graph_init nvf0_grctx_init_l1c_0[]; - -extern const struct nvc0_graph_pack nvf0_grctx_pack_ppc[]; - -extern const struct nvc0_graph_init nv108_grctx_init_rstr2d_0[]; - -extern const struct nvc0_graph_init nv108_grctx_init_prop_0[]; -extern const struct nvc0_graph_init nv108_grctx_init_crstr_0[]; - - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h deleted file mode 100644 index 2bea7313e03f..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __NV20_GRAPH_H__ -#define __NV20_GRAPH_H__ - -#include <core/enum.h> - -#include <engine/graph.h> -#include <engine/fifo.h> - -struct nv20_graph_priv { - struct nouveau_graph base; - struct nouveau_gpuobj *ctxtab; -}; - -struct nv20_graph_chan { - struct nouveau_graph_chan base; - int chid; -}; - -extern struct nouveau_oclass nv25_graph_sclass[]; -int nv20_graph_context_init(struct nouveau_object *); -int nv20_graph_context_fini(struct nouveau_object *, bool); - -void nv20_graph_tile_prog(struct nouveau_engine *, int); -void nv20_graph_intr(struct nouveau_subdev *); - -void nv20_graph_dtor(struct nouveau_object *); -int nv20_graph_init(struct nouveau_object *); - -int nv30_graph_init(struct nouveau_object *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h deleted file mode 100644 index 0505fb419bde..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __NV50_GRAPH_H__ -#define __NV50_GRAPH_H__ - -int nv50_grctx_init(struct nouveau_device *, u32 *size); -void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h deleted file mode 100644 index 7ed9e89c3435..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#ifndef __NVC0_GRAPH_H__ -#define __NVC0_GRAPH_H__ - -#include <core/client.h> -#include <core/handle.h> -#include <core/gpuobj.h> -#include <core/option.h> - -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <subdev/fb.h> -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/timer.h> -#include <subdev/mc.h> -#include <subdev/ltc.h> - -#include <engine/fifo.h> -#include <engine/graph.h> - -#include "fuc/os.h" - -#define GPC_MAX 32 -#define TPC_MAX (GPC_MAX * 8) - -#define ROP_BCAST(r) (0x408800 + (r)) -#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r)) -#define GPC_BCAST(r) (0x418000 + (r)) -#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r)) -#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r)) -#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r)) - -struct nvc0_graph_data { - u32 size; - u32 align; - u32 access; -}; - -struct nvc0_graph_mmio { - u32 addr; - u32 data; - u32 shift; - int buffer; -}; - -struct nvc0_graph_fuc { - u32 *data; - u32 size; -}; - -struct nvc0_graph_zbc_color { - u32 format; - u32 ds[4]; - u32 l2[4]; -}; - -struct nvc0_graph_zbc_depth { - u32 format; - u32 ds; - u32 l2; -}; - -struct nvc0_graph_priv { - struct nouveau_graph base; - - struct nvc0_graph_fuc fuc409c; - struct nvc0_graph_fuc fuc409d; - struct nvc0_graph_fuc fuc41ac; - struct nvc0_graph_fuc fuc41ad; - bool firmware; - - struct nvc0_graph_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT]; - struct nvc0_graph_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT]; - - u8 rop_nr; - u8 gpc_nr; - u8 tpc_nr[GPC_MAX]; - u8 tpc_total; - u8 ppc_nr[GPC_MAX]; - u8 ppc_tpc_nr[GPC_MAX][4]; - - struct nouveau_gpuobj *unk4188b4; - struct nouveau_gpuobj *unk4188b8; - - struct nvc0_graph_data mmio_data[4]; - struct nvc0_graph_mmio mmio_list[4096/8]; - u32 size; - u32 *data; - - u8 magic_not_rop_nr; -}; - -struct nvc0_graph_chan { - struct nouveau_graph_chan base; - - struct nouveau_gpuobj *mmio; - struct nouveau_vma mmio_vma; - int mmio_nr; - struct { - struct nouveau_gpuobj *mem; - struct nouveau_vma vma; - } data[4]; -}; - -int nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nvc0_graph_context_dtor(struct nouveau_object *); - -void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *); - -u64 nvc0_graph_units(struct nouveau_graph *); -int nvc0_graph_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *data, u32 size, - struct nouveau_object **); -void nvc0_graph_dtor(struct nouveau_object *); -int nvc0_graph_init(struct nouveau_object *); -void nvc0_graph_zbc_init(struct nvc0_graph_priv *); - -int nve4_graph_fini(struct nouveau_object *, bool); -int nve4_graph_init(struct nouveau_object *); - -int nvf0_graph_fini(struct nouveau_object *, bool); - -extern struct nouveau_ofuncs nvc0_fermi_ofuncs; - -extern struct nouveau_oclass nvc0_graph_sclass[]; -extern struct nouveau_omthds nvc0_graph_9097_omthds[]; -extern struct nouveau_omthds nvc0_graph_90c0_omthds[]; -extern struct nouveau_oclass nvc8_graph_sclass[]; -extern struct nouveau_oclass nvf0_graph_sclass[]; - -struct nvc0_graph_init { - u32 addr; - u8 count; - u8 pitch; - u32 data; -}; - -struct nvc0_graph_pack { - const struct nvc0_graph_init *init; - u32 type; -}; - -#define pack_for_each_init(init, pack, head) \ - for (pack = head; pack && pack->init; pack++) \ - for (init = pack->init; init && init->count; init++) - -struct nvc0_graph_ucode { - struct nvc0_graph_fuc code; - struct nvc0_graph_fuc data; -}; - -extern struct nvc0_graph_ucode nvc0_graph_fecs_ucode; -extern struct nvc0_graph_ucode nvc0_graph_gpccs_ucode; - -extern struct nvc0_graph_ucode nvf0_graph_fecs_ucode; -extern struct nvc0_graph_ucode nvf0_graph_gpccs_ucode; - -struct nvc0_graph_oclass { - struct nouveau_oclass base; - struct nouveau_oclass **cclass; - struct nouveau_oclass *sclass; - const struct nvc0_graph_pack *mmio; - struct { - struct nvc0_graph_ucode *ucode; - } fecs; - struct { - struct nvc0_graph_ucode *ucode; - } gpccs; - int ppc_nr; -}; - -void nvc0_graph_mmio(struct nvc0_graph_priv *, const struct nvc0_graph_pack *); -void nvc0_graph_icmd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *); -void nvc0_graph_mthd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *); -int nvc0_graph_init_ctxctl(struct nvc0_graph_priv *); - -/* register init value lists */ - -extern const struct nvc0_graph_init nvc0_graph_init_main_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_fe_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_pri_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_rstr2d_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_pd_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_ds_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_scc_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_prop_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_setup_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_crstr_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_setup_1[]; -extern const struct nvc0_graph_init nvc0_graph_init_zcull_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_gpm_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvc0_graph_init_gcc_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_tpccs_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_tex_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_pe_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_l1c_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_wwdx_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_tpccs_1[]; -extern const struct nvc0_graph_init nvc0_graph_init_mpc_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_be_0[]; -extern const struct nvc0_graph_init nvc0_graph_init_fe_1[]; -extern const struct nvc0_graph_init nvc0_graph_init_pe_1[]; - -extern const struct nvc0_graph_init nvc4_graph_init_ds_0[]; -extern const struct nvc0_graph_init nvc4_graph_init_tex_0[]; -extern const struct nvc0_graph_init nvc4_graph_init_sm_0[]; - -extern const struct nvc0_graph_init nvc1_graph_init_gpc_unk_0[]; -extern const struct nvc0_graph_init nvc1_graph_init_setup_1[]; - -extern const struct nvc0_graph_init nvd9_graph_init_pd_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_ds_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_prop_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_gpm_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvd9_graph_init_tex_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_sm_0[]; -extern const struct nvc0_graph_init nvd9_graph_init_fe_1[]; - -extern const struct nvc0_graph_init nvd7_graph_init_pes_0[]; -extern const struct nvc0_graph_init nvd7_graph_init_wwdx_0[]; -extern const struct nvc0_graph_init nvd7_graph_init_cbm_0[]; - -extern const struct nvc0_graph_init nve4_graph_init_main_0[]; -extern const struct nvc0_graph_init nve4_graph_init_tpccs_0[]; -extern const struct nvc0_graph_init nve4_graph_init_pe_0[]; -extern const struct nvc0_graph_init nve4_graph_init_be_0[]; -extern const struct nvc0_graph_pack nve4_graph_pack_mmio[]; - -extern const struct nvc0_graph_init nvf0_graph_init_fe_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_ds_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_sked_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_cwd_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_gpc_unk_1[]; -extern const struct nvc0_graph_init nvf0_graph_init_tex_0[]; -extern const struct nvc0_graph_init nvf0_graph_init_sm_0[]; - -extern const struct nvc0_graph_init nv108_graph_init_gpc_unk_0[]; - - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h deleted file mode 100644 index 1b5792d1df14..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __NVKM_PM_NV40_H__ -#define __NVKM_PM_NV40_H__ - -#include "priv.h" - -struct nv40_perfmon_oclass { - struct nouveau_oclass base; - const struct nouveau_specdom *doms; -}; - -struct nv40_perfmon_priv { - struct nouveau_perfmon base; - u32 sequence; -}; - -int nv40_perfmon_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *data, u32 size, - struct nouveau_object **pobject); - -struct nv40_perfmon_cntr { - struct nouveau_perfctr base; -}; - -extern const struct nouveau_funcdom nv40_perfctr_func; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c deleted file mode 100644 index 94217691fe67..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nv40.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nv50_perfmon[] = { - { 0x040, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x100, (const struct nouveau_specsig[]) { - { 0xc8, "gr_idle" }, - {} - }, &nv40_perfctr_func }, - { 0x100, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x020, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x040, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - {} -}; - -struct nouveau_oclass * -nv50_perfmon_oclass = &(struct nv40_perfmon_oclass) { - .base.handle = NV_ENGINE(PERFMON, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = _nouveau_perfmon_fini, - }, - .doms = nv50_perfmon, -}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c deleted file mode 100644 index 6197ebdeb648..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nv40.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nva3_perfmon[] = { - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - {} -}; - -static int -nva3_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **object) -{ - int ret = nv40_perfmon_ctor(parent, engine, oclass, data, size, object); - if (ret == 0) { - struct nv40_perfmon_priv *priv = (void *)*object; - ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, - nva3_perfmon_pwr); - if (ret) - return ret; - - priv->base.last = 3; - } - return ret; -} - -struct nouveau_oclass * -nva3_perfmon_oclass = &(struct nv40_perfmon_oclass) { - .base.handle = NV_ENGINE(PERFMON, 0xa3), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = _nouveau_perfmon_fini, - }, - .doms = nva3_perfmon, -}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h deleted file mode 100644 index f66bca484263..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __NVKM_PM_NVC0_H__ -#define __NVKM_PM_NVC0_H__ - -#include "priv.h" - -struct nvc0_perfmon_priv { - struct nouveau_perfmon base; -}; - -struct nvc0_perfmon_cntr { - struct nouveau_perfctr base; -}; - -extern const struct nouveau_funcdom nvc0_perfctr_func; -int nvc0_perfmon_fini(struct nouveau_object *, bool); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c deleted file mode 100644 index 71d718c12075..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nve0_perfmon_hub[] = { - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub00_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x40, (const struct nouveau_specsig[]) { - { 0x27, "hub01_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub02_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub03_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x40, (const struct nouveau_specsig[]) { - { 0x03, "host_mmio_rd" }, - { 0x27, "hub04_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub05_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0xc0, (const struct nouveau_specsig[]) { - { 0x74, "host_fb_rd3x" }, - { 0x75, "host_fb_rd3x_2" }, - { 0xa7, "hub06_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub07_user_0" }, - {} - }, &nvc0_perfctr_func }, - {} -}; - -static const struct nouveau_specdom -nve0_perfmon_gpc[] = { - { 0xe0, (const struct nouveau_specsig[]) { - { 0xc7, "gpc00_user_0" }, - {} - }, &nvc0_perfctr_func }, - {} -}; - -static const struct nouveau_specdom -nve0_perfmon_part[] = { - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "part00_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "part01_user_0" }, - {} - }, &nvc0_perfctr_func }, - {} -}; - -static int -nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_perfmon_priv *priv; - u32 mask; - int ret; - - ret = nouveau_perfmon_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - /* PDAEMON */ - ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, - nve0_perfmon_pwr); - if (ret) - return ret; - - /* HUB */ - ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, - nve0_perfmon_hub); - if (ret) - return ret; - - /* GPC */ - mask = (1 << nv_rd32(priv, 0x022430)) - 1; - mask &= ~nv_rd32(priv, 0x022504); - mask &= ~nv_rd32(priv, 0x022584); - - ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000, - 0x1000, 0x200, nve0_perfmon_gpc); - if (ret) - return ret; - - /* PART */ - mask = (1 << nv_rd32(priv, 0x022438)) - 1; - mask &= ~nv_rd32(priv, 0x022548); - mask &= ~nv_rd32(priv, 0x0225c8); - - ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000, - 0x1000, 0x200, nve0_perfmon_part); - if (ret) - return ret; - - nv_engine(priv)->cclass = &nouveau_perfmon_cclass; - nv_engine(priv)->sclass = nouveau_perfmon_sclass; - priv->base.last = 7; - return 0; -} - -struct nouveau_oclass -nve0_perfmon_oclass = { - .handle = NV_ENGINE(PERFMON, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = nvc0_perfmon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c deleted file mode 100644 index 47256f78a895..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static int -nvf0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_perfmon_priv *priv; - int ret; - - ret = nouveau_perfmon_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, - nve0_perfmon_pwr); - if (ret) - return ret; - - nv_engine(priv)->cclass = &nouveau_perfmon_cclass; - nv_engine(priv)->sclass = nouveau_perfmon_sclass; - return 0; -} - -struct nouveau_oclass -nvf0_perfmon_oclass = { - .handle = NV_ENGINE(PERFMON, 0xf0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvf0_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = nvc0_perfmon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h b/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h deleted file mode 100644 index 0ac8714fe0ba..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef __NVKM_PERFMON_PRIV_H__ -#define __NVKM_PERFMON_PRIV_H__ - -#include <engine/perfmon.h> - -struct nouveau_perfctr { - struct nouveau_object base; - struct list_head head; - struct nouveau_perfsig *signal[4]; - int slot; - u32 logic_op; - u32 clk; - u32 ctr; -}; - -extern struct nouveau_oclass nouveau_perfmon_sclass[]; - -struct nouveau_perfctx { - struct nouveau_engctx base; -}; - -extern struct nouveau_oclass nouveau_perfmon_cclass; - -struct nouveau_specsig { - u8 signal; - const char *name; -}; - -struct nouveau_perfsig { - const char *name; -}; - -struct nouveau_perfdom; -struct nouveau_perfctr * -nouveau_perfsig_wrap(struct nouveau_perfmon *, const char *, - struct nouveau_perfdom **); - -struct nouveau_specdom { - u16 signal_nr; - const struct nouveau_specsig *signal; - const struct nouveau_funcdom *func; -}; - -extern const struct nouveau_specdom nva3_perfmon_pwr[]; -extern const struct nouveau_specdom nvc0_perfmon_pwr[]; -extern const struct nouveau_specdom nve0_perfmon_pwr[]; - -struct nouveau_perfdom { - struct list_head head; - struct list_head list; - const struct nouveau_funcdom *func; - char name[32]; - u32 addr; - u8 quad; - u32 signal_nr; - struct nouveau_perfsig signal[]; -}; - -struct nouveau_funcdom { - void (*init)(struct nouveau_perfmon *, struct nouveau_perfdom *, - struct nouveau_perfctr *); - void (*read)(struct nouveau_perfmon *, struct nouveau_perfdom *, - struct nouveau_perfctr *); - void (*next)(struct nouveau_perfmon *, struct nouveau_perfdom *); -}; - -int nouveau_perfdom_new(struct nouveau_perfmon *, const char *, u32, - u32, u32, u32, const struct nouveau_specdom *); - -#define nouveau_perfmon_create(p,e,o,d) \ - nouveau_perfmon_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_perfmon_dtor(p) ({ \ - struct nouveau_perfmon *c = (p); \ - _nouveau_perfmon_dtor(nv_object(c)); \ -}) -#define nouveau_perfmon_init(p) ({ \ - struct nouveau_perfmon *c = (p); \ - _nouveau_perfmon_init(nv_object(c)); \ -}) -#define nouveau_perfmon_fini(p,s) ({ \ - struct nouveau_perfmon *c = (p); \ - _nouveau_perfmon_fini(nv_object(c), (s)); \ -}) - -int nouveau_perfmon_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_perfmon_dtor(struct nouveau_object *); -int _nouveau_perfmon_init(struct nouveau_object *); -int _nouveau_perfmon_fini(struct nouveau_object *, bool); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.h b/drivers/gpu/drm/nouveau/core/engine/software/nv50.h deleted file mode 100644 index 41542e725b4b..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef __NVKM_SW_NV50_H__ -#define __NVKM_SW_NV50_H__ - -#include <engine/software.h> - -struct nv50_software_oclass { - struct nouveau_oclass base; - struct nouveau_oclass *cclass; - struct nouveau_oclass *sclass; -}; - -struct nv50_software_priv { - struct nouveau_software base; -}; - -int nv50_software_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); - -struct nv50_software_cclass { - struct nouveau_oclass base; - int (*vblank)(struct nvkm_notify *); -}; - -struct nv50_software_chan { - struct nouveau_software_chan base; - struct { - struct nvkm_notify notify[4]; - u32 channel; - u32 ctxdma; - u64 offset; - u32 value; - } vblank; -}; - -int nv50_software_context_ctor(struct nouveau_object *, - struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nv50_software_context_dtor(struct nouveau_object *); - -int nv50_software_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32); -int nv50_software_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32); -int nv50_software_mthd_flip(struct nouveau_object *, u32, void *, u32); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/client.h b/drivers/gpu/drm/nouveau/core/include/core/client.h deleted file mode 100644 index b0ce9f6680b5..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/client.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef __NOUVEAU_CLIENT_H__ -#define __NOUVEAU_CLIENT_H__ - -#include <core/namedb.h> - -struct nouveau_client { - struct nouveau_namedb base; - struct nouveau_handle *root; - struct nouveau_object *device; - char name[32]; - u32 debug; - struct nouveau_vm *vm; - bool super; - void *data; - - int (*ntfy)(const void *, u32, const void *, u32); - struct nvkm_client_notify *notify[16]; -}; - -static inline struct nouveau_client * -nv_client(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - if (unlikely(!nv_iclass(obj, NV_CLIENT_CLASS))) - nv_assert("BAD CAST -> NvClient, %08x", nv_hclass(obj)); -#endif - return obj; -} - -static inline struct nouveau_client * -nouveau_client(void *obj) -{ - struct nouveau_object *client = nv_object(obj); - while (client && !(nv_iclass(client, NV_CLIENT_CLASS))) - client = client->parent; - return (void *)client; -} - -#define nouveau_client_create(n,c,oc,od,d) \ - nouveau_client_create_((n), (c), (oc), (od), sizeof(**d), (void **)d) - -int nouveau_client_create_(const char *name, u64 device, const char *cfg, - const char *dbg, int, void **); -#define nouveau_client_destroy(p) \ - nouveau_namedb_destroy(&(p)->base) - -int nouveau_client_init(struct nouveau_client *); -int nouveau_client_fini(struct nouveau_client *, bool suspend); -const char *nouveau_client_name(void *obj); - -int nvkm_client_notify_new(struct nouveau_object *, struct nvkm_event *, - void *data, u32 size); -int nvkm_client_notify_del(struct nouveau_client *, int index); -int nvkm_client_notify_get(struct nouveau_client *, int index); -int nvkm_client_notify_put(struct nouveau_client *, int index); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h deleted file mode 100644 index 2ec2e50d3676..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/device.h +++ /dev/null @@ -1,184 +0,0 @@ -#ifndef __NOUVEAU_DEVICE_H__ -#define __NOUVEAU_DEVICE_H__ - -#include <core/object.h> -#include <core/subdev.h> -#include <core/engine.h> -#include <core/event.h> - -enum nv_subdev_type { - NVDEV_ENGINE_DEVICE, - NVDEV_SUBDEV_VBIOS, - - /* All subdevs from DEVINIT to DEVINIT_LAST will be created before - * *any* of them are initialised. This subdev category is used - * for any subdevs that the VBIOS init table parsing may call out - * to during POST. - */ - NVDEV_SUBDEV_DEVINIT, - NVDEV_SUBDEV_IBUS, - NVDEV_SUBDEV_GPIO, - NVDEV_SUBDEV_I2C, - NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C, - - /* This grouping of subdevs are initialised right after they've - * been created, and are allowed to assume any subdevs in the - * list above them exist and have been initialised. - */ - NVDEV_SUBDEV_FUSE, - NVDEV_SUBDEV_MXM, - NVDEV_SUBDEV_MC, - NVDEV_SUBDEV_BUS, - NVDEV_SUBDEV_TIMER, - NVDEV_SUBDEV_FB, - NVDEV_SUBDEV_LTC, - NVDEV_SUBDEV_INSTMEM, - NVDEV_SUBDEV_VM, - NVDEV_SUBDEV_BAR, - NVDEV_SUBDEV_PWR, - NVDEV_SUBDEV_VOLT, - NVDEV_SUBDEV_THERM, - NVDEV_SUBDEV_CLOCK, - - NVDEV_ENGINE_FIRST, - NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, - NVDEV_ENGINE_IFB, - NVDEV_ENGINE_FIFO, - NVDEV_ENGINE_SW, - NVDEV_ENGINE_GR, - NVDEV_ENGINE_MPEG, - NVDEV_ENGINE_ME, - NVDEV_ENGINE_VP, - NVDEV_ENGINE_CRYPT, - NVDEV_ENGINE_BSP, - NVDEV_ENGINE_PPP, - NVDEV_ENGINE_COPY0, - NVDEV_ENGINE_COPY1, - NVDEV_ENGINE_COPY2, - NVDEV_ENGINE_VIC, - NVDEV_ENGINE_VENC, - NVDEV_ENGINE_DISP, - NVDEV_ENGINE_PERFMON, - - NVDEV_SUBDEV_NR, -}; - -struct nouveau_device { - struct nouveau_engine base; - struct list_head head; - - struct pci_dev *pdev; - struct platform_device *platformdev; - u64 handle; - - struct nvkm_event event; - - const char *cfgopt; - const char *dbgopt; - const char *name; - const char *cname; - u64 disable_mask; - - enum { - NV_04 = 0x04, - NV_10 = 0x10, - NV_11 = 0x11, - NV_20 = 0x20, - NV_30 = 0x30, - NV_40 = 0x40, - NV_50 = 0x50, - NV_C0 = 0xc0, - NV_E0 = 0xe0, - GM100 = 0x110, - } card_type; - u32 chipset; - u8 chiprev; - u32 crystal; - - struct nouveau_oclass *oclass[NVDEV_SUBDEV_NR]; - struct nouveau_object *subdev[NVDEV_SUBDEV_NR]; - - struct { - struct notifier_block nb; - } acpi; -}; - -int nouveau_device_list(u64 *name, int size); - -static inline struct nouveau_device * -nv_device(void *obj) -{ - struct nouveau_object *object = nv_object(obj); - struct nouveau_object *device = object; - - if (device->engine) - device = device->engine; - if (device->parent) - device = device->parent; - -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - if (unlikely(!nv_iclass(device, NV_SUBDEV_CLASS) || - (nv_hclass(device) & 0xff) != NVDEV_ENGINE_DEVICE)) { - nv_assert("BAD CAST -> NvDevice, 0x%08x 0x%08x", - nv_hclass(object), nv_hclass(device)); - } -#endif - - return (void *)device; -} - -static inline struct nouveau_subdev * -nouveau_subdev(void *obj, int sub) -{ - if (nv_device(obj)->subdev[sub]) - return nv_subdev(nv_device(obj)->subdev[sub]); - return NULL; -} - -static inline struct nouveau_engine * -nouveau_engine(void *obj, int sub) -{ - struct nouveau_subdev *subdev = nouveau_subdev(obj, sub); - if (subdev && nv_iclass(subdev, NV_ENGINE_CLASS)) - return nv_engine(subdev); - return NULL; -} - -static inline bool -nv_device_match(struct nouveau_object *object, u16 dev, u16 ven, u16 sub) -{ - struct nouveau_device *device = nv_device(object); - return device->pdev->device == dev && - device->pdev->subsystem_vendor == ven && - device->pdev->subsystem_device == sub; -} - -static inline bool -nv_device_is_pci(struct nouveau_device *device) -{ - return device->pdev != NULL; -} - -static inline bool -nv_device_is_cpu_coherent(struct nouveau_device *device) -{ - return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device)); -} - -static inline struct device * -nv_device_base(struct nouveau_device *device) -{ - return nv_device_is_pci(device) ? &device->pdev->dev : - &device->platformdev->dev; -} - -resource_size_t -nv_device_resource_start(struct nouveau_device *device, unsigned int bar); - -resource_size_t -nv_device_resource_len(struct nouveau_device *device, unsigned int bar); - -int -nv_device_get_irq(struct nouveau_device *device, bool stall); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/engctx.h b/drivers/gpu/drm/nouveau/core/include/core/engctx.h deleted file mode 100644 index 2fd48b564c7d..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/engctx.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef __NOUVEAU_ENGCTX_H__ -#define __NOUVEAU_ENGCTX_H__ - -#include <core/object.h> -#include <core/gpuobj.h> - -#include <subdev/vm.h> - -#define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng)) -#define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var)) - -struct nouveau_engctx { - struct nouveau_gpuobj base; - struct nouveau_vma vma; - struct list_head head; - unsigned long save; - u64 addr; -}; - -static inline struct nouveau_engctx * -nv_engctx(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - if (unlikely(!nv_iclass(obj, NV_ENGCTX_CLASS))) - nv_assert("BAD CAST -> NvEngCtx, %08x", nv_hclass(obj)); -#endif - return obj; -} - -#define nouveau_engctx_create(p,e,c,g,s,a,f,d) \ - nouveau_engctx_create_((p), (e), (c), (g), (s), (a), (f), \ - sizeof(**d), (void **)d) - -int nouveau_engctx_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, struct nouveau_object *, - u32 size, u32 align, u32 flags, - int length, void **data); -void nouveau_engctx_destroy(struct nouveau_engctx *); -int nouveau_engctx_init(struct nouveau_engctx *); -int nouveau_engctx_fini(struct nouveau_engctx *, bool suspend); - -int _nouveau_engctx_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void _nouveau_engctx_dtor(struct nouveau_object *); -int _nouveau_engctx_init(struct nouveau_object *); -int _nouveau_engctx_fini(struct nouveau_object *, bool suspend); -#define _nouveau_engctx_rd32 _nouveau_gpuobj_rd32 -#define _nouveau_engctx_wr32 _nouveau_gpuobj_wr32 - -struct nouveau_object *nouveau_engctx_get(struct nouveau_engine *, u64 addr); -void nouveau_engctx_put(struct nouveau_object *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/engine.h b/drivers/gpu/drm/nouveau/core/include/core/engine.h deleted file mode 100644 index 666d06de77ec..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/engine.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef __NOUVEAU_ENGINE_H__ -#define __NOUVEAU_ENGINE_H__ - -#include <core/object.h> -#include <core/subdev.h> - -#define NV_ENGINE_(eng,var) (NV_ENGINE_CLASS | ((var) << 8) | (eng)) -#define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var)) - -struct nouveau_engine { - struct nouveau_subdev base; - struct nouveau_oclass *cclass; - struct nouveau_oclass *sclass; - - struct list_head contexts; - spinlock_t lock; - - void (*tile_prog)(struct nouveau_engine *, int region); - int (*tlb_flush)(struct nouveau_engine *); -}; - -static inline struct nouveau_engine * -nv_engine(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - if (unlikely(!nv_iclass(obj, NV_ENGINE_CLASS))) - nv_assert("BAD CAST -> NvEngine, %08x", nv_hclass(obj)); -#endif - return obj; -} - -static inline int -nv_engidx(struct nouveau_object *object) -{ - return nv_subidx(object); -} - -#define nouveau_engine_create(p,e,c,d,i,f,r) \ - nouveau_engine_create_((p), (e), (c), (d), (i), (f), \ - sizeof(**r),(void **)r) - -#define nouveau_engine_destroy(p) \ - nouveau_subdev_destroy(&(p)->base) -#define nouveau_engine_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_engine_fini(p,s) \ - nouveau_subdev_fini(&(p)->base, (s)) - -int nouveau_engine_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, bool, const char *, - const char *, int, void **); - -#define _nouveau_engine_dtor _nouveau_subdev_dtor -#define _nouveau_engine_init _nouveau_subdev_init -#define _nouveau_engine_fini _nouveau_subdev_fini - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/enum.h b/drivers/gpu/drm/nouveau/core/include/core/enum.h deleted file mode 100644 index 4fc62bb8c1f0..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/enum.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __NOUVEAU_ENUM_H__ -#define __NOUVEAU_ENUM_H__ - -struct nouveau_enum { - u32 value; - const char *name; - const void *data; - u32 data2; -}; - -const struct nouveau_enum * -nouveau_enum_find(const struct nouveau_enum *, u32 value); - -const struct nouveau_enum * -nouveau_enum_print(const struct nouveau_enum *en, u32 value); - -struct nouveau_bitfield { - u32 mask; - const char *name; -}; - -void nouveau_bitfield_print(const struct nouveau_bitfield *, u32 value); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h b/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h deleted file mode 100644 index b3b9ce4e9d38..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef __NOUVEAU_GPUOBJ_H__ -#define __NOUVEAU_GPUOBJ_H__ - -#include <core/object.h> -#include <core/device.h> -#include <core/parent.h> -#include <core/mm.h> - -struct nouveau_vma; -struct nouveau_vm; - -#define NVOBJ_FLAG_ZERO_ALLOC 0x00000001 -#define NVOBJ_FLAG_ZERO_FREE 0x00000002 -#define NVOBJ_FLAG_HEAP 0x00000004 - -struct nouveau_gpuobj { - struct nouveau_object base; - struct nouveau_object *parent; - struct nouveau_mm_node *node; - struct nouveau_mm heap; - - u32 flags; - u64 addr; - u32 size; -}; - -static inline struct nouveau_gpuobj * -nv_gpuobj(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - if (unlikely(!nv_iclass(obj, NV_GPUOBJ_CLASS))) - nv_assert("BAD CAST -> NvGpuObj, %08x", nv_hclass(obj)); -#endif - return obj; -} - -#define nouveau_gpuobj_create(p,e,c,v,g,s,a,f,d) \ - nouveau_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \ - sizeof(**d), (void **)d) -#define nouveau_gpuobj_init(p) nouveau_object_init(&(p)->base) -#define nouveau_gpuobj_fini(p,s) nouveau_object_fini(&(p)->base, (s)) -int nouveau_gpuobj_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, u32 pclass, - struct nouveau_object *, u32 size, u32 align, - u32 flags, int length, void **); -void nouveau_gpuobj_destroy(struct nouveau_gpuobj *); - -int nouveau_gpuobj_new(struct nouveau_object *, struct nouveau_object *, - u32 size, u32 align, u32 flags, - struct nouveau_gpuobj **); -int nouveau_gpuobj_dup(struct nouveau_object *, struct nouveau_gpuobj *, - struct nouveau_gpuobj **); - -int nouveau_gpuobj_map(struct nouveau_gpuobj *, u32 acc, struct nouveau_vma *); -int nouveau_gpuobj_map_vm(struct nouveau_gpuobj *, struct nouveau_vm *, - u32 access, struct nouveau_vma *); -void nouveau_gpuobj_unmap(struct nouveau_vma *); - -static inline void -nouveau_gpuobj_ref(struct nouveau_gpuobj *obj, struct nouveau_gpuobj **ref) -{ - nouveau_object_ref(&obj->base, (struct nouveau_object **)ref); -} - -void _nouveau_gpuobj_dtor(struct nouveau_object *); -int _nouveau_gpuobj_init(struct nouveau_object *); -int _nouveau_gpuobj_fini(struct nouveau_object *, bool); -u32 _nouveau_gpuobj_rd32(struct nouveau_object *, u64); -void _nouveau_gpuobj_wr32(struct nouveau_object *, u64, u32); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/handle.h b/drivers/gpu/drm/nouveau/core/include/core/handle.h deleted file mode 100644 index d22a59138a9b..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/handle.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef __NOUVEAU_HANDLE_H__ -#define __NOUVEAU_HANDLE_H__ - -struct nouveau_handle { - struct nouveau_namedb *namedb; - struct list_head node; - - struct list_head head; - struct list_head tree; - u32 name; - u32 priv; - - u8 route; - u64 token; - - struct nouveau_handle *parent; - struct nouveau_object *object; -}; - -int nouveau_handle_create(struct nouveau_object *, u32 parent, u32 handle, - struct nouveau_object *, struct nouveau_handle **); -void nouveau_handle_destroy(struct nouveau_handle *); -int nouveau_handle_init(struct nouveau_handle *); -int nouveau_handle_fini(struct nouveau_handle *, bool suspend); - -struct nouveau_object * -nouveau_handle_ref(struct nouveau_object *, u32 name); - -struct nouveau_handle *nouveau_handle_get_class(struct nouveau_object *, u16); -struct nouveau_handle *nouveau_handle_get_vinst(struct nouveau_object *, u64); -struct nouveau_handle *nouveau_handle_get_cinst(struct nouveau_object *, u32); -void nouveau_handle_put(struct nouveau_handle *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/ioctl.h b/drivers/gpu/drm/nouveau/core/include/core/ioctl.h deleted file mode 100644 index ac7935c2474e..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/ioctl.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __NVKM_IOCTL_H__ -#define __NVKM_IOCTL_H__ - -int nvkm_ioctl(struct nouveau_client *, bool, void *, u32, void **); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/mm.h b/drivers/gpu/drm/nouveau/core/include/core/mm.h deleted file mode 100644 index bfe6931544fe..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/mm.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef __NOUVEAU_MM_H__ -#define __NOUVEAU_MM_H__ - -struct nouveau_mm_node { - struct list_head nl_entry; - struct list_head fl_entry; - struct list_head rl_entry; - -#define NVKM_MM_HEAP_ANY 0x00 - u8 heap; -#define NVKM_MM_TYPE_NONE 0x00 -#define NVKM_MM_TYPE_HOLE 0xff - u8 type; - u32 offset; - u32 length; -}; - -struct nouveau_mm { - struct list_head nodes; - struct list_head free; - - u32 block_size; - int heap_nodes; -}; - -static inline bool -nouveau_mm_initialised(struct nouveau_mm *mm) -{ - return mm->block_size != 0; -} - -int nouveau_mm_init(struct nouveau_mm *, u32 offset, u32 length, u32 block); -int nouveau_mm_fini(struct nouveau_mm *); -int nouveau_mm_head(struct nouveau_mm *, u8 heap, u8 type, u32 size_max, - u32 size_min, u32 align, struct nouveau_mm_node **); -int nouveau_mm_tail(struct nouveau_mm *, u8 heap, u8 type, u32 size_max, - u32 size_min, u32 align, struct nouveau_mm_node **); -void nouveau_mm_free(struct nouveau_mm *, struct nouveau_mm_node **); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/namedb.h b/drivers/gpu/drm/nouveau/core/include/core/namedb.h deleted file mode 100644 index f5b5fd8e1fc9..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/namedb.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef __NOUVEAU_NAMEDB_H__ -#define __NOUVEAU_NAMEDB_H__ - -#include <core/parent.h> - -struct nouveau_handle; - -struct nouveau_namedb { - struct nouveau_parent base; - rwlock_t lock; - struct list_head list; -}; - -static inline struct nouveau_namedb * -nv_namedb(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - if (unlikely(!nv_iclass(obj, NV_NAMEDB_CLASS))) - nv_assert("BAD CAST -> NvNameDB, %08x", nv_hclass(obj)); -#endif - return obj; -} - -#define nouveau_namedb_create(p,e,c,v,s,m,d) \ - nouveau_namedb_create_((p), (e), (c), (v), (s), (m), \ - sizeof(**d), (void **)d) -#define nouveau_namedb_init(p) \ - nouveau_parent_init(&(p)->base) -#define nouveau_namedb_fini(p,s) \ - nouveau_parent_fini(&(p)->base, (s)) -#define nouveau_namedb_destroy(p) \ - nouveau_parent_destroy(&(p)->base) - -int nouveau_namedb_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, u32 pclass, - struct nouveau_oclass *, u64 engcls, - int size, void **); - -int _nouveau_namedb_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -#define _nouveau_namedb_dtor _nouveau_parent_dtor -#define _nouveau_namedb_init _nouveau_parent_init -#define _nouveau_namedb_fini _nouveau_parent_fini - -int nouveau_namedb_insert(struct nouveau_namedb *, u32 name, - struct nouveau_object *, struct nouveau_handle *); -void nouveau_namedb_remove(struct nouveau_handle *); - -struct nouveau_handle *nouveau_namedb_get(struct nouveau_namedb *, u32); -struct nouveau_handle *nouveau_namedb_get_class(struct nouveau_namedb *, u16); -struct nouveau_handle *nouveau_namedb_get_vinst(struct nouveau_namedb *, u64); -struct nouveau_handle *nouveau_namedb_get_cinst(struct nouveau_namedb *, u32); -void nouveau_namedb_put(struct nouveau_handle *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/option.h b/drivers/gpu/drm/nouveau/core/include/core/option.h deleted file mode 100644 index ed055847887e..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/option.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __NOUVEAU_OPTION_H__ -#define __NOUVEAU_OPTION_H__ - -#include <core/os.h> - -const char *nouveau_stropt(const char *optstr, const char *opt, int *len); -bool nouveau_boolopt(const char *optstr, const char *opt, bool value); - -int nouveau_dbgopt(const char *optstr, const char *sub); - -/* compares unterminated string 'str' with zero-terminated string 'cmp' */ -static inline int -strncasecmpz(const char *str, const char *cmp, size_t len) -{ - if (strlen(cmp) != len) - return len; - return strncasecmp(str, cmp, len); -} - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/parent.h b/drivers/gpu/drm/nouveau/core/include/core/parent.h deleted file mode 100644 index 12da418ec70a..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/parent.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef __NOUVEAU_PARENT_H__ -#define __NOUVEAU_PARENT_H__ - -#include <core/device.h> -#include <core/object.h> - -struct nouveau_sclass { - struct nouveau_sclass *sclass; - struct nouveau_engine *engine; - struct nouveau_oclass *oclass; -}; - -struct nouveau_parent { - struct nouveau_object base; - - struct nouveau_sclass *sclass; - u64 engine; - - int (*context_attach)(struct nouveau_object *, - struct nouveau_object *); - int (*context_detach)(struct nouveau_object *, bool suspend, - struct nouveau_object *); - - int (*object_attach)(struct nouveau_object *parent, - struct nouveau_object *object, u32 name); - void (*object_detach)(struct nouveau_object *parent, int cookie); -}; - -static inline struct nouveau_parent * -nv_parent(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - if (unlikely(!(nv_iclass(obj, NV_PARENT_CLASS)))) - nv_assert("BAD CAST -> NvParent, %08x", nv_hclass(obj)); -#endif - return obj; -} - -#define nouveau_parent_create(p,e,c,v,s,m,d) \ - nouveau_parent_create_((p), (e), (c), (v), (s), (m), \ - sizeof(**d), (void **)d) -#define nouveau_parent_init(p) \ - nouveau_object_init(&(p)->base) -#define nouveau_parent_fini(p,s) \ - nouveau_object_fini(&(p)->base, (s)) - -int nouveau_parent_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, u32 pclass, - struct nouveau_oclass *, u64 engcls, - int size, void **); -void nouveau_parent_destroy(struct nouveau_parent *); - -void _nouveau_parent_dtor(struct nouveau_object *); -#define _nouveau_parent_init nouveau_object_init -#define _nouveau_parent_fini nouveau_object_fini - -int nouveau_parent_sclass(struct nouveau_object *, u16 handle, - struct nouveau_object **pengine, - struct nouveau_oclass **poclass); -int nouveau_parent_lclass(struct nouveau_object *, u32 *, int); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/ramht.h b/drivers/gpu/drm/nouveau/core/include/core/ramht.h deleted file mode 100644 index 47e4cacbca37..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/core/ramht.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __NOUVEAU_RAMHT_H__ -#define __NOUVEAU_RAMHT_H__ - -#include <core/gpuobj.h> - -struct nouveau_ramht { - struct nouveau_gpuobj base; - int bits; -}; - -int nouveau_ramht_insert(struct nouveau_ramht *, int chid, - u32 handle, u32 context); -void nouveau_ramht_remove(struct nouveau_ramht *, int cookie); -int nouveau_ramht_new(struct nouveau_object *, struct nouveau_object *, - u32 size, u32 align, struct nouveau_ramht **); - -static inline void -nouveau_ramht_ref(struct nouveau_ramht *obj, struct nouveau_ramht **ref) -{ - nouveau_gpuobj_ref(&obj->base, (struct nouveau_gpuobj **)ref); -} - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/bsp.h b/drivers/gpu/drm/nouveau/core/include/engine/bsp.h deleted file mode 100644 index 67662e2c4547..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/bsp.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __NOUVEAU_BSP_H__ -#define __NOUVEAU_BSP_H__ - -extern struct nouveau_oclass nv84_bsp_oclass; -extern struct nouveau_oclass nv98_bsp_oclass; -extern struct nouveau_oclass nvc0_bsp_oclass; -extern struct nouveau_oclass nve0_bsp_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/copy.h b/drivers/gpu/drm/nouveau/core/include/engine/copy.h deleted file mode 100644 index 316a28ae5f5c..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/copy.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __NOUVEAU_COPY_H__ -#define __NOUVEAU_COPY_H__ - -void nva3_copy_intr(struct nouveau_subdev *); - -extern struct nouveau_oclass nva3_copy_oclass; -extern struct nouveau_oclass nvc0_copy0_oclass; -extern struct nouveau_oclass nvc0_copy1_oclass; -extern struct nouveau_oclass nve0_copy0_oclass; -extern struct nouveau_oclass nve0_copy1_oclass; -extern struct nouveau_oclass nve0_copy2_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/crypt.h b/drivers/gpu/drm/nouveau/core/include/engine/crypt.h deleted file mode 100644 index db975618e937..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/crypt.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __NOUVEAU_CRYPT_H__ -#define __NOUVEAU_CRYPT_H__ - -extern struct nouveau_oclass nv84_crypt_oclass; -extern struct nouveau_oclass nv98_crypt_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/disp.h b/drivers/gpu/drm/nouveau/core/include/engine/disp.h deleted file mode 100644 index fc307f1317ff..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/disp.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef __NOUVEAU_DISP_H__ -#define __NOUVEAU_DISP_H__ - -#include <core/object.h> -#include <core/engine.h> -#include <core/device.h> -#include <core/event.h> - -struct nouveau_disp { - struct nouveau_engine base; - - struct list_head outp; - - struct nvkm_event hpd; - struct nvkm_event vblank; -}; - -static inline struct nouveau_disp * -nouveau_disp(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_DISP]; -} - -extern struct nouveau_oclass *nv04_disp_oclass; -extern struct nouveau_oclass *nv50_disp_oclass; -extern struct nouveau_oclass *nv84_disp_oclass; -extern struct nouveau_oclass *nva0_disp_oclass; -extern struct nouveau_oclass *nv94_disp_oclass; -extern struct nouveau_oclass *nva3_disp_oclass; -extern struct nouveau_oclass *nvd0_disp_oclass; -extern struct nouveau_oclass *nve0_disp_oclass; -extern struct nouveau_oclass *nvf0_disp_oclass; -extern struct nouveau_oclass *gm107_disp_oclass; -extern struct nouveau_oclass *gm204_disp_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h b/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h deleted file mode 100644 index 1b283a7b78e6..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __NOUVEAU_DMAOBJ_H__ -#define __NOUVEAU_DMAOBJ_H__ - -#include <core/object.h> -#include <core/engine.h> - -struct nouveau_gpuobj; - -struct nouveau_dmaobj { - struct nouveau_object base; - u32 target; - u32 access; - u64 start; - u64 limit; -}; - -struct nouveau_dmaeng { - struct nouveau_engine base; - - /* creates a "physical" dma object from a struct nouveau_dmaobj */ - int (*bind)(struct nouveau_dmaobj *dmaobj, - struct nouveau_object *parent, - struct nouveau_gpuobj **); -}; - -extern struct nouveau_oclass *nv04_dmaeng_oclass; -extern struct nouveau_oclass *nv50_dmaeng_oclass; -extern struct nouveau_oclass *nvc0_dmaeng_oclass; -extern struct nouveau_oclass *nvd0_dmaeng_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/falcon.h b/drivers/gpu/drm/nouveau/core/include/engine/falcon.h deleted file mode 100644 index 181aa7da524d..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/falcon.h +++ /dev/null @@ -1,83 +0,0 @@ -#ifndef __NOUVEAU_FALCON_H__ -#define __NOUVEAU_FALCON_H__ - -#include <core/engine.h> -#include <core/engctx.h> -#include <core/gpuobj.h> - -struct nouveau_falcon_chan { - struct nouveau_engctx base; -}; - -#define nouveau_falcon_context_create(p,e,c,g,s,a,f,d) \ - nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) -#define nouveau_falcon_context_destroy(d) \ - nouveau_engctx_destroy(&(d)->base) -#define nouveau_falcon_context_init(d) \ - nouveau_engctx_init(&(d)->base) -#define nouveau_falcon_context_fini(d,s) \ - nouveau_engctx_fini(&(d)->base, (s)) - -#define _nouveau_falcon_context_ctor _nouveau_engctx_ctor -#define _nouveau_falcon_context_dtor _nouveau_engctx_dtor -#define _nouveau_falcon_context_init _nouveau_engctx_init -#define _nouveau_falcon_context_fini _nouveau_engctx_fini -#define _nouveau_falcon_context_rd32 _nouveau_engctx_rd32 -#define _nouveau_falcon_context_wr32 _nouveau_engctx_wr32 - -struct nouveau_falcon_data { - bool external; -}; - -struct nouveau_falcon { - struct nouveau_engine base; - - u32 addr; - u8 version; - u8 secret; - - struct nouveau_gpuobj *core; - bool external; - - struct { - u32 limit; - u32 *data; - u32 size; - } code; - - struct { - u32 limit; - u32 *data; - u32 size; - } data; -}; - -#define nv_falcon(priv) (&(priv)->base) - -#define nouveau_falcon_create(p,e,c,b,d,i,f,r) \ - nouveau_falcon_create_((p), (e), (c), (b), (d), (i), (f), \ - sizeof(**r),(void **)r) -#define nouveau_falcon_destroy(p) \ - nouveau_engine_destroy(&(p)->base) -#define nouveau_falcon_init(p) ({ \ - struct nouveau_falcon *falcon = (p); \ - _nouveau_falcon_init(nv_object(falcon)); \ -}) -#define nouveau_falcon_fini(p,s) ({ \ - struct nouveau_falcon *falcon = (p); \ - _nouveau_falcon_fini(nv_object(falcon), (s)); \ -}) - -int nouveau_falcon_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, u32, bool, const char *, - const char *, int, void **); - -void nouveau_falcon_intr(struct nouveau_subdev *subdev); - -#define _nouveau_falcon_dtor _nouveau_engine_dtor -int _nouveau_falcon_init(struct nouveau_object *); -int _nouveau_falcon_fini(struct nouveau_object *, bool); -u32 _nouveau_falcon_rd32(struct nouveau_object *, u64); -void _nouveau_falcon_wr32(struct nouveau_object *, u64, u32); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h deleted file mode 100644 index 2007453f6fce..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h +++ /dev/null @@ -1,126 +0,0 @@ -#ifndef __NOUVEAU_FIFO_H__ -#define __NOUVEAU_FIFO_H__ - -#include <core/namedb.h> -#include <core/gpuobj.h> -#include <core/engine.h> -#include <core/event.h> - -struct nouveau_fifo_chan { - struct nouveau_namedb base; - struct nouveau_dmaobj *pushdma; - struct nouveau_gpuobj *pushgpu; - void __iomem *user; - u64 addr; - u32 size; - u16 chid; - atomic_t refcnt; /* NV04_NVSW_SET_REF */ -}; - -static inline struct nouveau_fifo_chan * -nouveau_fifo_chan(void *obj) -{ - return (void *)nv_namedb(obj); -} - -#define nouveau_fifo_channel_create(p,e,c,b,a,s,n,m,d) \ - nouveau_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \ - (m), sizeof(**d), (void **)d) -#define nouveau_fifo_channel_init(p) \ - nouveau_namedb_init(&(p)->base) -#define nouveau_fifo_channel_fini(p,s) \ - nouveau_namedb_fini(&(p)->base, (s)) - -int nouveau_fifo_channel_create_(struct nouveau_object *, - struct nouveau_object *, - struct nouveau_oclass *, - int bar, u32 addr, u32 size, u32 push, - u64 engmask, int len, void **); -void nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *); - -#define _nouveau_fifo_channel_init _nouveau_namedb_init -#define _nouveau_fifo_channel_fini _nouveau_namedb_fini - -void _nouveau_fifo_channel_dtor(struct nouveau_object *); -int _nouveau_fifo_channel_map(struct nouveau_object *, u64 *, u32 *); -u32 _nouveau_fifo_channel_rd32(struct nouveau_object *, u64); -void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32); -int _nouveau_fifo_channel_ntfy(struct nouveau_object *, u32, struct nvkm_event **); - -struct nouveau_fifo_base { - struct nouveau_gpuobj base; -}; - -#define nouveau_fifo_context_create(p,e,c,g,s,a,f,d) \ - nouveau_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d)) -#define nouveau_fifo_context_destroy(p) \ - nouveau_gpuobj_destroy(&(p)->base) -#define nouveau_fifo_context_init(p) \ - nouveau_gpuobj_init(&(p)->base) -#define nouveau_fifo_context_fini(p,s) \ - nouveau_gpuobj_fini(&(p)->base, (s)) - -#define _nouveau_fifo_context_dtor _nouveau_gpuobj_dtor -#define _nouveau_fifo_context_init _nouveau_gpuobj_init -#define _nouveau_fifo_context_fini _nouveau_gpuobj_fini -#define _nouveau_fifo_context_rd32 _nouveau_gpuobj_rd32 -#define _nouveau_fifo_context_wr32 _nouveau_gpuobj_wr32 - -struct nouveau_fifo { - struct nouveau_engine base; - - struct nvkm_event cevent; /* channel creation event */ - struct nvkm_event uevent; /* async user trigger */ - - struct nouveau_object **channel; - spinlock_t lock; - u16 min; - u16 max; - - int (*chid)(struct nouveau_fifo *, struct nouveau_object *); - void (*pause)(struct nouveau_fifo *, unsigned long *); - void (*start)(struct nouveau_fifo *, unsigned long *); -}; - -static inline struct nouveau_fifo * -nouveau_fifo(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_FIFO]; -} - -#define nouveau_fifo_create(o,e,c,fc,lc,d) \ - nouveau_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d) -#define nouveau_fifo_init(p) \ - nouveau_engine_init(&(p)->base) -#define nouveau_fifo_fini(p,s) \ - nouveau_engine_fini(&(p)->base, (s)) - -int nouveau_fifo_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int min, int max, - int size, void **); -void nouveau_fifo_destroy(struct nouveau_fifo *); -const char * -nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid); - -#define _nouveau_fifo_init _nouveau_engine_init -#define _nouveau_fifo_fini _nouveau_engine_fini - -extern struct nouveau_oclass *nv04_fifo_oclass; -extern struct nouveau_oclass *nv10_fifo_oclass; -extern struct nouveau_oclass *nv17_fifo_oclass; -extern struct nouveau_oclass *nv40_fifo_oclass; -extern struct nouveau_oclass *nv50_fifo_oclass; -extern struct nouveau_oclass *nv84_fifo_oclass; -extern struct nouveau_oclass *nvc0_fifo_oclass; -extern struct nouveau_oclass *nve0_fifo_oclass; -extern struct nouveau_oclass *gk20a_fifo_oclass; -extern struct nouveau_oclass *nv108_fifo_oclass; - -int nouveau_fifo_uevent_ctor(struct nouveau_object *, void *, u32, - struct nvkm_notify *); -void nouveau_fifo_uevent(struct nouveau_fifo *); - -void nv04_fifo_intr(struct nouveau_subdev *); -int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/core/include/engine/graph.h deleted file mode 100644 index d5055570d01b..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/graph.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef __NOUVEAU_GRAPH_H__ -#define __NOUVEAU_GRAPH_H__ - -#include <core/engine.h> -#include <core/engctx.h> -#include <core/enum.h> - -struct nouveau_graph_chan { - struct nouveau_engctx base; -}; - -#define nouveau_graph_context_create(p,e,c,g,s,a,f,d) \ - nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) -#define nouveau_graph_context_destroy(d) \ - nouveau_engctx_destroy(&(d)->base) -#define nouveau_graph_context_init(d) \ - nouveau_engctx_init(&(d)->base) -#define nouveau_graph_context_fini(d,s) \ - nouveau_engctx_fini(&(d)->base, (s)) - -#define _nouveau_graph_context_dtor _nouveau_engctx_dtor -#define _nouveau_graph_context_init _nouveau_engctx_init -#define _nouveau_graph_context_fini _nouveau_engctx_fini -#define _nouveau_graph_context_rd32 _nouveau_engctx_rd32 -#define _nouveau_graph_context_wr32 _nouveau_engctx_wr32 - -struct nouveau_graph { - struct nouveau_engine base; - - /* Returns chipset-specific counts of units packed into an u64. - */ - u64 (*units)(struct nouveau_graph *); -}; - -static inline struct nouveau_graph * -nouveau_graph(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_GR]; -} - -#define nouveau_graph_create(p,e,c,y,d) \ - nouveau_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d)) -#define nouveau_graph_destroy(d) \ - nouveau_engine_destroy(&(d)->base) -#define nouveau_graph_init(d) \ - nouveau_engine_init(&(d)->base) -#define nouveau_graph_fini(d,s) \ - nouveau_engine_fini(&(d)->base, (s)) - -#define _nouveau_graph_dtor _nouveau_engine_dtor -#define _nouveau_graph_init _nouveau_engine_init -#define _nouveau_graph_fini _nouveau_engine_fini - -extern struct nouveau_oclass nv04_graph_oclass; -extern struct nouveau_oclass nv10_graph_oclass; -extern struct nouveau_oclass nv20_graph_oclass; -extern struct nouveau_oclass nv25_graph_oclass; -extern struct nouveau_oclass nv2a_graph_oclass; -extern struct nouveau_oclass nv30_graph_oclass; -extern struct nouveau_oclass nv34_graph_oclass; -extern struct nouveau_oclass nv35_graph_oclass; -extern struct nouveau_oclass nv40_graph_oclass; -extern struct nouveau_oclass nv50_graph_oclass; -extern struct nouveau_oclass *nvc0_graph_oclass; -extern struct nouveau_oclass *nvc1_graph_oclass; -extern struct nouveau_oclass *nvc4_graph_oclass; -extern struct nouveau_oclass *nvc8_graph_oclass; -extern struct nouveau_oclass *nvd7_graph_oclass; -extern struct nouveau_oclass *nvd9_graph_oclass; -extern struct nouveau_oclass *nve4_graph_oclass; -extern struct nouveau_oclass *gk20a_graph_oclass; -extern struct nouveau_oclass *nvf0_graph_oclass; -extern struct nouveau_oclass *gk110b_graph_oclass; -extern struct nouveau_oclass *nv108_graph_oclass; -extern struct nouveau_oclass *gm107_graph_oclass; - -extern const struct nouveau_bitfield nv04_graph_nsource[]; -extern struct nouveau_ofuncs nv04_graph_ofuncs; -bool nv04_graph_idle(void *obj); - -extern const struct nouveau_bitfield nv10_graph_intr_name[]; -extern const struct nouveau_bitfield nv10_graph_nstatus[]; - -extern const struct nouveau_enum nv50_data_error_names[]; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h b/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h deleted file mode 100644 index 9b0d938199f6..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __NOUVEAU_MPEG_H__ -#define __NOUVEAU_MPEG_H__ - -#include <core/engine.h> -#include <core/engctx.h> - -struct nouveau_mpeg_chan { - struct nouveau_engctx base; -}; - -#define nouveau_mpeg_context_create(p,e,c,g,s,a,f,d) \ - nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) -#define nouveau_mpeg_context_destroy(d) \ - nouveau_engctx_destroy(&(d)->base) -#define nouveau_mpeg_context_init(d) \ - nouveau_engctx_init(&(d)->base) -#define nouveau_mpeg_context_fini(d,s) \ - nouveau_engctx_fini(&(d)->base, (s)) - -#define _nouveau_mpeg_context_dtor _nouveau_engctx_dtor -#define _nouveau_mpeg_context_init _nouveau_engctx_init -#define _nouveau_mpeg_context_fini _nouveau_engctx_fini -#define _nouveau_mpeg_context_rd32 _nouveau_engctx_rd32 -#define _nouveau_mpeg_context_wr32 _nouveau_engctx_wr32 - -struct nouveau_mpeg { - struct nouveau_engine base; -}; - -#define nouveau_mpeg_create(p,e,c,d) \ - nouveau_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d)) -#define nouveau_mpeg_destroy(d) \ - nouveau_engine_destroy(&(d)->base) -#define nouveau_mpeg_init(d) \ - nouveau_engine_init(&(d)->base) -#define nouveau_mpeg_fini(d,s) \ - nouveau_engine_fini(&(d)->base, (s)) - -#define _nouveau_mpeg_dtor _nouveau_engine_dtor -#define _nouveau_mpeg_init _nouveau_engine_init -#define _nouveau_mpeg_fini _nouveau_engine_fini - -extern struct nouveau_oclass nv31_mpeg_oclass; -extern struct nouveau_oclass nv40_mpeg_oclass; -extern struct nouveau_oclass nv44_mpeg_oclass; -extern struct nouveau_oclass nv50_mpeg_oclass; -extern struct nouveau_oclass nv84_mpeg_oclass; -extern struct nouveau_ofuncs nv31_mpeg_ofuncs; -extern struct nouveau_oclass nv31_mpeg_cclass; -extern struct nouveau_oclass nv31_mpeg_sclass[]; -extern struct nouveau_oclass nv40_mpeg_sclass[]; -void nv31_mpeg_intr(struct nouveau_subdev *); -void nv31_mpeg_tile_prog(struct nouveau_engine *, int); -int nv31_mpeg_init(struct nouveau_object *); - -extern struct nouveau_ofuncs nv50_mpeg_ofuncs; -int nv50_mpeg_context_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nv50_mpeg_intr(struct nouveau_subdev *); -int nv50_mpeg_init(struct nouveau_object *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h b/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h deleted file mode 100644 index 88cc812baaa3..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef __NVKM_PERFMON_H__ -#define __NVKM_PERFMON_H__ - -#include <core/device.h> -#include <core/engine.h> -#include <core/engctx.h> - -struct nouveau_perfdom; -struct nouveau_perfctr; -struct nouveau_perfmon { - struct nouveau_engine base; - - struct nouveau_perfctx *context; - void *profile_data; - - struct list_head domains; - u32 sequence; - - /*XXX: temp for daemon backend */ - u32 pwr[8]; - u32 last; -}; - -static inline struct nouveau_perfmon * -nouveau_perfmon(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_PERFMON]; -} - -extern struct nouveau_oclass *nv40_perfmon_oclass; -extern struct nouveau_oclass *nv50_perfmon_oclass; -extern struct nouveau_oclass *nv84_perfmon_oclass; -extern struct nouveau_oclass *nva3_perfmon_oclass; -extern struct nouveau_oclass nvc0_perfmon_oclass; -extern struct nouveau_oclass nve0_perfmon_oclass; -extern struct nouveau_oclass nvf0_perfmon_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/ppp.h b/drivers/gpu/drm/nouveau/core/include/engine/ppp.h deleted file mode 100644 index 0a66781e8cf1..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/ppp.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __NOUVEAU_PPP_H__ -#define __NOUVEAU_PPP_H__ - -extern struct nouveau_oclass nv98_ppp_oclass; -extern struct nouveau_oclass nvc0_ppp_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/software.h b/drivers/gpu/drm/nouveau/core/include/engine/software.h deleted file mode 100644 index 23a462b50d03..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/software.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef __NOUVEAU_SOFTWARE_H__ -#define __NOUVEAU_SOFTWARE_H__ - -#include <core/engine.h> -#include <core/engctx.h> - -struct nouveau_software_chan { - struct nouveau_engctx base; - - int (*flip)(void *); - void *flip_data; -}; - -#define nouveau_software_context_create(p,e,c,d) \ - nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d)) -#define nouveau_software_context_destroy(d) \ - nouveau_engctx_destroy(&(d)->base) -#define nouveau_software_context_init(d) \ - nouveau_engctx_init(&(d)->base) -#define nouveau_software_context_fini(d,s) \ - nouveau_engctx_fini(&(d)->base, (s)) - -#define _nouveau_software_context_dtor _nouveau_engctx_dtor -#define _nouveau_software_context_init _nouveau_engctx_init -#define _nouveau_software_context_fini _nouveau_engctx_fini - -struct nouveau_software { - struct nouveau_engine base; -}; - -#define nouveau_software_create(p,e,c,d) \ - nouveau_engine_create((p), (e), (c), true, "SW", "software", (d)) -#define nouveau_software_destroy(d) \ - nouveau_engine_destroy(&(d)->base) -#define nouveau_software_init(d) \ - nouveau_engine_init(&(d)->base) -#define nouveau_software_fini(d,s) \ - nouveau_engine_fini(&(d)->base, (s)) - -#define _nouveau_software_dtor _nouveau_engine_dtor -#define _nouveau_software_init _nouveau_engine_init -#define _nouveau_software_fini _nouveau_engine_fini - -extern struct nouveau_oclass *nv04_software_oclass; -extern struct nouveau_oclass *nv10_software_oclass; -extern struct nouveau_oclass *nv50_software_oclass; -extern struct nouveau_oclass *nvc0_software_oclass; - -void nv04_software_intr(struct nouveau_subdev *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/vp.h b/drivers/gpu/drm/nouveau/core/include/engine/vp.h deleted file mode 100644 index 39baebec7fbb..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/vp.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __NOUVEAU_VP_H__ -#define __NOUVEAU_VP_H__ - -extern struct nouveau_oclass nv84_vp_oclass; -extern struct nouveau_oclass nv98_vp_oclass; -extern struct nouveau_oclass nvc0_vp_oclass; -extern struct nouveau_oclass nve0_vp_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h b/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h deleted file mode 100644 index 306100f31f02..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef __NOUVEAU_XTENSA_H__ -#define __NOUVEAU_XTENSA_H__ - -#include <core/engine.h> -#include <core/engctx.h> -#include <core/gpuobj.h> - -struct nouveau_xtensa { - struct nouveau_engine base; - - u32 addr; - struct nouveau_gpuobj *gpu_fw; - u32 fifo_val; - u32 unkd28; -}; - -#define nouveau_xtensa_create(p,e,c,b,d,i,f,r) \ - nouveau_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \ - sizeof(**r),(void **)r) - -int _nouveau_xtensa_engctx_ctor(struct nouveau_object *, - struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); - -void _nouveau_xtensa_intr(struct nouveau_subdev *); -int nouveau_xtensa_create_(struct nouveau_object *, - struct nouveau_object *, - struct nouveau_oclass *, u32, bool, - const char *, const char *, - int, void **); -#define _nouveau_xtensa_dtor _nouveau_engine_dtor -int _nouveau_xtensa_init(struct nouveau_object *); -int _nouveau_xtensa_fini(struct nouveau_object *, bool); -u32 _nouveau_xtensa_rd32(struct nouveau_object *, u64); -void _nouveau_xtensa_wr32(struct nouveau_object *, u64, u32); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/class.h b/drivers/gpu/drm/nouveau/core/include/nvif/class.h deleted file mode 120000 index f1ac4859edd4..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/nvif/class.h +++ /dev/null @@ -1 +0,0 @@ -../../../nvif/class.h
\ No newline at end of file diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/event.h b/drivers/gpu/drm/nouveau/core/include/nvif/event.h deleted file mode 120000 index 1b798538a725..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/nvif/event.h +++ /dev/null @@ -1 +0,0 @@ -../../../nvif/event.h
\ No newline at end of file diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h b/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h deleted file mode 120000 index 8569c86907c5..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h +++ /dev/null @@ -1 +0,0 @@ -../../../nvif/ioctl.h
\ No newline at end of file diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h b/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h deleted file mode 120000 index 69d99292bca4..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h +++ /dev/null @@ -1 +0,0 @@ -../../../nvif/unpack.h
\ No newline at end of file diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h b/drivers/gpu/drm/nouveau/core/include/subdev/bar.h deleted file mode 100644 index 257ddf6d36d4..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef __NOUVEAU_BAR_H__ -#define __NOUVEAU_BAR_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_mem; -struct nouveau_vma; - -struct nouveau_bar { - struct nouveau_subdev base; - - int (*alloc)(struct nouveau_bar *, struct nouveau_object *, - struct nouveau_mem *, struct nouveau_object **); - - int (*kmap)(struct nouveau_bar *, struct nouveau_mem *, - u32 flags, struct nouveau_vma *); - int (*umap)(struct nouveau_bar *, struct nouveau_mem *, - u32 flags, struct nouveau_vma *); - void (*unmap)(struct nouveau_bar *, struct nouveau_vma *); - void (*flush)(struct nouveau_bar *); - - /* whether the BAR supports to be ioremapped WC or should be uncached */ - bool iomap_uncached; -}; - -static inline struct nouveau_bar * -nouveau_bar(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BAR]; -} - -extern struct nouveau_oclass nv50_bar_oclass; -extern struct nouveau_oclass nvc0_bar_oclass; -extern struct nouveau_oclass gk20a_bar_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios.h deleted file mode 100644 index 5bd1ca8cd20d..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __NOUVEAU_BIOS_H__ -#define __NOUVEAU_BIOS_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_bios { - struct nouveau_subdev base; - u32 size; - u8 *data; - - u32 bmp_offset; - u32 bit_offset; - - struct { - u8 major; - u8 chip; - u8 minor; - u8 micro; - u8 patch; - } version; -}; - -static inline struct nouveau_bios * -nouveau_bios(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VBIOS]; -} - -u8 nvbios_checksum(const u8 *data, int size); -u16 nvbios_findstr(const u8 *data, int size, const char *str, int len); - -extern struct nouveau_oclass nouveau_bios_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h deleted file mode 100644 index e171120cec81..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef __NVBIOS_M0205_H__ -#define __NVBIOS_M0205_H__ - -struct nvbios_M0205T { - u16 freq; -}; - -u32 nvbios_M0205Te(struct nouveau_bios *, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); -u32 nvbios_M0205Tp(struct nouveau_bios *, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz, - struct nvbios_M0205T *); - -struct nvbios_M0205E { - u8 type; -}; - -u32 nvbios_M0205Ee(struct nouveau_bios *, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u32 nvbios_M0205Ep(struct nouveau_bios *, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_M0205E *); - -struct nvbios_M0205S { - u8 data; -}; - -u32 nvbios_M0205Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr); -u32 nvbios_M0205Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr, - struct nvbios_M0205S *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h deleted file mode 100644 index 67dc50d837bc..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __NVBIOS_M0209_H__ -#define __NVBIOS_M0209_H__ - -u32 nvbios_M0209Te(struct nouveau_bios *, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); - -struct nvbios_M0209E { - u8 v00_40; - u8 bits; - u8 modulo; - u8 v02_40; - u8 v02_07; - u8 v03; -}; - -u32 nvbios_M0209Ee(struct nouveau_bios *, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u32 nvbios_M0209Ep(struct nouveau_bios *, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_M0209E *); - -struct nvbios_M0209S { - u32 data[0x200]; -}; - -u32 nvbios_M0209Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr); -u32 nvbios_M0209Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr, - struct nvbios_M0209S *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h deleted file mode 100644 index bba01ab1e049..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __NVBIOS_P0260_H__ -#define __NVBIOS_P0260_H__ - -u32 nvbios_P0260Te(struct nouveau_bios *, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz); - -struct nvbios_P0260E { - u32 data; -}; - -u32 nvbios_P0260Ee(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); -u32 nvbios_P0260Ep(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, - struct nvbios_P0260E *); - -struct nvbios_P0260X { - u32 data; -}; - -u32 nvbios_P0260Xe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); -u32 nvbios_P0260Xp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, - struct nvbios_P0260X *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h deleted file mode 100644 index 662b20726851..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __NVBIOS_BOOST_H__ -#define __NVBIOS_BOOST_H__ - -u16 nvbios_boostTe(struct nouveau_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *); - -struct nvbios_boostE { - u8 pstate; - u32 min; - u32 max; -}; - -u16 nvbios_boostEe(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *); -u16 nvbios_boostEp(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *, - struct nvbios_boostE *); -u16 nvbios_boostEm(struct nouveau_bios *, u8, u8 *, u8 *, u8 *, u8 *, - struct nvbios_boostE *); - -struct nvbios_boostS { - u8 domain; - u8 percent; - u32 min; - u32 max; -}; - -u16 nvbios_boostSe(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8); -u16 nvbios_boostSp(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8, - struct nvbios_boostS *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h deleted file mode 100644 index a80a43809883..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __NVBIOS_CSTEP_H__ -#define __NVBIOS_CSTEP_H__ - -u16 nvbios_cstepTe(struct nouveau_bios *, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz); - -struct nvbios_cstepE { - u8 pstate; - u8 index; -}; - -u16 nvbios_cstepEe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); -u16 nvbios_cstepEp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, - struct nvbios_cstepE *); -u16 nvbios_cstepEm(struct nouveau_bios *, u8 pstate, u8 *ver, u8 *hdr, - struct nvbios_cstepE *); - -struct nvbios_cstepX { - u32 freq; - u8 unkn[2]; - u8 voltage; -}; - -u16 nvbios_cstepXe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); -u16 nvbios_cstepXp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, - struct nvbios_cstepX *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h deleted file mode 100644 index c35937e2f6a4..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef __NVBIOS_DISP_H__ -#define __NVBIOS_DISP_H__ - -u16 nvbios_disp_table(struct nouveau_bios *, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub); - -struct nvbios_disp { - u16 data; -}; - -u16 nvbios_disp_entry(struct nouveau_bios *, u8 idx, - u8 *ver, u8 *hdr__, u8 *sub); -u16 nvbios_disp_parse(struct nouveau_bios *, u8 idx, - u8 *ver, u8 *hdr__, u8 *sub, - struct nvbios_disp *); - -struct nvbios_outp { - u16 type; - u16 mask; - u16 script[3]; -}; - -u16 nvbios_outp_entry(struct nouveau_bios *, u8 idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_outp_parse(struct nouveau_bios *, u8 idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_outp *); -u16 nvbios_outp_match(struct nouveau_bios *, u16 type, u16 mask, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_outp *); - - -struct nvbios_ocfg { - u16 match; - u16 clkcmp[2]; -}; - -u16 nvbios_ocfg_entry(struct nouveau_bios *, u16 outp, u8 idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_ocfg_parse(struct nouveau_bios *, u16 outp, u8 idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ocfg *); -u16 nvbios_ocfg_match(struct nouveau_bios *, u16 outp, u16 type, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ocfg *); -u16 nvbios_oclk_match(struct nouveau_bios *, u16 cmp, u32 khz); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h deleted file mode 100644 index 728206e21777..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __NVBIOS_DP_H__ -#define __NVBIOS_DP_H__ - -struct nvbios_dpout { - u16 type; - u16 mask; - u8 flags; - u32 script[5]; - u32 lnkcmp; -}; - -u16 nvbios_dpout_parse(struct nouveau_bios *, u8 idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_dpout *); -u16 nvbios_dpout_match(struct nouveau_bios *, u16 type, u16 mask, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_dpout *); - -struct nvbios_dpcfg { - u8 pc; - u8 dc; - u8 pe; - u8 tx_pu; -}; - -u16 -nvbios_dpcfg_parse(struct nouveau_bios *, u16 outp, u8 idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_dpcfg *); -u16 -nvbios_dpcfg_match(struct nouveau_bios *, u16 outp, u8 pc, u8 vs, u8 pe, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_dpcfg *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h deleted file mode 100644 index 5572e60414e8..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __NVBIOS_MXM_H__ -#define __NVBIOS_MXM_H__ - -u16 mxm_table(struct nouveau_bios *, u8 *ver, u8 *hdr); - -u8 mxm_sor_map(struct nouveau_bios *, u8 conn); -u8 mxm_ddc_map(struct nouveau_bios *, u8 port); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/npde.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/npde.h deleted file mode 100644 index b18413d951e5..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/npde.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __NVBIOS_NPDE_H__ -#define __NVBIOS_NPDE_H__ - -struct nvbios_npdeT { - u32 image_size; - bool last; -}; - -u32 nvbios_npdeTe(struct nouveau_bios *, u32); -u32 nvbios_npdeTp(struct nouveau_bios *, u32, struct nvbios_npdeT *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h deleted file mode 100644 index 47e021d3e20d..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __NVBIOS_RAMMAP_H__ -#define __NVBIOS_RAMMAP_H__ - -struct nvbios_ramcfg; - -u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr, - u8 *cnt, u8 *len, u8 *snr, u8 *ssz); - -u32 nvbios_rammapEe(struct nouveau_bios *, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u32 nvbios_rammapEp(struct nouveau_bios *, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ramcfg *); -u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ramcfg *); - -u32 nvbios_rammapSe(struct nouveau_bios *, u32 data, - u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, - u8 *ver, u8 *hdr); -u32 nvbios_rammapSp(struct nouveau_bios *, u32 data, - u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, - u8 *ver, u8 *hdr, - struct nvbios_ramcfg *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h deleted file mode 100644 index 76d914b67ab5..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __NVBIOS_TIMING_H__ -#define __NVBIOS_TIMING_H__ - -struct nvbios_ramcfg; - -u16 nvbios_timingTe(struct nouveau_bios *, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); -u16 nvbios_timingEe(struct nouveau_bios *, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_timingEp(struct nouveau_bios *, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ramcfg *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h deleted file mode 100644 index ad5a8f20e113..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __NVBIOS_VMAP_H__ -#define __NVBIOS_VMAP_H__ - -struct nouveau_bios; - -struct nvbios_vmap { -}; - -u16 nvbios_vmap_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_vmap_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_vmap *); - -struct nvbios_vmap_entry { - u8 unk0; - u8 link; - u32 min; - u32 max; - s32 arg[6]; -}; - -u16 nvbios_vmap_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len); -u16 nvbios_vmap_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len, - struct nvbios_vmap_entry *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h deleted file mode 100644 index 6a11dcd59770..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __NVBIOS_VOLT_H__ -#define __NVBIOS_VOLT_H__ - -struct nouveau_bios; - -struct nvbios_volt { - u8 vidmask; - u32 min; - u32 max; - u32 base; - s16 step; -}; - -u16 nvbios_volt_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_volt_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_volt *); - -struct nvbios_volt_entry { - u32 voltage; - u8 vid; -}; - -u16 nvbios_volt_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len); -u16 nvbios_volt_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len, - struct nvbios_volt_entry *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h b/drivers/gpu/drm/nouveau/core/include/subdev/bus.h deleted file mode 100644 index 697f7ce70aab..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef __NOUVEAU_BUS_H__ -#define __NOUVEAU_BUS_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_bus_intr { - u32 stat; - u32 unit; -}; - -struct nouveau_bus { - struct nouveau_subdev base; - int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32); - u32 hwsq_size; -}; - -static inline struct nouveau_bus * -nouveau_bus(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BUS]; -} - -#define nouveau_bus_create(p, e, o, d) \ - nouveau_subdev_create_((p), (e), (o), 0, "PBUS", "master", \ - sizeof(**d), (void **)d) -#define nouveau_bus_destroy(p) \ - nouveau_subdev_destroy(&(p)->base) -#define nouveau_bus_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_bus_fini(p, s) \ - nouveau_subdev_fini(&(p)->base, (s)) - -#define _nouveau_bus_dtor _nouveau_subdev_dtor -#define _nouveau_bus_init _nouveau_subdev_init -#define _nouveau_bus_fini _nouveau_subdev_fini - -extern struct nouveau_oclass *nv04_bus_oclass; -extern struct nouveau_oclass *nv31_bus_oclass; -extern struct nouveau_oclass *nv50_bus_oclass; -extern struct nouveau_oclass *nv94_bus_oclass; -extern struct nouveau_oclass *nvc0_bus_oclass; - -/* interface to sequencer */ -struct nouveau_hwsq; -int nouveau_hwsq_init(struct nouveau_bus *, struct nouveau_hwsq **); -int nouveau_hwsq_fini(struct nouveau_hwsq **, bool exec); -void nouveau_hwsq_wr32(struct nouveau_hwsq *, u32 addr, u32 data); -void nouveau_hwsq_setf(struct nouveau_hwsq *, u8 flag, int data); -void nouveau_hwsq_wait(struct nouveau_hwsq *, u8 flag, u8 data); -void nouveau_hwsq_nsec(struct nouveau_hwsq *, u32 nsec); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h deleted file mode 100644 index 36ed035d4d42..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ /dev/null @@ -1,166 +0,0 @@ -#ifndef __NOUVEAU_CLOCK_H__ -#define __NOUVEAU_CLOCK_H__ - -#include <core/device.h> -#include <core/subdev.h> - -struct nouveau_pll_vals; -struct nvbios_pll; - -enum nv_clk_src { - nv_clk_src_crystal, - nv_clk_src_href, - - nv_clk_src_hclk, - nv_clk_src_hclkm3, - nv_clk_src_hclkm3d2, - nv_clk_src_hclkm2d3, /* NVAA */ - nv_clk_src_hclkm4, /* NVAA */ - nv_clk_src_cclk, /* NVAA */ - - nv_clk_src_host, - - nv_clk_src_sppll0, - nv_clk_src_sppll1, - - nv_clk_src_mpllsrcref, - nv_clk_src_mpllsrc, - nv_clk_src_mpll, - nv_clk_src_mdiv, - - nv_clk_src_core, - nv_clk_src_core_intm, - nv_clk_src_shader, - - nv_clk_src_mem, - - nv_clk_src_gpc, - nv_clk_src_rop, - nv_clk_src_hubk01, - nv_clk_src_hubk06, - nv_clk_src_hubk07, - nv_clk_src_copy, - nv_clk_src_daemon, - nv_clk_src_disp, - nv_clk_src_vdec, - - nv_clk_src_dom6, - - nv_clk_src_max, -}; - -struct nouveau_cstate { - struct list_head head; - u8 voltage; - u32 domain[nv_clk_src_max]; -}; - -struct nouveau_pstate { - struct list_head head; - struct list_head list; /* c-states */ - struct nouveau_cstate base; - u8 pstate; - u8 fanspeed; -}; - -struct nouveau_clock { - struct nouveau_subdev base; - - struct nouveau_clocks *domains; - struct nouveau_pstate bstate; - - struct list_head states; - int state_nr; - - struct work_struct work; - wait_queue_head_t wait; - atomic_t waiting; - - struct nvkm_notify pwrsrc_ntfy; - int pwrsrc; - int pstate; /* current */ - int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ - int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ - int astate; /* perfmon adjustment (base) */ - int tstate; /* thermal adjustment (max-) */ - int dstate; /* display adjustment (min+) */ - - bool allow_reclock; - - int (*read)(struct nouveau_clock *, enum nv_clk_src); - int (*calc)(struct nouveau_clock *, struct nouveau_cstate *); - int (*prog)(struct nouveau_clock *); - void (*tidy)(struct nouveau_clock *); - - /*XXX: die, these are here *only* to support the completely - * bat-shit insane what-was-nouveau_hw.c code - */ - int (*pll_calc)(struct nouveau_clock *, struct nvbios_pll *, - int clk, struct nouveau_pll_vals *pv); - int (*pll_prog)(struct nouveau_clock *, u32 reg1, - struct nouveau_pll_vals *pv); -}; - -static inline struct nouveau_clock * -nouveau_clock(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_CLOCK]; -} - -struct nouveau_clocks { - enum nv_clk_src name; - u8 bios; /* 0xff for none */ -#define NVKM_CLK_DOM_FLAG_CORE 0x01 - u8 flags; - const char *mname; - int mdiv; -}; - -#define nouveau_clock_create(p,e,o,i,r,s,n,d) \ - nouveau_clock_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \ - (void **)d) -#define nouveau_clock_destroy(p) ({ \ - struct nouveau_clock *clk = (p); \ - _nouveau_clock_dtor(nv_object(clk)); \ -}) -#define nouveau_clock_init(p) ({ \ - struct nouveau_clock *clk = (p); \ - _nouveau_clock_init(nv_object(clk)); \ -}) -#define nouveau_clock_fini(p,s) ({ \ - struct nouveau_clock *clk = (p); \ - _nouveau_clock_fini(nv_object(clk), (s)); \ -}) - -int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, - struct nouveau_clocks *, struct nouveau_pstate *, - int, bool, int, void **); -void _nouveau_clock_dtor(struct nouveau_object *); -int _nouveau_clock_init(struct nouveau_object *); -int _nouveau_clock_fini(struct nouveau_object *, bool); - -extern struct nouveau_oclass nv04_clock_oclass; -extern struct nouveau_oclass nv40_clock_oclass; -extern struct nouveau_oclass *nv50_clock_oclass; -extern struct nouveau_oclass *nv84_clock_oclass; -extern struct nouveau_oclass *nvaa_clock_oclass; -extern struct nouveau_oclass nva3_clock_oclass; -extern struct nouveau_oclass nvc0_clock_oclass; -extern struct nouveau_oclass nve0_clock_oclass; -extern struct nouveau_oclass gk20a_clock_oclass; - -int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq); -int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, - int clk, struct nouveau_pll_vals *); -int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, - struct nouveau_pll_vals *); -int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, - int clk, struct nouveau_pll_vals *); - -int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr); -int nouveau_clock_astate(struct nouveau_clock *, int req, int rel); -int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel); -int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h deleted file mode 100644 index e007a9d44683..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __NOUVEAU_DEVINIT_H__ -#define __NOUVEAU_DEVINIT_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_devinit { - struct nouveau_subdev base; - bool post; - void (*meminit)(struct nouveau_devinit *); - int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq); - u32 (*mmio)(struct nouveau_devinit *, u32 addr); -}; - -static inline struct nouveau_devinit * -nouveau_devinit(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_DEVINIT]; -} - -extern struct nouveau_oclass *nv04_devinit_oclass; -extern struct nouveau_oclass *nv05_devinit_oclass; -extern struct nouveau_oclass *nv10_devinit_oclass; -extern struct nouveau_oclass *nv1a_devinit_oclass; -extern struct nouveau_oclass *nv20_devinit_oclass; -extern struct nouveau_oclass *nv50_devinit_oclass; -extern struct nouveau_oclass *nv84_devinit_oclass; -extern struct nouveau_oclass *nv98_devinit_oclass; -extern struct nouveau_oclass *nva3_devinit_oclass; -extern struct nouveau_oclass *nvaf_devinit_oclass; -extern struct nouveau_oclass *nvc0_devinit_oclass; -extern struct nouveau_oclass *gm107_devinit_oclass; -extern struct nouveau_oclass *gm204_devinit_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h deleted file mode 100644 index 8d0032f15205..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h +++ /dev/null @@ -1,159 +0,0 @@ -#ifndef __NOUVEAU_FB_H__ -#define __NOUVEAU_FB_H__ - -#include <core/subdev.h> -#include <core/device.h> -#include <core/mm.h> - -#include <subdev/vm.h> - -/* memory type/access flags, do not match hardware values */ -#define NV_MEM_ACCESS_RO 1 -#define NV_MEM_ACCESS_WO 2 -#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) -#define NV_MEM_ACCESS_SYS 4 -#define NV_MEM_ACCESS_VM 8 -#define NV_MEM_ACCESS_NOSNOOP 16 - -#define NV_MEM_TARGET_VRAM 0 -#define NV_MEM_TARGET_PCI 1 -#define NV_MEM_TARGET_PCI_NOSNOOP 2 -#define NV_MEM_TARGET_VM 3 -#define NV_MEM_TARGET_GART 4 - -#define NV_MEM_TYPE_VM 0x7f -#define NV_MEM_COMP_VM 0x03 - -struct nouveau_mem { - struct drm_device *dev; - - struct nouveau_vma bar_vma; - struct nouveau_vma vma[2]; - u8 page_shift; - - struct nouveau_mm_node *tag; - struct list_head regions; - dma_addr_t *pages; - u32 memtype; - u64 offset; - u64 size; - struct sg_table *sg; -}; - -struct nouveau_fb_tile { - struct nouveau_mm_node *tag; - u32 addr; - u32 limit; - u32 pitch; - u32 zcomp; -}; - -struct nouveau_fb { - struct nouveau_subdev base; - - bool (*memtype_valid)(struct nouveau_fb *, u32 memtype); - - struct nouveau_ram *ram; - - struct nouveau_mm vram; - struct nouveau_mm tags; - - struct { - struct nouveau_fb_tile region[16]; - int regions; - void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); - void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags, - struct nouveau_fb_tile *); - void (*fini)(struct nouveau_fb *, int i, - struct nouveau_fb_tile *); - void (*prog)(struct nouveau_fb *, int i, - struct nouveau_fb_tile *); - } tile; -}; - -static inline struct nouveau_fb * -nouveau_fb(void *obj) -{ - /* fbram uses this before device subdev pointer is valid */ - if (nv_iclass(obj, NV_SUBDEV_CLASS) && - nv_subidx(obj) == NVDEV_SUBDEV_FB) - return obj; - - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FB]; -} - -extern struct nouveau_oclass *nv04_fb_oclass; -extern struct nouveau_oclass *nv10_fb_oclass; -extern struct nouveau_oclass *nv1a_fb_oclass; -extern struct nouveau_oclass *nv20_fb_oclass; -extern struct nouveau_oclass *nv25_fb_oclass; -extern struct nouveau_oclass *nv30_fb_oclass; -extern struct nouveau_oclass *nv35_fb_oclass; -extern struct nouveau_oclass *nv36_fb_oclass; -extern struct nouveau_oclass *nv40_fb_oclass; -extern struct nouveau_oclass *nv41_fb_oclass; -extern struct nouveau_oclass *nv44_fb_oclass; -extern struct nouveau_oclass *nv46_fb_oclass; -extern struct nouveau_oclass *nv47_fb_oclass; -extern struct nouveau_oclass *nv49_fb_oclass; -extern struct nouveau_oclass *nv4e_fb_oclass; -extern struct nouveau_oclass *nv50_fb_oclass; -extern struct nouveau_oclass *nv84_fb_oclass; -extern struct nouveau_oclass *nva3_fb_oclass; -extern struct nouveau_oclass *nvaa_fb_oclass; -extern struct nouveau_oclass *nvaf_fb_oclass; -extern struct nouveau_oclass *nvc0_fb_oclass; -extern struct nouveau_oclass *nve0_fb_oclass; -extern struct nouveau_oclass *gk20a_fb_oclass; -extern struct nouveau_oclass *gm107_fb_oclass; - -#include <subdev/bios/ramcfg.h> - -struct nouveau_ram_data { - struct list_head head; - struct nvbios_ramcfg bios; - u32 freq; -}; - -struct nouveau_ram { - struct nouveau_object base; - enum { - NV_MEM_TYPE_UNKNOWN = 0, - NV_MEM_TYPE_STOLEN, - NV_MEM_TYPE_SGRAM, - NV_MEM_TYPE_SDRAM, - NV_MEM_TYPE_DDR1, - NV_MEM_TYPE_DDR2, - NV_MEM_TYPE_DDR3, - NV_MEM_TYPE_GDDR2, - NV_MEM_TYPE_GDDR3, - NV_MEM_TYPE_GDDR4, - NV_MEM_TYPE_GDDR5 - } type; - u64 stolen; - u64 size; - u32 tags; - - int ranks; - int parts; - int part_mask; - - int (*get)(struct nouveau_fb *, u64 size, u32 align, - u32 size_nc, u32 type, struct nouveau_mem **); - void (*put)(struct nouveau_fb *, struct nouveau_mem **); - - int (*calc)(struct nouveau_fb *, u32 freq); - int (*prog)(struct nouveau_fb *); - void (*tidy)(struct nouveau_fb *); - u32 freq; - u32 mr[16]; - u32 mr1_nuts; - - struct nouveau_ram_data *next; - struct nouveau_ram_data former; - struct nouveau_ram_data xition; - struct nouveau_ram_data target; -}; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h b/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h deleted file mode 100644 index 2b1ddb2a9a7d..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __NOUVEAU_FUSE_H__ -#define __NOUVEAU_FUSE_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_fuse { - struct nouveau_subdev base; -}; - -static inline struct nouveau_fuse * -nouveau_fuse(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FUSE]; -} - -#define nouveau_fuse_create(p, e, o, d) \ - nouveau_fuse_create_((p), (e), (o), sizeof(**d), (void **)d) - -int nouveau_fuse_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_fuse_dtor(struct nouveau_object *); -int _nouveau_fuse_init(struct nouveau_object *); -#define _nouveau_fuse_fini _nouveau_subdev_fini - -extern struct nouveau_oclass g80_fuse_oclass; -extern struct nouveau_oclass gf100_fuse_oclass; -extern struct nouveau_oclass gm107_fuse_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h deleted file mode 100644 index f855140dbcb7..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef __NOUVEAU_GPIO_H__ -#define __NOUVEAU_GPIO_H__ - -#include <core/subdev.h> -#include <core/device.h> -#include <core/event.h> - -#include <subdev/bios.h> -#include <subdev/bios/gpio.h> - -struct nvkm_gpio_ntfy_req { -#define NVKM_GPIO_HI 0x01 -#define NVKM_GPIO_LO 0x02 -#define NVKM_GPIO_TOGGLED 0x03 - u8 mask; - u8 line; -}; - -struct nvkm_gpio_ntfy_rep { - u8 mask; -}; - -struct nouveau_gpio { - struct nouveau_subdev base; - - struct nvkm_event event; - - void (*reset)(struct nouveau_gpio *, u8 func); - int (*find)(struct nouveau_gpio *, int idx, u8 tag, u8 line, - struct dcb_gpio_func *); - int (*set)(struct nouveau_gpio *, int idx, u8 tag, u8 line, int state); - int (*get)(struct nouveau_gpio *, int idx, u8 tag, u8 line); -}; - -static inline struct nouveau_gpio * -nouveau_gpio(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_GPIO]; -} - -extern struct nouveau_oclass *nv10_gpio_oclass; -extern struct nouveau_oclass *nv50_gpio_oclass; -extern struct nouveau_oclass *nv94_gpio_oclass; -extern struct nouveau_oclass *nvd0_gpio_oclass; -extern struct nouveau_oclass *nve0_gpio_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h deleted file mode 100644 index d94ccacb40bf..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h +++ /dev/null @@ -1,136 +0,0 @@ -#ifndef __NOUVEAU_I2C_H__ -#define __NOUVEAU_I2C_H__ - -#include <core/subdev.h> -#include <core/device.h> - -#include <subdev/bios.h> -#include <subdev/bios/i2c.h> - -#define NV_I2C_PORT(n) (0x00 + (n)) -#define NV_I2C_AUX(n) (0x10 + (n)) -#define NV_I2C_EXT(n) (0x20 + (n)) -#define NV_I2C_DEFAULT(n) (0x80 + (n)) - -#define NV_I2C_TYPE_DCBI2C(n) (0x0000 | (n)) -#define NV_I2C_TYPE_EXTDDC(e) (0x0005 | (e) << 8) -#define NV_I2C_TYPE_EXTAUX(e) (0x0006 | (e) << 8) - -struct nvkm_i2c_ntfy_req { -#define NVKM_I2C_PLUG 0x01 -#define NVKM_I2C_UNPLUG 0x02 -#define NVKM_I2C_IRQ 0x04 -#define NVKM_I2C_DONE 0x08 -#define NVKM_I2C_ANY 0x0f - u8 mask; - u8 port; -}; - -struct nvkm_i2c_ntfy_rep { - u8 mask; -}; - -struct nouveau_i2c_port { - struct nouveau_object base; - struct i2c_adapter adapter; - struct mutex mutex; - - struct list_head head; - u8 index; - int aux; - - const struct nouveau_i2c_func *func; -}; - -struct nouveau_i2c_func { - void (*drive_scl)(struct nouveau_i2c_port *, int); - void (*drive_sda)(struct nouveau_i2c_port *, int); - int (*sense_scl)(struct nouveau_i2c_port *); - int (*sense_sda)(struct nouveau_i2c_port *); - - int (*aux)(struct nouveau_i2c_port *, bool, u8, u32, u8 *, u8); - int (*pattern)(struct nouveau_i2c_port *, int pattern); - int (*lnk_ctl)(struct nouveau_i2c_port *, int nr, int bw, bool enh); - int (*drv_ctl)(struct nouveau_i2c_port *, int lane, int sw, int pe); -}; - -struct nouveau_i2c_board_info { - struct i2c_board_info dev; - u8 udelay; /* set to 0 to use the standard delay */ -}; - -struct nouveau_i2c { - struct nouveau_subdev base; - struct nvkm_event event; - - struct nouveau_i2c_port *(*find)(struct nouveau_i2c *, u8 index); - struct nouveau_i2c_port *(*find_type)(struct nouveau_i2c *, u16 type); - int (*acquire_pad)(struct nouveau_i2c_port *, unsigned long timeout); - void (*release_pad)(struct nouveau_i2c_port *); - int (*acquire)(struct nouveau_i2c_port *, unsigned long timeout); - void (*release)(struct nouveau_i2c_port *); - int (*identify)(struct nouveau_i2c *, int index, - const char *what, struct nouveau_i2c_board_info *, - bool (*match)(struct nouveau_i2c_port *, - struct i2c_board_info *, void *), void *); - - wait_queue_head_t wait; - struct list_head ports; -}; - -static inline struct nouveau_i2c * -nouveau_i2c(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_I2C]; -} - -extern struct nouveau_oclass *nv04_i2c_oclass; -extern struct nouveau_oclass *nv4e_i2c_oclass; -extern struct nouveau_oclass *nv50_i2c_oclass; -extern struct nouveau_oclass *nv94_i2c_oclass; -extern struct nouveau_oclass *nvd0_i2c_oclass; -extern struct nouveau_oclass *gf117_i2c_oclass; -extern struct nouveau_oclass *nve0_i2c_oclass; -extern struct nouveau_oclass *gm204_i2c_oclass; - -static inline int -nv_rdi2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg) -{ - u8 val; - struct i2c_msg msgs[] = { - { .addr = addr, .flags = 0, .len = 1, .buf = ® }, - { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = &val }, - }; - - int ret = i2c_transfer(&port->adapter, msgs, 2); - if (ret != 2) - return -EIO; - - return val; -} - -static inline int -nv_wri2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg, u8 val) -{ - u8 buf[2] = { reg, val }; - struct i2c_msg msgs[] = { - { .addr = addr, .flags = 0, .len = 2, .buf = buf }, - }; - - int ret = i2c_transfer(&port->adapter, msgs, 1); - if (ret != 1) - return -EIO; - - return 0; -} - -static inline bool -nv_probe_i2c(struct nouveau_i2c_port *port, u8 addr) -{ - return nv_rdi2cr(port, addr, 0) >= 0; -} - -int nv_rdaux(struct nouveau_i2c_port *, u32 addr, u8 *data, u8 size); -int nv_wraux(struct nouveau_i2c_port *, u32 addr, u8 *data, u8 size); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h b/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h deleted file mode 100644 index 31df634c0fdc..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __NOUVEAU_IBUS_H__ -#define __NOUVEAU_IBUS_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_ibus { - struct nouveau_subdev base; -}; - -static inline struct nouveau_ibus * -nouveau_ibus(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_IBUS]; -} - -#define nouveau_ibus_create(p,e,o,d) \ - nouveau_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \ - sizeof(**d), (void **)d) -#define nouveau_ibus_destroy(p) \ - nouveau_subdev_destroy(&(p)->base) -#define nouveau_ibus_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_ibus_fini(p,s) \ - nouveau_subdev_fini(&(p)->base, (s)) - -#define _nouveau_ibus_dtor _nouveau_subdev_dtor -#define _nouveau_ibus_init _nouveau_subdev_init -#define _nouveau_ibus_fini _nouveau_subdev_fini - -extern struct nouveau_oclass nvc0_ibus_oclass; -extern struct nouveau_oclass nve0_ibus_oclass; -extern struct nouveau_oclass gk20a_ibus_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h b/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h deleted file mode 100644 index c1df26f3230c..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef __NOUVEAU_INSTMEM_H__ -#define __NOUVEAU_INSTMEM_H__ - -#include <core/subdev.h> -#include <core/device.h> -#include <core/mm.h> - -struct nouveau_instobj { - struct nouveau_object base; - struct list_head head; - u32 *suspend; - u64 addr; - u32 size; -}; - -static inline struct nouveau_instobj * -nv_memobj(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - if (unlikely(!nv_iclass(obj, NV_MEMOBJ_CLASS))) - nv_assert("BAD CAST -> NvMemObj, %08x", nv_hclass(obj)); -#endif - return obj; -} - -struct nouveau_instmem { - struct nouveau_subdev base; - struct list_head list; - - u32 reserved; - int (*alloc)(struct nouveau_instmem *, struct nouveau_object *, - u32 size, u32 align, struct nouveau_object **); -}; - -static inline struct nouveau_instmem * -nouveau_instmem(void *obj) -{ - /* nv04/nv40 impls need to create objects in their constructor, - * which is before the subdev pointer is valid - */ - if (nv_iclass(obj, NV_SUBDEV_CLASS) && - nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM) - return obj; - - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_INSTMEM]; -} - -extern struct nouveau_oclass *nv04_instmem_oclass; -extern struct nouveau_oclass *nv40_instmem_oclass; -extern struct nouveau_oclass *nv50_instmem_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h b/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h deleted file mode 100644 index b909a7363f6b..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __NOUVEAU_LTC_H__ -#define __NOUVEAU_LTC_H__ - -#include <core/subdev.h> -#include <core/device.h> - -#define NOUVEAU_LTC_MAX_ZBC_CNT 16 - -struct nouveau_mm_node; - -struct nouveau_ltc { - struct nouveau_subdev base; - - int (*tags_alloc)(struct nouveau_ltc *, u32 count, - struct nouveau_mm_node **); - void (*tags_free)(struct nouveau_ltc *, struct nouveau_mm_node **); - void (*tags_clear)(struct nouveau_ltc *, u32 first, u32 count); - - int zbc_min; - int zbc_max; - int (*zbc_color_get)(struct nouveau_ltc *, int index, const u32[4]); - int (*zbc_depth_get)(struct nouveau_ltc *, int index, const u32); -}; - -static inline struct nouveau_ltc * -nouveau_ltc(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_LTC]; -} - -extern struct nouveau_oclass *gf100_ltc_oclass; -extern struct nouveau_oclass *gk104_ltc_oclass; -extern struct nouveau_oclass *gm107_ltc_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h b/drivers/gpu/drm/nouveau/core/include/subdev/mc.h deleted file mode 100644 index 568e4dfc5e9e..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __NOUVEAU_MC_H__ -#define __NOUVEAU_MC_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_mc { - struct nouveau_subdev base; - bool use_msi; - unsigned int irq; - void (*unk260)(struct nouveau_mc *, u32); -}; - -static inline struct nouveau_mc * -nouveau_mc(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MC]; -} - -extern struct nouveau_oclass *nv04_mc_oclass; -extern struct nouveau_oclass *nv40_mc_oclass; -extern struct nouveau_oclass *nv44_mc_oclass; -extern struct nouveau_oclass *nv4c_mc_oclass; -extern struct nouveau_oclass *nv50_mc_oclass; -extern struct nouveau_oclass *nv94_mc_oclass; -extern struct nouveau_oclass *nv98_mc_oclass; -extern struct nouveau_oclass *nvc0_mc_oclass; -extern struct nouveau_oclass *nvc3_mc_oclass; -extern struct nouveau_oclass *gk20a_mc_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h b/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h deleted file mode 100644 index b93b152cb566..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef __NOUVEAU_MXM_H__ -#define __NOUVEAU_MXM_H__ - -#include <core/subdev.h> -#include <core/device.h> - -#define MXM_SANITISE_DCB 0x00000001 - -struct nouveau_mxm { - struct nouveau_subdev base; - u32 action; - u8 *mxms; -}; - -static inline struct nouveau_mxm * -nouveau_mxm(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MXM]; -} - -#define nouveau_mxm_create(p,e,o,d) \ - nouveau_mxm_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_mxm_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_mxm_fini(p,s) \ - nouveau_subdev_fini(&(p)->base, (s)) -int nouveau_mxm_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void nouveau_mxm_destroy(struct nouveau_mxm *); - -#define _nouveau_mxm_dtor _nouveau_subdev_dtor -#define _nouveau_mxm_init _nouveau_subdev_init -#define _nouveau_mxm_fini _nouveau_subdev_fini - -extern struct nouveau_oclass nv50_mxm_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h deleted file mode 100644 index f2427bf5aeed..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef __NOUVEAU_PWR_H__ -#define __NOUVEAU_PWR_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_pwr { - struct nouveau_subdev base; - - struct { - u32 base; - u32 size; - } send; - - struct { - u32 base; - u32 size; - - struct work_struct work; - wait_queue_head_t wait; - u32 process; - u32 message; - u32 data[2]; - } recv; - - int (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32); - void (*pgob)(struct nouveau_pwr *, bool); -}; - -static inline struct nouveau_pwr * -nouveau_pwr(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_PWR]; -} - -extern struct nouveau_oclass *nva3_pwr_oclass; -extern struct nouveau_oclass *nvc0_pwr_oclass; -extern struct nouveau_oclass *nvd0_pwr_oclass; -extern struct nouveau_oclass *gk104_pwr_oclass; -extern struct nouveau_oclass *nv108_pwr_oclass; - -/* interface to MEMX process running on PPWR */ -struct nouveau_memx; -int nouveau_memx_init(struct nouveau_pwr *, struct nouveau_memx **); -int nouveau_memx_fini(struct nouveau_memx **, bool exec); -void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data); -void nouveau_memx_wait(struct nouveau_memx *, - u32 addr, u32 mask, u32 data, u32 nsec); -void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec); -void nouveau_memx_wait_vblank(struct nouveau_memx *); -void nouveau_memx_train(struct nouveau_memx *); -int nouveau_memx_train_result(struct nouveau_pwr *, u32 *, int); -void nouveau_memx_block(struct nouveau_memx *); -void nouveau_memx_unblock(struct nouveau_memx *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h b/drivers/gpu/drm/nouveau/core/include/subdev/therm.h deleted file mode 100644 index a437597dcafc..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h +++ /dev/null @@ -1,83 +0,0 @@ -#ifndef __NOUVEAU_THERM_H__ -#define __NOUVEAU_THERM_H__ - -#include <core/device.h> -#include <core/subdev.h> - -enum nouveau_therm_fan_mode { - NOUVEAU_THERM_CTRL_NONE = 0, - NOUVEAU_THERM_CTRL_MANUAL = 1, - NOUVEAU_THERM_CTRL_AUTO = 2, -}; - -enum nouveau_therm_attr_type { - NOUVEAU_THERM_ATTR_FAN_MIN_DUTY = 0, - NOUVEAU_THERM_ATTR_FAN_MAX_DUTY = 1, - NOUVEAU_THERM_ATTR_FAN_MODE = 2, - - NOUVEAU_THERM_ATTR_THRS_FAN_BOOST = 10, - NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST = 11, - NOUVEAU_THERM_ATTR_THRS_DOWN_CLK = 12, - NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST = 13, - NOUVEAU_THERM_ATTR_THRS_CRITICAL = 14, - NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST = 15, - NOUVEAU_THERM_ATTR_THRS_SHUTDOWN = 16, - NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST = 17, -}; - -struct nouveau_therm { - struct nouveau_subdev base; - - int (*pwm_ctrl)(struct nouveau_therm *, int line, bool); - int (*pwm_get)(struct nouveau_therm *, int line, u32 *, u32 *); - int (*pwm_set)(struct nouveau_therm *, int line, u32, u32); - int (*pwm_clock)(struct nouveau_therm *, int line); - - int (*fan_get)(struct nouveau_therm *); - int (*fan_set)(struct nouveau_therm *, int); - int (*fan_sense)(struct nouveau_therm *); - - int (*temp_get)(struct nouveau_therm *); - - int (*attr_get)(struct nouveau_therm *, enum nouveau_therm_attr_type); - int (*attr_set)(struct nouveau_therm *, - enum nouveau_therm_attr_type, int); -}; - -static inline struct nouveau_therm * -nouveau_therm(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_THERM]; -} - -#define nouveau_therm_create(p,e,o,d) \ - nouveau_therm_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_therm_destroy(p) ({ \ - struct nouveau_therm *therm = (p); \ - _nouveau_therm_dtor(nv_object(therm)); \ -}) -#define nouveau_therm_init(p) ({ \ - struct nouveau_therm *therm = (p); \ - _nouveau_therm_init(nv_object(therm)); \ -}) -#define nouveau_therm_fini(p,s) ({ \ - struct nouveau_therm *therm = (p); \ - _nouveau_therm_init(nv_object(therm), (s)); \ -}) - -int nouveau_therm_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_therm_dtor(struct nouveau_object *); -int _nouveau_therm_init(struct nouveau_object *); -int _nouveau_therm_fini(struct nouveau_object *, bool); - -int nouveau_therm_cstate(struct nouveau_therm *, int, int); - -extern struct nouveau_oclass nv40_therm_oclass; -extern struct nouveau_oclass nv50_therm_oclass; -extern struct nouveau_oclass nv84_therm_oclass; -extern struct nouveau_oclass nva3_therm_oclass; -extern struct nouveau_oclass nvd0_therm_oclass; -extern struct nouveau_oclass gm107_therm_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h b/drivers/gpu/drm/nouveau/core/include/subdev/timer.h deleted file mode 100644 index db9be803a874..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __NOUVEAU_TIMER_H__ -#define __NOUVEAU_TIMER_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_alarm { - struct list_head head; - u64 timestamp; - void (*func)(struct nouveau_alarm *); -}; - -static inline void -nouveau_alarm_init(struct nouveau_alarm *alarm, - void (*func)(struct nouveau_alarm *)) -{ - INIT_LIST_HEAD(&alarm->head); - alarm->func = func; -} - -bool nouveau_timer_wait_eq(void *, u64 nsec, u32 addr, u32 mask, u32 data); -bool nouveau_timer_wait_ne(void *, u64 nsec, u32 addr, u32 mask, u32 data); -bool nouveau_timer_wait_cb(void *, u64 nsec, bool (*func)(void *), void *data); -void nouveau_timer_alarm(void *, u32 nsec, struct nouveau_alarm *); -void nouveau_timer_alarm_cancel(void *, struct nouveau_alarm *); - -#define NV_WAIT_DEFAULT 2000000000ULL -#define nv_wait(o,a,m,v) \ - nouveau_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v)) -#define nv_wait_ne(o,a,m,v) \ - nouveau_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v)) -#define nv_wait_cb(o,c,d) \ - nouveau_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d)) - -struct nouveau_timer { - struct nouveau_subdev base; - u64 (*read)(struct nouveau_timer *); - void (*alarm)(struct nouveau_timer *, u64 time, struct nouveau_alarm *); - void (*alarm_cancel)(struct nouveau_timer *, struct nouveau_alarm *); -}; - -static inline struct nouveau_timer * -nouveau_timer(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_TIMER]; -} - -#define nouveau_timer_create(p,e,o,d) \ - nouveau_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \ - sizeof(**d), (void **)d) -#define nouveau_timer_destroy(p) \ - nouveau_subdev_destroy(&(p)->base) -#define nouveau_timer_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_timer_fini(p,s) \ - nouveau_subdev_fini(&(p)->base, (s)) - -int nouveau_timer_create_(struct nouveau_object *, struct nouveau_engine *, - struct nouveau_oclass *, int size, void **); - -extern struct nouveau_oclass nv04_timer_oclass; -extern struct nouveau_oclass gk20a_timer_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h deleted file mode 100644 index c9509039f94b..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#ifndef __NOUVEAU_VM_H__ -#define __NOUVEAU_VM_H__ - -#include <core/object.h> -#include <core/subdev.h> -#include <core/device.h> -#include <core/mm.h> - -struct nouveau_vm_pgt { - struct nouveau_gpuobj *obj[2]; - u32 refcount[2]; -}; - -struct nouveau_vm_pgd { - struct list_head head; - struct nouveau_gpuobj *obj; -}; - -struct nouveau_gpuobj; -struct nouveau_mem; - -struct nouveau_vma { - struct list_head head; - int refcount; - struct nouveau_vm *vm; - struct nouveau_mm_node *node; - u64 offset; - u32 access; -}; - -struct nouveau_vm { - struct nouveau_vmmgr *vmm; - struct nouveau_mm mm; - struct kref refcount; - - struct list_head pgd_list; - atomic_t engref[NVDEV_SUBDEV_NR]; - - struct nouveau_vm_pgt *pgt; - u32 fpde; - u32 lpde; -}; - -struct nouveau_vmmgr { - struct nouveau_subdev base; - - u64 limit; - u8 dma_bits; - u32 pgt_bits; - u8 spg_shift; - u8 lpg_shift; - - int (*create)(struct nouveau_vmmgr *, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **); - - void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, - struct nouveau_gpuobj *pgt[2]); - void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *, - struct nouveau_mem *, u32 pte, u32 cnt, - u64 phys, u64 delta); - void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *, - struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *); - void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt); - void (*flush)(struct nouveau_vm *); -}; - -static inline struct nouveau_vmmgr * -nouveau_vmmgr(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VM]; -} - -#define nouveau_vmmgr_create(p,e,o,i,f,d) \ - nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d)) -#define nouveau_vmmgr_destroy(p) \ - nouveau_subdev_destroy(&(p)->base) -#define nouveau_vmmgr_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_vmmgr_fini(p,s) \ - nouveau_subdev_fini(&(p)->base, (s)) - -#define _nouveau_vmmgr_dtor _nouveau_subdev_dtor -#define _nouveau_vmmgr_init _nouveau_subdev_init -#define _nouveau_vmmgr_fini _nouveau_subdev_fini - -extern struct nouveau_oclass nv04_vmmgr_oclass; -extern struct nouveau_oclass nv41_vmmgr_oclass; -extern struct nouveau_oclass nv44_vmmgr_oclass; -extern struct nouveau_oclass nv50_vmmgr_oclass; -extern struct nouveau_oclass nvc0_vmmgr_oclass; - -int nv04_vm_create(struct nouveau_vmmgr *, u64, u64, u64, - struct nouveau_vm **); -void nv04_vmmgr_dtor(struct nouveau_object *); - -/* nouveau_vm.c */ -int nouveau_vm_create(struct nouveau_vmmgr *, u64 offset, u64 length, - u64 mm_offset, u32 block, struct nouveau_vm **); -int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **); -int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **, - struct nouveau_gpuobj *pgd); -int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift, - u32 access, struct nouveau_vma *); -void nouveau_vm_put(struct nouveau_vma *); -void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *); -void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); -void nouveau_vm_unmap(struct nouveau_vma *); -void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/volt.h b/drivers/gpu/drm/nouveau/core/include/subdev/volt.h deleted file mode 100644 index 67db5e58880d..000000000000 --- a/drivers/gpu/drm/nouveau/core/include/subdev/volt.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef __NOUVEAU_VOLT_H__ -#define __NOUVEAU_VOLT_H__ - -#include <core/subdev.h> -#include <core/device.h> - -struct nouveau_voltage { - u32 uv; - u8 id; -}; - -struct nouveau_volt { - struct nouveau_subdev base; - - int (*vid_get)(struct nouveau_volt *); - int (*get)(struct nouveau_volt *); - int (*vid_set)(struct nouveau_volt *, u8 vid); - int (*set)(struct nouveau_volt *, u32 uv); - int (*set_id)(struct nouveau_volt *, u8 id, int condition); - - u8 vid_mask; - u8 vid_nr; - struct { - u32 uv; - u8 vid; - } vid[256]; -}; - -static inline struct nouveau_volt * -nouveau_volt(void *obj) -{ - return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VOLT]; -} - -#define nouveau_volt_create(p, e, o, d) \ - nouveau_volt_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_volt_destroy(p) ({ \ - struct nouveau_volt *v = (p); \ - _nouveau_volt_dtor(nv_object(v)); \ -}) -#define nouveau_volt_init(p) ({ \ - struct nouveau_volt *v = (p); \ - _nouveau_volt_init(nv_object(v)); \ -}) -#define nouveau_volt_fini(p,s) \ - nouveau_subdev_fini((p), (s)) - -int nouveau_volt_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_volt_dtor(struct nouveau_object *); -int _nouveau_volt_init(struct nouveau_object *); -#define _nouveau_volt_fini _nouveau_subdev_fini - -extern struct nouveau_oclass nv40_volt_oclass; -extern struct nouveau_oclass gk20a_volt_oclass; - -int nouveau_voltgpio_init(struct nouveau_volt *); -int nouveau_voltgpio_get(struct nouveau_volt *); -int nouveau_voltgpio_set(struct nouveau_volt *, u8); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c deleted file mode 100644 index b1adc69efd88..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <core/object.h> - -#include <subdev/fb.h> -#include <subdev/vm.h> - -#include "priv.h" - -struct nouveau_barobj { - struct nouveau_object base; - struct nouveau_vma vma; - void __iomem *iomem; -}; - -static int -nouveau_barobj_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_device *device = nv_device(parent); - struct nouveau_bar *bar = (void *)engine; - struct nouveau_mem *mem = data; - struct nouveau_barobj *barobj; - int ret; - - ret = nouveau_object_create(parent, engine, oclass, 0, &barobj); - *pobject = nv_object(barobj); - if (ret) - return ret; - - ret = bar->kmap(bar, mem, NV_MEM_ACCESS_RW, &barobj->vma); - if (ret) - return ret; - - barobj->iomem = ioremap(nv_device_resource_start(device, 3) + - (u32)barobj->vma.offset, mem->size << 12); - if (!barobj->iomem) { - nv_warn(bar, "PRAMIN ioremap failed\n"); - return -ENOMEM; - } - - return 0; -} - -static void -nouveau_barobj_dtor(struct nouveau_object *object) -{ - struct nouveau_bar *bar = (void *)object->engine; - struct nouveau_barobj *barobj = (void *)object; - if (barobj->vma.node) { - if (barobj->iomem) - iounmap(barobj->iomem); - bar->unmap(bar, &barobj->vma); - } - nouveau_object_destroy(&barobj->base); -} - -static u32 -nouveau_barobj_rd32(struct nouveau_object *object, u64 addr) -{ - struct nouveau_barobj *barobj = (void *)object; - return ioread32_native(barobj->iomem + addr); -} - -static void -nouveau_barobj_wr32(struct nouveau_object *object, u64 addr, u32 data) -{ - struct nouveau_barobj *barobj = (void *)object; - iowrite32_native(data, barobj->iomem + addr); -} - -static struct nouveau_oclass -nouveau_barobj_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nouveau_barobj_ctor, - .dtor = nouveau_barobj_dtor, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - .rd32 = nouveau_barobj_rd32, - .wr32 = nouveau_barobj_wr32, - }, -}; - -int -nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent, - struct nouveau_mem *mem, struct nouveau_object **pobject) -{ - struct nouveau_object *engine = nv_object(bar); - struct nouveau_object *gpuobj; - int ret = nouveau_object_ctor(parent, engine, &nouveau_barobj_oclass, - mem, 0, &gpuobj); - if (ret == 0) - *pobject = gpuobj; - return ret; -} - -int -nouveau_bar_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) -{ - struct nouveau_bar *bar; - int ret; - - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "BARCTL", - "bar", length, pobject); - bar = *pobject; - if (ret) - return ret; - - return 0; -} - -void -nouveau_bar_destroy(struct nouveau_bar *bar) -{ - nouveau_subdev_destroy(&bar->base); -} - -void -_nouveau_bar_dtor(struct nouveau_object *object) -{ - struct nouveau_bar *bar = (void *)object; - nouveau_bar_destroy(bar); -} diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c deleted file mode 100644 index 05a278bab247..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <core/gpuobj.h> - -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/vm.h> - -#include "priv.h" - -struct nvc0_bar_priv_vm { - struct nouveau_gpuobj *mem; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *vm; -}; - -struct nvc0_bar_priv { - struct nouveau_bar base; - spinlock_t lock; - struct nvc0_bar_priv_vm bar[2]; -}; - -static int -nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem, - u32 flags, struct nouveau_vma *vma) -{ - struct nvc0_bar_priv *priv = (void *)bar; - int ret; - - ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma); - if (ret) - return ret; - - nouveau_vm_map(vma, mem); - return 0; -} - -static int -nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem, - u32 flags, struct nouveau_vma *vma) -{ - struct nvc0_bar_priv *priv = (void *)bar; - int ret; - - ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12, - mem->page_shift, flags, vma); - if (ret) - return ret; - - nouveau_vm_map(vma, mem); - return 0; -} - -static void -nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma) -{ - nouveau_vm_unmap(vma); - nouveau_vm_put(vma); -} - -static int -nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm, - int bar_nr) -{ - struct nouveau_device *device = nv_device(&priv->base); - struct nouveau_vm *vm; - resource_size_t bar_len; - int ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, - &bar_vm->mem); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, - &bar_vm->pgd); - if (ret) - return ret; - - bar_len = nv_device_resource_len(device, bar_nr); - - ret = nouveau_vm_new(device, 0, bar_len, 0, &vm); - if (ret) - return ret; - - atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); - - /* - * Bootstrap page table lookup. - */ - if (bar_nr == 3) { - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (bar_len >> 12) * 8, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, - &vm->pgt[0].obj[0]); - vm->pgt[0].refcount[0] = 1; - if (ret) - return ret; - } - - ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd); - nouveau_vm_ref(NULL, &vm, NULL); - if (ret) - return ret; - - nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); - nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); - nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); - nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); - - return 0; -} - -int -nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_device *device = nv_device(parent); - struct nvc0_bar_priv *priv; - bool has_bar3 = nv_device_resource_len(device, 3) != 0; - int ret; - - ret = nouveau_bar_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - /* BAR3 */ - if (has_bar3) { - ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3); - if (ret) - return ret; - priv->base.alloc = nouveau_bar_alloc; - priv->base.kmap = nvc0_bar_kmap; - } - - /* BAR1 */ - ret = nvc0_bar_init_vm(priv, &priv->bar[1], 1); - if (ret) - return ret; - - priv->base.umap = nvc0_bar_umap; - priv->base.unmap = nvc0_bar_unmap; - priv->base.flush = nv84_bar_flush; - spin_lock_init(&priv->lock); - return 0; -} - -void -nvc0_bar_dtor(struct nouveau_object *object) -{ - struct nvc0_bar_priv *priv = (void *)object; - - nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd); - nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd); - nouveau_gpuobj_ref(NULL, &priv->bar[1].mem); - - if (priv->bar[0].vm) { - nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]); - nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd); - } - nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd); - nouveau_gpuobj_ref(NULL, &priv->bar[0].mem); - - nouveau_bar_destroy(&priv->base); -} - -int -nvc0_bar_init(struct nouveau_object *object) -{ - struct nvc0_bar_priv *priv = (void *)object; - int ret; - - ret = nouveau_bar_init(&priv->base); - if (ret) - return ret; - - nv_mask(priv, 0x000200, 0x00000100, 0x00000000); - nv_mask(priv, 0x000200, 0x00000100, 0x00000100); - - nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12); - if (priv->bar[0].mem) - nv_wr32(priv, 0x001714, - 0xc0000000 | priv->bar[0].mem->addr >> 12); - return 0; -} - -struct nouveau_oclass -nvc0_bar_oclass = { - .handle = NV_SUBDEV(BAR, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_bar_ctor, - .dtor = nvc0_bar_dtor, - .init = nvc0_bar_init, - .fini = _nouveau_bar_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h deleted file mode 100644 index 3ee8b1476d00..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef __NVKM_BAR_PRIV_H__ -#define __NVKM_BAR_PRIV_H__ - -#include <subdev/bar.h> - -#define nouveau_bar_create(p,e,o,d) \ - nouveau_bar_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_bar_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_bar_fini(p,s) \ - nouveau_subdev_fini(&(p)->base, (s)) - -int nouveau_bar_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void nouveau_bar_destroy(struct nouveau_bar *); - -void _nouveau_bar_dtor(struct nouveau_object *); -#define _nouveau_bar_init _nouveau_subdev_init -#define _nouveau_bar_fini _nouveau_subdev_fini - -int nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *, - struct nouveau_mem *, struct nouveau_object **); - -void nv84_bar_flush(struct nouveau_bar *); - -int nvc0_bar_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nvc0_bar_dtor(struct nouveau_object *); -int nvc0_bar_init(struct nouveau_object *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h deleted file mode 100644 index 4d7602450a20..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __NVKM_BUS_NV04_H__ -#define __NVKM_BUS_NV04_H__ - -#include <subdev/bus.h> - -struct nv04_bus_priv { - struct nouveau_bus base; -}; - -int nv04_bus_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -int nv50_bus_init(struct nouveau_object *); -void nv50_bus_intr(struct nouveau_subdev *); - -struct nv04_bus_impl { - struct nouveau_oclass base; - void (*intr)(struct nouveau_subdev *); - int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32); - u32 hwsq_size; -}; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h deleted file mode 100644 index f10917d789e8..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __NVKM_CLK_NV50_H__ -#define __NVKM_CLK_NV50_H__ - -#include <subdev/bus.h> -#include <subdev/bus/hwsq.h> -#include <subdev/clock.h> - -struct nv50_clock_hwsq { - struct hwsq base; - struct hwsq_reg r_fifo; - struct hwsq_reg r_spll[2]; - struct hwsq_reg r_nvpll[2]; - struct hwsq_reg r_divs; - struct hwsq_reg r_mast; -}; - -struct nv50_clock_priv { - struct nouveau_clock base; - struct nv50_clock_hwsq hwsq; -}; - -int nv50_clock_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); - -struct nv50_clock_oclass { - struct nouveau_oclass base; - struct nouveau_clocks *domains; -}; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h deleted file mode 100644 index a45a1038b12f..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __NVKM_CLK_NVA3_H__ -#define __NVKM_CLK_NVA3_H__ - -#include <subdev/clock.h> - -struct nva3_clock_info { - u32 clk; - u32 pll; - enum { - NVA3_HOST_277, - NVA3_HOST_CLK, - } host_out; - u32 fb_delay; -}; - -int nva3_pll_info(struct nouveau_clock *, int, u32, u32, - struct nva3_clock_info *); -int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags); -void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags); -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h b/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h deleted file mode 100644 index 445b14c33a98..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __NOUVEAU_PLL_H__ -#define __NOUVEAU_PLL_H__ - -int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, - int *N1, int *M1, int *N2, int *M2, int *P); -int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, - int *N, int *fN, int *M, int *P); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h deleted file mode 100644 index 23470a57510c..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __NVKM_DEVINIT_NV04_H__ -#define __NVKM_DEVINIT_NV04_H__ - -#include "priv.h" - -struct nv04_devinit_priv { - struct nouveau_devinit base; - u8 owner; -}; - -int nv04_devinit_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nv04_devinit_dtor(struct nouveau_object *); -int nv04_devinit_init(struct nouveau_object *); -int nv04_devinit_fini(struct nouveau_object *, bool); -int nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32); - -void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); -void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); -void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h deleted file mode 100644 index f412bb7f780e..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __NVKM_DEVINIT_NV50_H__ -#define __NVKM_DEVINIT_NV50_H__ - -#include "priv.h" - -struct nv50_devinit_priv { - struct nouveau_devinit base; - u32 r001540; -}; - -int nv50_devinit_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -int nv50_devinit_init(struct nouveau_object *); -int nv50_devinit_pll_set(struct nouveau_devinit *, u32, u32); - -int nva3_devinit_pll_set(struct nouveau_devinit *, u32, u32); - -int nvc0_devinit_pll_set(struct nouveau_devinit *, u32, u32); - -u64 gm107_devinit_disable(struct nouveau_devinit *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h deleted file mode 100644 index cbcd51852472..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef __NVKM_DEVINIT_PRIV_H__ -#define __NVKM_DEVINIT_PRIV_H__ - -#include <subdev/bios.h> -#include <subdev/bios/pll.h> -#include <subdev/bios/init.h> -#include <subdev/clock/pll.h> -#include <subdev/devinit.h> - -struct nouveau_devinit_impl { - struct nouveau_oclass base; - void (*meminit)(struct nouveau_devinit *); - int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq); - u64 (*disable)(struct nouveau_devinit *); - u32 (*mmio)(struct nouveau_devinit *, u32); - int (*post)(struct nouveau_subdev *, bool); -}; - -#define nouveau_devinit_create(p,e,o,d) \ - nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_devinit_destroy(p) ({ \ - struct nouveau_devinit *d = (p); \ - _nouveau_devinit_dtor(nv_object(d)); \ -}) -#define nouveau_devinit_init(p) ({ \ - struct nouveau_devinit *d = (p); \ - _nouveau_devinit_init(nv_object(d)); \ -}) -#define nouveau_devinit_fini(p,s) ({ \ - struct nouveau_devinit *d = (p); \ - _nouveau_devinit_fini(nv_object(d), (s)); \ -}) - -int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_devinit_dtor(struct nouveau_object *); -int _nouveau_devinit_init(struct nouveau_object *); -int _nouveau_devinit_fini(struct nouveau_object *, bool suspend); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h deleted file mode 100644 index 06ce71f87a74..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef __NVKM_FB_NV04_H__ -#define __NVKM_FB_NV04_H__ - -#include "priv.h" - -struct nv04_fb_priv { - struct nouveau_fb base; -}; - -int nv04_fb_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); - -struct nv04_fb_impl { - struct nouveau_fb_impl base; - struct { - int regions; - void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); - void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags, - struct nouveau_fb_tile *); - void (*fini)(struct nouveau_fb *, int i, - struct nouveau_fb_tile *); - void (*prog)(struct nouveau_fb *, int i, - struct nouveau_fb_tile *); - } tile; -}; - -void nv10_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); -void nv10_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *); -void nv10_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); - -void nv20_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); -void nv20_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *); -void nv20_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); - -int nv30_fb_init(struct nouveau_object *); -void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); - -void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags, - struct nouveau_fb_tile *); - -int nv41_fb_init(struct nouveau_object *); -void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); - -int nv44_fb_init(struct nouveau_object *); -void nv44_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); - -void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h deleted file mode 100644 index 581f808527f2..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __NVKM_FB_NV40_H__ -#define __NVKM_FB_NV40_H__ - -#include "priv.h" - -struct nv40_ram { - struct nouveau_ram base; - u32 ctrl; - u32 coef; -}; - - -int nv40_ram_calc(struct nouveau_fb *, u32); -int nv40_ram_prog(struct nouveau_fb *); -void nv40_ram_tidy(struct nouveau_fb *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h deleted file mode 100644 index c5e5a888c607..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __NVKM_FB_NV50_H__ -#define __NVKM_FB_NV50_H__ - -#include "priv.h" - -struct nv50_fb_priv { - struct nouveau_fb base; - struct page *r100c08_page; - dma_addr_t r100c08; -}; - -int nv50_fb_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nv50_fb_dtor(struct nouveau_object *); -int nv50_fb_init(struct nouveau_object *); - -struct nv50_fb_impl { - struct nouveau_fb_impl base; - u32 trap; -}; - -#define nv50_ram_create(p,e,o,d) \ - nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d) -int nv50_ram_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -int nv50_ram_get(struct nouveau_fb *, u64 size, u32 align, u32 ncmin, - u32 memtype, struct nouveau_mem **); -void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **); -void __nv50_ram_put(struct nouveau_fb *, struct nouveau_mem *); -extern int nv50_fb_memtype[0x80]; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h deleted file mode 100644 index 705a06d755ad..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __NVKM_RAM_NVC0_H__ -#define __NVKM_RAM_NVC0_H__ - -#include "priv.h" -#include "nv50.h" - -struct nvc0_fb_priv { - struct nouveau_fb base; - struct page *r100c10_page; - dma_addr_t r100c10; -}; - -int nvc0_fb_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nvc0_fb_dtor(struct nouveau_object *); -int nvc0_fb_init(struct nouveau_object *); -bool nvc0_fb_memtype_valid(struct nouveau_fb *, u32); - - -#define nvc0_ram_create(p,e,o,m,d) \ - nvc0_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d) -int nvc0_ram_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, u32, int, void **); -int nvc0_ram_get(struct nouveau_fb *, u64, u32, u32, u32, - struct nouveau_mem **); -void nvc0_ram_put(struct nouveau_fb *, struct nouveau_mem **); - -int nve0_ram_init(struct nouveau_object*); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h deleted file mode 100644 index 283863f7aa9b..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef __NVKM_FB_PRIV_H__ -#define __NVKM_FB_PRIV_H__ - -#include <subdev/fb.h> - -#define nouveau_ram_create(p,e,o,d) \ - nouveau_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d) -#define nouveau_ram_destroy(p) \ - nouveau_object_destroy(&(p)->base) -#define nouveau_ram_init(p) \ - nouveau_object_init(&(p)->base) -#define nouveau_ram_fini(p,s) \ - nouveau_object_fini(&(p)->base, (s)) - -#define nouveau_ram_create_(p,e,o,s,d) \ - nouveau_object_create_((p), (e), (o), 0, (s), (void **)d) -#define _nouveau_ram_dtor nouveau_object_destroy -#define _nouveau_ram_init nouveau_object_init -#define _nouveau_ram_fini nouveau_object_fini - -extern struct nouveau_oclass nv04_ram_oclass; -extern struct nouveau_oclass nv10_ram_oclass; -extern struct nouveau_oclass nv1a_ram_oclass; -extern struct nouveau_oclass nv20_ram_oclass; -extern struct nouveau_oclass nv40_ram_oclass; -extern struct nouveau_oclass nv41_ram_oclass; -extern struct nouveau_oclass nv44_ram_oclass; -extern struct nouveau_oclass nv49_ram_oclass; -extern struct nouveau_oclass nv4e_ram_oclass; -extern struct nouveau_oclass nv50_ram_oclass; -extern struct nouveau_oclass nva3_ram_oclass; -extern struct nouveau_oclass nvaa_ram_oclass; -extern struct nouveau_oclass nvc0_ram_oclass; -extern struct nouveau_oclass nve0_ram_oclass; -extern struct nouveau_oclass gk20a_ram_oclass; -extern struct nouveau_oclass gm107_ram_oclass; - -int nouveau_sddr2_calc(struct nouveau_ram *ram); -int nouveau_sddr3_calc(struct nouveau_ram *ram); -int nouveau_gddr3_calc(struct nouveau_ram *ram); -int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); - -#define nouveau_fb_create(p,e,c,d) \ - nouveau_fb_create_((p), (e), (c), sizeof(**d), (void **)d) -#define nouveau_fb_destroy(p) ({ \ - struct nouveau_fb *pfb = (p); \ - _nouveau_fb_dtor(nv_object(pfb)); \ -}) -#define nouveau_fb_init(p) ({ \ - struct nouveau_fb *pfb = (p); \ - _nouveau_fb_init(nv_object(pfb)); \ -}) -#define nouveau_fb_fini(p,s) ({ \ - struct nouveau_fb *pfb = (p); \ - _nouveau_fb_fini(nv_object(pfb), (s)); \ -}) - -int nouveau_fb_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_fb_dtor(struct nouveau_object *); -int _nouveau_fb_init(struct nouveau_object *); -int _nouveau_fb_fini(struct nouveau_object *, bool); - -struct nouveau_fb_impl { - struct nouveau_oclass base; - struct nouveau_oclass *ram; - bool (*memtype)(struct nouveau_fb *, u32); -}; - -bool nv04_fb_memtype_valid(struct nouveau_fb *, u32 memtype); -bool nv50_fb_memtype_valid(struct nouveau_fb *, u32 memtype); - -struct nouveau_bios; -int nouveau_fb_bios_memtype(struct nouveau_bios *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c deleted file mode 100644 index 00f2ca7e44a5..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nv50.h" - -static int -nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 datasize, - struct nouveau_object **pobject) -{ - const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ - const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; - int ret; - - ret = nouveau_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; - - ram->size = nv_rd32(pfb, 0x10020c); - ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32); - - ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) - - (rsvd_head + rsvd_tail), 1); - if (ret) - return ret; - - ram->type = NV_MEM_TYPE_STOLEN; - ram->stolen = (u64)nv_rd32(pfb, 0x100e10) << 12; - ram->get = nv50_ram_get; - ram->put = nv50_ram_put; - return 0; -} - -struct nouveau_oclass -nvaa_ram_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvaa_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h deleted file mode 100644 index d2085411a5cb..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __NVKM_FUSE_PRIV_H__ -#define __NVKM_FUSE_PRIV_H__ - -#include <subdev/fuse.h> - -int _nouveau_fuse_init(struct nouveau_object *object); -void _nouveau_fuse_dtor(struct nouveau_object *object); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h deleted file mode 100644 index bff98b86e2b5..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef __NVKM_GPIO_H__ -#define __NVKM_GPIO_H__ - -#include <subdev/gpio.h> - -#define nouveau_gpio_create(p,e,o,d) \ - nouveau_gpio_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_gpio_destroy(p) ({ \ - struct nouveau_gpio *gpio = (p); \ - _nouveau_gpio_dtor(nv_object(gpio)); \ -}) -#define nouveau_gpio_init(p) ({ \ - struct nouveau_gpio *gpio = (p); \ - _nouveau_gpio_init(nv_object(gpio)); \ -}) -#define nouveau_gpio_fini(p,s) ({ \ - struct nouveau_gpio *gpio = (p); \ - _nouveau_gpio_fini(nv_object(gpio), (s)); \ -}) - -int nouveau_gpio_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -int _nouveau_gpio_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void _nouveau_gpio_dtor(struct nouveau_object *); -int _nouveau_gpio_init(struct nouveau_object *); -int _nouveau_gpio_fini(struct nouveau_object *, bool); - -struct nouveau_gpio_impl { - struct nouveau_oclass base; - int lines; - - /* read and ack pending interrupts, returning only data - * for lines that have not been masked off, while still - * performing the ack for anything that was pending. - */ - void (*intr_stat)(struct nouveau_gpio *, u32 *, u32 *); - - /* mask on/off interrupts for hi/lo transitions on a - * given set of gpio lines - */ - void (*intr_mask)(struct nouveau_gpio *, u32, u32, u32); - - /* configure gpio direction and output value */ - int (*drive)(struct nouveau_gpio *, int line, int dir, int out); - - /* sense current state of given gpio line */ - int (*sense)(struct nouveau_gpio *, int line); - - /*XXX*/ - void (*reset)(struct nouveau_gpio *, u8); -}; - -void nv50_gpio_reset(struct nouveau_gpio *, u8); -int nv50_gpio_drive(struct nouveau_gpio *, int, int, int); -int nv50_gpio_sense(struct nouveau_gpio *, int); - -void nv94_gpio_intr_stat(struct nouveau_gpio *, u32 *, u32 *); -void nv94_gpio_intr_mask(struct nouveau_gpio *, u32, u32, u32); - -void nvd0_gpio_reset(struct nouveau_gpio *, u8); -int nvd0_gpio_drive(struct nouveau_gpio *, int, int, int); -int nvd0_gpio_sense(struct nouveau_gpio *, int); - - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h deleted file mode 100644 index 9ef965692fb1..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef __NV50_I2C_H__ -#define __NV50_I2C_H__ - -#include "priv.h" - -struct nv50_i2c_priv { - struct nouveau_i2c base; -}; - -struct nv50_i2c_port { - struct nouveau_i2c_port base; - u32 addr; - u32 state; -}; - -extern const u32 nv50_i2c_addr[]; -extern const int nv50_i2c_addr_nr; -int nv50_i2c_port_init(struct nouveau_object *); -int nv50_i2c_sense_scl(struct nouveau_i2c_port *); -int nv50_i2c_sense_sda(struct nouveau_i2c_port *); -void nv50_i2c_drive_scl(struct nouveau_i2c_port *, int state); -void nv50_i2c_drive_sda(struct nouveau_i2c_port *, int state); - -int nv94_aux_port_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nv94_i2c_acquire(struct nouveau_i2c_port *); -void nv94_i2c_release(struct nouveau_i2c_port *); - -int nvd0_i2c_port_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h deleted file mode 100644 index 4fe7ae3fde4e..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h +++ /dev/null @@ -1,89 +0,0 @@ -#ifndef __NVKM_I2C_H__ -#define __NVKM_I2C_H__ - -#include <subdev/i2c.h> - -extern struct nouveau_oclass nv04_i2c_pad_oclass; -extern struct nouveau_oclass nv94_i2c_pad_oclass; -extern struct nouveau_oclass gm204_i2c_pad_oclass; - -#define nouveau_i2c_port_create(p,e,o,i,a,f,d) \ - nouveau_i2c_port_create_((p), (e), (o), (i), (a), (f), \ - sizeof(**d), (void **)d) -#define nouveau_i2c_port_destroy(p) ({ \ - struct nouveau_i2c_port *port = (p); \ - _nouveau_i2c_port_dtor(nv_object(i2c)); \ -}) -#define nouveau_i2c_port_init(p) \ - nouveau_object_init(&(p)->base) -#define nouveau_i2c_port_fini(p,s) \ - nouveau_object_fini(&(p)->base, (s)) - -int nouveau_i2c_port_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, u8, - const struct i2c_algorithm *, - const struct nouveau_i2c_func *, - int, void **); -void _nouveau_i2c_port_dtor(struct nouveau_object *); -#define _nouveau_i2c_port_init nouveau_object_init -int _nouveau_i2c_port_fini(struct nouveau_object *, bool); - -#define nouveau_i2c_create(p,e,o,d) \ - nouveau_i2c_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_i2c_destroy(p) ({ \ - struct nouveau_i2c *i2c = (p); \ - _nouveau_i2c_dtor(nv_object(i2c)); \ -}) -#define nouveau_i2c_init(p) ({ \ - struct nouveau_i2c *i2c = (p); \ - _nouveau_i2c_init(nv_object(i2c)); \ -}) -#define nouveau_i2c_fini(p,s) ({ \ - struct nouveau_i2c *i2c = (p); \ - _nouveau_i2c_fini(nv_object(i2c), (s)); \ -}) - -int nouveau_i2c_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -int _nouveau_i2c_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void _nouveau_i2c_dtor(struct nouveau_object *); -int _nouveau_i2c_init(struct nouveau_object *); -int _nouveau_i2c_fini(struct nouveau_object *, bool); - -extern struct nouveau_oclass nouveau_anx9805_sclass[]; -extern struct nouveau_oclass nvd0_i2c_sclass[]; - -extern const struct i2c_algorithm nouveau_i2c_bit_algo; -extern const struct i2c_algorithm nouveau_i2c_aux_algo; - -struct nouveau_i2c_impl { - struct nouveau_oclass base; - - /* supported i2c port classes */ - struct nouveau_oclass *sclass; - struct nouveau_oclass *pad_x; - struct nouveau_oclass *pad_s; - - /* number of native dp aux channels present */ - int aux; - - /* read and ack pending interrupts, returning only data - * for ports that have not been masked off, while still - * performing the ack for anything that was pending. - */ - void (*aux_stat)(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *); - - /* mask on/off interrupt types for a given set of auxch - */ - void (*aux_mask)(struct nouveau_i2c *, u32, u32, u32); -}; - -void nv94_aux_stat(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *); -void nv94_aux_mask(struct nouveau_i2c *, u32, u32, u32); - -void nve0_aux_stat(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *); -void nve0_aux_mask(struct nouveau_i2c *, u32, u32, u32); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h deleted file mode 100644 index 095fbc6fc099..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef __NV04_INSTMEM_H__ -#define __NV04_INSTMEM_H__ - -#include <core/gpuobj.h> -#include <core/ramht.h> -#include <core/mm.h> - -#include "priv.h" - -extern struct nouveau_instobj_impl nv04_instobj_oclass; - -struct nv04_instmem_priv { - struct nouveau_instmem base; - - void __iomem *iomem; - struct nouveau_mm heap; - - struct nouveau_gpuobj *vbios; - struct nouveau_ramht *ramht; - struct nouveau_gpuobj *ramro; - struct nouveau_gpuobj *ramfc; -}; - -static inline struct nv04_instmem_priv * -nv04_instmem(void *obj) -{ - return (void *)nouveau_instmem(obj); -} - -struct nv04_instobj_priv { - struct nouveau_instobj base; - struct nouveau_mm_node *mem; -}; - -void nv04_instmem_dtor(struct nouveau_object *); - -int nv04_instmem_alloc(struct nouveau_instmem *, struct nouveau_object *, - u32 size, u32 align, struct nouveau_object **pobject); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h deleted file mode 100644 index 8d67dedc5bb2..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef __NVKM_INSTMEM_PRIV_H__ -#define __NVKM_INSTMEM_PRIV_H__ - -#include <subdev/instmem.h> - -struct nouveau_instobj_impl { - struct nouveau_oclass base; -}; - -struct nouveau_instobj_args { - u32 size; - u32 align; -}; - -#define nouveau_instobj_create(p,e,o,d) \ - nouveau_instobj_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_instobj_destroy(p) ({ \ - struct nouveau_instobj *iobj = (p); \ - _nouveau_instobj_dtor(nv_object(iobj)); \ -}) -#define nouveau_instobj_init(p) \ - nouveau_object_init(&(p)->base) -#define nouveau_instobj_fini(p,s) \ - nouveau_object_fini(&(p)->base, (s)) - -int nouveau_instobj_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_instobj_dtor(struct nouveau_object *); -#define _nouveau_instobj_init nouveau_object_init -#define _nouveau_instobj_fini nouveau_object_fini - -struct nouveau_instmem_impl { - struct nouveau_oclass base; - struct nouveau_oclass *instobj; -}; - -#define nouveau_instmem_create(p,e,o,d) \ - nouveau_instmem_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_instmem_destroy(p) \ - nouveau_subdev_destroy(&(p)->base) -#define nouveau_instmem_init(p) ({ \ - struct nouveau_instmem *imem = (p); \ - _nouveau_instmem_init(nv_object(imem)); \ -}) -#define nouveau_instmem_fini(p,s) ({ \ - struct nouveau_instmem *imem = (p); \ - _nouveau_instmem_fini(nv_object(imem), (s)); \ -}) - -int nouveau_instmem_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -#define _nouveau_instmem_dtor _nouveau_subdev_dtor -int _nouveau_instmem_init(struct nouveau_object *); -int _nouveau_instmem_fini(struct nouveau_object *, bool); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h deleted file mode 100644 index 4d9ea46c47c2..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef __NVKM_MC_NV04_H__ -#define __NVKM_MC_NV04_H__ - -#include "priv.h" - -struct nv04_mc_priv { - struct nouveau_mc base; -}; - -int nv04_mc_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); - -extern const struct nouveau_mc_intr nv04_mc_intr[]; -int nv04_mc_init(struct nouveau_object *); -void nv40_mc_msi_rearm(struct nouveau_mc *); -int nv44_mc_init(struct nouveau_object *object); -int nv50_mc_init(struct nouveau_object *); -extern const struct nouveau_mc_intr nv50_mc_intr[]; -extern const struct nouveau_mc_intr nvc0_mc_intr[]; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h deleted file mode 100644 index 911e66392587..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef __NVKM_MC_PRIV_H__ -#define __NVKM_MC_PRIV_H__ - -#include <subdev/mc.h> - -#define nouveau_mc_create(p,e,o,d) \ - nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_mc_destroy(p) ({ \ - struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc)); \ -}) -#define nouveau_mc_init(p) ({ \ - struct nouveau_mc *pmc = (p); _nouveau_mc_init(nv_object(pmc)); \ -}) -#define nouveau_mc_fini(p,s) ({ \ - struct nouveau_mc *pmc = (p); _nouveau_mc_fini(nv_object(pmc), (s)); \ -}) - -int nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_mc_dtor(struct nouveau_object *); -int _nouveau_mc_init(struct nouveau_object *); -int _nouveau_mc_fini(struct nouveau_object *, bool); - -struct nouveau_mc_intr { - u32 stat; - u32 unit; -}; - -struct nouveau_mc_oclass { - struct nouveau_oclass base; - const struct nouveau_mc_intr *intr; - void (*msi_rearm)(struct nouveau_mc *); - void (*unk260)(struct nouveau_mc *, u32); -}; - -void nvc0_mc_unk260(struct nouveau_mc *, u32); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h b/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h deleted file mode 100644 index 5e0be0c591ca..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef __NVMXM_MXMS_H__ -#define __NVMXM_MXMS_H__ - -struct mxms_odev { - u8 outp_type; - u8 conn_type; - u8 ddc_port; - u8 dig_conn; -}; - -void mxms_output_device(struct nouveau_mxm *, u8 *, struct mxms_odev *); - -u16 mxms_version(struct nouveau_mxm *); -u16 mxms_headerlen(struct nouveau_mxm *); -u16 mxms_structlen(struct nouveau_mxm *); -bool mxms_checksum(struct nouveau_mxm *); -bool mxms_valid(struct nouveau_mxm *); - -bool mxms_foreach(struct nouveau_mxm *, u8, - bool (*)(struct nouveau_mxm *, u8 *, void *), void *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c deleted file mode 100644 index 0ab55f27ec45..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <subdev/timer.h> - -#include "priv.h" - -static void -nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) -{ - const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); - if (impl->pgob) - impl->pgob(ppwr, enable); -} - -static int -nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2], - u32 process, u32 message, u32 data0, u32 data1) -{ - struct nouveau_subdev *subdev = nv_subdev(ppwr); - u32 addr; - - /* wait for a free slot in the fifo */ - addr = nv_rd32(ppwr, 0x10a4a0); - if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8)) - return -EBUSY; - - /* we currently only support a single process at a time waiting - * on a synchronous reply, take the PPWR mutex and tell the - * receive handler what we're waiting for - */ - if (reply) { - mutex_lock(&subdev->mutex); - ppwr->recv.message = message; - ppwr->recv.process = process; - } - - /* acquire data segment access */ - do { - nv_wr32(ppwr, 0x10a580, 0x00000001); - } while (nv_rd32(ppwr, 0x10a580) != 0x00000001); - - /* write the packet */ - nv_wr32(ppwr, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) + - ppwr->send.base)); - nv_wr32(ppwr, 0x10a1c4, process); - nv_wr32(ppwr, 0x10a1c4, message); - nv_wr32(ppwr, 0x10a1c4, data0); - nv_wr32(ppwr, 0x10a1c4, data1); - nv_wr32(ppwr, 0x10a4a0, (addr + 1) & 0x0f); - - /* release data segment access */ - nv_wr32(ppwr, 0x10a580, 0x00000000); - - /* wait for reply, if requested */ - if (reply) { - wait_event(ppwr->recv.wait, (ppwr->recv.process == 0)); - reply[0] = ppwr->recv.data[0]; - reply[1] = ppwr->recv.data[1]; - mutex_unlock(&subdev->mutex); - } - - return 0; -} - -static void -nouveau_pwr_recv(struct work_struct *work) -{ - struct nouveau_pwr *ppwr = - container_of(work, struct nouveau_pwr, recv.work); - u32 process, message, data0, data1; - - /* nothing to do if GET == PUT */ - u32 addr = nv_rd32(ppwr, 0x10a4cc); - if (addr == nv_rd32(ppwr, 0x10a4c8)) - return; - - /* acquire data segment access */ - do { - nv_wr32(ppwr, 0x10a580, 0x00000002); - } while (nv_rd32(ppwr, 0x10a580) != 0x00000002); - - /* read the packet */ - nv_wr32(ppwr, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) + - ppwr->recv.base)); - process = nv_rd32(ppwr, 0x10a1c4); - message = nv_rd32(ppwr, 0x10a1c4); - data0 = nv_rd32(ppwr, 0x10a1c4); - data1 = nv_rd32(ppwr, 0x10a1c4); - nv_wr32(ppwr, 0x10a4cc, (addr + 1) & 0x0f); - - /* release data segment access */ - nv_wr32(ppwr, 0x10a580, 0x00000000); - - /* wake process if it's waiting on a synchronous reply */ - if (ppwr->recv.process) { - if (process == ppwr->recv.process && - message == ppwr->recv.message) { - ppwr->recv.data[0] = data0; - ppwr->recv.data[1] = data1; - ppwr->recv.process = 0; - wake_up(&ppwr->recv.wait); - return; - } - } - - /* right now there's no other expected responses from the engine, - * so assume that any unexpected message is an error. - */ - nv_warn(ppwr, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n", - (char)((process & 0x000000ff) >> 0), - (char)((process & 0x0000ff00) >> 8), - (char)((process & 0x00ff0000) >> 16), - (char)((process & 0xff000000) >> 24), - process, message, data0, data1); -} - -static void -nouveau_pwr_intr(struct nouveau_subdev *subdev) -{ - struct nouveau_pwr *ppwr = (void *)subdev; - u32 disp = nv_rd32(ppwr, 0x10a01c); - u32 intr = nv_rd32(ppwr, 0x10a008) & disp & ~(disp >> 16); - - if (intr & 0x00000020) { - u32 stat = nv_rd32(ppwr, 0x10a16c); - if (stat & 0x80000000) { - nv_error(ppwr, "UAS fault at 0x%06x addr 0x%08x\n", - stat & 0x00ffffff, nv_rd32(ppwr, 0x10a168)); - nv_wr32(ppwr, 0x10a16c, 0x00000000); - intr &= ~0x00000020; - } - } - - if (intr & 0x00000040) { - schedule_work(&ppwr->recv.work); - nv_wr32(ppwr, 0x10a004, 0x00000040); - intr &= ~0x00000040; - } - - if (intr & 0x00000080) { - nv_info(ppwr, "wr32 0x%06x 0x%08x\n", nv_rd32(ppwr, 0x10a7a0), - nv_rd32(ppwr, 0x10a7a4)); - nv_wr32(ppwr, 0x10a004, 0x00000080); - intr &= ~0x00000080; - } - - if (intr) { - nv_error(ppwr, "intr 0x%08x\n", intr); - nv_wr32(ppwr, 0x10a004, intr); - } -} - -int -_nouveau_pwr_fini(struct nouveau_object *object, bool suspend) -{ - struct nouveau_pwr *ppwr = (void *)object; - - nv_wr32(ppwr, 0x10a014, 0x00000060); - flush_work(&ppwr->recv.work); - - return nouveau_subdev_fini(&ppwr->base, suspend); -} - -int -_nouveau_pwr_init(struct nouveau_object *object) -{ - const struct nvkm_pwr_impl *impl = (void *)object->oclass; - struct nouveau_pwr *ppwr = (void *)object; - int ret, i; - - ret = nouveau_subdev_init(&ppwr->base); - if (ret) - return ret; - - nv_subdev(ppwr)->intr = nouveau_pwr_intr; - ppwr->message = nouveau_pwr_send; - ppwr->pgob = nouveau_pwr_pgob; - - /* prevent previous ucode from running, wait for idle, reset */ - nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */ - nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000); - nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000); - nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000); - nv_rd32(ppwr, 0x000200); - nv_wait(ppwr, 0x10a10c, 0x00000006, 0x00000000); - - /* upload data segment */ - nv_wr32(ppwr, 0x10a1c0, 0x01000000); - for (i = 0; i < impl->data.size / 4; i++) - nv_wr32(ppwr, 0x10a1c4, impl->data.data[i]); - - /* upload code segment */ - nv_wr32(ppwr, 0x10a180, 0x01000000); - for (i = 0; i < impl->code.size / 4; i++) { - if ((i & 0x3f) == 0) - nv_wr32(ppwr, 0x10a188, i >> 6); - nv_wr32(ppwr, 0x10a184, impl->code.data[i]); - } - - /* start it running */ - nv_wr32(ppwr, 0x10a10c, 0x00000000); - nv_wr32(ppwr, 0x10a104, 0x00000000); - nv_wr32(ppwr, 0x10a100, 0x00000002); - - /* wait for valid host->pwr ring configuration */ - if (!nv_wait_ne(ppwr, 0x10a4d0, 0xffffffff, 0x00000000)) - return -EBUSY; - ppwr->send.base = nv_rd32(ppwr, 0x10a4d0) & 0x0000ffff; - ppwr->send.size = nv_rd32(ppwr, 0x10a4d0) >> 16; - - /* wait for valid pwr->host ring configuration */ - if (!nv_wait_ne(ppwr, 0x10a4dc, 0xffffffff, 0x00000000)) - return -EBUSY; - ppwr->recv.base = nv_rd32(ppwr, 0x10a4dc) & 0x0000ffff; - ppwr->recv.size = nv_rd32(ppwr, 0x10a4dc) >> 16; - - nv_wr32(ppwr, 0x10a010, 0x000000e0); - return 0; -} - -int -nouveau_pwr_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) -{ - struct nouveau_pwr *ppwr; - int ret; - - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PPWR", - "pwr", length, pobject); - ppwr = *pobject; - if (ret) - return ret; - - INIT_WORK(&ppwr->recv.work, nouveau_pwr_recv); - init_waitqueue_head(&ppwr->recv.wait); - return 0; -} - -int -_nouveau_pwr_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_pwr *ppwr; - int ret = nouveau_pwr_create(parent, engine, oclass, &ppwr); - *pobject = nv_object(ppwr); - return ret; -} diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c deleted file mode 100644 index 7a9299d7159f..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c +++ /dev/null @@ -1,201 +0,0 @@ -#ifndef __NVKM_PWR_MEMX_H__ -#define __NVKM_PWR_MEMX_H__ - -#include "priv.h" - -struct nouveau_memx { - struct nouveau_pwr *ppwr; - u32 base; - u32 size; - struct { - u32 mthd; - u32 size; - u32 data[64]; - } c; -}; - -static void -memx_out(struct nouveau_memx *memx) -{ - struct nouveau_pwr *ppwr = memx->ppwr; - int i; - - if (memx->c.mthd) { - nv_wr32(ppwr, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd); - for (i = 0; i < memx->c.size; i++) - nv_wr32(ppwr, 0x10a1c4, memx->c.data[i]); - memx->c.mthd = 0; - memx->c.size = 0; - } -} - -static void -memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[]) -{ - if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) || - (memx->c.mthd && memx->c.mthd != mthd)) - memx_out(memx); - memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0])); - memx->c.size += size; - memx->c.mthd = mthd; -} - -int -nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx) -{ - struct nouveau_memx *memx; - u32 reply[2]; - int ret; - - ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO, - MEMX_INFO_DATA, 0); - if (ret) - return ret; - - memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL); - if (!memx) - return -ENOMEM; - memx->ppwr = ppwr; - memx->base = reply[0]; - memx->size = reply[1]; - - /* acquire data segment access */ - do { - nv_wr32(ppwr, 0x10a580, 0x00000003); - } while (nv_rd32(ppwr, 0x10a580) != 0x00000003); - nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base); - - return 0; -} - -int -nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec) -{ - struct nouveau_memx *memx = *pmemx; - struct nouveau_pwr *ppwr = memx->ppwr; - u32 finish, reply[2]; - - /* flush the cache... */ - memx_out(memx); - - /* release data segment access */ - finish = nv_rd32(ppwr, 0x10a1c0) & 0x00ffffff; - nv_wr32(ppwr, 0x10a580, 0x00000000); - - /* call MEMX process to execute the script, and wait for reply */ - if (exec) { - ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_EXEC, - memx->base, finish); - } - - nv_debug(memx->ppwr, "Exec took %uns, PPWR_IN %08x\n", - reply[0], reply[1]); - kfree(memx); - return 0; -} - -void -nouveau_memx_wr32(struct nouveau_memx *memx, u32 addr, u32 data) -{ - nv_debug(memx->ppwr, "R[%06x] = 0x%08x\n", addr, data); - memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data }); -} - -void -nouveau_memx_wait(struct nouveau_memx *memx, - u32 addr, u32 mask, u32 data, u32 nsec) -{ - nv_debug(memx->ppwr, "R[%06x] & 0x%08x == 0x%08x, %d us\n", - addr, mask, data, nsec); - memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, mask, data, nsec }); - memx_out(memx); /* fuc can't handle multiple */ -} - -void -nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec) -{ - nv_debug(memx->ppwr, " DELAY = %d ns\n", nsec); - memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec }); - memx_out(memx); /* fuc can't handle multiple */ -} - -void -nouveau_memx_wait_vblank(struct nouveau_memx *memx) -{ - struct nouveau_pwr *ppwr = memx->ppwr; - u32 heads, x, y, px = 0; - int i, head_sync; - - if (nv_device(ppwr)->chipset < 0xd0) { - heads = nv_rd32(ppwr, 0x610050); - for (i = 0; i < 2; i++) { - /* Heuristic: sync to head with biggest resolution */ - if (heads & (2 << (i << 3))) { - x = nv_rd32(ppwr, 0x610b40 + (0x540 * i)); - y = (x & 0xffff0000) >> 16; - x &= 0x0000ffff; - if ((x * y) > px) { - px = (x * y); - head_sync = i; - } - } - } - } - - if (px == 0) { - nv_debug(memx->ppwr, "WAIT VBLANK !NO ACTIVE HEAD\n"); - return; - } - - nv_debug(memx->ppwr, "WAIT VBLANK HEAD%d\n", head_sync); - memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync }); - memx_out(memx); /* fuc can't handle multiple */ -} - -void -nouveau_memx_train(struct nouveau_memx *memx) -{ - nv_debug(memx->ppwr, " MEM TRAIN\n"); - memx_cmd(memx, MEMX_TRAIN, 0, NULL); -} - -int -nouveau_memx_train_result(struct nouveau_pwr *ppwr, u32 *res, int rsize) -{ - u32 reply[2], base, size, i; - int ret; - - ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO, - MEMX_INFO_TRAIN, 0); - if (ret) - return ret; - - base = reply[0]; - size = reply[1] >> 2; - if (size > rsize) - return -ENOMEM; - - /* read the packet */ - nv_wr32(ppwr, 0x10a1c0, 0x02000000 | base); - - for (i = 0; i < size; i++) - res[i] = nv_rd32(ppwr, 0x10a1c4); - - return 0; -} - -void -nouveau_memx_block(struct nouveau_memx *memx) -{ - nv_debug(memx->ppwr, " HOST BLOCKED\n"); - memx_cmd(memx, MEMX_ENTER, 0, NULL); -} - -void -nouveau_memx_unblock(struct nouveau_memx *memx) -{ - nv_debug(memx->ppwr, " HOST UNBLOCKED\n"); - memx_cmd(memx, MEMX_LEAVE, 0, NULL); -} - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h deleted file mode 100644 index 3814a341db32..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __NVKM_PWR_PRIV_H__ -#define __NVKM_PWR_PRIV_H__ - -#include <subdev/pwr.h> -#include <subdev/pwr/fuc/os.h> - -#define nouveau_pwr_create(p, e, o, d) \ - nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_pwr_destroy(p) \ - nouveau_subdev_destroy(&(p)->base) -#define nouveau_pwr_init(p) ({ \ - struct nouveau_pwr *_ppwr = (p); \ - _nouveau_pwr_init(nv_object(_ppwr)); \ -}) -#define nouveau_pwr_fini(p,s) ({ \ - struct nouveau_pwr *_ppwr = (p); \ - _nouveau_pwr_fini(nv_object(_ppwr), (s)); \ -}) - -int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); - -int _nouveau_pwr_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -#define _nouveau_pwr_dtor _nouveau_subdev_dtor -int _nouveau_pwr_init(struct nouveau_object *); -int _nouveau_pwr_fini(struct nouveau_object *, bool); - -struct nvkm_pwr_impl { - struct nouveau_oclass base; - struct { - u32 *data; - u32 size; - } code; - struct { - u32 *data; - u32 size; - } data; - - void (*pgob)(struct nouveau_pwr *, bool); -}; - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h deleted file mode 100644 index 7dba8c281a0b..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h +++ /dev/null @@ -1,159 +0,0 @@ -#ifndef __NVTHERM_PRIV_H__ -#define __NVTHERM_PRIV_H__ - -/* - * Copyright 2012 The Nouveau community - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Martin Peres - */ - -#include <subdev/therm.h> - -#include <subdev/bios/extdev.h> -#include <subdev/bios/gpio.h> -#include <subdev/bios/perf.h> -#include <subdev/bios/therm.h> -#include <subdev/timer.h> - -struct nouveau_fan { - struct nouveau_therm *parent; - const char *type; - - struct nvbios_therm_fan bios; - struct nvbios_perf_fan perf; - - struct nouveau_alarm alarm; - spinlock_t lock; - int percent; - - int (*get)(struct nouveau_therm *therm); - int (*set)(struct nouveau_therm *therm, int percent); - - struct dcb_gpio_func tach; -}; - -enum nouveau_therm_thrs_direction { - NOUVEAU_THERM_THRS_FALLING = 0, - NOUVEAU_THERM_THRS_RISING = 1 -}; - -enum nouveau_therm_thrs_state { - NOUVEAU_THERM_THRS_LOWER = 0, - NOUVEAU_THERM_THRS_HIGHER = 1 -}; - -enum nouveau_therm_thrs { - NOUVEAU_THERM_THRS_FANBOOST = 0, - NOUVEAU_THERM_THRS_DOWNCLOCK = 1, - NOUVEAU_THERM_THRS_CRITICAL = 2, - NOUVEAU_THERM_THRS_SHUTDOWN = 3, - NOUVEAU_THERM_THRS_NR -}; - -struct nouveau_therm_priv { - struct nouveau_therm base; - - /* automatic thermal management */ - struct nouveau_alarm alarm; - spinlock_t lock; - struct nouveau_therm_trip_point *last_trip; - int mode; - int cstate; - int suspend; - - /* bios */ - struct nvbios_therm_sensor bios_sensor; - - /* fan priv */ - struct nouveau_fan *fan; - - /* alarms priv */ - struct { - spinlock_t alarm_program_lock; - struct nouveau_alarm therm_poll_alarm; - enum nouveau_therm_thrs_state alarm_state[NOUVEAU_THERM_THRS_NR]; - void (*program_alarms)(struct nouveau_therm *); - } sensor; - - /* what should be done if the card overheats */ - struct { - void (*downclock)(struct nouveau_therm *, bool active); - void (*pause)(struct nouveau_therm *, bool active); - } emergency; - - /* ic */ - struct i2c_client *ic; -}; - -int nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode); -int nouveau_therm_attr_get(struct nouveau_therm *therm, - enum nouveau_therm_attr_type type); -int nouveau_therm_attr_set(struct nouveau_therm *therm, - enum nouveau_therm_attr_type type, int value); - -void nouveau_therm_ic_ctor(struct nouveau_therm *therm); - -int nouveau_therm_sensor_ctor(struct nouveau_therm *therm); - -int nouveau_therm_fan_ctor(struct nouveau_therm *therm); -int nouveau_therm_fan_init(struct nouveau_therm *therm); -int nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend); -int nouveau_therm_fan_get(struct nouveau_therm *therm); -int nouveau_therm_fan_set(struct nouveau_therm *therm, bool now, int percent); -int nouveau_therm_fan_user_get(struct nouveau_therm *therm); -int nouveau_therm_fan_user_set(struct nouveau_therm *therm, int percent); - -int nouveau_therm_fan_sense(struct nouveau_therm *therm); - -int nouveau_therm_preinit(struct nouveau_therm *); - -int nouveau_therm_sensor_init(struct nouveau_therm *therm); -int nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend); -void nouveau_therm_sensor_preinit(struct nouveau_therm *); -void nouveau_therm_sensor_set_threshold_state(struct nouveau_therm *therm, - enum nouveau_therm_thrs thrs, - enum nouveau_therm_thrs_state st); -enum nouveau_therm_thrs_state -nouveau_therm_sensor_get_threshold_state(struct nouveau_therm *therm, - enum nouveau_therm_thrs thrs); -void nouveau_therm_sensor_event(struct nouveau_therm *therm, - enum nouveau_therm_thrs thrs, - enum nouveau_therm_thrs_direction dir); -void nouveau_therm_program_alarms_polling(struct nouveau_therm *therm); - -void nv40_therm_intr(struct nouveau_subdev *); -int nv50_fan_pwm_ctrl(struct nouveau_therm *, int, bool); -int nv50_fan_pwm_get(struct nouveau_therm *, int, u32 *, u32 *); -int nv50_fan_pwm_set(struct nouveau_therm *, int, u32, u32); -int nv50_fan_pwm_clock(struct nouveau_therm *, int); -int nv84_temp_get(struct nouveau_therm *therm); -void nv84_sensor_setup(struct nouveau_therm *therm); -int nv84_therm_fini(struct nouveau_object *object, bool suspend); - -int nva3_therm_fan_sense(struct nouveau_therm *); - -int nvd0_therm_init(struct nouveau_object *object); - -int nouveau_fanpwm_create(struct nouveau_therm *, struct dcb_gpio_func *); -int nouveau_fantog_create(struct nouveau_therm *, struct dcb_gpio_func *); -int nouveau_fannil_create(struct nouveau_therm *); - -#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c deleted file mode 100644 index f75a683bd47a..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c +++ /dev/null @@ -1,483 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include <core/gpuobj.h> -#include <core/mm.h> - -#include <subdev/fb.h> -#include <subdev/vm.h> - -void -nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_mm_node *r; - int big = vma->node->type != vmm->spg_shift; - u32 offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; - u32 max = 1 << (vmm->pgt_bits - bits); - u32 end, len; - - delta = 0; - list_for_each_entry(r, &node->regions, rl_entry) { - u64 phys = (u64)r->offset << 12; - u32 num = r->length >> bits; - - while (num) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; - - end = (pte + num); - if (unlikely(end >= max)) - end = max; - len = end - pte; - - vmm->map(vma, pgt, node, pte, len, phys, delta); - - num -= len; - pte += len; - if (unlikely(end >= max)) { - phys += len << (bits + 12); - pde++; - pte = 0; - } - - delta += (u64)len << vma->node->type; - } - } - - vmm->flush(vm); -} - -static void -nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, - struct nouveau_mem *mem) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - int big = vma->node->type != vmm->spg_shift; - u32 offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 num = length >> vma->node->type; - u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; - u32 max = 1 << (vmm->pgt_bits - bits); - unsigned m, sglen; - u32 end, len; - int i; - struct scatterlist *sg; - - for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; - sglen = sg_dma_len(sg) >> PAGE_SHIFT; - - end = pte + sglen; - if (unlikely(end >= max)) - end = max; - len = end - pte; - - for (m = 0; m < len; m++) { - dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); - - vmm->map_sg(vma, pgt, mem, pte, 1, &addr); - num--; - pte++; - - if (num == 0) - goto finish; - } - if (unlikely(end >= max)) { - pde++; - pte = 0; - } - if (m < sglen) { - for (; m < sglen; m++) { - dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); - - vmm->map_sg(vma, pgt, mem, pte, 1, &addr); - num--; - pte++; - if (num == 0) - goto finish; - } - } - - } -finish: - vmm->flush(vm); -} - -static void -nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, - struct nouveau_mem *mem) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - dma_addr_t *list = mem->pages; - int big = vma->node->type != vmm->spg_shift; - u32 offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 num = length >> vma->node->type; - u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; - u32 max = 1 << (vmm->pgt_bits - bits); - u32 end, len; - - while (num) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; - - end = (pte + num); - if (unlikely(end >= max)) - end = max; - len = end - pte; - - vmm->map_sg(vma, pgt, mem, pte, len, list); - - num -= len; - pte += len; - list += len; - if (unlikely(end >= max)) { - pde++; - pte = 0; - } - } - - vmm->flush(vm); -} - -void -nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node) -{ - if (node->sg) - nouveau_vm_map_sg_table(vma, 0, node->size << 12, node); - else - if (node->pages) - nouveau_vm_map_sg(vma, 0, node->size << 12, node); - else - nouveau_vm_map_at(vma, 0, node); -} - -void -nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - int big = vma->node->type != vmm->spg_shift; - u32 offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 num = length >> vma->node->type; - u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; - u32 max = 1 << (vmm->pgt_bits - bits); - u32 end, len; - - while (num) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; - - end = (pte + num); - if (unlikely(end >= max)) - end = max; - len = end - pte; - - vmm->unmap(pgt, pte, len); - - num -= len; - pte += len; - if (unlikely(end >= max)) { - pde++; - pte = 0; - } - } - - vmm->flush(vm); -} - -void -nouveau_vm_unmap(struct nouveau_vma *vma) -{ - nouveau_vm_unmap_at(vma, 0, (u64)vma->node->length << 12); -} - -static void -nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_vm_pgd *vpgd; - struct nouveau_vm_pgt *vpgt; - struct nouveau_gpuobj *pgt; - u32 pde; - - for (pde = fpde; pde <= lpde; pde++) { - vpgt = &vm->pgt[pde - vm->fpde]; - if (--vpgt->refcount[big]) - continue; - - pgt = vpgt->obj[big]; - vpgt->obj[big] = NULL; - - list_for_each_entry(vpgd, &vm->pgd_list, head) { - vmm->map_pgt(vpgd->obj, pde, vpgt->obj); - } - - mutex_unlock(&nv_subdev(vmm)->mutex); - nouveau_gpuobj_ref(NULL, &pgt); - mutex_lock(&nv_subdev(vmm)->mutex); - } -} - -static int -nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; - struct nouveau_vm_pgd *vpgd; - struct nouveau_gpuobj *pgt; - int big = (type != vmm->spg_shift); - u32 pgt_size; - int ret; - - pgt_size = (1 << (vmm->pgt_bits + 12)) >> type; - pgt_size *= 8; - - mutex_unlock(&nv_subdev(vmm)->mutex); - ret = nouveau_gpuobj_new(nv_object(vm->vmm), NULL, pgt_size, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &pgt); - mutex_lock(&nv_subdev(vmm)->mutex); - if (unlikely(ret)) - return ret; - - /* someone beat us to filling the PDE while we didn't have the lock */ - if (unlikely(vpgt->refcount[big]++)) { - mutex_unlock(&nv_subdev(vmm)->mutex); - nouveau_gpuobj_ref(NULL, &pgt); - mutex_lock(&nv_subdev(vmm)->mutex); - return 0; - } - - vpgt->obj[big] = pgt; - list_for_each_entry(vpgd, &vm->pgd_list, head) { - vmm->map_pgt(vpgd->obj, pde, vpgt->obj); - } - - return 0; -} - -int -nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, - u32 access, struct nouveau_vma *vma) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - u32 align = (1 << page_shift) >> 12; - u32 msize = size >> 12; - u32 fpde, lpde, pde; - int ret; - - mutex_lock(&nv_subdev(vmm)->mutex); - ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align, - &vma->node); - if (unlikely(ret != 0)) { - mutex_unlock(&nv_subdev(vmm)->mutex); - return ret; - } - - fpde = (vma->node->offset >> vmm->pgt_bits); - lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits; - - for (pde = fpde; pde <= lpde; pde++) { - struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; - int big = (vma->node->type != vmm->spg_shift); - - if (likely(vpgt->refcount[big])) { - vpgt->refcount[big]++; - continue; - } - - ret = nouveau_vm_map_pgt(vm, pde, vma->node->type); - if (ret) { - if (pde != fpde) - nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1); - nouveau_mm_free(&vm->mm, &vma->node); - mutex_unlock(&nv_subdev(vmm)->mutex); - return ret; - } - } - mutex_unlock(&nv_subdev(vmm)->mutex); - - vma->vm = NULL; - nouveau_vm_ref(vm, &vma->vm, NULL); - vma->offset = (u64)vma->node->offset << 12; - vma->access = access; - return 0; -} - -void -nouveau_vm_put(struct nouveau_vma *vma) -{ - struct nouveau_vm *vm = vma->vm; - struct nouveau_vmmgr *vmm = vm->vmm; - u32 fpde, lpde; - - if (unlikely(vma->node == NULL)) - return; - fpde = (vma->node->offset >> vmm->pgt_bits); - lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits; - - mutex_lock(&nv_subdev(vmm)->mutex); - nouveau_vm_unmap_pgt(vm, vma->node->type != vmm->spg_shift, fpde, lpde); - nouveau_mm_free(&vm->mm, &vma->node); - mutex_unlock(&nv_subdev(vmm)->mutex); - - nouveau_vm_ref(NULL, &vma->vm, NULL); -} - -int -nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, - u64 mm_offset, u32 block, struct nouveau_vm **pvm) -{ - struct nouveau_vm *vm; - u64 mm_length = (offset + length) - mm_offset; - int ret; - - vm = kzalloc(sizeof(*vm), GFP_KERNEL); - if (!vm) - return -ENOMEM; - - INIT_LIST_HEAD(&vm->pgd_list); - vm->vmm = vmm; - kref_init(&vm->refcount); - vm->fpde = offset >> (vmm->pgt_bits + 12); - vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12); - - vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); - if (!vm->pgt) { - kfree(vm); - return -ENOMEM; - } - - ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, - block >> 12); - if (ret) { - vfree(vm->pgt); - kfree(vm); - return ret; - } - - *pvm = vm; - - return 0; -} - -int -nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **pvm) -{ - struct nouveau_vmmgr *vmm = nouveau_vmmgr(device); - return vmm->create(vmm, offset, length, mm_offset, pvm); -} - -static int -nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_vm_pgd *vpgd; - int i; - - if (!pgd) - return 0; - - vpgd = kzalloc(sizeof(*vpgd), GFP_KERNEL); - if (!vpgd) - return -ENOMEM; - - nouveau_gpuobj_ref(pgd, &vpgd->obj); - - mutex_lock(&nv_subdev(vmm)->mutex); - for (i = vm->fpde; i <= vm->lpde; i++) - vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj); - list_add(&vpgd->head, &vm->pgd_list); - mutex_unlock(&nv_subdev(vmm)->mutex); - return 0; -} - -static void -nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd) -{ - struct nouveau_vmmgr *vmm = vm->vmm; - struct nouveau_vm_pgd *vpgd, *tmp; - struct nouveau_gpuobj *pgd = NULL; - - if (!mpgd) - return; - - mutex_lock(&nv_subdev(vmm)->mutex); - list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { - if (vpgd->obj == mpgd) { - pgd = vpgd->obj; - list_del(&vpgd->head); - kfree(vpgd); - break; - } - } - mutex_unlock(&nv_subdev(vmm)->mutex); - - nouveau_gpuobj_ref(NULL, &pgd); -} - -static void -nouveau_vm_del(struct kref *kref) -{ - struct nouveau_vm *vm = container_of(kref, typeof(*vm), refcount); - struct nouveau_vm_pgd *vpgd, *tmp; - - list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { - nouveau_vm_unlink(vm, vpgd->obj); - } - - nouveau_mm_fini(&vm->mm); - vfree(vm->pgt); - kfree(vm); -} - -int -nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr, - struct nouveau_gpuobj *pgd) -{ - if (ref) { - int ret = nouveau_vm_link(ref, pgd); - if (ret) - return ret; - - kref_get(&ref->refcount); - } - - if (*ptr) { - nouveau_vm_unlink(*ptr, pgd); - kref_put(&(*ptr)->refcount, nouveau_vm_del); - } - - *ptr = ref; - return 0; -} diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h deleted file mode 100644 index ec42d4bc86a6..000000000000 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __NV04_VMMGR_PRIV__ -#define __NV04_VMMGR_PRIV__ - -#include <subdev/vm.h> - -struct nv04_vmmgr_priv { - struct nouveau_vmmgr base; - struct nouveau_vm *vm; - dma_addr_t null; - void *nullp; -}; - -static inline struct nv04_vmmgr_priv * -nv04_vmmgr(void *obj) -{ - return (void *)nouveau_vmmgr(obj); -} - -#endif diff --git a/drivers/gpu/drm/nouveau/dispnv04/Makefile b/drivers/gpu/drm/nouveau/dispnv04/Kbuild index 424a489d0f03..424a489d0f03 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/Makefile +++ b/drivers/gpu/drm/nouveau/dispnv04/Kbuild diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 38402ade6835..542bb266a0ab 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -41,7 +41,7 @@ #include "disp.h" #include <subdev/bios/pll.h> -#include <subdev/clock.h> +#include <subdev/clk.h> static int nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, @@ -112,12 +112,12 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod { struct drm_device *dev = crtc->dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_bios *bios = nvkm_bios(&drm->device); - struct nouveau_clock *clk = nvkm_clock(&drm->device); + struct nvkm_bios *bios = nvxx_bios(&drm->device); + struct nvkm_clk *clk = nvxx_clk(&drm->device); struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; - struct nouveau_pll_vals *pv = ®p->pllvals; + struct nvkm_pll_vals *pv = ®p->pllvals; struct nvbios_pll pll_lim; if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c index 2d8056cde996..d7b495a5f30c 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dac.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dac.c @@ -66,7 +66,7 @@ int nv04_dac_output_offset(struct drm_encoder *encoder) static int sample_load_twice(struct drm_device *dev, bool sense[2]) { struct nvif_device *device = &nouveau_drm(dev)->device; - struct nouveau_timer *ptimer = nvkm_timer(device); + struct nvkm_timer *ptimer = nvxx_timer(device); int i; for (i = 0; i < 2; i++) { @@ -80,17 +80,17 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2]) * use a 10ms timeout (guards against crtc being inactive, in * which case blank state would never change) */ - if (!nouveau_timer_wait_eq(ptimer, 10000000, - NV_PRMCIO_INP0__COLOR, - 0x00000001, 0x00000000)) + if (!nvkm_timer_wait_eq(ptimer, 10000000, + NV_PRMCIO_INP0__COLOR, + 0x00000001, 0x00000000)) return -EBUSY; - if (!nouveau_timer_wait_eq(ptimer, 10000000, - NV_PRMCIO_INP0__COLOR, - 0x00000001, 0x00000001)) + if (!nvkm_timer_wait_eq(ptimer, 10000000, + NV_PRMCIO_INP0__COLOR, + 0x00000001, 0x00000001)) return -EBUSY; - if (!nouveau_timer_wait_eq(ptimer, 10000000, - NV_PRMCIO_INP0__COLOR, - 0x00000001, 0x00000000)) + if (!nvkm_timer_wait_eq(ptimer, 10000000, + NV_PRMCIO_INP0__COLOR, + 0x00000001, 0x00000000)) return -EBUSY; udelay(100); @@ -232,7 +232,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct nouveau_drm *drm = nouveau_drm(dev); struct nvif_device *device = &nouveau_drm(dev)->device; - struct nouveau_gpio *gpio = nvkm_gpio(device); + struct nvkm_gpio *gpio = nvxx_gpio(device); struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c index 42a5435259f7..f6ca343fd34a 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c @@ -623,9 +623,9 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); - struct nouveau_i2c_port *port = i2c->find(i2c, 2); - struct nouveau_i2c_board_info info[] = { + struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c_port *port = i2c->find(i2c, 2); + struct nvkm_i2c_board_info info[] = { { { .type = "sil164", diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c index 3d0afa1c6cff..f96237ef2a6b 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c @@ -32,28 +32,10 @@ #include "nouveau_connector.h" int -nv04_display_early_init(struct drm_device *dev) -{ - /* ensure vblank interrupts are off, they can't be enabled until - * drm_vblank has been initialised - */ - NVWriteCRTC(dev, 0, NV_PCRTC_INTR_EN_0, 0); - if (nv_two_heads(dev)) - NVWriteCRTC(dev, 1, NV_PCRTC_INTR_EN_0, 0); - - return 0; -} - -void -nv04_display_late_takedown(struct drm_device *dev) -{ -} - -int nv04_display_create(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); struct dcb_table *dcb = &drm->vbios.dcb; struct drm_connector *connector, *ct; struct drm_encoder *encoder; diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h index 17b899d9aba3..c910c5d5c662 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h @@ -36,7 +36,7 @@ struct nv04_crtc_reg { /* PRAMDAC regs */ uint32_t nv10_cursync; - struct nouveau_pll_vals pllvals; + struct nvkm_pll_vals pllvals; uint32_t ramdac_gen_ctrl; uint32_t ramdac_630; uint32_t ramdac_634; @@ -90,8 +90,6 @@ nv04_display(struct drm_device *dev) } /* nv04_display.c */ -int nv04_display_early_init(struct drm_device *); -void nv04_display_late_takedown(struct drm_device *); int nv04_display_create(struct drm_device *); void nv04_display_destroy(struct drm_device *); int nv04_display_init(struct drm_device *); @@ -172,7 +170,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, u16 table, struct dcb_output *outp, int crtc) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_bios *bios = nvkm_bios(&drm->device); + struct nvkm_bios *bios = nvxx_bios(&drm->device); struct nvbios_init init = { .subdev = nv_subdev(bios), .bios = bios, diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c index 3d4c19300768..42e07afc4c2b 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c @@ -130,7 +130,7 @@ NVBlankScreen(struct drm_device *dev, int head, bool blank) static void nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, - uint32_t pll2, struct nouveau_pll_vals *pllvals) + uint32_t pll2, struct nvkm_pll_vals *pllvals) { struct nouveau_drm *drm = nouveau_drm(dev); @@ -162,11 +162,11 @@ nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, int nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, - struct nouveau_pll_vals *pllvals) + struct nvkm_pll_vals *pllvals) { struct nouveau_drm *drm = nouveau_drm(dev); struct nvif_device *device = &drm->device; - struct nouveau_bios *bios = nvkm_bios(device); + struct nvkm_bios *bios = nvxx_bios(device); uint32_t reg1, pll1, pll2 = 0; struct nvbios_pll pll_lim; int ret; @@ -202,7 +202,7 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, } int -nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv) +nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) { /* Avoid divide by zero if called at an inappropriate time */ if (!pv->M1 || !pv->M2) @@ -214,7 +214,7 @@ nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv) int nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) { - struct nouveau_pll_vals pllvals; + struct nvkm_pll_vals pllvals; int ret; if (plltype == PLL_MEMORY && @@ -253,10 +253,10 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) struct nouveau_drm *drm = nouveau_drm(dev); struct nvif_device *device = &drm->device; - struct nouveau_clock *clk = nvkm_clock(device); - struct nouveau_bios *bios = nvkm_bios(device); + struct nvkm_clk *clk = nvxx_clk(device); + struct nvkm_bios *bios = nvxx_bios(device); struct nvbios_pll pll_lim; - struct nouveau_pll_vals pv; + struct nvkm_pll_vals pv; enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; if (nvbios_pll_parse(bios, pll, &pll_lim)) @@ -463,7 +463,7 @@ nv_load_state_ramdac(struct drm_device *dev, int head, struct nv04_mode_state *state) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_clock *clk = nvkm_clock(&drm->device); + struct nvkm_clk *clk = nvxx_clk(&drm->device); struct nv04_crtc_reg *regp = &state->crtc_reg[head]; uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; int i; @@ -661,7 +661,7 @@ nv_load_state_ext(struct drm_device *dev, int head, { struct nouveau_drm *drm = nouveau_drm(dev); struct nvif_device *device = &drm->device; - struct nouveau_timer *ptimer = nvkm_timer(device); + struct nvkm_timer *ptimer = nvxx_timer(device); struct nv04_crtc_reg *regp = &state->crtc_reg[head]; uint32_t reg900; int i; @@ -741,8 +741,8 @@ nv_load_state_ext(struct drm_device *dev, int head, if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) { /* Not waiting for vertical retrace before modifying CRE_53/CRE_54 causes lockups. */ - nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); - nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); + nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); + nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); } wr_cio_state(dev, head, regp, NV_CIO_CRE_42); diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.h b/drivers/gpu/drm/nouveau/dispnv04/hw.h index 7f53c571f31f..6c796178bf0c 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.h +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.h @@ -42,8 +42,8 @@ uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index); void NVSetOwner(struct drm_device *, int owner); void NVBlankScreen(struct drm_device *, int head, bool blank); int nouveau_hw_get_pllvals(struct drm_device *, enum nvbios_pll_type plltype, - struct nouveau_pll_vals *pllvals); -int nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pllvals); + struct nvkm_pll_vals *pllvals); +int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pllvals); int nouveau_hw_get_clock(struct drm_device *, enum nvbios_pll_type plltype); void nouveau_hw_save_vga_fonts(struct drm_device *, bool save); void nouveau_hw_save_state(struct drm_device *, int head, diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c index 8061d8d0ce79..d9664b37def1 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c @@ -35,7 +35,7 @@ #include <drm/i2c/ch7006.h> -static struct nouveau_i2c_board_info nv04_tv_encoder_info[] = { +static struct nvkm_i2c_board_info nv04_tv_encoder_info[] = { { { I2C_BOARD_INFO("ch7006", 0x75), @@ -54,7 +54,7 @@ static struct nouveau_i2c_board_info nv04_tv_encoder_info[] = { int nv04_tv_identify(struct drm_device *dev, int i2c_index) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); return i2c->identify(i2c, i2c_index, "TV encoder", nv04_tv_encoder_info, NULL, NULL); @@ -204,8 +204,8 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry) struct drm_encoder *encoder; struct drm_device *dev = connector->dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); - struct nouveau_i2c_port *port = i2c->find(i2c, entry->i2c_index); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c_port *port = i2c->find(i2c, entry->i2c_index); int type, ret; /* Ensure that we can talk to this encoder */ diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c index 72d2ab04db47..731d74efc1e5 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c @@ -46,7 +46,7 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) { struct drm_device *dev = encoder->dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_gpio *gpio = nvkm_gpio(&drm->device); + struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); uint32_t testval, regoffset = nv04_dac_output_offset(encoder); uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; @@ -133,14 +133,14 @@ get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) struct nvif_device *device = &drm->device; /* Zotac FX5200 */ - if (nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x1035) || - nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x2035)) { + if (nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x1035) || + nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x2035)) { *pin_mask = 0xc; return false; } /* MSI nForce2 IGP */ - if (nv_device_match(nvkm_object(device), 0x01f0, 0x1462, 0x5710)) { + if (nv_device_match(nvxx_object(device), 0x01f0, 0x1462, 0x5710)) { *pin_mask = 0xc; return false; } @@ -370,7 +370,7 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) { struct drm_device *dev = encoder->dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_gpio *gpio = nvkm_gpio(&drm->device); + struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 4e308eacb27a..5ad17fc36ae3 100644 --- a/drivers/gpu/drm/nouveau/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -122,18 +122,21 @@ struct nv_device_v0 { #define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL #define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL #define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL -#define NV_DEVICE_V0_DISABLE_GRAPH 0x0000000100000000ULL +#define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL #define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL #define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL #define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL -#define NV_DEVICE_V0_DISABLE_CRYPT 0x0000001000000000ULL +#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL #define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL -#define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL -#define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL -#define NV_DEVICE_V0_DISABLE_COPY1 0x0000010000000000ULL +#define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL +#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL +#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL #define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL -#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL -#define NV_DEVICE_V0_DISABLE_COPY2 0x0000080000000000ULL +#define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL +#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL +#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL +#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL +#define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL __u64 disable; /* disable particular subsystems */ __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ }; @@ -346,9 +349,9 @@ struct nv50_channel_gpfifo_v0 { struct kepler_channel_gpfifo_a_v0 { __u8 version; #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 diff --git a/drivers/gpu/drm/nouveau/nvif/client.h b/drivers/gpu/drm/nouveau/include/nvif/client.h index 28352f0882ec..eca648ef0f7a 100644 --- a/drivers/gpu/drm/nouveau/nvif/client.h +++ b/drivers/gpu/drm/nouveau/include/nvif/client.h @@ -1,7 +1,7 @@ #ifndef __NVIF_CLIENT_H__ #define __NVIF_CLIENT_H__ -#include "object.h" +#include <nvif/object.h> struct nvif_client { struct nvif_object base; @@ -31,9 +31,9 @@ int nvif_client_resume(struct nvif_client *); /*XXX*/ #include <core/client.h> -#define nvkm_client(a) ({ \ +#define nvxx_client(a) ({ \ struct nvif_client *_client = nvif_client(nvif_object(a)); \ - nouveau_client(_client->base.priv); \ + nvkm_client(_client->base.priv); \ }) #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h new file mode 100644 index 000000000000..88553a741ab7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -0,0 +1,61 @@ +#ifndef __NVIF_DEVICE_H__ +#define __NVIF_DEVICE_H__ + +#include <nvif/object.h> +#include <nvif/class.h> + +struct nvif_device { + struct nvif_object base; + struct nvif_object *object; /*XXX: hack for nvif_object() */ + struct nv_device_info_v0 info; +}; + +static inline struct nvif_device * +nvif_device(struct nvif_object *object) +{ + while (object && object->oclass != 0x0080 /*XXX: NV_DEVICE_CLASS*/ ) + object = object->parent; + return (void *)object; +} + +int nvif_device_init(struct nvif_object *, void (*dtor)(struct nvif_device *), + u32 handle, u32 oclass, void *, u32, + struct nvif_device *); +void nvif_device_fini(struct nvif_device *); +int nvif_device_new(struct nvif_object *, u32 handle, u32 oclass, + void *, u32, struct nvif_device **); +void nvif_device_ref(struct nvif_device *, struct nvif_device **); + +/*XXX*/ +#include <subdev/bios.h> +#include <subdev/fb.h> +#include <subdev/mmu.h> +#include <subdev/bar.h> +#include <subdev/gpio.h> +#include <subdev/clk.h> +#include <subdev/i2c.h> +#include <subdev/timer.h> +#include <subdev/therm.h> + +#define nvxx_device(a) nv_device(nvxx_object((a))) +#define nvxx_bios(a) nvkm_bios(nvxx_device(a)) +#define nvxx_fb(a) nvkm_fb(nvxx_device(a)) +#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a)) +#define nvxx_bar(a) nvkm_bar(nvxx_device(a)) +#define nvxx_gpio(a) nvkm_gpio(nvxx_device(a)) +#define nvxx_clk(a) nvkm_clk(nvxx_device(a)) +#define nvxx_i2c(a) nvkm_i2c(nvxx_device(a)) +#define nvxx_timer(a) nvkm_timer(nvxx_device(a)) +#define nvxx_wait(a,b,c,d) nv_wait(nvxx_timer(a), (b), (c), (d)) +#define nvxx_wait_cb(a,b,c) nv_wait_cb(nvxx_timer(a), (b), (c)) +#define nvxx_therm(a) nvkm_therm(nvxx_device(a)) + +#include <core/device.h> +#include <engine/fifo.h> +#include <engine/gr.h> +#include <engine/sw.h> + +#define nvxx_fifo(a) nvkm_fifo(nvxx_device(a)) +#define nvxx_fifo_chan(a) ((struct nvkm_fifo_chan *)nvxx_object(a)) +#define nvxx_gr(a) ((struct nvkm_gr *)nvkm_engine(nvxx_object(a), NVDEV_ENGINE_GR)) +#endif diff --git a/drivers/gpu/drm/nouveau/nvif/driver.h b/drivers/gpu/drm/nouveau/include/nvif/driver.h index 8bd39e69229c..8bd39e69229c 100644 --- a/drivers/gpu/drm/nouveau/nvif/driver.h +++ b/drivers/gpu/drm/nouveau/include/nvif/driver.h diff --git a/drivers/gpu/drm/nouveau/nvif/event.h b/drivers/gpu/drm/nouveau/include/nvif/event.h index 21764499b4be..21764499b4be 100644 --- a/drivers/gpu/drm/nouveau/nvif/event.h +++ b/drivers/gpu/drm/nouveau/include/nvif/event.h diff --git a/drivers/gpu/drm/nouveau/nvif/ioctl.h b/drivers/gpu/drm/nouveau/include/nvif/ioctl.h index 4cd8e323b23d..4cd8e323b23d 100644 --- a/drivers/gpu/drm/nouveau/nvif/ioctl.h +++ b/drivers/gpu/drm/nouveau/include/nvif/ioctl.h diff --git a/drivers/gpu/drm/nouveau/nvif/list.h b/drivers/gpu/drm/nouveau/include/nvif/list.h index 8af5d144ecb0..8af5d144ecb0 100644 --- a/drivers/gpu/drm/nouveau/nvif/list.h +++ b/drivers/gpu/drm/nouveau/include/nvif/list.h diff --git a/drivers/gpu/drm/nouveau/nvif/notify.h b/drivers/gpu/drm/nouveau/include/nvif/notify.h index 9ebfa3b45e76..9ebfa3b45e76 100644 --- a/drivers/gpu/drm/nouveau/nvif/notify.h +++ b/drivers/gpu/drm/nouveau/include/nvif/notify.h diff --git a/drivers/gpu/drm/nouveau/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h index fe519179b76c..04c874707b96 100644 --- a/drivers/gpu/drm/nouveau/nvif/object.h +++ b/drivers/gpu/drm/nouveau/include/nvif/object.h @@ -70,6 +70,6 @@ void nvif_object_unmap(struct nvif_object *); /*XXX*/ #include <core/object.h> -#define nvkm_object(a) ((struct nouveau_object *)nvif_object(a)->priv) +#define nvxx_object(a) ((struct nvkm_object *)nvif_object(a)->priv) #endif diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/include/nvif/os.h index bdd05ee7ec72..bdd05ee7ec72 100644 --- a/drivers/gpu/drm/nouveau/core/os.h +++ b/drivers/gpu/drm/nouveau/include/nvif/os.h diff --git a/drivers/gpu/drm/nouveau/nvif/unpack.h b/drivers/gpu/drm/nouveau/include/nvif/unpack.h index 5933188b4a77..5933188b4a77 100644 --- a/drivers/gpu/drm/nouveau/nvif/unpack.h +++ b/drivers/gpu/drm/nouveau/include/nvif/unpack.h diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h new file mode 100644 index 000000000000..a35b38244502 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -0,0 +1,55 @@ +#ifndef __NVKM_CLIENT_H__ +#define __NVKM_CLIENT_H__ +#include <core/namedb.h> + +struct nvkm_client { + struct nvkm_namedb namedb; + struct nvkm_handle *root; + struct nvkm_object *device; + char name[32]; + u32 debug; + struct nvkm_vm *vm; + bool super; + void *data; + + int (*ntfy)(const void *, u32, const void *, u32); + struct nvkm_client_notify *notify[16]; +}; + +static inline struct nvkm_client * +nv_client(void *obj) +{ +#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA + if (unlikely(!nv_iclass(obj, NV_CLIENT_CLASS))) + nv_assert("BAD CAST -> NvClient, %08x", nv_hclass(obj)); +#endif + return obj; +} + +static inline struct nvkm_client * +nvkm_client(void *obj) +{ + struct nvkm_object *client = nv_object(obj); + while (client && !(nv_iclass(client, NV_CLIENT_CLASS))) + client = client->parent; + return (void *)client; +} + +#define nvkm_client_create(n,c,oc,od,d) \ + nvkm_client_create_((n), (c), (oc), (od), sizeof(**d), (void **)d) + +int nvkm_client_create_(const char *name, u64 device, const char *cfg, + const char *dbg, int, void **); +#define nvkm_client_destroy(p) \ + nvkm_namedb_destroy(&(p)->base) + +int nvkm_client_init(struct nvkm_client *); +int nvkm_client_fini(struct nvkm_client *, bool suspend); +const char *nvkm_client_name(void *obj); + +int nvkm_client_notify_new(struct nvkm_object *, struct nvkm_event *, + void *data, u32 size); +int nvkm_client_notify_del(struct nvkm_client *, int index); +int nvkm_client_notify_get(struct nvkm_client *, int index); +int nvkm_client_notify_put(struct nvkm_client *, int index); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/debug.h b/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h index 8092e2e90323..d07cb860b56c 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/debug.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h @@ -1,6 +1,5 @@ -#ifndef __NOUVEAU_DEBUG_H__ -#define __NOUVEAU_DEBUG_H__ - +#ifndef __NVKM_DEBUG_H__ +#define __NVKM_DEBUG_H__ extern int nv_info_debug_level; #define NV_DBG_FATAL 0 @@ -16,5 +15,4 @@ extern int nv_info_debug_level; #define NV_DBG_INFO_SILENT NV_DBG_DEBUG #define nv_debug_level(a) nv_info_debug_level = NV_DBG_INFO_##a - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h new file mode 100644 index 000000000000..333db33a162c --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -0,0 +1,101 @@ +#ifndef __NVKM_DEVICE_H__ +#define __NVKM_DEVICE_H__ +#include <core/engine.h> +#include <core/event.h> + +struct nvkm_device { + struct nvkm_engine engine; + struct list_head head; + + struct pci_dev *pdev; + struct platform_device *platformdev; + u64 handle; + + struct nvkm_event event; + + const char *cfgopt; + const char *dbgopt; + const char *name; + const char *cname; + u64 disable_mask; + + enum { + NV_04 = 0x04, + NV_10 = 0x10, + NV_11 = 0x11, + NV_20 = 0x20, + NV_30 = 0x30, + NV_40 = 0x40, + NV_50 = 0x50, + NV_C0 = 0xc0, + NV_E0 = 0xe0, + GM100 = 0x110, + } card_type; + u32 chipset; + u8 chiprev; + u32 crystal; + + struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR]; + struct nvkm_object *subdev[NVDEV_SUBDEV_NR]; + + struct { + struct notifier_block nb; + } acpi; +}; + +struct nvkm_device *nvkm_device_find(u64 name); +int nvkm_device_list(u64 *name, int size); + +struct nvkm_device *nv_device(void *obj); + +static inline bool +nv_device_match(struct nvkm_object *object, u16 dev, u16 ven, u16 sub) +{ + struct nvkm_device *device = nv_device(object); + return device->pdev->device == dev && + device->pdev->subsystem_vendor == ven && + device->pdev->subsystem_device == sub; +} + +static inline bool +nv_device_is_pci(struct nvkm_device *device) +{ + return device->pdev != NULL; +} + +static inline bool +nv_device_is_cpu_coherent(struct nvkm_device *device) +{ + return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device)); +} + +static inline struct device * +nv_device_base(struct nvkm_device *device) +{ + return nv_device_is_pci(device) ? &device->pdev->dev : + &device->platformdev->dev; +} + +resource_size_t +nv_device_resource_start(struct nvkm_device *device, unsigned int bar); + +resource_size_t +nv_device_resource_len(struct nvkm_device *device, unsigned int bar); + +int +nv_device_get_irq(struct nvkm_device *device, bool stall); + +struct platform_device; + +enum nv_bus_type { + NVKM_BUS_PCI, + NVKM_BUS_PLATFORM, +}; + +#define nvkm_device_create(p,t,n,s,c,d,u) \ + nvkm_device_create_((void *)(p), (t), (n), (s), (c), (d), \ + sizeof(**u), (void **)u) +int nvkm_device_create_(void *, enum nv_bus_type type, u64 name, + const char *sname, const char *cfg, const char *dbg, + int, void **); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h new file mode 100644 index 000000000000..60c5888b5df3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h @@ -0,0 +1,62 @@ +#ifndef __NVKM_DEVIDX_H__ +#define __NVKM_DEVIDX_H__ +enum nvkm_devidx { + NVDEV_ENGINE_DEVICE, + NVDEV_SUBDEV_VBIOS, + + /* All subdevs from DEVINIT to DEVINIT_LAST will be created before + * *any* of them are initialised. This subdev category is used + * for any subdevs that the VBIOS init table parsing may call out + * to during POST. + */ + NVDEV_SUBDEV_DEVINIT, + NVDEV_SUBDEV_IBUS, + NVDEV_SUBDEV_GPIO, + NVDEV_SUBDEV_I2C, + NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C, + + /* This grouping of subdevs are initialised right after they've + * been created, and are allowed to assume any subdevs in the + * list above them exist and have been initialised. + */ + NVDEV_SUBDEV_FUSE, + NVDEV_SUBDEV_MXM, + NVDEV_SUBDEV_MC, + NVDEV_SUBDEV_BUS, + NVDEV_SUBDEV_TIMER, + NVDEV_SUBDEV_FB, + NVDEV_SUBDEV_LTC, + NVDEV_SUBDEV_INSTMEM, + NVDEV_SUBDEV_MMU, + NVDEV_SUBDEV_BAR, + NVDEV_SUBDEV_PMU, + NVDEV_SUBDEV_VOLT, + NVDEV_SUBDEV_THERM, + NVDEV_SUBDEV_CLK, + + NVDEV_ENGINE_FIRST, + NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, + NVDEV_ENGINE_IFB, + NVDEV_ENGINE_FIFO, + NVDEV_ENGINE_SW, + NVDEV_ENGINE_GR, + NVDEV_ENGINE_MPEG, + NVDEV_ENGINE_ME, + NVDEV_ENGINE_VP, + NVDEV_ENGINE_CIPHER, + NVDEV_ENGINE_BSP, + NVDEV_ENGINE_MSPPP, + NVDEV_ENGINE_CE0, + NVDEV_ENGINE_CE1, + NVDEV_ENGINE_CE2, + NVDEV_ENGINE_VIC, + NVDEV_ENGINE_MSENC, + NVDEV_ENGINE_DISP, + NVDEV_ENGINE_PM, + NVDEV_ENGINE_MSVLD, + NVDEV_ENGINE_SEC, + NVDEV_ENGINE_MSPDEC, + + NVDEV_SUBDEV_NR, +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h new file mode 100644 index 000000000000..1bf2e8eb4268 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h @@ -0,0 +1,51 @@ +#ifndef __NVKM_ENGCTX_H__ +#define __NVKM_ENGCTX_H__ +#include <core/gpuobj.h> + +#include <subdev/mmu.h> + +#define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng)) +#define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var)) + +struct nvkm_engctx { + struct nvkm_gpuobj gpuobj; + struct nvkm_vma vma; + struct list_head head; + unsigned long save; + u64 addr; +}; + +static inline struct nvkm_engctx * +nv_engctx(void *obj) +{ +#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA + if (unlikely(!nv_iclass(obj, NV_ENGCTX_CLASS))) + nv_assert("BAD CAST -> NvEngCtx, %08x", nv_hclass(obj)); +#endif + return obj; +} + +#define nvkm_engctx_create(p,e,c,g,s,a,f,d) \ + nvkm_engctx_create_((p), (e), (c), (g), (s), (a), (f), \ + sizeof(**d), (void **)d) + +int nvkm_engctx_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, struct nvkm_object *, + u32 size, u32 align, u32 flags, + int length, void **data); +void nvkm_engctx_destroy(struct nvkm_engctx *); +int nvkm_engctx_init(struct nvkm_engctx *); +int nvkm_engctx_fini(struct nvkm_engctx *, bool suspend); + +int _nvkm_engctx_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void _nvkm_engctx_dtor(struct nvkm_object *); +int _nvkm_engctx_init(struct nvkm_object *); +int _nvkm_engctx_fini(struct nvkm_object *, bool suspend); +#define _nvkm_engctx_rd32 _nvkm_gpuobj_rd32 +#define _nvkm_engctx_wr32 _nvkm_gpuobj_wr32 + +struct nvkm_object *nvkm_engctx_get(struct nvkm_engine *, u64 addr); +void nvkm_engctx_put(struct nvkm_object *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h new file mode 100644 index 000000000000..faf0fd2f0638 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h @@ -0,0 +1,56 @@ +#ifndef __NVKM_ENGINE_H__ +#define __NVKM_ENGINE_H__ +#include <core/subdev.h> + +#define NV_ENGINE_(eng,var) (NV_ENGINE_CLASS | ((var) << 8) | (eng)) +#define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var)) + +struct nvkm_engine { + struct nvkm_subdev subdev; + struct nvkm_oclass *cclass; + struct nvkm_oclass *sclass; + + struct list_head contexts; + spinlock_t lock; + + void (*tile_prog)(struct nvkm_engine *, int region); + int (*tlb_flush)(struct nvkm_engine *); +}; + +static inline struct nvkm_engine * +nv_engine(void *obj) +{ +#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA + if (unlikely(!nv_iclass(obj, NV_ENGINE_CLASS))) + nv_assert("BAD CAST -> NvEngine, %08x", nv_hclass(obj)); +#endif + return obj; +} + +static inline int +nv_engidx(struct nvkm_engine *engine) +{ + return nv_subidx(&engine->subdev); +} + +struct nvkm_engine *nvkm_engine(void *obj, int idx); + +#define nvkm_engine_create(p,e,c,d,i,f,r) \ + nvkm_engine_create_((p), (e), (c), (d), (i), (f), \ + sizeof(**r),(void **)r) + +#define nvkm_engine_destroy(p) \ + nvkm_subdev_destroy(&(p)->subdev) +#define nvkm_engine_init(p) \ + nvkm_subdev_init(&(p)->subdev) +#define nvkm_engine_fini(p,s) \ + nvkm_subdev_fini(&(p)->subdev, (s)) + +int nvkm_engine_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, bool, const char *, + const char *, int, void **); + +#define _nvkm_engine_dtor _nvkm_subdev_dtor +#define _nvkm_engine_init _nvkm_subdev_init +#define _nvkm_engine_fini _nvkm_subdev_fini +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h new file mode 100644 index 000000000000..e76f76f115e9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h @@ -0,0 +1,21 @@ +#ifndef __NVKM_ENUM_H__ +#define __NVKM_ENUM_H__ +#include <core/os.h> + +struct nvkm_enum { + u32 value; + const char *name; + const void *data; + u32 data2; +}; + +const struct nvkm_enum *nvkm_enum_find(const struct nvkm_enum *, u32 value); +const struct nvkm_enum *nvkm_enum_print(const struct nvkm_enum *, u32 value); + +struct nvkm_bitfield { + u32 mask; + const char *name; +}; + +void nvkm_bitfield_print(const struct nvkm_bitfield *, u32 value); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/event.h b/drivers/gpu/drm/nouveau/include/nvkm/core/event.h index 92876528972f..b98fe2de546a 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/event.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/event.h @@ -1,15 +1,8 @@ #ifndef __NVKM_EVENT_H__ #define __NVKM_EVENT_H__ - -#include <core/notify.h> - -struct nvkm_event_func { - int (*ctor)(struct nouveau_object *, void *data, u32 size, - struct nvkm_notify *); - void (*send)(void *data, u32 size, struct nvkm_notify *); - void (*init)(struct nvkm_event *, int type, int index); - void (*fini)(struct nvkm_event *, int type, int index); -}; +#include <core/os.h> +struct nvkm_notify; +struct nvkm_object; struct nvkm_event { const struct nvkm_event_func *func; @@ -23,13 +16,19 @@ struct nvkm_event { int *refs; }; -int nvkm_event_init(const struct nvkm_event_func *func, - int types_nr, int index_nr, - struct nvkm_event *); +struct nvkm_event_func { + int (*ctor)(struct nvkm_object *, void *data, u32 size, + struct nvkm_notify *); + void (*send)(void *data, u32 size, struct nvkm_notify *); + void (*init)(struct nvkm_event *, int type, int index); + void (*fini)(struct nvkm_event *, int type, int index); +}; + +int nvkm_event_init(const struct nvkm_event_func *func, int types_nr, + int index_nr, struct nvkm_event *); void nvkm_event_fini(struct nvkm_event *); void nvkm_event_get(struct nvkm_event *, u32 types, int index); void nvkm_event_put(struct nvkm_event *, u32 types, int index); void nvkm_event_send(struct nvkm_event *, u32 types, int index, void *data, u32 size); - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h new file mode 100644 index 000000000000..e0187e7abb6e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h @@ -0,0 +1,64 @@ +#ifndef __NVKM_GPUOBJ_H__ +#define __NVKM_GPUOBJ_H__ +#include <core/object.h> +#include <core/mm.h> +struct nvkm_vma; +struct nvkm_vm; + +#define NVOBJ_FLAG_ZERO_ALLOC 0x00000001 +#define NVOBJ_FLAG_ZERO_FREE 0x00000002 +#define NVOBJ_FLAG_HEAP 0x00000004 + +struct nvkm_gpuobj { + struct nvkm_object object; + struct nvkm_object *parent; + struct nvkm_mm_node *node; + struct nvkm_mm heap; + + u32 flags; + u64 addr; + u32 size; +}; + +static inline struct nvkm_gpuobj * +nv_gpuobj(void *obj) +{ +#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA + if (unlikely(!nv_iclass(obj, NV_GPUOBJ_CLASS))) + nv_assert("BAD CAST -> NvGpuObj, %08x", nv_hclass(obj)); +#endif + return obj; +} + +#define nvkm_gpuobj_create(p,e,c,v,g,s,a,f,d) \ + nvkm_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \ + sizeof(**d), (void **)d) +#define nvkm_gpuobj_init(p) nvkm_object_init(&(p)->object) +#define nvkm_gpuobj_fini(p,s) nvkm_object_fini(&(p)->object, (s)) +int nvkm_gpuobj_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, u32 pclass, + struct nvkm_object *, u32 size, u32 align, + u32 flags, int length, void **); +void nvkm_gpuobj_destroy(struct nvkm_gpuobj *); + +int nvkm_gpuobj_new(struct nvkm_object *, struct nvkm_object *, u32 size, + u32 align, u32 flags, struct nvkm_gpuobj **); +int nvkm_gpuobj_dup(struct nvkm_object *, struct nvkm_gpuobj *, + struct nvkm_gpuobj **); +int nvkm_gpuobj_map(struct nvkm_gpuobj *, u32 acc, struct nvkm_vma *); +int nvkm_gpuobj_map_vm(struct nvkm_gpuobj *, struct nvkm_vm *, u32 access, + struct nvkm_vma *); +void nvkm_gpuobj_unmap(struct nvkm_vma *); + +static inline void +nvkm_gpuobj_ref(struct nvkm_gpuobj *obj, struct nvkm_gpuobj **ref) +{ + nvkm_object_ref(&obj->object, (struct nvkm_object **)ref); +} + +void _nvkm_gpuobj_dtor(struct nvkm_object *); +int _nvkm_gpuobj_init(struct nvkm_object *); +int _nvkm_gpuobj_fini(struct nvkm_object *, bool); +u32 _nvkm_gpuobj_rd32(struct nvkm_object *, u64); +void _nvkm_gpuobj_wr32(struct nvkm_object *, u64, u32); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h b/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h new file mode 100644 index 000000000000..67f384d0916c --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h @@ -0,0 +1,34 @@ +#ifndef __NVKM_HANDLE_H__ +#define __NVKM_HANDLE_H__ +#include <core/os.h> +struct nvkm_object; + +struct nvkm_handle { + struct nvkm_namedb *namedb; + struct list_head node; + + struct list_head head; + struct list_head tree; + u32 name; + u32 priv; + + u8 route; + u64 token; + + struct nvkm_handle *parent; + struct nvkm_object *object; +}; + +int nvkm_handle_create(struct nvkm_object *, u32 parent, u32 handle, + struct nvkm_object *, struct nvkm_handle **); +void nvkm_handle_destroy(struct nvkm_handle *); +int nvkm_handle_init(struct nvkm_handle *); +int nvkm_handle_fini(struct nvkm_handle *, bool suspend); + +struct nvkm_object *nvkm_handle_ref(struct nvkm_object *, u32 name); + +struct nvkm_handle *nvkm_handle_get_class(struct nvkm_object *, u16); +struct nvkm_handle *nvkm_handle_get_vinst(struct nvkm_object *, u64); +struct nvkm_handle *nvkm_handle_get_cinst(struct nvkm_object *, u32); +void nvkm_handle_put(struct nvkm_handle *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h b/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h new file mode 100644 index 000000000000..88971eb37afa --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h @@ -0,0 +1,7 @@ +#ifndef __NVKM_IOCTL_H__ +#define __NVKM_IOCTL_H__ +#include <core/os.h> +struct nvkm_client; + +int nvkm_ioctl(struct nvkm_client *, bool, void *, u32, void **); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h new file mode 100644 index 000000000000..096eb1a623ee --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h @@ -0,0 +1,40 @@ +#ifndef __NVKM_MM_H__ +#define __NVKM_MM_H__ +#include <core/os.h> + +struct nvkm_mm_node { + struct list_head nl_entry; + struct list_head fl_entry; + struct list_head rl_entry; + +#define NVKM_MM_HEAP_ANY 0x00 + u8 heap; +#define NVKM_MM_TYPE_NONE 0x00 +#define NVKM_MM_TYPE_HOLE 0xff + u8 type; + u32 offset; + u32 length; +}; + +struct nvkm_mm { + struct list_head nodes; + struct list_head free; + + u32 block_size; + int heap_nodes; +}; + +static inline bool +nvkm_mm_initialised(struct nvkm_mm *mm) +{ + return mm->block_size != 0; +} + +int nvkm_mm_init(struct nvkm_mm *, u32 offset, u32 length, u32 block); +int nvkm_mm_fini(struct nvkm_mm *); +int nvkm_mm_head(struct nvkm_mm *, u8 heap, u8 type, u32 size_max, + u32 size_min, u32 align, struct nvkm_mm_node **); +int nvkm_mm_tail(struct nvkm_mm *, u8 heap, u8 type, u32 size_max, + u32 size_min, u32 align, struct nvkm_mm_node **); +void nvkm_mm_free(struct nvkm_mm *, struct nvkm_mm_node **); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h b/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h new file mode 100644 index 000000000000..4cfe16fcde9b --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h @@ -0,0 +1,53 @@ +#ifndef __NVKM_NAMEDB_H__ +#define __NVKM_NAMEDB_H__ +#include <core/parent.h> +struct nvkm_handle; + +struct nvkm_namedb { + struct nvkm_parent parent; + rwlock_t lock; + struct list_head list; +}; + +static inline struct nvkm_namedb * +nv_namedb(void *obj) +{ +#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA + if (unlikely(!nv_iclass(obj, NV_NAMEDB_CLASS))) + nv_assert("BAD CAST -> NvNameDB, %08x", nv_hclass(obj)); +#endif + return obj; +} + +#define nvkm_namedb_create(p,e,c,v,s,m,d) \ + nvkm_namedb_create_((p), (e), (c), (v), (s), (m), \ + sizeof(**d), (void **)d) +#define nvkm_namedb_init(p) \ + nvkm_parent_init(&(p)->parent) +#define nvkm_namedb_fini(p,s) \ + nvkm_parent_fini(&(p)->parent, (s)) +#define nvkm_namedb_destroy(p) \ + nvkm_parent_destroy(&(p)->parent) + +int nvkm_namedb_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, u32 pclass, + struct nvkm_oclass *, u64 engcls, + int size, void **); + +int _nvkm_namedb_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +#define _nvkm_namedb_dtor _nvkm_parent_dtor +#define _nvkm_namedb_init _nvkm_parent_init +#define _nvkm_namedb_fini _nvkm_parent_fini + +int nvkm_namedb_insert(struct nvkm_namedb *, u32 name, struct nvkm_object *, + struct nvkm_handle *); +void nvkm_namedb_remove(struct nvkm_handle *); + +struct nvkm_handle *nvkm_namedb_get(struct nvkm_namedb *, u32); +struct nvkm_handle *nvkm_namedb_get_class(struct nvkm_namedb *, u16); +struct nvkm_handle *nvkm_namedb_get_vinst(struct nvkm_namedb *, u64); +struct nvkm_handle *nvkm_namedb_get_cinst(struct nvkm_namedb *, u32); +void nvkm_namedb_put(struct nvkm_handle *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/notify.h b/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h index a7c3c5f578cc..753d08c1767b 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/notify.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h @@ -1,5 +1,7 @@ #ifndef __NVKM_NOTIFY_H__ #define __NVKM_NOTIFY_H__ +#include <core/os.h> +struct nvkm_object; struct nvkm_notify { struct nvkm_event *event; @@ -25,7 +27,7 @@ struct nvkm_notify { const void *data; }; -int nvkm_notify_init(struct nouveau_object *, struct nvkm_event *, +int nvkm_notify_init(struct nvkm_object *, struct nvkm_event *, int (*func)(struct nvkm_notify *), bool work, void *data, u32 size, u32 reply, struct nvkm_notify *); @@ -33,5 +35,4 @@ void nvkm_notify_fini(struct nvkm_notify *); void nvkm_notify_get(struct nvkm_notify *); void nvkm_notify_put(struct nvkm_notify *); void nvkm_notify_send(struct nvkm_notify *, void *data, u32 size); - #endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/object.h b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h index 2e2afa502c99..6e3cd3908400 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/object.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h @@ -1,6 +1,5 @@ -#ifndef __NOUVEAU_OBJECT_H__ -#define __NOUVEAU_OBJECT_H__ - +#ifndef __NVKM_OBJECT_H__ +#define __NVKM_OBJECT_H__ #include <core/os.h> #include <core/printk.h> @@ -14,52 +13,52 @@ #define NV_ENGCTX_CLASS 0x01000000 #define NV_OBJECT_CLASS 0x0000ffff -struct nouveau_object { - struct nouveau_oclass *oclass; - struct nouveau_object *parent; - struct nouveau_object *engine; +struct nvkm_object { + struct nvkm_oclass *oclass; + struct nvkm_object *parent; + struct nvkm_engine *engine; atomic_t refcount; atomic_t usecount; #if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA -#define NOUVEAU_OBJECT_MAGIC 0x75ef0bad +#define NVKM_OBJECT_MAGIC 0x75ef0bad struct list_head list; u32 _magic; #endif }; -static inline struct nouveau_object * +static inline struct nvkm_object * nv_object(void *obj) { #if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA if (likely(obj)) { - struct nouveau_object *object = obj; - if (unlikely(object->_magic != NOUVEAU_OBJECT_MAGIC)) + struct nvkm_object *object = obj; + if (unlikely(object->_magic != NVKM_OBJECT_MAGIC)) nv_assert("BAD CAST -> NvObject, invalid magic"); } #endif return obj; } -#define nouveau_object_create(p,e,c,s,d) \ - nouveau_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d) -int nouveau_object_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, u32, int size, void **); -void nouveau_object_destroy(struct nouveau_object *); -int nouveau_object_init(struct nouveau_object *); -int nouveau_object_fini(struct nouveau_object *, bool suspend); +#define nvkm_object_create(p,e,c,s,d) \ + nvkm_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d) +int nvkm_object_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, u32, int size, void **); +void nvkm_object_destroy(struct nvkm_object *); +int nvkm_object_init(struct nvkm_object *); +int nvkm_object_fini(struct nvkm_object *, bool suspend); -int _nouveau_object_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); +int _nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); -extern struct nouveau_ofuncs nouveau_object_ofuncs; +extern struct nvkm_ofuncs nvkm_object_ofuncs; /* Don't allocate dynamically, because lockdep needs lock_class_keys to be in * ".data". */ -struct nouveau_oclass { +struct nvkm_oclass { u32 handle; - struct nouveau_ofuncs * const ofuncs; - struct nouveau_omthds * const omthds; + struct nvkm_ofuncs * const ofuncs; + struct nvkm_omthds * const omthds; struct lock_class_key lock_class_key; }; @@ -68,58 +67,57 @@ struct nouveau_oclass { #define nv_iclass(o,i) (nv_hclass(o) & (i)) #define nv_mclass(o) nv_iclass(o, NV_OBJECT_CLASS) -static inline struct nouveau_object * -nv_pclass(struct nouveau_object *parent, u32 oclass) +static inline struct nvkm_object * +nv_pclass(struct nvkm_object *parent, u32 oclass) { while (parent && !nv_iclass(parent, oclass)) parent = parent->parent; return parent; } -struct nouveau_omthds { +struct nvkm_omthds { u32 start; u32 limit; - int (*call)(struct nouveau_object *, u32, void *, u32); + int (*call)(struct nvkm_object *, u32, void *, u32); }; struct nvkm_event; -struct nouveau_ofuncs { - int (*ctor)(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *data, u32 size, - struct nouveau_object **); - void (*dtor)(struct nouveau_object *); - int (*init)(struct nouveau_object *); - int (*fini)(struct nouveau_object *, bool suspend); - int (*mthd)(struct nouveau_object *, u32, void *, u32); - int (*ntfy)(struct nouveau_object *, u32, struct nvkm_event **); - int (* map)(struct nouveau_object *, u64 *, u32 *); - u8 (*rd08)(struct nouveau_object *, u64 offset); - u16 (*rd16)(struct nouveau_object *, u64 offset); - u32 (*rd32)(struct nouveau_object *, u64 offset); - void (*wr08)(struct nouveau_object *, u64 offset, u8 data); - void (*wr16)(struct nouveau_object *, u64 offset, u16 data); - void (*wr32)(struct nouveau_object *, u64 offset, u32 data); +struct nvkm_ofuncs { + int (*ctor)(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *data, u32 size, + struct nvkm_object **); + void (*dtor)(struct nvkm_object *); + int (*init)(struct nvkm_object *); + int (*fini)(struct nvkm_object *, bool suspend); + int (*mthd)(struct nvkm_object *, u32, void *, u32); + int (*ntfy)(struct nvkm_object *, u32, struct nvkm_event **); + int (* map)(struct nvkm_object *, u64 *, u32 *); + u8 (*rd08)(struct nvkm_object *, u64 offset); + u16 (*rd16)(struct nvkm_object *, u64 offset); + u32 (*rd32)(struct nvkm_object *, u64 offset); + void (*wr08)(struct nvkm_object *, u64 offset, u8 data); + void (*wr16)(struct nvkm_object *, u64 offset, u16 data); + void (*wr32)(struct nvkm_object *, u64 offset, u32 data); }; -static inline struct nouveau_ofuncs * +static inline struct nvkm_ofuncs * nv_ofuncs(void *obj) { return nv_oclass(obj)->ofuncs; } -int nouveau_object_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nouveau_object_ref(struct nouveau_object *, struct nouveau_object **); -int nouveau_object_inc(struct nouveau_object *); -int nouveau_object_dec(struct nouveau_object *, bool suspend); - -void nouveau_object_debug(void); +int nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nvkm_object_ref(struct nvkm_object *, struct nvkm_object **); +int nvkm_object_inc(struct nvkm_object *); +int nvkm_object_dec(struct nvkm_object *, bool suspend); +void nvkm_object_debug(void); static inline int nv_exec(void *obj, u32 mthd, void *data, u32 size) { - struct nouveau_omthds *method = nv_oclass(obj)->omthds; + struct nvkm_omthds *method = nv_oclass(obj)->omthds; while (method && method->call) { if (mthd >= method->start && mthd <= method->limit) @@ -202,5 +200,4 @@ nv_memcmp(void *obj, u32 addr, const char *str, u32 len) } return 0; } - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/option.h b/drivers/gpu/drm/nouveau/include/nvkm/core/option.h new file mode 100644 index 000000000000..532bfa8e3f72 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/option.h @@ -0,0 +1,17 @@ +#ifndef __NVKM_OPTION_H__ +#define __NVKM_OPTION_H__ +#include <core/os.h> + +const char *nvkm_stropt(const char *optstr, const char *opt, int *len); +bool nvkm_boolopt(const char *optstr, const char *opt, bool value); +int nvkm_dbgopt(const char *optstr, const char *sub); + +/* compares unterminated string 'str' with zero-terminated string 'cmp' */ +static inline int +strncasecmpz(const char *str, const char *cmp, size_t len) +{ + if (strlen(cmp) != len) + return len; + return strncasecmp(str, cmp, len); +} +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h new file mode 100644 index 000000000000..cd57e238ddd3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h @@ -0,0 +1,4 @@ +#ifndef __NVKM_OS_H__ +#define __NVKM_OS_H__ +#include <nvif/os.h> +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h b/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h new file mode 100644 index 000000000000..837e4fe966a5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h @@ -0,0 +1,58 @@ +#ifndef __NVKM_PARENT_H__ +#define __NVKM_PARENT_H__ +#include <core/object.h> + +struct nvkm_sclass { + struct nvkm_sclass *sclass; + struct nvkm_engine *engine; + struct nvkm_oclass *oclass; +}; + +struct nvkm_parent { + struct nvkm_object object; + + struct nvkm_sclass *sclass; + u64 engine; + + int (*context_attach)(struct nvkm_object *, struct nvkm_object *); + int (*context_detach)(struct nvkm_object *, bool suspend, + struct nvkm_object *); + + int (*object_attach)(struct nvkm_object *parent, + struct nvkm_object *object, u32 name); + void (*object_detach)(struct nvkm_object *parent, int cookie); +}; + +static inline struct nvkm_parent * +nv_parent(void *obj) +{ +#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA + if (unlikely(!(nv_iclass(obj, NV_PARENT_CLASS)))) + nv_assert("BAD CAST -> NvParent, %08x", nv_hclass(obj)); +#endif + return obj; +} + +#define nvkm_parent_create(p,e,c,v,s,m,d) \ + nvkm_parent_create_((p), (e), (c), (v), (s), (m), \ + sizeof(**d), (void **)d) +#define nvkm_parent_init(p) \ + nvkm_object_init(&(p)->object) +#define nvkm_parent_fini(p,s) \ + nvkm_object_fini(&(p)->object, (s)) + +int nvkm_parent_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, u32 pclass, + struct nvkm_oclass *, u64 engcls, + int size, void **); +void nvkm_parent_destroy(struct nvkm_parent *); + +void _nvkm_parent_dtor(struct nvkm_object *); +#define _nvkm_parent_init nvkm_object_init +#define _nvkm_parent_fini nvkm_object_fini + +int nvkm_parent_sclass(struct nvkm_object *, u16 handle, + struct nvkm_object **pengine, + struct nvkm_oclass **poclass); +int nvkm_parent_lclass(struct nvkm_object *, u32 *, int); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/printk.h b/drivers/gpu/drm/nouveau/include/nvkm/core/printk.h index 451b6ed20b7e..83648177059f 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/printk.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/printk.h @@ -1,13 +1,11 @@ -#ifndef __NOUVEAU_PRINTK_H__ -#define __NOUVEAU_PRINTK_H__ - +#ifndef __NVKM_PRINTK_H__ +#define __NVKM_PRINTK_H__ #include <core/os.h> #include <core/debug.h> - -struct nouveau_object; +struct nvkm_object; void __printf(3, 4) -nv_printk_(struct nouveau_object *, int, const char *, ...); +nv_printk_(struct nvkm_object *, int, const char *, ...); #define nv_printk(o,l,f,a...) do { \ if (NV_DBG_##l <= CONFIG_NOUVEAU_DEBUG) \ @@ -21,12 +19,11 @@ nv_printk_(struct nouveau_object *, int, const char *, ...); #define nv_debug(o,f,a...) nv_printk((o), DEBUG, f, ##a) #define nv_trace(o,f,a...) nv_printk((o), TRACE, f, ##a) #define nv_spam(o,f,a...) nv_printk((o), SPAM, f, ##a) -#define nv_ioctl(o,f,a...) nv_trace(nouveau_client(o), "ioctl: "f, ##a) +#define nv_ioctl(o,f,a...) nv_trace(nvkm_client(o), "ioctl: "f, ##a) #define nv_assert(f,a...) do { \ if (NV_DBG_FATAL <= CONFIG_NOUVEAU_DEBUG) \ nv_printk_(NULL, NV_DBG_FATAL, f "\n", ##a); \ BUG_ON(1); \ } while(0) - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h b/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h new file mode 100644 index 000000000000..cc132eaa10cc --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h @@ -0,0 +1,20 @@ +#ifndef __NVKM_RAMHT_H__ +#define __NVKM_RAMHT_H__ +#include <core/gpuobj.h> + +struct nvkm_ramht { + struct nvkm_gpuobj gpuobj; + int bits; +}; + +int nvkm_ramht_insert(struct nvkm_ramht *, int chid, u32 handle, u32 context); +void nvkm_ramht_remove(struct nvkm_ramht *, int cookie); +int nvkm_ramht_new(struct nvkm_object *, struct nvkm_object *, u32 size, + u32 align, struct nvkm_ramht **); + +static inline void +nvkm_ramht_ref(struct nvkm_ramht *obj, struct nvkm_ramht **ref) +{ + nvkm_gpuobj_ref(&obj->gpuobj, (struct nvkm_gpuobj **)ref); +} +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/core/subdev.h b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h index e9632e931616..6fdc39116aac 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/subdev.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h @@ -1,23 +1,23 @@ -#ifndef __NOUVEAU_SUBDEV_H__ -#define __NOUVEAU_SUBDEV_H__ - +#ifndef __NVKM_SUBDEV_H__ +#define __NVKM_SUBDEV_H__ #include <core/object.h> +#include <core/devidx.h> #define NV_SUBDEV_(sub,var) (NV_SUBDEV_CLASS | ((var) << 8) | (sub)) #define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var)) -struct nouveau_subdev { - struct nouveau_object base; +struct nvkm_subdev { + struct nvkm_object object; struct mutex mutex; const char *name; void __iomem *mmio; u32 debug; u32 unit; - void (*intr)(struct nouveau_subdev *); + void (*intr)(struct nvkm_subdev *); }; -static inline struct nouveau_subdev * +static inline struct nvkm_subdev * nv_subdev(void *obj) { #if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA @@ -28,27 +28,29 @@ nv_subdev(void *obj) } static inline int -nv_subidx(struct nouveau_object *object) +nv_subidx(struct nvkm_subdev *subdev) { - return nv_hclass(nv_subdev(object)) & 0xff; + return nv_hclass(subdev) & 0xff; } -#define nouveau_subdev_create(p,e,o,v,s,f,d) \ - nouveau_subdev_create_((p), (e), (o), (v), (s), (f), \ +struct nvkm_subdev *nvkm_subdev(void *obj, int idx); + +#define nvkm_subdev_create(p,e,o,v,s,f,d) \ + nvkm_subdev_create_((p), (e), (o), (v), (s), (f), \ sizeof(**d),(void **)d) -int nouveau_subdev_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, u32 pclass, +int nvkm_subdev_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, u32 pclass, const char *sname, const char *fname, int size, void **); -void nouveau_subdev_destroy(struct nouveau_subdev *); -int nouveau_subdev_init(struct nouveau_subdev *); -int nouveau_subdev_fini(struct nouveau_subdev *, bool suspend); -void nouveau_subdev_reset(struct nouveau_object *); +void nvkm_subdev_destroy(struct nvkm_subdev *); +int nvkm_subdev_init(struct nvkm_subdev *); +int nvkm_subdev_fini(struct nvkm_subdev *, bool suspend); +void nvkm_subdev_reset(struct nvkm_object *); -void _nouveau_subdev_dtor(struct nouveau_object *); -int _nouveau_subdev_init(struct nouveau_object *); -int _nouveau_subdev_fini(struct nouveau_object *, bool suspend); +void _nvkm_subdev_dtor(struct nvkm_object *); +int _nvkm_subdev_init(struct nvkm_object *); +int _nvkm_subdev_fini(struct nvkm_object *, bool suspend); #define s_printk(s,l,f,a...) do { \ if ((s)->debug >= OS_DBG_##l) { \ @@ -59,7 +61,7 @@ int _nouveau_subdev_fini(struct nouveau_object *, bool suspend); static inline u8 nv_rd08(void *obj, u32 addr) { - struct nouveau_subdev *subdev = nv_subdev(obj); + struct nvkm_subdev *subdev = nv_subdev(obj); u8 data = ioread8(subdev->mmio + addr); nv_spam(subdev, "nv_rd08 0x%06x 0x%02x\n", addr, data); return data; @@ -68,7 +70,7 @@ nv_rd08(void *obj, u32 addr) static inline u16 nv_rd16(void *obj, u32 addr) { - struct nouveau_subdev *subdev = nv_subdev(obj); + struct nvkm_subdev *subdev = nv_subdev(obj); u16 data = ioread16_native(subdev->mmio + addr); nv_spam(subdev, "nv_rd16 0x%06x 0x%04x\n", addr, data); return data; @@ -77,7 +79,7 @@ nv_rd16(void *obj, u32 addr) static inline u32 nv_rd32(void *obj, u32 addr) { - struct nouveau_subdev *subdev = nv_subdev(obj); + struct nvkm_subdev *subdev = nv_subdev(obj); u32 data = ioread32_native(subdev->mmio + addr); nv_spam(subdev, "nv_rd32 0x%06x 0x%08x\n", addr, data); return data; @@ -86,7 +88,7 @@ nv_rd32(void *obj, u32 addr) static inline void nv_wr08(void *obj, u32 addr, u8 data) { - struct nouveau_subdev *subdev = nv_subdev(obj); + struct nvkm_subdev *subdev = nv_subdev(obj); nv_spam(subdev, "nv_wr08 0x%06x 0x%02x\n", addr, data); iowrite8(data, subdev->mmio + addr); } @@ -94,7 +96,7 @@ nv_wr08(void *obj, u32 addr, u8 data) static inline void nv_wr16(void *obj, u32 addr, u16 data) { - struct nouveau_subdev *subdev = nv_subdev(obj); + struct nvkm_subdev *subdev = nv_subdev(obj); nv_spam(subdev, "nv_wr16 0x%06x 0x%04x\n", addr, data); iowrite16_native(data, subdev->mmio + addr); } @@ -102,7 +104,7 @@ nv_wr16(void *obj, u32 addr, u16 data) static inline void nv_wr32(void *obj, u32 addr, u32 data) { - struct nouveau_subdev *subdev = nv_subdev(obj); + struct nvkm_subdev *subdev = nv_subdev(obj); nv_spam(subdev, "nv_wr32 0x%06x 0x%08x\n", addr, data); iowrite32_native(data, subdev->mmio + addr); } @@ -114,5 +116,4 @@ nv_mask(void *obj, u32 addr, u32 mask, u32 data) nv_wr32(obj, addr, (temp & ~mask) | data); return temp; } - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h new file mode 100644 index 000000000000..e489beef2b92 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h @@ -0,0 +1,5 @@ +#ifndef __NVKM_BSP_H__ +#define __NVKM_BSP_H__ +#include <core/engine.h> +extern struct nvkm_oclass g84_bsp_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h new file mode 100644 index 000000000000..7e29c52617ea --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h @@ -0,0 +1,13 @@ +#ifndef __NVKM_CE_H__ +#define __NVKM_CE_H__ +#include <core/engine.h> + +void gt215_ce_intr(struct nvkm_subdev *); + +extern struct nvkm_oclass gt215_ce_oclass; +extern struct nvkm_oclass gf100_ce0_oclass; +extern struct nvkm_oclass gf100_ce1_oclass; +extern struct nvkm_oclass gk104_ce0_oclass; +extern struct nvkm_oclass gk104_ce1_oclass; +extern struct nvkm_oclass gk104_ce2_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h new file mode 100644 index 000000000000..57c29e91bad5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h @@ -0,0 +1,5 @@ +#ifndef __NVKM_CIPHER_H__ +#define __NVKM_CIPHER_H__ +#include <core/engine.h> +extern struct nvkm_oclass g84_cipher_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/engine/device.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/device.h index 672d3c8f4145..5d4805e67e76 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/device.h @@ -27,7 +27,4 @@ int nv50_identify(struct nouveau_device *); int nvc0_identify(struct nouveau_device *); int nve0_identify(struct nouveau_device *); int gm100_identify(struct nouveau_device *); - -struct nouveau_device *nouveau_device_find(u64 name); - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h new file mode 100644 index 000000000000..a5e1ed81312f --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h @@ -0,0 +1,32 @@ +#ifndef __NVKM_DISP_H__ +#define __NVKM_DISP_H__ +#include <core/engine.h> +#include <core/event.h> + +struct nvkm_disp { + struct nvkm_engine base; + + struct list_head outp; + + struct nvkm_event hpd; + struct nvkm_event vblank; +}; + +static inline struct nvkm_disp * +nvkm_disp(void *obj) +{ + return (void *)nvkm_engine(obj, NVDEV_ENGINE_DISP); +} + +extern struct nvkm_oclass *nv04_disp_oclass; +extern struct nvkm_oclass *nv50_disp_oclass; +extern struct nvkm_oclass *g84_disp_oclass; +extern struct nvkm_oclass *gt200_disp_oclass; +extern struct nvkm_oclass *g94_disp_oclass; +extern struct nvkm_oclass *gt215_disp_oclass; +extern struct nvkm_oclass *gf110_disp_oclass; +extern struct nvkm_oclass *gk104_disp_oclass; +extern struct nvkm_oclass *gk110_disp_oclass; +extern struct nvkm_oclass *gm107_disp_oclass; +extern struct nvkm_oclass *gm204_disp_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h new file mode 100644 index 000000000000..c4fce8afcf83 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h @@ -0,0 +1,26 @@ +#ifndef __NVKM_DMAOBJ_H__ +#define __NVKM_DMAOBJ_H__ +#include <core/engine.h> +struct nvkm_gpuobj; + +struct nvkm_dmaobj { + struct nvkm_object base; + u32 target; + u32 access; + u64 start; + u64 limit; +}; + +struct nvkm_dmaeng { + struct nvkm_engine base; + + /* creates a "physical" dma object from a struct nvkm_dmaobj */ + int (*bind)(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent, + struct nvkm_gpuobj **); +}; + +extern struct nvkm_oclass *nv04_dmaeng_oclass; +extern struct nvkm_oclass *nv50_dmaeng_oclass; +extern struct nvkm_oclass *gf100_dmaeng_oclass; +extern struct nvkm_oclass *gf110_dmaeng_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h new file mode 100644 index 000000000000..bd38cf9130fc --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h @@ -0,0 +1,81 @@ +#ifndef __NVKM_FALCON_H__ +#define __NVKM_FALCON_H__ +#include <core/engctx.h> + +struct nvkm_falcon_chan { + struct nvkm_engctx base; +}; + +#define nvkm_falcon_context_create(p,e,c,g,s,a,f,d) \ + nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) +#define nvkm_falcon_context_destroy(d) \ + nvkm_engctx_destroy(&(d)->base) +#define nvkm_falcon_context_init(d) \ + nvkm_engctx_init(&(d)->base) +#define nvkm_falcon_context_fini(d,s) \ + nvkm_engctx_fini(&(d)->base, (s)) + +#define _nvkm_falcon_context_ctor _nvkm_engctx_ctor +#define _nvkm_falcon_context_dtor _nvkm_engctx_dtor +#define _nvkm_falcon_context_init _nvkm_engctx_init +#define _nvkm_falcon_context_fini _nvkm_engctx_fini +#define _nvkm_falcon_context_rd32 _nvkm_engctx_rd32 +#define _nvkm_falcon_context_wr32 _nvkm_engctx_wr32 + +struct nvkm_falcon_data { + bool external; +}; + +#include <core/engine.h> + +struct nvkm_falcon { + struct nvkm_engine base; + + u32 addr; + u8 version; + u8 secret; + + struct nvkm_gpuobj *core; + bool external; + + struct { + u32 limit; + u32 *data; + u32 size; + } code; + + struct { + u32 limit; + u32 *data; + u32 size; + } data; +}; + +#define nv_falcon(priv) (&(priv)->base) + +#define nvkm_falcon_create(p,e,c,b,d,i,f,r) \ + nvkm_falcon_create_((p), (e), (c), (b), (d), (i), (f), \ + sizeof(**r),(void **)r) +#define nvkm_falcon_destroy(p) \ + nvkm_engine_destroy(&(p)->base) +#define nvkm_falcon_init(p) ({ \ + struct nvkm_falcon *falcon = (p); \ + _nvkm_falcon_init(nv_object(falcon)); \ +}) +#define nvkm_falcon_fini(p,s) ({ \ + struct nvkm_falcon *falcon = (p); \ + _nvkm_falcon_fini(nv_object(falcon), (s)); \ +}) + +int nvkm_falcon_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, u32, bool, const char *, + const char *, int, void **); + +void nvkm_falcon_intr(struct nvkm_subdev *subdev); + +#define _nvkm_falcon_dtor _nvkm_engine_dtor +int _nvkm_falcon_init(struct nvkm_object *); +int _nvkm_falcon_fini(struct nvkm_object *, bool); +u32 _nvkm_falcon_rd32(struct nvkm_object *, u64); +void _nvkm_falcon_wr32(struct nvkm_object *, u64, u32); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h new file mode 100644 index 000000000000..05321ce7ab15 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -0,0 +1,126 @@ +#ifndef __NVKM_FIFO_H__ +#define __NVKM_FIFO_H__ +#include <core/namedb.h> + +struct nvkm_fifo_chan { + struct nvkm_namedb namedb; + struct nvkm_dmaobj *pushdma; + struct nvkm_gpuobj *pushgpu; + void __iomem *user; + u64 addr; + u32 size; + u16 chid; + atomic_t refcnt; /* NV04_NVSW_SET_REF */ +}; + +static inline struct nvkm_fifo_chan * +nvkm_fifo_chan(void *obj) +{ + return (void *)nv_namedb(obj); +} + +#define nvkm_fifo_channel_create(p,e,c,b,a,s,n,m,d) \ + nvkm_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \ + (m), sizeof(**d), (void **)d) +#define nvkm_fifo_channel_init(p) \ + nvkm_namedb_init(&(p)->namedb) +#define nvkm_fifo_channel_fini(p,s) \ + nvkm_namedb_fini(&(p)->namedb, (s)) + +int nvkm_fifo_channel_create_(struct nvkm_object *, + struct nvkm_object *, + struct nvkm_oclass *, + int bar, u32 addr, u32 size, u32 push, + u64 engmask, int len, void **); +void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *); + +#define _nvkm_fifo_channel_init _nvkm_namedb_init +#define _nvkm_fifo_channel_fini _nvkm_namedb_fini + +void _nvkm_fifo_channel_dtor(struct nvkm_object *); +int _nvkm_fifo_channel_map(struct nvkm_object *, u64 *, u32 *); +u32 _nvkm_fifo_channel_rd32(struct nvkm_object *, u64); +void _nvkm_fifo_channel_wr32(struct nvkm_object *, u64, u32); +int _nvkm_fifo_channel_ntfy(struct nvkm_object *, u32, struct nvkm_event **); + +#include <core/gpuobj.h> + +struct nvkm_fifo_base { + struct nvkm_gpuobj gpuobj; +}; + +#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d) \ + nvkm_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d)) +#define nvkm_fifo_context_destroy(p) \ + nvkm_gpuobj_destroy(&(p)->gpuobj) +#define nvkm_fifo_context_init(p) \ + nvkm_gpuobj_init(&(p)->gpuobj) +#define nvkm_fifo_context_fini(p,s) \ + nvkm_gpuobj_fini(&(p)->gpuobj, (s)) + +#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor +#define _nvkm_fifo_context_init _nvkm_gpuobj_init +#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini +#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32 +#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32 + +#include <core/engine.h> +#include <core/event.h> + +struct nvkm_fifo { + struct nvkm_engine base; + + struct nvkm_event cevent; /* channel creation event */ + struct nvkm_event uevent; /* async user trigger */ + + struct nvkm_object **channel; + spinlock_t lock; + u16 min; + u16 max; + + int (*chid)(struct nvkm_fifo *, struct nvkm_object *); + void (*pause)(struct nvkm_fifo *, unsigned long *); + void (*start)(struct nvkm_fifo *, unsigned long *); +}; + +static inline struct nvkm_fifo * +nvkm_fifo(void *obj) +{ + return (void *)nvkm_engine(obj, NVDEV_ENGINE_FIFO); +} + +#define nvkm_fifo_create(o,e,c,fc,lc,d) \ + nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d) +#define nvkm_fifo_init(p) \ + nvkm_engine_init(&(p)->base) +#define nvkm_fifo_fini(p,s) \ + nvkm_engine_fini(&(p)->base, (s)) + +int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int min, int max, + int size, void **); +void nvkm_fifo_destroy(struct nvkm_fifo *); +const char * +nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid); + +#define _nvkm_fifo_init _nvkm_engine_init +#define _nvkm_fifo_fini _nvkm_engine_fini + +extern struct nvkm_oclass *nv04_fifo_oclass; +extern struct nvkm_oclass *nv10_fifo_oclass; +extern struct nvkm_oclass *nv17_fifo_oclass; +extern struct nvkm_oclass *nv40_fifo_oclass; +extern struct nvkm_oclass *nv50_fifo_oclass; +extern struct nvkm_oclass *g84_fifo_oclass; +extern struct nvkm_oclass *gf100_fifo_oclass; +extern struct nvkm_oclass *gk104_fifo_oclass; +extern struct nvkm_oclass *gk20a_fifo_oclass; +extern struct nvkm_oclass *gk208_fifo_oclass; + +int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32, + struct nvkm_notify *); +void nvkm_fifo_uevent(struct nvkm_fifo *); + +void nv04_fifo_intr(struct nvkm_subdev *); +int nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h new file mode 100644 index 000000000000..93ef1f2bfac4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h @@ -0,0 +1,86 @@ +#ifndef __NVKM_GR_H__ +#define __NVKM_GR_H__ +#include <core/engctx.h> + +struct nvkm_gr_chan { + struct nvkm_engctx base; +}; + +#define nvkm_gr_context_create(p,e,c,g,s,a,f,d) \ + nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) +#define nvkm_gr_context_destroy(d) \ + nvkm_engctx_destroy(&(d)->base) +#define nvkm_gr_context_init(d) \ + nvkm_engctx_init(&(d)->base) +#define nvkm_gr_context_fini(d,s) \ + nvkm_engctx_fini(&(d)->base, (s)) + +#define _nvkm_gr_context_dtor _nvkm_engctx_dtor +#define _nvkm_gr_context_init _nvkm_engctx_init +#define _nvkm_gr_context_fini _nvkm_engctx_fini +#define _nvkm_gr_context_rd32 _nvkm_engctx_rd32 +#define _nvkm_gr_context_wr32 _nvkm_engctx_wr32 + +#include <core/engine.h> + +struct nvkm_gr { + struct nvkm_engine base; + + /* Returns chipset-specific counts of units packed into an u64. + */ + u64 (*units)(struct nvkm_gr *); +}; + +static inline struct nvkm_gr * +nvkm_gr(void *obj) +{ + return (void *)nvkm_engine(obj, NVDEV_ENGINE_GR); +} + +#define nvkm_gr_create(p,e,c,y,d) \ + nvkm_engine_create((p), (e), (c), (y), "PGR", "graphics", (d)) +#define nvkm_gr_destroy(d) \ + nvkm_engine_destroy(&(d)->base) +#define nvkm_gr_init(d) \ + nvkm_engine_init(&(d)->base) +#define nvkm_gr_fini(d,s) \ + nvkm_engine_fini(&(d)->base, (s)) + +#define _nvkm_gr_dtor _nvkm_engine_dtor +#define _nvkm_gr_init _nvkm_engine_init +#define _nvkm_gr_fini _nvkm_engine_fini + +extern struct nvkm_oclass nv04_gr_oclass; +extern struct nvkm_oclass nv10_gr_oclass; +extern struct nvkm_oclass nv20_gr_oclass; +extern struct nvkm_oclass nv25_gr_oclass; +extern struct nvkm_oclass nv2a_gr_oclass; +extern struct nvkm_oclass nv30_gr_oclass; +extern struct nvkm_oclass nv34_gr_oclass; +extern struct nvkm_oclass nv35_gr_oclass; +extern struct nvkm_oclass nv40_gr_oclass; +extern struct nvkm_oclass nv50_gr_oclass; +extern struct nvkm_oclass *gf100_gr_oclass; +extern struct nvkm_oclass *gf108_gr_oclass; +extern struct nvkm_oclass *gf104_gr_oclass; +extern struct nvkm_oclass *gf110_gr_oclass; +extern struct nvkm_oclass *gf117_gr_oclass; +extern struct nvkm_oclass *gf119_gr_oclass; +extern struct nvkm_oclass *gk104_gr_oclass; +extern struct nvkm_oclass *gk20a_gr_oclass; +extern struct nvkm_oclass *gk110_gr_oclass; +extern struct nvkm_oclass *gk110b_gr_oclass; +extern struct nvkm_oclass *gk208_gr_oclass; +extern struct nvkm_oclass *gm107_gr_oclass; + +#include <core/enum.h> + +extern const struct nvkm_bitfield nv04_gr_nsource[]; +extern struct nvkm_ofuncs nv04_gr_ofuncs; +bool nv04_gr_idle(void *obj); + +extern const struct nvkm_bitfield nv10_gr_intr_name[]; +extern const struct nvkm_bitfield nv10_gr_nstatus[]; + +extern const struct nvkm_enum nv50_data_error_names[]; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h new file mode 100644 index 000000000000..4e500b398064 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h @@ -0,0 +1,62 @@ +#ifndef __NVKM_MPEG_H__ +#define __NVKM_MPEG_H__ +#include <core/engctx.h> + +struct nvkm_mpeg_chan { + struct nvkm_engctx base; +}; + +#define nvkm_mpeg_context_create(p,e,c,g,s,a,f,d) \ + nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) +#define nvkm_mpeg_context_destroy(d) \ + nvkm_engctx_destroy(&(d)->base) +#define nvkm_mpeg_context_init(d) \ + nvkm_engctx_init(&(d)->base) +#define nvkm_mpeg_context_fini(d,s) \ + nvkm_engctx_fini(&(d)->base, (s)) + +#define _nvkm_mpeg_context_dtor _nvkm_engctx_dtor +#define _nvkm_mpeg_context_init _nvkm_engctx_init +#define _nvkm_mpeg_context_fini _nvkm_engctx_fini +#define _nvkm_mpeg_context_rd32 _nvkm_engctx_rd32 +#define _nvkm_mpeg_context_wr32 _nvkm_engctx_wr32 + +#include <core/engine.h> + +struct nvkm_mpeg { + struct nvkm_engine base; +}; + +#define nvkm_mpeg_create(p,e,c,d) \ + nvkm_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d)) +#define nvkm_mpeg_destroy(d) \ + nvkm_engine_destroy(&(d)->base) +#define nvkm_mpeg_init(d) \ + nvkm_engine_init(&(d)->base) +#define nvkm_mpeg_fini(d,s) \ + nvkm_engine_fini(&(d)->base, (s)) + +#define _nvkm_mpeg_dtor _nvkm_engine_dtor +#define _nvkm_mpeg_init _nvkm_engine_init +#define _nvkm_mpeg_fini _nvkm_engine_fini + +extern struct nvkm_oclass nv31_mpeg_oclass; +extern struct nvkm_oclass nv40_mpeg_oclass; +extern struct nvkm_oclass nv44_mpeg_oclass; +extern struct nvkm_oclass nv50_mpeg_oclass; +extern struct nvkm_oclass g84_mpeg_oclass; +extern struct nvkm_ofuncs nv31_mpeg_ofuncs; +extern struct nvkm_oclass nv31_mpeg_cclass; +extern struct nvkm_oclass nv31_mpeg_sclass[]; +extern struct nvkm_oclass nv40_mpeg_sclass[]; +void nv31_mpeg_intr(struct nvkm_subdev *); +void nv31_mpeg_tile_prog(struct nvkm_engine *, int); +int nv31_mpeg_init(struct nvkm_object *); + +extern struct nvkm_ofuncs nv50_mpeg_ofuncs; +int nv50_mpeg_context_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nv50_mpeg_intr(struct nvkm_subdev *); +int nv50_mpeg_init(struct nvkm_object *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h new file mode 100644 index 000000000000..54b7672eed9c --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h @@ -0,0 +1,7 @@ +#ifndef __NVKM_MSPDEC_H__ +#define __NVKM_MSPDEC_H__ +#include <core/engine.h> +extern struct nvkm_oclass g98_mspdec_oclass; +extern struct nvkm_oclass gf100_mspdec_oclass; +extern struct nvkm_oclass gk104_mspdec_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h new file mode 100644 index 000000000000..c6c69d0a8d01 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h @@ -0,0 +1,6 @@ +#ifndef __NVKM_MSPPP_H__ +#define __NVKM_MSPPP_H__ +#include <core/engine.h> +extern struct nvkm_oclass g98_msppp_oclass; +extern struct nvkm_oclass gf100_msppp_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h new file mode 100644 index 000000000000..1f193b7bd6c5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h @@ -0,0 +1,7 @@ +#ifndef __NVKM_MSVLD_H__ +#define __NVKM_MSVLD_H__ +#include <core/engine.h> +extern struct nvkm_oclass g98_msvld_oclass; +extern struct nvkm_oclass gf100_msvld_oclass; +extern struct nvkm_oclass gk104_msvld_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h new file mode 100644 index 000000000000..93181bbf0f63 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h @@ -0,0 +1,34 @@ +#ifndef __NVKM_PM_H__ +#define __NVKM_PM_H__ +#include <core/engine.h> + +struct nvkm_perfdom; +struct nvkm_perfctr; +struct nvkm_pm { + struct nvkm_engine base; + + struct nvkm_perfctx *context; + void *profile_data; + + struct list_head domains; + u32 sequence; + + /*XXX: temp for daemon backend */ + u32 pwr[8]; + u32 last; +}; + +static inline struct nvkm_pm * +nvkm_pm(void *obj) +{ + return (void *)nvkm_engine(obj, NVDEV_ENGINE_PM); +} + +extern struct nvkm_oclass *nv40_pm_oclass; +extern struct nvkm_oclass *nv50_pm_oclass; +extern struct nvkm_oclass *g84_pm_oclass; +extern struct nvkm_oclass *gt215_pm_oclass; +extern struct nvkm_oclass gf100_pm_oclass; +extern struct nvkm_oclass gk104_pm_oclass; +extern struct nvkm_oclass gk110_pm_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h new file mode 100644 index 000000000000..44590a2a479d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h @@ -0,0 +1,5 @@ +#ifndef __NVKM_SEC_H__ +#define __NVKM_SEC_H__ +#include <core/engine.h> +extern struct nvkm_oclass g98_sec_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h new file mode 100644 index 000000000000..a529013c92ab --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h @@ -0,0 +1,50 @@ +#ifndef __NVKM_SW_H__ +#define __NVKM_SW_H__ +#include <core/engctx.h> + +struct nvkm_sw_chan { + struct nvkm_engctx base; + + int (*flip)(void *); + void *flip_data; +}; + +#define nvkm_sw_context_create(p,e,c,d) \ + nvkm_engctx_create((p), (e), (c), (p), 0, 0, 0, (d)) +#define nvkm_sw_context_destroy(d) \ + nvkm_engctx_destroy(&(d)->base) +#define nvkm_sw_context_init(d) \ + nvkm_engctx_init(&(d)->base) +#define nvkm_sw_context_fini(d,s) \ + nvkm_engctx_fini(&(d)->base, (s)) + +#define _nvkm_sw_context_dtor _nvkm_engctx_dtor +#define _nvkm_sw_context_init _nvkm_engctx_init +#define _nvkm_sw_context_fini _nvkm_engctx_fini + +#include <core/engine.h> + +struct nvkm_sw { + struct nvkm_engine base; +}; + +#define nvkm_sw_create(p,e,c,d) \ + nvkm_engine_create((p), (e), (c), true, "SW", "software", (d)) +#define nvkm_sw_destroy(d) \ + nvkm_engine_destroy(&(d)->base) +#define nvkm_sw_init(d) \ + nvkm_engine_init(&(d)->base) +#define nvkm_sw_fini(d,s) \ + nvkm_engine_fini(&(d)->base, (s)) + +#define _nvkm_sw_dtor _nvkm_engine_dtor +#define _nvkm_sw_init _nvkm_engine_init +#define _nvkm_sw_fini _nvkm_engine_fini + +extern struct nvkm_oclass *nv04_sw_oclass; +extern struct nvkm_oclass *nv10_sw_oclass; +extern struct nvkm_oclass *nv50_sw_oclass; +extern struct nvkm_oclass *gf100_sw_oclass; + +void nv04_sw_intr(struct nvkm_subdev *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h new file mode 100644 index 000000000000..7851f18c5add --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h @@ -0,0 +1,5 @@ +#ifndef __NVKM_VP_H__ +#define __NVKM_VP_H__ +#include <core/engine.h> +extern struct nvkm_oclass g84_vp_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h new file mode 100644 index 000000000000..7a216cca2865 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h @@ -0,0 +1,35 @@ +#ifndef __NVKM_XTENSA_H__ +#define __NVKM_XTENSA_H__ +#include <core/engine.h> +struct nvkm_gpuobj; + +struct nvkm_xtensa { + struct nvkm_engine base; + + u32 addr; + struct nvkm_gpuobj *gpu_fw; + u32 fifo_val; + u32 unkd28; +}; + +#define nvkm_xtensa_create(p,e,c,b,d,i,f,r) \ + nvkm_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \ + sizeof(**r),(void **)r) + +int _nvkm_xtensa_engctx_ctor(struct nvkm_object *, + struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); + +void _nvkm_xtensa_intr(struct nvkm_subdev *); +int nvkm_xtensa_create_(struct nvkm_object *, + struct nvkm_object *, + struct nvkm_oclass *, u32, bool, + const char *, const char *, + int, void **); +#define _nvkm_xtensa_dtor _nvkm_engine_dtor +int _nvkm_xtensa_init(struct nvkm_object *); +int _nvkm_xtensa_fini(struct nvkm_object *, bool); +u32 _nvkm_xtensa_rd32(struct nvkm_object *, u64); +void _nvkm_xtensa_wr32(struct nvkm_object *, u64, u32); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h new file mode 100644 index 000000000000..c7a007b8bc10 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h @@ -0,0 +1,33 @@ +#ifndef __NVKM_BAR_H__ +#define __NVKM_BAR_H__ +#include <core/subdev.h> +struct nvkm_mem; +struct nvkm_vma; + +struct nvkm_bar { + struct nvkm_subdev base; + + int (*alloc)(struct nvkm_bar *, struct nvkm_object *, + struct nvkm_mem *, struct nvkm_object **); + + int (*kmap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags, + struct nvkm_vma *); + int (*umap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags, + struct nvkm_vma *); + void (*unmap)(struct nvkm_bar *, struct nvkm_vma *); + void (*flush)(struct nvkm_bar *); + + /* whether the BAR supports to be ioremapped WC or should be uncached */ + bool iomap_uncached; +}; + +static inline struct nvkm_bar * +nvkm_bar(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BAR); +} + +extern struct nvkm_oclass nv50_bar_oclass; +extern struct nvkm_oclass gf100_bar_oclass; +extern struct nvkm_oclass gk20a_bar_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h new file mode 100644 index 000000000000..cef287e0bbf2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h @@ -0,0 +1,32 @@ +#ifndef __NVKM_BIOS_H__ +#define __NVKM_BIOS_H__ +#include <core/subdev.h> + +struct nvkm_bios { + struct nvkm_subdev base; + u32 size; + u8 *data; + + u32 bmp_offset; + u32 bit_offset; + + struct { + u8 major; + u8 chip; + u8 minor; + u8 micro; + u8 patch; + } version; +}; + +static inline struct nvkm_bios * +nvkm_bios(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_VBIOS); +} + +u8 nvbios_checksum(const u8 *data, int size); +u16 nvbios_findstr(const u8 *data, int size, const char *str, int len); + +extern struct nvkm_oclass nvkm_bios_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0203.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h index 1f84d3612dd8..cf202c793a1d 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0203.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h @@ -1,14 +1,13 @@ #ifndef __NVBIOS_M0203_H__ #define __NVBIOS_M0203_H__ - struct nvbios_M0203T { #define M0203T_TYPE_RAMCFG 0x00 u8 type; u16 pointer; }; -u32 nvbios_M0203Te(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u32 nvbios_M0203Tp(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +u32 nvbios_M0203Te(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_M0203Tp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0203T *); struct nvbios_M0203E { @@ -22,10 +21,9 @@ struct nvbios_M0203E { u8 group; }; -u32 nvbios_M0203Ee(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); -u32 nvbios_M0203Ep(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, +u32 nvbios_M0203Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_M0203Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, struct nvbios_M0203E *); -u32 nvbios_M0203Em(struct nouveau_bios *, u8 ramcfg, u8 *ver, u8 *hdr, +u32 nvbios_M0203Em(struct nvkm_bios *, u8 ramcfg, u8 *ver, u8 *hdr, struct nvbios_M0203E *); - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h new file mode 100644 index 000000000000..d34608ff241e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h @@ -0,0 +1,29 @@ +#ifndef __NVBIOS_M0205_H__ +#define __NVBIOS_M0205_H__ +struct nvbios_M0205T { + u16 freq; +}; + +u32 nvbios_M0205Te(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); +u32 nvbios_M0205Tp(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz, + struct nvbios_M0205T *); + +struct nvbios_M0205E { + u8 type; +}; + +u32 nvbios_M0205Ee(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_M0205Ep(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0205E *); + +struct nvbios_M0205S { + u8 data; +}; + +u32 nvbios_M0205Se(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr); +u32 nvbios_M0205Sp(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr, + struct nvbios_M0205S *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h new file mode 100644 index 000000000000..c7ff8d9526e7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h @@ -0,0 +1,27 @@ +#ifndef __NVBIOS_M0209_H__ +#define __NVBIOS_M0209_H__ +u32 nvbios_M0209Te(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); + +struct nvbios_M0209E { + u8 v00_40; + u8 bits; + u8 modulo; + u8 v02_40; + u8 v02_07; + u8 v03; +}; + +u32 nvbios_M0209Ee(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_M0209Ep(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0209E *); + +struct nvbios_M0209S { + u32 data[0x200]; +}; + +u32 nvbios_M0209Se(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr); +u32 nvbios_M0209Sp(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr, + struct nvbios_M0209S *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h new file mode 100644 index 000000000000..1c1c52eac97d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h @@ -0,0 +1,21 @@ +#ifndef __NVBIOS_P0260_H__ +#define __NVBIOS_P0260_H__ +u32 nvbios_P0260Te(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz); + +struct nvbios_P0260E { + u32 data; +}; + +u32 nvbios_P0260Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_P0260Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_P0260E *); + +struct nvbios_P0260X { + u32 data; +}; + +u32 nvbios_P0260Xe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_P0260Xp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_P0260X *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h index 73f060b07981..6711732b7cb1 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h @@ -1,6 +1,5 @@ #ifndef __NVBIOS_BIT_H__ #define __NVBIOS_BIT_H__ - struct bit_entry { u8 id; u8 version; @@ -8,6 +7,5 @@ struct bit_entry { u16 offset; }; -int bit_entry(struct nouveau_bios *, u8 id, struct bit_entry *); - +int bit_entry(struct nvkm_bios *, u8 id, struct bit_entry *); #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h index 10e4dbca649a..4107aa546a21 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h @@ -1,8 +1,7 @@ #ifndef __NVBIOS_BMP_H__ #define __NVBIOS_BMP_H__ - static inline u16 -bmp_version(struct nouveau_bios *bios) +bmp_version(struct nvkm_bios *bios) { if (bios->bmp_offset) { return nv_ro08(bios, bios->bmp_offset + 5) << 8 | @@ -13,7 +12,7 @@ bmp_version(struct nouveau_bios *bios) } static inline u16 -bmp_mem_init_table(struct nouveau_bios *bios) +bmp_mem_init_table(struct nvkm_bios *bios) { if (bmp_version(bios) >= 0x0300) return nv_ro16(bios, bios->bmp_offset + 24); @@ -21,7 +20,7 @@ bmp_mem_init_table(struct nouveau_bios *bios) } static inline u16 -bmp_sdr_seq_table(struct nouveau_bios *bios) +bmp_sdr_seq_table(struct nvkm_bios *bios) { if (bmp_version(bios) >= 0x0300) return nv_ro16(bios, bios->bmp_offset + 26); @@ -29,11 +28,10 @@ bmp_sdr_seq_table(struct nouveau_bios *bios) } static inline u16 -bmp_ddr_seq_table(struct nouveau_bios *bios) +bmp_ddr_seq_table(struct nvkm_bios *bios) { if (bmp_version(bios) >= 0x0300) return nv_ro16(bios, bios->bmp_offset + 28); return 0x0000; } - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h new file mode 100644 index 000000000000..934b0ae5521d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h @@ -0,0 +1,27 @@ +#ifndef __NVBIOS_BOOST_H__ +#define __NVBIOS_BOOST_H__ +u16 nvbios_boostTe(struct nvkm_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *); + +struct nvbios_boostE { + u8 pstate; + u32 min; + u32 max; +}; + +u16 nvbios_boostEe(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *); +u16 nvbios_boostEp(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *, + struct nvbios_boostE *); +u16 nvbios_boostEm(struct nvkm_bios *, u8, u8 *, u8 *, u8 *, u8 *, + struct nvbios_boostE *); + +struct nvbios_boostS { + u8 domain; + u8 percent; + u32 min; + u32 max; +}; + +u16 nvbios_boostSe(struct nvkm_bios *, int, u16, u8 *, u8 *, u8, u8); +u16 nvbios_boostSp(struct nvkm_bios *, int, u16, u8 *, u8 *, u8, u8, + struct nvbios_boostS *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h index f3930c27cb7a..e8e77ee24776 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h @@ -1,6 +1,5 @@ #ifndef __NVBIOS_CONN_H__ #define __NVBIOS_CONN_H__ - enum dcb_connector_type { DCB_CONNECTOR_VGA = 0x00, DCB_CONNECTOR_TV_0 = 0x10, @@ -25,8 +24,8 @@ enum dcb_connector_type { struct nvbios_connT { }; -u32 nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u32 nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +u32 nvbios_connTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_connTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_connT *info); struct nvbios_connE { @@ -39,8 +38,7 @@ struct nvbios_connE { u8 lcdid; }; -u32 nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *hdr); -u32 nvbios_connEp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *hdr, +u32 nvbios_connEe(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr); +u32 nvbios_connEp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr, struct nvbios_connE *info); - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h new file mode 100644 index 000000000000..2f0e0c8e83be --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h @@ -0,0 +1,26 @@ +#ifndef __NVBIOS_CSTEP_H__ +#define __NVBIOS_CSTEP_H__ +u16 nvbios_cstepTe(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz); + +struct nvbios_cstepE { + u8 pstate; + u8 index; +}; + +u16 nvbios_cstepEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u16 nvbios_cstepEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_cstepE *); +u16 nvbios_cstepEm(struct nvkm_bios *, u8 pstate, u8 *ver, u8 *hdr, + struct nvbios_cstepE *); + +struct nvbios_cstepX { + u32 freq; + u8 unkn[2]; + u8 voltage; +}; + +u16 nvbios_cstepXe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u16 nvbios_cstepXp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, + struct nvbios_cstepX *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h index 123270e9813a..4892a65ddd48 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h @@ -1,8 +1,5 @@ #ifndef __NVBIOS_DCB_H__ #define __NVBIOS_DCB_H__ - -struct nouveau_bios; - enum dcb_output_type { DCB_OUTPUT_ANALOG = 0x0, DCB_OUTPUT_TV = 0x1, @@ -57,13 +54,12 @@ struct dcb_output { bool i2c_upper_default; }; -u16 dcb_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len); -u16 dcb_outp(struct nouveau_bios *, u8 idx, u8 *ver, u8 *len); -u16 dcb_outp_parse(struct nouveau_bios *, u8 idx, u8 *, u8 *, +u16 dcb_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len); +u16 dcb_outp(struct nvkm_bios *, u8 idx, u8 *ver, u8 *len); +u16 dcb_outp_parse(struct nvkm_bios *, u8 idx, u8 *, u8 *, struct dcb_output *); -u16 dcb_outp_match(struct nouveau_bios *, u16 type, u16 mask, u8 *, u8 *, +u16 dcb_outp_match(struct nvkm_bios *, u16 type, u16 mask, u8 *, u8 *, struct dcb_output *); -int dcb_outp_foreach(struct nouveau_bios *, void *data, int (*exec) - (struct nouveau_bios *, void *, int index, u16 entry)); - +int dcb_outp_foreach(struct nvkm_bios *, void *data, int (*exec) + (struct nvkm_bios *, void *, int index, u16 entry)); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h new file mode 100644 index 000000000000..db10c11f0595 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h @@ -0,0 +1,39 @@ +#ifndef __NVBIOS_DISP_H__ +#define __NVBIOS_DISP_H__ +u16 nvbios_disp_table(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub); + +struct nvbios_disp { + u16 data; +}; + +u16 nvbios_disp_entry(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *sub); +u16 nvbios_disp_parse(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *sub, + struct nvbios_disp *); + +struct nvbios_outp { + u16 type; + u16 mask; + u16 script[3]; +}; + +u16 nvbios_outp_entry(struct nvkm_bios *, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_outp_parse(struct nvkm_bios *, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *); +u16 nvbios_outp_match(struct nvkm_bios *, u16 type, u16 mask, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *); + +struct nvbios_ocfg { + u16 match; + u16 clkcmp[2]; +}; + +u16 nvbios_ocfg_entry(struct nvkm_bios *, u16 outp, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_ocfg_parse(struct nvkm_bios *, u16 outp, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *); +u16 nvbios_ocfg_match(struct nvkm_bios *, u16 outp, u16 type, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *); +u16 nvbios_oclk_match(struct nvkm_bios *, u16 cmp, u32 khz); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h new file mode 100644 index 000000000000..b4d39df70d4e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h @@ -0,0 +1,31 @@ +#ifndef __NVBIOS_DP_H__ +#define __NVBIOS_DP_H__ +struct nvbios_dpout { + u16 type; + u16 mask; + u8 flags; + u32 script[5]; + u32 lnkcmp; +}; + +u16 nvbios_dpout_parse(struct nvkm_bios *, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_dpout *); +u16 nvbios_dpout_match(struct nvkm_bios *, u16 type, u16 mask, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_dpout *); + +struct nvbios_dpcfg { + u8 pc; + u8 dc; + u8 pe; + u8 tx_pu; +}; + +u16 +nvbios_dpcfg_parse(struct nvkm_bios *, u16 outp, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *); +u16 +nvbios_dpcfg_match(struct nvkm_bios *, u16 outp, u8 pc, u8 vs, u8 pe, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h index 949fee3af8fb..6d3bedc633b3 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h @@ -1,8 +1,5 @@ #ifndef __NVBIOS_EXTDEV_H__ #define __NVBIOS_EXTDEV_H__ - -struct nouveau_bios; - enum nvbios_extdev_type { NVBIOS_EXTDEV_LM89 = 0x02, NVBIOS_EXTDEV_VT1103M = 0x40, @@ -20,11 +17,9 @@ struct nvbios_extdev_func { }; int -nvbios_extdev_parse(struct nouveau_bios *, int, struct nvbios_extdev_func *); +nvbios_extdev_parse(struct nvkm_bios *, int, struct nvbios_extdev_func *); int -nvbios_extdev_find(struct nouveau_bios *, enum nvbios_extdev_type, +nvbios_extdev_find(struct nvkm_bios *, enum nvbios_extdev_type, struct nvbios_extdev_func *); - - #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h index 119d0874e041..693ea7d9ec43 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h @@ -1,8 +1,6 @@ #ifndef __NVBIOS_FAN_H__ #define __NVBIOS_FAN_H__ - #include <subdev/bios/therm.h> -u16 nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan); - +u16 nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan); #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h index c7b2e586be0b..33be260ddd38 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h @@ -1,6 +1,5 @@ #ifndef __NVBIOS_GPIO_H__ #define __NVBIOS_GPIO_H__ - enum dcb_gpio_func_name { DCB_GPIO_PANEL_POWER = 0x01, DCB_GPIO_TVDAC0 = 0x0c, @@ -38,11 +37,10 @@ struct dcb_gpio_func { u8 param; }; -u16 dcb_gpio_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 dcb_gpio_entry(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len); -u16 dcb_gpio_parse(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len, +u16 dcb_gpio_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 dcb_gpio_entry(struct nvkm_bios *, int idx, int ent, u8 *ver, u8 *len); +u16 dcb_gpio_parse(struct nvkm_bios *, int idx, int ent, u8 *ver, u8 *len, struct dcb_gpio_func *); -u16 dcb_gpio_match(struct nouveau_bios *, int idx, u8 func, u8 line, +u16 dcb_gpio_match(struct nvkm_bios *, int idx, u8 func, u8 line, u8 *ver, u8 *len, struct dcb_gpio_func *); - #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h index c9bb112895af..85c529ecf9b1 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h @@ -1,8 +1,5 @@ #ifndef __NVBIOS_I2C_H__ #define __NVBIOS_I2C_H__ - -struct nouveau_bios; - enum dcb_i2c_type { /* matches bios type field prior to ccb 4.1 */ DCB_I2C_NV04_BIT = 0x00, @@ -22,8 +19,7 @@ struct dcb_i2c_entry { u8 auxch; }; -u16 dcb_i2c_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 dcb_i2c_entry(struct nouveau_bios *, u8 index, u8 *ver, u8 *len); -int dcb_i2c_parse(struct nouveau_bios *, u8 index, struct dcb_i2c_entry *); - +u16 dcb_i2c_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 dcb_i2c_entry(struct nvkm_bios *, u8 index, u8 *ver, u8 *len); +int dcb_i2c_parse(struct nvkm_bios *, u8 index, struct dcb_i2c_entry *); #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/image.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h index 3348b4580843..e15d63b9a5eb 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/image.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h @@ -1,6 +1,5 @@ #ifndef __NVBIOS_IMAGE_H__ #define __NVBIOS_IMAGE_H__ - struct nvbios_image { u32 base; u32 size; @@ -8,6 +7,5 @@ struct nvbios_image { bool last; }; -bool nvbios_image(struct nouveau_bios *, int, struct nvbios_image *); - +bool nvbios_image(struct nvkm_bios *, int, struct nvbios_image *); #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h index ca2f6bf37f46..578a667eed3b 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h @@ -1,9 +1,8 @@ #ifndef __NVBIOS_INIT_H__ #define __NVBIOS_INIT_H__ - struct nvbios_init { - struct nouveau_subdev *subdev; - struct nouveau_bios *bios; + struct nvkm_subdev *subdev; + struct nvkm_bios *bios; u16 offset; struct dcb_output *outp; int crtc; @@ -17,6 +16,5 @@ struct nvbios_init { }; int nvbios_exec(struct nvbios_init *); -int nvbios_init(struct nouveau_subdev *, bool execute); - +int nvbios_init(struct nvkm_subdev *, bool execute); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h new file mode 100644 index 000000000000..4e31b64c5edf --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h @@ -0,0 +1,6 @@ +#ifndef __NVBIOS_MXM_H__ +#define __NVBIOS_MXM_H__ +u16 mxm_table(struct nvkm_bios *, u8 *ver, u8 *hdr); +u8 mxm_sor_map(struct nvkm_bios *, u8 conn); +u8 mxm_ddc_map(struct nvkm_bios *, u8 port); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h new file mode 100644 index 000000000000..64a59549b7ea --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h @@ -0,0 +1,10 @@ +#ifndef __NVBIOS_NPDE_H__ +#define __NVBIOS_NPDE_H__ +struct nvbios_npdeT { + u32 image_size; + bool last; +}; + +u32 nvbios_npdeTe(struct nvkm_bios *, u32); +u32 nvbios_npdeTp(struct nvkm_bios *, u32, struct nvbios_npdeT *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pcir.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h index 3d634a06dca1..e85931541f4f 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pcir.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h @@ -1,6 +1,5 @@ #ifndef __NVBIOS_PCIR_H__ #define __NVBIOS_PCIR_H__ - struct nvbios_pcirT { u16 vendor_id; u16 device_id; @@ -11,8 +10,7 @@ struct nvbios_pcirT { bool last; }; -u32 nvbios_pcirTe(struct nouveau_bios *, u32, u8 *ver, u16 *hdr); -u32 nvbios_pcirTp(struct nouveau_bios *, u32, u8 *ver, u16 *hdr, +u32 nvbios_pcirTe(struct nvkm_bios *, u32, u8 *ver, u16 *hdr); +u32 nvbios_pcirTp(struct nvkm_bios *, u32, u8 *ver, u16 *hdr, struct nvbios_pcirT *); - #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h index 16ff06ec2a88..7cc2becabc69 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h @@ -1,9 +1,6 @@ #ifndef __NVBIOS_PERF_H__ #define __NVBIOS_PERF_H__ - -struct nouveau_bios; - -u16 nvbios_perf_table(struct nouveau_bios *, u8 *ver, u8 *hdr, +u16 nvbios_perf_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); struct nvbios_perfE { @@ -18,9 +15,9 @@ struct nvbios_perfE { u32 script; }; -u16 nvbios_perf_entry(struct nouveau_bios *, int idx, +u16 nvbios_perf_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_perfEp(struct nouveau_bios *, int idx, +u16 nvbios_perfEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *); struct nvbios_perfS { @@ -31,17 +28,14 @@ struct nvbios_perfS { }; }; -u32 nvbios_perfSe(struct nouveau_bios *, u32 data, int idx, +u32 nvbios_perfSe(struct nvkm_bios *, u32 data, int idx, u8 *ver, u8 *hdr, u8 cnt, u8 len); -u32 nvbios_perfSp(struct nouveau_bios *, u32 data, int idx, +u32 nvbios_perfSp(struct nvkm_bios *, u32 data, int idx, u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_perfS *); struct nvbios_perf_fan { u32 pwm_divisor; }; -int -nvbios_perf_fan_parse(struct nouveau_bios *, struct nvbios_perf_fan *); - - +int nvbios_perf_fan_parse(struct nvkm_bios *, struct nvbios_perf_fan *); #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h index b2f3d4d0aa49..5a69978d1e3b 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h @@ -1,8 +1,7 @@ #ifndef __NVBIOS_PLL_H__ #define __NVBIOS_PLL_H__ - /*XXX: kill me */ -struct nouveau_pll_vals { +struct nvkm_pll_vals { union { struct { #ifdef __BIG_ENDIAN @@ -20,10 +19,8 @@ struct nouveau_pll_vals { int refclk; }; -struct nouveau_bios; - /* these match types in pll limits table version 0x40, - * nouveau uses them on all chipsets internally where a + * nvkm uses them on all chipsets internally where a * specific pll needs to be referenced, but the exact * register isn't known. */ @@ -74,6 +71,5 @@ struct nvbios_pll { } vco1, vco2; }; -int nvbios_pll_parse(struct nouveau_bios *, u32 type, struct nvbios_pll *); - +int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *); #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h index 9de593deaea8..d606875c125a 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h @@ -1,11 +1,10 @@ #ifndef __NVBIOS_PMU_H__ #define __NVBIOS_PMU_H__ - struct nvbios_pmuT { }; -u32 nvbios_pmuTe(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u32 nvbios_pmuTp(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +u32 nvbios_pmuTe(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_pmuTp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_pmuT *); struct nvbios_pmuE { @@ -13,8 +12,8 @@ struct nvbios_pmuE { u32 data; }; -u32 nvbios_pmuEe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); -u32 nvbios_pmuEp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, +u32 nvbios_pmuEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_pmuEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, struct nvbios_pmuE *); struct nvbios_pmuR { @@ -32,6 +31,5 @@ struct nvbios_pmuR { u32 args_addr_pmu; }; -bool nvbios_pmuRm(struct nouveau_bios *, u8 type, struct nvbios_pmuR *); - +bool nvbios_pmuRm(struct nvkm_bios *, u8 type, struct nvbios_pmuR *); #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h index 4a0e0ceb41ba..420426793880 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h @@ -1,8 +1,5 @@ #ifndef __NVBIOS_RAMCFG_H__ #define __NVBIOS_RAMCFG_H__ - -struct nouveau_bios; - struct nvbios_ramcfg { unsigned rammap_ver; unsigned rammap_hdr; @@ -139,7 +136,6 @@ struct nvbios_ramcfg { }; }; -u8 nvbios_ramcfg_count(struct nouveau_bios *); -u8 nvbios_ramcfg_index(struct nouveau_subdev *); - +u8 nvbios_ramcfg_count(struct nvkm_bios *); +u8 nvbios_ramcfg_index(struct nvkm_subdev *); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h new file mode 100644 index 000000000000..609a905ec780 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h @@ -0,0 +1,21 @@ +#ifndef __NVBIOS_RAMMAP_H__ +#define __NVBIOS_RAMMAP_H__ +#include <subdev/bios/ramcfg.h> + +u32 nvbios_rammapTe(struct nvkm_bios *, u8 *ver, u8 *hdr, + u8 *cnt, u8 *len, u8 *snr, u8 *ssz); + +u32 nvbios_rammapEe(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_rammapEp(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *); +u32 nvbios_rammapEm(struct nvkm_bios *, u16 mhz, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *); + +u32 nvbios_rammapSe(struct nvkm_bios *, u32 data, + u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, + u8 *ver, u8 *hdr); +u32 nvbios_rammapSp(struct nvkm_bios *, u32 data, + u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, + u8 *ver, u8 *hdr, struct nvbios_ramcfg *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h index 295d093f3b30..dd3ba960e75d 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h @@ -1,8 +1,5 @@ #ifndef __NVBIOS_THERM_H__ #define __NVBIOS_THERM_H__ - -struct nouveau_bios; - struct nvbios_therm_threshold { u8 temp; u8 hysteresis; @@ -30,8 +27,8 @@ enum nvbios_therm_fan_type { }; /* no vbios have more than 6 */ -#define NOUVEAU_TEMP_FAN_TRIP_MAX 10 -struct nouveau_therm_trip_point { +#define NVKM_TEMP_FAN_TRIP_MAX 10 +struct nvbios_therm_trip_point { int fan_duty; int temp; int hysteresis; @@ -55,7 +52,7 @@ struct nvbios_therm_fan { u16 slow_down_period; enum nvbios_therm_fan_mode fan_mode; - struct nouveau_therm_trip_point trip[NOUVEAU_TEMP_FAN_TRIP_MAX]; + struct nvbios_therm_trip_point trip[NVKM_TEMP_FAN_TRIP_MAX]; u8 nr_fan_trip; u8 linear_min_temp; u8 linear_max_temp; @@ -67,11 +64,9 @@ enum nvbios_therm_domain { }; int -nvbios_therm_sensor_parse(struct nouveau_bios *, enum nvbios_therm_domain, +nvbios_therm_sensor_parse(struct nvkm_bios *, enum nvbios_therm_domain, struct nvbios_therm_sensor *); int -nvbios_therm_fan_parse(struct nouveau_bios *, struct nvbios_therm_fan *); - - +nvbios_therm_fan_parse(struct nvkm_bios *, struct nvbios_therm_fan *); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h new file mode 100644 index 000000000000..339a826aa176 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h @@ -0,0 +1,11 @@ +#ifndef __NVBIOS_TIMING_H__ +#define __NVBIOS_TIMING_H__ +#include <subdev/bios/ramcfg.h> + +u16 nvbios_timingTe(struct nvkm_bios *, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); +u16 nvbios_timingEe(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_timingEp(struct nvkm_bios *, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h new file mode 100644 index 000000000000..6633c6db9281 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h @@ -0,0 +1,21 @@ +#ifndef __NVBIOS_VMAP_H__ +#define __NVBIOS_VMAP_H__ +struct nvbios_vmap { +}; + +u16 nvbios_vmap_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_vmap_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_vmap *); + +struct nvbios_vmap_entry { + u8 unk0; + u8 link; + u32 min; + u32 max; + s32 arg[6]; +}; + +u16 nvbios_vmap_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len); +u16 nvbios_vmap_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len, + struct nvbios_vmap_entry *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h new file mode 100644 index 000000000000..eb2de4b85bbd --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h @@ -0,0 +1,23 @@ +#ifndef __NVBIOS_VOLT_H__ +#define __NVBIOS_VOLT_H__ +struct nvbios_volt { + u8 vidmask; + u32 min; + u32 max; + u32 base; + s16 step; +}; + +u16 nvbios_volt_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u16 nvbios_volt_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_volt *); + +struct nvbios_volt_entry { + u32 voltage; + u8 vid; +}; + +u16 nvbios_volt_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len); +u16 nvbios_volt_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len, + struct nvbios_volt_entry *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h index 360baab52e4c..0c0fe234ff12 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h @@ -11,9 +11,8 @@ struct nvbios_xpio { u8 flags; }; -u16 dcb_xpio_table(struct nouveau_bios *, u8 idx, +u16 dcb_xpio_table(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 dcb_xpio_parse(struct nouveau_bios *, u8 idx, +u16 dcb_xpio_parse(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_xpio *); - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h new file mode 100644 index 000000000000..fba83c04849e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h @@ -0,0 +1,50 @@ +#ifndef __NVKM_BUS_H__ +#define __NVKM_BUS_H__ +#include <core/subdev.h> + +struct nvkm_bus_intr { + u32 stat; + u32 unit; +}; + +struct nvkm_bus { + struct nvkm_subdev base; + int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32); + u32 hwsq_size; +}; + +static inline struct nvkm_bus * +nvkm_bus(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BUS); +} + +#define nvkm_bus_create(p, e, o, d) \ + nvkm_subdev_create_((p), (e), (o), 0, "PBUS", "master", \ + sizeof(**d), (void **)d) +#define nvkm_bus_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_bus_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_bus_fini(p, s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +#define _nvkm_bus_dtor _nvkm_subdev_dtor +#define _nvkm_bus_init _nvkm_subdev_init +#define _nvkm_bus_fini _nvkm_subdev_fini + +extern struct nvkm_oclass *nv04_bus_oclass; +extern struct nvkm_oclass *nv31_bus_oclass; +extern struct nvkm_oclass *nv50_bus_oclass; +extern struct nvkm_oclass *g94_bus_oclass; +extern struct nvkm_oclass *gf100_bus_oclass; + +/* interface to sequencer */ +struct nvkm_hwsq; +int nvkm_hwsq_init(struct nvkm_bus *, struct nvkm_hwsq **); +int nvkm_hwsq_fini(struct nvkm_hwsq **, bool exec); +void nvkm_hwsq_wr32(struct nvkm_hwsq *, u32 addr, u32 data); +void nvkm_hwsq_setf(struct nvkm_hwsq *, u8 flag, int data); +void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data); +void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h new file mode 100644 index 000000000000..f5d303850d8c --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h @@ -0,0 +1,161 @@ +#ifndef __NVKM_CLK_H__ +#define __NVKM_CLK_H__ +#include <core/subdev.h> +#include <core/notify.h> +struct nvbios_pll; +struct nvkm_pll_vals; + +enum nv_clk_src { + nv_clk_src_crystal, + nv_clk_src_href, + + nv_clk_src_hclk, + nv_clk_src_hclkm3, + nv_clk_src_hclkm3d2, + nv_clk_src_hclkm2d3, /* NVAA */ + nv_clk_src_hclkm4, /* NVAA */ + nv_clk_src_cclk, /* NVAA */ + + nv_clk_src_host, + + nv_clk_src_sppll0, + nv_clk_src_sppll1, + + nv_clk_src_mpllsrcref, + nv_clk_src_mpllsrc, + nv_clk_src_mpll, + nv_clk_src_mdiv, + + nv_clk_src_core, + nv_clk_src_core_intm, + nv_clk_src_shader, + + nv_clk_src_mem, + + nv_clk_src_gpc, + nv_clk_src_rop, + nv_clk_src_hubk01, + nv_clk_src_hubk06, + nv_clk_src_hubk07, + nv_clk_src_copy, + nv_clk_src_daemon, + nv_clk_src_disp, + nv_clk_src_vdec, + + nv_clk_src_dom6, + + nv_clk_src_max, +}; + +struct nvkm_cstate { + struct list_head head; + u8 voltage; + u32 domain[nv_clk_src_max]; +}; + +struct nvkm_pstate { + struct list_head head; + struct list_head list; /* c-states */ + struct nvkm_cstate base; + u8 pstate; + u8 fanspeed; +}; + +struct nvkm_domain { + enum nv_clk_src name; + u8 bios; /* 0xff for none */ +#define NVKM_CLK_DOM_FLAG_CORE 0x01 + u8 flags; + const char *mname; + int mdiv; +}; + +struct nvkm_clk { + struct nvkm_subdev base; + + struct nvkm_domain *domains; + struct nvkm_pstate bstate; + + struct list_head states; + int state_nr; + + struct work_struct work; + wait_queue_head_t wait; + atomic_t waiting; + + struct nvkm_notify pwrsrc_ntfy; + int pwrsrc; + int pstate; /* current */ + int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ + int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ + int astate; /* perfmon adjustment (base) */ + int tstate; /* thermal adjustment (max-) */ + int dstate; /* display adjustment (min+) */ + + bool allow_reclock; + + int (*read)(struct nvkm_clk *, enum nv_clk_src); + int (*calc)(struct nvkm_clk *, struct nvkm_cstate *); + int (*prog)(struct nvkm_clk *); + void (*tidy)(struct nvkm_clk *); + + /*XXX: die, these are here *only* to support the completely + * bat-shit insane what-was-nvkm_hw.c code + */ + int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk, + struct nvkm_pll_vals *pv); + int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv); +}; + +static inline struct nvkm_clk * +nvkm_clk(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_CLK); +} + +#define nvkm_clk_create(p,e,o,i,r,s,n,d) \ + nvkm_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \ + (void **)d) +#define nvkm_clk_destroy(p) ({ \ + struct nvkm_clk *clk = (p); \ + _nvkm_clk_dtor(nv_object(clk)); \ +}) +#define nvkm_clk_init(p) ({ \ + struct nvkm_clk *clk = (p); \ + _nvkm_clk_init(nv_object(clk)); \ +}) +#define nvkm_clk_fini(p,s) ({ \ + struct nvkm_clk *clk = (p); \ + _nvkm_clk_fini(nv_object(clk), (s)); \ +}) + +int nvkm_clk_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, + struct nvkm_domain *, struct nvkm_pstate *, + int, bool, int, void **); +void _nvkm_clk_dtor(struct nvkm_object *); +int _nvkm_clk_init(struct nvkm_object *); +int _nvkm_clk_fini(struct nvkm_object *, bool); + +extern struct nvkm_oclass nv04_clk_oclass; +extern struct nvkm_oclass nv40_clk_oclass; +extern struct nvkm_oclass *nv50_clk_oclass; +extern struct nvkm_oclass *g84_clk_oclass; +extern struct nvkm_oclass *mcp77_clk_oclass; +extern struct nvkm_oclass gt215_clk_oclass; +extern struct nvkm_oclass gf100_clk_oclass; +extern struct nvkm_oclass gk104_clk_oclass; +extern struct nvkm_oclass gk20a_clk_oclass; + +int nv04_clk_pll_set(struct nvkm_clk *, u32 type, u32 freq); +int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk, + struct nvkm_pll_vals *); +int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *); +int gt215_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, + int clk, struct nvkm_pll_vals *); + +int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr); +int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait); +int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel); +int nvkm_clk_tstate(struct nvkm_clk *, int req, int rel); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h new file mode 100644 index 000000000000..d1bbe0d62b35 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h @@ -0,0 +1,32 @@ +#ifndef __NVKM_DEVINIT_H__ +#define __NVKM_DEVINIT_H__ +#include <core/subdev.h> + +struct nvkm_devinit { + struct nvkm_subdev base; + bool post; + void (*meminit)(struct nvkm_devinit *); + int (*pll_set)(struct nvkm_devinit *, u32 type, u32 freq); + u32 (*mmio)(struct nvkm_devinit *, u32 addr); +}; + +static inline struct nvkm_devinit * +nvkm_devinit(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_DEVINIT); +} + +extern struct nvkm_oclass *nv04_devinit_oclass; +extern struct nvkm_oclass *nv05_devinit_oclass; +extern struct nvkm_oclass *nv10_devinit_oclass; +extern struct nvkm_oclass *nv1a_devinit_oclass; +extern struct nvkm_oclass *nv20_devinit_oclass; +extern struct nvkm_oclass *nv50_devinit_oclass; +extern struct nvkm_oclass *g84_devinit_oclass; +extern struct nvkm_oclass *g98_devinit_oclass; +extern struct nvkm_oclass *gt215_devinit_oclass; +extern struct nvkm_oclass *mcp89_devinit_oclass; +extern struct nvkm_oclass *gf100_devinit_oclass; +extern struct nvkm_oclass *gm107_devinit_oclass; +extern struct nvkm_oclass *gm204_devinit_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h new file mode 100644 index 000000000000..16da56cf43b0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -0,0 +1,154 @@ +#ifndef __NVKM_FB_H__ +#define __NVKM_FB_H__ +#include <core/subdev.h> + +#include <subdev/mmu.h> + +/* memory type/access flags, do not match hardware values */ +#define NV_MEM_ACCESS_RO 1 +#define NV_MEM_ACCESS_WO 2 +#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) +#define NV_MEM_ACCESS_SYS 4 +#define NV_MEM_ACCESS_VM 8 +#define NV_MEM_ACCESS_NOSNOOP 16 + +#define NV_MEM_TARGET_VRAM 0 +#define NV_MEM_TARGET_PCI 1 +#define NV_MEM_TARGET_PCI_NOSNOOP 2 +#define NV_MEM_TARGET_VM 3 +#define NV_MEM_TARGET_GART 4 + +#define NV_MEM_TYPE_VM 0x7f +#define NV_MEM_COMP_VM 0x03 + +struct nvkm_mem { + struct drm_device *dev; + + struct nvkm_vma bar_vma; + struct nvkm_vma vma[2]; + u8 page_shift; + + struct nvkm_mm_node *tag; + struct list_head regions; + dma_addr_t *pages; + u32 memtype; + u64 offset; + u64 size; + struct sg_table *sg; +}; + +struct nvkm_fb_tile { + struct nvkm_mm_node *tag; + u32 addr; + u32 limit; + u32 pitch; + u32 zcomp; +}; + +struct nvkm_fb { + struct nvkm_subdev base; + + bool (*memtype_valid)(struct nvkm_fb *, u32 memtype); + + struct nvkm_ram *ram; + + struct nvkm_mm vram; + struct nvkm_mm tags; + + struct { + struct nvkm_fb_tile region[16]; + int regions; + void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); + void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags, + struct nvkm_fb_tile *); + void (*fini)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); + void (*prog)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); + } tile; +}; + +static inline struct nvkm_fb * +nvkm_fb(void *obj) +{ + /* fbram uses this before device subdev pointer is valid */ + if (nv_iclass(obj, NV_SUBDEV_CLASS) && + nv_subidx(obj) == NVDEV_SUBDEV_FB) + return obj; + + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FB); +} + +extern struct nvkm_oclass *nv04_fb_oclass; +extern struct nvkm_oclass *nv10_fb_oclass; +extern struct nvkm_oclass *nv1a_fb_oclass; +extern struct nvkm_oclass *nv20_fb_oclass; +extern struct nvkm_oclass *nv25_fb_oclass; +extern struct nvkm_oclass *nv30_fb_oclass; +extern struct nvkm_oclass *nv35_fb_oclass; +extern struct nvkm_oclass *nv36_fb_oclass; +extern struct nvkm_oclass *nv40_fb_oclass; +extern struct nvkm_oclass *nv41_fb_oclass; +extern struct nvkm_oclass *nv44_fb_oclass; +extern struct nvkm_oclass *nv46_fb_oclass; +extern struct nvkm_oclass *nv47_fb_oclass; +extern struct nvkm_oclass *nv49_fb_oclass; +extern struct nvkm_oclass *nv4e_fb_oclass; +extern struct nvkm_oclass *nv50_fb_oclass; +extern struct nvkm_oclass *g84_fb_oclass; +extern struct nvkm_oclass *gt215_fb_oclass; +extern struct nvkm_oclass *mcp77_fb_oclass; +extern struct nvkm_oclass *mcp89_fb_oclass; +extern struct nvkm_oclass *gf100_fb_oclass; +extern struct nvkm_oclass *gk104_fb_oclass; +extern struct nvkm_oclass *gk20a_fb_oclass; +extern struct nvkm_oclass *gm107_fb_oclass; + +#include <subdev/bios.h> +#include <subdev/bios/ramcfg.h> + +struct nvkm_ram_data { + struct list_head head; + struct nvbios_ramcfg bios; + u32 freq; +}; + +struct nvkm_ram { + struct nvkm_object base; + enum { + NV_MEM_TYPE_UNKNOWN = 0, + NV_MEM_TYPE_STOLEN, + NV_MEM_TYPE_SGRAM, + NV_MEM_TYPE_SDRAM, + NV_MEM_TYPE_DDR1, + NV_MEM_TYPE_DDR2, + NV_MEM_TYPE_DDR3, + NV_MEM_TYPE_GDDR2, + NV_MEM_TYPE_GDDR3, + NV_MEM_TYPE_GDDR4, + NV_MEM_TYPE_GDDR5 + } type; + u64 stolen; + u64 size; + u32 tags; + + int ranks; + int parts; + int part_mask; + + int (*get)(struct nvkm_fb *, u64 size, u32 align, u32 size_nc, + u32 type, struct nvkm_mem **); + void (*put)(struct nvkm_fb *, struct nvkm_mem **); + + int (*calc)(struct nvkm_fb *, u32 freq); + int (*prog)(struct nvkm_fb *); + void (*tidy)(struct nvkm_fb *); + u32 freq; + u32 mr[16]; + u32 mr1_nuts; + + struct nvkm_ram_data *next; + struct nvkm_ram_data former; + struct nvkm_ram_data xition; + struct nvkm_ram_data target; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h new file mode 100644 index 000000000000..a1384786adc9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h @@ -0,0 +1,28 @@ +#ifndef __NVKM_FUSE_H__ +#define __NVKM_FUSE_H__ +#include <core/subdev.h> +#include <core/device.h> + +struct nvkm_fuse { + struct nvkm_subdev base; +}; + +static inline struct nvkm_fuse * +nvkm_fuse(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FUSE); +} + +#define nvkm_fuse_create(p, e, o, d) \ + nvkm_fuse_create_((p), (e), (o), sizeof(**d), (void **)d) + +int nvkm_fuse_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_fuse_dtor(struct nvkm_object *); +int _nvkm_fuse_init(struct nvkm_object *); +#define _nvkm_fuse_fini _nvkm_subdev_fini + +extern struct nvkm_oclass nv50_fuse_oclass; +extern struct nvkm_oclass gf100_fuse_oclass; +extern struct nvkm_oclass gm107_fuse_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h new file mode 100644 index 000000000000..ca5099a81b5a --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h @@ -0,0 +1,44 @@ +#ifndef __NVKM_GPIO_H__ +#define __NVKM_GPIO_H__ +#include <core/subdev.h> +#include <core/event.h> + +#include <subdev/bios.h> +#include <subdev/bios/gpio.h> + +struct nvkm_gpio_ntfy_req { +#define NVKM_GPIO_HI 0x01 +#define NVKM_GPIO_LO 0x02 +#define NVKM_GPIO_TOGGLED 0x03 + u8 mask; + u8 line; +}; + +struct nvkm_gpio_ntfy_rep { + u8 mask; +}; + +struct nvkm_gpio { + struct nvkm_subdev base; + + struct nvkm_event event; + + void (*reset)(struct nvkm_gpio *, u8 func); + int (*find)(struct nvkm_gpio *, int idx, u8 tag, u8 line, + struct dcb_gpio_func *); + int (*set)(struct nvkm_gpio *, int idx, u8 tag, u8 line, int state); + int (*get)(struct nvkm_gpio *, int idx, u8 tag, u8 line); +}; + +static inline struct nvkm_gpio * +nvkm_gpio(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_GPIO); +} + +extern struct nvkm_oclass *nv10_gpio_oclass; +extern struct nvkm_oclass *nv50_gpio_oclass; +extern struct nvkm_oclass *g94_gpio_oclass; +extern struct nvkm_oclass *gf110_gpio_oclass; +extern struct nvkm_oclass *gk104_gpio_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h new file mode 100644 index 000000000000..a2e33730f05e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h @@ -0,0 +1,135 @@ +#ifndef __NVKM_I2C_H__ +#define __NVKM_I2C_H__ +#include <core/subdev.h> +#include <core/event.h> + +#include <subdev/bios.h> +#include <subdev/bios/i2c.h> + +#define NV_I2C_PORT(n) (0x00 + (n)) +#define NV_I2C_AUX(n) (0x10 + (n)) +#define NV_I2C_EXT(n) (0x20 + (n)) +#define NV_I2C_DEFAULT(n) (0x80 + (n)) + +#define NV_I2C_TYPE_DCBI2C(n) (0x0000 | (n)) +#define NV_I2C_TYPE_EXTDDC(e) (0x0005 | (e) << 8) +#define NV_I2C_TYPE_EXTAUX(e) (0x0006 | (e) << 8) + +struct nvkm_i2c_ntfy_req { +#define NVKM_I2C_PLUG 0x01 +#define NVKM_I2C_UNPLUG 0x02 +#define NVKM_I2C_IRQ 0x04 +#define NVKM_I2C_DONE 0x08 +#define NVKM_I2C_ANY 0x0f + u8 mask; + u8 port; +}; + +struct nvkm_i2c_ntfy_rep { + u8 mask; +}; + +struct nvkm_i2c_port { + struct nvkm_object base; + struct i2c_adapter adapter; + struct mutex mutex; + + struct list_head head; + u8 index; + int aux; + + const struct nvkm_i2c_func *func; +}; + +struct nvkm_i2c_func { + void (*drive_scl)(struct nvkm_i2c_port *, int); + void (*drive_sda)(struct nvkm_i2c_port *, int); + int (*sense_scl)(struct nvkm_i2c_port *); + int (*sense_sda)(struct nvkm_i2c_port *); + + int (*aux)(struct nvkm_i2c_port *, bool, u8, u32, u8 *, u8); + int (*pattern)(struct nvkm_i2c_port *, int pattern); + int (*lnk_ctl)(struct nvkm_i2c_port *, int nr, int bw, bool enh); + int (*drv_ctl)(struct nvkm_i2c_port *, int lane, int sw, int pe); +}; + +struct nvkm_i2c_board_info { + struct i2c_board_info dev; + u8 udelay; /* set to 0 to use the standard delay */ +}; + +struct nvkm_i2c { + struct nvkm_subdev base; + struct nvkm_event event; + + struct nvkm_i2c_port *(*find)(struct nvkm_i2c *, u8 index); + struct nvkm_i2c_port *(*find_type)(struct nvkm_i2c *, u16 type); + int (*acquire_pad)(struct nvkm_i2c_port *, unsigned long timeout); + void (*release_pad)(struct nvkm_i2c_port *); + int (*acquire)(struct nvkm_i2c_port *, unsigned long timeout); + void (*release)(struct nvkm_i2c_port *); + int (*identify)(struct nvkm_i2c *, int index, + const char *what, struct nvkm_i2c_board_info *, + bool (*match)(struct nvkm_i2c_port *, + struct i2c_board_info *, void *), + void *); + + wait_queue_head_t wait; + struct list_head ports; +}; + +static inline struct nvkm_i2c * +nvkm_i2c(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_I2C); +} + +extern struct nvkm_oclass *nv04_i2c_oclass; +extern struct nvkm_oclass *nv4e_i2c_oclass; +extern struct nvkm_oclass *nv50_i2c_oclass; +extern struct nvkm_oclass *g94_i2c_oclass; +extern struct nvkm_oclass *gf110_i2c_oclass; +extern struct nvkm_oclass *gf117_i2c_oclass; +extern struct nvkm_oclass *gk104_i2c_oclass; +extern struct nvkm_oclass *gm204_i2c_oclass; + +static inline int +nv_rdi2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg) +{ + u8 val; + struct i2c_msg msgs[] = { + { .addr = addr, .flags = 0, .len = 1, .buf = ® }, + { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = &val }, + }; + + int ret = i2c_transfer(&port->adapter, msgs, 2); + if (ret != 2) + return -EIO; + + return val; +} + +static inline int +nv_wri2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg, u8 val) +{ + u8 buf[2] = { reg, val }; + struct i2c_msg msgs[] = { + { .addr = addr, .flags = 0, .len = 2, .buf = buf }, + }; + + int ret = i2c_transfer(&port->adapter, msgs, 1); + if (ret != 1) + return -EIO; + + return 0; +} + +static inline bool +nv_probe_i2c(struct nvkm_i2c_port *port, u8 addr) +{ + return nv_rdi2cr(port, addr, 0) >= 0; +} + +int nv_rdaux(struct nvkm_i2c_port *, u32 addr, u8 *data, u8 size); +int nv_wraux(struct nvkm_i2c_port *, u32 addr, u8 *data, u8 size); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h new file mode 100644 index 000000000000..2150d8af0040 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h @@ -0,0 +1,32 @@ +#ifndef __NVKM_IBUS_H__ +#define __NVKM_IBUS_H__ +#include <core/subdev.h> + +struct nvkm_ibus { + struct nvkm_subdev base; +}; + +static inline struct nvkm_ibus * +nvkm_ibus(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_IBUS); +} + +#define nvkm_ibus_create(p,e,o,d) \ + nvkm_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \ + sizeof(**d), (void **)d) +#define nvkm_ibus_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_ibus_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_ibus_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +#define _nvkm_ibus_dtor _nvkm_subdev_dtor +#define _nvkm_ibus_init _nvkm_subdev_init +#define _nvkm_ibus_fini _nvkm_subdev_fini + +extern struct nvkm_oclass gf100_ibus_oclass; +extern struct nvkm_oclass gk104_ibus_oclass; +extern struct nvkm_oclass gk20a_ibus_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h new file mode 100644 index 000000000000..d104c1aac807 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h @@ -0,0 +1,48 @@ +#ifndef __NVKM_INSTMEM_H__ +#define __NVKM_INSTMEM_H__ +#include <core/subdev.h> + +struct nvkm_instobj { + struct nvkm_object base; + struct list_head head; + u32 *suspend; + u64 addr; + u32 size; +}; + +static inline struct nvkm_instobj * +nv_memobj(void *obj) +{ +#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA + if (unlikely(!nv_iclass(obj, NV_MEMOBJ_CLASS))) + nv_assert("BAD CAST -> NvMemObj, %08x", nv_hclass(obj)); +#endif + return obj; +} + +struct nvkm_instmem { + struct nvkm_subdev base; + struct list_head list; + + u32 reserved; + int (*alloc)(struct nvkm_instmem *, struct nvkm_object *, + u32 size, u32 align, struct nvkm_object **); +}; + +static inline struct nvkm_instmem * +nvkm_instmem(void *obj) +{ + /* nv04/nv40 impls need to create objects in their constructor, + * which is before the subdev pointer is valid + */ + if (nv_iclass(obj, NV_SUBDEV_CLASS) && + nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM) + return obj; + + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_INSTMEM); +} + +extern struct nvkm_oclass *nv04_instmem_oclass; +extern struct nvkm_oclass *nv40_instmem_oclass; +extern struct nvkm_oclass *nv50_instmem_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h new file mode 100644 index 000000000000..cd5d29fc0565 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h @@ -0,0 +1,31 @@ +#ifndef __NVKM_LTC_H__ +#define __NVKM_LTC_H__ +#include <core/subdev.h> +struct nvkm_mm_node; + +#define NVKM_LTC_MAX_ZBC_CNT 16 + +struct nvkm_ltc { + struct nvkm_subdev base; + + int (*tags_alloc)(struct nvkm_ltc *, u32 count, + struct nvkm_mm_node **); + void (*tags_free)(struct nvkm_ltc *, struct nvkm_mm_node **); + void (*tags_clear)(struct nvkm_ltc *, u32 first, u32 count); + + int zbc_min; + int zbc_max; + int (*zbc_color_get)(struct nvkm_ltc *, int index, const u32[4]); + int (*zbc_depth_get)(struct nvkm_ltc *, int index, const u32); +}; + +static inline struct nvkm_ltc * +nvkm_ltc(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_LTC); +} + +extern struct nvkm_oclass *gf100_ltc_oclass; +extern struct nvkm_oclass *gk104_ltc_oclass; +extern struct nvkm_oclass *gm107_ltc_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h new file mode 100644 index 000000000000..055bea7702a1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h @@ -0,0 +1,28 @@ +#ifndef __NVKM_MC_H__ +#define __NVKM_MC_H__ +#include <core/subdev.h> + +struct nvkm_mc { + struct nvkm_subdev base; + bool use_msi; + unsigned int irq; + void (*unk260)(struct nvkm_mc *, u32); +}; + +static inline struct nvkm_mc * +nvkm_mc(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MC); +} + +extern struct nvkm_oclass *nv04_mc_oclass; +extern struct nvkm_oclass *nv40_mc_oclass; +extern struct nvkm_oclass *nv44_mc_oclass; +extern struct nvkm_oclass *nv4c_mc_oclass; +extern struct nvkm_oclass *nv50_mc_oclass; +extern struct nvkm_oclass *g94_mc_oclass; +extern struct nvkm_oclass *g98_mc_oclass; +extern struct nvkm_oclass *gf100_mc_oclass; +extern struct nvkm_oclass *gf106_mc_oclass; +extern struct nvkm_oclass *gk20a_mc_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h new file mode 100644 index 000000000000..3a5368776c31 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h @@ -0,0 +1,104 @@ +#ifndef __NVKM_MMU_H__ +#define __NVKM_MMU_H__ +#include <core/subdev.h> +#include <core/mm.h> +struct nvkm_device; +struct nvkm_mem; + +struct nvkm_vm_pgt { + struct nvkm_gpuobj *obj[2]; + u32 refcount[2]; +}; + +struct nvkm_vm_pgd { + struct list_head head; + struct nvkm_gpuobj *obj; +}; + +struct nvkm_vma { + struct list_head head; + int refcount; + struct nvkm_vm *vm; + struct nvkm_mm_node *node; + u64 offset; + u32 access; +}; + +struct nvkm_vm { + struct nvkm_mmu *mmu; + struct nvkm_mm mm; + struct kref refcount; + + struct list_head pgd_list; + atomic_t engref[NVDEV_SUBDEV_NR]; + + struct nvkm_vm_pgt *pgt; + u32 fpde; + u32 lpde; +}; + +struct nvkm_mmu { + struct nvkm_subdev base; + + u64 limit; + u8 dma_bits; + u32 pgt_bits; + u8 spg_shift; + u8 lpg_shift; + + int (*create)(struct nvkm_mmu *, u64 offset, u64 length, + u64 mm_offset, struct nvkm_vm **); + + void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde, + struct nvkm_gpuobj *pgt[2]); + void (*map)(struct nvkm_vma *, struct nvkm_gpuobj *, + struct nvkm_mem *, u32 pte, u32 cnt, + u64 phys, u64 delta); + void (*map_sg)(struct nvkm_vma *, struct nvkm_gpuobj *, + struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *); + void (*unmap)(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt); + void (*flush)(struct nvkm_vm *); +}; + +static inline struct nvkm_mmu * +nvkm_mmu(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU); +} + +#define nvkm_mmu_create(p,e,o,i,f,d) \ + nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d)) +#define nvkm_mmu_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_mmu_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_mmu_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +#define _nvkm_mmu_dtor _nvkm_subdev_dtor +#define _nvkm_mmu_init _nvkm_subdev_init +#define _nvkm_mmu_fini _nvkm_subdev_fini + +extern struct nvkm_oclass nv04_mmu_oclass; +extern struct nvkm_oclass nv41_mmu_oclass; +extern struct nvkm_oclass nv44_mmu_oclass; +extern struct nvkm_oclass nv50_mmu_oclass; +extern struct nvkm_oclass gf100_mmu_oclass; + +int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64, + struct nvkm_vm **); +void nv04_mmu_dtor(struct nvkm_object *); + +int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset, + u32 block, struct nvkm_vm **); +int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset, + struct nvkm_vm **); +int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd); +int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access, + struct nvkm_vma *); +void nvkm_vm_put(struct nvkm_vma *); +void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *); +void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *); +void nvkm_vm_unmap(struct nvkm_vma *); +void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h new file mode 100644 index 000000000000..fba613477b1a --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h @@ -0,0 +1,34 @@ +#ifndef __NVKM_MXM_H__ +#define __NVKM_MXM_H__ +#include <core/subdev.h> + +#define MXM_SANITISE_DCB 0x00000001 + +struct nvkm_mxm { + struct nvkm_subdev base; + u32 action; + u8 *mxms; +}; + +static inline struct nvkm_mxm * +nvkm_mxm(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MXM); +} + +#define nvkm_mxm_create(p,e,o,d) \ + nvkm_mxm_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_mxm_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_mxm_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) +int nvkm_mxm_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void nvkm_mxm_destroy(struct nvkm_mxm *); + +#define _nvkm_mxm_dtor _nvkm_subdev_dtor +#define _nvkm_mxm_init _nvkm_subdev_init +#define _nvkm_mxm_fini _nvkm_subdev_fini + +extern struct nvkm_oclass nv50_mxm_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h new file mode 100644 index 000000000000..7b86acc634a0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h @@ -0,0 +1,53 @@ +#ifndef __NVKM_PMU_H__ +#define __NVKM_PMU_H__ +#include <core/subdev.h> + +struct nvkm_pmu { + struct nvkm_subdev base; + + struct { + u32 base; + u32 size; + } send; + + struct { + u32 base; + u32 size; + + struct work_struct work; + wait_queue_head_t wait; + u32 process; + u32 message; + u32 data[2]; + } recv; + + int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32); + void (*pgob)(struct nvkm_pmu *, bool); +}; + +static inline struct nvkm_pmu * +nvkm_pmu(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU); +} + +extern struct nvkm_oclass *gt215_pmu_oclass; +extern struct nvkm_oclass *gf100_pmu_oclass; +extern struct nvkm_oclass *gf110_pmu_oclass; +extern struct nvkm_oclass *gk104_pmu_oclass; +extern struct nvkm_oclass *gk208_pmu_oclass; +extern struct nvkm_oclass *gk20a_pmu_oclass; + +/* interface to MEMX process running on PMU */ +struct nvkm_memx; +int nvkm_memx_init(struct nvkm_pmu *, struct nvkm_memx **); +int nvkm_memx_fini(struct nvkm_memx **, bool exec); +void nvkm_memx_wr32(struct nvkm_memx *, u32 addr, u32 data); +void nvkm_memx_wait(struct nvkm_memx *, u32 addr, u32 mask, u32 data, u32 nsec); +void nvkm_memx_nsec(struct nvkm_memx *, u32 nsec); +void nvkm_memx_wait_vblank(struct nvkm_memx *); +void nvkm_memx_train(struct nvkm_memx *); +int nvkm_memx_train_result(struct nvkm_pmu *, u32 *, int); +void nvkm_memx_block(struct nvkm_memx *); +void nvkm_memx_unblock(struct nvkm_memx *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h new file mode 100644 index 000000000000..6662829b6db1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h @@ -0,0 +1,79 @@ +#ifndef __NVKM_THERM_H__ +#define __NVKM_THERM_H__ +#include <core/subdev.h> + +enum nvkm_therm_fan_mode { + NVKM_THERM_CTRL_NONE = 0, + NVKM_THERM_CTRL_MANUAL = 1, + NVKM_THERM_CTRL_AUTO = 2, +}; + +enum nvkm_therm_attr_type { + NVKM_THERM_ATTR_FAN_MIN_DUTY = 0, + NVKM_THERM_ATTR_FAN_MAX_DUTY = 1, + NVKM_THERM_ATTR_FAN_MODE = 2, + + NVKM_THERM_ATTR_THRS_FAN_BOOST = 10, + NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST = 11, + NVKM_THERM_ATTR_THRS_DOWN_CLK = 12, + NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST = 13, + NVKM_THERM_ATTR_THRS_CRITICAL = 14, + NVKM_THERM_ATTR_THRS_CRITICAL_HYST = 15, + NVKM_THERM_ATTR_THRS_SHUTDOWN = 16, + NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST = 17, +}; + +struct nvkm_therm { + struct nvkm_subdev base; + + int (*pwm_ctrl)(struct nvkm_therm *, int line, bool); + int (*pwm_get)(struct nvkm_therm *, int line, u32 *, u32 *); + int (*pwm_set)(struct nvkm_therm *, int line, u32, u32); + int (*pwm_clock)(struct nvkm_therm *, int line); + + int (*fan_get)(struct nvkm_therm *); + int (*fan_set)(struct nvkm_therm *, int); + int (*fan_sense)(struct nvkm_therm *); + + int (*temp_get)(struct nvkm_therm *); + + int (*attr_get)(struct nvkm_therm *, enum nvkm_therm_attr_type); + int (*attr_set)(struct nvkm_therm *, enum nvkm_therm_attr_type, int); +}; + +static inline struct nvkm_therm * +nvkm_therm(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_THERM); +} + +#define nvkm_therm_create(p,e,o,d) \ + nvkm_therm_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_therm_destroy(p) ({ \ + struct nvkm_therm *therm = (p); \ + _nvkm_therm_dtor(nv_object(therm)); \ +}) +#define nvkm_therm_init(p) ({ \ + struct nvkm_therm *therm = (p); \ + _nvkm_therm_init(nv_object(therm)); \ +}) +#define nvkm_therm_fini(p,s) ({ \ + struct nvkm_therm *therm = (p); \ + _nvkm_therm_init(nv_object(therm), (s)); \ +}) + +int nvkm_therm_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_therm_dtor(struct nvkm_object *); +int _nvkm_therm_init(struct nvkm_object *); +int _nvkm_therm_fini(struct nvkm_object *, bool); + +int nvkm_therm_cstate(struct nvkm_therm *, int, int); + +extern struct nvkm_oclass nv40_therm_oclass; +extern struct nvkm_oclass nv50_therm_oclass; +extern struct nvkm_oclass g84_therm_oclass; +extern struct nvkm_oclass gt215_therm_oclass; +extern struct nvkm_oclass gf110_therm_oclass; +extern struct nvkm_oclass gm107_therm_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h new file mode 100644 index 000000000000..4ad55082ef7a --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h @@ -0,0 +1,61 @@ +#ifndef __NVKM_TIMER_H__ +#define __NVKM_TIMER_H__ +#include <core/subdev.h> + +struct nvkm_alarm { + struct list_head head; + u64 timestamp; + void (*func)(struct nvkm_alarm *); +}; + +static inline void +nvkm_alarm_init(struct nvkm_alarm *alarm, + void (*func)(struct nvkm_alarm *)) +{ + INIT_LIST_HEAD(&alarm->head); + alarm->func = func; +} + +bool nvkm_timer_wait_eq(void *, u64 nsec, u32 addr, u32 mask, u32 data); +bool nvkm_timer_wait_ne(void *, u64 nsec, u32 addr, u32 mask, u32 data); +bool nvkm_timer_wait_cb(void *, u64 nsec, bool (*func)(void *), void *data); +void nvkm_timer_alarm(void *, u32 nsec, struct nvkm_alarm *); +void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *); + +#define NV_WAIT_DEFAULT 2000000000ULL +#define nv_wait(o,a,m,v) \ + nvkm_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v)) +#define nv_wait_ne(o,a,m,v) \ + nvkm_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v)) +#define nv_wait_cb(o,c,d) \ + nvkm_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d)) + +struct nvkm_timer { + struct nvkm_subdev base; + u64 (*read)(struct nvkm_timer *); + void (*alarm)(struct nvkm_timer *, u64 time, struct nvkm_alarm *); + void (*alarm_cancel)(struct nvkm_timer *, struct nvkm_alarm *); +}; + +static inline struct nvkm_timer * +nvkm_timer(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_TIMER); +} + +#define nvkm_timer_create(p,e,o,d) \ + nvkm_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \ + sizeof(**d), (void **)d) +#define nvkm_timer_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_timer_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_timer_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +int nvkm_timer_create_(struct nvkm_object *, struct nvkm_engine *, + struct nvkm_oclass *, int size, void **); + +extern struct nvkm_oclass nv04_timer_oclass; +extern struct nvkm_oclass gk20a_timer_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vga.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h index fee09ad818e4..fee09ad818e4 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/vga.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h new file mode 100644 index 000000000000..e3d7243fbb1d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h @@ -0,0 +1,58 @@ +#ifndef __NVKM_VOLT_H__ +#define __NVKM_VOLT_H__ +#include <core/subdev.h> + +struct nvkm_voltage { + u32 uv; + u8 id; +}; + +struct nvkm_volt { + struct nvkm_subdev base; + + int (*vid_get)(struct nvkm_volt *); + int (*get)(struct nvkm_volt *); + int (*vid_set)(struct nvkm_volt *, u8 vid); + int (*set)(struct nvkm_volt *, u32 uv); + int (*set_id)(struct nvkm_volt *, u8 id, int condition); + + u8 vid_mask; + u8 vid_nr; + struct { + u32 uv; + u8 vid; + } vid[256]; +}; + +static inline struct nvkm_volt * +nvkm_volt(void *obj) +{ + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_VOLT); +} + +#define nvkm_volt_create(p, e, o, d) \ + nvkm_volt_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_volt_destroy(p) ({ \ + struct nvkm_volt *v = (p); \ + _nvkm_volt_dtor(nv_object(v)); \ +}) +#define nvkm_volt_init(p) ({ \ + struct nvkm_volt *v = (p); \ + _nvkm_volt_init(nv_object(v)); \ +}) +#define nvkm_volt_fini(p,s) \ + nvkm_subdev_fini((p), (s)) + +int nvkm_volt_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_volt_dtor(struct nvkm_object *); +int _nvkm_volt_init(struct nvkm_object *); +#define _nvkm_volt_fini _nvkm_subdev_fini + +extern struct nvkm_oclass nv40_volt_oclass; +extern struct nvkm_oclass gk20a_volt_oclass; + +int nvkm_voltgpio_init(struct nvkm_volt *); +int nvkm_voltgpio_get(struct nvkm_volt *); +int nvkm_voltgpio_set(struct nvkm_volt *, u8); +#endif diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index d39a15000068..d8b0891a141c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -100,7 +100,7 @@ static void nouveau_abi16_ntfy_fini(struct nouveau_abi16_chan *chan, struct nouveau_abi16_ntfy *ntfy) { - nouveau_mm_free(&chan->heap, &ntfy->node); + nvkm_mm_free(&chan->heap, &ntfy->node); list_del(&ntfy->head); kfree(ntfy); } @@ -128,7 +128,7 @@ nouveau_abi16_chan_fini(struct nouveau_abi16 *abi16, } if (chan->heap.block_size) - nouveau_mm_fini(&chan->heap); + nvkm_mm_fini(&chan->heap); /* destroy channel object, all children will be killed too */ if (chan->chan) { @@ -164,8 +164,8 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) struct nouveau_cli *cli = nouveau_cli(file_priv); struct nouveau_drm *drm = nouveau_drm(dev); struct nvif_device *device = &drm->device; - struct nouveau_timer *ptimer = nvkm_timer(device); - struct nouveau_graph *graph = nvkm_gr(device); + struct nvkm_timer *ptimer = nvxx_timer(device); + struct nvkm_gr *gr = nvxx_gr(device); struct drm_nouveau_getparam *getparam = data; switch (getparam->param) { @@ -173,19 +173,19 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) getparam->value = device->info.chipset; break; case NOUVEAU_GETPARAM_PCI_VENDOR: - if (nv_device_is_pci(nvkm_device(device))) + if (nv_device_is_pci(nvxx_device(device))) getparam->value = dev->pdev->vendor; else getparam->value = 0; break; case NOUVEAU_GETPARAM_PCI_DEVICE: - if (nv_device_is_pci(nvkm_device(device))) + if (nv_device_is_pci(nvxx_device(device))) getparam->value = dev->pdev->device; else getparam->value = 0; break; case NOUVEAU_GETPARAM_BUS_TYPE: - if (!nv_device_is_pci(nvkm_device(device))) + if (!nv_device_is_pci(nvxx_device(device))) getparam->value = 3; else if (drm_pci_device_is_agp(dev)) @@ -215,7 +215,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) getparam->value = 1; break; case NOUVEAU_GETPARAM_GRAPH_UNITS: - getparam->value = graph->units ? graph->units(graph) : 0; + getparam->value = gr->units ? gr->units(gr) : 0; break; default: NV_PRINTK(debug, cli, "unknown parameter %lld\n", getparam->param); @@ -324,7 +324,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) if (ret) goto done; - ret = nouveau_mm_init(&chan->heap, 0, PAGE_SIZE, 1); + ret = nvkm_mm_init(&chan->heap, 0, PAGE_SIZE, 1); done: if (ret) nouveau_abi16_chan_fini(abi16, chan); @@ -448,8 +448,8 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS) list_add(&ntfy->head, &chan->notifiers); ntfy->handle = info->handle; - ret = nouveau_mm_head(&chan->heap, 0, 1, info->size, info->size, 1, - &ntfy->node); + ret = nvkm_mm_head(&chan->heap, 0, 1, info->size, info->size, 1, + &ntfy->node); if (ret) goto done; @@ -527,7 +527,7 @@ nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS) /* cleanup extra state if this object was a notifier */ list_for_each_entry(ntfy, &chan->notifiers, head) { if (ntfy->handle == fini->handle) { - nouveau_mm_free(&chan->heap, &ntfy->node); + nvkm_mm_free(&chan->heap, &ntfy->node); list_del(&ntfy->head); break; } diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.h b/drivers/gpu/drm/nouveau/nouveau_abi16.h index 39844e6bfbff..86eb1caf4957 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.h +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.h @@ -14,7 +14,7 @@ int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS); struct nouveau_abi16_ntfy { struct list_head head; - struct nouveau_mm_node *node; + struct nvkm_mm_node *node; u32 handle; }; @@ -23,8 +23,8 @@ struct nouveau_abi16_chan { struct nouveau_channel *chan; struct list_head notifiers; struct nouveau_bo *ntfy; - struct nouveau_vma ntfy_vma; - struct nouveau_mm heap; + struct nvkm_vma ntfy_vma; + struct nvkm_mm heap; }; struct nouveau_abi16 { diff --git a/drivers/gpu/drm/nouveau/nouveau_agp.c b/drivers/gpu/drm/nouveau/nouveau_agp.c index 1f6f6ba6847a..0b5970955604 100644 --- a/drivers/gpu/drm/nouveau/nouveau_agp.c +++ b/drivers/gpu/drm/nouveau/nouveau_agp.c @@ -45,8 +45,8 @@ get_agp_mode(struct nouveau_drm *drm, const struct drm_agp_info *info) while (agpmode == -1 && quirk->hostbridge_vendor) { if (info->id_vendor == quirk->hostbridge_vendor && info->id_device == quirk->hostbridge_device && - nvkm_device(device)->pdev->vendor == quirk->chip_vendor && - nvkm_device(device)->pdev->device == quirk->chip_device) { + nvxx_device(device)->pdev->vendor == quirk->chip_vendor && + nvxx_device(device)->pdev->device == quirk->chip_device) { agpmode = quirk->mode; NV_INFO(drm, "Forcing agp mode to %dX. Use agpmode to override.\n", agpmode); diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 7df6acc8bb34..0190b69bbe25 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -2009,7 +2009,7 @@ uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) static bool NVInitVBIOS(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_bios *bios = nvkm_bios(&drm->device); + struct nvkm_bios *bios = nvxx_bios(&drm->device); struct nvbios *legacy = &drm->vbios; memset(legacy, 0, sizeof(struct nvbios)); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 21ec561edc99..77326e344dad 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -48,9 +48,9 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, { struct nouveau_drm *drm = nouveau_drm(dev); int i = reg - drm->tile.reg; - struct nouveau_fb *pfb = nvkm_fb(&drm->device); - struct nouveau_fb_tile *tile = &pfb->tile.region[i]; - struct nouveau_engine *engine; + struct nvkm_fb *pfb = nvxx_fb(&drm->device); + struct nvkm_fb_tile *tile = &pfb->tile.region[i]; + struct nvkm_engine *engine; nouveau_fence_unref(®->fence); @@ -62,9 +62,9 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, pfb->tile.prog(pfb, i, tile); - if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR))) + if ((engine = nvkm_engine(pfb, NVDEV_ENGINE_GR))) engine->tile_prog(engine, i); - if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG))) + if ((engine = nvkm_engine(pfb, NVDEV_ENGINE_MPEG))) engine->tile_prog(engine, i); } @@ -105,7 +105,7 @@ nv10_bo_set_tiling(struct drm_device *dev, u32 addr, u32 size, u32 pitch, u32 flags) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_fb *pfb = nvkm_fb(&drm->device); + struct nvkm_fb *pfb = nvxx_fb(&drm->device); struct nouveau_drm_tile *tile, *found = NULL; int i; @@ -193,7 +193,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, int max_size; if (drm->client.vm) - lpg_shift = drm->client.vm->vmm->lpg_shift; + lpg_shift = drm->client.vm->mmu->lpg_shift; max_size = INT_MAX & ~((1 << lpg_shift) - 1); if (size <= 0 || size > max_size) { @@ -214,13 +214,13 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, nvbo->tile_flags = tile_flags; nvbo->bo.bdev = &drm->ttm.bdev; - if (!nv_device_is_cpu_coherent(nvkm_device(&drm->device))) + if (!nv_device_is_cpu_coherent(nvxx_device(&drm->device))) nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED; nvbo->page_shift = 12; if (drm->client.vm) { if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024) - nvbo->page_shift = drm->client.vm->vmm->lpg_shift; + nvbo->page_shift = drm->client.vm->mmu->lpg_shift; } nouveau_bo_fixup_align(nvbo, flags, &align, &size); @@ -325,7 +325,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) memtype == TTM_PL_FLAG_VRAM && contig) { if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) { if (bo->mem.mem_type == TTM_PL_VRAM) { - struct nouveau_mem *mem = bo->mem.mm_node; + struct nvkm_mem *mem = bo->mem.mm_node; if (!list_is_singular(&mem->regions)) evict = true; } @@ -459,7 +459,7 @@ void nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) { struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); - struct nouveau_device *device = nvkm_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->device); struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; int i; @@ -479,7 +479,7 @@ void nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) { struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); - struct nouveau_device *device = nvkm_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->device); struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; int i; @@ -533,20 +533,6 @@ _nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz) } #define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m)) -u16 -nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) -{ - bool is_iomem; - u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); - - mem = nouveau_bo_mem_index(nvbo, index, mem); - - if (is_iomem) - return ioread16_native((void __force __iomem *)mem); - else - return *mem; -} - void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) { @@ -634,7 +620,7 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { /* Some BARs do not support being ioremapped WC */ - if (nvkm_bar(&drm->device)->iomap_uncached) { + if (nvxx_bar(&drm->device)->iomap_uncached) { man->available_caching = TTM_PL_FLAG_UNCACHED; man->default_caching = TTM_PL_FLAG_UNCACHED; } @@ -709,7 +695,7 @@ static int nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) { - struct nouveau_mem *node = old_mem->mm_node; + struct nvkm_mem *node = old_mem->mm_node; int ret = RING_SPACE(chan, 10); if (ret == 0) { BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); @@ -741,7 +727,7 @@ static int nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) { - struct nouveau_mem *node = old_mem->mm_node; + struct nvkm_mem *node = old_mem->mm_node; u64 src_offset = node->vma[0].offset; u64 dst_offset = node->vma[1].offset; u32 page_count = new_mem->num_pages; @@ -779,7 +765,7 @@ static int nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) { - struct nouveau_mem *node = old_mem->mm_node; + struct nvkm_mem *node = old_mem->mm_node; u64 src_offset = node->vma[0].offset; u64 dst_offset = node->vma[1].offset; u32 page_count = new_mem->num_pages; @@ -818,7 +804,7 @@ static int nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) { - struct nouveau_mem *node = old_mem->mm_node; + struct nvkm_mem *node = old_mem->mm_node; u64 src_offset = node->vma[0].offset; u64 dst_offset = node->vma[1].offset; u32 page_count = new_mem->num_pages; @@ -856,7 +842,7 @@ static int nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) { - struct nouveau_mem *node = old_mem->mm_node; + struct nvkm_mem *node = old_mem->mm_node; int ret = RING_SPACE(chan, 7); if (ret == 0) { BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); @@ -874,7 +860,7 @@ static int nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) { - struct nouveau_mem *node = old_mem->mm_node; + struct nvkm_mem *node = old_mem->mm_node; int ret = RING_SPACE(chan, 7); if (ret == 0) { BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); @@ -908,12 +894,12 @@ static int nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) { - struct nouveau_mem *node = old_mem->mm_node; + struct nvkm_mem *node = old_mem->mm_node; u64 length = (new_mem->num_pages << PAGE_SHIFT); u64 src_offset = node->vma[0].offset; u64 dst_offset = node->vma[1].offset; int src_tiled = !!node->memtype; - int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype; + int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype; int ret; while (length) { @@ -1050,25 +1036,25 @@ static int nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, struct ttm_mem_reg *mem) { - struct nouveau_mem *old_node = bo->mem.mm_node; - struct nouveau_mem *new_node = mem->mm_node; + struct nvkm_mem *old_node = bo->mem.mm_node; + struct nvkm_mem *new_node = mem->mm_node; u64 size = (u64)mem->num_pages << PAGE_SHIFT; int ret; - ret = nouveau_vm_get(drm->client.vm, size, old_node->page_shift, - NV_MEM_ACCESS_RW, &old_node->vma[0]); + ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift, + NV_MEM_ACCESS_RW, &old_node->vma[0]); if (ret) return ret; - ret = nouveau_vm_get(drm->client.vm, size, new_node->page_shift, - NV_MEM_ACCESS_RW, &old_node->vma[1]); + ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift, + NV_MEM_ACCESS_RW, &old_node->vma[1]); if (ret) { - nouveau_vm_put(&old_node->vma[0]); + nvkm_vm_put(&old_node->vma[0]); return ret; } - nouveau_vm_map(&old_node->vma[0], old_node); - nouveau_vm_map(&old_node->vma[1], new_node); + nvkm_vm_map(&old_node->vma[0], old_node); + nvkm_vm_map(&old_node->vma[1], new_node); return 0; } @@ -1083,7 +1069,7 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, int ret; /* create temporary vmas for the transfer and attach them to the - * old nouveau_mem node, these will get cleaned up after ttm has + * old nvkm_mem node, these will get cleaned up after ttm has * destroyed the ttm_mem_reg */ if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { @@ -1245,7 +1231,7 @@ static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) { struct nouveau_bo *nvbo = nouveau_bo(bo); - struct nouveau_vma *vma; + struct nvkm_vma *vma; /* ttm can now (stupidly) pass the driver bos it didn't create... */ if (bo->destroy != nouveau_bo_del_ttm) @@ -1254,10 +1240,10 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) list_for_each_entry(vma, &nvbo->vma_list, head) { if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM && (new_mem->mem_type == TTM_PL_VRAM || - nvbo->page_shift != vma->vm->vmm->lpg_shift)) { - nouveau_vm_map(vma, new_mem->mm_node); + nvbo->page_shift != vma->vm->mmu->lpg_shift)) { + nvkm_vm_map(vma, new_mem->mm_node); } else { - nouveau_vm_unmap(vma); + nvkm_vm_unmap(vma); } } } @@ -1368,7 +1354,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) { struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; struct nouveau_drm *drm = nouveau_bdev(bdev); - struct nouveau_mem *node = mem->mm_node; + struct nvkm_mem *node = mem->mm_node; int ret; mem->bus.addr = NULL; @@ -1396,10 +1382,10 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) /* fallthrough, tiled memory */ case TTM_PL_VRAM: mem->bus.offset = mem->start << PAGE_SHIFT; - mem->bus.base = nv_device_resource_start(nvkm_device(&drm->device), 1); + mem->bus.base = nv_device_resource_start(nvxx_device(&drm->device), 1); mem->bus.is_iomem = true; if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { - struct nouveau_bar *bar = nvkm_bar(&drm->device); + struct nvkm_bar *bar = nvxx_bar(&drm->device); ret = bar->umap(bar, node, NV_MEM_ACCESS_RW, &node->bar_vma); @@ -1419,8 +1405,8 @@ static void nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) { struct nouveau_drm *drm = nouveau_bdev(bdev); - struct nouveau_bar *bar = nvkm_bar(&drm->device); - struct nouveau_mem *node = mem->mm_node; + struct nvkm_bar *bar = nvxx_bar(&drm->device); + struct nvkm_mem *node = mem->mm_node; if (!node->bar_vma.node) return; @@ -1434,7 +1420,7 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct nouveau_bo *nvbo = nouveau_bo(bo); struct nvif_device *device = &drm->device; - u32 mappable = nv_device_resource_len(nvkm_device(device), 1) >> PAGE_SHIFT; + u32 mappable = nv_device_resource_len(nvxx_device(device), 1) >> PAGE_SHIFT; int i, ret; /* as long as the bo isn't in vram, and isn't tiled, we've got @@ -1479,7 +1465,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) { struct ttm_dma_tt *ttm_dma = (void *)ttm; struct nouveau_drm *drm; - struct nouveau_device *device; + struct nvkm_device *device; struct drm_device *dev; struct device *pdev; unsigned i; @@ -1498,7 +1484,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) } drm = nouveau_bdev(ttm->bdev); - device = nvkm_device(&drm->device); + device = nvxx_device(&drm->device); dev = drm->dev; pdev = nv_device_base(device); @@ -1553,7 +1539,7 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) { struct ttm_dma_tt *ttm_dma = (void *)ttm; struct nouveau_drm *drm; - struct nouveau_device *device; + struct nvkm_device *device; struct drm_device *dev; struct device *pdev; unsigned i; @@ -1563,7 +1549,7 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) return; drm = nouveau_bdev(ttm->bdev); - device = nvkm_device(&drm->device); + device = nvxx_device(&drm->device); dev = drm->dev; pdev = nv_device_base(device); @@ -1572,8 +1558,10 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) * so use the DMA API for them. */ if (!nv_device_is_cpu_coherent(device) && - ttm->caching_state == tt_uncached) + ttm->caching_state == tt_uncached) { ttm_dma_unpopulate(ttm_dma, dev->dev); + return; + } #if __OS_HAS_AGP if (drm->agp.stat == ENABLED) { @@ -1625,10 +1613,10 @@ struct ttm_bo_driver nouveau_bo_driver = { .io_mem_free = &nouveau_ttm_io_mem_free, }; -struct nouveau_vma * -nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm) +struct nvkm_vma * +nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nvkm_vm *vm) { - struct nouveau_vma *vma; + struct nvkm_vma *vma; list_for_each_entry(vma, &nvbo->vma_list, head) { if (vma->vm == vm) return vma; @@ -1638,21 +1626,21 @@ nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm) } int -nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, - struct nouveau_vma *vma) +nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm, + struct nvkm_vma *vma) { const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT; int ret; - ret = nouveau_vm_get(vm, size, nvbo->page_shift, + ret = nvkm_vm_get(vm, size, nvbo->page_shift, NV_MEM_ACCESS_RW, vma); if (ret) return ret; if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM && (nvbo->bo.mem.mem_type == TTM_PL_VRAM || - nvbo->page_shift != vma->vm->vmm->lpg_shift)) - nouveau_vm_map(vma, nvbo->bo.mem.mm_node); + nvbo->page_shift != vma->vm->mmu->lpg_shift)) + nvkm_vm_map(vma, nvbo->bo.mem.mm_node); list_add_tail(&vma->head, &nvbo->vma_list); vma->refcount = 1; @@ -1660,12 +1648,12 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, } void -nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma) +nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nvkm_vma *vma) { if (vma->node) { if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) - nouveau_vm_unmap(vma); - nouveau_vm_put(vma); + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); list_del(&vma->head); } } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h index 072222efeeb7..e42360983229 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.h +++ b/drivers/gpu/drm/nouveau/nouveau_bo.h @@ -5,7 +5,7 @@ struct nouveau_channel; struct nouveau_fence; -struct nouveau_vma; +struct nvkm_vma; struct nouveau_bo { struct ttm_buffer_object bo; @@ -78,7 +78,6 @@ int nouveau_bo_unpin(struct nouveau_bo *); int nouveau_bo_map(struct nouveau_bo *); void nouveau_bo_unmap(struct nouveau_bo *); void nouveau_bo_placement_set(struct nouveau_bo *, u32 type, u32 busy); -u16 nouveau_bo_rd16(struct nouveau_bo *, unsigned index); void nouveau_bo_wr16(struct nouveau_bo *, unsigned index, u16 val); u32 nouveau_bo_rd32(struct nouveau_bo *, unsigned index); void nouveau_bo_wr32(struct nouveau_bo *, unsigned index, u32 val); @@ -88,12 +87,12 @@ int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, void nouveau_bo_sync_for_device(struct nouveau_bo *nvbo); void nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo); -struct nouveau_vma * -nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); +struct nvkm_vma * +nouveau_bo_vma_find(struct nouveau_bo *, struct nvkm_vm *); -int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, - struct nouveau_vma *); -void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); +int nouveau_bo_vma_add(struct nouveau_bo *, struct nvkm_vm *, + struct nvkm_vma *); +void nouveau_bo_vma_del(struct nouveau_bo *, struct nvkm_vma *); /* TODO: submit equivalent to TTM generic API upstream? */ static inline void __iomem * diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index aff9099aae6c..e581f63cbf25 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -54,7 +54,7 @@ nouveau_channel_idle(struct nouveau_channel *chan) if (ret) NV_PRINTK(error, cli, "failed to idle channel 0x%08x [%s]\n", - chan->object->handle, nvkm_client(&cli->base)->name); + chan->object->handle, nvxx_client(&cli->base)->name); return ret; } @@ -88,7 +88,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, u32 handle, u32 size, struct nouveau_channel **pchan) { struct nouveau_cli *cli = (void *)nvif_client(&device->base); - struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); + struct nvkm_mmu *mmu = nvxx_mmu(device); struct nv_dma_v0 args = {}; struct nouveau_channel *chan; u32 target; @@ -136,7 +136,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_VM; args.start = 0; - args.limit = cli->vm->vmm->limit - 1; + args.limit = cli->vm->mmu->limit - 1; } else if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { if (device->info.family == NV_DEVICE_INFO_V0_TNT) { @@ -146,7 +146,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, */ args.target = NV_DMA_V0_TARGET_PCI; args.access = NV_DMA_V0_ACCESS_RDWR; - args.start = nv_device_resource_start(nvkm_device(device), 1); + args.start = nv_device_resource_start(nvxx_device(device), 1); args.limit = args.start + device->info.ram_user - 1; } else { args.target = NV_DMA_V0_TARGET_VRAM; @@ -165,7 +165,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_RDWR; args.start = 0; - args.limit = vmm->limit - 1; + args.limit = mmu->limit - 1; } } @@ -281,8 +281,8 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) { struct nvif_device *device = chan->device; struct nouveau_cli *cli = (void *)nvif_client(&device->base); - struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); - struct nouveau_software_chan *swch; + struct nvkm_mmu *mmu = nvxx_mmu(device); + struct nvkm_sw_chan *swch; struct nv_dma_v0 args = {}; int ret, i; @@ -294,7 +294,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_VM; args.start = 0; - args.limit = cli->vm->vmm->limit - 1; + args.limit = cli->vm->mmu->limit - 1; } else { args.target = NV_DMA_V0_TARGET_VRAM; args.access = NV_DMA_V0_ACCESS_RDWR; @@ -312,7 +312,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_VM; args.start = 0; - args.limit = cli->vm->vmm->limit - 1; + args.limit = cli->vm->mmu->limit - 1; } else if (chan->drm->agp.stat == ENABLED) { args.target = NV_DMA_V0_TARGET_AGP; @@ -324,7 +324,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) args.target = NV_DMA_V0_TARGET_VM; args.access = NV_DMA_V0_ACCESS_RDWR; args.start = 0; - args.limit = vmm->limit - 1; + args.limit = mmu->limit - 1; } ret = nvif_object_init(chan->object, NULL, gart, @@ -372,7 +372,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) if (ret) return ret; - swch = (void *)nvkm_object(&chan->nvsw)->parent; + swch = (void *)nvxx_object(&chan->nvsw)->parent; swch->flip = nouveau_flip_complete; swch->flip_data = chan; diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h index 8309c24ee698..8b3640f69e4f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.h +++ b/drivers/gpu/drm/nouveau/nouveau_chan.h @@ -16,7 +16,7 @@ struct nouveau_channel { struct { struct nouveau_bo *buffer; - struct nouveau_vma vma; + struct nvkm_vma vma; struct nvif_object ctxdma; } push; diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index c8ac9482cf2e..db7095ae4ebb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -115,7 +115,7 @@ nouveau_connector_ddc_detect(struct drm_connector *connector) struct drm_device *dev = connector->dev; struct nouveau_connector *nv_connector = nouveau_connector(connector); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_gpio *gpio = nvkm_gpio(&drm->device); + struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); struct nouveau_encoder *nv_encoder; struct drm_encoder *encoder; int i, panel = -ENODEV; @@ -241,7 +241,7 @@ nouveau_connector_detect(struct drm_connector *connector, bool force) struct nouveau_connector *nv_connector = nouveau_connector(connector); struct nouveau_encoder *nv_encoder = NULL; struct nouveau_encoder *nv_partner; - struct nouveau_i2c_port *i2c; + struct nvkm_i2c_port *i2c; int type; int ret; enum drm_connector_status conn_status = connector_status_disconnected; @@ -458,6 +458,28 @@ nouveau_connector_set_property(struct drm_connector *connector, switch (value) { case DRM_MODE_SCALE_NONE: + /* We allow 'None' for EDID modes, even on a fixed + * panel (some exist with support for lower refresh + * rates, which people might want to use for power + * saving purposes). + * + * Non-EDID modes will force the use of GPU scaling + * to the native mode regardless of this setting. + */ + switch (nv_connector->type) { + case DCB_CONNECTOR_LVDS: + case DCB_CONNECTOR_LVDS_SPWG: + case DCB_CONNECTOR_eDP: + /* ... except prior to G80, where the code + * doesn't support such things. + */ + if (disp->disp.oclass < NV50_DISP) + return -EINVAL; + break; + default: + break; + } + break; case DRM_MODE_SCALE_FULLSCREEN: case DRM_MODE_SCALE_CENTER: case DRM_MODE_SCALE_ASPECT: @@ -466,11 +488,6 @@ nouveau_connector_set_property(struct drm_connector *connector, return -EINVAL; } - /* LVDS always needs gpu scaling */ - if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS && - value == DRM_MODE_SCALE_NONE) - return -EINVAL; - /* Changing between GPU and panel scaling requires a full * modeset */ @@ -655,15 +672,15 @@ nouveau_connector_scaler_modes_add(struct drm_connector *connector) while (mode->hdisplay) { if (mode->hdisplay <= native->hdisplay && - mode->vdisplay <= native->vdisplay) { + mode->vdisplay <= native->vdisplay && + (mode->hdisplay != native->hdisplay || + mode->vdisplay != native->vdisplay)) { m = drm_cvt_mode(dev, mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(native), false, false, false); if (!m) continue; - m->type |= DRM_MODE_TYPE_DRIVER; - drm_mode_probed_add(connector, m); modes++; } @@ -968,7 +985,7 @@ nouveau_connector_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) struct nouveau_connector *nv_connector = container_of(aux, typeof(*nv_connector), aux); struct nouveau_encoder *nv_encoder; - struct nouveau_i2c_port *port; + struct nvkm_i2c_port *port; int ret; nv_encoder = find_encoder(&nv_connector->base, DCB_OUTPUT_DP); @@ -979,13 +996,13 @@ nouveau_connector_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) if (msg->size == 0) return msg->size; - ret = nouveau_i2c(port)->acquire(port, 0); + ret = nvkm_i2c(port)->acquire(port, 0); if (ret) return ret; ret = port->func->aux(port, false, msg->request, msg->address, msg->buffer, msg->size); - nouveau_i2c(port)->release(port); + nvkm_i2c(port)->release(port); if (ret >= 0) { msg->reply = ret; return msg->size; @@ -1180,36 +1197,61 @@ nouveau_connector_create(struct drm_device *dev, int index) disp->color_vibrance_property, 150); + /* default scaling mode */ switch (nv_connector->type) { - case DCB_CONNECTOR_VGA: - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { - drm_object_attach_property(&connector->base, - dev->mode_config.scaling_mode_property, - nv_connector->scaling_mode); + case DCB_CONNECTOR_LVDS: + case DCB_CONNECTOR_LVDS_SPWG: + case DCB_CONNECTOR_eDP: + /* see note in nouveau_connector_set_property() */ + if (disp->disp.oclass < NV50_DISP) { + nv_connector->scaling_mode = DRM_MODE_SCALE_FULLSCREEN; + break; } - /* fall-through */ + nv_connector->scaling_mode = DRM_MODE_SCALE_NONE; + break; + default: + nv_connector->scaling_mode = DRM_MODE_SCALE_NONE; + break; + } + + /* scaling mode property */ + switch (nv_connector->type) { case DCB_CONNECTOR_TV_0: case DCB_CONNECTOR_TV_1: case DCB_CONNECTOR_TV_3: - nv_connector->scaling_mode = DRM_MODE_SCALE_NONE; break; + case DCB_CONNECTOR_VGA: + if (disp->disp.oclass < NV50_DISP) + break; /* can only scale on DFPs */ + /* fall-through */ default: - nv_connector->scaling_mode = DRM_MODE_SCALE_FULLSCREEN; + drm_object_attach_property(&connector->base, dev->mode_config. + scaling_mode_property, + nv_connector->scaling_mode); + break; + } - drm_object_attach_property(&connector->base, - dev->mode_config.scaling_mode_property, - nv_connector->scaling_mode); + /* dithering properties */ + switch (nv_connector->type) { + case DCB_CONNECTOR_TV_0: + case DCB_CONNECTOR_TV_1: + case DCB_CONNECTOR_TV_3: + case DCB_CONNECTOR_VGA: + break; + default: if (disp->dithering_mode) { - nv_connector->dithering_mode = DITHERING_MODE_AUTO; drm_object_attach_property(&connector->base, - disp->dithering_mode, - nv_connector->dithering_mode); + disp->dithering_mode, + nv_connector-> + dithering_mode); + nv_connector->dithering_mode = DITHERING_MODE_AUTO; } if (disp->dithering_depth) { - nv_connector->dithering_depth = DITHERING_DEPTH_AUTO; drm_object_attach_property(&connector->base, - disp->dithering_depth, - nv_connector->dithering_depth); + disp->dithering_depth, + nv_connector-> + dithering_depth); + nv_connector->dithering_depth = DITHERING_DEPTH_AUTO; } break; } diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h index 629a380c7085..7446ee66ea04 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.h +++ b/drivers/gpu/drm/nouveau/nouveau_connector.h @@ -33,7 +33,7 @@ #include <drm/drm_dp_helper.h> #include "nouveau_crtc.h" -struct nouveau_i2c_port; +struct nvkm_i2c_port; enum nouveau_underscan_type { UNDERSCAN_OFF, @@ -72,6 +72,7 @@ struct nouveau_connector { int dithering_mode; int dithering_depth; int scaling_mode; + bool scaling_full; enum nouveau_underscan_type underscan; u32 underscan_hborder; u32 underscan_vborder; diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index f8042433752b..860b0e2d4181 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -450,7 +450,7 @@ nouveau_display_create(struct drm_device *dev) drm_mode_create_dvi_i_properties(dev); dev->mode_config.funcs = &nouveau_mode_config_funcs; - dev->mode_config.fb_base = nv_device_resource_start(nvkm_device(&drm->device), 1); + dev->mode_config.fb_base = nv_device_resource_start(nvxx_device(&drm->device), 1); dev->mode_config.min_width = 0; dev->mode_config.min_height = 0; @@ -570,7 +570,8 @@ nouveau_display_suspend(struct drm_device *dev, bool runtime) list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); if (nv_crtc->cursor.nvbo) { - nouveau_bo_unmap(nv_crtc->cursor.nvbo); + if (nv_crtc->cursor.set_offset) + nouveau_bo_unmap(nv_crtc->cursor.nvbo); nouveau_bo_unpin(nv_crtc->cursor.nvbo); } } @@ -604,7 +605,7 @@ nouveau_display_resume(struct drm_device *dev, bool runtime) continue; ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, true); - if (!ret) + if (!ret && nv_crtc->cursor.set_offset) ret = nouveau_bo_map(nv_crtc->cursor.nvbo); if (ret) NV_ERROR(drm, "Could not pin/map cursor.\n"); @@ -637,7 +638,9 @@ nouveau_display_resume(struct drm_device *dev, bool runtime) if (!nv_crtc->cursor.nvbo) continue; - nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset); + + if (nv_crtc->cursor.set_offset) + nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset); nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x, nv_crtc->cursor_saved_y); } diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index be3d5947c6be..a6213e2425c5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -1,14 +1,14 @@ #ifndef __NOUVEAU_DISPLAY_H__ #define __NOUVEAU_DISPLAY_H__ -#include <subdev/vm.h> +#include <subdev/mmu.h> #include "nouveau_drm.h" struct nouveau_framebuffer { struct drm_framebuffer base; struct nouveau_bo *nvbo; - struct nouveau_vma vma; + struct nvkm_vma vma; u32 r_handle; u32 r_format; u32 r_pitch; diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c index 8508603cc8c3..6d9245aa81a6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/drivers/gpu/drm/nouveau/nouveau_dma.c @@ -84,7 +84,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, { struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base); struct nouveau_bo *pb = chan->push.buffer; - struct nouveau_vma *vma; + struct nvkm_vma *vma; int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; u64 offset; diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c index c5137cccce7d..c3ef30b3a5ec 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dp.c +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c @@ -31,7 +31,7 @@ #include "nouveau_crtc.h" static void -nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch, +nouveau_dp_probe_oui(struct drm_device *dev, struct nvkm_i2c_port *auxch, u8 *dpcd) { struct nouveau_drm *drm = nouveau_drm(dev); @@ -55,7 +55,7 @@ nouveau_dp_detect(struct nouveau_encoder *nv_encoder) { struct drm_device *dev = nv_encoder->base.base.dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_i2c_port *auxch; + struct nvkm_i2c_port *auxch; u8 *dpcd = nv_encoder->dp.dpcd; int ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 65910e3aed0c..8763deb5188b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -52,6 +52,7 @@ #include "nouveau_debugfs.h" #include "nouveau_usif.h" #include "nouveau_connector.h" +#include "nouveau_platform.h" MODULE_PARM_DESC(config, "option string to pass to driver core"); static char *nouveau_config; @@ -123,7 +124,7 @@ nouveau_cli_create(u64 name, const char *sname, static void nouveau_cli_destroy(struct nouveau_cli *cli) { - nouveau_vm_ref(NULL, &nvkm_client(&cli->base)->vm, NULL); + nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL); nvif_client_fini(&cli->base); usif_client_fini(cli); } @@ -133,7 +134,7 @@ nouveau_accel_fini(struct nouveau_drm *drm) { nouveau_channel_del(&drm->channel); nvif_object_fini(&drm->ntfy); - nouveau_gpuobj_ref(NULL, &drm->notify); + nvkm_gpuobj_ref(NULL, &drm->notify); nvif_object_fini(&drm->nvsw); nouveau_channel_del(&drm->cechan); nvif_object_fini(&drm->ttm.copy); @@ -230,7 +231,7 @@ nouveau_accel_init(struct nouveau_drm *drm) ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW, nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw); if (ret == 0) { - struct nouveau_software_chan *swch; + struct nvkm_sw_chan *swch; ret = RING_SPACE(drm->channel, 2); if (ret == 0) { if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { @@ -242,7 +243,7 @@ nouveau_accel_init(struct nouveau_drm *drm) OUT_RING (drm->channel, 0x001f0000); } } - swch = (void *)nvkm_object(&drm->nvsw)->parent; + swch = (void *)nvxx_object(&drm->nvsw)->parent; swch->flip = nouveau_flip_complete; swch->flip_data = drm->channel; } @@ -254,8 +255,8 @@ nouveau_accel_init(struct nouveau_drm *drm) } if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { - ret = nouveau_gpuobj_new(nvkm_object(&drm->device), NULL, 32, - 0, 0, &drm->notify); + ret = nvkm_gpuobj_new(nvxx_object(&drm->device), NULL, 32, + 0, 0, &drm->notify); if (ret) { NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); nouveau_accel_fini(drm); @@ -284,7 +285,7 @@ nouveau_accel_init(struct nouveau_drm *drm) static int nouveau_drm_probe(struct pci_dev *pdev, const struct pci_device_id *pent) { - struct nouveau_device *device; + struct nvkm_device *device; struct apertures_struct *aper; bool boot = false; int ret; @@ -317,9 +318,9 @@ static int nouveau_drm_probe(struct pci_dev *pdev, remove_conflicting_framebuffers(aper, "nouveaufb", boot); kfree(aper); - ret = nouveau_device_create(pdev, NOUVEAU_BUS_PCI, - nouveau_pci_name(pdev), pci_name(pdev), - nouveau_config, nouveau_debug, &device); + ret = nvkm_device_create(pdev, NVKM_BUS_PCI, + nouveau_pci_name(pdev), pci_name(pdev), + nouveau_config, nouveau_debug, &device); if (ret) return ret; @@ -327,7 +328,7 @@ static int nouveau_drm_probe(struct pci_dev *pdev, ret = drm_get_pci_dev(pdev, pent, &driver_pci); if (ret) { - nouveau_object_ref(NULL, (struct nouveau_object **)&device); + nvkm_object_ref(NULL, (struct nvkm_object **)&device); return ret; } @@ -378,8 +379,8 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags) dev->dev_private = drm; drm->dev = dev; - nvkm_client(&drm->client.base)->debug = - nouveau_dbgopt(nouveau_debug, "DRM"); + nvxx_client(&drm->client.base)->debug = + nvkm_dbgopt(nouveau_debug, "DRM"); INIT_LIST_HEAD(&drm->clients); spin_lock_init(&drm->tile.lock); @@ -434,12 +435,12 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags) nouveau_agp_init(drm); if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { - ret = nouveau_vm_new(nvkm_device(&drm->device), 0, (1ULL << 40), - 0x1000, &drm->client.vm); + ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40), + 0x1000, &drm->client.vm); if (ret) goto fail_device; - nvkm_client(&drm->client.base)->vm = drm->client.vm; + nvxx_client(&drm->client.base)->vm = drm->client.vm; } ret = nouveau_ttm_init(drm); @@ -522,18 +523,17 @@ void nouveau_drm_device_remove(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_client *client; - struct nouveau_object *device; + struct nvkm_client *client; + struct nvkm_object *device; dev->irq_enabled = false; - client = nvkm_client(&drm->client.base); + client = nvxx_client(&drm->client.base); device = client->device; drm_put_dev(dev); - nouveau_object_ref(NULL, &device); - nouveau_object_debug(); + nvkm_object_ref(NULL, &device); + nvkm_object_debug(); } -EXPORT_SYMBOL(nouveau_drm_device_remove); static void nouveau_drm_remove(struct pci_dev *pdev) @@ -831,14 +831,14 @@ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) cli->base.super = false; if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { - ret = nouveau_vm_new(nvkm_device(&drm->device), 0, (1ULL << 40), - 0x1000, &cli->vm); + ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40), + 0x1000, &cli->vm); if (ret) { nouveau_cli_destroy(cli); goto out_suspend; } - nvkm_client(&cli->base)->vm = cli->vm; + nvxx_client(&cli->base)->vm = cli->vm; } fpriv->driver_priv = cli; @@ -1056,10 +1056,10 @@ nouveau_platform_device_create_(struct platform_device *pdev, int size, struct drm_device *drm; int err; - err = nouveau_device_create_(pdev, NOUVEAU_BUS_PLATFORM, - nouveau_platform_name(pdev), - dev_name(&pdev->dev), nouveau_config, - nouveau_debug, size, pobject); + err = nvkm_device_create_(pdev, NVKM_BUS_PLATFORM, + nouveau_platform_name(pdev), + dev_name(&pdev->dev), nouveau_config, + nouveau_debug, size, pobject); if (err) return ERR_PTR(err); @@ -1079,11 +1079,10 @@ nouveau_platform_device_create_(struct platform_device *pdev, int size, return drm; err_free: - nouveau_object_ref(NULL, (struct nouveau_object **)pobject); + nvkm_object_ref(NULL, (struct nvkm_object **)pobject); return ERR_PTR(err); } -EXPORT_SYMBOL(nouveau_platform_device_create_); static int __init nouveau_drm_init(void) @@ -1105,6 +1104,10 @@ nouveau_drm_init(void) if (!nouveau_modeset) return 0; +#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER + platform_driver_register(&nouveau_platform_driver); +#endif + nouveau_register_dsm_handler(); return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver); } @@ -1117,6 +1120,10 @@ nouveau_drm_exit(void) drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver); nouveau_unregister_dsm_handler(); + +#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER + platform_driver_unregister(&nouveau_platform_driver); +#endif } module_init(nouveau_drm_init); diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h index 8ae36f265fb8..fc68f0973f9e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.h +++ b/drivers/gpu/drm/nouveau/nouveau_drm.h @@ -80,7 +80,7 @@ enum nouveau_drm_handle { struct nouveau_cli { struct nvif_client base; - struct nouveau_vm *vm; /*XXX*/ + struct nvkm_vm *vm; /*XXX*/ struct list_head head; struct mutex mutex; void *abi16; @@ -142,7 +142,7 @@ struct nouveau_drm { /* context for accelerated drm-internal operations */ struct nouveau_channel *cechan; struct nouveau_channel *channel; - struct nouveau_gpuobj *notify; + struct nvkm_gpuobj *notify; struct nouveau_fbdev *fbcon; struct nvif_object nvsw; struct nvif_object ntfy; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index 5f0e37fc2849..c57a37e8e1eb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h @@ -34,14 +34,14 @@ #define NV_DPMS_CLEARED 0x80 -struct nouveau_i2c_port; +struct nvkm_i2c_port; struct nouveau_encoder { struct drm_encoder_slave base; struct dcb_output *dcb; int or; - struct nouveau_i2c_port *i2c; + struct nvkm_i2c_port *i2c; /* different to drm_encoder.crtc, this reflects what's * actually programmed on the hw, not the proposed crtc */ diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 5a7705dcd67e..79924e4b1b49 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -370,6 +370,7 @@ nouveau_fbcon_create(struct drm_fb_helper *helper, ret = -ENOMEM; goto out_unlock; } + info->skip_vt_switch = 1; ret = fb_alloc_cmap(&info->cmap, 256, 0); if (ret) { @@ -487,30 +488,17 @@ static const struct drm_fb_helper_funcs nouveau_fbcon_helper_funcs = { .fb_probe = nouveau_fbcon_create, }; -static void -nouveau_fbcon_set_suspend_work(struct work_struct *work) -{ - struct nouveau_fbdev *fbcon = container_of(work, typeof(*fbcon), work); - console_lock(); - nouveau_fbcon_accel_restore(fbcon->dev); - nouveau_fbcon_zfill(fbcon->dev, fbcon); - fb_set_suspend(fbcon->helper.fbdev, FBINFO_STATE_RUNNING); - console_unlock(); -} - void nouveau_fbcon_set_suspend(struct drm_device *dev, int state) { struct nouveau_drm *drm = nouveau_drm(dev); if (drm->fbcon) { - if (state == FBINFO_STATE_RUNNING) { - schedule_work(&drm->fbcon->work); - return; - } - flush_work(&drm->fbcon->work); console_lock(); + if (state == FBINFO_STATE_RUNNING) + nouveau_fbcon_accel_restore(dev); fb_set_suspend(drm->fbcon->helper.fbdev, state); - nouveau_fbcon_accel_save_disable(dev); + if (state != FBINFO_STATE_RUNNING) + nouveau_fbcon_accel_save_disable(dev); console_unlock(); } } @@ -531,7 +519,6 @@ nouveau_fbcon_init(struct drm_device *dev) if (!fbcon) return -ENOMEM; - INIT_WORK(&fbcon->work, nouveau_fbcon_set_suspend_work); fbcon->dev = dev; drm->fbcon = fbcon; diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h index 6208e70e4a1c..1e2e9e27a03b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h @@ -36,7 +36,6 @@ struct nouveau_fbdev { struct nouveau_framebuffer nouveau_fb; struct list_head fbdev_list; struct drm_device *dev; - struct work_struct work; unsigned int saved_flags; struct nvif_object surf2d; struct nvif_object clip; diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index f32a434724e3..c6d56bef5823 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -182,7 +182,7 @@ nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_cha else if (chan == chan->drm->channel) strcpy(fctx->name, "generic kernel channel"); else - strcpy(fctx->name, nvkm_client(&cli->base)->name); + strcpy(fctx->name, nvxx_client(&cli->base)->name); kref_init(&fctx->fence_ref); if (!priv->uevent) diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h index 96e461c6f68f..d9241d8247fb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.h +++ b/drivers/gpu/drm/nouveau/nouveau_fence.h @@ -89,9 +89,9 @@ int nouveau_flip_complete(void *chan); struct nv84_fence_chan { struct nouveau_fence_chan base; - struct nouveau_vma vma; - struct nouveau_vma vma_gart; - struct nouveau_vma dispc_vma[4]; + struct nvkm_vma vma; + struct nvkm_vma vma_gart; + struct nvkm_vma dispc_vma[4]; }; struct nv84_fence_priv { diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 42c34babc2e5..7c077fced1d1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -36,7 +36,14 @@ void nouveau_gem_object_del(struct drm_gem_object *gem) { struct nouveau_bo *nvbo = nouveau_gem_object(gem); + struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); struct ttm_buffer_object *bo = &nvbo->bo; + struct device *dev = drm->dev->dev; + int ret; + + ret = pm_runtime_get_sync(dev); + if (WARN_ON(ret < 0 && ret != -EACCES)) + return; if (gem->import_attach) drm_prime_gem_destroy(gem, nvbo->bo.sg); @@ -46,6 +53,9 @@ nouveau_gem_object_del(struct drm_gem_object *gem) /* reset filp so nouveau_bo_del_ttm() can test for it */ gem->filp = NULL; ttm_bo_unref(&bo); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); } int @@ -53,7 +63,9 @@ nouveau_gem_object_open(struct drm_gem_object *gem, struct drm_file *file_priv) { struct nouveau_cli *cli = nouveau_cli(file_priv); struct nouveau_bo *nvbo = nouveau_gem_object(gem); - struct nouveau_vma *vma; + struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); + struct nvkm_vma *vma; + struct device *dev = drm->dev->dev; int ret; if (!cli->vm) @@ -71,11 +83,16 @@ nouveau_gem_object_open(struct drm_gem_object *gem, struct drm_file *file_priv) goto out; } + ret = pm_runtime_get_sync(dev); + if (ret < 0 && ret != -EACCES) + goto out; + ret = nouveau_bo_vma_add(nvbo, cli->vm, vma); - if (ret) { + if (ret) kfree(vma); - goto out; - } + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); } else { vma->refcount++; } @@ -88,14 +105,14 @@ out: static void nouveau_gem_object_delete(void *data) { - struct nouveau_vma *vma = data; - nouveau_vm_unmap(vma); - nouveau_vm_put(vma); + struct nvkm_vma *vma = data; + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); kfree(vma); } static void -nouveau_gem_object_unmap(struct nouveau_bo *nvbo, struct nouveau_vma *vma) +nouveau_gem_object_unmap(struct nouveau_bo *nvbo, struct nvkm_vma *vma) { const bool mapped = nvbo->bo.mem.mem_type != TTM_PL_SYSTEM; struct reservation_object *resv = nvbo->bo.resv; @@ -118,8 +135,8 @@ nouveau_gem_object_unmap(struct nouveau_bo *nvbo, struct nouveau_vma *vma) nouveau_fence_work(fence, nouveau_gem_object_delete, vma); } else { if (mapped) - nouveau_vm_unmap(vma); - nouveau_vm_put(vma); + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); kfree(vma); } } @@ -129,7 +146,9 @@ nouveau_gem_object_close(struct drm_gem_object *gem, struct drm_file *file_priv) { struct nouveau_cli *cli = nouveau_cli(file_priv); struct nouveau_bo *nvbo = nouveau_gem_object(gem); - struct nouveau_vma *vma; + struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); + struct device *dev = drm->dev->dev; + struct nvkm_vma *vma; int ret; if (!cli->vm) @@ -141,8 +160,14 @@ nouveau_gem_object_close(struct drm_gem_object *gem, struct drm_file *file_priv) vma = nouveau_bo_vma_find(nvbo, cli->vm); if (vma) { - if (--vma->refcount == 0) - nouveau_gem_object_unmap(nvbo, vma); + if (--vma->refcount == 0) { + ret = pm_runtime_get_sync(dev); + if (!WARN_ON(ret < 0 && ret != -EACCES)) { + nouveau_gem_object_unmap(nvbo, vma); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + } + } } ttm_bo_unreserve(&nvbo->bo); } @@ -197,7 +222,7 @@ nouveau_gem_info(struct drm_file *file_priv, struct drm_gem_object *gem, { struct nouveau_cli *cli = nouveau_cli(file_priv); struct nouveau_bo *nvbo = nouveau_gem_object(gem); - struct nouveau_vma *vma; + struct nvkm_vma *vma; if (nvbo->bo.mem.mem_type == TTM_PL_TT) rep->domain = NOUVEAU_GEM_DOMAIN_GART; @@ -226,7 +251,7 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data, { struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_cli *cli = nouveau_cli(file_priv); - struct nouveau_fb *pfb = nvkm_fb(&drm->device); + struct nvkm_fb *pfb = nvxx_fb(&drm->device); struct drm_nouveau_gem_new *req = data; struct nouveau_bo *nvbo = NULL; int ret = 0; @@ -825,19 +850,6 @@ out_next: return nouveau_abi16_put(abi16, ret); } -static inline uint32_t -domain_to_ttm(struct nouveau_bo *nvbo, uint32_t domain) -{ - uint32_t flags = 0; - - if (domain & NOUVEAU_GEM_DOMAIN_VRAM) - flags |= TTM_PL_FLAG_VRAM; - if (domain & NOUVEAU_GEM_DOMAIN_GART) - flags |= TTM_PL_FLAG_TT; - - return flags; -} - int nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data, struct drm_file *file_priv) diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c index afb36d66e78d..0dbe0060f86e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c +++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c @@ -40,7 +40,7 @@ nouveau_hwmon_show_temp(struct device *d, struct device_attribute *a, char *buf) { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); int temp = therm->temp_get(therm); if (temp < 0) @@ -66,10 +66,10 @@ nouveau_hwmon_temp1_auto_point1_temp(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); return snprintf(buf, PAGE_SIZE, "%d\n", - therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST) * 1000); + therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST) * 1000); } static ssize_t nouveau_hwmon_set_temp1_auto_point1_temp(struct device *d, @@ -78,13 +78,13 @@ nouveau_hwmon_set_temp1_auto_point1_temp(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) return count; - therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST, + therm->attr_set(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST, value / 1000); return count; @@ -99,10 +99,10 @@ nouveau_hwmon_temp1_auto_point1_temp_hyst(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); return snprintf(buf, PAGE_SIZE, "%d\n", - therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST) * 1000); + therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST) * 1000); } static ssize_t nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device *d, @@ -111,13 +111,13 @@ nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) return count; - therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST, + therm->attr_set(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST, value / 1000); return count; @@ -131,10 +131,10 @@ nouveau_hwmon_max_temp(struct device *d, struct device_attribute *a, char *buf) { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); return snprintf(buf, PAGE_SIZE, "%d\n", - therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK) * 1000); + therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK) * 1000); } static ssize_t nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a, @@ -142,13 +142,13 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) return count; - therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK, value / 1000); + therm->attr_set(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK, value / 1000); return count; } @@ -162,10 +162,10 @@ nouveau_hwmon_max_temp_hyst(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); return snprintf(buf, PAGE_SIZE, "%d\n", - therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST) * 1000); + therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST) * 1000); } static ssize_t nouveau_hwmon_set_max_temp_hyst(struct device *d, struct device_attribute *a, @@ -173,13 +173,13 @@ nouveau_hwmon_set_max_temp_hyst(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) return count; - therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST, + therm->attr_set(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST, value / 1000); return count; @@ -194,10 +194,10 @@ nouveau_hwmon_critical_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); return snprintf(buf, PAGE_SIZE, "%d\n", - therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL) * 1000); + therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL) * 1000); } static ssize_t nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a, @@ -206,13 +206,13 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) return count; - therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL, value / 1000); + therm->attr_set(therm, NVKM_THERM_ATTR_THRS_CRITICAL, value / 1000); return count; } @@ -227,10 +227,10 @@ nouveau_hwmon_critical_temp_hyst(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); return snprintf(buf, PAGE_SIZE, "%d\n", - therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST) * 1000); + therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST) * 1000); } static ssize_t nouveau_hwmon_set_critical_temp_hyst(struct device *d, @@ -240,13 +240,13 @@ nouveau_hwmon_set_critical_temp_hyst(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) return count; - therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST, + therm->attr_set(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST, value / 1000); return count; @@ -260,10 +260,10 @@ nouveau_hwmon_emergency_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); return snprintf(buf, PAGE_SIZE, "%d\n", - therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN) * 1000); + therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN) * 1000); } static ssize_t nouveau_hwmon_set_emergency_temp(struct device *d, struct device_attribute *a, @@ -272,13 +272,13 @@ nouveau_hwmon_set_emergency_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) return count; - therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN, value / 1000); + therm->attr_set(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN, value / 1000); return count; } @@ -293,10 +293,10 @@ nouveau_hwmon_emergency_temp_hyst(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); return snprintf(buf, PAGE_SIZE, "%d\n", - therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST) * 1000); + therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST) * 1000); } static ssize_t nouveau_hwmon_set_emergency_temp_hyst(struct device *d, @@ -306,13 +306,13 @@ nouveau_hwmon_set_emergency_temp_hyst(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) return count; - therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST, + therm->attr_set(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST, value / 1000); return count; @@ -346,7 +346,7 @@ nouveau_hwmon_show_fan1_input(struct device *d, struct device_attribute *attr, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); return snprintf(buf, PAGE_SIZE, "%d\n", therm->fan_sense(therm)); } @@ -359,10 +359,10 @@ nouveau_hwmon_get_pwm1_enable(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); int ret; - ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MODE); + ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MODE); if (ret < 0) return ret; @@ -375,7 +375,7 @@ nouveau_hwmon_set_pwm1_enable(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; int ret; @@ -383,7 +383,7 @@ nouveau_hwmon_set_pwm1_enable(struct device *d, struct device_attribute *a, if (ret) return ret; - ret = therm->attr_set(therm, NOUVEAU_THERM_ATTR_FAN_MODE, value); + ret = therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MODE, value); if (ret) return ret; else @@ -398,7 +398,7 @@ nouveau_hwmon_get_pwm1(struct device *d, struct device_attribute *a, char *buf) { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); int ret; ret = therm->fan_get(therm); @@ -414,7 +414,7 @@ nouveau_hwmon_set_pwm1(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); int ret = -ENODEV; long value; @@ -438,10 +438,10 @@ nouveau_hwmon_get_pwm1_min(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); int ret; - ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MIN_DUTY); + ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MIN_DUTY); if (ret < 0) return ret; @@ -454,14 +454,14 @@ nouveau_hwmon_set_pwm1_min(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; int ret; if (kstrtol(buf, 10, &value) == -EINVAL) return -EINVAL; - ret = therm->attr_set(therm, NOUVEAU_THERM_ATTR_FAN_MIN_DUTY, value); + ret = therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MIN_DUTY, value); if (ret < 0) return ret; @@ -478,10 +478,10 @@ nouveau_hwmon_get_pwm1_max(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); int ret; - ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MAX_DUTY); + ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MAX_DUTY); if (ret < 0) return ret; @@ -494,14 +494,14 @@ nouveau_hwmon_set_pwm1_max(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); long value; int ret; if (kstrtol(buf, 10, &value) == -EINVAL) return -EINVAL; - ret = therm->attr_set(therm, NOUVEAU_THERM_ATTR_FAN_MAX_DUTY, value); + ret = therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MAX_DUTY, value); if (ret < 0) return ret; @@ -561,7 +561,7 @@ nouveau_hwmon_init(struct drm_device *dev) { #if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nvkm_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->device); struct nouveau_hwmon *hwmon; struct device *hwmon_dev; int ret = 0; diff --git a/drivers/gpu/drm/nouveau/nouveau_nvif.c b/drivers/gpu/drm/nouveau/nouveau_nvif.c index 6544b84f0303..ca0ad9d1563d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_nvif.c +++ b/drivers/gpu/drm/nouveau/nouveau_nvif.c @@ -60,22 +60,22 @@ nvkm_client_ioctl(void *priv, bool super, void *data, u32 size, void **hack) static int nvkm_client_resume(void *priv) { - return nouveau_client_init(priv); + return nvkm_client_init(priv); } static int nvkm_client_suspend(void *priv) { - return nouveau_client_fini(priv, true); + return nvkm_client_fini(priv, true); } static void -nvkm_client_fini(void *priv) +nvkm_client_driver_fini(void *priv) { - struct nouveau_object *client = priv; - nouveau_client_fini(nv_client(client), false); + struct nvkm_object *client = priv; + nvkm_client_fini(nv_client(client), false); atomic_set(&client->refcount, 1); - nouveau_object_ref(NULL, &client); + nvkm_object_ref(NULL, &client); } static int @@ -107,13 +107,13 @@ nvkm_client_ntfy(const void *header, u32 length, const void *data, u32 size) } static int -nvkm_client_init(const char *name, u64 device, const char *cfg, - const char *dbg, void **ppriv) +nvkm_client_driver_init(const char *name, u64 device, const char *cfg, + const char *dbg, void **ppriv) { - struct nouveau_client *client; + struct nvkm_client *client; int ret; - ret = nouveau_client_create(name, device, cfg, dbg, &client); + ret = nvkm_client_create(name, device, cfg, dbg, &client); *ppriv = client; if (ret) return ret; @@ -125,8 +125,8 @@ nvkm_client_init(const char *name, u64 device, const char *cfg, const struct nvif_driver nvif_driver_nvkm = { .name = "nvkm", - .init = nvkm_client_init, - .fini = nvkm_client_fini, + .init = nvkm_client_driver_init, + .fini = nvkm_client_driver_fini, .suspend = nvkm_client_suspend, .resume = nvkm_client_resume, .ioctl = nvkm_client_ioctl, diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c index b307bbedd4c4..dc5900bf54ff 100644 --- a/drivers/gpu/drm/nouveau/nouveau_platform.c +++ b/drivers/gpu/drm/nouveau/nouveau_platform.c @@ -152,7 +152,7 @@ static int nouveau_platform_remove(struct platform_device *pdev) { struct drm_device *drm_dev = platform_get_drvdata(pdev); struct nouveau_drm *drm = nouveau_drm(drm_dev); - struct nouveau_device *device = nvkm_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->device); struct nouveau_platform_gpu *gpu = nv_device_to_platform(device)->gpu; nouveau_drm_device_remove(drm_dev); @@ -177,9 +177,3 @@ struct platform_driver nouveau_platform_driver = { .probe = nouveau_platform_probe, .remove = nouveau_platform_remove, }; - -module_platform_driver(nouveau_platform_driver); - -MODULE_AUTHOR(DRIVER_AUTHOR); -MODULE_DESCRIPTION(DRIVER_DESC); -MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.h b/drivers/gpu/drm/nouveau/nouveau_platform.h index 58c28b5653d5..268bb7213681 100644 --- a/drivers/gpu/drm/nouveau/nouveau_platform.h +++ b/drivers/gpu/drm/nouveau/nouveau_platform.h @@ -28,6 +28,7 @@ struct reset_control; struct clk; struct regulator; +struct platform_driver; struct nouveau_platform_gpu { struct reset_control *rst; @@ -38,7 +39,7 @@ struct nouveau_platform_gpu { }; struct nouveau_platform_device { - struct nouveau_device device; + struct nvkm_device device; struct nouveau_platform_gpu *gpu; @@ -48,4 +49,6 @@ struct nouveau_platform_device { #define nv_device_to_platform(d) \ container_of(d, struct nouveau_platform_device, device) +extern struct platform_driver nouveau_platform_driver; + #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h index 43a96b99e180..7226f1f60901 100644 --- a/drivers/gpu/drm/nouveau/nouveau_reg.h +++ b/drivers/gpu/drm/nouveau/nouveau_reg.h @@ -72,7 +72,7 @@ # define NV_RAMHT_CONTEXT_VALID (1<<31) # define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24 # define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16 -# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0 +# define NV_RAMHT_CONTEXT_ENGINE_SW 0 # define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1 # define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0 # define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23 diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index 01707e7deaf5..8c3053a177d6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c @@ -9,8 +9,7 @@ struct nouveau_sgdma_be { * nouve_bo.c works properly, otherwise have to move them here */ struct ttm_dma_tt ttm; - struct drm_device *dev; - struct nouveau_mem *node; + struct nvkm_mem *node; }; static void @@ -28,7 +27,7 @@ static int nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) { struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; - struct nouveau_mem *node = mem->mm_node; + struct nvkm_mem *node = mem->mm_node; if (ttm->sg) { node->sg = ttm->sg; @@ -39,7 +38,7 @@ nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) } node->size = (mem->num_pages << PAGE_SHIFT) >> 12; - nouveau_vm_map(&node->vma[0], node); + nvkm_vm_map(&node->vma[0], node); nvbe->node = node; return 0; } @@ -48,7 +47,7 @@ static int nv04_sgdma_unbind(struct ttm_tt *ttm) { struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; - nouveau_vm_unmap(&nvbe->node->vma[0]); + nvkm_vm_unmap(&nvbe->node->vma[0]); return 0; } @@ -62,7 +61,7 @@ static int nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) { struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; - struct nouveau_mem *node = mem->mm_node; + struct nvkm_mem *node = mem->mm_node; /* noop: bound in move_notify() */ if (ttm->sg) { @@ -101,13 +100,17 @@ nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, if (!nvbe) return NULL; - nvbe->dev = drm->dev; if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) nvbe->ttm.ttm.func = &nv04_sgdma_backend; else nvbe->ttm.ttm.func = &nv50_sgdma_backend; if (ttm_dma_tt_init(&nvbe->ttm, bdev, size, page_flags, dummy_read_page)) + /* + * A failing ttm_dma_tt_init() will call ttm_tt_destroy() + * and thus our nouveau_sgdma_destroy() hook, so we don't need + * to free nvbe here. + */ return NULL; return &nvbe->ttm.ttm; } diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.c b/drivers/gpu/drm/nouveau/nouveau_sysfs.c index 8fbbf3093d86..1ec8f38ae69a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sysfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_sysfs.c @@ -165,7 +165,7 @@ nouveau_sysfs_fini(struct drm_device *dev) struct nvif_device *device = &drm->device; if (sysfs && sysfs->ctrl.priv) { - device_remove_file(nv_device_base(nvkm_device(device)), &dev_attr_pstate); + device_remove_file(nv_device_base(nvxx_device(device)), &dev_attr_pstate); nvif_object_fini(&sysfs->ctrl); } @@ -192,7 +192,7 @@ nouveau_sysfs_init(struct drm_device *dev) NVIF_IOCTL_NEW_V0_CONTROL, NULL, 0, &sysfs->ctrl); if (ret == 0) - device_create_file(nv_device_base(nvkm_device(device)), &dev_attr_pstate); + device_create_file(nv_device_base(nvxx_device(device)), &dev_attr_pstate); return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 3d1cfcb96b6b..273e50110ec3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -33,7 +33,7 @@ static int nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nouveau_fb *pfb = nvkm_fb(&drm->device); + struct nvkm_fb *pfb = nvxx_fb(&drm->device); man->priv = pfb; return 0; } @@ -46,16 +46,16 @@ nouveau_vram_manager_fini(struct ttm_mem_type_manager *man) } static inline void -nouveau_mem_node_cleanup(struct nouveau_mem *node) +nvkm_mem_node_cleanup(struct nvkm_mem *node) { if (node->vma[0].node) { - nouveau_vm_unmap(&node->vma[0]); - nouveau_vm_put(&node->vma[0]); + nvkm_vm_unmap(&node->vma[0]); + nvkm_vm_put(&node->vma[0]); } if (node->vma[1].node) { - nouveau_vm_unmap(&node->vma[1]); - nouveau_vm_put(&node->vma[1]); + nvkm_vm_unmap(&node->vma[1]); + nvkm_vm_put(&node->vma[1]); } } @@ -64,9 +64,9 @@ nouveau_vram_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nouveau_fb *pfb = nvkm_fb(&drm->device); - nouveau_mem_node_cleanup(mem->mm_node); - pfb->ram->put(pfb, (struct nouveau_mem **)&mem->mm_node); + struct nvkm_fb *pfb = nvxx_fb(&drm->device); + nvkm_mem_node_cleanup(mem->mm_node); + pfb->ram->put(pfb, (struct nvkm_mem **)&mem->mm_node); } static int @@ -76,9 +76,9 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nouveau_fb *pfb = nvkm_fb(&drm->device); + struct nvkm_fb *pfb = nvxx_fb(&drm->device); struct nouveau_bo *nvbo = nouveau_bo(bo); - struct nouveau_mem *node; + struct nvkm_mem *node; u32 size_nc = 0; int ret; @@ -103,9 +103,9 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, static void nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) { - struct nouveau_fb *pfb = man->priv; - struct nouveau_mm *mm = &pfb->vram; - struct nouveau_mm_node *r; + struct nvkm_fb *pfb = man->priv; + struct nvkm_mm *mm = &pfb->vram; + struct nvkm_mm_node *r; u32 total = 0, free = 0; mutex_lock(&nv_subdev(pfb)->mutex); @@ -150,7 +150,7 @@ static void nouveau_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { - nouveau_mem_node_cleanup(mem->mm_node); + nvkm_mem_node_cleanup(mem->mm_node); kfree(mem->mm_node); mem->mm_node = NULL; } @@ -163,7 +163,7 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man, { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct nouveau_bo *nvbo = nouveau_bo(bo); - struct nouveau_mem *node; + struct nvkm_mem *node; node = kzalloc(sizeof(*node), GFP_KERNEL); if (!node) @@ -203,15 +203,15 @@ const struct ttm_mem_type_manager_func nouveau_gart_manager = { }; /*XXX*/ -#include <core/subdev/vm/nv04.h> +#include <subdev/mmu/nv04.h> static int nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nouveau_vmmgr *vmm = nvkm_vmmgr(&drm->device); - struct nv04_vmmgr_priv *priv = (void *)vmm; - struct nouveau_vm *vm = NULL; - nouveau_vm_ref(priv->vm, &vm, NULL); + struct nvkm_mmu *mmu = nvxx_mmu(&drm->device); + struct nv04_mmu_priv *priv = (void *)mmu; + struct nvkm_vm *vm = NULL; + nvkm_vm_ref(priv->vm, &vm, NULL); man->priv = vm; return 0; } @@ -219,8 +219,8 @@ nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) static int nv04_gart_manager_fini(struct ttm_mem_type_manager *man) { - struct nouveau_vm *vm = man->priv; - nouveau_vm_ref(NULL, &vm, NULL); + struct nvkm_vm *vm = man->priv; + nvkm_vm_ref(NULL, &vm, NULL); man->priv = NULL; return 0; } @@ -228,9 +228,9 @@ nv04_gart_manager_fini(struct ttm_mem_type_manager *man) static void nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { - struct nouveau_mem *node = mem->mm_node; + struct nvkm_mem *node = mem->mm_node; if (node->vma[0].node) - nouveau_vm_put(&node->vma[0]); + nvkm_vm_put(&node->vma[0]); kfree(mem->mm_node); mem->mm_node = NULL; } @@ -241,7 +241,7 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, const struct ttm_place *place, struct ttm_mem_reg *mem) { - struct nouveau_mem *node; + struct nvkm_mem *node; int ret; node = kzalloc(sizeof(*node), GFP_KERNEL); @@ -250,8 +250,8 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, node->page_shift = 12; - ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, - NV_MEM_ACCESS_RW, &node->vma[0]); + ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift, + NV_MEM_ACCESS_RW, &node->vma[0]); if (ret) { kfree(node); return ret; @@ -354,8 +354,8 @@ nouveau_ttm_init(struct nouveau_drm *drm) u32 bits; int ret; - bits = nvkm_vmmgr(&drm->device)->dma_bits; - if (nv_device_is_pci(nvkm_device(&drm->device))) { + bits = nvxx_mmu(&drm->device)->dma_bits; + if (nv_device_is_pci(nvxx_device(&drm->device))) { if (drm->agp.stat == ENABLED || !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits))) bits = 32; @@ -396,12 +396,12 @@ nouveau_ttm_init(struct nouveau_drm *drm) return ret; } - drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvkm_device(&drm->device), 1), - nv_device_resource_len(nvkm_device(&drm->device), 1)); + drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvxx_device(&drm->device), 1), + nv_device_resource_len(nvxx_device(&drm->device), 1)); /* GART init */ if (drm->agp.stat != ENABLED) { - drm->gem.gart_available = nvkm_vmmgr(&drm->device)->limit; + drm->gem.gart_available = nvxx_mmu(&drm->device)->limit; } else { drm->gem.gart_available = drm->agp.size; } diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c index f9859deb108a..c2e05e64cd6f 100644 --- a/drivers/gpu/drm/nouveau/nv04_fence.c +++ b/drivers/gpu/drm/nouveau/nv04_fence.c @@ -57,7 +57,7 @@ nv04_fence_sync(struct nouveau_fence *fence, static u32 nv04_fence_read(struct nouveau_channel *chan) { - struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);; + struct nvkm_fifo_chan *fifo = nvxx_fifo_chan(chan);; return atomic_read(&fifo->refcnt); } diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 490b90866baf..7da7958556a3 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -125,7 +125,6 @@ nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head, struct nv50_curs { struct nv50_pioc base; - struct nouveau_bo *image; }; static int @@ -201,7 +200,7 @@ nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp) nv50_chan_destroy(&dmac->base); if (dmac->ptr) { - struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev; + struct pci_dev *pdev = nvxx_device(nvif_device(disp))->pdev; pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle); } } @@ -218,7 +217,7 @@ nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head, mutex_init(&dmac->lock); - dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev, + dmac->ptr = pci_alloc_consistent(nvxx_device(device)->pdev, PAGE_SIZE, &dmac->handle); if (!dmac->ptr) return -ENOMEM; @@ -421,9 +420,9 @@ evo_wait(void *evoc, int nr) dmac->ptr[put] = 0x20000000; nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); - if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) { + if (!nvxx_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) { mutex_unlock(&dmac->lock); - nv_error(nvkm_object(&dmac->base.user), "channel stalled\n"); + nv_error(nvxx_object(&dmac->base.user), "channel stalled\n"); return NULL; } @@ -481,7 +480,7 @@ evo_sync(struct drm_device *dev) evo_data(push, 0x00000000); evo_data(push, 0x00000000); evo_kick(push, mast); - if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync)) + if (nv_wait_cb(nvxx_device(device), evo_sync_wait, disp->sync)) return 0; } @@ -536,7 +535,7 @@ nv50_display_flip_stop(struct drm_crtc *crtc) evo_kick(push, flip.chan); } - nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip); + nv_wait_cb(nvxx_device(device), nv50_display_flip_wait, &flip); } int @@ -550,6 +549,10 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, u32 *push; int ret; + if (crtc->primary->fb->width != fb->width || + crtc->primary->fb->height != fb->height) + return -EINVAL; + swap_interval <<= 4; if (swap_interval == 0) swap_interval |= 0x100; @@ -729,8 +732,11 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) * effectively handles NONE/FULL scaling */ nv_connector = nouveau_crtc_connector_get(nv_crtc); - if (nv_connector && nv_connector->native_mode) + if (nv_connector && nv_connector->native_mode) { mode = nv_connector->scaling_mode; + if (nv_connector->scaling_full) /* non-EDID LVDS/eDP mode */ + mode = DRM_MODE_SCALE_FULLSCREEN; + } if (mode != DRM_MODE_SCALE_NONE) omode = nv_connector->native_mode; @@ -917,29 +923,29 @@ static void nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) { struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); - struct nv50_curs *curs = nv50_curs(&nv_crtc->base); u32 *push = evo_wait(mast, 16); if (push) { if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); evo_data(push, 0x85000000); - evo_data(push, curs->image->bo.offset >> 8); + evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); } else if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); evo_data(push, 0x85000000); - evo_data(push, curs->image->bo.offset >> 8); + evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); evo_data(push, mast->base.vram.handle); } else { evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); evo_data(push, 0x85000000); - evo_data(push, curs->image->bo.offset >> 8); + evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); evo_data(push, mast->base.vram.handle); } evo_kick(push, mast); } + nv_crtc->cursor.visible = true; } static void @@ -965,15 +971,15 @@ nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc) } evo_kick(push, mast); } + nv_crtc->cursor.visible = false; } static void nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) { struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); - struct nv50_curs *curs = nv50_curs(&nv_crtc->base); - if (show && curs->image) + if (show && nv_crtc->cursor.nvbo) nv50_crtc_cursor_show(nv_crtc); else nv50_crtc_cursor_hide(nv_crtc); @@ -1273,7 +1279,6 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, uint32_t handle, uint32_t width, uint32_t height) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); - struct nv50_curs *curs = nv50_curs(crtc); struct drm_device *dev = crtc->dev; struct drm_gem_object *gem = NULL; struct nouveau_bo *nvbo = NULL; @@ -1292,9 +1297,9 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, } if (ret == 0) { - if (curs->image) - nouveau_bo_unpin(curs->image); - nouveau_bo_ref(nvbo, &curs->image); + if (nv_crtc->cursor.nvbo) + nouveau_bo_unpin(nv_crtc->cursor.nvbo); + nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo); } drm_gem_object_unreference_unlocked(gem); @@ -1305,10 +1310,14 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, static int nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) { + struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nv50_curs *curs = nv50_curs(crtc); struct nv50_chan *chan = nv50_chan(curs); nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff)); nvif_wr32(&chan->user, 0x0080, 0x00000000); + + nv_crtc->cursor_saved_x = x; + nv_crtc->cursor_saved_y = y; return 0; } @@ -1330,6 +1339,14 @@ nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, } static void +nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y) +{ + nv50_crtc_cursor_move(&nv_crtc->base, x, y); + + nv50_crtc_cursor_show_hide(nv_crtc, true, true); +} + +static void nv50_crtc_destroy(struct drm_crtc *crtc) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); @@ -1354,9 +1371,9 @@ nv50_crtc_destroy(struct drm_crtc *crtc) nouveau_bo_ref(NULL, &head->image); /*XXX: ditto */ - if (head->curs.image) - nouveau_bo_unpin(head->curs.image); - nouveau_bo_ref(NULL, &head->curs.image); + if (nv_crtc->cursor.nvbo) + nouveau_bo_unpin(nv_crtc->cursor.nvbo); + nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); nouveau_bo_unmap(nv_crtc->lut.nvbo); if (nv_crtc->lut.nvbo) @@ -1406,6 +1423,7 @@ nv50_crtc_create(struct drm_device *dev, int index) head->base.set_color_vibrance = nv50_crtc_set_color_vibrance; head->base.color_vibrance = 50; head->base.vibrant_hue = 0; + head->base.cursor.set_pos = nv50_crtc_cursor_restore; for (i = 0; i < 256; i++) { head->base.lut.r[i] = i << 8; head->base.lut.g[i] = i << 8; @@ -1433,8 +1451,6 @@ nv50_crtc_create(struct drm_device *dev, int index) if (ret) goto out; - nv50_crtc_lut_load(crtc); - /* allocate cursor resources */ ret = nv50_curs_create(disp->disp, index, &head->curs); if (ret) @@ -1466,6 +1482,41 @@ out: } /****************************************************************************** + * Encoder helpers + *****************************************************************************/ +static bool +nv50_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); + struct nouveau_connector *nv_connector; + + nv_connector = nouveau_encoder_connector_get(nv_encoder); + if (nv_connector && nv_connector->native_mode) { + nv_connector->scaling_full = false; + if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) { + switch (nv_connector->type) { + case DCB_CONNECTOR_LVDS: + case DCB_CONNECTOR_LVDS_SPWG: + case DCB_CONNECTOR_eDP: + /* force use of scaler for non-edid modes */ + if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) + return true; + nv_connector->scaling_full = true; + break; + default: + return true; + } + } + + drm_mode_copy(adjusted_mode, nv_connector->native_mode); + } + + return true; +} + +/****************************************************************************** * DAC *****************************************************************************/ static void @@ -1492,26 +1543,6 @@ nv50_dac_dpms(struct drm_encoder *encoder, int mode) nvif_mthd(disp->disp, 0, &args, sizeof(args)); } -static bool -nv50_dac_mode_fixup(struct drm_encoder *encoder, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); - struct nouveau_connector *nv_connector; - - nv_connector = nouveau_encoder_connector_get(nv_encoder); - if (nv_connector && nv_connector->native_mode) { - if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { - int id = adjusted_mode->base.id; - *adjusted_mode = *nv_connector->native_mode; - adjusted_mode->base.id = id; - } - } - - return true; -} - static void nv50_dac_commit(struct drm_encoder *encoder) { @@ -1629,7 +1660,7 @@ nv50_dac_destroy(struct drm_encoder *encoder) static const struct drm_encoder_helper_funcs nv50_dac_hfunc = { .dpms = nv50_dac_dpms, - .mode_fixup = nv50_dac_mode_fixup, + .mode_fixup = nv50_encoder_mode_fixup, .prepare = nv50_dac_disconnect, .commit = nv50_dac_commit, .mode_set = nv50_dac_mode_set, @@ -1646,7 +1677,7 @@ static int nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) { struct nouveau_drm *drm = nouveau_drm(connector->dev); - struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); struct nouveau_encoder *nv_encoder; struct drm_encoder *encoder; int type = DRM_MODE_ENCODER_DAC; @@ -1834,26 +1865,6 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode) } } -static bool -nv50_sor_mode_fixup(struct drm_encoder *encoder, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); - struct nouveau_connector *nv_connector; - - nv_connector = nouveau_encoder_connector_get(nv_encoder); - if (nv_connector && nv_connector->native_mode) { - if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { - int id = adjusted_mode->base.id; - *adjusted_mode = *nv_connector->native_mode; - adjusted_mode->base.id = id; - } - } - - return true; -} - static void nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data) { @@ -2035,7 +2046,7 @@ nv50_sor_destroy(struct drm_encoder *encoder) static const struct drm_encoder_helper_funcs nv50_sor_hfunc = { .dpms = nv50_sor_dpms, - .mode_fixup = nv50_sor_mode_fixup, + .mode_fixup = nv50_encoder_mode_fixup, .prepare = nv50_sor_disconnect, .commit = nv50_sor_commit, .mode_set = nv50_sor_mode_set, @@ -2051,7 +2062,7 @@ static int nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) { struct nouveau_drm *drm = nouveau_drm(connector->dev); - struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); struct nouveau_encoder *nv_encoder; struct drm_encoder *encoder; int type; @@ -2112,18 +2123,8 @@ nv50_pior_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { - struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); - struct nouveau_connector *nv_connector; - - nv_connector = nouveau_encoder_connector_get(nv_encoder); - if (nv_connector && nv_connector->native_mode) { - if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { - int id = adjusted_mode->base.id; - *adjusted_mode = *nv_connector->native_mode; - adjusted_mode->base.id = id; - } - } - + if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode)) + return false; adjusted_mode->clock *= 2; return true; } @@ -2232,8 +2233,8 @@ static int nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) { struct nouveau_drm *drm = nouveau_drm(connector->dev); - struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); - struct nouveau_i2c_port *ddc = NULL; + struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c_port *ddc = NULL; struct nouveau_encoder *nv_encoder; struct drm_encoder *encoder; int type; @@ -2427,6 +2428,8 @@ nv50_display_init(struct drm_device *dev) list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct nv50_sync *sync = nv50_sync(crtc); + + nv50_crtc_lut_load(crtc); nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data); } diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index cb5b88938d45..bf429cabbaa8 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -213,7 +213,7 @@ nv84_fence_destroy(struct nouveau_drm *drm) int nv84_fence_create(struct nouveau_drm *drm) { - struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device); + struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); struct nv84_fence_priv *priv; int ret; diff --git a/drivers/gpu/drm/nouveau/nvif/Kbuild b/drivers/gpu/drm/nouveau/nvif/Kbuild new file mode 100644 index 000000000000..ff8ed3a04d06 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvif/Kbuild @@ -0,0 +1,4 @@ +nvif-y := nvif/object.o +nvif-y += nvif/client.o +nvif-y += nvif/device.o +nvif-y += nvif/notify.o diff --git a/drivers/gpu/drm/nouveau/nvif/client.c b/drivers/gpu/drm/nouveau/nvif/client.c index 3f7ac5bc8e03..80b96844221e 100644 --- a/drivers/gpu/drm/nouveau/nvif/client.c +++ b/drivers/gpu/drm/nouveau/nvif/client.c @@ -22,9 +22,9 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> */ -#include "client.h" -#include "driver.h" -#include "ioctl.h" +#include <nvif/client.h> +#include <nvif/driver.h> +#include <nvif/ioctl.h> int nvif_client_ioctl(struct nvif_client *client, void *data, u32 size) diff --git a/drivers/gpu/drm/nouveau/nvif/device.c b/drivers/gpu/drm/nouveau/nvif/device.c index f477579725e3..6f72244c52cd 100644 --- a/drivers/gpu/drm/nouveau/nvif/device.c +++ b/drivers/gpu/drm/nouveau/nvif/device.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> */ -#include "device.h" +#include <nvif/device.h> void nvif_device_fini(struct nvif_device *device) diff --git a/drivers/gpu/drm/nouveau/nvif/device.h b/drivers/gpu/drm/nouveau/nvif/device.h deleted file mode 100644 index 43180f9fe630..000000000000 --- a/drivers/gpu/drm/nouveau/nvif/device.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef __NVIF_DEVICE_H__ -#define __NVIF_DEVICE_H__ - -#include "object.h" -#include "class.h" - -struct nvif_device { - struct nvif_object base; - struct nvif_object *object; /*XXX: hack for nvif_object() */ - struct nv_device_info_v0 info; -}; - -static inline struct nvif_device * -nvif_device(struct nvif_object *object) -{ - while (object && object->oclass != 0x0080 /*XXX: NV_DEVICE_CLASS*/ ) - object = object->parent; - return (void *)object; -} - -int nvif_device_init(struct nvif_object *, void (*dtor)(struct nvif_device *), - u32 handle, u32 oclass, void *, u32, - struct nvif_device *); -void nvif_device_fini(struct nvif_device *); -int nvif_device_new(struct nvif_object *, u32 handle, u32 oclass, - void *, u32, struct nvif_device **); -void nvif_device_ref(struct nvif_device *, struct nvif_device **); - -/*XXX*/ -#include <subdev/bios.h> -#include <subdev/fb.h> -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/gpio.h> -#include <subdev/clock.h> -#include <subdev/i2c.h> -#include <subdev/timer.h> -#include <subdev/therm.h> - -#define nvkm_device(a) nv_device(nvkm_object((a))) -#define nvkm_bios(a) nouveau_bios(nvkm_device(a)) -#define nvkm_fb(a) nouveau_fb(nvkm_device(a)) -#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a)) -#define nvkm_bar(a) nouveau_bar(nvkm_device(a)) -#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a)) -#define nvkm_clock(a) nouveau_clock(nvkm_device(a)) -#define nvkm_i2c(a) nouveau_i2c(nvkm_device(a)) -#define nvkm_timer(a) nouveau_timer(nvkm_device(a)) -#define nvkm_wait(a,b,c,d) nv_wait(nvkm_timer(a), (b), (c), (d)) -#define nvkm_wait_cb(a,b,c) nv_wait_cb(nvkm_timer(a), (b), (c)) -#define nvkm_therm(a) nouveau_therm(nvkm_device(a)) - -#include <engine/device.h> -#include <engine/fifo.h> -#include <engine/graph.h> -#include <engine/software.h> - -#define nvkm_fifo(a) nouveau_fifo(nvkm_device(a)) -#define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a)) -#define nvkm_gr(a) ((struct nouveau_graph *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR)) - -#endif diff --git a/drivers/gpu/drm/nouveau/nvif/notify.c b/drivers/gpu/drm/nouveau/nvif/notify.c index 0898c3155292..8e34748709a0 100644 --- a/drivers/gpu/drm/nouveau/nvif/notify.c +++ b/drivers/gpu/drm/nouveau/nvif/notify.c @@ -92,7 +92,7 @@ nvif_notify_func(struct nvif_notify *notify, bool keep) { int ret = notify->func(notify); if (ret == NVIF_NOTIFY_KEEP || - !test_and_clear_bit(NVKM_NOTIFY_USER, ¬ify->flags)) { + !test_and_clear_bit(NVIF_NOTIFY_USER, ¬ify->flags)) { if (!keep) atomic_dec(¬ify->putcnt); else diff --git a/drivers/gpu/drm/nouveau/nvif/object.c b/drivers/gpu/drm/nouveau/nvif/object.c index dd85b56f6aa5..3ab4e2f8cc12 100644 --- a/drivers/gpu/drm/nouveau/nvif/object.c +++ b/drivers/gpu/drm/nouveau/nvif/object.c @@ -22,10 +22,10 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> */ -#include "object.h" -#include "client.h" -#include "driver.h" -#include "ioctl.h" +#include <nvif/object.h> +#include <nvif/client.h> +#include <nvif/driver.h> +#include <nvif/ioctl.h> int nvif_object_ioctl(struct nvif_object *object, void *data, u32 size, void **hack) diff --git a/drivers/gpu/drm/nouveau/nvif/os.h b/drivers/gpu/drm/nouveau/nvif/os.h deleted file mode 120000 index bd744b2cf5cf..000000000000 --- a/drivers/gpu/drm/nouveau/nvif/os.h +++ /dev/null @@ -1 +0,0 @@ -../core/os.h
\ No newline at end of file diff --git a/drivers/gpu/drm/nouveau/nvkm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/Kbuild new file mode 100644 index 000000000000..2832147b676c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/Kbuild @@ -0,0 +1,3 @@ +include $(src)/nvkm/core/Kbuild +include $(src)/nvkm/subdev/Kbuild +include $(src)/nvkm/engine/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/core/Kbuild b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild new file mode 100644 index 000000000000..a2bdb2069113 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild @@ -0,0 +1,17 @@ +nvkm-y := nvkm/core/client.o +nvkm-y += nvkm/core/engctx.o +nvkm-y += nvkm/core/engine.o +nvkm-y += nvkm/core/enum.o +nvkm-y += nvkm/core/event.o +nvkm-y += nvkm/core/gpuobj.o +nvkm-y += nvkm/core/handle.o +nvkm-y += nvkm/core/ioctl.o +nvkm-y += nvkm/core/mm.o +nvkm-y += nvkm/core/namedb.o +nvkm-y += nvkm/core/notify.o +nvkm-y += nvkm/core/object.o +nvkm-y += nvkm/core/option.o +nvkm-y += nvkm/core/parent.o +nvkm-y += nvkm/core/printk.o +nvkm-y += nvkm/core/ramht.o +nvkm-y += nvkm/core/subdev.o diff --git a/drivers/gpu/drm/nouveau/core/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index e962433294c3..878a82f8f295 100644 --- a/drivers/gpu/drm/nouveau/core/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -21,21 +21,18 @@ * * Authors: Ben Skeggs */ - -#include <core/object.h> #include <core/client.h> +#include <core/device.h> #include <core/handle.h> +#include <core/notify.h> #include <core/option.h> -#include <nvif/unpack.h> -#include <nvif/class.h> -#include <nvif/unpack.h> +#include <nvif/class.h> #include <nvif/event.h> - -#include <engine/device.h> +#include <nvif/unpack.h> struct nvkm_client_notify { - struct nouveau_client *client; + struct nvkm_client *client; struct nvkm_notify n; u8 version; u8 size; @@ -48,12 +45,12 @@ static int nvkm_client_notify(struct nvkm_notify *n) { struct nvkm_client_notify *notify = container_of(n, typeof(*notify), n); - struct nouveau_client *client = notify->client; + struct nvkm_client *client = notify->client; return client->ntfy(¬ify->rep, notify->size, n->data, n->size); } int -nvkm_client_notify_put(struct nouveau_client *client, int index) +nvkm_client_notify_put(struct nvkm_client *client, int index) { if (index < ARRAY_SIZE(client->notify)) { if (client->notify[index]) { @@ -65,7 +62,7 @@ nvkm_client_notify_put(struct nouveau_client *client, int index) } int -nvkm_client_notify_get(struct nouveau_client *client, int index) +nvkm_client_notify_get(struct nvkm_client *client, int index) { if (index < ARRAY_SIZE(client->notify)) { if (client->notify[index]) { @@ -77,7 +74,7 @@ nvkm_client_notify_get(struct nouveau_client *client, int index) } int -nvkm_client_notify_del(struct nouveau_client *client, int index) +nvkm_client_notify_del(struct nvkm_client *client, int index) { if (index < ARRAY_SIZE(client->notify)) { if (client->notify[index]) { @@ -91,10 +88,10 @@ nvkm_client_notify_del(struct nouveau_client *client, int index) } int -nvkm_client_notify_new(struct nouveau_object *object, +nvkm_client_notify_new(struct nvkm_object *object, struct nvkm_event *event, void *data, u32 size) { - struct nouveau_client *client = nouveau_client(object); + struct nvkm_client *client = nvkm_client(object); struct nvkm_client_notify *notify; union { struct nvif_notify_req_v0 v0; @@ -142,7 +139,7 @@ nvkm_client_notify_new(struct nouveau_object *object, } static int -nouveau_client_devlist(struct nouveau_object *object, void *data, u32 size) +nvkm_client_mthd_devlist(struct nvkm_object *object, void *data, u32 size) { union { struct nv_client_devlist_v0 v0; @@ -154,8 +151,7 @@ nouveau_client_devlist(struct nouveau_object *object, void *data, u32 size) nv_ioctl(object, "client devlist vers %d count %d\n", args->v0.version, args->v0.count); if (size == sizeof(args->v0.device[0]) * args->v0.count) { - ret = nouveau_device_list(args->v0.device, - args->v0.count); + ret = nvkm_device_list(args->v0.device, args->v0.count); if (ret >= 0) { args->v0.count = ret; ret = 0; @@ -169,12 +165,11 @@ nouveau_client_devlist(struct nouveau_object *object, void *data, u32 size) } static int -nouveau_client_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) +nvkm_client_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { switch (mthd) { case NV_CLIENT_DEVLIST: - return nouveau_client_devlist(object, data, size); + return nvkm_client_mthd_devlist(object, data, size); default: break; } @@ -182,71 +177,71 @@ nouveau_client_mthd(struct nouveau_object *object, u32 mthd, } static void -nouveau_client_dtor(struct nouveau_object *object) +nvkm_client_dtor(struct nvkm_object *object) { - struct nouveau_client *client = (void *)object; + struct nvkm_client *client = (void *)object; int i; for (i = 0; i < ARRAY_SIZE(client->notify); i++) nvkm_client_notify_del(client, i); - nouveau_object_ref(NULL, &client->device); - nouveau_handle_destroy(client->root); - nouveau_namedb_destroy(&client->base); + nvkm_object_ref(NULL, &client->device); + nvkm_handle_destroy(client->root); + nvkm_namedb_destroy(&client->namedb); } -static struct nouveau_oclass -nouveau_client_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { - .dtor = nouveau_client_dtor, - .mthd = nouveau_client_mthd, +static struct nvkm_oclass +nvkm_client_oclass = { + .ofuncs = &(struct nvkm_ofuncs) { + .dtor = nvkm_client_dtor, + .mthd = nvkm_client_mthd, }, }; int -nouveau_client_create_(const char *name, u64 devname, const char *cfg, - const char *dbg, int length, void **pobject) +nvkm_client_create_(const char *name, u64 devname, const char *cfg, + const char *dbg, int length, void **pobject) { - struct nouveau_object *device; - struct nouveau_client *client; + struct nvkm_object *device; + struct nvkm_client *client; int ret; - device = (void *)nouveau_device_find(devname); + device = (void *)nvkm_device_find(devname); if (!device) return -ENODEV; - ret = nouveau_namedb_create_(NULL, NULL, &nouveau_client_oclass, - NV_CLIENT_CLASS, NULL, - (1ULL << NVDEV_ENGINE_DEVICE), - length, pobject); + ret = nvkm_namedb_create_(NULL, NULL, &nvkm_client_oclass, + NV_CLIENT_CLASS, NULL, + (1ULL << NVDEV_ENGINE_DEVICE), + length, pobject); client = *pobject; if (ret) return ret; - ret = nouveau_handle_create(nv_object(client), ~0, ~0, - nv_object(client), &client->root); + ret = nvkm_handle_create(nv_object(client), ~0, ~0, nv_object(client), + &client->root); if (ret) return ret; /* prevent init/fini being called, os in in charge of this */ atomic_set(&nv_object(client)->usecount, 2); - nouveau_object_ref(device, &client->device); + nvkm_object_ref(device, &client->device); snprintf(client->name, sizeof(client->name), "%s", name); - client->debug = nouveau_dbgopt(dbg, "CLIENT"); + client->debug = nvkm_dbgopt(dbg, "CLIENT"); return 0; } int -nouveau_client_init(struct nouveau_client *client) +nvkm_client_init(struct nvkm_client *client) { int ret; nv_debug(client, "init running\n"); - ret = nouveau_handle_init(client->root); + ret = nvkm_handle_init(client->root); nv_debug(client, "init completed with %d\n", ret); return ret; } int -nouveau_client_fini(struct nouveau_client *client, bool suspend) +nvkm_client_fini(struct nvkm_client *client, bool suspend) { const char *name[2] = { "fini", "suspend" }; int ret, i; @@ -255,16 +250,16 @@ nouveau_client_fini(struct nouveau_client *client, bool suspend) for (i = 0; i < ARRAY_SIZE(client->notify); i++) nvkm_client_notify_put(client, i); nv_debug(client, "%s object\n", name[suspend]); - ret = nouveau_handle_fini(client->root, suspend); + ret = nvkm_handle_fini(client->root, suspend); nv_debug(client, "%s completed with %d\n", name[suspend], ret); return ret; } const char * -nouveau_client_name(void *obj) +nvkm_client_name(void *obj) { const char *client_name = "unknown"; - struct nouveau_client *client = nouveau_client(obj); + struct nvkm_client *client = nvkm_client(obj); if (client) client_name = client->name; return client_name; diff --git a/drivers/gpu/drm/nouveau/core/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c index 84c71fad2b6c..fb2acbca75d9 100644 --- a/drivers/gpu/drm/nouveau/core/core/engctx.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c @@ -21,21 +21,16 @@ * * Authors: Ben Skeggs */ - -#include <core/object.h> -#include <core/namedb.h> -#include <core/handle.h> -#include <core/client.h> #include <core/engctx.h> - -#include <subdev/vm.h> +#include <core/engine.h> +#include <core/client.h> static inline int -nouveau_engctx_exists(struct nouveau_object *parent, - struct nouveau_engine *engine, void **pobject) +nvkm_engctx_exists(struct nvkm_object *parent, + struct nvkm_engine *engine, void **pobject) { - struct nouveau_engctx *engctx; - struct nouveau_object *parctx; + struct nvkm_engctx *engctx; + struct nvkm_object *parctx; list_for_each_entry(engctx, &engine->contexts, head) { parctx = nv_pclass(nv_object(engctx), NV_PARENT_CLASS); @@ -50,16 +45,13 @@ nouveau_engctx_exists(struct nouveau_object *parent, } int -nouveau_engctx_create_(struct nouveau_object *parent, - struct nouveau_object *engobj, - struct nouveau_oclass *oclass, - struct nouveau_object *pargpu, - u32 size, u32 align, u32 flags, - int length, void **pobject) +nvkm_engctx_create_(struct nvkm_object *parent, struct nvkm_object *engobj, + struct nvkm_oclass *oclass, struct nvkm_object *pargpu, + u32 size, u32 align, u32 flags, int length, void **pobject) { - struct nouveau_client *client = nouveau_client(parent); - struct nouveau_engine *engine = nv_engine(engobj); - struct nouveau_object *engctx; + struct nvkm_client *client = nvkm_client(parent); + struct nvkm_engine *engine = nv_engine(engobj); + struct nvkm_object *engctx; unsigned long save; int ret; @@ -67,7 +59,7 @@ nouveau_engctx_create_(struct nouveau_object *parent, * and reference it instead of creating a new one */ spin_lock_irqsave(&engine->lock, save); - ret = nouveau_engctx_exists(parent, engine, pobject); + ret = nvkm_engctx_exists(parent, engine, pobject); spin_unlock_irqrestore(&engine->lock, save); if (ret) return ret; @@ -76,13 +68,12 @@ nouveau_engctx_create_(struct nouveau_object *parent, * objects backed by instance memory */ if (size) { - ret = nouveau_gpuobj_create_(parent, engobj, oclass, - NV_ENGCTX_CLASS, - pargpu, size, align, flags, - length, pobject); + ret = nvkm_gpuobj_create_(parent, engobj, oclass, + NV_ENGCTX_CLASS, pargpu, size, + align, flags, length, pobject); } else { - ret = nouveau_object_create_(parent, engobj, oclass, - NV_ENGCTX_CLASS, length, pobject); + ret = nvkm_object_create_(parent, engobj, oclass, + NV_ENGCTX_CLASS, length, pobject); } engctx = *pobject; @@ -94,15 +85,15 @@ nouveau_engctx_create_(struct nouveau_object *parent, * it's not possible to allocate the object with it held. */ spin_lock_irqsave(&engine->lock, save); - ret = nouveau_engctx_exists(parent, engine, pobject); + ret = nvkm_engctx_exists(parent, engine, pobject); if (ret) { spin_unlock_irqrestore(&engine->lock, save); - nouveau_object_ref(NULL, &engctx); + nvkm_object_ref(NULL, &engctx); return ret; } if (client->vm) - atomic_inc(&client->vm->engref[nv_engidx(engobj)]); + atomic_inc(&client->vm->engref[nv_engidx(engine)]); list_add(&nv_engctx(engctx)->head, &engine->contexts); nv_engctx(engctx)->addr = ~0ULL; spin_unlock_irqrestore(&engine->lock, save); @@ -110,37 +101,36 @@ nouveau_engctx_create_(struct nouveau_object *parent, } void -nouveau_engctx_destroy(struct nouveau_engctx *engctx) +nvkm_engctx_destroy(struct nvkm_engctx *engctx) { - struct nouveau_object *engobj = nv_object(engctx)->engine; - struct nouveau_engine *engine = nv_engine(engobj); - struct nouveau_client *client = nouveau_client(engctx); + struct nvkm_engine *engine = engctx->gpuobj.object.engine; + struct nvkm_client *client = nvkm_client(engctx); unsigned long save; - nouveau_gpuobj_unmap(&engctx->vma); + nvkm_gpuobj_unmap(&engctx->vma); spin_lock_irqsave(&engine->lock, save); list_del(&engctx->head); spin_unlock_irqrestore(&engine->lock, save); if (client->vm) - atomic_dec(&client->vm->engref[nv_engidx(engobj)]); + atomic_dec(&client->vm->engref[nv_engidx(engine)]); - if (engctx->base.size) - nouveau_gpuobj_destroy(&engctx->base); + if (engctx->gpuobj.size) + nvkm_gpuobj_destroy(&engctx->gpuobj); else - nouveau_object_destroy(&engctx->base.base); + nvkm_object_destroy(&engctx->gpuobj.object); } int -nouveau_engctx_init(struct nouveau_engctx *engctx) +nvkm_engctx_init(struct nvkm_engctx *engctx) { - struct nouveau_object *object = nv_object(engctx); - struct nouveau_subdev *subdev = nv_subdev(object->engine); - struct nouveau_object *parent; - struct nouveau_subdev *pardev; + struct nvkm_object *object = nv_object(engctx); + struct nvkm_subdev *subdev = nv_subdev(object->engine); + struct nvkm_object *parent; + struct nvkm_subdev *pardev; int ret; - ret = nouveau_gpuobj_init(&engctx->base); + ret = nvkm_gpuobj_init(&engctx->gpuobj); if (ret) return ret; @@ -163,12 +153,12 @@ nouveau_engctx_init(struct nouveau_engctx *engctx) } int -nouveau_engctx_fini(struct nouveau_engctx *engctx, bool suspend) +nvkm_engctx_fini(struct nvkm_engctx *engctx, bool suspend) { - struct nouveau_object *object = nv_object(engctx); - struct nouveau_subdev *subdev = nv_subdev(object->engine); - struct nouveau_object *parent; - struct nouveau_subdev *pardev; + struct nvkm_object *object = nv_object(engctx); + struct nvkm_subdev *subdev = nv_subdev(object->engine); + struct nvkm_object *parent; + struct nvkm_subdev *pardev; int ret = 0; parent = nv_pclass(object->parent, NV_PARENT_CLASS); @@ -186,47 +176,45 @@ nouveau_engctx_fini(struct nouveau_engctx *engctx, bool suspend) } nv_debug(parent, "detached %s context\n", subdev->name); - return nouveau_gpuobj_fini(&engctx->base, suspend); + return nvkm_gpuobj_fini(&engctx->gpuobj, suspend); } int -_nouveau_engctx_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +_nvkm_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_engctx *engctx; + struct nvkm_engctx *engctx; int ret; - ret = nouveau_engctx_create(parent, engine, oclass, NULL, 256, 256, - NVOBJ_FLAG_ZERO_ALLOC, &engctx); + ret = nvkm_engctx_create(parent, engine, oclass, NULL, 256, 256, + NVOBJ_FLAG_ZERO_ALLOC, &engctx); *pobject = nv_object(engctx); return ret; } void -_nouveau_engctx_dtor(struct nouveau_object *object) +_nvkm_engctx_dtor(struct nvkm_object *object) { - nouveau_engctx_destroy(nv_engctx(object)); + nvkm_engctx_destroy(nv_engctx(object)); } int -_nouveau_engctx_init(struct nouveau_object *object) +_nvkm_engctx_init(struct nvkm_object *object) { - return nouveau_engctx_init(nv_engctx(object)); + return nvkm_engctx_init(nv_engctx(object)); } - int -_nouveau_engctx_fini(struct nouveau_object *object, bool suspend) +_nvkm_engctx_fini(struct nvkm_object *object, bool suspend) { - return nouveau_engctx_fini(nv_engctx(object), suspend); + return nvkm_engctx_fini(nv_engctx(object), suspend); } -struct nouveau_object * -nouveau_engctx_get(struct nouveau_engine *engine, u64 addr) +struct nvkm_object * +nvkm_engctx_get(struct nvkm_engine *engine, u64 addr) { - struct nouveau_engctx *engctx; + struct nvkm_engctx *engctx; unsigned long flags; spin_lock_irqsave(&engine->lock, flags); @@ -241,11 +229,11 @@ nouveau_engctx_get(struct nouveau_engine *engine, u64 addr) } void -nouveau_engctx_put(struct nouveau_object *object) +nvkm_engctx_put(struct nvkm_object *object) { if (object) { - struct nouveau_engine *engine = nv_engine(object->engine); - struct nouveau_engctx *engctx = nv_engctx(object); + struct nvkm_engine *engine = nv_engine(object->engine); + struct nvkm_engctx *engctx = nv_engctx(object); spin_unlock_irqrestore(&engine->lock, engctx->save); } } diff --git a/drivers/gpu/drm/nouveau/core/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c index 1f6954ae9dd3..60820173c6aa 100644 --- a/drivers/gpu/drm/nouveau/core/core/engine.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engine.c @@ -21,33 +21,40 @@ * * Authors: Ben Skeggs */ - -#include <core/device.h> #include <core/engine.h> +#include <core/device.h> #include <core/option.h> +struct nvkm_engine * +nvkm_engine(void *obj, int idx) +{ + obj = nvkm_subdev(obj, idx); + if (obj && nv_iclass(obj, NV_ENGINE_CLASS)) + return nv_engine(obj); + return NULL; +} + int -nouveau_engine_create_(struct nouveau_object *parent, - struct nouveau_object *engobj, - struct nouveau_oclass *oclass, bool enable, - const char *iname, const char *fname, - int length, void **pobject) +nvkm_engine_create_(struct nvkm_object *parent, struct nvkm_object *engobj, + struct nvkm_oclass *oclass, bool enable, + const char *iname, const char *fname, + int length, void **pobject) { - struct nouveau_engine *engine; + struct nvkm_engine *engine; int ret; - ret = nouveau_subdev_create_(parent, engobj, oclass, NV_ENGINE_CLASS, - iname, fname, length, pobject); + ret = nvkm_subdev_create_(parent, engobj, oclass, NV_ENGINE_CLASS, + iname, fname, length, pobject); engine = *pobject; if (ret) return ret; if (parent) { - struct nouveau_device *device = nv_device(parent); - int engidx = nv_engidx(nv_object(engine)); + struct nvkm_device *device = nv_device(parent); + int engidx = nv_engidx(engine); if (device->disable_mask & (1ULL << engidx)) { - if (!nouveau_boolopt(device->cfgopt, iname, false)) { + if (!nvkm_boolopt(device->cfgopt, iname, false)) { nv_debug(engine, "engine disabled by hw/fw\n"); return -ENODEV; } @@ -55,7 +62,7 @@ nouveau_engine_create_(struct nouveau_object *parent, nv_warn(engine, "ignoring hw/fw engine disable\n"); } - if (!nouveau_boolopt(device->cfgopt, iname, enable)) { + if (!nvkm_boolopt(device->cfgopt, iname, enable)) { if (!enable) nv_warn(engine, "disabled, %s=1 to enable\n", iname); return -ENODEV; diff --git a/drivers/gpu/drm/nouveau/core/core/enum.c b/drivers/gpu/drm/nouveau/nvkm/core/enum.c index dd434790ccc4..4f92bfc13d6b 100644 --- a/drivers/gpu/drm/nouveau/core/core/enum.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/enum.c @@ -24,12 +24,10 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - -#include <core/os.h> #include <core/enum.h> -const struct nouveau_enum * -nouveau_enum_find(const struct nouveau_enum *en, u32 value) +const struct nvkm_enum * +nvkm_enum_find(const struct nvkm_enum *en, u32 value) { while (en->name) { if (en->value == value) @@ -40,10 +38,10 @@ nouveau_enum_find(const struct nouveau_enum *en, u32 value) return NULL; } -const struct nouveau_enum * -nouveau_enum_print(const struct nouveau_enum *en, u32 value) +const struct nvkm_enum * +nvkm_enum_print(const struct nvkm_enum *en, u32 value) { - en = nouveau_enum_find(en, value); + en = nvkm_enum_find(en, value); if (en) pr_cont("%s", en->name); else @@ -52,7 +50,7 @@ nouveau_enum_print(const struct nouveau_enum *en, u32 value) } void -nouveau_bitfield_print(const struct nouveau_bitfield *bf, u32 value) +nvkm_bitfield_print(const struct nvkm_bitfield *bf, u32 value) { while (bf->name) { if (value & bf->mask) { diff --git a/drivers/gpu/drm/nouveau/core/core/event.c b/drivers/gpu/drm/nouveau/nvkm/core/event.c index ff2b434b3db4..4e8d3fa042df 100644 --- a/drivers/gpu/drm/nouveau/core/core/event.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/event.c @@ -19,14 +19,13 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ - -#include <core/object.h> #include <core/event.h> +#include <core/notify.h> void nvkm_event_put(struct nvkm_event *event, u32 types, int index) { - BUG_ON(!spin_is_locked(&event->refs_lock)); + assert_spin_locked(&event->refs_lock); while (types) { int type = __ffs(types); types &= ~(1 << type); if (--event->refs[index * event->types_nr + type] == 0) { @@ -39,7 +38,7 @@ nvkm_event_put(struct nvkm_event *event, u32 types, int index) void nvkm_event_get(struct nvkm_event *event, u32 types, int index) { - BUG_ON(!spin_is_locked(&event->refs_lock)); + assert_spin_locked(&event->refs_lock); while (types) { int type = __ffs(types); types &= ~(1 << type); if (++event->refs[index * event->types_nr + type] == 1) { diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c new file mode 100644 index 000000000000..2eba801aae6f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c @@ -0,0 +1,316 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include <core/gpuobj.h> +#include <core/engine.h> + +#include <subdev/instmem.h> +#include <subdev/bar.h> +#include <subdev/mmu.h> + +void +nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj) +{ + int i; + + if (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE) { + for (i = 0; i < gpuobj->size; i += 4) + nv_wo32(gpuobj, i, 0x00000000); + } + + if (gpuobj->node) + nvkm_mm_free(&nv_gpuobj(gpuobj->parent)->heap, &gpuobj->node); + + if (gpuobj->heap.block_size) + nvkm_mm_fini(&gpuobj->heap); + + nvkm_object_destroy(&gpuobj->object); +} + +int +nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 pclass, + struct nvkm_object *pargpu, u32 size, u32 align, u32 flags, + int length, void **pobject) +{ + struct nvkm_instmem *imem = nvkm_instmem(parent); + struct nvkm_bar *bar = nvkm_bar(parent); + struct nvkm_gpuobj *gpuobj; + struct nvkm_mm *heap = NULL; + int ret, i; + u64 addr; + + *pobject = NULL; + + if (pargpu) { + while ((pargpu = nv_pclass(pargpu, NV_GPUOBJ_CLASS))) { + if (nv_gpuobj(pargpu)->heap.block_size) + break; + pargpu = pargpu->parent; + } + + if (unlikely(pargpu == NULL)) { + nv_error(parent, "no gpuobj heap\n"); + return -EINVAL; + } + + addr = nv_gpuobj(pargpu)->addr; + heap = &nv_gpuobj(pargpu)->heap; + atomic_inc(&parent->refcount); + } else { + ret = imem->alloc(imem, parent, size, align, &parent); + pargpu = parent; + if (ret) + return ret; + + addr = nv_memobj(pargpu)->addr; + size = nv_memobj(pargpu)->size; + + if (bar && bar->alloc) { + struct nvkm_instobj *iobj = (void *)parent; + struct nvkm_mem **mem = (void *)(iobj + 1); + struct nvkm_mem *node = *mem; + if (!bar->alloc(bar, parent, node, &pargpu)) { + nvkm_object_ref(NULL, &parent); + parent = pargpu; + } + } + } + + ret = nvkm_object_create_(parent, engine, oclass, pclass | + NV_GPUOBJ_CLASS, length, pobject); + nvkm_object_ref(NULL, &parent); + gpuobj = *pobject; + if (ret) + return ret; + + gpuobj->parent = pargpu; + gpuobj->flags = flags; + gpuobj->addr = addr; + gpuobj->size = size; + + if (heap) { + ret = nvkm_mm_head(heap, 0, 1, size, size, max(align, (u32)1), + &gpuobj->node); + if (ret) + return ret; + + gpuobj->addr += gpuobj->node->offset; + } + + if (gpuobj->flags & NVOBJ_FLAG_HEAP) { + ret = nvkm_mm_init(&gpuobj->heap, 0, gpuobj->size, 1); + if (ret) + return ret; + } + + if (flags & NVOBJ_FLAG_ZERO_ALLOC) { + for (i = 0; i < gpuobj->size; i += 4) + nv_wo32(gpuobj, i, 0x00000000); + } + + return ret; +} + +struct nvkm_gpuobj_class { + struct nvkm_object *pargpu; + u64 size; + u32 align; + u32 flags; +}; + +static int +_nvkm_gpuobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_gpuobj_class *args = data; + struct nvkm_gpuobj *object; + int ret; + + ret = nvkm_gpuobj_create(parent, engine, oclass, 0, args->pargpu, + args->size, args->align, args->flags, + &object); + *pobject = nv_object(object); + if (ret) + return ret; + + return 0; +} + +void +_nvkm_gpuobj_dtor(struct nvkm_object *object) +{ + nvkm_gpuobj_destroy(nv_gpuobj(object)); +} + +int +_nvkm_gpuobj_init(struct nvkm_object *object) +{ + return nvkm_gpuobj_init(nv_gpuobj(object)); +} + +int +_nvkm_gpuobj_fini(struct nvkm_object *object, bool suspend) +{ + return nvkm_gpuobj_fini(nv_gpuobj(object), suspend); +} + +u32 +_nvkm_gpuobj_rd32(struct nvkm_object *object, u64 addr) +{ + struct nvkm_gpuobj *gpuobj = nv_gpuobj(object); + struct nvkm_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent); + if (gpuobj->node) + addr += gpuobj->node->offset; + return pfuncs->rd32(gpuobj->parent, addr); +} + +void +_nvkm_gpuobj_wr32(struct nvkm_object *object, u64 addr, u32 data) +{ + struct nvkm_gpuobj *gpuobj = nv_gpuobj(object); + struct nvkm_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent); + if (gpuobj->node) + addr += gpuobj->node->offset; + pfuncs->wr32(gpuobj->parent, addr, data); +} + +static struct nvkm_oclass +_nvkm_gpuobj_oclass = { + .handle = 0x00000000, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_gpuobj_ctor, + .dtor = _nvkm_gpuobj_dtor, + .init = _nvkm_gpuobj_init, + .fini = _nvkm_gpuobj_fini, + .rd32 = _nvkm_gpuobj_rd32, + .wr32 = _nvkm_gpuobj_wr32, + }, +}; + +int +nvkm_gpuobj_new(struct nvkm_object *parent, struct nvkm_object *pargpu, + u32 size, u32 align, u32 flags, + struct nvkm_gpuobj **pgpuobj) +{ + struct nvkm_object *engine = parent; + struct nvkm_gpuobj_class args = { + .pargpu = pargpu, + .size = size, + .align = align, + .flags = flags, + }; + + if (!nv_iclass(engine, NV_SUBDEV_CLASS)) + engine = &engine->engine->subdev.object; + BUG_ON(engine == NULL); + + return nvkm_object_ctor(parent, engine, &_nvkm_gpuobj_oclass, + &args, sizeof(args), + (struct nvkm_object **)pgpuobj); +} + +int +nvkm_gpuobj_map(struct nvkm_gpuobj *gpuobj, u32 access, struct nvkm_vma *vma) +{ + struct nvkm_bar *bar = nvkm_bar(gpuobj); + int ret = -EINVAL; + + if (bar && bar->umap) { + struct nvkm_instobj *iobj = (void *) + nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS); + struct nvkm_mem **mem = (void *)(iobj + 1); + ret = bar->umap(bar, *mem, access, vma); + } + + return ret; +} + +int +nvkm_gpuobj_map_vm(struct nvkm_gpuobj *gpuobj, struct nvkm_vm *vm, + u32 access, struct nvkm_vma *vma) +{ + struct nvkm_instobj *iobj = (void *) + nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS); + struct nvkm_mem **mem = (void *)(iobj + 1); + int ret; + + ret = nvkm_vm_get(vm, gpuobj->size, 12, access, vma); + if (ret) + return ret; + + nvkm_vm_map(vma, *mem); + return 0; +} + +void +nvkm_gpuobj_unmap(struct nvkm_vma *vma) +{ + if (vma->node) { + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); + } +} + +/* the below is basically only here to support sharing the paged dma object + * for PCI(E)GART on <=nv4x chipsets, and should *not* be expected to work + * anywhere else. + */ + +static void +nvkm_gpudup_dtor(struct nvkm_object *object) +{ + struct nvkm_gpuobj *gpuobj = (void *)object; + nvkm_object_ref(NULL, &gpuobj->parent); + nvkm_object_destroy(&gpuobj->object); +} + +static struct nvkm_oclass +nvkm_gpudup_oclass = { + .handle = NV_GPUOBJ_CLASS, + .ofuncs = &(struct nvkm_ofuncs) { + .dtor = nvkm_gpudup_dtor, + .init = nvkm_object_init, + .fini = nvkm_object_fini, + }, +}; + +int +nvkm_gpuobj_dup(struct nvkm_object *parent, struct nvkm_gpuobj *base, + struct nvkm_gpuobj **pgpuobj) +{ + struct nvkm_gpuobj *gpuobj; + int ret; + + ret = nvkm_object_create(parent, &parent->engine->subdev.object, + &nvkm_gpudup_oclass, 0, &gpuobj); + *pgpuobj = gpuobj; + if (ret) + return ret; + + nvkm_object_ref(nv_object(base), &gpuobj->parent); + gpuobj->addr = base->addr; + gpuobj->size = base->size; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/core/core/handle.c b/drivers/gpu/drm/nouveau/nvkm/core/handle.c index 13f816cb08bd..dc7ff10ebe7b 100644 --- a/drivers/gpu/drm/nouveau/core/core/handle.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/handle.c @@ -21,31 +21,29 @@ * * Authors: Ben Skeggs */ - -#include <core/object.h> #include <core/handle.h> #include <core/client.h> #define hprintk(h,l,f,a...) do { \ - struct nouveau_client *c = nouveau_client((h)->object); \ - struct nouveau_handle *p = (h)->parent; u32 n = p ? p->name : ~0; \ + struct nvkm_client *c = nvkm_client((h)->object); \ + struct nvkm_handle *p = (h)->parent; u32 n = p ? p->name : ~0; \ nv_printk((c), l, "0x%08x:0x%08x "f, n, (h)->name, ##a); \ } while(0) int -nouveau_handle_init(struct nouveau_handle *handle) +nvkm_handle_init(struct nvkm_handle *handle) { - struct nouveau_handle *item; + struct nvkm_handle *item; int ret; hprintk(handle, TRACE, "init running\n"); - ret = nouveau_object_inc(handle->object); + ret = nvkm_object_inc(handle->object); if (ret) return ret; hprintk(handle, TRACE, "init children\n"); list_for_each_entry(item, &handle->tree, head) { - ret = nouveau_handle_init(item); + ret = nvkm_handle_init(item); if (ret) goto fail; } @@ -55,30 +53,30 @@ nouveau_handle_init(struct nouveau_handle *handle) fail: hprintk(handle, ERROR, "init failed with %d\n", ret); list_for_each_entry_continue_reverse(item, &handle->tree, head) { - nouveau_handle_fini(item, false); + nvkm_handle_fini(item, false); } - nouveau_object_dec(handle->object, false); + nvkm_object_dec(handle->object, false); return ret; } int -nouveau_handle_fini(struct nouveau_handle *handle, bool suspend) +nvkm_handle_fini(struct nvkm_handle *handle, bool suspend) { static char *name[2] = { "fini", "suspend" }; - struct nouveau_handle *item; + struct nvkm_handle *item; int ret; hprintk(handle, TRACE, "%s children\n", name[suspend]); list_for_each_entry(item, &handle->tree, head) { - ret = nouveau_handle_fini(item, suspend); + ret = nvkm_handle_fini(item, suspend); if (ret && suspend) goto fail; } hprintk(handle, TRACE, "%s running\n", name[suspend]); if (handle->object) { - ret = nouveau_object_dec(handle->object, suspend); + ret = nvkm_object_dec(handle->object, suspend); if (ret && suspend) goto fail; } @@ -88,7 +86,7 @@ nouveau_handle_fini(struct nouveau_handle *handle, bool suspend) fail: hprintk(handle, ERROR, "%s failed with %d\n", name[suspend], ret); list_for_each_entry_continue_reverse(item, &handle->tree, head) { - int rret = nouveau_handle_init(item); + int rret = nvkm_handle_init(item); if (rret) hprintk(handle, FATAL, "failed to restart, %d\n", rret); } @@ -97,12 +95,11 @@ fail: } int -nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle, - struct nouveau_object *object, - struct nouveau_handle **phandle) +nvkm_handle_create(struct nvkm_object *parent, u32 _parent, u32 _handle, + struct nvkm_object *object, struct nvkm_handle **phandle) { - struct nouveau_object *namedb; - struct nouveau_handle *handle; + struct nvkm_object *namedb; + struct nvkm_handle *handle; int ret; namedb = parent; @@ -118,7 +115,7 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle, handle->name = _handle; handle->priv = ~0; - ret = nouveau_namedb_insert(nv_namedb(namedb), _handle, object, handle); + ret = nvkm_namedb_insert(nv_namedb(namedb), _handle, object, handle); if (ret) { kfree(handle); return ret; @@ -127,7 +124,7 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle, if (nv_parent(parent)->object_attach) { ret = nv_parent(parent)->object_attach(parent, object, _handle); if (ret < 0) { - nouveau_handle_destroy(handle); + nvkm_handle_destroy(handle); return ret; } @@ -138,10 +135,10 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle, while (!nv_iclass(namedb, NV_CLIENT_CLASS)) namedb = namedb->parent; - handle->parent = nouveau_namedb_get(nv_namedb(namedb), _parent); + handle->parent = nvkm_namedb_get(nv_namedb(namedb), _parent); if (handle->parent) { list_add(&handle->head, &handle->parent->tree); - nouveau_namedb_put(handle->parent); + nvkm_namedb_put(handle->parent); } } @@ -151,74 +148,74 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle, } void -nouveau_handle_destroy(struct nouveau_handle *handle) +nvkm_handle_destroy(struct nvkm_handle *handle) { - struct nouveau_handle *item, *temp; + struct nvkm_handle *item, *temp; hprintk(handle, TRACE, "destroy running\n"); list_for_each_entry_safe(item, temp, &handle->tree, head) { - nouveau_handle_destroy(item); + nvkm_handle_destroy(item); } list_del(&handle->head); if (handle->priv != ~0) { - struct nouveau_object *parent = handle->parent->object; + struct nvkm_object *parent = handle->parent->object; nv_parent(parent)->object_detach(parent, handle->priv); } hprintk(handle, TRACE, "destroy completed\n"); - nouveau_namedb_remove(handle); + nvkm_namedb_remove(handle); kfree(handle); } -struct nouveau_object * -nouveau_handle_ref(struct nouveau_object *parent, u32 name) +struct nvkm_object * +nvkm_handle_ref(struct nvkm_object *parent, u32 name) { - struct nouveau_object *object = NULL; - struct nouveau_handle *handle; + struct nvkm_object *object = NULL; + struct nvkm_handle *handle; while (!nv_iclass(parent, NV_NAMEDB_CLASS)) parent = parent->parent; - handle = nouveau_namedb_get(nv_namedb(parent), name); + handle = nvkm_namedb_get(nv_namedb(parent), name); if (handle) { - nouveau_object_ref(handle->object, &object); - nouveau_namedb_put(handle); + nvkm_object_ref(handle->object, &object); + nvkm_namedb_put(handle); } return object; } -struct nouveau_handle * -nouveau_handle_get_class(struct nouveau_object *engctx, u16 oclass) +struct nvkm_handle * +nvkm_handle_get_class(struct nvkm_object *engctx, u16 oclass) { - struct nouveau_namedb *namedb; + struct nvkm_namedb *namedb; if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS))) - return nouveau_namedb_get_class(namedb, oclass); + return nvkm_namedb_get_class(namedb, oclass); return NULL; } -struct nouveau_handle * -nouveau_handle_get_vinst(struct nouveau_object *engctx, u64 vinst) +struct nvkm_handle * +nvkm_handle_get_vinst(struct nvkm_object *engctx, u64 vinst) { - struct nouveau_namedb *namedb; + struct nvkm_namedb *namedb; if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS))) - return nouveau_namedb_get_vinst(namedb, vinst); + return nvkm_namedb_get_vinst(namedb, vinst); return NULL; } -struct nouveau_handle * -nouveau_handle_get_cinst(struct nouveau_object *engctx, u32 cinst) +struct nvkm_handle * +nvkm_handle_get_cinst(struct nvkm_object *engctx, u32 cinst) { - struct nouveau_namedb *namedb; + struct nvkm_namedb *namedb; if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS))) - return nouveau_namedb_get_cinst(namedb, cinst); + return nvkm_namedb_get_cinst(namedb, cinst); return NULL; } void -nouveau_handle_put(struct nouveau_handle *handle) +nvkm_handle_put(struct nvkm_handle *handle) { if (handle) - nouveau_namedb_put(handle); + nvkm_namedb_put(handle); } diff --git a/drivers/gpu/drm/nouveau/core/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index 692aa92dd850..4459ff5f4cb8 100644 --- a/drivers/gpu/drm/nouveau/core/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -21,23 +21,19 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include <core/object.h> -#include <core/parent.h> +#include <core/ioctl.h> +#include <core/client.h> +#include <core/engine.h> #include <core/handle.h> #include <core/namedb.h> -#include <core/client.h> -#include <core/device.h> -#include <core/ioctl.h> -#include <core/event.h> #include <nvif/unpack.h> #include <nvif/ioctl.h> static int -nvkm_ioctl_nop(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_nop(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_object *object = handle->object; + struct nvkm_object *object = handle->object; union { struct nvif_ioctl_nop none; } *args = data; @@ -52,9 +48,9 @@ nvkm_ioctl_nop(struct nouveau_handle *handle, void *data, u32 size) } static int -nvkm_ioctl_sclass(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_sclass(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_object *object = handle->object; + struct nvkm_object *object = handle->object; union { struct nvif_ioctl_sclass_v0 v0; } *args = data; @@ -70,8 +66,8 @@ nvkm_ioctl_sclass(struct nouveau_handle *handle, void *data, u32 size) nv_ioctl(object, "sclass vers %d count %d\n", args->v0.version, args->v0.count); if (size == args->v0.count * sizeof(args->v0.oclass[0])) { - ret = nouveau_parent_lclass(object, args->v0.oclass, - args->v0.count); + ret = nvkm_parent_lclass(object, args->v0.oclass, + args->v0.count); if (ret >= 0) { args->v0.count = ret; ret = 0; @@ -85,17 +81,17 @@ nvkm_ioctl_sclass(struct nouveau_handle *handle, void *data, u32 size) } static int -nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size) +nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size) { union { struct nvif_ioctl_new_v0 v0; } *args = data; - struct nouveau_client *client = nouveau_client(parent->object); - struct nouveau_object *engctx = NULL; - struct nouveau_object *object = NULL; - struct nouveau_object *engine; - struct nouveau_oclass *oclass; - struct nouveau_handle *handle; + struct nvkm_client *client = nvkm_client(handle->object); + struct nvkm_object *engctx = NULL; + struct nvkm_object *object = NULL; + struct nvkm_parent *parent; + struct nvkm_object *engine; + struct nvkm_oclass *oclass; u32 _handle, _oclass; int ret; @@ -108,19 +104,21 @@ nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size) nv_ioctl(client, "new vers %d handle %08x class %08x " "route %02x token %llx\n", - args->v0.version, _handle, _oclass, - args->v0.route, args->v0.token); + args->v0.version, _handle, _oclass, + args->v0.route, args->v0.token); - if (!nv_iclass(parent->object, NV_PARENT_CLASS)) { - nv_debug(parent->object, "cannot have children (ctor)\n"); + if (!nv_iclass(handle->object, NV_PARENT_CLASS)) { + nv_debug(handle->object, "cannot have children (ctor)\n"); ret = -ENODEV; goto fail_class; } + parent = nv_parent(handle->object); + /* check that parent supports the requested subclass */ - ret = nouveau_parent_sclass(parent->object, _oclass, &engine, &oclass); + ret = nvkm_parent_sclass(&parent->object, _oclass, &engine, &oclass); if (ret) { - nv_debug(parent->object, "illegal class 0x%04x\n", _oclass); + nv_debug(parent, "illegal class 0x%04x\n", _oclass); goto fail_class; } @@ -129,7 +127,7 @@ nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size) * state calculated at init (ie. default context construction) */ if (engine) { - ret = nouveau_object_inc(engine); + ret = nvkm_object_inc(engine); if (ret) goto fail_class; } @@ -138,53 +136,53 @@ nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size) * between the parent and its children (eg. PGRAPH context) */ if (engine && nv_engine(engine)->cclass) { - ret = nouveau_object_ctor(parent->object, engine, - nv_engine(engine)->cclass, - data, size, &engctx); + ret = nvkm_object_ctor(&parent->object, engine, + nv_engine(engine)->cclass, + data, size, &engctx); if (ret) goto fail_engctx; } else { - nouveau_object_ref(parent->object, &engctx); + nvkm_object_ref(&parent->object, &engctx); } /* finally, create new object and bind it to its handle */ - ret = nouveau_object_ctor(engctx, engine, oclass, data, size, &object); + ret = nvkm_object_ctor(engctx, engine, oclass, data, size, &object); client->data = object; if (ret) goto fail_ctor; - ret = nouveau_object_inc(object); + ret = nvkm_object_inc(object); if (ret) goto fail_init; - ret = nouveau_handle_create(parent->object, parent->name, - _handle, object, &handle); + ret = nvkm_handle_create(&parent->object, handle->name, + _handle, object, &handle); if (ret) goto fail_handle; - ret = nouveau_handle_init(handle); + ret = nvkm_handle_init(handle); handle->route = args->v0.route; handle->token = args->v0.token; if (ret) - nouveau_handle_destroy(handle); + nvkm_handle_destroy(handle); fail_handle: - nouveau_object_dec(object, false); + nvkm_object_dec(object, false); fail_init: - nouveau_object_ref(NULL, &object); + nvkm_object_ref(NULL, &object); fail_ctor: - nouveau_object_ref(NULL, &engctx); + nvkm_object_ref(NULL, &engctx); fail_engctx: if (engine) - nouveau_object_dec(engine, false); + nvkm_object_dec(engine, false); fail_class: return ret; } static int -nvkm_ioctl_del(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_del(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_object *object = handle->object; + struct nvkm_object *object = handle->object; union { struct nvif_ioctl_del none; } *args = data; @@ -193,18 +191,18 @@ nvkm_ioctl_del(struct nouveau_handle *handle, void *data, u32 size) nv_ioctl(object, "delete size %d\n", size); if (nvif_unvers(args->none)) { nv_ioctl(object, "delete\n"); - nouveau_handle_fini(handle, false); - nouveau_handle_destroy(handle); + nvkm_handle_fini(handle, false); + nvkm_handle_destroy(handle); } return ret; } static int -nvkm_ioctl_mthd(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_mthd(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_object *object = handle->object; - struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; + struct nvkm_object *object = handle->object; + struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; union { struct nvif_ioctl_mthd_v0 v0; } *args = data; @@ -223,10 +221,10 @@ nvkm_ioctl_mthd(struct nouveau_handle *handle, void *data, u32 size) static int -nvkm_ioctl_rd(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_rd(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_object *object = handle->object; - struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; + struct nvkm_object *object = handle->object; + struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; union { struct nvif_ioctl_rd_v0 v0; } *args = data; @@ -235,7 +233,7 @@ nvkm_ioctl_rd(struct nouveau_handle *handle, void *data, u32 size) nv_ioctl(object, "rd size %d\n", size); if (nvif_unpack(args->v0, 0, 0, false)) { nv_ioctl(object, "rd vers %d size %d addr %016llx\n", - args->v0.version, args->v0.size, args->v0.addr); + args->v0.version, args->v0.size, args->v0.addr); switch (args->v0.size) { case 1: if (ret = -ENODEV, ofuncs->rd08) { @@ -265,10 +263,10 @@ nvkm_ioctl_rd(struct nouveau_handle *handle, void *data, u32 size) } static int -nvkm_ioctl_wr(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_wr(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_object *object = handle->object; - struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; + struct nvkm_object *object = handle->object; + struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; union { struct nvif_ioctl_wr_v0 v0; } *args = data; @@ -308,10 +306,10 @@ nvkm_ioctl_wr(struct nouveau_handle *handle, void *data, u32 size) } static int -nvkm_ioctl_map(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_map(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_object *object = handle->object; - struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; + struct nvkm_object *object = handle->object; + struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; union { struct nvif_ioctl_map_v0 v0; } *args = data; @@ -330,9 +328,9 @@ nvkm_ioctl_map(struct nouveau_handle *handle, void *data, u32 size) } static int -nvkm_ioctl_unmap(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_unmap(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_object *object = handle->object; + struct nvkm_object *object = handle->object; union { struct nvif_ioctl_unmap none; } *args = data; @@ -347,10 +345,10 @@ nvkm_ioctl_unmap(struct nouveau_handle *handle, void *data, u32 size) } static int -nvkm_ioctl_ntfy_new(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_ntfy_new(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_object *object = handle->object; - struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; + struct nvkm_object *object = handle->object; + struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; union { struct nvif_ioctl_ntfy_new_v0 v0; } *args = data; @@ -376,10 +374,10 @@ nvkm_ioctl_ntfy_new(struct nouveau_handle *handle, void *data, u32 size) } static int -nvkm_ioctl_ntfy_del(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_ntfy_del(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_client *client = nouveau_client(handle->object); - struct nouveau_object *object = handle->object; + struct nvkm_client *client = nvkm_client(handle->object); + struct nvkm_object *object = handle->object; union { struct nvif_ioctl_ntfy_del_v0 v0; } *args = data; @@ -396,10 +394,10 @@ nvkm_ioctl_ntfy_del(struct nouveau_handle *handle, void *data, u32 size) } static int -nvkm_ioctl_ntfy_get(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_ntfy_get(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_client *client = nouveau_client(handle->object); - struct nouveau_object *object = handle->object; + struct nvkm_client *client = nvkm_client(handle->object); + struct nvkm_object *object = handle->object; union { struct nvif_ioctl_ntfy_get_v0 v0; } *args = data; @@ -416,10 +414,10 @@ nvkm_ioctl_ntfy_get(struct nouveau_handle *handle, void *data, u32 size) } static int -nvkm_ioctl_ntfy_put(struct nouveau_handle *handle, void *data, u32 size) +nvkm_ioctl_ntfy_put(struct nvkm_handle *handle, void *data, u32 size) { - struct nouveau_client *client = nouveau_client(handle->object); - struct nouveau_object *object = handle->object; + struct nvkm_client *client = nvkm_client(handle->object); + struct nvkm_object *object = handle->object; union { struct nvif_ioctl_ntfy_put_v0 v0; } *args = data; @@ -437,7 +435,7 @@ nvkm_ioctl_ntfy_put(struct nouveau_handle *handle, void *data, u32 size) static struct { int version; - int (*func)(struct nouveau_handle *, void *, u32); + int (*func)(struct nvkm_handle *, void *, u32); } nvkm_ioctl_v0[] = { { 0x00, nvkm_ioctl_nop }, @@ -456,13 +454,12 @@ nvkm_ioctl_v0[] = { }; static int -nvkm_ioctl_path(struct nouveau_handle *parent, u32 type, u32 nr, - u32 *path, void *data, u32 size, - u8 owner, u8 *route, u64 *token) +nvkm_ioctl_path(struct nvkm_handle *parent, u32 type, u32 nr, u32 *path, + void *data, u32 size, u8 owner, u8 *route, u64 *token) { - struct nouveau_handle *handle = parent; - struct nouveau_namedb *namedb; - struct nouveau_object *object; + struct nvkm_handle *handle = parent; + struct nvkm_namedb *namedb; + struct nvkm_object *object; int ret; while ((object = parent->object), nr--) { @@ -473,16 +470,15 @@ nvkm_ioctl_path(struct nouveau_handle *parent, u32 type, u32 nr, } if (!(namedb = (void *)nv_pclass(object, NV_NAMEDB_CLASS)) || - !(handle = nouveau_namedb_get(namedb, path[nr]))) { + !(handle = nvkm_namedb_get(namedb, path[nr]))) { nv_debug(object, "handle 0x%08x not found\n", path[nr]); return -ENOENT; } - nouveau_namedb_put(handle); + nvkm_namedb_put(handle); parent = handle; } - if (owner != NVIF_IOCTL_V0_OWNER_ANY && - owner != handle->route) { + if (owner != NVIF_IOCTL_V0_OWNER_ANY && owner != handle->route) { nv_ioctl(object, "object route != owner\n"); return -EACCES; } @@ -490,16 +486,15 @@ nvkm_ioctl_path(struct nouveau_handle *parent, u32 type, u32 nr, *token = handle->token; if (ret = -EINVAL, type < ARRAY_SIZE(nvkm_ioctl_v0)) { - if (nvkm_ioctl_v0[type].version == 0) { + if (nvkm_ioctl_v0[type].version == 0) ret = nvkm_ioctl_v0[type].func(handle, data, size); - } } return ret; } int -nvkm_ioctl(struct nouveau_client *client, bool supervisor, +nvkm_ioctl(struct nvkm_client *client, bool supervisor, void *data, u32 size, void **hack) { union { @@ -517,7 +512,7 @@ nvkm_ioctl(struct nouveau_client *client, bool supervisor, ret = nvkm_ioctl_path(client->root, args->v0.type, args->v0.path_nr, args->v0.path, data, size, args->v0.owner, - &args->v0.route, &args->v0.token); + &args->v0.route, &args->v0.token); } nv_ioctl(client, "return %d\n", ret); @@ -525,6 +520,7 @@ nvkm_ioctl(struct nouveau_client *client, bool supervisor, *hack = client->data; client->data = NULL; } + client->super = false; return ret; } diff --git a/drivers/gpu/drm/nouveau/core/core/mm.c b/drivers/gpu/drm/nouveau/nvkm/core/mm.c index b4f5db66d5b5..7f458dfd5608 100644 --- a/drivers/gpu/drm/nouveau/core/core/mm.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/mm.c @@ -21,39 +21,37 @@ * * Authors: Ben Skeggs */ +#include <core/mm.h> -#include "core/os.h" -#include "core/mm.h" - -#define node(root, dir) ((root)->nl_entry.dir == &mm->nodes) ? NULL : \ - list_entry((root)->nl_entry.dir, struct nouveau_mm_node, nl_entry) +#define node(root, dir) ((root)->nl_entry.dir == &mm->nodes) ? NULL : \ + list_entry((root)->nl_entry.dir, struct nvkm_mm_node, nl_entry) static void -nouveau_mm_dump(struct nouveau_mm *mm, const char *header) +nvkm_mm_dump(struct nvkm_mm *mm, const char *header) { - struct nouveau_mm_node *node; + struct nvkm_mm_node *node; - printk(KERN_ERR "nouveau: %s\n", header); - printk(KERN_ERR "nouveau: node list:\n"); + printk(KERN_ERR "nvkm: %s\n", header); + printk(KERN_ERR "nvkm: node list:\n"); list_for_each_entry(node, &mm->nodes, nl_entry) { - printk(KERN_ERR "nouveau: \t%08x %08x %d\n", + printk(KERN_ERR "nvkm: \t%08x %08x %d\n", node->offset, node->length, node->type); } - printk(KERN_ERR "nouveau: free list:\n"); + printk(KERN_ERR "nvkm: free list:\n"); list_for_each_entry(node, &mm->free, fl_entry) { - printk(KERN_ERR "nouveau: \t%08x %08x %d\n", + printk(KERN_ERR "nvkm: \t%08x %08x %d\n", node->offset, node->length, node->type); } } void -nouveau_mm_free(struct nouveau_mm *mm, struct nouveau_mm_node **pthis) +nvkm_mm_free(struct nvkm_mm *mm, struct nvkm_mm_node **pthis) { - struct nouveau_mm_node *this = *pthis; + struct nvkm_mm_node *this = *pthis; if (this) { - struct nouveau_mm_node *prev = node(this, prev); - struct nouveau_mm_node *next = node(this, next); + struct nvkm_mm_node *prev = node(this, prev); + struct nvkm_mm_node *next = node(this, next); if (prev && prev->type == NVKM_MM_TYPE_NONE) { prev->length += this->length; @@ -84,10 +82,10 @@ nouveau_mm_free(struct nouveau_mm *mm, struct nouveau_mm_node **pthis) *pthis = NULL; } -static struct nouveau_mm_node * -region_head(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size) +static struct nvkm_mm_node * +region_head(struct nvkm_mm *mm, struct nvkm_mm_node *a, u32 size) { - struct nouveau_mm_node *b; + struct nvkm_mm_node *b; if (a->length == size) return a; @@ -105,14 +103,15 @@ region_head(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size) list_add_tail(&b->nl_entry, &a->nl_entry); if (b->type == NVKM_MM_TYPE_NONE) list_add_tail(&b->fl_entry, &a->fl_entry); + return b; } int -nouveau_mm_head(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max, - u32 size_min, u32 align, struct nouveau_mm_node **pnode) +nvkm_mm_head(struct nvkm_mm *mm, u8 heap, u8 type, u32 size_max, u32 size_min, + u32 align, struct nvkm_mm_node **pnode) { - struct nouveau_mm_node *prev, *this, *next; + struct nvkm_mm_node *prev, *this, *next; u32 mask = align - 1; u32 splitoff; u32 s, e; @@ -157,10 +156,10 @@ nouveau_mm_head(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max, return -ENOSPC; } -static struct nouveau_mm_node * -region_tail(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size) +static struct nvkm_mm_node * +region_tail(struct nvkm_mm *mm, struct nvkm_mm_node *a, u32 size) { - struct nouveau_mm_node *b; + struct nvkm_mm_node *b; if (a->length == size) return a; @@ -178,14 +177,15 @@ region_tail(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size) list_add(&b->nl_entry, &a->nl_entry); if (b->type == NVKM_MM_TYPE_NONE) list_add(&b->fl_entry, &a->fl_entry); + return b; } int -nouveau_mm_tail(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max, - u32 size_min, u32 align, struct nouveau_mm_node **pnode) +nvkm_mm_tail(struct nvkm_mm *mm, u8 heap, u8 type, u32 size_max, u32 size_min, + u32 align, struct nvkm_mm_node **pnode) { - struct nouveau_mm_node *prev, *this, *next; + struct nvkm_mm_node *prev, *this, *next; u32 mask = align - 1; BUG_ON(type == NVKM_MM_TYPE_NONE || type == NVKM_MM_TYPE_HOLE); @@ -235,12 +235,12 @@ nouveau_mm_tail(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max, } int -nouveau_mm_init(struct nouveau_mm *mm, u32 offset, u32 length, u32 block) +nvkm_mm_init(struct nvkm_mm *mm, u32 offset, u32 length, u32 block) { - struct nouveau_mm_node *node, *prev; + struct nvkm_mm_node *node, *prev; u32 next; - if (nouveau_mm_initialised(mm)) { + if (nvkm_mm_initialised(mm)) { prev = list_last_entry(&mm->nodes, typeof(*node), nl_entry); next = prev->offset + prev->length; if (next != offset) { @@ -277,18 +277,18 @@ nouveau_mm_init(struct nouveau_mm *mm, u32 offset, u32 length, u32 block) } int -nouveau_mm_fini(struct nouveau_mm *mm) +nvkm_mm_fini(struct nvkm_mm *mm) { - struct nouveau_mm_node *node, *temp; + struct nvkm_mm_node *node, *temp; int nodes = 0; - if (!nouveau_mm_initialised(mm)) + if (!nvkm_mm_initialised(mm)) return 0; list_for_each_entry(node, &mm->nodes, nl_entry) { if (node->type != NVKM_MM_TYPE_HOLE) { if (++nodes > mm->heap_nodes) { - nouveau_mm_dump(mm, "mm not clean!"); + nvkm_mm_dump(mm, "mm not clean!"); return -EBUSY; } } @@ -298,6 +298,7 @@ nouveau_mm_fini(struct nouveau_mm *mm) list_del(&node->nl_entry); kfree(node); } + mm->heap_nodes = 0; return 0; } diff --git a/drivers/gpu/drm/nouveau/core/core/namedb.c b/drivers/gpu/drm/nouveau/nvkm/core/namedb.c index 0594a599f6fb..6400767c5dba 100644 --- a/drivers/gpu/drm/nouveau/core/core/namedb.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/namedb.c @@ -21,16 +21,14 @@ * * Authors: Ben Skeggs */ - -#include <core/object.h> #include <core/namedb.h> -#include <core/handle.h> #include <core/gpuobj.h> +#include <core/handle.h> -static struct nouveau_handle * -nouveau_namedb_lookup(struct nouveau_namedb *namedb, u32 name) +static struct nvkm_handle * +nvkm_namedb_lookup(struct nvkm_namedb *namedb, u32 name) { - struct nouveau_handle *handle; + struct nvkm_handle *handle; list_for_each_entry(handle, &namedb->list, node) { if (handle->name == name) @@ -40,10 +38,10 @@ nouveau_namedb_lookup(struct nouveau_namedb *namedb, u32 name) return NULL; } -static struct nouveau_handle * -nouveau_namedb_lookup_class(struct nouveau_namedb *namedb, u16 oclass) +static struct nvkm_handle * +nvkm_namedb_lookup_class(struct nvkm_namedb *namedb, u16 oclass) { - struct nouveau_handle *handle; + struct nvkm_handle *handle; list_for_each_entry(handle, &namedb->list, node) { if (nv_mclass(handle->object) == oclass) @@ -53,10 +51,10 @@ nouveau_namedb_lookup_class(struct nouveau_namedb *namedb, u16 oclass) return NULL; } -static struct nouveau_handle * -nouveau_namedb_lookup_vinst(struct nouveau_namedb *namedb, u64 vinst) +static struct nvkm_handle * +nvkm_namedb_lookup_vinst(struct nvkm_namedb *namedb, u64 vinst) { - struct nouveau_handle *handle; + struct nvkm_handle *handle; list_for_each_entry(handle, &namedb->list, node) { if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { @@ -68,10 +66,10 @@ nouveau_namedb_lookup_vinst(struct nouveau_namedb *namedb, u64 vinst) return NULL; } -static struct nouveau_handle * -nouveau_namedb_lookup_cinst(struct nouveau_namedb *namedb, u32 cinst) +static struct nvkm_handle * +nvkm_namedb_lookup_cinst(struct nvkm_namedb *namedb, u32 cinst) { - struct nouveau_handle *handle; + struct nvkm_handle *handle; list_for_each_entry(handle, &namedb->list, node) { if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { @@ -85,14 +83,14 @@ nouveau_namedb_lookup_cinst(struct nouveau_namedb *namedb, u32 cinst) } int -nouveau_namedb_insert(struct nouveau_namedb *namedb, u32 name, - struct nouveau_object *object, - struct nouveau_handle *handle) +nvkm_namedb_insert(struct nvkm_namedb *namedb, u32 name, + struct nvkm_object *object, + struct nvkm_handle *handle) { int ret = -EEXIST; write_lock_irq(&namedb->lock); - if (!nouveau_namedb_lookup(namedb, name)) { - nouveau_object_ref(object, &handle->object); + if (!nvkm_namedb_lookup(namedb, name)) { + nvkm_object_ref(object, &handle->object); handle->namedb = namedb; list_add(&handle->node, &namedb->list); ret = 0; @@ -102,80 +100,79 @@ nouveau_namedb_insert(struct nouveau_namedb *namedb, u32 name, } void -nouveau_namedb_remove(struct nouveau_handle *handle) +nvkm_namedb_remove(struct nvkm_handle *handle) { - struct nouveau_namedb *namedb = handle->namedb; - struct nouveau_object *object = handle->object; + struct nvkm_namedb *namedb = handle->namedb; + struct nvkm_object *object = handle->object; write_lock_irq(&namedb->lock); list_del(&handle->node); write_unlock_irq(&namedb->lock); - nouveau_object_ref(NULL, &object); + nvkm_object_ref(NULL, &object); } -struct nouveau_handle * -nouveau_namedb_get(struct nouveau_namedb *namedb, u32 name) +struct nvkm_handle * +nvkm_namedb_get(struct nvkm_namedb *namedb, u32 name) { - struct nouveau_handle *handle; + struct nvkm_handle *handle; read_lock(&namedb->lock); - handle = nouveau_namedb_lookup(namedb, name); + handle = nvkm_namedb_lookup(namedb, name); if (handle == NULL) read_unlock(&namedb->lock); return handle; } -struct nouveau_handle * -nouveau_namedb_get_class(struct nouveau_namedb *namedb, u16 oclass) +struct nvkm_handle * +nvkm_namedb_get_class(struct nvkm_namedb *namedb, u16 oclass) { - struct nouveau_handle *handle; + struct nvkm_handle *handle; read_lock(&namedb->lock); - handle = nouveau_namedb_lookup_class(namedb, oclass); + handle = nvkm_namedb_lookup_class(namedb, oclass); if (handle == NULL) read_unlock(&namedb->lock); return handle; } -struct nouveau_handle * -nouveau_namedb_get_vinst(struct nouveau_namedb *namedb, u64 vinst) +struct nvkm_handle * +nvkm_namedb_get_vinst(struct nvkm_namedb *namedb, u64 vinst) { - struct nouveau_handle *handle; + struct nvkm_handle *handle; read_lock(&namedb->lock); - handle = nouveau_namedb_lookup_vinst(namedb, vinst); + handle = nvkm_namedb_lookup_vinst(namedb, vinst); if (handle == NULL) read_unlock(&namedb->lock); return handle; } -struct nouveau_handle * -nouveau_namedb_get_cinst(struct nouveau_namedb *namedb, u32 cinst) +struct nvkm_handle * +nvkm_namedb_get_cinst(struct nvkm_namedb *namedb, u32 cinst) { - struct nouveau_handle *handle; + struct nvkm_handle *handle; read_lock(&namedb->lock); - handle = nouveau_namedb_lookup_cinst(namedb, cinst); + handle = nvkm_namedb_lookup_cinst(namedb, cinst); if (handle == NULL) read_unlock(&namedb->lock); return handle; } void -nouveau_namedb_put(struct nouveau_handle *handle) +nvkm_namedb_put(struct nvkm_handle *handle) { if (handle) read_unlock(&handle->namedb->lock); } int -nouveau_namedb_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 pclass, - struct nouveau_oclass *sclass, u64 engcls, - int length, void **pobject) +nvkm_namedb_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 pclass, + struct nvkm_oclass *sclass, u64 engcls, + int length, void **pobject) { - struct nouveau_namedb *namedb; + struct nvkm_namedb *namedb; int ret; - ret = nouveau_parent_create_(parent, engine, oclass, pclass | - NV_NAMEDB_CLASS, sclass, engcls, - length, pobject); + ret = nvkm_parent_create_(parent, engine, oclass, pclass | + NV_NAMEDB_CLASS, sclass, engcls, + length, pobject); namedb = *pobject; if (ret) return ret; @@ -186,15 +183,14 @@ nouveau_namedb_create_(struct nouveau_object *parent, } int -_nouveau_namedb_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +_nvkm_namedb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_namedb *object; + struct nvkm_namedb *object; int ret; - ret = nouveau_namedb_create(parent, engine, oclass, 0, NULL, 0, &object); + ret = nvkm_namedb_create(parent, engine, oclass, 0, NULL, 0, &object); *pobject = nv_object(object); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/core/notify.c b/drivers/gpu/drm/nouveau/nvkm/core/notify.c index d1bcde55e9d7..023610d01458 100644 --- a/drivers/gpu/drm/nouveau/core/core/notify.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/notify.c @@ -21,13 +21,8 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include <core/client.h> -#include <core/event.h> #include <core/notify.h> - -#include <nvif/unpack.h> -#include <nvif/event.h> +#include <core/event.h> static inline void nvkm_notify_put_locked(struct nvkm_notify *notify) @@ -98,7 +93,7 @@ nvkm_notify_send(struct nvkm_notify *notify, void *data, u32 size) struct nvkm_event *event = notify->event; unsigned long flags; - BUG_ON(!spin_is_locked(&event->list_lock)); + assert_spin_locked(&event->list_lock); BUG_ON(size != notify->size); spin_lock_irqsave(&event->refs_lock, flags); @@ -134,7 +129,7 @@ nvkm_notify_fini(struct nvkm_notify *notify) } int -nvkm_notify_init(struct nouveau_object *object, struct nvkm_event *event, +nvkm_notify_init(struct nvkm_object *object, struct nvkm_event *event, int (*func)(struct nvkm_notify *), bool work, void *data, u32 size, u32 reply, struct nvkm_notify *notify) diff --git a/drivers/gpu/drm/nouveau/core/core/object.c b/drivers/gpu/drm/nouveau/nvkm/core/object.c index b08630577c82..979f3627d395 100644 --- a/drivers/gpu/drm/nouveau/core/core/object.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/object.c @@ -21,36 +21,34 @@ * * Authors: Ben Skeggs */ - #include <core/object.h> #include <core/engine.h> -#ifdef NOUVEAU_OBJECT_MAGIC +#ifdef NVKM_OBJECT_MAGIC static struct list_head _objlist = LIST_HEAD_INIT(_objlist); static DEFINE_SPINLOCK(_objlist_lock); #endif int -nouveau_object_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 pclass, - int size, void **pobject) +nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 pclass, + int size, void **pobject) { - struct nouveau_object *object; + struct nvkm_object *object; object = *pobject = kzalloc(size, GFP_KERNEL); if (!object) return -ENOMEM; - nouveau_object_ref(parent, &object->parent); - nouveau_object_ref(engine, &object->engine); + nvkm_object_ref(parent, &object->parent); + nvkm_object_ref(engine, (struct nvkm_object **)&object->engine); object->oclass = oclass; object->oclass->handle |= pclass; atomic_set(&object->refcount, 1); atomic_set(&object->usecount, 0); -#ifdef NOUVEAU_OBJECT_MAGIC - object->_magic = NOUVEAU_OBJECT_MAGIC; +#ifdef NVKM_OBJECT_MAGIC + object->_magic = NVKM_OBJECT_MAGIC; spin_lock(&_objlist_lock); list_add(&object->list, &_objlist); spin_unlock(&_objlist_lock); @@ -59,57 +57,55 @@ nouveau_object_create_(struct nouveau_object *parent, } int -_nouveau_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +_nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { if (size != 0) return -ENOSYS; - return nouveau_object_create(parent, engine, oclass, 0, pobject); + return nvkm_object_create(parent, engine, oclass, 0, pobject); } void -nouveau_object_destroy(struct nouveau_object *object) +nvkm_object_destroy(struct nvkm_object *object) { -#ifdef NOUVEAU_OBJECT_MAGIC +#ifdef NVKM_OBJECT_MAGIC spin_lock(&_objlist_lock); list_del(&object->list); spin_unlock(&_objlist_lock); #endif - nouveau_object_ref(NULL, &object->engine); - nouveau_object_ref(NULL, &object->parent); + nvkm_object_ref(NULL, (struct nvkm_object **)&object->engine); + nvkm_object_ref(NULL, &object->parent); kfree(object); } int -nouveau_object_init(struct nouveau_object *object) +nvkm_object_init(struct nvkm_object *object) { return 0; } int -nouveau_object_fini(struct nouveau_object *object, bool suspend) +nvkm_object_fini(struct nvkm_object *object, bool suspend) { return 0; } -struct nouveau_ofuncs -nouveau_object_ofuncs = { - .ctor = _nouveau_object_ctor, - .dtor = nouveau_object_destroy, - .init = nouveau_object_init, - .fini = nouveau_object_fini, +struct nvkm_ofuncs +nvkm_object_ofuncs = { + .ctor = _nvkm_object_ctor, + .dtor = nvkm_object_destroy, + .init = nvkm_object_init, + .fini = nvkm_object_fini, }; int -nouveau_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_ofuncs *ofuncs = oclass->ofuncs; - struct nouveau_object *object = NULL; + struct nvkm_ofuncs *ofuncs = oclass->ofuncs; + struct nvkm_object *object = NULL; int ret; ret = ofuncs->ctor(parent, engine, oclass, data, size, &object); @@ -137,14 +133,14 @@ nouveau_object_ctor(struct nouveau_object *parent, } static void -nouveau_object_dtor(struct nouveau_object *object) +nvkm_object_dtor(struct nvkm_object *object) { nv_trace(object, "destroying\n"); nv_ofuncs(object)->dtor(object); } void -nouveau_object_ref(struct nouveau_object *obj, struct nouveau_object **ref) +nvkm_object_ref(struct nvkm_object *obj, struct nvkm_object **ref) { if (obj) { atomic_inc(&obj->refcount); @@ -155,14 +151,14 @@ nouveau_object_ref(struct nouveau_object *obj, struct nouveau_object **ref) int dead = atomic_dec_and_test(&(*ref)->refcount); nv_trace(*ref, "dec() == %d\n", atomic_read(&(*ref)->refcount)); if (dead) - nouveau_object_dtor(*ref); + nvkm_object_dtor(*ref); } *ref = obj; } int -nouveau_object_inc(struct nouveau_object *object) +nvkm_object_inc(struct nvkm_object *object) { int ref = atomic_add_return(1, &object->usecount); int ret; @@ -173,7 +169,7 @@ nouveau_object_inc(struct nouveau_object *object) nv_trace(object, "initialising...\n"); if (object->parent) { - ret = nouveau_object_inc(object->parent); + ret = nvkm_object_inc(object->parent); if (ret) { nv_error(object, "parent failed, %d\n", ret); goto fail_parent; @@ -182,7 +178,7 @@ nouveau_object_inc(struct nouveau_object *object) if (object->engine) { mutex_lock(&nv_subdev(object->engine)->mutex); - ret = nouveau_object_inc(object->engine); + ret = nvkm_object_inc(&object->engine->subdev.object); mutex_unlock(&nv_subdev(object->engine)->mutex); if (ret) { nv_error(object, "engine failed, %d\n", ret); @@ -203,19 +199,19 @@ nouveau_object_inc(struct nouveau_object *object) fail_self: if (object->engine) { mutex_lock(&nv_subdev(object->engine)->mutex); - nouveau_object_dec(object->engine, false); + nvkm_object_dec(&object->engine->subdev.object, false); mutex_unlock(&nv_subdev(object->engine)->mutex); } fail_engine: if (object->parent) - nouveau_object_dec(object->parent, false); + nvkm_object_dec(object->parent, false); fail_parent: atomic_dec(&object->usecount); return ret; } static int -nouveau_object_decf(struct nouveau_object *object) +nvkm_object_decf(struct nvkm_object *object) { int ret; @@ -228,19 +224,19 @@ nouveau_object_decf(struct nouveau_object *object) if (object->engine) { mutex_lock(&nv_subdev(object->engine)->mutex); - nouveau_object_dec(object->engine, false); + nvkm_object_dec(&object->engine->subdev.object, false); mutex_unlock(&nv_subdev(object->engine)->mutex); } if (object->parent) - nouveau_object_dec(object->parent, false); + nvkm_object_dec(object->parent, false); nv_trace(object, "stopped\n"); return 0; } static int -nouveau_object_decs(struct nouveau_object *object) +nvkm_object_decs(struct nvkm_object *object) { int ret, rret; @@ -255,7 +251,7 @@ nouveau_object_decs(struct nouveau_object *object) if (object->engine) { mutex_lock(&nv_subdev(object->engine)->mutex); - ret = nouveau_object_dec(object->engine, true); + ret = nvkm_object_dec(&object->engine->subdev.object, true); mutex_unlock(&nv_subdev(object->engine)->mutex); if (ret) { nv_warn(object, "engine failed suspend, %d\n", ret); @@ -264,7 +260,7 @@ nouveau_object_decs(struct nouveau_object *object) } if (object->parent) { - ret = nouveau_object_dec(object->parent, true); + ret = nvkm_object_dec(object->parent, true); if (ret) { nv_warn(object, "parent failed suspend, %d\n", ret); goto fail_parent; @@ -277,7 +273,7 @@ nouveau_object_decs(struct nouveau_object *object) fail_parent: if (object->engine) { mutex_lock(&nv_subdev(object->engine)->mutex); - rret = nouveau_object_inc(object->engine); + rret = nvkm_object_inc(&object->engine->subdev.object); mutex_unlock(&nv_subdev(object->engine)->mutex); if (rret) nv_fatal(object, "engine failed to reinit, %d\n", rret); @@ -292,7 +288,7 @@ fail_engine: } int -nouveau_object_dec(struct nouveau_object *object, bool suspend) +nvkm_object_dec(struct nvkm_object *object, bool suspend) { int ref = atomic_add_return(-1, &object->usecount); int ret; @@ -301,9 +297,9 @@ nouveau_object_dec(struct nouveau_object *object, bool suspend) if (ref == 0) { if (suspend) - ret = nouveau_object_decs(object); + ret = nvkm_object_decs(object); else - ret = nouveau_object_decf(object); + ret = nvkm_object_decf(object); if (ret) { atomic_inc(&object->usecount); @@ -315,10 +311,10 @@ nouveau_object_dec(struct nouveau_object *object, bool suspend) } void -nouveau_object_debug(void) +nvkm_object_debug(void) { -#ifdef NOUVEAU_OBJECT_MAGIC - struct nouveau_object *object; +#ifdef NVKM_OBJECT_MAGIC + struct nvkm_object *object; if (!list_empty(&_objlist)) { nv_fatal(NULL, "*******************************************\n"); nv_fatal(NULL, "* AIIIII! object(s) still exist!!!\n"); diff --git a/drivers/gpu/drm/nouveau/core/core/option.c b/drivers/gpu/drm/nouveau/nvkm/core/option.c index 9f6fcc5f66c2..19d153f8c8fd 100644 --- a/drivers/gpu/drm/nouveau/core/core/option.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/option.c @@ -21,12 +21,11 @@ * * Authors: Ben Skeggs */ - #include <core/option.h> #include <core/debug.h> const char * -nouveau_stropt(const char *optstr, const char *opt, int *arglen) +nvkm_stropt(const char *optstr, const char *opt, int *arglen) { while (optstr && *optstr != '\0') { int len = strcspn(optstr, ",="); @@ -52,11 +51,11 @@ nouveau_stropt(const char *optstr, const char *opt, int *arglen) } bool -nouveau_boolopt(const char *optstr, const char *opt, bool value) +nvkm_boolopt(const char *optstr, const char *opt, bool value) { int arglen; - optstr = nouveau_stropt(optstr, opt, &arglen); + optstr = nvkm_stropt(optstr, opt, &arglen); if (optstr) { if (!strncasecmpz(optstr, "0", arglen) || !strncasecmpz(optstr, "no", arglen) || @@ -75,7 +74,7 @@ nouveau_boolopt(const char *optstr, const char *opt, bool value) } int -nouveau_dbgopt(const char *optstr, const char *sub) +nvkm_dbgopt(const char *optstr, const char *sub) { int mode = 1, level = CONFIG_NOUVEAU_DEBUG_DEFAULT; diff --git a/drivers/gpu/drm/nouveau/core/core/parent.c b/drivers/gpu/drm/nouveau/nvkm/core/parent.c index 30a2911878f8..dd56cd1eeb38 100644 --- a/drivers/gpu/drm/nouveau/core/core/parent.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/parent.c @@ -21,25 +21,24 @@ * * Authors: Ben Skeggs */ - -#include <core/object.h> #include <core/parent.h> #include <core/client.h> +#include <core/engine.h> int -nouveau_parent_sclass(struct nouveau_object *parent, u16 handle, - struct nouveau_object **pengine, - struct nouveau_oclass **poclass) +nvkm_parent_sclass(struct nvkm_object *parent, u16 handle, + struct nvkm_object **pengine, + struct nvkm_oclass **poclass) { - struct nouveau_sclass *sclass; - struct nouveau_engine *engine; - struct nouveau_oclass *oclass; + struct nvkm_sclass *sclass; + struct nvkm_engine *engine; + struct nvkm_oclass *oclass; u64 mask; sclass = nv_parent(parent)->sclass; while (sclass) { if ((sclass->oclass->handle & 0xffff) == handle) { - *pengine = parent->engine; + *pengine = &parent->engine->subdev.object; *poclass = sclass->oclass; return 0; } @@ -54,7 +53,7 @@ nouveau_parent_sclass(struct nouveau_object *parent, u16 handle, if (nv_iclass(parent, NV_CLIENT_CLASS)) engine = nv_engine(nv_client(parent)->device); else - engine = nouveau_engine(parent, i); + engine = nvkm_engine(parent, i); if (engine) { oclass = engine->sclass; @@ -75,11 +74,11 @@ nouveau_parent_sclass(struct nouveau_object *parent, u16 handle, } int -nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size) +nvkm_parent_lclass(struct nvkm_object *parent, u32 *lclass, int size) { - struct nouveau_sclass *sclass; - struct nouveau_engine *engine; - struct nouveau_oclass *oclass; + struct nvkm_sclass *sclass; + struct nvkm_engine *engine; + struct nvkm_oclass *oclass; int nr = -1, i; u64 mask; @@ -92,7 +91,7 @@ nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size) mask = nv_parent(parent)->engine; while (i = __ffs64(mask), mask) { - engine = nouveau_engine(parent, i); + engine = nvkm_engine(parent, i); if (engine && (oclass = engine->sclass)) { while (oclass->ofuncs) { if (++nr < size) @@ -108,18 +107,17 @@ nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size) } int -nouveau_parent_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 pclass, - struct nouveau_oclass *sclass, u64 engcls, - int size, void **pobject) +nvkm_parent_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 pclass, + struct nvkm_oclass *sclass, u64 engcls, + int size, void **pobject) { - struct nouveau_parent *object; - struct nouveau_sclass *nclass; + struct nvkm_parent *object; + struct nvkm_sclass *nclass; int ret; - ret = nouveau_object_create_(parent, engine, oclass, pclass | - NV_PARENT_CLASS, size, pobject); + ret = nvkm_object_create_(parent, engine, oclass, pclass | + NV_PARENT_CLASS, size, pobject); object = *pobject; if (ret) return ret; @@ -141,21 +139,21 @@ nouveau_parent_create_(struct nouveau_object *parent, } void -nouveau_parent_destroy(struct nouveau_parent *parent) +nvkm_parent_destroy(struct nvkm_parent *parent) { - struct nouveau_sclass *sclass; + struct nvkm_sclass *sclass; while ((sclass = parent->sclass)) { parent->sclass = sclass->sclass; kfree(sclass); } - nouveau_object_destroy(&parent->base); + nvkm_object_destroy(&parent->object); } void -_nouveau_parent_dtor(struct nouveau_object *object) +_nvkm_parent_dtor(struct nvkm_object *object) { - nouveau_parent_destroy(nv_parent(object)); + nvkm_parent_destroy(nv_parent(object)); } diff --git a/drivers/gpu/drm/nouveau/core/core/printk.c b/drivers/gpu/drm/nouveau/nvkm/core/printk.c index 03e0060b13da..4a220eb91660 100644 --- a/drivers/gpu/drm/nouveau/core/core/printk.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/printk.c @@ -21,16 +21,14 @@ * * Authors: Ben Skeggs */ - -#include <core/object.h> -#include <core/client.h> -#include <core/subdev.h> #include <core/printk.h> +#include <core/client.h> +#include <core/device.h> int nv_info_debug_level = NV_DBG_INFO_NORMAL; void -nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...) +nv_printk_(struct nvkm_object *object, int level, const char *fmt, ...) { static const char name[] = { '!', 'E', 'W', ' ', 'D', 'T', 'P', 'S' }; const char *pfx; @@ -60,20 +58,27 @@ nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...) } if (object && !nv_iclass(object, NV_CLIENT_CLASS)) { - struct nouveau_object *device = object; - struct nouveau_object *subdev = object; + struct nvkm_object *device; + struct nvkm_object *subdev; char obuf[64], *ofmt = ""; - if (object->engine) { - snprintf(obuf, sizeof(obuf), "[0x%08x][%p]", - nv_hclass(object), object); - ofmt = obuf; - subdev = object->engine; - device = object->engine; + if (object->engine == NULL) { + subdev = object; + while (subdev && !nv_iclass(subdev, NV_SUBDEV_CLASS)) + subdev = subdev->parent; + } else { + subdev = &object->engine->subdev.object; } - if (subdev->parent) - device = subdev->parent; + device = subdev; + if (device->parent) + device = device->parent; + + if (object != subdev) { + snprintf(obuf, sizeof(obuf), "[0x%08x]", + nv_hclass(object)); + ofmt = obuf; + } if (level > nv_subdev(subdev)->debug) return; diff --git a/drivers/gpu/drm/nouveau/core/core/ramht.c b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c index f3b9bddc3875..ebd4d15479bd 100644 --- a/drivers/gpu/drm/nouveau/core/core/ramht.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c @@ -19,14 +19,13 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ - -#include <core/object.h> #include <core/ramht.h> +#include <core/engine.h> #include <subdev/bar.h> static u32 -nouveau_ramht_hash(struct nouveau_ramht *ramht, int chid, u32 handle) +nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle) { u32 hash = 0; @@ -41,13 +40,12 @@ nouveau_ramht_hash(struct nouveau_ramht *ramht, int chid, u32 handle) } int -nouveau_ramht_insert(struct nouveau_ramht *ramht, int chid, - u32 handle, u32 context) +nvkm_ramht_insert(struct nvkm_ramht *ramht, int chid, u32 handle, u32 context) { - struct nouveau_bar *bar = nouveau_bar(ramht); + struct nvkm_bar *bar = nvkm_bar(ramht); u32 co, ho; - co = ho = nouveau_ramht_hash(ramht, chid, handle); + co = ho = nvkm_ramht_hash(ramht, chid, handle); do { if (!nv_ro32(ramht, co + 4)) { nv_wo32(ramht, co + 0, handle); @@ -66,39 +64,39 @@ nouveau_ramht_insert(struct nouveau_ramht *ramht, int chid, } void -nouveau_ramht_remove(struct nouveau_ramht *ramht, int cookie) +nvkm_ramht_remove(struct nvkm_ramht *ramht, int cookie) { - struct nouveau_bar *bar = nouveau_bar(ramht); + struct nvkm_bar *bar = nvkm_bar(ramht); nv_wo32(ramht, cookie + 0, 0x00000000); nv_wo32(ramht, cookie + 4, 0x00000000); if (bar) bar->flush(bar); } -static struct nouveau_oclass -nouveau_ramht_oclass = { +static struct nvkm_oclass +nvkm_ramht_oclass = { .handle = 0x0000abcd, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = NULL, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, + .dtor = _nvkm_gpuobj_dtor, + .init = _nvkm_gpuobj_init, + .fini = _nvkm_gpuobj_fini, + .rd32 = _nvkm_gpuobj_rd32, + .wr32 = _nvkm_gpuobj_wr32, }, }; int -nouveau_ramht_new(struct nouveau_object *parent, struct nouveau_object *pargpu, - u32 size, u32 align, struct nouveau_ramht **pramht) +nvkm_ramht_new(struct nvkm_object *parent, struct nvkm_object *pargpu, + u32 size, u32 align, struct nvkm_ramht **pramht) { - struct nouveau_ramht *ramht; + struct nvkm_ramht *ramht; int ret; - ret = nouveau_gpuobj_create(parent, parent->engine ? - parent->engine : parent, /* <nv50 ramht */ - &nouveau_ramht_oclass, 0, pargpu, size, - align, NVOBJ_FLAG_ZERO_ALLOC, &ramht); + ret = nvkm_gpuobj_create(parent, parent->engine ? + &parent->engine->subdev.object : parent, /* <nv50 ramht */ + &nvkm_ramht_oclass, 0, pargpu, size, + align, NVOBJ_FLAG_ZERO_ALLOC, &ramht); *pramht = ramht; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/core/subdev.c b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c index 2ea5568b6cf5..c5fb3a793174 100644 --- a/drivers/gpu/drm/nouveau/core/core/subdev.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c @@ -21,14 +21,23 @@ * * Authors: Ben Skeggs */ - -#include <core/object.h> #include <core/subdev.h> #include <core/device.h> #include <core/option.h> +struct nvkm_subdev * +nvkm_subdev(void *obj, int idx) +{ + struct nvkm_object *object = nv_object(obj); + while (object && !nv_iclass(object, NV_SUBDEV_CLASS)) + object = object->parent; + if (object == NULL || nv_subidx(nv_subdev(object)) != idx) + object = nv_device(obj)->subdev[idx]; + return object ? nv_subdev(object) : NULL; +} + void -nouveau_subdev_reset(struct nouveau_object *subdev) +nvkm_subdev_reset(struct nvkm_object *subdev) { nv_trace(subdev, "resetting...\n"); nv_ofuncs(subdev)->fini(subdev, false); @@ -36,65 +45,64 @@ nouveau_subdev_reset(struct nouveau_object *subdev) } int -nouveau_subdev_init(struct nouveau_subdev *subdev) +nvkm_subdev_init(struct nvkm_subdev *subdev) { - int ret = nouveau_object_init(&subdev->base); + int ret = nvkm_object_init(&subdev->object); if (ret) return ret; - nouveau_subdev_reset(&subdev->base); + nvkm_subdev_reset(&subdev->object); return 0; } int -_nouveau_subdev_init(struct nouveau_object *object) +_nvkm_subdev_init(struct nvkm_object *object) { - return nouveau_subdev_init(nv_subdev(object)); + return nvkm_subdev_init(nv_subdev(object)); } int -nouveau_subdev_fini(struct nouveau_subdev *subdev, bool suspend) +nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend) { if (subdev->unit) { nv_mask(subdev, 0x000200, subdev->unit, 0x00000000); nv_mask(subdev, 0x000200, subdev->unit, subdev->unit); } - return nouveau_object_fini(&subdev->base, suspend); + return nvkm_object_fini(&subdev->object, suspend); } int -_nouveau_subdev_fini(struct nouveau_object *object, bool suspend) +_nvkm_subdev_fini(struct nvkm_object *object, bool suspend) { - return nouveau_subdev_fini(nv_subdev(object), suspend); + return nvkm_subdev_fini(nv_subdev(object), suspend); } void -nouveau_subdev_destroy(struct nouveau_subdev *subdev) +nvkm_subdev_destroy(struct nvkm_subdev *subdev) { int subidx = nv_hclass(subdev) & 0xff; nv_device(subdev)->subdev[subidx] = NULL; - nouveau_object_destroy(&subdev->base); + nvkm_object_destroy(&subdev->object); } void -_nouveau_subdev_dtor(struct nouveau_object *object) +_nvkm_subdev_dtor(struct nvkm_object *object) { - nouveau_subdev_destroy(nv_subdev(object)); + nvkm_subdev_destroy(nv_subdev(object)); } int -nouveau_subdev_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 pclass, - const char *subname, const char *sysname, - int size, void **pobject) +nvkm_subdev_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 pclass, + const char *subname, const char *sysname, + int size, void **pobject) { - struct nouveau_subdev *subdev; + struct nvkm_subdev *subdev; int ret; - ret = nouveau_object_create_(parent, engine, oclass, pclass | - NV_SUBDEV_CLASS, size, pobject); + ret = nvkm_object_create_(parent, engine, oclass, pclass | + NV_SUBDEV_CLASS, size, pobject); subdev = *pobject; if (ret) return ret; @@ -103,8 +111,8 @@ nouveau_subdev_create_(struct nouveau_object *parent, subdev->name = subname; if (parent) { - struct nouveau_device *device = nv_device(parent); - subdev->debug = nouveau_dbgopt(device->dbgopt, subname); + struct nvkm_device *device = nv_device(parent); + subdev->debug = nvkm_dbgopt(device->dbgopt, subname); subdev->mmio = nv_subdev(device)->mmio; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild new file mode 100644 index 000000000000..6bd3d756f32c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild @@ -0,0 +1,19 @@ +nvkm-y += nvkm/engine/falcon.o +nvkm-y += nvkm/engine/xtensa.o + +include $(src)/nvkm/engine/bsp/Kbuild +include $(src)/nvkm/engine/ce/Kbuild +include $(src)/nvkm/engine/cipher/Kbuild +include $(src)/nvkm/engine/device/Kbuild +include $(src)/nvkm/engine/disp/Kbuild +include $(src)/nvkm/engine/dmaobj/Kbuild +include $(src)/nvkm/engine/fifo/Kbuild +include $(src)/nvkm/engine/gr/Kbuild +include $(src)/nvkm/engine/mpeg/Kbuild +include $(src)/nvkm/engine/mspdec/Kbuild +include $(src)/nvkm/engine/msppp/Kbuild +include $(src)/nvkm/engine/msvld/Kbuild +include $(src)/nvkm/engine/pm/Kbuild +include $(src)/nvkm/engine/sec/Kbuild +include $(src)/nvkm/engine/sw/Kbuild +include $(src)/nvkm/engine/vp/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild new file mode 100644 index 000000000000..5ac9f9e1a283 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild @@ -0,0 +1 @@ +nvkm-y += nvkm/engine/bsp/g84.o diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c index 1e8e75c0684a..a0b1fd80fa93 100644 --- a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c @@ -21,17 +21,18 @@ * * Authors: Ben Skeggs, Ilia Mirkin */ - -#include <engine/xtensa.h> #include <engine/bsp.h> +#include <engine/xtensa.h> + +#include <core/engctx.h> /******************************************************************************* * BSP object classes ******************************************************************************/ -static struct nouveau_oclass -nv84_bsp_sclass[] = { - { 0x74b0, &nouveau_object_ofuncs }, +static struct nvkm_oclass +g84_bsp_sclass[] = { + { 0x74b0, &nvkm_object_ofuncs }, {}, }; @@ -39,16 +40,16 @@ nv84_bsp_sclass[] = { * BSP context ******************************************************************************/ -static struct nouveau_oclass -nv84_bsp_cclass = { +static struct nvkm_oclass +g84_bsp_cclass = { .handle = NV_ENGCTX(BSP, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_xtensa_engctx_ctor, - .dtor = _nouveau_engctx_dtor, - .init = _nouveau_engctx_init, - .fini = _nouveau_engctx_fini, - .rd32 = _nouveau_engctx_rd32, - .wr32 = _nouveau_engctx_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_xtensa_engctx_ctor, + .dtor = _nvkm_engctx_dtor, + .init = _nvkm_engctx_init, + .fini = _nvkm_engctx_fini, + .rd32 = _nvkm_engctx_rd32, + .wr32 = _nvkm_engctx_wr32, }, }; @@ -57,36 +58,36 @@ nv84_bsp_cclass = { ******************************************************************************/ static int -nv84_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_bsp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_xtensa *priv; + struct nvkm_xtensa *priv; int ret; - ret = nouveau_xtensa_create(parent, engine, oclass, 0x103000, true, - "PBSP", "bsp", &priv); + ret = nvkm_xtensa_create(parent, engine, oclass, 0x103000, true, + "PBSP", "bsp", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x04008000; - nv_engine(priv)->cclass = &nv84_bsp_cclass; - nv_engine(priv)->sclass = nv84_bsp_sclass; + nv_engine(priv)->cclass = &g84_bsp_cclass; + nv_engine(priv)->sclass = g84_bsp_sclass; priv->fifo_val = 0x1111; priv->unkd28 = 0x90044; return 0; } -struct nouveau_oclass -nv84_bsp_oclass = { +struct nvkm_oclass +g84_bsp_oclass = { .handle = NV_ENGINE(BSP, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_bsp_ctor, - .dtor = _nouveau_xtensa_dtor, - .init = _nouveau_xtensa_init, - .fini = _nouveau_xtensa_fini, - .rd32 = _nouveau_xtensa_rd32, - .wr32 = _nouveau_xtensa_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_bsp_ctor, + .dtor = _nvkm_xtensa_dtor, + .init = _nvkm_xtensa_init, + .fini = _nvkm_xtensa_fini, + .rd32 = _nvkm_xtensa_rd32, + .wr32 = _nvkm_xtensa_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild new file mode 100644 index 000000000000..858797453e0b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild @@ -0,0 +1,3 @@ +nvkm-y += nvkm/engine/ce/gt215.o +nvkm-y += nvkm/engine/ce/gf100.o +nvkm-y += nvkm/engine/ce/gk104.o diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc index 219850d53286..a558dfa4d76a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc @@ -1,4 +1,4 @@ -/* fuc microcode for copy engine on nva3- chipsets +/* fuc microcode for copy engine on gt215- chipsets * * Copyright 2011 Red Hat Inc. * @@ -23,26 +23,19 @@ * Authors: Ben Skeggs */ -/* To build for nva3:nvc0 - * m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h - * - * To build for nvc0- - * m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h - */ - -ifdef(`NVA3', -.section #nva3_pcopy_data -, -.section #nvc0_pcopy_data -) +#ifdef GT215 +.section #gt215_pce_data +#else +.section #gf100_pce_data +#endif ctx_object: .b32 0 -ifdef(`NVA3', +#ifdef GT215 ctx_dma: ctx_dma_query: .b32 0 ctx_dma_src: .b32 0 ctx_dma_dst: .b32 0 -,) +#endif .equ #ctx_dma_count 3 ctx_query_address_high: .b32 0 ctx_query_address_low: .b32 0 @@ -86,14 +79,14 @@ dispatch_table: // mthd 0x0140, PM_TRIGGER .b16 0x050 1 .b32 0x00010000 + #cmd_pm_trigger ~0xffffffff -ifdef(`NVA3', ` +#ifdef GT215 // mthd 0x0180-0x018c, DMA_ .b16 0x060 #ctx_dma_count dispatch_dma: .b32 0x00010000 + #cmd_dma ~0xffffffff .b32 0x00010000 + #cmd_dma ~0xffffffff .b32 0x00010000 + #cmd_dma ~0xffffffff -',) +#endif // mthd 0x0200-0x0218, SRC_TILE .b16 0x80 7 .b32 #ctx_src_tile_mode ~0x00000fff @@ -134,11 +127,11 @@ dispatch_dma: .b32 #ctx_query_counter ~0xffffffff .b16 0x800 0 -ifdef(`NVA3', -.section #nva3_pcopy_code -, -.section #nvc0_pcopy_code -) +#ifdef GT215 +.section #gt215_pce_code +#else +.section #gf100_pce_code +#endif main: clear b32 $r0 @@ -190,10 +183,10 @@ ih: swctx: mov $r4 0x7700 mov $xtargets $r4 -ifdef(`NVA3', ` +#ifdef GT215 // target 7 hardcoded to ctx dma object mov $xdbase $r0 -', ` // NVC0 +#else // read SCRATCH3 to decide if we are PCOPY0 or PCOPY1 mov $r4 0x2100 iord $r4 I[$r4 + 0] @@ -231,7 +224,7 @@ ifdef(`NVA3', ` shl b32 $r6 24 or $r4 $r6 mov $xdbase $r4 -') +#endif // 256-byte context, at start of data segment mov b32 $r4 $r0 sethi $r4 0x60000 @@ -271,7 +264,7 @@ chsw: bra e #chsw_finish_load bset $flags $p1 call #swctx -ifdef(`NVA3', +#ifdef GT215 // load dma objects back into TARGET regs mov $r5 #ctx_dma mov $r6 #ctx_dma_count @@ -282,8 +275,7 @@ ifdef(`NVA3', iowr I[$r8] $r7 sub b32 $r6 1 bra nc #chsw_load_ctx_dma -,) - +#endif chsw_finish_load: mov $r3 2 iowr I[$r2 + 0x200] $r3 @@ -397,7 +389,7 @@ cmd_pm_trigger: iowr I[$r2] $r3 ret -ifdef(`NVA3', +#ifdef GT215 // SET_DMA_* method handler // // Inputs: @@ -419,7 +411,7 @@ cmd_dma: shl b32 $r4 6 iowr I[$r4] $r3 ret -,) +#endif // Calculates the hw swizzle mask and adjusts the surface's xcnt to match // @@ -548,11 +540,11 @@ cmd_exec_set_surface_tiled: ld b32 $r7 D[$r5 + #ctx_src_tile_mode] extr $r9 $r7 8:11 extr $r8 $r7 4:7 -ifdef(`NVA3', +#ifdef GT215 add b32 $r8 2 -, +#else add b32 $r8 3 -) +#endif extr $r7 $r7 0:3 cmp b32 $r7 0xe bra ne #xtile64 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3 new file mode 100644 index 000000000000..36f0a99ac7a2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3 @@ -0,0 +1,2 @@ +#define GF100 +#include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h index 98cc4216a372..d9af6e4e4585 100644 --- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nvc0_pcopy_data[] = { +uint32_t gf100_pce_data[] = { /* 0x0000: ctx_object */ 0x00000000, /* 0x0004: ctx_query_address_high */ @@ -171,7 +171,7 @@ uint32_t nvc0_pcopy_data[] = { 0x00000800, }; -uint32_t nvc0_pcopy_code[] = { +uint32_t gf100_pce_code[] = { /* 0x0000: main */ 0x04fe04bd, 0x3517f000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3 new file mode 100644 index 000000000000..07bda93cfd79 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3 @@ -0,0 +1,2 @@ +#define GT215 +#include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h index 241b27201206..f42c0d0d6cee 100644 --- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nva3_pcopy_data[] = { +uint32_t gt215_pce_data[] = { /* 0x0000: ctx_object */ 0x00000000, /* 0x0004: ctx_dma */ @@ -183,7 +183,7 @@ uint32_t nva3_pcopy_data[] = { 0x00000800, }; -uint32_t nva3_pcopy_code[] = { +uint32_t gt215_pce_code[] = { /* 0x0000: main */ 0x04fe04bd, 0x3517f000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c new file mode 100644 index 000000000000..2d2e549c2e34 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c @@ -0,0 +1,166 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include <engine/ce.h> +#include <engine/falcon.h> +#include "fuc/gf100.fuc3.h" + +struct gf100_ce_priv { + struct nvkm_falcon base; +}; + +/******************************************************************************* + * Copy object classes + ******************************************************************************/ + +static struct nvkm_oclass +gf100_ce0_sclass[] = { + { 0x90b5, &nvkm_object_ofuncs }, + {}, +}; + +static struct nvkm_oclass +gf100_ce1_sclass[] = { + { 0x90b8, &nvkm_object_ofuncs }, + {}, +}; + +/******************************************************************************* + * PCE context + ******************************************************************************/ + +static struct nvkm_ofuncs +gf100_ce_context_ofuncs = { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, +}; + +static struct nvkm_oclass +gf100_ce0_cclass = { + .handle = NV_ENGCTX(CE0, 0xc0), + .ofuncs = &gf100_ce_context_ofuncs, +}; + +static struct nvkm_oclass +gf100_ce1_cclass = { + .handle = NV_ENGCTX(CE1, 0xc0), + .ofuncs = &gf100_ce_context_ofuncs, +}; + +/******************************************************************************* + * PCE engine/subdev functions + ******************************************************************************/ + +static int +gf100_ce_init(struct nvkm_object *object) +{ + struct gf100_ce_priv *priv = (void *)object; + int ret; + + ret = nvkm_falcon_init(&priv->base); + if (ret) + return ret; + + nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0); + return 0; +} + +static int +gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gf100_ce_priv *priv; + int ret; + + ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, true, + "PCE0", "ce0", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000040; + nv_subdev(priv)->intr = gt215_ce_intr; + nv_engine(priv)->cclass = &gf100_ce0_cclass; + nv_engine(priv)->sclass = gf100_ce0_sclass; + nv_falcon(priv)->code.data = gf100_pce_code; + nv_falcon(priv)->code.size = sizeof(gf100_pce_code); + nv_falcon(priv)->data.data = gf100_pce_data; + nv_falcon(priv)->data.size = sizeof(gf100_pce_data); + return 0; +} + +static int +gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gf100_ce_priv *priv; + int ret; + + ret = nvkm_falcon_create(parent, engine, oclass, 0x105000, true, + "PCE1", "ce1", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000080; + nv_subdev(priv)->intr = gt215_ce_intr; + nv_engine(priv)->cclass = &gf100_ce1_cclass; + nv_engine(priv)->sclass = gf100_ce1_sclass; + nv_falcon(priv)->code.data = gf100_pce_code; + nv_falcon(priv)->code.size = sizeof(gf100_pce_code); + nv_falcon(priv)->data.data = gf100_pce_data; + nv_falcon(priv)->data.size = sizeof(gf100_pce_data); + return 0; +} + +struct nvkm_oclass +gf100_ce0_oclass = { + .handle = NV_ENGINE(CE0, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_ce0_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gf100_ce_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, + }, +}; + +struct nvkm_oclass +gf100_ce1_oclass = { + .handle = NV_ENGINE(CE1, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_ce1_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gf100_ce_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c new file mode 100644 index 000000000000..a998932fae45 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c @@ -0,0 +1,173 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include <engine/ce.h> + +#include <core/engctx.h> + +struct gk104_ce_priv { + struct nvkm_engine base; +}; + +/******************************************************************************* + * Copy object classes + ******************************************************************************/ + +static struct nvkm_oclass +gk104_ce_sclass[] = { + { 0xa0b5, &nvkm_object_ofuncs }, + {}, +}; + +/******************************************************************************* + * PCE context + ******************************************************************************/ + +static struct nvkm_ofuncs +gk104_ce_context_ofuncs = { + .ctor = _nvkm_engctx_ctor, + .dtor = _nvkm_engctx_dtor, + .init = _nvkm_engctx_init, + .fini = _nvkm_engctx_fini, + .rd32 = _nvkm_engctx_rd32, + .wr32 = _nvkm_engctx_wr32, +}; + +static struct nvkm_oclass +gk104_ce_cclass = { + .handle = NV_ENGCTX(CE0, 0xc0), + .ofuncs = &gk104_ce_context_ofuncs, +}; + +/******************************************************************************* + * PCE engine/subdev functions + ******************************************************************************/ + +static void +gk104_ce_intr(struct nvkm_subdev *subdev) +{ + const int ce = nv_subidx(subdev) - NVDEV_ENGINE_CE0; + struct gk104_ce_priv *priv = (void *)subdev; + u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000)); + + if (stat) { + nv_warn(priv, "unhandled intr 0x%08x\n", stat); + nv_wr32(priv, 0x104908 + (ce * 0x1000), stat); + } +} + +static int +gk104_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gk104_ce_priv *priv; + int ret; + + ret = nvkm_engine_create(parent, engine, oclass, true, + "PCE0", "ce0", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000040; + nv_subdev(priv)->intr = gk104_ce_intr; + nv_engine(priv)->cclass = &gk104_ce_cclass; + nv_engine(priv)->sclass = gk104_ce_sclass; + return 0; +} + +static int +gk104_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gk104_ce_priv *priv; + int ret; + + ret = nvkm_engine_create(parent, engine, oclass, true, + "PCE1", "ce1", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000080; + nv_subdev(priv)->intr = gk104_ce_intr; + nv_engine(priv)->cclass = &gk104_ce_cclass; + nv_engine(priv)->sclass = gk104_ce_sclass; + return 0; +} + +static int +gk104_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gk104_ce_priv *priv; + int ret; + + ret = nvkm_engine_create(parent, engine, oclass, true, + "PCE2", "ce2", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00200000; + nv_subdev(priv)->intr = gk104_ce_intr; + nv_engine(priv)->cclass = &gk104_ce_cclass; + nv_engine(priv)->sclass = gk104_ce_sclass; + return 0; +} + +struct nvkm_oclass +gk104_ce0_oclass = { + .handle = NV_ENGINE(CE0, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_ce0_ctor, + .dtor = _nvkm_engine_dtor, + .init = _nvkm_engine_init, + .fini = _nvkm_engine_fini, + }, +}; + +struct nvkm_oclass +gk104_ce1_oclass = { + .handle = NV_ENGINE(CE1, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_ce1_ctor, + .dtor = _nvkm_engine_dtor, + .init = _nvkm_engine_init, + .fini = _nvkm_engine_fini, + }, +}; + +struct nvkm_oclass +gk104_ce2_oclass = { + .handle = NV_ENGINE(CE2, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_ce2_ctor, + .dtor = _nvkm_engine_dtor, + .init = _nvkm_engine_init, + .fini = _nvkm_engine_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index abb410ef09ea..d8bb4293bc11 100644 --- a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -21,57 +21,53 @@ * * Authors: Ben Skeggs */ - +#include <engine/ce.h> #include <engine/falcon.h> #include <engine/fifo.h> -#include <engine/copy.h> - -#include <subdev/fb.h> -#include <subdev/vm.h> +#include "fuc/gt215.fuc3.h" #include <core/client.h> +#include <core/device.h> #include <core/enum.h> - -#include "fuc/nva3.fuc.h" - -struct nva3_copy_priv { - struct nouveau_falcon base; +struct gt215_ce_priv { + struct nvkm_falcon base; }; /******************************************************************************* * Copy object classes ******************************************************************************/ -static struct nouveau_oclass -nva3_copy_sclass[] = { - { 0x85b5, &nouveau_object_ofuncs }, +static struct nvkm_oclass +gt215_ce_sclass[] = { + { 0x85b5, &nvkm_object_ofuncs }, {} }; /******************************************************************************* - * PCOPY context + * PCE context ******************************************************************************/ -static struct nouveau_oclass -nva3_copy_cclass = { - .handle = NV_ENGCTX(COPY0, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +gt215_ce_cclass = { + .handle = NV_ENGCTX(CE0, 0xa3), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PCOPY engine/subdev functions + * PCE engine/subdev functions ******************************************************************************/ -static const struct nouveau_enum nva3_copy_isr_error_name[] = { +static const struct nvkm_enum +gt215_ce_isr_error_name[] = { { 0x0001, "ILLEGAL_MTHD" }, { 0x0002, "INVALID_ENUM" }, { 0x0003, "INVALID_BITFIELD" }, @@ -79,12 +75,12 @@ static const struct nouveau_enum nva3_copy_isr_error_name[] = { }; void -nva3_copy_intr(struct nouveau_subdev *subdev) +gt215_ce_intr(struct nvkm_subdev *subdev) { - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_falcon *falcon = (void *)subdev; - struct nouveau_object *engctx; + struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_engine *engine = nv_engine(subdev); + struct nvkm_falcon *falcon = (void *)subdev; + struct nvkm_object *engctx; u32 dispatch = nv_ro32(falcon, 0x01c); u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff; @@ -95,14 +91,14 @@ nva3_copy_intr(struct nouveau_subdev *subdev) u32 data = nv_ro32(falcon, 0x044); int chid; - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); chid = pfifo->chid(pfifo, engctx); if (stat & 0x00000040) { nv_error(falcon, "DISPATCH_ERROR ["); - nouveau_enum_print(nva3_copy_isr_error_name, ssta); + nvkm_enum_print(gt215_ce_isr_error_name, ssta); pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nouveau_client_name(engctx), subc, + chid, inst << 12, nvkm_client_name(engctx), subc, mthd, data); nv_wo32(falcon, 0x004, 0x00000040); stat &= ~0x00000040; @@ -113,44 +109,44 @@ nva3_copy_intr(struct nouveau_subdev *subdev) nv_wo32(falcon, 0x004, stat); } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } static int -nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { bool enable = (nv_device(parent)->chipset != 0xaf); - struct nva3_copy_priv *priv; + struct gt215_ce_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, enable, - "PCE0", "copy0", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, enable, + "PCE0", "ce0", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00802000; - nv_subdev(priv)->intr = nva3_copy_intr; - nv_engine(priv)->cclass = &nva3_copy_cclass; - nv_engine(priv)->sclass = nva3_copy_sclass; - nv_falcon(priv)->code.data = nva3_pcopy_code; - nv_falcon(priv)->code.size = sizeof(nva3_pcopy_code); - nv_falcon(priv)->data.data = nva3_pcopy_data; - nv_falcon(priv)->data.size = sizeof(nva3_pcopy_data); + nv_subdev(priv)->intr = gt215_ce_intr; + nv_engine(priv)->cclass = >215_ce_cclass; + nv_engine(priv)->sclass = gt215_ce_sclass; + nv_falcon(priv)->code.data = gt215_pce_code; + nv_falcon(priv)->code.size = sizeof(gt215_pce_code); + nv_falcon(priv)->data.data = gt215_pce_data; + nv_falcon(priv)->data.size = sizeof(gt215_pce_data); return 0; } -struct nouveau_oclass -nva3_copy_oclass = { - .handle = NV_ENGINE(COPY0, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_copy_ctor, - .dtor = _nouveau_falcon_dtor, - .init = _nouveau_falcon_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +gt215_ce_oclass = { + .handle = NV_ENGINE(CE0, 0xa3), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gt215_ce_ctor, + .dtor = _nvkm_falcon_dtor, + .init = _nvkm_falcon_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild new file mode 100644 index 000000000000..fa39945327ce --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild @@ -0,0 +1 @@ +nvkm-y += nvkm/engine/cipher/g84.o diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c index ea5c42f31791..13f30428a305 100644 --- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c @@ -21,20 +21,15 @@ * * Authors: Ben Skeggs */ +#include <engine/cipher.h> +#include <engine/fifo.h> #include <core/client.h> -#include <core/os.h> -#include <core/enum.h> #include <core/engctx.h> -#include <core/gpuobj.h> - -#include <subdev/fb.h> - -#include <engine/fifo.h> -#include <engine/crypt.h> +#include <core/enum.h> -struct nv84_crypt_priv { - struct nouveau_engine base; +struct g84_cipher_priv { + struct nvkm_engine base; }; /******************************************************************************* @@ -42,16 +37,16 @@ struct nv84_crypt_priv { ******************************************************************************/ static int -nv84_crypt_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_cipher_object_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_gpuobj *obj; + struct nvkm_gpuobj *obj; int ret; - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, - 16, 16, 0, &obj); + ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, + 16, 16, 0, &obj); *pobject = nv_object(obj); if (ret) return ret; @@ -63,44 +58,45 @@ nv84_crypt_object_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs -nv84_crypt_ofuncs = { - .ctor = nv84_crypt_object_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, +static struct nvkm_ofuncs +g84_cipher_ofuncs = { + .ctor = g84_cipher_object_ctor, + .dtor = _nvkm_gpuobj_dtor, + .init = _nvkm_gpuobj_init, + .fini = _nvkm_gpuobj_fini, + .rd32 = _nvkm_gpuobj_rd32, + .wr32 = _nvkm_gpuobj_wr32, }; -static struct nouveau_oclass -nv84_crypt_sclass[] = { - { 0x74c1, &nv84_crypt_ofuncs }, +static struct nvkm_oclass +g84_cipher_sclass[] = { + { 0x74c1, &g84_cipher_ofuncs }, {} }; /******************************************************************************* - * PCRYPT context + * PCIPHER context ******************************************************************************/ -static struct nouveau_oclass -nv84_crypt_cclass = { - .handle = NV_ENGCTX(CRYPT, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_engctx_ctor, - .dtor = _nouveau_engctx_dtor, - .init = _nouveau_engctx_init, - .fini = _nouveau_engctx_fini, - .rd32 = _nouveau_engctx_rd32, - .wr32 = _nouveau_engctx_wr32, +static struct nvkm_oclass +g84_cipher_cclass = { + .handle = NV_ENGCTX(CIPHER, 0x84), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_engctx_ctor, + .dtor = _nvkm_engctx_dtor, + .init = _nvkm_engctx_init, + .fini = _nvkm_engctx_fini, + .rd32 = _nvkm_engctx_rd32, + .wr32 = _nvkm_engctx_wr32, }, }; /******************************************************************************* - * PCRYPT engine/subdev functions + * PCIPHER engine/subdev functions ******************************************************************************/ -static const struct nouveau_bitfield nv84_crypt_intr_mask[] = { +static const struct nvkm_bitfield +g84_cipher_intr_mask[] = { { 0x00000001, "INVALID_STATE" }, { 0x00000002, "ILLEGAL_MTHD" }, { 0x00000004, "ILLEGAL_CLASS" }, @@ -110,63 +106,63 @@ static const struct nouveau_bitfield nv84_crypt_intr_mask[] = { }; static void -nv84_crypt_intr(struct nouveau_subdev *subdev) +g84_cipher_intr(struct nvkm_subdev *subdev) { - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nv84_crypt_priv *priv = (void *)subdev; + struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_engine *engine = nv_engine(subdev); + struct nvkm_object *engctx; + struct g84_cipher_priv *priv = (void *)subdev; u32 stat = nv_rd32(priv, 0x102130); u32 mthd = nv_rd32(priv, 0x102190); u32 data = nv_rd32(priv, 0x102194); u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff; int chid; - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); chid = pfifo->chid(pfifo, engctx); if (stat) { nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv84_crypt_intr_mask, stat); + nvkm_bitfield_print(g84_cipher_intr_mask, stat); pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n", - chid, (u64)inst << 12, nouveau_client_name(engctx), + chid, (u64)inst << 12, nvkm_client_name(engctx), mthd, data); } nv_wr32(priv, 0x102130, stat); nv_wr32(priv, 0x10200c, 0x10); - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } static int -nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_cipher_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv84_crypt_priv *priv; + struct g84_cipher_priv *priv; int ret; - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCRYPT", "crypt", &priv); + ret = nvkm_engine_create(parent, engine, oclass, true, + "PCIPHER", "cipher", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00004000; - nv_subdev(priv)->intr = nv84_crypt_intr; - nv_engine(priv)->cclass = &nv84_crypt_cclass; - nv_engine(priv)->sclass = nv84_crypt_sclass; + nv_subdev(priv)->intr = g84_cipher_intr; + nv_engine(priv)->cclass = &g84_cipher_cclass; + nv_engine(priv)->sclass = g84_cipher_sclass; return 0; } static int -nv84_crypt_init(struct nouveau_object *object) +g84_cipher_init(struct nvkm_object *object) { - struct nv84_crypt_priv *priv = (void *)object; + struct g84_cipher_priv *priv = (void *)object; int ret; - ret = nouveau_engine_init(&priv->base); + ret = nvkm_engine_init(&priv->base); if (ret) return ret; @@ -176,13 +172,13 @@ nv84_crypt_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass -nv84_crypt_oclass = { - .handle = NV_ENGINE(CRYPT, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_crypt_ctor, - .dtor = _nouveau_engine_dtor, - .init = nv84_crypt_init, - .fini = _nouveau_engine_fini, +struct nvkm_oclass +g84_cipher_oclass = { + .handle = NV_ENGINE(CIPHER, 0x84), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_cipher_ctor, + .dtor = _nvkm_engine_dtor, + .init = g84_cipher_init, + .fini = _nvkm_engine_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild new file mode 100644 index 000000000000..de1bf092b2b2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild @@ -0,0 +1,12 @@ +nvkm-y += nvkm/engine/device/acpi.o +nvkm-y += nvkm/engine/device/base.o +nvkm-y += nvkm/engine/device/ctrl.o +nvkm-y += nvkm/engine/device/nv04.o +nvkm-y += nvkm/engine/device/nv10.o +nvkm-y += nvkm/engine/device/nv20.o +nvkm-y += nvkm/engine/device/nv30.o +nvkm-y += nvkm/engine/device/nv40.o +nvkm-y += nvkm/engine/device/nv50.o +nvkm-y += nvkm/engine/device/gf100.o +nvkm-y += nvkm/engine/device/gk104.o +nvkm-y += nvkm/engine/device/gm100.o diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c index 4dbf0ba89e5c..f42706e1d5db 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/acpi.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c @@ -21,14 +21,15 @@ * * Authors: Ben Skeggs */ - #include "acpi.h" +#include <core/device.h> + #ifdef CONFIG_ACPI static int nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data) { - struct nouveau_device *device = + struct nvkm_device *device = container_of(nb, typeof(*device), acpi.nb); struct acpi_bus_event *info = data; @@ -40,7 +41,7 @@ nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data) #endif int -nvkm_acpi_fini(struct nouveau_device *device, bool suspend) +nvkm_acpi_fini(struct nvkm_device *device, bool suspend) { #ifdef CONFIG_ACPI unregister_acpi_notifier(&device->acpi.nb); @@ -49,7 +50,7 @@ nvkm_acpi_fini(struct nouveau_device *device, bool suspend) } int -nvkm_acpi_init(struct nouveau_device *device) +nvkm_acpi_init(struct nvkm_device *device) { #ifdef CONFIG_ACPI device->acpi.nb.notifier_call = nvkm_acpi_ntfy; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h new file mode 100644 index 000000000000..82dd359ddfa4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h @@ -0,0 +1,8 @@ +#ifndef __NVKM_DEVICE_ACPI_H__ +#define __NVKM_DEVICE_ACPI_H__ +#include <core/os.h> +struct nvkm_device; + +int nvkm_acpi_init(struct nvkm_device *); +int nvkm_acpi_fini(struct nvkm_device *, bool); +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 137e0b0faeae..29bd539af183 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -21,28 +21,27 @@ * * Authors: Ben Skeggs */ +#include "priv.h" +#include "acpi.h" -#include <core/object.h> -#include <core/device.h> #include <core/client.h> #include <core/option.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - +#include <core/notify.h> +#include <core/parent.h> #include <subdev/bios.h> #include <subdev/fb.h> #include <subdev/instmem.h> -#include "priv.h" -#include "acpi.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static DEFINE_MUTEX(nv_devices_mutex); static LIST_HEAD(nv_devices); -struct nouveau_device * -nouveau_device_find(u64 name) +struct nvkm_device * +nvkm_device_find(u64 name) { - struct nouveau_device *device, *match = NULL; + struct nvkm_device *device, *match = NULL; mutex_lock(&nv_devices_mutex); list_for_each_entry(device, &nv_devices, head) { if (device->handle == name) { @@ -55,9 +54,9 @@ nouveau_device_find(u64 name) } int -nouveau_device_list(u64 *name, int size) +nvkm_device_list(u64 *name, int size) { - struct nouveau_device *device; + struct nvkm_device *device; int nr = 0; mutex_lock(&nv_devices_mutex); list_for_each_entry(device, &nv_devices, head) { @@ -69,20 +68,20 @@ nouveau_device_list(u64 *name, int size) } /****************************************************************************** - * nouveau_devobj (0x0080): class implementation + * nvkm_devobj (0x0080): class implementation *****************************************************************************/ -struct nouveau_devobj { - struct nouveau_parent base; - struct nouveau_object *subdev[NVDEV_SUBDEV_NR]; +struct nvkm_devobj { + struct nvkm_parent base; + struct nvkm_object *subdev[NVDEV_SUBDEV_NR]; }; static int -nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size) +nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size) { - struct nouveau_device *device = nv_device(object); - struct nouveau_fb *pfb = nouveau_fb(device); - struct nouveau_instmem *imem = nouveau_instmem(device); + struct nvkm_device *device = nv_device(object); + struct nvkm_fb *pfb = nvkm_fb(device); + struct nvkm_instmem *imem = nvkm_instmem(device); union { struct nv_device_info_v0 v0; } *args = data; @@ -147,12 +146,11 @@ nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size) } static int -nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) +nvkm_devobj_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { switch (mthd) { case NV_DEVICE_V0_INFO: - return nouveau_devobj_info(object, data, size); + return nvkm_devobj_info(object, data, size); default: break; } @@ -160,45 +158,45 @@ nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd, } static u8 -nouveau_devobj_rd08(struct nouveau_object *object, u64 addr) +nvkm_devobj_rd08(struct nvkm_object *object, u64 addr) { return nv_rd08(object->engine, addr); } static u16 -nouveau_devobj_rd16(struct nouveau_object *object, u64 addr) +nvkm_devobj_rd16(struct nvkm_object *object, u64 addr) { return nv_rd16(object->engine, addr); } static u32 -nouveau_devobj_rd32(struct nouveau_object *object, u64 addr) +nvkm_devobj_rd32(struct nvkm_object *object, u64 addr) { return nv_rd32(object->engine, addr); } static void -nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data) +nvkm_devobj_wr08(struct nvkm_object *object, u64 addr, u8 data) { nv_wr08(object->engine, addr, data); } static void -nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data) +nvkm_devobj_wr16(struct nvkm_object *object, u64 addr, u16 data) { nv_wr16(object->engine, addr, data); } static void -nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data) +nvkm_devobj_wr32(struct nvkm_object *object, u64 addr, u32 data) { nv_wr32(object->engine, addr, data); } static int -nouveau_devobj_map(struct nouveau_object *object, u64 *addr, u32 *size) +nvkm_devobj_map(struct nvkm_object *object, u64 *addr, u32 *size) { - struct nouveau_device *device = nv_device(object); + struct nvkm_device *device = nv_device(object); *addr = nv_device_resource_start(device, 0); *size = nv_device_resource_len(device, 0); return 0; @@ -209,7 +207,7 @@ static const u64 disable_map[] = { [NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_GPIO] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_I2C] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_CLOCK] = NV_DEVICE_V0_DISABLE_CORE, + [NVDEV_SUBDEV_CLK ] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_MXM] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_MC] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE, @@ -218,74 +216,75 @@ static const u64 disable_map[] = { [NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_VM] = NV_DEVICE_V0_DISABLE_CORE, + [NVDEV_SUBDEV_MMU] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_BAR] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_VOLT] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_THERM] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_SUBDEV_PWR] = NV_DEVICE_V0_DISABLE_CORE, + [NVDEV_SUBDEV_PMU] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_FUSE] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_ENGINE_PERFMON] = NV_DEVICE_V0_DISABLE_CORE, + [NVDEV_ENGINE_PM ] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_ENGINE_FIFO] = NV_DEVICE_V0_DISABLE_FIFO, [NVDEV_ENGINE_SW] = NV_DEVICE_V0_DISABLE_FIFO, - [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GRAPH, + [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GR, [NVDEV_ENGINE_MPEG] = NV_DEVICE_V0_DISABLE_MPEG, [NVDEV_ENGINE_ME] = NV_DEVICE_V0_DISABLE_ME, [NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP, - [NVDEV_ENGINE_CRYPT] = NV_DEVICE_V0_DISABLE_CRYPT, + [NVDEV_ENGINE_CIPHER] = NV_DEVICE_V0_DISABLE_CIPHER, [NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP, - [NVDEV_ENGINE_PPP] = NV_DEVICE_V0_DISABLE_PPP, - [NVDEV_ENGINE_COPY0] = NV_DEVICE_V0_DISABLE_COPY0, - [NVDEV_ENGINE_COPY1] = NV_DEVICE_V0_DISABLE_COPY1, - [NVDEV_ENGINE_COPY2] = NV_DEVICE_V0_DISABLE_COPY1, + [NVDEV_ENGINE_MSPPP] = NV_DEVICE_V0_DISABLE_MSPPP, + [NVDEV_ENGINE_CE0] = NV_DEVICE_V0_DISABLE_CE0, + [NVDEV_ENGINE_CE1] = NV_DEVICE_V0_DISABLE_CE1, + [NVDEV_ENGINE_CE2] = NV_DEVICE_V0_DISABLE_CE2, [NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC, - [NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC, + [NVDEV_ENGINE_MSENC] = NV_DEVICE_V0_DISABLE_MSENC, [NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP, + [NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD, + [NVDEV_ENGINE_SEC] = NV_DEVICE_V0_DISABLE_SEC, [NVDEV_SUBDEV_NR] = 0, }; static void -nouveau_devobj_dtor(struct nouveau_object *object) +nvkm_devobj_dtor(struct nvkm_object *object) { - struct nouveau_devobj *devobj = (void *)object; + struct nvkm_devobj *devobj = (void *)object; int i; for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) - nouveau_object_ref(NULL, &devobj->subdev[i]); + nvkm_object_ref(NULL, &devobj->subdev[i]); - nouveau_parent_destroy(&devobj->base); + nvkm_parent_destroy(&devobj->base); } -static struct nouveau_oclass -nouveau_devobj_oclass_super = { +static struct nvkm_oclass +nvkm_devobj_oclass_super = { .handle = NV_DEVICE, - .ofuncs = &(struct nouveau_ofuncs) { - .dtor = nouveau_devobj_dtor, - .init = _nouveau_parent_init, - .fini = _nouveau_parent_fini, - .mthd = nouveau_devobj_mthd, - .map = nouveau_devobj_map, - .rd08 = nouveau_devobj_rd08, - .rd16 = nouveau_devobj_rd16, - .rd32 = nouveau_devobj_rd32, - .wr08 = nouveau_devobj_wr08, - .wr16 = nouveau_devobj_wr16, - .wr32 = nouveau_devobj_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .dtor = nvkm_devobj_dtor, + .init = _nvkm_parent_init, + .fini = _nvkm_parent_fini, + .mthd = nvkm_devobj_mthd, + .map = nvkm_devobj_map, + .rd08 = nvkm_devobj_rd08, + .rd16 = nvkm_devobj_rd16, + .rd32 = nvkm_devobj_rd32, + .wr08 = nvkm_devobj_wr08, + .wr16 = nvkm_devobj_wr16, + .wr32 = nvkm_devobj_wr32, } }; static int -nouveau_devobj_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv_device_v0 v0; } *args = data; - struct nouveau_client *client = nv_client(parent); - struct nouveau_device *device; - struct nouveau_devobj *devobj; + struct nvkm_client *client = nv_client(parent); + struct nvkm_device *device; + struct nvkm_devobj *devobj; u32 boot0, strap; u64 disable, mmio_base, mmio_size; void __iomem *map; @@ -302,22 +301,22 @@ nouveau_devobj_ctor(struct nouveau_object *parent, /* give priviledged clients register access */ if (client->super) - oclass = &nouveau_devobj_oclass_super; + oclass = &nvkm_devobj_oclass_super; /* find the device subdev that matches what the client requested */ device = nv_device(client->device); if (args->v0.device != ~0) { - device = nouveau_device_find(args->v0.device); + device = nvkm_device_find(args->v0.device); if (!device) return -ENODEV; } - ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, - nouveau_control_oclass, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_FIFO) | - (1ULL << NVDEV_ENGINE_DISP) | - (1ULL << NVDEV_ENGINE_PERFMON), &devobj); + ret = nvkm_parent_create(parent, nv_object(device), oclass, 0, + nvkm_control_oclass, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_FIFO) | + (1ULL << NVDEV_ENGINE_DISP) | + (1ULL << NVDEV_ENGINE_PM), &devobj); *pobject = nv_object(devobj); if (ret) return ret; @@ -400,8 +399,8 @@ nouveau_devobj_ctor(struct nouveau_object *parent, case NV_30: ret = nv30_identify(device); break; case NV_40: ret = nv40_identify(device); break; case NV_50: ret = nv50_identify(device); break; - case NV_C0: ret = nvc0_identify(device); break; - case NV_E0: ret = nve0_identify(device); break; + case NV_C0: ret = gf100_identify(device); break; + case NV_E0: ret = gk104_identify(device); break; case GM100: ret = gm100_identify(device); break; default: ret = -EINVAL; @@ -436,7 +435,7 @@ nouveau_devobj_ctor(struct nouveau_object *parent, } else if ( (args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY)) { device->cname = "NULL"; - device->oclass[NVDEV_SUBDEV_VBIOS] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass; } if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_MMIO) && @@ -454,14 +453,12 @@ nouveau_devobj_ctor(struct nouveau_object *parent, continue; if (device->subdev[i]) { - nouveau_object_ref(device->subdev[i], - &devobj->subdev[i]); + nvkm_object_ref(device->subdev[i], &devobj->subdev[i]); continue; } - ret = nouveau_object_ctor(nv_object(device), NULL, - oclass, NULL, i, - &devobj->subdev[i]); + ret = nvkm_object_ctor(nv_object(device), NULL, oclass, + NULL, i, &devobj->subdev[i]); if (ret == -ENODEV) continue; if (ret) @@ -479,15 +476,15 @@ nouveau_devobj_ctor(struct nouveau_object *parent, * subdev in turn as they're created. */ while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { - struct nouveau_object *subdev = devobj->subdev[c++]; + struct nvkm_object *subdev = devobj->subdev[c++]; if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_inc(subdev); + ret = nvkm_object_inc(subdev); if (ret) return ret; atomic_dec(&nv_object(device)->usecount); } else if (subdev) { - nouveau_subdev_reset(subdev); + nvkm_subdev_reset(subdev); } } } @@ -495,28 +492,47 @@ nouveau_devobj_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs -nouveau_devobj_ofuncs = { - .ctor = nouveau_devobj_ctor, - .dtor = nouveau_devobj_dtor, - .init = _nouveau_parent_init, - .fini = _nouveau_parent_fini, - .mthd = nouveau_devobj_mthd, +static struct nvkm_ofuncs +nvkm_devobj_ofuncs = { + .ctor = nvkm_devobj_ctor, + .dtor = nvkm_devobj_dtor, + .init = _nvkm_parent_init, + .fini = _nvkm_parent_fini, + .mthd = nvkm_devobj_mthd, }; /****************************************************************************** - * nouveau_device: engine functions + * nvkm_device: engine functions *****************************************************************************/ -static struct nouveau_oclass -nouveau_device_sclass[] = { - { 0x0080, &nouveau_devobj_ofuncs }, +struct nvkm_device * +nv_device(void *obj) +{ + struct nvkm_object *device = nv_object(obj); + if (device->engine == NULL) { + while (device && device->parent) + device = device->parent; + } else { + device = &nv_object(obj)->engine->subdev.object; + if (device && device->parent) + device = device->parent; + } +#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA + if (unlikely(!device)) + nv_assert("BAD CAST -> NvDevice, 0x%08x\n", nv_hclass(obj)); +#endif + return (void *)device; +} + +static struct nvkm_oclass +nvkm_device_sclass[] = { + { 0x0080, &nvkm_devobj_ofuncs }, {} }; static int -nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { if (!WARN_ON(size != 0)) { notify->size = 0; @@ -528,21 +544,21 @@ nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size, } static const struct nvkm_event_func -nouveau_device_event_func = { - .ctor = nouveau_device_event_ctor, +nvkm_device_event_func = { + .ctor = nvkm_device_event_ctor, }; static int -nouveau_device_fini(struct nouveau_object *object, bool suspend) +nvkm_device_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_device *device = (void *)object; - struct nouveau_object *subdev; + struct nvkm_device *device = (void *)object; + struct nvkm_object *subdev; int ret, i; for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { if ((subdev = device->subdev[i])) { if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_dec(subdev, suspend); + ret = nvkm_object_dec(subdev, suspend); if (ret && suspend) goto fail; } @@ -554,7 +570,7 @@ fail: for (; ret && i < NVDEV_SUBDEV_NR; i++) { if ((subdev = device->subdev[i])) { if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_inc(subdev); + ret = nvkm_object_inc(subdev); if (ret) { /* XXX */ } @@ -566,10 +582,10 @@ fail: } static int -nouveau_device_init(struct nouveau_object *object) +nvkm_device_init(struct nvkm_object *object) { - struct nouveau_device *device = (void *)object; - struct nouveau_object *subdev; + struct nvkm_device *device = (void *)object; + struct nvkm_object *subdev; int ret, i = 0; ret = nvkm_acpi_init(device); @@ -579,11 +595,11 @@ nouveau_device_init(struct nouveau_object *object) for (i = 0; i < NVDEV_SUBDEV_NR; i++) { if ((subdev = device->subdev[i])) { if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nouveau_object_inc(subdev); + ret = nvkm_object_inc(subdev); if (ret) goto fail; } else { - nouveau_subdev_reset(subdev); + nvkm_subdev_reset(subdev); } } } @@ -593,7 +609,7 @@ fail: for (--i; ret && i >= 0; i--) { if ((subdev = device->subdev[i])) { if (!nv_iclass(subdev, NV_ENGINE_CLASS)) - nouveau_object_dec(subdev, false); + nvkm_object_dec(subdev, false); } } @@ -603,9 +619,9 @@ fail: } static void -nouveau_device_dtor(struct nouveau_object *object) +nvkm_device_dtor(struct nvkm_object *object) { - struct nouveau_device *device = (void *)object; + struct nvkm_device *device = (void *)object; nvkm_event_fini(&device->event); @@ -616,11 +632,11 @@ nouveau_device_dtor(struct nouveau_object *object) if (nv_subdev(device)->mmio) iounmap(nv_subdev(device)->mmio); - nouveau_engine_destroy(&device->base); + nvkm_engine_destroy(&device->engine); } resource_size_t -nv_device_resource_start(struct nouveau_device *device, unsigned int bar) +nv_device_resource_start(struct nvkm_device *device, unsigned int bar) { if (nv_device_is_pci(device)) { return pci_resource_start(device->pdev, bar); @@ -635,7 +651,7 @@ nv_device_resource_start(struct nouveau_device *device, unsigned int bar) } resource_size_t -nv_device_resource_len(struct nouveau_device *device, unsigned int bar) +nv_device_resource_len(struct nvkm_device *device, unsigned int bar) { if (nv_device_is_pci(device)) { return pci_resource_len(device->pdev, bar); @@ -650,7 +666,7 @@ nv_device_resource_len(struct nouveau_device *device, unsigned int bar) } int -nv_device_get_irq(struct nouveau_device *device, bool stall) +nv_device_get_irq(struct nvkm_device *device, bool stall) { if (nv_device_is_pci(device)) { return device->pdev->irq; @@ -660,22 +676,22 @@ nv_device_get_irq(struct nouveau_device *device, bool stall) } } -static struct nouveau_oclass -nouveau_device_oclass = { +static struct nvkm_oclass +nvkm_device_oclass = { .handle = NV_ENGINE(DEVICE, 0x00), - .ofuncs = &(struct nouveau_ofuncs) { - .dtor = nouveau_device_dtor, - .init = nouveau_device_init, - .fini = nouveau_device_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .dtor = nvkm_device_dtor, + .init = nvkm_device_init, + .fini = nvkm_device_fini, }, }; int -nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name, - const char *sname, const char *cfg, const char *dbg, - int length, void **pobject) +nvkm_device_create_(void *dev, enum nv_bus_type type, u64 name, + const char *sname, const char *cfg, const char *dbg, + int length, void **pobject) { - struct nouveau_device *device; + struct nvkm_device *device; int ret = -EEXIST; mutex_lock(&nv_devices_mutex); @@ -684,17 +700,17 @@ nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name, goto done; } - ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true, - "DEVICE", "device", length, pobject); + ret = nvkm_engine_create_(NULL, NULL, &nvkm_device_oclass, true, + "DEVICE", "device", length, pobject); device = *pobject; if (ret) goto done; switch (type) { - case NOUVEAU_BUS_PCI: + case NVKM_BUS_PCI: device->pdev = dev; break; - case NOUVEAU_BUS_PLATFORM: + case NVKM_BUS_PLATFORM: device->platformdev = dev; break; } @@ -703,12 +719,11 @@ nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name, device->dbgopt = dbg; device->name = sname; - nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE"); - nv_engine(device)->sclass = nouveau_device_sclass; + nv_subdev(device)->debug = nvkm_dbgopt(device->dbgopt, "DEVICE"); + nv_engine(device)->sclass = nvkm_device_sclass; list_add(&device->head, &nv_devices); - ret = nvkm_event_init(&nouveau_device_event_func, 1, 1, - &device->event); + ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); done: mutex_unlock(&nv_devices_mutex); return ret; diff --git a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c index e34101a3490e..0b794b13cec3 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c @@ -21,25 +21,22 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "priv.h" #include <core/client.h> -#include <core/object.h> -#include <nvif/unpack.h> +#include <subdev/clk.h> + #include <nvif/class.h> #include <nvif/ioctl.h> - -#include <subdev/clock.h> - -#include "priv.h" +#include <nvif/unpack.h> static int -nouveau_control_mthd_pstate_info(struct nouveau_object *object, - void *data, u32 size) +nvkm_control_mthd_pstate_info(struct nvkm_object *object, void *data, u32 size) { union { struct nvif_control_pstate_info_v0 v0; } *args = data; - struct nouveau_clock *clk = nouveau_clock(object); + struct nvkm_clk *clk = nvkm_clk(object); int ret; nv_ioctl(object, "control pstate info size %d\n", size); @@ -67,16 +64,15 @@ nouveau_control_mthd_pstate_info(struct nouveau_object *object, } static int -nouveau_control_mthd_pstate_attr(struct nouveau_object *object, - void *data, u32 size) +nvkm_control_mthd_pstate_attr(struct nvkm_object *object, void *data, u32 size) { union { struct nvif_control_pstate_attr_v0 v0; } *args = data; - struct nouveau_clock *clk = nouveau_clock(object); - struct nouveau_clocks *domain; - struct nouveau_pstate *pstate; - struct nouveau_cstate *cstate; + struct nvkm_clk *clk = nvkm_clk(object); + struct nvkm_domain *domain; + struct nvkm_pstate *pstate; + struct nvkm_cstate *cstate; int i = 0, j = -1; u32 lo, hi; int ret; @@ -141,13 +137,12 @@ nouveau_control_mthd_pstate_attr(struct nouveau_object *object, } static int -nouveau_control_mthd_pstate_user(struct nouveau_object *object, - void *data, u32 size) +nvkm_control_mthd_pstate_user(struct nvkm_object *object, void *data, u32 size) { union { struct nvif_control_pstate_user_v0 v0; } *args = data; - struct nouveau_clock *clk = nouveau_clock(object); + struct nvkm_clk *clk = nvkm_clk(object); int ret; nv_ioctl(object, "control pstate user size %d\n", size); @@ -161,45 +156,44 @@ nouveau_control_mthd_pstate_user(struct nouveau_object *object, return ret; if (args->v0.pwrsrc >= 0) { - ret |= nouveau_clock_ustate(clk, args->v0.ustate, args->v0.pwrsrc); + ret |= nvkm_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc); } else { - ret |= nouveau_clock_ustate(clk, args->v0.ustate, 0); - ret |= nouveau_clock_ustate(clk, args->v0.ustate, 1); + ret |= nvkm_clk_ustate(clk, args->v0.ustate, 0); + ret |= nvkm_clk_ustate(clk, args->v0.ustate, 1); } return ret; } static int -nouveau_control_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) +nvkm_control_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { switch (mthd) { case NVIF_CONTROL_PSTATE_INFO: - return nouveau_control_mthd_pstate_info(object, data, size); + return nvkm_control_mthd_pstate_info(object, data, size); case NVIF_CONTROL_PSTATE_ATTR: - return nouveau_control_mthd_pstate_attr(object, data, size); + return nvkm_control_mthd_pstate_attr(object, data, size); case NVIF_CONTROL_PSTATE_USER: - return nouveau_control_mthd_pstate_user(object, data, size); + return nvkm_control_mthd_pstate_user(object, data, size); default: break; } return -EINVAL; } -static struct nouveau_ofuncs -nouveau_control_ofuncs = { - .ctor = _nouveau_object_ctor, - .dtor = nouveau_object_destroy, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - .mthd = nouveau_control_mthd, +static struct nvkm_ofuncs +nvkm_control_ofuncs = { + .ctor = _nvkm_object_ctor, + .dtor = nvkm_object_destroy, + .init = nvkm_object_init, + .fini = nvkm_object_fini, + .mthd = nvkm_control_mthd, }; -struct nouveau_oclass -nouveau_control_oclass[] = { +struct nvkm_oclass +nvkm_control_oclass[] = { { .handle = NVIF_IOCTL_NEW_V0_CONTROL, - .ofuncs = &nouveau_control_ofuncs + .ofuncs = &nvkm_control_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c new file mode 100644 index 000000000000..82b38d7e9730 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -0,0 +1,358 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include <subdev/bios.h> +#include <subdev/bus.h> +#include <subdev/gpio.h> +#include <subdev/i2c.h> +#include <subdev/fuse.h> +#include <subdev/clk.h> +#include <subdev/therm.h> +#include <subdev/mxm.h> +#include <subdev/devinit.h> +#include <subdev/mc.h> +#include <subdev/timer.h> +#include <subdev/fb.h> +#include <subdev/ltc.h> +#include <subdev/ibus.h> +#include <subdev/instmem.h> +#include <subdev/mmu.h> +#include <subdev/bar.h> +#include <subdev/pmu.h> +#include <subdev/volt.h> + +#include <engine/dmaobj.h> +#include <engine/fifo.h> +#include <engine/sw.h> +#include <engine/gr.h> +#include <engine/mspdec.h> +#include <engine/bsp.h> +#include <engine/msvld.h> +#include <engine/msppp.h> +#include <engine/ce.h> +#include <engine/disp.h> +#include <engine/pm.h> + +int +gf100_identify(struct nvkm_device *device) +{ + switch (device->chipset) { + case 0xc0: + device->cname = "GF100"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xc4: + device->cname = "GF104"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xc3: + device->cname = "GF106"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xce: + device->cname = "GF114"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xcf: + device->cname = "GF116"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xc1: + device->cname = "GF108"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xc8: + device->cname = "GF110"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xd9: + device->cname = "GF119"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + case 0xd7: + device->cname = "GF117"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; + break; + default: + nv_fatal(device, "unknown Fermi chipset\n"); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c new file mode 100644 index 000000000000..bf5893458a47 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -0,0 +1,326 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include <subdev/bios.h> +#include <subdev/bus.h> +#include <subdev/gpio.h> +#include <subdev/i2c.h> +#include <subdev/fuse.h> +#include <subdev/clk.h> +#include <subdev/therm.h> +#include <subdev/mxm.h> +#include <subdev/devinit.h> +#include <subdev/mc.h> +#include <subdev/timer.h> +#include <subdev/fb.h> +#include <subdev/ltc.h> +#include <subdev/ibus.h> +#include <subdev/instmem.h> +#include <subdev/mmu.h> +#include <subdev/bar.h> +#include <subdev/pmu.h> +#include <subdev/volt.h> + +#include <engine/dmaobj.h> +#include <engine/fifo.h> +#include <engine/sw.h> +#include <engine/gr.h> +#include <engine/disp.h> +#include <engine/ce.h> +#include <engine/bsp.h> +#include <engine/msvld.h> +#include <engine/mspdec.h> +#include <engine/msppp.h> +#include <engine/pm.h> + +int +gk104_identify(struct nvkm_device *device) +{ + switch (device->chipset) { + case 0xe4: + device->cname = "GK104"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; + break; + case 0xe7: + device->cname = "GK107"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; + break; + case 0xe6: + device->cname = "GK106"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; + break; + case 0xea: + device->cname = "GK20A"; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; + break; + case 0xf0: + device->cname = "GK110"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; + break; + case 0xf1: + device->cname = "GK110B"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; + break; + case 0x106: + device->cname = "GK208B"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + break; + case 0x108: + device->cname = "GK208"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; + break; + default: + nv_fatal(device, "unknown Kepler chipset\n"); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 4e74a3376de8..539561ed3281 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -21,13 +21,14 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/bios.h> #include <subdev/bus.h> #include <subdev/gpio.h> #include <subdev/i2c.h> #include <subdev/fuse.h> -#include <subdev/clock.h> +#include <subdev/clk.h> #include <subdev/therm.h> #include <subdev/mxm.h> #include <subdev/devinit.h> @@ -37,108 +38,108 @@ #include <subdev/ltc.h> #include <subdev/ibus.h> #include <subdev/instmem.h> -#include <subdev/vm.h> +#include <subdev/mmu.h> #include <subdev/bar.h> -#include <subdev/pwr.h> +#include <subdev/pmu.h> #include <subdev/volt.h> -#include <engine/device.h> #include <engine/dmaobj.h> #include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> +#include <engine/sw.h> +#include <engine/gr.h> #include <engine/disp.h> -#include <engine/copy.h> +#include <engine/ce.h> #include <engine/bsp.h> -#include <engine/vp.h> -#include <engine/ppp.h> -#include <engine/perfmon.h> +#include <engine/msvld.h> +#include <engine/mspdec.h> +#include <engine/msppp.h> +#include <engine/pm.h> int -gm100_identify(struct nouveau_device *device) +gm100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x117: device->cname = "GM107"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; - device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; - device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; #if 0 - device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; #endif - device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; #if 0 - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; #endif break; case 0x124: device->cname = "GM204"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; - device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; #if 0 /* looks to be some non-trivial changes */ - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; /* priv ring says no to 0x10eb14 writes */ device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; - device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; - device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; - device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif - device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; #if 0 - device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; #endif device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; #if 0 - device->oclass[NVDEV_ENGINE_COPY0 ] = &gm204_copy0_oclass; - device->oclass[NVDEV_ENGINE_COPY1 ] = &gm204_copy1_oclass; - device->oclass[NVDEV_ENGINE_COPY2 ] = &gm204_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; - device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; - device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; #endif break; default: diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index 573b55f5c2f9..5a2ae043b478 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -21,63 +21,63 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/bios.h> #include <subdev/bus.h> #include <subdev/i2c.h> -#include <subdev/clock.h> +#include <subdev/clk.h> #include <subdev/devinit.h> #include <subdev/mc.h> #include <subdev/timer.h> #include <subdev/fb.h> #include <subdev/instmem.h> -#include <subdev/vm.h> +#include <subdev/mmu.h> -#include <engine/device.h> #include <engine/dmaobj.h> #include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> +#include <engine/sw.h> +#include <engine/gr.h> #include <engine/disp.h> int -nv04_identify(struct nouveau_device *device) +nv04_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x04: device->cname = "NV04"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x05: device->cname = "NV05"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 183a85a6204e..94a1ca45e94a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -21,178 +21,178 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/bios.h> #include <subdev/bus.h> #include <subdev/gpio.h> #include <subdev/i2c.h> -#include <subdev/clock.h> +#include <subdev/clk.h> #include <subdev/devinit.h> #include <subdev/mc.h> #include <subdev/timer.h> #include <subdev/fb.h> #include <subdev/instmem.h> -#include <subdev/vm.h> +#include <subdev/mmu.h> -#include <engine/device.h> #include <engine/dmaobj.h> #include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> +#include <engine/sw.h> +#include <engine/gr.h> #include <engine/disp.h> int -nv10_identify(struct nouveau_device *device) +nv10_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x10: device->cname = "NV10"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x15: device->cname = "NV15"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x16: device->cname = "NV16"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1a: device->cname = "nForce"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x11: device->cname = "NV11"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x17: device->cname = "NV17"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1f: device->cname = "nForce2"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x18: device->cname = "NV18"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index aa564c68a920..d5ec8937df68 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -21,105 +21,105 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/bios.h> #include <subdev/bus.h> #include <subdev/gpio.h> #include <subdev/i2c.h> -#include <subdev/clock.h> +#include <subdev/clk.h> #include <subdev/therm.h> #include <subdev/devinit.h> #include <subdev/mc.h> #include <subdev/timer.h> #include <subdev/fb.h> #include <subdev/instmem.h> -#include <subdev/vm.h> +#include <subdev/mmu.h> -#include <engine/device.h> #include <engine/dmaobj.h> #include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> +#include <engine/sw.h> +#include <engine/gr.h> #include <engine/disp.h> int -nv20_identify(struct nouveau_device *device) +nv20_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x20: device->cname = "NV20"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x25: device->cname = "NV25"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x28: device->cname = "NV28"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x2a: device->cname = "NV2A"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index 11bd31da82ab..dda09621e898 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -21,126 +21,126 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/bios.h> #include <subdev/bus.h> #include <subdev/gpio.h> #include <subdev/i2c.h> -#include <subdev/clock.h> +#include <subdev/clk.h> #include <subdev/devinit.h> #include <subdev/mc.h> #include <subdev/timer.h> #include <subdev/fb.h> #include <subdev/instmem.h> -#include <subdev/vm.h> +#include <subdev/mmu.h> -#include <engine/device.h> #include <engine/dmaobj.h> #include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> +#include <engine/sw.h> +#include <engine/gr.h> #include <engine/mpeg.h> #include <engine/disp.h> int -nv30_identify(struct nouveau_device *device) +nv30_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x30: device->cname = "NV30"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x35: device->cname = "NV35"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x31: device->cname = "NV31"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x36: device->cname = "NV36"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x34: device->cname = "NV34"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index e96c223cb797..c6301361d14f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -21,41 +21,41 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/bios.h> #include <subdev/bus.h> -#include <subdev/vm.h> +#include <subdev/mmu.h> #include <subdev/gpio.h> #include <subdev/i2c.h> -#include <subdev/clock.h> +#include <subdev/clk.h> #include <subdev/therm.h> #include <subdev/devinit.h> #include <subdev/mc.h> #include <subdev/timer.h> #include <subdev/fb.h> #include <subdev/instmem.h> -#include <subdev/vm.h> +#include <subdev/mmu.h> #include <subdev/volt.h> -#include <engine/device.h> #include <engine/dmaobj.h> #include <engine/fifo.h> -#include <engine/software.h> -#include <engine/graph.h> +#include <engine/sw.h> +#include <engine/gr.h> #include <engine/mpeg.h> #include <engine/disp.h> -#include <engine/perfmon.h> +#include <engine/pm.h> int -nv40_identify(struct nouveau_device *device) +nv40_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x40: device->cname = "NV40"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -63,22 +63,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x41: device->cname = "NV41"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -86,22 +86,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x42: device->cname = "NV42"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -109,22 +109,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x43: device->cname = "NV43"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -132,22 +132,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x45: device->cname = "NV45"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -155,22 +155,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x47: device->cname = "G70"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -178,22 +178,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x49: device->cname = "G71"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -201,22 +201,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4b: device->cname = "G73"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; @@ -224,22 +224,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x44: device->cname = "NV44"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; @@ -247,22 +247,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x46: device->cname = "G72"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; @@ -270,22 +270,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4a: device->cname = "NV44A"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; @@ -293,22 +293,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4c: device->cname = "C61"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; @@ -316,22 +316,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4e: device->cname = "C51"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; @@ -339,22 +339,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x63: device->cname = "C73"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; @@ -362,22 +362,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x67: device->cname = "C67"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; @@ -385,22 +385,22 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x68: device->cname = "C68"; - device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; - device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; @@ -408,15 +408,15 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; - device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; - device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; default: nv_fatal(device, "unknown Curie chipset\n"); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c new file mode 100644 index 000000000000..249b84454612 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -0,0 +1,478 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include <subdev/bios.h> +#include <subdev/bus.h> +#include <subdev/gpio.h> +#include <subdev/i2c.h> +#include <subdev/fuse.h> +#include <subdev/clk.h> +#include <subdev/therm.h> +#include <subdev/mxm.h> +#include <subdev/devinit.h> +#include <subdev/mc.h> +#include <subdev/timer.h> +#include <subdev/fb.h> +#include <subdev/instmem.h> +#include <subdev/mmu.h> +#include <subdev/bar.h> +#include <subdev/pmu.h> +#include <subdev/volt.h> + +#include <engine/dmaobj.h> +#include <engine/fifo.h> +#include <engine/sw.h> +#include <engine/gr.h> +#include <engine/mpeg.h> +#include <engine/vp.h> +#include <engine/cipher.h> +#include <engine/sec.h> +#include <engine/bsp.h> +#include <engine/msvld.h> +#include <engine/mspdec.h> +#include <engine/msppp.h> +#include <engine/ce.h> +#include <engine/disp.h> +#include <engine/pm.h> + +int +nv50_identify(struct nvkm_device *device) +{ + switch (device->chipset) { + case 0x50: + device->cname = "G80"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; + break; + case 0x84: + device->cname = "G84"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; + device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; + device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; + break; + case 0x86: + device->cname = "G86"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; + device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; + device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; + break; + case 0x92: + device->cname = "G92"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; + device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; + device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; + break; + case 0x94: + device->cname = "G94"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; + device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; + device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; + break; + case 0x96: + device->cname = "G96"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; + device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; + device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; + break; + case 0x98: + device->cname = "G98"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; + device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; + break; + case 0xa0: + device->cname = "G200"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; + device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; + device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; + break; + case 0xaa: + device->cname = "MCP77/MCP78"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; + device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; + break; + case 0xac: + device->cname = "MCP79/MCP7A"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; + device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; + break; + case 0xa3: + device->cname = "GT215"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; + break; + case 0xa5: + device->cname = "GT216"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; + break; + case 0xa8: + device->cname = "GT218"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; + break; + case 0xaf: + device->cname = "MCP89"; + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; + device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; + device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; + device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass; + device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; + device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; + device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; + device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; + device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; + device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; + device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; + break; + default: + nv_fatal(device, "unknown Tesla chipset\n"); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h new file mode 100644 index 000000000000..8d3590e7bd87 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h @@ -0,0 +1,16 @@ +#ifndef __NVKM_DEVICE_PRIV_H__ +#define __NVKM_DEVICE_PRIV_H__ +#include <core/device.h> + +extern struct nvkm_oclass nvkm_control_oclass[]; + +int nv04_identify(struct nvkm_device *); +int nv10_identify(struct nvkm_device *); +int nv20_identify(struct nvkm_device *); +int nv30_identify(struct nvkm_device *); +int nv40_identify(struct nvkm_device *); +int nv50_identify(struct nvkm_device *); +int gf100_identify(struct nvkm_device *); +int gk104_identify(struct nvkm_device *); +int gm100_identify(struct nvkm_device *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild new file mode 100644 index 000000000000..16a4e2a37008 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild @@ -0,0 +1,29 @@ +nvkm-y += nvkm/engine/disp/base.o +nvkm-y += nvkm/engine/disp/conn.o +nvkm-y += nvkm/engine/disp/outp.o +nvkm-y += nvkm/engine/disp/outpdp.o +nvkm-y += nvkm/engine/disp/nv04.o +nvkm-y += nvkm/engine/disp/nv50.o +nvkm-y += nvkm/engine/disp/g84.o +nvkm-y += nvkm/engine/disp/g94.o +nvkm-y += nvkm/engine/disp/gt200.o +nvkm-y += nvkm/engine/disp/gt215.o +nvkm-y += nvkm/engine/disp/gf110.o +nvkm-y += nvkm/engine/disp/gk104.o +nvkm-y += nvkm/engine/disp/gk110.o +nvkm-y += nvkm/engine/disp/gm107.o +nvkm-y += nvkm/engine/disp/gm204.o +nvkm-y += nvkm/engine/disp/dacnv50.o +nvkm-y += nvkm/engine/disp/dport.o +nvkm-y += nvkm/engine/disp/hdagt215.o +nvkm-y += nvkm/engine/disp/hdagf110.o +nvkm-y += nvkm/engine/disp/hdmig84.o +nvkm-y += nvkm/engine/disp/hdmigt215.o +nvkm-y += nvkm/engine/disp/hdmigf110.o +nvkm-y += nvkm/engine/disp/hdmigk104.o +nvkm-y += nvkm/engine/disp/piornv50.o +nvkm-y += nvkm/engine/disp/sornv50.o +nvkm-y += nvkm/engine/disp/sorg94.o +nvkm-y += nvkm/engine/disp/sorgf110.o +nvkm-y += nvkm/engine/disp/sorgm204.o +nvkm-y += nvkm/engine/disp/vga.o diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c index 64b84667f3a5..23d1b5c0dc16 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c @@ -21,21 +21,23 @@ * * Authors: Ben Skeggs */ +#include "priv.h" +#include "conn.h" +#include "outp.h" + +#include <core/notify.h> +#include <subdev/bios.h> +#include <subdev/bios/dcb.h> -#include <core/os.h> -#include <nvif/unpack.h> #include <nvif/class.h> #include <nvif/event.h> - -#include "priv.h" -#include "outp.h" -#include "conn.h" +#include <nvif/unpack.h> int -nouveau_disp_vblank_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_disp_vblank_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { - struct nouveau_disp *disp = + struct nvkm_disp *disp = container_of(notify->event, typeof(*disp), vblank); union { struct nvif_notify_head_req_v0 v0; @@ -55,17 +57,17 @@ nouveau_disp_vblank_ctor(struct nouveau_object *object, void *data, u32 size, } void -nouveau_disp_vblank(struct nouveau_disp *disp, int head) +nvkm_disp_vblank(struct nvkm_disp *disp, int head) { struct nvif_notify_head_rep_v0 rep = {}; nvkm_event_send(&disp->vblank, 1, head, &rep, sizeof(rep)); } static int -nouveau_disp_hpd_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_disp_hpd_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { - struct nouveau_disp *disp = + struct nvkm_disp *disp = container_of(notify->event, typeof(*disp), hpd); union { struct nvif_notify_conn_req_v0 v0; @@ -91,15 +93,14 @@ nouveau_disp_hpd_ctor(struct nouveau_object *object, void *data, u32 size, } static const struct nvkm_event_func -nouveau_disp_hpd_func = { - .ctor = nouveau_disp_hpd_ctor +nvkm_disp_hpd_func = { + .ctor = nvkm_disp_hpd_ctor }; int -nouveau_disp_ntfy(struct nouveau_object *object, u32 type, - struct nvkm_event **event) +nvkm_disp_ntfy(struct nvkm_object *object, u32 type, struct nvkm_event **event) { - struct nouveau_disp *disp = (void *)object->engine; + struct nvkm_disp *disp = (void *)object->engine; switch (type) { case NV04_DISP_NTFY_VBLANK: *event = &disp->vblank; @@ -114,9 +115,9 @@ nouveau_disp_ntfy(struct nouveau_object *object, u32 type, } int -_nouveau_disp_fini(struct nouveau_object *object, bool suspend) +_nvkm_disp_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_disp *disp = (void *)object; + struct nvkm_disp *disp = (void *)object; struct nvkm_output *outp; int ret; @@ -126,7 +127,7 @@ _nouveau_disp_fini(struct nouveau_object *object, bool suspend) goto fail_outp; } - return nouveau_engine_fini(&disp->base, suspend); + return nvkm_engine_fini(&disp->base, suspend); fail_outp: list_for_each_entry_continue_reverse(outp, &disp->outp, head) { @@ -137,13 +138,13 @@ fail_outp: } int -_nouveau_disp_init(struct nouveau_object *object) +_nvkm_disp_init(struct nvkm_object *object) { - struct nouveau_disp *disp = (void *)object; + struct nvkm_disp *disp = (void *)object; struct nvkm_output *outp; int ret; - ret = nouveau_engine_init(&disp->base); + ret = nvkm_engine_init(&disp->base); if (ret) return ret; @@ -164,9 +165,9 @@ fail_outp: } void -_nouveau_disp_dtor(struct nouveau_object *object) +_nvkm_disp_dtor(struct nvkm_object *object) { - struct nouveau_disp *disp = (void *)object; + struct nvkm_disp *disp = (void *)object; struct nvkm_output *outp, *outt; nvkm_event_fini(&disp->vblank); @@ -174,32 +175,30 @@ _nouveau_disp_dtor(struct nouveau_object *object) if (disp->outp.next) { list_for_each_entry_safe(outp, outt, &disp->outp, head) { - nouveau_object_ref(NULL, (struct nouveau_object **)&outp); + nvkm_object_ref(NULL, (struct nvkm_object **)&outp); } } - nouveau_engine_destroy(&disp->base); + nvkm_engine_destroy(&disp->base); } int -nouveau_disp_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int heads, - const char *intname, const char *extname, - int length, void **pobject) +nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int heads, const char *intname, + const char *extname, int length, void **pobject) { - struct nouveau_disp_impl *impl = (void *)oclass; - struct nouveau_bios *bios = nouveau_bios(parent); - struct nouveau_disp *disp; - struct nouveau_oclass **sclass; - struct nouveau_object *object; + struct nvkm_disp_impl *impl = (void *)oclass; + struct nvkm_bios *bios = nvkm_bios(parent); + struct nvkm_disp *disp; + struct nvkm_oclass **sclass; + struct nvkm_object *object; struct dcb_output dcbE; u8 hpd = 0, ver, hdr; u32 data; int ret, i; - ret = nouveau_engine_create_(parent, engine, oclass, true, - intname, extname, length, pobject); + ret = nvkm_engine_create_(parent, engine, oclass, true, intname, + extname, length, pobject); disp = *pobject; if (ret) return ret; @@ -225,12 +224,11 @@ nouveau_disp_create_(struct nouveau_object *parent, sclass++; } - nouveau_object_ctor(*pobject, *pobject, oclass, - &dcbE, i, &object); + nvkm_object_ctor(*pobject, NULL, oclass, &dcbE, i, &object); hpd = max(hpd, (u8)(dcbE.connector + 1)); } - ret = nvkm_event_init(&nouveau_disp_hpd_func, 3, hpd, &disp->hpd); + ret = nvkm_event_init(&nvkm_disp_hpd_func, 3, hpd, &disp->hpd); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c index 1496b567dd4a..cf03e0240ced 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c @@ -21,21 +21,20 @@ * * Authors: Ben Skeggs */ - -#include <core/os.h> -#include <nvif/event.h> +#include "conn.h" +#include "outp.h" +#include "priv.h" #include <subdev/gpio.h> -#include "conn.h" -#include "outp.h" +#include <nvif/event.h> static int nvkm_connector_hpd(struct nvkm_notify *notify) { struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd); - struct nouveau_disp *disp = nouveau_disp(conn); - struct nouveau_gpio *gpio = nouveau_gpio(conn); + struct nvkm_disp *disp = nvkm_disp(conn); + struct nvkm_gpio *gpio = nvkm_gpio(conn); const struct nvkm_gpio_ntfy_rep *line = notify->data; struct nvif_notify_conn_rep_v0 rep; int index = conn->index; @@ -53,41 +52,41 @@ nvkm_connector_hpd(struct nvkm_notify *notify) } int -_nvkm_connector_fini(struct nouveau_object *object, bool suspend) +_nvkm_connector_fini(struct nvkm_object *object, bool suspend) { struct nvkm_connector *conn = (void *)object; nvkm_notify_put(&conn->hpd); - return nouveau_object_fini(&conn->base, suspend); + return nvkm_object_fini(&conn->base, suspend); } int -_nvkm_connector_init(struct nouveau_object *object) +_nvkm_connector_init(struct nvkm_object *object) { struct nvkm_connector *conn = (void *)object; - int ret = nouveau_object_init(&conn->base); + int ret = nvkm_object_init(&conn->base); if (ret == 0) nvkm_notify_get(&conn->hpd); return ret; } void -_nvkm_connector_dtor(struct nouveau_object *object) +_nvkm_connector_dtor(struct nvkm_object *object) { struct nvkm_connector *conn = (void *)object; nvkm_notify_fini(&conn->hpd); - nouveau_object_destroy(&conn->base); + nvkm_object_destroy(&conn->base); } int -nvkm_connector_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, +nvkm_connector_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, struct nvbios_connE *info, int index, int length, void **pobject) { static const u8 hpd[] = { 0x07, 0x08, 0x51, 0x52, 0x5e, 0x5f, 0x60 }; - struct nouveau_gpio *gpio = nouveau_gpio(parent); - struct nouveau_disp *disp = (void *)engine; + struct nvkm_disp *disp = nvkm_disp(parent); + struct nvkm_gpio *gpio = nvkm_gpio(parent); struct nvkm_connector *conn; struct nvkm_output *outp; struct dcb_gpio_func func; @@ -101,7 +100,7 @@ nvkm_connector_create_(struct nouveau_object *parent, } } - ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject); + ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); conn = *pobject; if (ret) return ret; @@ -145,10 +144,10 @@ nvkm_connector_create_(struct nouveau_object *parent, } int -_nvkm_connector_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *info, u32 index, - struct nouveau_object **pobject) +_nvkm_connector_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *info, u32 index, + struct nvkm_object **pobject) { struct nvkm_connector *conn; int ret; @@ -161,11 +160,11 @@ _nvkm_connector_ctor(struct nouveau_object *parent, return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nvkm_connector_oclass = &(struct nvkm_connector_impl) { .base = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_connector_ctor, .dtor = _nvkm_connector_dtor, .init = _nvkm_connector_init, diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h index 55e5f5c82c14..c87a061f7f7d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/conn.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h @@ -1,10 +1,13 @@ #ifndef __NVKM_DISP_CONN_H__ #define __NVKM_DISP_CONN_H__ +#include <core/object.h> +#include <core/notify.h> -#include "priv.h" +#include <subdev/bios.h> +#include <subdev/bios/conn.h> struct nvkm_connector { - struct nouveau_object base; + struct nvkm_object base; struct list_head head; struct nvbios_connE info; @@ -28,29 +31,28 @@ struct nvkm_connector { _nvkm_connector_fini(nv_object(disp), (s)); \ }) -int nvkm_connector_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, struct nvbios_connE *, +int nvkm_connector_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, struct nvbios_connE *, int, int, void **); -int _nvkm_connector_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void _nvkm_connector_dtor(struct nouveau_object *); -int _nvkm_connector_init(struct nouveau_object *); -int _nvkm_connector_fini(struct nouveau_object *, bool); +int _nvkm_connector_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void _nvkm_connector_dtor(struct nvkm_object *); +int _nvkm_connector_init(struct nvkm_object *); +int _nvkm_connector_fini(struct nvkm_object *, bool); struct nvkm_connector_impl { - struct nouveau_oclass base; + struct nvkm_oclass base; }; #ifndef MSG #define MSG(l,f,a...) do { \ struct nvkm_connector *_conn = (void *)conn; \ - nv_##l(nv_object(conn)->engine, "%02x:%02x%02x: "f, _conn->index, \ + nv_##l(_conn, "%02x:%02x%02x: "f, _conn->index, \ _conn->info.location, _conn->info.type, ##a); \ } while(0) #define DBG(f,a...) MSG(debug, f, ##a) #define ERR(f,a...) MSG(error, f, ##a) #endif - #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c index b36addff06a9..0f7d1ec4d37e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c @@ -21,16 +21,14 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "outp.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <subdev/bios.h> -#include <subdev/bios/dcb.h> #include <subdev/timer.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> int nv50_dac_power(NV50_DISP_MTHD_V1) diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c index 16db08dfba6e..68347661adca 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c @@ -21,20 +21,16 @@ * * Authors: Ben Skeggs */ +#include "dport.h" +#include "outpdp.h" +#include "nv50.h" #include <subdev/bios.h> -#include <subdev/bios/dcb.h> -#include <subdev/bios/dp.h> #include <subdev/bios/init.h> #include <subdev/i2c.h> -#include "nv50.h" - #include <nvif/class.h> -#include "dport.h" -#include "outpdp.h" - /****************************************************************************** * link training *****************************************************************************/ @@ -54,8 +50,8 @@ dp_set_link_config(struct dp_state *dp) { struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); struct nvkm_output_dp *outp = dp->outp; - struct nouveau_disp *disp = nouveau_disp(outp); - struct nouveau_bios *bios = nouveau_bios(disp); + struct nvkm_disp *disp = nvkm_disp(outp); + struct nvkm_bios *bios = nvkm_bios(disp); struct nvbios_init init = { .subdev = nv_subdev(disp), .bios = bios, @@ -264,8 +260,8 @@ static void dp_link_train_init(struct dp_state *dp, bool spread) { struct nvkm_output_dp *outp = dp->outp; - struct nouveau_disp *disp = nouveau_disp(outp); - struct nouveau_bios *bios = nouveau_bios(disp); + struct nvkm_disp *disp = nvkm_disp(outp); + struct nvkm_bios *bios = nvkm_bios(disp); struct nvbios_init init = { .subdev = nv_subdev(disp), .bios = bios, @@ -290,8 +286,8 @@ static void dp_link_train_fini(struct dp_state *dp) { struct nvkm_output_dp *outp = dp->outp; - struct nouveau_disp *disp = nouveau_disp(outp); - struct nouveau_bios *bios = nouveau_bios(disp); + struct nvkm_disp *disp = nvkm_disp(outp); + struct nvkm_bios *bios = nvkm_bios(disp); struct nvbios_init init = { .subdev = nv_subdev(disp), .bios = bios, @@ -309,7 +305,7 @@ static const struct dp_rates { u32 rate; u8 bw; u8 nr; -} nouveau_dp_rates[] = { +} nvkm_dp_rates[] = { { 2160000, 0x14, 4 }, { 1080000, 0x0a, 4 }, { 1080000, 0x14, 2 }, @@ -323,11 +319,11 @@ static const struct dp_rates { }; void -nouveau_dp_train(struct work_struct *w) +nvkm_dp_train(struct work_struct *w) { struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work); - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); - const struct dp_rates *cfg = nouveau_dp_rates; + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + const struct dp_rates *cfg = nvkm_dp_rates; struct dp_state _dp = { .outp = outp, }, *dp = &_dp; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h index 5628d2d5ec71..9596290329c7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h @@ -1,5 +1,6 @@ #ifndef __NVKM_DISP_DPORT_H__ #define __NVKM_DISP_DPORT_H__ +#include <core/os.h> /* DPCD Receiver Capabilities */ #define DPCD_RC00_DPCD_REV 0x00000 @@ -70,6 +71,5 @@ #define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c #define DPCD_LS0C_LANE0_POST_CURSOR2 0x03 -void nouveau_dp_train(struct work_struct *); - +void nvkm_dp_train(struct work_struct *); #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c index 13eff5e4ee51..a0dcf534cb20 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c @@ -21,20 +21,16 @@ * * Authors: Ben Skeggs */ - -#include <engine/software.h> -#include <engine/disp.h> +#include "nv50.h" #include <nvif/class.h> -#include "nv50.h" - /******************************************************************************* * EVO master channel object ******************************************************************************/ const struct nv50_disp_mthd_list -nv84_disp_core_mthd_dac = { +g84_disp_core_mthd_dac = { .mthd = 0x0080, .addr = 0x000008, .data = { @@ -46,7 +42,7 @@ nv84_disp_core_mthd_dac = { }; const struct nv50_disp_mthd_list -nv84_disp_core_mthd_head = { +g84_disp_core_mthd_head = { .mthd = 0x0400, .addr = 0x000540, .data = { @@ -98,15 +94,15 @@ nv84_disp_core_mthd_head = { }; const struct nv50_disp_mthd_chan -nv84_disp_core_mthd_chan = { +g84_disp_core_mthd_chan = { .name = "Core", .addr = 0x000000, .data = { { "Global", 1, &nv50_disp_core_mthd_base }, - { "DAC", 3, &nv84_disp_core_mthd_dac }, + { "DAC", 3, &g84_disp_core_mthd_dac }, { "SOR", 2, &nv50_disp_core_mthd_sor }, { "PIOR", 3, &nv50_disp_core_mthd_pior }, - { "HEAD", 2, &nv84_disp_core_mthd_head }, + { "HEAD", 2, &g84_disp_core_mthd_head }, {} } }; @@ -116,7 +112,7 @@ nv84_disp_core_mthd_chan = { ******************************************************************************/ static const struct nv50_disp_mthd_list -nv84_disp_base_mthd_base = { +g84_disp_base_mthd_base = { .mthd = 0x0000, .addr = 0x000000, .data = { @@ -146,11 +142,11 @@ nv84_disp_base_mthd_base = { }; const struct nv50_disp_mthd_chan -nv84_disp_base_mthd_chan = { +g84_disp_base_mthd_chan = { .name = "Base", .addr = 0x000540, .data = { - { "Global", 1, &nv84_disp_base_mthd_base }, + { "Global", 1, &g84_disp_base_mthd_base }, { "Image", 2, &nv50_disp_base_mthd_image }, {} } @@ -161,7 +157,7 @@ nv84_disp_base_mthd_chan = { ******************************************************************************/ static const struct nv50_disp_mthd_list -nv84_disp_ovly_mthd_base = { +g84_disp_ovly_mthd_base = { .mthd = 0x0000, .addr = 0x000000, .data = { @@ -189,11 +185,11 @@ nv84_disp_ovly_mthd_base = { }; const struct nv50_disp_mthd_chan -nv84_disp_ovly_mthd_chan = { +g84_disp_ovly_mthd_chan = { .name = "Overlay", .addr = 0x000540, .data = { - { "Global", 1, &nv84_disp_ovly_mthd_base }, + { "Global", 1, &g84_disp_ovly_mthd_base }, {} } }; @@ -202,8 +198,8 @@ nv84_disp_ovly_mthd_chan = { * Base display object ******************************************************************************/ -static struct nouveau_oclass -nv84_disp_sclass[] = { +static struct nvkm_oclass +g84_disp_sclass[] = { { G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, { G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, { G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, @@ -212,8 +208,8 @@ nv84_disp_sclass[] = { {} }; -static struct nouveau_oclass -nv84_disp_main_oclass[] = { +static struct nvkm_oclass +g84_disp_main_oclass[] = { { G82_DISP, &nv50_disp_main_ofuncs }, {} }; @@ -223,15 +219,15 @@ nv84_disp_main_oclass[] = { ******************************************************************************/ static int -nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int ret; - ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", + "display", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -240,11 +236,11 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, if (ret) return ret; - nv_engine(priv)->sclass = nv84_disp_main_oclass; + nv_engine(priv)->sclass = g84_disp_main_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); - priv->sclass = nv84_disp_sclass; + priv->sclass = g84_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; priv->sor.nr = 2; @@ -252,25 +248,25 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; - priv->sor.hdmi = nv84_hdmi_ctrl; + priv->sor.hdmi = g84_hdmi_ctrl; priv->pior.power = nv50_pior_power; return 0; } -struct nouveau_oclass * -nv84_disp_oclass = &(struct nv50_disp_impl) { +struct nvkm_oclass * +g84_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x82), - .base.base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .base.base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_disp_ctor, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, .base.vblank = &nv50_disp_vblank_func, .base.outp = nv50_disp_outp_sclass, - .mthd.core = &nv84_disp_core_mthd_chan, - .mthd.base = &nv84_disp_base_mthd_chan, - .mthd.ovly = &nv84_disp_ovly_mthd_chan, + .mthd.core = &g84_disp_core_mthd_chan, + .mthd.base = &g84_disp_base_mthd_chan, + .mthd.ovly = &g84_disp_ovly_mthd_chan, .mthd.prev = 0x000004, .head.scanoutpos = nv50_disp_main_scanoutpos, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c index 2bb7ac5cd0e6..1ab0d0ae3cc8 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c @@ -21,20 +21,17 @@ * * Authors: Ben Skeggs */ - -#include <engine/software.h> -#include <engine/disp.h> +#include "nv50.h" +#include "outpdp.h" #include <nvif/class.h> -#include "nv50.h" - /******************************************************************************* * EVO master channel object ******************************************************************************/ const struct nv50_disp_mthd_list -nv94_disp_core_mthd_sor = { +g94_disp_core_mthd_sor = { .mthd = 0x0040, .addr = 0x000008, .data = { @@ -44,15 +41,15 @@ nv94_disp_core_mthd_sor = { }; const struct nv50_disp_mthd_chan -nv94_disp_core_mthd_chan = { +g94_disp_core_mthd_chan = { .name = "Core", .addr = 0x000000, .data = { { "Global", 1, &nv50_disp_core_mthd_base }, - { "DAC", 3, &nv84_disp_core_mthd_dac }, - { "SOR", 4, &nv94_disp_core_mthd_sor }, + { "DAC", 3, &g84_disp_core_mthd_dac }, + { "SOR", 4, &g94_disp_core_mthd_sor }, { "PIOR", 3, &nv50_disp_core_mthd_pior }, - { "HEAD", 2, &nv84_disp_core_mthd_head }, + { "HEAD", 2, &g84_disp_core_mthd_head }, {} } }; @@ -61,8 +58,8 @@ nv94_disp_core_mthd_chan = { * Base display object ******************************************************************************/ -static struct nouveau_oclass -nv94_disp_sclass[] = { +static struct nvkm_oclass +g94_disp_sclass[] = { { GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, @@ -71,8 +68,8 @@ nv94_disp_sclass[] = { {} }; -static struct nouveau_oclass -nv94_disp_main_oclass[] = { +static struct nvkm_oclass +g94_disp_main_oclass[] = { { GT206_DISP, &nv50_disp_main_ofuncs }, {} }; @@ -82,15 +79,15 @@ nv94_disp_main_oclass[] = { ******************************************************************************/ static int -nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int ret; - ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", + "display", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -99,11 +96,11 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, if (ret) return ret; - nv_engine(priv)->sclass = nv94_disp_main_oclass; + nv_engine(priv)->sclass = g94_disp_main_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); - priv->sclass = nv94_disp_sclass; + priv->sclass = g94_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; priv->sor.nr = 4; @@ -111,32 +108,32 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; - priv->sor.hdmi = nv84_hdmi_ctrl; + priv->sor.hdmi = g84_hdmi_ctrl; priv->pior.power = nv50_pior_power; return 0; } -struct nouveau_oclass * -nv94_disp_outp_sclass[] = { +struct nvkm_oclass * +g94_disp_outp_sclass[] = { &nv50_pior_dp_impl.base.base, - &nv94_sor_dp_impl.base.base, + &g94_sor_dp_impl.base.base, NULL }; -struct nouveau_oclass * -nv94_disp_oclass = &(struct nv50_disp_impl) { +struct nvkm_oclass * +g94_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x88), - .base.base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv94_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .base.base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = g94_disp_ctor, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, .base.vblank = &nv50_disp_vblank_func, - .base.outp = nv94_disp_outp_sclass, - .mthd.core = &nv94_disp_core_mthd_chan, - .mthd.base = &nv84_disp_base_mthd_chan, - .mthd.ovly = &nv84_disp_ovly_mthd_chan, + .base.outp = g94_disp_outp_sclass, + .mthd.core = &g94_disp_core_mthd_chan, + .mthd.base = &g84_disp_base_mthd_chan, + .mthd.ovly = &g84_disp_ovly_mthd_chan, .mthd.prev = 0x000004, .head.scanoutpos = nv50_disp_main_scanoutpos, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c index 181a2d57e356..0ebf466e9ef3 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c @@ -21,33 +21,30 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "outp.h" +#include "outpdp.h" -#include <core/object.h> #include <core/client.h> -#include <core/parent.h> -#include <core/handle.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <engine/disp.h> - +#include <core/gpuobj.h> +#include <core/ramht.h> #include <subdev/bios.h> #include <subdev/bios/dcb.h> #include <subdev/bios/disp.h> #include <subdev/bios/init.h> #include <subdev/bios/pll.h> #include <subdev/devinit.h> -#include <subdev/fb.h> #include <subdev/timer.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> /******************************************************************************* * EVO channel base class ******************************************************************************/ static void -nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) +gf110_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) { struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index); @@ -55,7 +52,7 @@ nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) } static void -nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) +gf110_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) { struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); nv_wr32(priv, 0x61008c, 0x00000001 << index); @@ -63,10 +60,10 @@ nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) } const struct nvkm_event_func -nvd0_disp_chan_uevent = { +gf110_disp_chan_uevent = { .ctor = nv50_disp_chan_uevent_ctor, - .init = nvd0_disp_chan_uevent_init, - .fini = nvd0_disp_chan_uevent_fini, + .init = gf110_disp_chan_uevent_init, + .fini = gf110_disp_chan_uevent_fini, }; /******************************************************************************* @@ -74,25 +71,25 @@ nvd0_disp_chan_uevent = { ******************************************************************************/ static int -nvd0_disp_dmac_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 name) +gf110_disp_dmac_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 name) { struct nv50_disp_base *base = (void *)parent->parent; struct nv50_disp_chan *chan = (void *)parent; u32 addr = nv_gpuobj(object)->node->offset; u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001; - return nouveau_ramht_insert(base->ramht, chan->chid, name, data); + return nvkm_ramht_insert(base->ramht, chan->chid, name, data); } static void -nvd0_disp_dmac_object_detach(struct nouveau_object *parent, int cookie) +gf110_disp_dmac_object_detach(struct nvkm_object *parent, int cookie) { struct nv50_disp_base *base = (void *)parent->parent; - nouveau_ramht_remove(base->ramht, cookie); + nvkm_ramht_remove(base->ramht, cookie); } static int -nvd0_disp_dmac_init(struct nouveau_object *object) +gf110_disp_dmac_init(struct nvkm_object *object) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; @@ -125,7 +122,7 @@ nvd0_disp_dmac_init(struct nouveau_object *object) } static int -nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend) +gf110_disp_dmac_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; @@ -153,7 +150,7 @@ nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend) ******************************************************************************/ const struct nv50_disp_mthd_list -nvd0_disp_core_mthd_base = { +gf110_disp_core_mthd_base = { .mthd = 0x0000, .addr = 0x000000, .data = { @@ -166,7 +163,7 @@ nvd0_disp_core_mthd_base = { }; const struct nv50_disp_mthd_list -nvd0_disp_core_mthd_dac = { +gf110_disp_core_mthd_dac = { .mthd = 0x0020, .addr = 0x000020, .data = { @@ -179,7 +176,7 @@ nvd0_disp_core_mthd_dac = { }; const struct nv50_disp_mthd_list -nvd0_disp_core_mthd_sor = { +gf110_disp_core_mthd_sor = { .mthd = 0x0020, .addr = 0x000020, .data = { @@ -192,7 +189,7 @@ nvd0_disp_core_mthd_sor = { }; const struct nv50_disp_mthd_list -nvd0_disp_core_mthd_pior = { +gf110_disp_core_mthd_pior = { .mthd = 0x0020, .addr = 0x000020, .data = { @@ -205,7 +202,7 @@ nvd0_disp_core_mthd_pior = { }; static const struct nv50_disp_mthd_list -nvd0_disp_core_mthd_head = { +gf110_disp_core_mthd_head = { .mthd = 0x0300, .addr = 0x000300, .data = { @@ -279,21 +276,21 @@ nvd0_disp_core_mthd_head = { }; static const struct nv50_disp_mthd_chan -nvd0_disp_core_mthd_chan = { +gf110_disp_core_mthd_chan = { .name = "Core", .addr = 0x000000, .data = { - { "Global", 1, &nvd0_disp_core_mthd_base }, - { "DAC", 3, &nvd0_disp_core_mthd_dac }, - { "SOR", 8, &nvd0_disp_core_mthd_sor }, - { "PIOR", 4, &nvd0_disp_core_mthd_pior }, - { "HEAD", 4, &nvd0_disp_core_mthd_head }, + { "Global", 1, &gf110_disp_core_mthd_base }, + { "DAC", 3, &gf110_disp_core_mthd_dac }, + { "SOR", 8, &gf110_disp_core_mthd_sor }, + { "PIOR", 4, &gf110_disp_core_mthd_pior }, + { "HEAD", 4, &gf110_disp_core_mthd_head }, {} } }; static int -nvd0_disp_core_init(struct nouveau_object *object) +gf110_disp_core_init(struct nvkm_object *object) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; @@ -324,7 +321,7 @@ nvd0_disp_core_init(struct nouveau_object *object) } static int -nvd0_disp_core_fini(struct nouveau_object *object, bool suspend) +gf110_disp_core_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; @@ -346,18 +343,18 @@ nvd0_disp_core_fini(struct nouveau_object *object, bool suspend) } struct nv50_disp_chan_impl -nvd0_disp_core_ofuncs = { +gf110_disp_core_ofuncs = { .base.ctor = nv50_disp_core_ctor, .base.dtor = nv50_disp_dmac_dtor, - .base.init = nvd0_disp_core_init, - .base.fini = nvd0_disp_core_fini, + .base.init = gf110_disp_core_init, + .base.fini = gf110_disp_core_fini, .base.ntfy = nv50_disp_chan_ntfy, .base.map = nv50_disp_chan_map, .base.rd32 = nv50_disp_chan_rd32, .base.wr32 = nv50_disp_chan_wr32, .chid = 0, - .attach = nvd0_disp_dmac_object_attach, - .detach = nvd0_disp_dmac_object_detach, + .attach = gf110_disp_dmac_object_attach, + .detach = gf110_disp_dmac_object_detach, }; /******************************************************************************* @@ -365,7 +362,7 @@ nvd0_disp_core_ofuncs = { ******************************************************************************/ static const struct nv50_disp_mthd_list -nvd0_disp_base_mthd_base = { +gf110_disp_base_mthd_base = { .mthd = 0x0000, .addr = 0x000000, .data = { @@ -415,7 +412,7 @@ nvd0_disp_base_mthd_base = { }; static const struct nv50_disp_mthd_list -nvd0_disp_base_mthd_image = { +gf110_disp_base_mthd_image = { .mthd = 0x0400, .addr = 0x000400, .data = { @@ -429,29 +426,29 @@ nvd0_disp_base_mthd_image = { }; const struct nv50_disp_mthd_chan -nvd0_disp_base_mthd_chan = { +gf110_disp_base_mthd_chan = { .name = "Base", .addr = 0x001000, .data = { - { "Global", 1, &nvd0_disp_base_mthd_base }, - { "Image", 2, &nvd0_disp_base_mthd_image }, + { "Global", 1, &gf110_disp_base_mthd_base }, + { "Image", 2, &gf110_disp_base_mthd_image }, {} } }; struct nv50_disp_chan_impl -nvd0_disp_base_ofuncs = { +gf110_disp_base_ofuncs = { .base.ctor = nv50_disp_base_ctor, .base.dtor = nv50_disp_dmac_dtor, - .base.init = nvd0_disp_dmac_init, - .base.fini = nvd0_disp_dmac_fini, + .base.init = gf110_disp_dmac_init, + .base.fini = gf110_disp_dmac_fini, .base.ntfy = nv50_disp_chan_ntfy, .base.map = nv50_disp_chan_map, .base.rd32 = nv50_disp_chan_rd32, .base.wr32 = nv50_disp_chan_wr32, .chid = 1, - .attach = nvd0_disp_dmac_object_attach, - .detach = nvd0_disp_dmac_object_detach, + .attach = gf110_disp_dmac_object_attach, + .detach = gf110_disp_dmac_object_detach, }; /******************************************************************************* @@ -459,7 +456,7 @@ nvd0_disp_base_ofuncs = { ******************************************************************************/ static const struct nv50_disp_mthd_list -nvd0_disp_ovly_mthd_base = { +gf110_disp_ovly_mthd_base = { .mthd = 0x0000, .data = { { 0x0080, 0x665080 }, @@ -511,28 +508,28 @@ nvd0_disp_ovly_mthd_base = { }; static const struct nv50_disp_mthd_chan -nvd0_disp_ovly_mthd_chan = { +gf110_disp_ovly_mthd_chan = { .name = "Overlay", .addr = 0x001000, .data = { - { "Global", 1, &nvd0_disp_ovly_mthd_base }, + { "Global", 1, &gf110_disp_ovly_mthd_base }, {} } }; struct nv50_disp_chan_impl -nvd0_disp_ovly_ofuncs = { +gf110_disp_ovly_ofuncs = { .base.ctor = nv50_disp_ovly_ctor, .base.dtor = nv50_disp_dmac_dtor, - .base.init = nvd0_disp_dmac_init, - .base.fini = nvd0_disp_dmac_fini, + .base.init = gf110_disp_dmac_init, + .base.fini = gf110_disp_dmac_fini, .base.ntfy = nv50_disp_chan_ntfy, .base.map = nv50_disp_chan_map, .base.rd32 = nv50_disp_chan_rd32, .base.wr32 = nv50_disp_chan_wr32, .chid = 5, - .attach = nvd0_disp_dmac_object_attach, - .detach = nvd0_disp_dmac_object_detach, + .attach = gf110_disp_dmac_object_attach, + .detach = gf110_disp_dmac_object_detach, }; /******************************************************************************* @@ -540,7 +537,7 @@ nvd0_disp_ovly_ofuncs = { ******************************************************************************/ static int -nvd0_disp_pioc_init(struct nouveau_object *object) +gf110_disp_pioc_init(struct nvkm_object *object) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; @@ -566,7 +563,7 @@ nvd0_disp_pioc_init(struct nouveau_object *object) } static int -nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend) +gf110_disp_pioc_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; @@ -592,11 +589,11 @@ nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend) ******************************************************************************/ struct nv50_disp_chan_impl -nvd0_disp_oimm_ofuncs = { +gf110_disp_oimm_ofuncs = { .base.ctor = nv50_disp_oimm_ctor, .base.dtor = nv50_disp_pioc_dtor, - .base.init = nvd0_disp_pioc_init, - .base.fini = nvd0_disp_pioc_fini, + .base.init = gf110_disp_pioc_init, + .base.fini = gf110_disp_pioc_fini, .base.ntfy = nv50_disp_chan_ntfy, .base.map = nv50_disp_chan_map, .base.rd32 = nv50_disp_chan_rd32, @@ -609,11 +606,11 @@ nvd0_disp_oimm_ofuncs = { ******************************************************************************/ struct nv50_disp_chan_impl -nvd0_disp_curs_ofuncs = { +gf110_disp_curs_ofuncs = { .base.ctor = nv50_disp_curs_ctor, .base.dtor = nv50_disp_pioc_dtor, - .base.init = nvd0_disp_pioc_init, - .base.fini = nvd0_disp_pioc_fini, + .base.init = gf110_disp_pioc_init, + .base.fini = gf110_disp_pioc_fini, .base.ntfy = nv50_disp_chan_ntfy, .base.map = nv50_disp_chan_map, .base.rd32 = nv50_disp_chan_rd32, @@ -626,7 +623,7 @@ nvd0_disp_curs_ofuncs = { ******************************************************************************/ int -nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0) +gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0) { const u32 total = nv_rd32(priv, 0x640414 + (head * 0x300)); const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300)); @@ -658,14 +655,14 @@ nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0) } static int -nvd0_disp_main_init(struct nouveau_object *object) +gf110_disp_main_init(struct nvkm_object *object) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_base *base = (void *)object; int ret, i; u32 tmp; - ret = nouveau_parent_init(&base->base); + ret = nvkm_parent_init(&base->base); if (ret) return ret; @@ -715,7 +712,7 @@ nvd0_disp_main_init(struct nouveau_object *object) nv_wr32(priv, 0x6100b0, 0x00000307); /* disable underflow reporting, preventing an intermittent issue - * on some nve4 boards where the production vbios left this + * on some gk104 boards where the production vbios left this * setting enabled by default. * * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt @@ -727,7 +724,7 @@ nvd0_disp_main_init(struct nouveau_object *object) } static int -nvd0_disp_main_fini(struct nouveau_object *object, bool suspend) +gf110_disp_main_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_base *base = (void *)object; @@ -735,32 +732,32 @@ nvd0_disp_main_fini(struct nouveau_object *object, bool suspend) /* disable all interrupts */ nv_wr32(priv, 0x6100b0, 0x00000000); - return nouveau_parent_fini(&base->base, suspend); + return nvkm_parent_fini(&base->base, suspend); } -struct nouveau_ofuncs -nvd0_disp_main_ofuncs = { +struct nvkm_ofuncs +gf110_disp_main_ofuncs = { .ctor = nv50_disp_main_ctor, .dtor = nv50_disp_main_dtor, - .init = nvd0_disp_main_init, - .fini = nvd0_disp_main_fini, + .init = gf110_disp_main_init, + .fini = gf110_disp_main_fini, .mthd = nv50_disp_main_mthd, - .ntfy = nouveau_disp_ntfy, + .ntfy = nvkm_disp_ntfy, }; -static struct nouveau_oclass -nvd0_disp_main_oclass[] = { - { GF110_DISP, &nvd0_disp_main_ofuncs }, +static struct nvkm_oclass +gf110_disp_main_oclass[] = { + { GF110_DISP, &gf110_disp_main_ofuncs }, {} }; -static struct nouveau_oclass -nvd0_disp_sclass[] = { - { GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base }, - { GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base }, - { GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, - { GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, - { GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, +static struct nvkm_oclass +gf110_disp_sclass[] = { + { GF110_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, + { GF110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, + { GF110_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, + { GF110_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, + { GF110_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, {} }; @@ -769,24 +766,24 @@ nvd0_disp_sclass[] = { ******************************************************************************/ static void -nvd0_disp_vblank_init(struct nvkm_event *event, int type, int head) +gf110_disp_vblank_init(struct nvkm_event *event, int type, int head) { - struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); + struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001); } static void -nvd0_disp_vblank_fini(struct nvkm_event *event, int type, int head) +gf110_disp_vblank_fini(struct nvkm_event *event, int type, int head) { - struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); + struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000); } const struct nvkm_event_func -nvd0_disp_vblank_func = { - .ctor = nouveau_disp_vblank_ctor, - .init = nvd0_disp_vblank_init, - .fini = nvd0_disp_vblank_fini, +gf110_disp_vblank_func = { + .ctor = nvkm_disp_vblank_ctor, + .init = gf110_disp_vblank_init, + .fini = gf110_disp_vblank_fini, }; static struct nvkm_output * @@ -794,7 +791,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *info) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvkm_output *outp; u16 mask, type; @@ -838,7 +835,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, static struct nvkm_output * exec_script(struct nv50_disp_priv *priv, int head, int id) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvkm_output *outp; struct nvbios_outp info; u8 ver, hdr, cnt, len; @@ -874,7 +871,7 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) static struct nvkm_output * exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvkm_output *outp; struct nvbios_outp info1; struct nvbios_ocfg info2; @@ -934,13 +931,13 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) } static void -nvd0_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head) { exec_script(priv, head, 1); } static void -nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head) { struct nvkm_output *outp = exec_script(priv, head, 2); @@ -949,7 +946,7 @@ nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head) struct nvkm_output_dp *outpdp = (void *)outp; struct nvbios_init init = { .subdev = nv_subdev(priv), - .bios = nouveau_bios(priv), + .bios = nvkm_bios(priv), .outp = &outp->info, .crtc = head, .offset = outpdp->info.script[4], @@ -962,9 +959,9 @@ nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head) } static void -nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head) { - struct nouveau_devinit *devinit = nouveau_devinit(priv); + struct nvkm_devinit *devinit = nvkm_devinit(priv); u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; if (pclk) devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); @@ -972,8 +969,8 @@ nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head) } static void -nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head, - struct dcb_output *outp) +gf110_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head, + struct dcb_output *outp) { const int or = ffs(outp->or) - 1; const u32 ctrl = nv_rd32(priv, 0x660200 + (or * 0x020)); @@ -1033,7 +1030,7 @@ nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head, } static void -nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) { struct nvkm_output *outp; u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; @@ -1075,7 +1072,7 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) nv_mask(priv, addr, 0x007c0000, 0x00280000); break; case DCB_OUTPUT_DP: - nvd0_disp_intr_unk2_2_tu(priv, head, &outp->info); + gf110_disp_intr_unk2_2_tu(priv, head, &outp->info); break; default: break; @@ -1086,7 +1083,7 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) } static void -nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head) { u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; u32 conf; @@ -1095,7 +1092,7 @@ nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head) } void -nvd0_disp_intr_supervisor(struct work_struct *work) +gf110_disp_intr_supervisor(struct work_struct *work) { struct nv50_disp_priv *priv = container_of(work, struct nv50_disp_priv, supervisor); @@ -1115,7 +1112,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work) if (!(mask[head] & 0x00001000)) continue; nv_debug(priv, "supervisor 1.0 - head %d\n", head); - nvd0_disp_intr_unk1_0(priv, head); + gf110_disp_intr_unk1_0(priv, head); } } else if (priv->super & 0x00000002) { @@ -1123,19 +1120,19 @@ nvd0_disp_intr_supervisor(struct work_struct *work) if (!(mask[head] & 0x00001000)) continue; nv_debug(priv, "supervisor 2.0 - head %d\n", head); - nvd0_disp_intr_unk2_0(priv, head); + gf110_disp_intr_unk2_0(priv, head); } for (head = 0; head < priv->head.nr; head++) { if (!(mask[head] & 0x00010000)) continue; nv_debug(priv, "supervisor 2.1 - head %d\n", head); - nvd0_disp_intr_unk2_1(priv, head); + gf110_disp_intr_unk2_1(priv, head); } for (head = 0; head < priv->head.nr; head++) { if (!(mask[head] & 0x00001000)) continue; nv_debug(priv, "supervisor 2.2 - head %d\n", head); - nvd0_disp_intr_unk2_2(priv, head); + gf110_disp_intr_unk2_2(priv, head); } } else if (priv->super & 0x00000004) { @@ -1143,7 +1140,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work) if (!(mask[head] & 0x00001000)) continue; nv_debug(priv, "supervisor 3.0 - head %d\n", head); - nvd0_disp_intr_unk4_0(priv, head); + gf110_disp_intr_unk4_0(priv, head); } } @@ -1153,7 +1150,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work) } static void -nvd0_disp_intr_error(struct nv50_disp_priv *priv, int chid) +gf110_disp_intr_error(struct nv50_disp_priv *priv, int chid) { const struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; u32 mthd = nv_rd32(priv, 0x6101f0 + (chid * 12)); @@ -1200,7 +1197,7 @@ nvd0_disp_intr_error(struct nv50_disp_priv *priv, int chid) } void -nvd0_disp_intr(struct nouveau_subdev *subdev) +gf110_disp_intr(struct nvkm_subdev *subdev) { struct nv50_disp_priv *priv = (void *)subdev; u32 intr = nv_rd32(priv, 0x610088); @@ -1220,7 +1217,7 @@ nvd0_disp_intr(struct nouveau_subdev *subdev) u32 stat = nv_rd32(priv, 0x61009c); int chid = ffs(stat) - 1; if (chid >= 0) - nvd0_disp_intr_error(priv, chid); + gf110_disp_intr_error(priv, chid); intr &= ~0x00000002; } @@ -1246,7 +1243,7 @@ nvd0_disp_intr(struct nouveau_subdev *subdev) if (mask & intr) { u32 stat = nv_rd32(priv, 0x6100bc + (i * 0x800)); if (stat & 0x00000001) - nouveau_disp_vblank(&priv->base, i); + nvkm_disp_vblank(&priv->base, i); nv_mask(priv, 0x6100bc + (i * 0x800), 0, 0); nv_rd32(priv, 0x6100c0 + (i * 0x800)); } @@ -1254,60 +1251,60 @@ nvd0_disp_intr(struct nouveau_subdev *subdev) } static int -nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int heads = nv_rd32(parent, 0x022448); int ret; - ret = nouveau_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, heads, + "PDISP", "display", &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); if (ret) return ret; - nv_engine(priv)->sclass = nvd0_disp_main_oclass; + nv_engine(priv)->sclass = gf110_disp_main_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nvd0_disp_intr; - INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); - priv->sclass = nvd0_disp_sclass; + nv_subdev(priv)->intr = gf110_disp_intr; + INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); + priv->sclass = gf110_disp_sclass; priv->head.nr = heads; priv->dac.nr = 3; priv->sor.nr = 4; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = nvd0_hda_eld; - priv->sor.hdmi = nvd0_hdmi_ctrl; + priv->sor.hda_eld = gf110_hda_eld; + priv->sor.hdmi = gf110_hdmi_ctrl; return 0; } -struct nouveau_oclass * -nvd0_disp_outp_sclass[] = { - &nvd0_sor_dp_impl.base.base, +struct nvkm_oclass * +gf110_disp_outp_sclass[] = { + &gf110_sor_dp_impl.base.base, NULL }; -struct nouveau_oclass * -nvd0_disp_oclass = &(struct nv50_disp_impl) { +struct nvkm_oclass * +gf110_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x90), - .base.base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvd0_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .base.base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf110_disp_ctor, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, - .base.vblank = &nvd0_disp_vblank_func, - .base.outp = nvd0_disp_outp_sclass, - .mthd.core = &nvd0_disp_core_mthd_chan, - .mthd.base = &nvd0_disp_base_mthd_chan, - .mthd.ovly = &nvd0_disp_ovly_mthd_chan, + .base.vblank = &gf110_disp_vblank_func, + .base.outp = gf110_disp_outp_sclass, + .mthd.core = &gf110_disp_core_mthd_chan, + .mthd.base = &gf110_disp_base_mthd_chan, + .mthd.ovly = &gf110_disp_ovly_mthd_chan, .mthd.prev = -0x020000, - .head.scanoutpos = nvd0_disp_main_scanoutpos, + .head.scanoutpos = gf110_disp_main_scanoutpos, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c index 55debec7e68f..6f4019ab4e65 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c @@ -21,20 +21,16 @@ * * Authors: Ben Skeggs */ - -#include <engine/software.h> -#include <engine/disp.h> +#include "nv50.h" #include <nvif/class.h> -#include "nv50.h" - /******************************************************************************* * EVO master channel object ******************************************************************************/ static const struct nv50_disp_mthd_list -nve0_disp_core_mthd_head = { +gk104_disp_core_mthd_head = { .mthd = 0x0300, .addr = 0x000300, .data = { @@ -113,15 +109,15 @@ nve0_disp_core_mthd_head = { }; const struct nv50_disp_mthd_chan -nve0_disp_core_mthd_chan = { +gk104_disp_core_mthd_chan = { .name = "Core", .addr = 0x000000, .data = { - { "Global", 1, &nvd0_disp_core_mthd_base }, - { "DAC", 3, &nvd0_disp_core_mthd_dac }, - { "SOR", 8, &nvd0_disp_core_mthd_sor }, - { "PIOR", 4, &nvd0_disp_core_mthd_pior }, - { "HEAD", 4, &nve0_disp_core_mthd_head }, + { "Global", 1, &gf110_disp_core_mthd_base }, + { "DAC", 3, &gf110_disp_core_mthd_dac }, + { "SOR", 8, &gf110_disp_core_mthd_sor }, + { "PIOR", 4, &gf110_disp_core_mthd_pior }, + { "HEAD", 4, &gk104_disp_core_mthd_head }, {} } }; @@ -131,7 +127,7 @@ nve0_disp_core_mthd_chan = { ******************************************************************************/ static const struct nv50_disp_mthd_list -nve0_disp_ovly_mthd_base = { +gk104_disp_ovly_mthd_base = { .mthd = 0x0000, .data = { { 0x0080, 0x665080 }, @@ -185,11 +181,11 @@ nve0_disp_ovly_mthd_base = { }; const struct nv50_disp_mthd_chan -nve0_disp_ovly_mthd_chan = { +gk104_disp_ovly_mthd_chan = { .name = "Overlay", .addr = 0x001000, .data = { - { "Global", 1, &nve0_disp_ovly_mthd_base }, + { "Global", 1, &gk104_disp_ovly_mthd_base }, {} } }; @@ -198,19 +194,19 @@ nve0_disp_ovly_mthd_chan = { * Base display object ******************************************************************************/ -static struct nouveau_oclass -nve0_disp_sclass[] = { - { GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base }, - { GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base }, - { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, - { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, - { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, +static struct nvkm_oclass +gk104_disp_sclass[] = { + { GK104_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, + { GK104_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, + { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, + { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, + { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, {} }; -static struct nouveau_oclass -nve0_disp_main_oclass[] = { - { GK104_DISP, &nvd0_disp_main_ofuncs }, +static struct nvkm_oclass +gk104_disp_main_oclass[] = { + { GK104_DISP, &gf110_disp_main_ofuncs }, {} }; @@ -219,54 +215,54 @@ nve0_disp_main_oclass[] = { ******************************************************************************/ static int -nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int heads = nv_rd32(parent, 0x022448); int ret; - ret = nouveau_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, heads, + "PDISP", "display", &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); if (ret) return ret; - nv_engine(priv)->sclass = nve0_disp_main_oclass; + nv_engine(priv)->sclass = gk104_disp_main_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nvd0_disp_intr; - INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); - priv->sclass = nve0_disp_sclass; + nv_subdev(priv)->intr = gf110_disp_intr; + INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); + priv->sclass = gk104_disp_sclass; priv->head.nr = heads; priv->dac.nr = 3; priv->sor.nr = 4; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = nvd0_hda_eld; - priv->sor.hdmi = nve0_hdmi_ctrl; + priv->sor.hda_eld = gf110_hda_eld; + priv->sor.hdmi = gk104_hdmi_ctrl; return 0; } -struct nouveau_oclass * -nve0_disp_oclass = &(struct nv50_disp_impl) { +struct nvkm_oclass * +gk104_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x91), - .base.base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .base.base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_disp_ctor, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, - .base.vblank = &nvd0_disp_vblank_func, - .base.outp = nvd0_disp_outp_sclass, - .mthd.core = &nve0_disp_core_mthd_chan, - .mthd.base = &nvd0_disp_base_mthd_chan, - .mthd.ovly = &nve0_disp_ovly_mthd_chan, + .base.vblank = &gf110_disp_vblank_func, + .base.outp = gf110_disp_outp_sclass, + .mthd.core = &gk104_disp_core_mthd_chan, + .mthd.base = &gf110_disp_base_mthd_chan, + .mthd.ovly = &gk104_disp_ovly_mthd_chan, .mthd.prev = -0x020000, - .head.scanoutpos = nvd0_disp_main_scanoutpos, + .head.scanoutpos = gf110_disp_main_scanoutpos, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c index 3e7e2d28744c..daa4b460a6ba 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c @@ -21,31 +21,27 @@ * * Authors: Ben Skeggs */ - -#include <engine/software.h> -#include <engine/disp.h> +#include "nv50.h" #include <nvif/class.h> -#include "nv50.h" - /******************************************************************************* * Base display object ******************************************************************************/ -static struct nouveau_oclass -nvf0_disp_sclass[] = { - { GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base }, - { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base }, - { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, - { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, - { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, +static struct nvkm_oclass +gk110_disp_sclass[] = { + { GK110_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, + { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, + { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, + { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, + { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, {} }; -static struct nouveau_oclass -nvf0_disp_main_oclass[] = { - { GK110_DISP, &nvd0_disp_main_ofuncs }, +static struct nvkm_oclass +gk110_disp_main_oclass[] = { + { GK110_DISP, &gf110_disp_main_ofuncs }, {} }; @@ -54,54 +50,54 @@ nvf0_disp_main_oclass[] = { ******************************************************************************/ static int -nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int heads = nv_rd32(parent, 0x022448); int ret; - ret = nouveau_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, heads, + "PDISP", "display", &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); if (ret) return ret; - nv_engine(priv)->sclass = nvf0_disp_main_oclass; + nv_engine(priv)->sclass = gk110_disp_main_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nvd0_disp_intr; - INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); - priv->sclass = nvf0_disp_sclass; + nv_subdev(priv)->intr = gf110_disp_intr; + INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); + priv->sclass = gk110_disp_sclass; priv->head.nr = heads; priv->dac.nr = 3; priv->sor.nr = 4; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = nvd0_hda_eld; - priv->sor.hdmi = nve0_hdmi_ctrl; + priv->sor.hda_eld = gf110_hda_eld; + priv->sor.hdmi = gk104_hdmi_ctrl; return 0; } -struct nouveau_oclass * -nvf0_disp_oclass = &(struct nv50_disp_impl) { +struct nvkm_oclass * +gk110_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x92), - .base.base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvf0_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .base.base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk110_disp_ctor, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, - .base.vblank = &nvd0_disp_vblank_func, - .base.outp = nvd0_disp_outp_sclass, - .mthd.core = &nve0_disp_core_mthd_chan, - .mthd.base = &nvd0_disp_base_mthd_chan, - .mthd.ovly = &nve0_disp_ovly_mthd_chan, + .base.vblank = &gf110_disp_vblank_func, + .base.outp = gf110_disp_outp_sclass, + .mthd.core = &gk104_disp_core_mthd_chan, + .mthd.base = &gf110_disp_base_mthd_chan, + .mthd.ovly = &gk104_disp_ovly_mthd_chan, .mthd.prev = -0x020000, - .head.scanoutpos = nvd0_disp_main_scanoutpos, + .head.scanoutpos = gf110_disp_main_scanoutpos, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c index e2ad0543fb31..881cc94385a1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c @@ -21,31 +21,27 @@ * * Authors: Ben Skeggs */ - -#include <engine/software.h> -#include <engine/disp.h> +#include "nv50.h" #include <nvif/class.h> -#include "nv50.h" - /******************************************************************************* * Base display object ******************************************************************************/ -static struct nouveau_oclass +static struct nvkm_oclass gm107_disp_sclass[] = { - { GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base }, - { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base }, - { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, - { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, - { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, + { GM107_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, + { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, + { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, + { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, + { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, {} }; -static struct nouveau_oclass +static struct nvkm_oclass gm107_disp_main_oclass[] = { - { GM107_DISP, &nvd0_disp_main_ofuncs }, + { GM107_DISP, &gf110_disp_main_ofuncs }, {} }; @@ -54,28 +50,28 @@ gm107_disp_main_oclass[] = { ******************************************************************************/ static int -gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int heads = nv_rd32(parent, 0x022448); int ret; - ret = nouveau_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, heads, + "PDISP", "display", &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); if (ret) return ret; nv_engine(priv)->sclass = gm107_disp_main_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nvd0_disp_intr; - INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); + nv_subdev(priv)->intr = gf110_disp_intr; + INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); priv->sclass = gm107_disp_sclass; priv->head.nr = heads; priv->dac.nr = 3; @@ -83,25 +79,25 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = nvd0_hda_eld; - priv->sor.hdmi = nve0_hdmi_ctrl; + priv->sor.hda_eld = gf110_hda_eld; + priv->sor.hdmi = gk104_hdmi_ctrl; return 0; } -struct nouveau_oclass * +struct nvkm_oclass * gm107_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x07), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gm107_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, - .base.vblank = &nvd0_disp_vblank_func, - .base.outp = nvd0_disp_outp_sclass, - .mthd.core = &nve0_disp_core_mthd_chan, - .mthd.base = &nvd0_disp_base_mthd_chan, - .mthd.ovly = &nve0_disp_ovly_mthd_chan, + .base.vblank = &gf110_disp_vblank_func, + .base.outp = gf110_disp_outp_sclass, + .mthd.core = &gk104_disp_core_mthd_chan, + .mthd.base = &gf110_disp_base_mthd_chan, + .mthd.ovly = &gk104_disp_ovly_mthd_chan, .mthd.prev = -0x020000, - .head.scanoutpos = nvd0_disp_main_scanoutpos, + .head.scanoutpos = gf110_disp_main_scanoutpos, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c index 672ded79b2a9..67004f8302b3 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c @@ -21,31 +21,28 @@ * * Authors: Ben Skeggs */ - -#include <engine/software.h> -#include <engine/disp.h> +#include "nv50.h" +#include "outpdp.h" #include <nvif/class.h> -#include "nv50.h" - /******************************************************************************* * Base display object ******************************************************************************/ -static struct nouveau_oclass +static struct nvkm_oclass gm204_disp_sclass[] = { - { GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base }, - { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base }, - { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, - { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, - { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, + { GM204_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, + { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, + { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, + { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, + { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, {} }; -static struct nouveau_oclass +static struct nvkm_oclass gm204_disp_main_oclass[] = { - { GM204_DISP, &nvd0_disp_main_ofuncs }, + { GM204_DISP, &gf110_disp_main_ofuncs }, {} }; @@ -54,28 +51,28 @@ gm204_disp_main_oclass[] = { ******************************************************************************/ static int -gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int heads = nv_rd32(parent, 0x022448); int ret; - ret = nouveau_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, heads, + "PDISP", "display", &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); if (ret) return ret; nv_engine(priv)->sclass = gm204_disp_main_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nvd0_disp_intr; - INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); + nv_subdev(priv)->intr = gf110_disp_intr; + INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); priv->sclass = gm204_disp_sclass; priv->head.nr = heads; priv->dac.nr = 3; @@ -83,32 +80,32 @@ gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = nvd0_hda_eld; - priv->sor.hdmi = nvd0_hdmi_ctrl; + priv->sor.hda_eld = gf110_hda_eld; + priv->sor.hdmi = gf110_hdmi_ctrl; priv->sor.magic = gm204_sor_magic; return 0; } -struct nouveau_oclass * +struct nvkm_oclass * gm204_disp_outp_sclass[] = { &gm204_sor_dp_impl.base.base, NULL }; -struct nouveau_oclass * +struct nvkm_oclass * gm204_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x07), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gm204_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, - .base.vblank = &nvd0_disp_vblank_func, + .base.vblank = &gf110_disp_vblank_func, .base.outp = gm204_disp_outp_sclass, - .mthd.core = &nve0_disp_core_mthd_chan, - .mthd.base = &nvd0_disp_base_mthd_chan, - .mthd.ovly = &nve0_disp_ovly_mthd_chan, + .mthd.core = &gk104_disp_core_mthd_chan, + .mthd.base = &gf110_disp_base_mthd_chan, + .mthd.ovly = &gk104_disp_ovly_mthd_chan, .mthd.prev = -0x020000, - .head.scanoutpos = nvd0_disp_main_scanoutpos, + .head.scanoutpos = gf110_disp_main_scanoutpos, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c index b32456c9494f..a45307213f4b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c @@ -21,20 +21,16 @@ * * Authors: Ben Skeggs */ - -#include <engine/software.h> -#include <engine/disp.h> +#include "nv50.h" #include <nvif/class.h> -#include "nv50.h" - /******************************************************************************* * EVO overlay channel objects ******************************************************************************/ static const struct nv50_disp_mthd_list -nva0_disp_ovly_mthd_base = { +gt200_disp_ovly_mthd_base = { .mthd = 0x0000, .addr = 0x000000, .data = { @@ -65,11 +61,11 @@ nva0_disp_ovly_mthd_base = { }; static const struct nv50_disp_mthd_chan -nva0_disp_ovly_mthd_chan = { +gt200_disp_ovly_mthd_chan = { .name = "Overlay", .addr = 0x000540, .data = { - { "Global", 1, &nva0_disp_ovly_mthd_base }, + { "Global", 1, >200_disp_ovly_mthd_base }, {} } }; @@ -78,8 +74,8 @@ nva0_disp_ovly_mthd_chan = { * Base display object ******************************************************************************/ -static struct nouveau_oclass -nva0_disp_sclass[] = { +static struct nvkm_oclass +gt200_disp_sclass[] = { { GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, @@ -88,8 +84,8 @@ nva0_disp_sclass[] = { {} }; -static struct nouveau_oclass -nva0_disp_main_oclass[] = { +static struct nvkm_oclass +gt200_disp_main_oclass[] = { { GT200_DISP, &nv50_disp_main_ofuncs }, {} }; @@ -99,15 +95,15 @@ nva0_disp_main_oclass[] = { ******************************************************************************/ static int -nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int ret; - ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", + "display", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -116,11 +112,11 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, if (ret) return ret; - nv_engine(priv)->sclass = nva0_disp_main_oclass; + nv_engine(priv)->sclass = gt200_disp_main_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); - priv->sclass = nva0_disp_sclass; + priv->sclass = gt200_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; priv->sor.nr = 2; @@ -128,25 +124,25 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; - priv->sor.hdmi = nv84_hdmi_ctrl; + priv->sor.hdmi = g84_hdmi_ctrl; priv->pior.power = nv50_pior_power; return 0; } -struct nouveau_oclass * -nva0_disp_oclass = &(struct nv50_disp_impl) { +struct nvkm_oclass * +gt200_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x83), - .base.base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva0_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .base.base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gt200_disp_ctor, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, .base.vblank = &nv50_disp_vblank_func, .base.outp = nv50_disp_outp_sclass, - .mthd.core = &nv84_disp_core_mthd_chan, - .mthd.base = &nv84_disp_base_mthd_chan, - .mthd.ovly = &nva0_disp_ovly_mthd_chan, + .mthd.core = &g84_disp_core_mthd_chan, + .mthd.base = &g84_disp_base_mthd_chan, + .mthd.ovly = >200_disp_ovly_mthd_chan, .mthd.prev = 0x000004, .head.scanoutpos = nv50_disp_main_scanoutpos, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c index 951d79f9b781..55f0d3ac591e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c @@ -21,20 +21,16 @@ * * Authors: Ben Skeggs */ - -#include <engine/software.h> -#include <engine/disp.h> +#include "nv50.h" #include <nvif/class.h> -#include "nv50.h" - /******************************************************************************* * Base display object ******************************************************************************/ -static struct nouveau_oclass -nva3_disp_sclass[] = { +static struct nvkm_oclass +gt215_disp_sclass[] = { { GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, { GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, { GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, @@ -43,8 +39,8 @@ nva3_disp_sclass[] = { {} }; -static struct nouveau_oclass -nva3_disp_main_oclass[] = { +static struct nvkm_oclass +gt215_disp_main_oclass[] = { { GT214_DISP, &nv50_disp_main_ofuncs }, {} }; @@ -54,15 +50,15 @@ nva3_disp_main_oclass[] = { ******************************************************************************/ static int -nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int ret; - ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", + "display", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -71,11 +67,11 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, if (ret) return ret; - nv_engine(priv)->sclass = nva3_disp_main_oclass; + nv_engine(priv)->sclass = gt215_disp_main_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); - priv->sclass = nva3_disp_sclass; + priv->sclass = gt215_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; priv->sor.nr = 4; @@ -83,26 +79,26 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = nva3_hda_eld; - priv->sor.hdmi = nva3_hdmi_ctrl; + priv->sor.hda_eld = gt215_hda_eld; + priv->sor.hdmi = gt215_hdmi_ctrl; priv->pior.power = nv50_pior_power; return 0; } -struct nouveau_oclass * -nva3_disp_oclass = &(struct nv50_disp_impl) { +struct nvkm_oclass * +gt215_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x85), - .base.base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .base.base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gt215_disp_ctor, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, .base.vblank = &nv50_disp_vblank_func, - .base.outp = nv94_disp_outp_sclass, - .mthd.core = &nv94_disp_core_mthd_chan, - .mthd.base = &nv84_disp_base_mthd_chan, - .mthd.ovly = &nv84_disp_ovly_mthd_chan, + .base.outp = g94_disp_outp_sclass, + .mthd.core = &g94_disp_core_mthd_chan, + .mthd.base = &g84_disp_base_mthd_chan, + .mthd.ovly = &g84_disp_ovly_mthd_chan, .mthd.prev = 0x000004, .head.scanoutpos = nv50_disp_main_scanoutpos, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c index 1d4e8432d857..b9813d246ba5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c @@ -21,17 +21,19 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "outp.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - +#include <subdev/bios.h> +#include <subdev/bios/dcb.h> #include <subdev/timer.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> int -nvd0_hda_eld(NV50_DISP_MTHD_V1) +gf110_hda_eld(NV50_DISP_MTHD_V1) { union { struct nv50_disp_sor_hda_eld_v0 v0; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c index fe9ef5894dd4..891d1e7bf7d2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c @@ -21,17 +21,17 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "outp.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - #include <subdev/timer.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> int -nva3_hda_eld(NV50_DISP_MTHD_V1) +gt215_hda_eld(NV50_DISP_MTHD_V1) { union { struct nv50_disp_sor_hda_eld_v0 v0; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c index fa276dede9cd..621cb0b7ff19 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c @@ -21,15 +21,15 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> int -nv84_hdmi_ctrl(NV50_DISP_MTHD_V1) +g84_hdmi_ctrl(NV50_DISP_MTHD_V1) { const u32 hoff = (head * 0x800); union { diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c index bac4fc4570f0..c28449061bbd 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c @@ -21,15 +21,15 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> int -nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1) +gf110_hdmi_ctrl(NV50_DISP_MTHD_V1) { const u32 hoff = (head * 0x800); union { diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c index 528d14ec2f7f..ca34ff81ad7f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c @@ -21,15 +21,15 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> int -nve0_hdmi_ctrl(NV50_DISP_MTHD_V1) +gk104_hdmi_ctrl(NV50_DISP_MTHD_V1) { const u32 hoff = (head * 0x800); const u32 hdmi = (head * 0x400); diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c index 57eeed1d1942..b641c167dcfa 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c @@ -21,15 +21,16 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "outp.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> int -nva3_hdmi_ctrl(NV50_DISP_MTHD_V1) +gt215_hdmi_ctrl(NV50_DISP_MTHD_V1) { const u32 soff = outp->or * 0x800; union { diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c index 366f315fc9a5..ff09b2659c17 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c @@ -21,20 +21,20 @@ * * Authors: Ben Skeggs */ - #include "priv.h" #include <core/client.h> -#include <core/event.h> -#include <nvif/unpack.h> +#include <core/device.h> + #include <nvif/class.h> +#include <nvif/unpack.h> struct nv04_disp_priv { - struct nouveau_disp base; + struct nvkm_disp base; }; static int -nv04_disp_scanoutpos(struct nouveau_object *object, struct nv04_disp_priv *priv, +nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv, void *data, u32 size, int head) { const u32 hoff = head * 0x2000; @@ -75,7 +75,7 @@ nv04_disp_scanoutpos(struct nouveau_object *object, struct nv04_disp_priv *priv, } static int -nv04_disp_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size) +nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { union { struct nv04_disp_mthd_v0 v0; @@ -105,17 +105,17 @@ nv04_disp_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size) return -EINVAL; } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv04_disp_ofuncs = { - .ctor = _nouveau_object_ctor, - .dtor = nouveau_object_destroy, - .init = nouveau_object_init, - .fini = nouveau_object_fini, + .ctor = _nvkm_object_ctor, + .dtor = nvkm_object_destroy, + .init = nvkm_object_init, + .fini = nvkm_object_fini, .mthd = nv04_disp_mthd, - .ntfy = nouveau_disp_ntfy, + .ntfy = nvkm_disp_ntfy, }; -static struct nouveau_oclass +static struct nvkm_oclass nv04_disp_sclass[] = { { NV04_DISP, &nv04_disp_ofuncs }, {}, @@ -128,26 +128,26 @@ nv04_disp_sclass[] = { static void nv04_disp_vblank_init(struct nvkm_event *event, int type, int head) { - struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); + struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000001); } static void nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head) { - struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); + struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000000); } static const struct nvkm_event_func nv04_disp_vblank_func = { - .ctor = nouveau_disp_vblank_ctor, + .ctor = nvkm_disp_vblank_ctor, .init = nv04_disp_vblank_init, .fini = nv04_disp_vblank_fini, }; static void -nv04_disp_intr(struct nouveau_subdev *subdev) +nv04_disp_intr(struct nvkm_subdev *subdev) { struct nv04_disp_priv *priv = (void *)subdev; u32 crtc0 = nv_rd32(priv, 0x600100); @@ -155,12 +155,12 @@ nv04_disp_intr(struct nouveau_subdev *subdev) u32 pvideo; if (crtc0 & 0x00000001) { - nouveau_disp_vblank(&priv->base, 0); + nvkm_disp_vblank(&priv->base, 0); nv_wr32(priv, 0x600100, 0x00000001); } if (crtc1 & 0x00000001) { - nouveau_disp_vblank(&priv->base, 1); + nvkm_disp_vblank(&priv->base, 1); nv_wr32(priv, 0x602100, 0x00000001); } @@ -174,15 +174,15 @@ nv04_disp_intr(struct nouveau_subdev *subdev) } static int -nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_disp_priv *priv; int ret; - ret = nouveau_disp_create(parent, engine, oclass, 2, "DISPLAY", - "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY", + "display", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -192,14 +192,14 @@ nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * -nv04_disp_oclass = &(struct nouveau_disp_impl) { +struct nvkm_oclass * +nv04_disp_oclass = &(struct nvkm_disp_impl) { .base.handle = NV_ENGINE(DISP, 0x04), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, .vblank = &nv04_disp_vblank_func, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c index 44a8290aaea5..84ade810e27c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c @@ -21,35 +21,38 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "outp.h" +#include "outpdp.h" -#include <core/object.h> #include <core/client.h> -#include <core/parent.h> -#include <core/handle.h> +#include <core/device.h> +#include <core/engctx.h> #include <core/enum.h> -#include <nvif/unpack.h> -#include <nvif/class.h> -#include <nvif/event.h> - +#include <core/handle.h> +#include <core/ramht.h> +#include <engine/dmaobj.h> #include <subdev/bios.h> #include <subdev/bios/dcb.h> #include <subdev/bios/disp.h> #include <subdev/bios/init.h> #include <subdev/bios/pll.h> #include <subdev/devinit.h> -#include <subdev/timer.h> #include <subdev/fb.h> +#include <subdev/timer.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/event.h> +#include <nvif/unpack.h> /******************************************************************************* * EVO channel base class ******************************************************************************/ static int -nv50_disp_chan_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int head, +nv50_disp_chan_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, int head, int length, void **pobject) { const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs; @@ -62,9 +65,9 @@ nv50_disp_chan_create_(struct nouveau_object *parent, return -EBUSY; base->chan |= (1 << chid); - ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL, - (1ULL << NVDEV_ENGINE_DMAOBJ), - length, pobject); + ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, + (1ULL << NVDEV_ENGINE_DMAOBJ), + length, pobject); chan = *pobject; if (ret) return ret; @@ -80,7 +83,7 @@ nv50_disp_chan_destroy(struct nv50_disp_chan *chan) { struct nv50_disp_base *base = (void *)nv_object(chan)->parent; base->chan &= ~(1 << chan->chid); - nouveau_namedb_destroy(&chan->base); + nvkm_namedb_destroy(&chan->base); } static void @@ -109,7 +112,7 @@ nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid) } int -nv50_disp_chan_uevent_ctor(struct nouveau_object *object, void *data, u32 size, +nv50_disp_chan_uevent_ctor(struct nvkm_object *object, void *data, u32 size, struct nvkm_notify *notify) { struct nv50_disp_dmac *dmac = (void *)object; @@ -136,7 +139,7 @@ nv50_disp_chan_uevent = { }; int -nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type, +nv50_disp_chan_ntfy(struct nvkm_object *object, u32 type, struct nvkm_event **pevent) { struct nv50_disp_priv *priv = (void *)object->engine; @@ -151,7 +154,7 @@ nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type, } int -nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size) +nv50_disp_chan_map(struct nvkm_object *object, u64 *addr, u32 *size) { struct nv50_disp_chan *chan = (void *)object; *addr = nv_device_resource_start(nv_device(object), 0) + @@ -161,7 +164,7 @@ nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size) } u32 -nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr) +nv50_disp_chan_rd32(struct nvkm_object *object, u64 addr) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_chan *chan = (void *)object; @@ -169,7 +172,7 @@ nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr) } void -nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data) +nv50_disp_chan_wr32(struct nvkm_object *object, u64 addr, u32 data) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_chan *chan = (void *)object; @@ -181,28 +184,28 @@ nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data) ******************************************************************************/ static int -nv50_disp_dmac_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 name) +nv50_disp_dmac_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 name) { struct nv50_disp_base *base = (void *)parent->parent; struct nv50_disp_chan *chan = (void *)parent; u32 addr = nv_gpuobj(object)->node->offset; u32 chid = chan->chid; u32 data = (chid << 28) | (addr << 10) | chid; - return nouveau_ramht_insert(base->ramht, chid, name, data); + return nvkm_ramht_insert(base->ramht, chid, name, data); } static void -nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie) +nv50_disp_dmac_object_detach(struct nvkm_object *parent, int cookie) { struct nv50_disp_base *base = (void *)parent->parent; - nouveau_ramht_remove(base->ramht, cookie); + nvkm_ramht_remove(base->ramht, cookie); } static int -nv50_disp_dmac_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 pushbuf, int head, +nv50_disp_dmac_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 pushbuf, int head, int length, void **pobject) { struct nv50_disp_dmac *dmac; @@ -214,7 +217,7 @@ nv50_disp_dmac_create_(struct nouveau_object *parent, if (ret) return ret; - dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf); + dmac->pushdma = (void *)nvkm_handle_ref(parent, pushbuf); if (!dmac->pushdma) return -ENOENT; @@ -243,15 +246,15 @@ nv50_disp_dmac_create_(struct nouveau_object *parent, } void -nv50_disp_dmac_dtor(struct nouveau_object *object) +nv50_disp_dmac_dtor(struct nvkm_object *object) { struct nv50_disp_dmac *dmac = (void *)object; - nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma); + nvkm_object_ref(NULL, (struct nvkm_object **)&dmac->pushdma); nv50_disp_chan_destroy(&dmac->base); } static int -nv50_disp_dmac_init(struct nouveau_object *object) +nv50_disp_dmac_init(struct nvkm_object *object) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; @@ -284,7 +287,7 @@ nv50_disp_dmac_init(struct nouveau_object *object) } static int -nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend) +nv50_disp_dmac_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; @@ -314,7 +317,7 @@ static void nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c, const struct nv50_disp_mthd_list *list, int inst) { - struct nouveau_object *disp = nv_object(priv); + struct nvkm_object *disp = nv_object(priv); int i; for (i = 0; list->data[i].mthd; i++) { @@ -341,7 +344,7 @@ void nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head, const struct nv50_disp_mthd_chan *chan) { - struct nouveau_object *disp = nv_object(priv); + struct nvkm_object *disp = nv_object(priv); const struct nv50_disp_impl *impl = (void *)disp->oclass; const struct nv50_disp_mthd_list *list; int i, j; @@ -482,10 +485,10 @@ nv50_disp_core_mthd_chan = { }; int -nv50_disp_core_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_disp_core_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_disp_core_channel_dma_v0 v0; @@ -511,7 +514,7 @@ nv50_disp_core_ctor(struct nouveau_object *parent, } static int -nv50_disp_core_init(struct nouveau_object *object) +nv50_disp_core_init(struct nvkm_object *object) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; @@ -548,7 +551,7 @@ nv50_disp_core_init(struct nouveau_object *object) } static int -nv50_disp_core_fini(struct nouveau_object *object, bool suspend) +nv50_disp_core_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; @@ -638,10 +641,10 @@ nv50_disp_base_mthd_chan = { }; int -nv50_disp_base_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_disp_base_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_disp_base_channel_dma_v0 v0; @@ -728,10 +731,10 @@ nv50_disp_ovly_mthd_chan = { }; int -nv50_disp_ovly_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_disp_ovly_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_disp_overlay_channel_dma_v0 v0; @@ -780,9 +783,9 @@ nv50_disp_ovly_ofuncs = { ******************************************************************************/ static int -nv50_disp_pioc_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int head, +nv50_disp_pioc_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, int head, int length, void **pobject) { return nv50_disp_chan_create_(parent, engine, oclass, head, @@ -790,14 +793,14 @@ nv50_disp_pioc_create_(struct nouveau_object *parent, } void -nv50_disp_pioc_dtor(struct nouveau_object *object) +nv50_disp_pioc_dtor(struct nvkm_object *object) { struct nv50_disp_pioc *pioc = (void *)object; nv50_disp_chan_destroy(&pioc->base); } static int -nv50_disp_pioc_init(struct nouveau_object *object) +nv50_disp_pioc_init(struct nvkm_object *object) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; @@ -826,7 +829,7 @@ nv50_disp_pioc_init(struct nouveau_object *object) } static int -nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend) +nv50_disp_pioc_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; @@ -848,10 +851,10 @@ nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend) ******************************************************************************/ int -nv50_disp_oimm_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_disp_oimm_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_disp_overlay_v0 v0; @@ -896,10 +899,10 @@ nv50_disp_oimm_ofuncs = { ******************************************************************************/ int -nv50_disp_curs_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_disp_curs_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_disp_cursor_v0 v0; @@ -976,8 +979,7 @@ nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0) } int -nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) +nv50_disp_main_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine); union { @@ -1100,42 +1102,42 @@ nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd, } int -nv50_disp_main_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_disp_main_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv = (void *)engine; struct nv50_disp_base *base; int ret; - ret = nouveau_parent_create(parent, engine, oclass, 0, - priv->sclass, 0, &base); + ret = nvkm_parent_create(parent, engine, oclass, 0, + priv->sclass, 0, &base); *pobject = nv_object(base); if (ret) return ret; - return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0, - &base->ramht); + return nvkm_ramht_new(nv_object(base), nv_object(base), 0x1000, 0, + &base->ramht); } void -nv50_disp_main_dtor(struct nouveau_object *object) +nv50_disp_main_dtor(struct nvkm_object *object) { struct nv50_disp_base *base = (void *)object; - nouveau_ramht_ref(NULL, &base->ramht); - nouveau_parent_destroy(&base->base); + nvkm_ramht_ref(NULL, &base->ramht); + nvkm_parent_destroy(&base->base); } static int -nv50_disp_main_init(struct nouveau_object *object) +nv50_disp_main_init(struct nvkm_object *object) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_base *base = (void *)object; int ret, i; u32 tmp; - ret = nouveau_parent_init(&base->base); + ret = nvkm_parent_init(&base->base); if (ret) return ret; @@ -1196,7 +1198,7 @@ nv50_disp_main_init(struct nouveau_object *object) } static int -nv50_disp_main_fini(struct nouveau_object *object, bool suspend) +nv50_disp_main_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_base *base = (void *)object; @@ -1205,26 +1207,26 @@ nv50_disp_main_fini(struct nouveau_object *object, bool suspend) nv_wr32(priv, 0x610024, 0x00000000); nv_wr32(priv, 0x610020, 0x00000000); - return nouveau_parent_fini(&base->base, suspend); + return nvkm_parent_fini(&base->base, suspend); } -struct nouveau_ofuncs +struct nvkm_ofuncs nv50_disp_main_ofuncs = { .ctor = nv50_disp_main_ctor, .dtor = nv50_disp_main_dtor, .init = nv50_disp_main_init, .fini = nv50_disp_main_fini, .mthd = nv50_disp_main_mthd, - .ntfy = nouveau_disp_ntfy, + .ntfy = nvkm_disp_ntfy, }; -static struct nouveau_oclass +static struct nvkm_oclass nv50_disp_main_oclass[] = { { NV50_DISP, &nv50_disp_main_ofuncs }, {} }; -static struct nouveau_oclass +static struct nvkm_oclass nv50_disp_sclass[] = { { NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, { NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, @@ -1240,13 +1242,13 @@ nv50_disp_sclass[] = { ******************************************************************************/ static int -nv50_disp_data_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_disp_data_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv = (void *)engine; - struct nouveau_engctx *ectx; + struct nvkm_engctx *ectx; int ret = -EBUSY; /* no context needed for channel objects... */ @@ -1259,25 +1261,24 @@ nv50_disp_data_ctor(struct nouveau_object *parent, /* allocate display hardware to client */ mutex_lock(&nv_subdev(priv)->mutex); if (list_empty(&nv_engine(priv)->contexts)) { - ret = nouveau_engctx_create(parent, engine, oclass, NULL, - 0x10000, 0x10000, - NVOBJ_FLAG_HEAP, &ectx); + ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, + 0x10000, NVOBJ_FLAG_HEAP, &ectx); *pobject = nv_object(ectx); } mutex_unlock(&nv_subdev(priv)->mutex); return ret; } -struct nouveau_oclass +struct nvkm_oclass nv50_disp_cclass = { .handle = NV_ENGCTX(DISP, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_disp_data_ctor, - .dtor = _nouveau_engctx_dtor, - .init = _nouveau_engctx_init, - .fini = _nouveau_engctx_fini, - .rd32 = _nouveau_engctx_rd32, - .wr32 = _nouveau_engctx_wr32, + .dtor = _nvkm_engctx_dtor, + .init = _nvkm_engctx_init, + .fini = _nvkm_engctx_fini, + .rd32 = _nvkm_engctx_rd32, + .wr32 = _nvkm_engctx_wr32, }, }; @@ -1288,25 +1289,25 @@ nv50_disp_cclass = { static void nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head) { - struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); + struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); nv_mask(disp, 0x61002c, (4 << head), 0); } static void nv50_disp_vblank_init(struct nvkm_event *event, int type, int head) { - struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); + struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); nv_mask(disp, 0x61002c, (4 << head), (4 << head)); } const struct nvkm_event_func nv50_disp_vblank_func = { - .ctor = nouveau_disp_vblank_ctor, + .ctor = nvkm_disp_vblank_ctor, .init = nv50_disp_vblank_init, .fini = nv50_disp_vblank_fini, }; -static const struct nouveau_enum +static const struct nvkm_enum nv50_disp_intr_error_type[] = { { 3, "ILLEGAL_MTHD" }, { 4, "INVALID_VALUE" }, @@ -1315,7 +1316,7 @@ nv50_disp_intr_error_type[] = { {} }; -static const struct nouveau_enum +static const struct nvkm_enum nv50_disp_intr_error_code[] = { { 0x00, "" }, {} @@ -1330,14 +1331,14 @@ nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) u32 code = (addr & 0x00ff0000) >> 16; u32 type = (addr & 0x00007000) >> 12; u32 mthd = (addr & 0x00000ffc); - const struct nouveau_enum *ec, *et; + const struct nvkm_enum *ec, *et; char ecunk[6], etunk[6]; - et = nouveau_enum_find(nv50_disp_intr_error_type, type); + et = nvkm_enum_find(nv50_disp_intr_error_type, type); if (!et) snprintf(etunk, sizeof(etunk), "UNK%02X", type); - ec = nouveau_enum_find(nv50_disp_intr_error_code, code); + ec = nvkm_enum_find(nv50_disp_intr_error_code, code); if (!ec) snprintf(ecunk, sizeof(ecunk), "UNK%02X", code); @@ -1385,7 +1386,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *info) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvkm_output *outp; u16 mask, type; @@ -1440,7 +1441,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, static struct nvkm_output * exec_script(struct nv50_disp_priv *priv, int head, int id) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvkm_output *outp; struct nvbios_outp info; u8 ver, hdr, cnt, len; @@ -1497,7 +1498,7 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) static struct nvkm_output * exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvkm_output *outp; struct nvbios_outp info1; struct nvbios_ocfg info2; @@ -1610,7 +1611,7 @@ nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head) struct nvkm_output_dp *outpdp = (void *)outp; struct nvbios_init init = { .subdev = nv_subdev(priv), - .bios = nouveau_bios(priv), + .bios = nvkm_bios(priv), .outp = &outp->info, .crtc = head, .offset = outpdp->info.script[4], @@ -1625,7 +1626,7 @@ nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head) static void nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head) { - struct nouveau_devinit *devinit = nouveau_devinit(priv); + struct nvkm_devinit *devinit = nvkm_devinit(priv); u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; if (pclk) devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); @@ -1841,9 +1842,10 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) * programmed for DisplayPort. */ static void -nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp) +nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, + struct dcb_output *outp) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); const int link = !(outp->sorconf.link & 1); const int or = ffs(outp->or) - 1; const u32 loff = (or * 0x800) + (link * 0x80); @@ -1920,7 +1922,7 @@ nv50_disp_intr_supervisor(struct work_struct *work) } void -nv50_disp_intr(struct nouveau_subdev *subdev) +nv50_disp_intr(struct nvkm_subdev *subdev) { struct nv50_disp_priv *priv = (void *)subdev; u32 intr0 = nv_rd32(priv, 0x610020); @@ -1939,13 +1941,13 @@ nv50_disp_intr(struct nouveau_subdev *subdev) } if (intr1 & 0x00000004) { - nouveau_disp_vblank(&priv->base, 0); + nvkm_disp_vblank(&priv->base, 0); nv_wr32(priv, 0x610024, 0x00000004); intr1 &= ~0x00000004; } if (intr1 & 0x00000008) { - nouveau_disp_vblank(&priv->base, 1); + nvkm_disp_vblank(&priv->base, 1); nv_wr32(priv, 0x610024, 0x00000008); intr1 &= ~0x00000008; } @@ -1959,15 +1961,15 @@ nv50_disp_intr(struct nouveau_subdev *subdev) } static int -nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_disp_priv *priv; int ret; - ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); + ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", + "display", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -1992,20 +1994,20 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv50_disp_outp_sclass[] = { &nv50_pior_dp_impl.base.base, NULL }; -struct nouveau_oclass * +struct nvkm_oclass * nv50_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x50), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_disp_ctor, - .dtor = _nouveau_disp_dtor, - .init = _nouveau_disp_init, - .fini = _nouveau_disp_fini, + .dtor = _nvkm_disp_dtor, + .init = _nvkm_disp_init, + .fini = _nvkm_disp_fini, }, .base.vblank = &nv50_disp_vblank_func, .base.outp = nv50_disp_outp_sclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h new file mode 100644 index 000000000000..b4ed620070fa --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h @@ -0,0 +1,226 @@ +#ifndef __NV50_DISP_H__ +#define __NV50_DISP_H__ +#include "priv.h" +struct nvkm_output; +struct nvkm_output_dp; + +#define NV50_DISP_MTHD_ struct nvkm_object *object, \ + struct nv50_disp_priv *priv, void *data, u32 size +#define NV50_DISP_MTHD_V0 NV50_DISP_MTHD_, int head +#define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp + +struct nv50_disp_priv { + struct nvkm_disp base; + struct nvkm_oclass *sclass; + + struct work_struct supervisor; + u32 super; + + struct nvkm_event uevent; + + struct { + int nr; + } head; + struct { + int nr; + int (*power)(NV50_DISP_MTHD_V1); + int (*sense)(NV50_DISP_MTHD_V1); + } dac; + struct { + int nr; + int (*power)(NV50_DISP_MTHD_V1); + int (*hda_eld)(NV50_DISP_MTHD_V1); + int (*hdmi)(NV50_DISP_MTHD_V1); + u32 lvdsconf; + void (*magic)(struct nvkm_output *); + } sor; + struct { + int nr; + int (*power)(NV50_DISP_MTHD_V1); + u8 type[3]; + } pior; +}; + +struct nv50_disp_impl { + struct nvkm_disp_impl base; + struct { + const struct nv50_disp_mthd_chan *core; + const struct nv50_disp_mthd_chan *base; + const struct nv50_disp_mthd_chan *ovly; + int prev; + } mthd; + struct { + int (*scanoutpos)(NV50_DISP_MTHD_V0); + } head; +}; + +int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0); +int nv50_disp_main_mthd(struct nvkm_object *, u32, void *, u32); + +int gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0); + +int nv50_dac_power(NV50_DISP_MTHD_V1); +int nv50_dac_sense(NV50_DISP_MTHD_V1); + +int gt215_hda_eld(NV50_DISP_MTHD_V1); +int gf110_hda_eld(NV50_DISP_MTHD_V1); + +int g84_hdmi_ctrl(NV50_DISP_MTHD_V1); +int gt215_hdmi_ctrl(NV50_DISP_MTHD_V1); +int gf110_hdmi_ctrl(NV50_DISP_MTHD_V1); +int gk104_hdmi_ctrl(NV50_DISP_MTHD_V1); + +int nv50_sor_power(NV50_DISP_MTHD_V1); +int nv50_pior_power(NV50_DISP_MTHD_V1); + +#include <core/parent.h> + +struct nv50_disp_base { + struct nvkm_parent base; + struct nvkm_ramht *ramht; + u32 chan; +}; + +struct nv50_disp_chan_impl { + struct nvkm_ofuncs base; + int chid; + int (*attach)(struct nvkm_object *, struct nvkm_object *, u32); + void (*detach)(struct nvkm_object *, int); +}; + +#include <core/namedb.h> + +struct nv50_disp_chan { + struct nvkm_namedb base; + int chid; +}; + +int nv50_disp_chan_ntfy(struct nvkm_object *, u32, struct nvkm_event **); +int nv50_disp_chan_map(struct nvkm_object *, u64 *, u32 *); +u32 nv50_disp_chan_rd32(struct nvkm_object *, u64); +void nv50_disp_chan_wr32(struct nvkm_object *, u64, u32); +extern const struct nvkm_event_func nv50_disp_chan_uevent; +int nv50_disp_chan_uevent_ctor(struct nvkm_object *, void *, u32, + struct nvkm_notify *); +void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int); + +extern const struct nvkm_event_func gf110_disp_chan_uevent; + +#define nv50_disp_chan_init(a) \ + nvkm_namedb_init(&(a)->base) +#define nv50_disp_chan_fini(a,b) \ + nvkm_namedb_fini(&(a)->base, (b)) + +struct nv50_disp_dmac { + struct nv50_disp_chan base; + struct nvkm_dmaobj *pushdma; + u32 push; +}; + +void nv50_disp_dmac_dtor(struct nvkm_object *); + +struct nv50_disp_pioc { + struct nv50_disp_chan base; +}; + +void nv50_disp_pioc_dtor(struct nvkm_object *); + +struct nv50_disp_mthd_list { + u32 mthd; + u32 addr; + struct { + u32 mthd; + u32 addr; + const char *name; + } data[]; +}; + +struct nv50_disp_mthd_chan { + const char *name; + u32 addr; + struct { + const char *name; + int nr; + const struct nv50_disp_mthd_list *mthd; + } data[]; +}; + +extern struct nv50_disp_chan_impl nv50_disp_core_ofuncs; +int nv50_disp_core_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base; +extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor; +extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior; +extern struct nv50_disp_chan_impl nv50_disp_base_ofuncs; +int nv50_disp_base_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image; +extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs; +int nv50_disp_ovly_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base; +extern struct nv50_disp_chan_impl nv50_disp_oimm_ofuncs; +int nv50_disp_oimm_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs; +int nv50_disp_curs_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +extern struct nvkm_ofuncs nv50_disp_main_ofuncs; +int nv50_disp_main_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nv50_disp_main_dtor(struct nvkm_object *); +extern struct nvkm_omthds nv50_disp_main_omthds[]; +extern struct nvkm_oclass nv50_disp_cclass; +void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head, + const struct nv50_disp_mthd_chan *); +void nv50_disp_intr_supervisor(struct work_struct *); +void nv50_disp_intr(struct nvkm_subdev *); +extern const struct nvkm_event_func nv50_disp_vblank_func; + +extern const struct nv50_disp_mthd_chan g84_disp_core_mthd_chan; +extern const struct nv50_disp_mthd_list g84_disp_core_mthd_dac; +extern const struct nv50_disp_mthd_list g84_disp_core_mthd_head; +extern const struct nv50_disp_mthd_chan g84_disp_base_mthd_chan; +extern const struct nv50_disp_mthd_chan g84_disp_ovly_mthd_chan; + +extern const struct nv50_disp_mthd_chan g94_disp_core_mthd_chan; + +extern struct nv50_disp_chan_impl gf110_disp_core_ofuncs; +extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_base; +extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_dac; +extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_sor; +extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_pior; +extern struct nv50_disp_chan_impl gf110_disp_base_ofuncs; +extern struct nv50_disp_chan_impl gf110_disp_ovly_ofuncs; +extern const struct nv50_disp_mthd_chan gf110_disp_base_mthd_chan; +extern struct nv50_disp_chan_impl gf110_disp_oimm_ofuncs; +extern struct nv50_disp_chan_impl gf110_disp_curs_ofuncs; +extern struct nvkm_ofuncs gf110_disp_main_ofuncs; +extern struct nvkm_oclass gf110_disp_cclass; +void gf110_disp_intr_supervisor(struct work_struct *); +void gf110_disp_intr(struct nvkm_subdev *); +extern const struct nvkm_event_func gf110_disp_vblank_func; + +extern const struct nv50_disp_mthd_chan gk104_disp_core_mthd_chan; +extern const struct nv50_disp_mthd_chan gk104_disp_ovly_mthd_chan; + +extern struct nvkm_output_dp_impl nv50_pior_dp_impl; +extern struct nvkm_oclass *nv50_disp_outp_sclass[]; + +extern struct nvkm_output_dp_impl g94_sor_dp_impl; +int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int); +extern struct nvkm_oclass *g94_disp_outp_sclass[]; + +extern struct nvkm_output_dp_impl gf110_sor_dp_impl; +int gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool); +extern struct nvkm_oclass *gf110_disp_outp_sclass[]; + +void gm204_sor_magic(struct nvkm_output *outp); +extern struct nvkm_output_dp_impl gm204_sor_dp_impl; +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c index bbd9b6fdc90f..9224bcbf0159 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/outp.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c @@ -21,57 +21,58 @@ * * Authors: Ben Skeggs */ +#include "outp.h" +#include "priv.h" -#include <subdev/i2c.h> #include <subdev/bios.h> #include <subdev/bios/conn.h> - -#include "outp.h" +#include <subdev/bios/dcb.h> +#include <subdev/i2c.h> int -_nvkm_output_fini(struct nouveau_object *object, bool suspend) +_nvkm_output_fini(struct nvkm_object *object, bool suspend) { struct nvkm_output *outp = (void *)object; nv_ofuncs(outp->conn)->fini(nv_object(outp->conn), suspend); - return nouveau_object_fini(&outp->base, suspend); + return nvkm_object_fini(&outp->base, suspend); } int -_nvkm_output_init(struct nouveau_object *object) +_nvkm_output_init(struct nvkm_object *object) { struct nvkm_output *outp = (void *)object; - int ret = nouveau_object_init(&outp->base); + int ret = nvkm_object_init(&outp->base); if (ret == 0) nv_ofuncs(outp->conn)->init(nv_object(outp->conn)); return 0; } void -_nvkm_output_dtor(struct nouveau_object *object) +_nvkm_output_dtor(struct nvkm_object *object) { struct nvkm_output *outp = (void *)object; list_del(&outp->head); - nouveau_object_ref(NULL, (void *)&outp->conn); - nouveau_object_destroy(&outp->base); + nvkm_object_ref(NULL, (void *)&outp->conn); + nvkm_object_destroy(&outp->base); } int -nvkm_output_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, +nvkm_output_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, struct dcb_output *dcbE, int index, int length, void **pobject) { - struct nouveau_bios *bios = nouveau_bios(engine); - struct nouveau_i2c *i2c = nouveau_i2c(parent); - struct nouveau_disp *disp = (void *)engine; + struct nvkm_disp *disp = nvkm_disp(parent); + struct nvkm_bios *bios = nvkm_bios(parent); + struct nvkm_i2c *i2c = nvkm_i2c(parent); struct nvbios_connE connE; struct nvkm_output *outp; u8 ver, hdr; u32 data; int ret; - ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject); + ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); outp = *pobject; if (ret) return ret; @@ -98,9 +99,9 @@ nvkm_output_create_(struct nouveau_object *parent, connE.type = DCB_CONNECTOR_NONE; } - ret = nouveau_object_ctor(parent, engine, nvkm_connector_oclass, - &connE, outp->info.connector, - (struct nouveau_object **)&outp->conn); + ret = nvkm_object_ctor(parent, NULL, nvkm_connector_oclass, + &connE, outp->info.connector, + (struct nvkm_object **)&outp->conn); if (ret < 0) { ERR("error %d creating connector, disabling\n", ret); return ret; @@ -111,10 +112,10 @@ nvkm_output_create_(struct nouveau_object *parent, } int -_nvkm_output_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *dcbE, u32 index, - struct nouveau_object **pobject) +_nvkm_output_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *dcbE, u32 index, + struct nvkm_object **pobject) { struct nvkm_output *outp; int ret; @@ -127,11 +128,11 @@ _nvkm_output_ctor(struct nouveau_object *parent, return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nvkm_output_oclass = &(struct nvkm_output_impl) { .base = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_output_ctor, .dtor = _nvkm_output_dtor, .init = _nvkm_output_init, diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h index 187f435ad0e2..d9253d26c31b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/outp.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h @@ -1,18 +1,20 @@ #ifndef __NVKM_DISP_OUTP_H__ #define __NVKM_DISP_OUTP_H__ +#include <core/object.h> -#include "priv.h" +#include <subdev/bios.h> +#include <subdev/bios/dcb.h> struct nvkm_output { - struct nouveau_object base; + struct nvkm_object base; struct list_head head; struct dcb_output info; int index; int or; - struct nouveau_i2c_port *port; - struct nouveau_i2c_port *edid; + struct nvkm_i2c_port *port; + struct nvkm_i2c_port *edid; struct nvkm_connector *conn; }; @@ -32,29 +34,28 @@ struct nvkm_output { _nvkm_output_fini(nv_object(_outp), (s)); \ }) -int nvkm_output_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, struct dcb_output *, +int nvkm_output_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, struct dcb_output *, int, int, void **); -int _nvkm_output_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void _nvkm_output_dtor(struct nouveau_object *); -int _nvkm_output_init(struct nouveau_object *); -int _nvkm_output_fini(struct nouveau_object *, bool); +int _nvkm_output_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void _nvkm_output_dtor(struct nvkm_object *); +int _nvkm_output_init(struct nvkm_object *); +int _nvkm_output_fini(struct nvkm_object *, bool); struct nvkm_output_impl { - struct nouveau_oclass base; + struct nvkm_oclass base; }; #ifndef MSG #define MSG(l,f,a...) do { \ struct nvkm_output *_outp = (void *)outp; \ - nv_##l(nv_object(outp)->engine, "%02x:%04x:%04x: "f, _outp->index, \ + nv_##l(_outp, "%02x:%04x:%04x: "f, _outp->index, \ _outp->info.hasht, _outp->info.hashm, ##a); \ } while(0) #define DBG(f,a...) MSG(debug, f, ##a) #define ERR(f,a...) MSG(error, f, ##a) #endif - #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c index 667a9070e006..0bde0fa5b59d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c @@ -21,15 +21,14 @@ * * Authors: Ben Skeggs */ - -#include <core/os.h> -#include <nvif/event.h> - -#include <subdev/i2c.h> - #include "outpdp.h" #include "conn.h" #include "dport.h" +#include "priv.h" + +#include <subdev/i2c.h> + +#include <nvif/event.h> int nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait) @@ -105,17 +104,17 @@ done: static void nvkm_output_dp_enable(struct nvkm_output_dp *outp, bool present) { - struct nouveau_i2c_port *port = outp->base.edid; + struct nvkm_i2c_port *port = outp->base.edid; if (present) { if (!outp->present) { - nouveau_i2c(port)->acquire_pad(port, 0); + nvkm_i2c(port)->acquire_pad(port, 0); DBG("aux power -> always\n"); outp->present = true; } nvkm_output_dp_train(&outp->base, 0, true); } else { if (outp->present) { - nouveau_i2c(port)->release_pad(port); + nvkm_i2c(port)->release_pad(port); DBG("aux power -> demand\n"); outp->present = false; } @@ -126,13 +125,13 @@ nvkm_output_dp_enable(struct nvkm_output_dp *outp, bool present) static void nvkm_output_dp_detect(struct nvkm_output_dp *outp) { - struct nouveau_i2c_port *port = outp->base.edid; - int ret = nouveau_i2c(port)->acquire_pad(port, 0); + struct nvkm_i2c_port *port = outp->base.edid; + int ret = nvkm_i2c(port)->acquire_pad(port, 0); if (ret == 0) { ret = nv_rdaux(outp->base.edid, DPCD_RC00_DPCD_REV, outp->dpcd, sizeof(outp->dpcd)); nvkm_output_dp_enable(outp, ret == 0); - nouveau_i2c(port)->release_pad(port); + nvkm_i2c(port)->release_pad(port); } } @@ -141,7 +140,7 @@ nvkm_output_dp_hpd(struct nvkm_notify *notify) { struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd); struct nvkm_output_dp *outp; - struct nouveau_disp *disp = nouveau_disp(conn); + struct nvkm_disp *disp = nvkm_disp(conn); const struct nvkm_i2c_ntfy_rep *line = notify->data; struct nvif_notify_conn_rep_v0 rep = {}; @@ -170,7 +169,7 @@ static int nvkm_output_dp_irq(struct nvkm_notify *notify) { struct nvkm_output_dp *outp = container_of(notify, typeof(*outp), irq); - struct nouveau_disp *disp = nouveau_disp(outp); + struct nvkm_disp *disp = nvkm_disp(outp); const struct nvkm_i2c_ntfy_rep *line = notify->data; struct nvif_notify_conn_rep_v0 rep = { .mask = NVIF_NOTIFY_CONN_V0_IRQ, @@ -185,7 +184,7 @@ nvkm_output_dp_irq(struct nvkm_notify *notify) } int -_nvkm_output_dp_fini(struct nouveau_object *object, bool suspend) +_nvkm_output_dp_fini(struct nvkm_object *object, bool suspend) { struct nvkm_output_dp *outp = (void *)object; nvkm_notify_put(&outp->irq); @@ -194,7 +193,7 @@ _nvkm_output_dp_fini(struct nouveau_object *object, bool suspend) } int -_nvkm_output_dp_init(struct nouveau_object *object) +_nvkm_output_dp_init(struct nvkm_object *object) { struct nvkm_output_dp *outp = (void *)object; nvkm_output_dp_detect(outp); @@ -202,7 +201,7 @@ _nvkm_output_dp_init(struct nouveau_object *object) } void -_nvkm_output_dp_dtor(struct nouveau_object *object) +_nvkm_output_dp_dtor(struct nvkm_object *object) { struct nvkm_output_dp *outp = (void *)object; nvkm_notify_fini(&outp->irq); @@ -210,14 +209,14 @@ _nvkm_output_dp_dtor(struct nouveau_object *object) } int -nvkm_output_dp_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, +nvkm_output_dp_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, struct dcb_output *info, int index, int length, void **pobject) { - struct nouveau_bios *bios = nouveau_bios(parent); - struct nouveau_i2c *i2c = nouveau_i2c(parent); + struct nvkm_bios *bios = nvkm_bios(parent); + struct nvkm_i2c *i2c = nvkm_i2c(parent); struct nvkm_output_dp *outp; u8 hdr, cnt, len; u32 data; @@ -249,7 +248,7 @@ nvkm_output_dp_create_(struct nouveau_object *parent, DBG("bios dp %02x %02x %02x %02x\n", outp->version, hdr, cnt, len); /* link training */ - INIT_WORK(&outp->lt.work, nouveau_dp_train); + INIT_WORK(&outp->lt.work, nvkm_dp_train); init_waitqueue_head(&outp->lt.wait); atomic_set(&outp->lt.done, 0); @@ -285,10 +284,10 @@ nvkm_output_dp_create_(struct nouveau_object *parent, } int -_nvkm_output_dp_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *info, u32 index, - struct nouveau_object **pobject) +_nvkm_output_dp_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *info, u32 index, + struct nvkm_object **pobject) { struct nvkm_output_dp *outp; int ret; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h index 1fac367cc867..70c77aec4850 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h @@ -1,11 +1,11 @@ #ifndef __NVKM_DISP_OUTP_DP_H__ #define __NVKM_DISP_OUTP_DP_H__ +#include "outp.h" +#include <core/notify.h> #include <subdev/bios.h> #include <subdev/bios/dp.h> -#include "outp.h" - struct nvkm_output_dp { struct nvkm_output base; @@ -38,16 +38,16 @@ struct nvkm_output_dp { _nvkm_output_dp_fini(nv_object(_outp), (s)); \ }) -int nvkm_output_dp_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, struct dcb_output *, +int nvkm_output_dp_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, struct dcb_output *, int, int, void **); -int _nvkm_output_dp_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void _nvkm_output_dp_dtor(struct nouveau_object *); -int _nvkm_output_dp_init(struct nouveau_object *); -int _nvkm_output_dp_fini(struct nouveau_object *, bool); +int _nvkm_output_dp_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void _nvkm_output_dp_dtor(struct nvkm_object *); +int _nvkm_output_dp_init(struct nvkm_object *); +int _nvkm_output_dp_fini(struct nvkm_object *, bool); struct nvkm_output_dp_impl { struct nvkm_output_impl base; @@ -58,5 +58,4 @@ struct nvkm_output_dp_impl { }; int nvkm_output_dp_train(struct nvkm_output *, u32 rate, bool wait); - #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c index d00f89a468a7..2a1d8871bf82 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c @@ -21,29 +21,27 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "outpdp.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <subdev/bios.h> -#include <subdev/bios/dcb.h> -#include <subdev/timer.h> #include <subdev/i2c.h> +#include <subdev/timer.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> /****************************************************************************** * TMDS *****************************************************************************/ static int -nv50_pior_tmds_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *info, u32 index, - struct nouveau_object **pobject) +nv50_pior_tmds_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *info, u32 index, + struct nvkm_object **pobject) { - struct nouveau_i2c *i2c = nouveau_i2c(parent); + struct nvkm_i2c *i2c = nvkm_i2c(parent); struct nvkm_output *outp; int ret; @@ -59,7 +57,7 @@ nv50_pior_tmds_ctor(struct nouveau_object *parent, struct nvkm_output_impl nv50_pior_tmds_impl = { .base.handle = DCB_OUTPUT_TMDS | 0x0100, - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_pior_tmds_ctor, .dtor = _nvkm_output_dtor, .init = _nvkm_output_init, @@ -74,7 +72,7 @@ nv50_pior_tmds_impl = { static int nv50_pior_dp_pattern(struct nvkm_output_dp *outp, int pattern) { - struct nouveau_i2c_port *port = outp->base.edid; + struct nvkm_i2c_port *port = outp->base.edid; if (port && port->func->pattern) return port->func->pattern(port, pattern); return port ? 0 : -ENODEV; @@ -89,7 +87,7 @@ nv50_pior_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) static int nv50_pior_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) { - struct nouveau_i2c_port *port = outp->base.edid; + struct nvkm_i2c_port *port = outp->base.edid; if (port && port->func->lnk_ctl) return port->func->lnk_ctl(port, nr, bw, ef); return port ? 0 : -ENODEV; @@ -98,19 +96,19 @@ nv50_pior_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) static int nv50_pior_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { - struct nouveau_i2c_port *port = outp->base.edid; + struct nvkm_i2c_port *port = outp->base.edid; if (port && port->func->drv_ctl) return port->func->drv_ctl(port, ln, vs, pe); return port ? 0 : -ENODEV; } static int -nv50_pior_dp_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *info, u32 index, - struct nouveau_object **pobject) +nv50_pior_dp_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *info, u32 index, + struct nvkm_object **pobject) { - struct nouveau_i2c *i2c = nouveau_i2c(parent); + struct nvkm_i2c *i2c = nvkm_i2c(parent); struct nvkm_output_dp *outp; int ret; @@ -127,7 +125,7 @@ nv50_pior_dp_ctor(struct nouveau_object *parent, struct nvkm_output_dp_impl nv50_pior_dp_impl = { .base.base.handle = DCB_OUTPUT_DP | 0x0010, - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_pior_dp_ctor, .dtor = _nvkm_output_dp_dtor, .init = _nvkm_output_dp_init, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h new file mode 100644 index 000000000000..961ce8bb2135 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h @@ -0,0 +1,42 @@ +#ifndef __NVKM_DISP_PRIV_H__ +#define __NVKM_DISP_PRIV_H__ +#include <engine/disp.h> + +struct nvkm_disp_impl { + struct nvkm_oclass base; + struct nvkm_oclass **outp; + struct nvkm_oclass **conn; + const struct nvkm_event_func *vblank; +}; + +#define nvkm_disp_create(p,e,c,h,i,x,d) \ + nvkm_disp_create_((p), (e), (c), (h), (i), (x), \ + sizeof(**d), (void **)d) +#define nvkm_disp_destroy(d) ({ \ + struct nvkm_disp *disp = (d); \ + _nvkm_disp_dtor(nv_object(disp)); \ +}) +#define nvkm_disp_init(d) ({ \ + struct nvkm_disp *disp = (d); \ + _nvkm_disp_init(nv_object(disp)); \ +}) +#define nvkm_disp_fini(d,s) ({ \ + struct nvkm_disp *disp = (d); \ + _nvkm_disp_fini(nv_object(disp), (s)); \ +}) + +int nvkm_disp_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int heads, + const char *, const char *, int, void **); +void _nvkm_disp_dtor(struct nvkm_object *); +int _nvkm_disp_init(struct nvkm_object *); +int _nvkm_disp_fini(struct nvkm_object *, bool); + +extern struct nvkm_oclass *nvkm_output_oclass; +extern struct nvkm_oclass *nvkm_connector_oclass; + +int nvkm_disp_vblank_ctor(struct nvkm_object *, void *data, u32 size, + struct nvkm_notify *); +void nvkm_disp_vblank(struct nvkm_disp *, int head); +int nvkm_disp_ntfy(struct nvkm_object *, u32, struct nvkm_event **); +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c index 39f85d627336..8918da7ffdf2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c @@ -21,59 +21,53 @@ * * Authors: Ben Skeggs */ - -#include <core/os.h> - -#include <subdev/bios.h> -#include <subdev/bios/dcb.h> -#include <subdev/bios/dp.h> -#include <subdev/bios/init.h> -#include <subdev/timer.h> - #include "nv50.h" #include "outpdp.h" +#include <core/device.h> +#include <subdev/timer.h> + static inline u32 -nv94_sor_soff(struct nvkm_output_dp *outp) +g94_sor_soff(struct nvkm_output_dp *outp) { return (ffs(outp->base.info.or) - 1) * 0x800; } static inline u32 -nv94_sor_loff(struct nvkm_output_dp *outp) +g94_sor_loff(struct nvkm_output_dp *outp) { - return nv94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; + return g94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; } static inline u32 -nv94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) +g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) { - static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ - static const u8 nv94[] = { 16, 8, 0, 24 }; + static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ + static const u8 g94[] = { 16, 8, 0, 24 }; if (nv_device(priv)->chipset == 0xaf) - return nvaf[lane]; - return nv94[lane]; + return mcp89[lane]; + return g94[lane]; } static int -nv94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) +g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); - const u32 loff = nv94_sor_loff(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + const u32 loff = g94_sor_loff(outp); nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24); return 0; } int -nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) +g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); - const u32 soff = nv94_sor_soff(outp); - const u32 loff = nv94_sor_loff(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + const u32 soff = g94_sor_soff(outp); + const u32 loff = g94_sor_loff(outp); u32 mask = 0, i; for (i = 0; i < nr; i++) - mask |= 1 << (nv94_sor_dp_lane_map(priv, i) >> 3); + mask |= 1 << (g94_sor_dp_lane_map(priv, i) >> 3); nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask); nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000); @@ -82,11 +76,11 @@ nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) } static int -nv94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) +g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); - const u32 soff = nv94_sor_soff(outp); - const u32 loff = nv94_sor_loff(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + const u32 soff = g94_sor_soff(outp); + const u32 loff = g94_sor_loff(outp); u32 dpctrl = 0x00000000; u32 clksor = 0x00000000; @@ -102,12 +96,12 @@ nv94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) } static int -nv94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) +g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); - struct nouveau_bios *bios = nouveau_bios(priv); - const u32 shift = nv94_sor_dp_lane_map(priv, ln); - const u32 loff = nv94_sor_loff(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nvkm_bios *bios = nvkm_bios(priv); + const u32 shift = g94_sor_dp_lane_map(priv, ln); + const u32 loff = g94_sor_loff(outp); u32 addr, data[3]; u8 ver, hdr, cnt, len; struct nvbios_dpout info; @@ -136,16 +130,16 @@ nv94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) } struct nvkm_output_dp_impl -nv94_sor_dp_impl = { +g94_sor_dp_impl = { .base.base.handle = DCB_OUTPUT_DP, - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_output_dp_ctor, .dtor = _nvkm_output_dp_dtor, .init = _nvkm_output_dp_init, .fini = _nvkm_output_dp_fini, }, - .pattern = nv94_sor_dp_pattern, - .lnk_pwr = nv94_sor_dp_lnk_pwr, - .lnk_ctl = nv94_sor_dp_lnk_ctl, - .drv_ctl = nv94_sor_dp_drv_ctl, + .pattern = g94_sor_dp_pattern, + .lnk_pwr = g94_sor_dp_lnk_pwr, + .lnk_ctl = g94_sor_dp_lnk_ctl, + .drv_ctl = g94_sor_dp_drv_ctl, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c index fdab2939070c..52fbe4880e13 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c @@ -21,51 +21,43 @@ * * Authors: Ben Skeggs */ - -#include <core/os.h> - -#include <subdev/bios.h> -#include <subdev/bios/dcb.h> -#include <subdev/bios/dp.h> -#include <subdev/bios/init.h> -#include <subdev/timer.h> - #include "nv50.h" +#include "outpdp.h" static inline u32 -nvd0_sor_soff(struct nvkm_output_dp *outp) +gf110_sor_soff(struct nvkm_output_dp *outp) { return (ffs(outp->base.info.or) - 1) * 0x800; } static inline u32 -nvd0_sor_loff(struct nvkm_output_dp *outp) +gf110_sor_loff(struct nvkm_output_dp *outp) { - return nvd0_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; + return gf110_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; } static inline u32 -nvd0_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) +gf110_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) { - static const u8 nvd0[] = { 16, 8, 0, 24 }; - return nvd0[lane]; + static const u8 gf110[] = { 16, 8, 0, 24 }; + return gf110[lane]; } static int -nvd0_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) +gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); - const u32 loff = nvd0_sor_loff(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + const u32 loff = gf110_sor_loff(outp); nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); return 0; } int -nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) +gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); - const u32 soff = nvd0_sor_soff(outp); - const u32 loff = nvd0_sor_loff(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + const u32 soff = gf110_sor_soff(outp); + const u32 loff = gf110_sor_loff(outp); u32 dpctrl = 0x00000000; u32 clksor = 0x00000000; @@ -80,12 +72,13 @@ nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) } static int -nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) +gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp, + int ln, int vs, int pe, int pc) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); - struct nouveau_bios *bios = nouveau_bios(priv); - const u32 shift = nvd0_sor_dp_lane_map(priv, ln); - const u32 loff = nvd0_sor_loff(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nvkm_bios *bios = nvkm_bios(priv); + const u32 shift = gf110_sor_dp_lane_map(priv, ln); + const u32 loff = gf110_sor_loff(outp); u32 addr, data[4]; u8 ver, hdr, cnt, len; struct nvbios_dpout info; @@ -93,12 +86,12 @@ nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) addr = nvbios_dpout_match(bios, outp->base.info.hasht, outp->base.info.hashm, - &ver, &hdr, &cnt, &len, &info); + &ver, &hdr, &cnt, &len, &info); if (!addr) return -ENODEV; addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe, - &ver, &hdr, &cnt, &len, &ocfg); + &ver, &hdr, &cnt, &len, &ocfg); if (!addr) return -EINVAL; @@ -116,16 +109,16 @@ nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) } struct nvkm_output_dp_impl -nvd0_sor_dp_impl = { +gf110_sor_dp_impl = { .base.base.handle = DCB_OUTPUT_DP, - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_output_dp_ctor, .dtor = _nvkm_output_dp_dtor, .init = _nvkm_output_dp_init, .fini = _nvkm_output_dp_fini, }, - .pattern = nvd0_sor_dp_pattern, - .lnk_pwr = nv94_sor_dp_lnk_pwr, - .lnk_ctl = nvd0_sor_dp_lnk_ctl, - .drv_ctl = nvd0_sor_dp_drv_ctl, + .pattern = gf110_sor_dp_pattern, + .lnk_pwr = g94_sor_dp_lnk_pwr, + .lnk_ctl = gf110_sor_dp_lnk_ctl, + .drv_ctl = gf110_sor_dp_drv_ctl, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c index 0b4fad39e9a6..1e40dfe11319 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c @@ -21,17 +21,11 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "outpdp.h" -#include <core/os.h> - -#include <subdev/bios.h> -#include <subdev/bios/dcb.h> -#include <subdev/bios/dp.h> -#include <subdev/bios/init.h> #include <subdev/timer.h> -#include "nv50.h" - static inline u32 gm204_sor_soff(struct nvkm_output_dp *outp) { @@ -47,7 +41,7 @@ gm204_sor_loff(struct nvkm_output_dp *outp) void gm204_sor_magic(struct nvkm_output *outp) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); const u32 soff = outp->or * 0x100; const u32 data = outp->or + 1; if (outp->info.sorconf.link & 1) @@ -65,7 +59,7 @@ gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) static int gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); const u32 soff = gm204_sor_soff(outp); const u32 data = 0x01010101 * pattern; if (outp->base.info.sorconf.link & 1) @@ -78,7 +72,7 @@ gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) static int gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); const u32 soff = gm204_sor_soff(outp); const u32 loff = gm204_sor_loff(outp); u32 mask = 0, i; @@ -93,10 +87,11 @@ gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) } static int -gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) +gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, + int ln, int vs, int pe, int pc) { - struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); - struct nouveau_bios *bios = nouveau_bios(priv); + struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nvkm_bios *bios = nvkm_bios(priv); const u32 shift = gm204_sor_dp_lane_map(priv, ln); const u32 loff = gm204_sor_loff(outp); u32 addr, data[4]; @@ -106,12 +101,12 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc addr = nvbios_dpout_match(bios, outp->base.info.hasht, outp->base.info.hashm, - &ver, &hdr, &cnt, &len, &info); + &ver, &hdr, &cnt, &len, &info); if (!addr) return -ENODEV; addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe, - &ver, &hdr, &cnt, &len, &ocfg); + &ver, &hdr, &cnt, &len, &ocfg); if (!addr) return -EINVAL; @@ -131,7 +126,7 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc struct nvkm_output_dp_impl gm204_sor_dp_impl = { .base.base.handle = DCB_OUTPUT_DP, - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_output_dp_ctor, .dtor = _nvkm_output_dp_dtor, .init = _nvkm_output_dp_init, @@ -139,6 +134,6 @@ gm204_sor_dp_impl = { }, .pattern = gm204_sor_dp_pattern, .lnk_pwr = gm204_sor_dp_lnk_pwr, - .lnk_ctl = nvd0_sor_dp_lnk_ctl, + .lnk_ctl = gf110_sor_dp_lnk_ctl, .drv_ctl = gm204_sor_dp_drv_ctl, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c index ddf1760c4400..b229a311c78c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c @@ -21,16 +21,14 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "outp.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <subdev/bios.h> -#include <subdev/bios/dcb.h> #include <subdev/timer.h> -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> int nv50_sor_power(NV50_DISP_MTHD_V1) diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/vga.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c index 8836c3cb99c3..c4622c7388d0 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/vga.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c @@ -21,15 +21,14 @@ * * Authors: Ben Skeggs */ +#include <subdev/vga.h> -#include <core/subdev.h> #include <core/device.h> -#include <subdev/vga.h> u8 nv_rdport(void *obj, int head, u16 port) { - struct nouveau_device *device = nv_device(obj); + struct nvkm_device *device = nv_device(obj); if (device->card_type >= NV_50) return nv_rd08(obj, 0x601000 + port); @@ -54,7 +53,7 @@ nv_rdport(void *obj, int head, u16 port) void nv_wrport(void *obj, int head, u16 port, u8 data) { - struct nouveau_device *device = nv_device(obj); + struct nvkm_device *device = nv_device(obj); if (device->card_type >= NV_50) nv_wr08(obj, 0x601000 + port, data); @@ -138,7 +137,7 @@ nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value) bool nv_lockvgac(void *obj, bool lock) { - struct nouveau_device *dev = nv_device(obj); + struct nvkm_device *dev = nv_device(obj); bool locked = !nv_rdvgac(obj, 0, 0x1f); u8 data = lock ? 0x99 : 0x57; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild new file mode 100644 index 000000000000..7529632dbedb --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild @@ -0,0 +1,5 @@ +nvkm-y += nvkm/engine/dmaobj/base.o +nvkm-y += nvkm/engine/dmaobj/nv04.o +nvkm-y += nvkm/engine/dmaobj/nv50.o +nvkm-y += nvkm/engine/dmaobj/gf100.o +nvkm-y += nvkm/engine/dmaobj/gf110.o diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c index e1500f77a56a..a2b60d86baba 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ +#include "priv.h" -#include <core/object.h> #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - +#include <core/device.h> #include <subdev/fb.h> #include <subdev/instmem.h> -#include "priv.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static int -nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent, - struct nouveau_gpuobj **pgpuobj) +nvkm_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent, + struct nvkm_gpuobj **pgpuobj) { const struct nvkm_dmaeng_impl *impl = (void *) nv_oclass(nv_object(dmaobj)->engine); @@ -47,7 +46,7 @@ nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent, } ret = impl->bind(dmaobj, parent, pgpuobj); if (ret == 0) - nouveau_object_ref(NULL, &parent); + nvkm_object_ref(NULL, &parent); return ret; } @@ -55,24 +54,24 @@ nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent, } int -nvkm_dmaobj_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void **pdata, u32 *psize, +nvkm_dmaobj_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void **pdata, u32 *psize, int length, void **pobject) { union { struct nv_dma_v0 v0; } *args = *pdata; - struct nouveau_instmem *instmem = nouveau_instmem(parent); - struct nouveau_client *client = nouveau_client(parent); - struct nouveau_device *device = nv_device(parent); - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_dmaobj *dmaobj; + struct nvkm_instmem *instmem = nvkm_instmem(parent); + struct nvkm_client *client = nvkm_client(parent); + struct nvkm_device *device = nv_device(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_dmaobj *dmaobj; void *data = *pdata; u32 size = *psize; int ret; - ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject); + ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); dmaobj = *pobject; if (ret) return ret; @@ -145,16 +144,16 @@ nvkm_dmaobj_create_(struct nouveau_object *parent, } int -_nvkm_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +_nvkm_dmaeng_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { const struct nvkm_dmaeng_impl *impl = (void *)oclass; - struct nouveau_dmaeng *dmaeng; + struct nvkm_dmaeng *dmaeng; int ret; - ret = nouveau_engine_create(parent, engine, oclass, true, "DMAOBJ", - "dmaobj", &dmaeng); + ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ", + "dmaobj", &dmaeng); *pobject = nv_object(dmaeng); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c index 88ec33b20048..f880e5167e45 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c @@ -21,29 +21,26 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <core/client.h> -#include <core/device.h> #include <core/gpuobj.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - #include <subdev/fb.h> -#include "priv.h" +#include <nvif/class.h> +#include <nvif/unpack.h> -struct nvc0_dmaobj_priv { - struct nouveau_dmaobj base; +struct gf100_dmaobj_priv { + struct nvkm_dmaobj base; u32 flags0; u32 flags5; }; static int -nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj, - struct nouveau_object *parent, - struct nouveau_gpuobj **pgpuobj) +gf100_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent, + struct nvkm_gpuobj **pgpuobj) { - struct nvc0_dmaobj_priv *priv = (void *)dmaobj; + struct gf100_dmaobj_priv *priv = (void *)dmaobj; int ret; if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { @@ -58,7 +55,7 @@ nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj, } else return 0; - ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); + ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); if (ret == 0) { nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj)); nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit)); @@ -73,15 +70,15 @@ nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj, } static int -nvc0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_dmaeng *dmaeng = (void *)engine; + struct nvkm_dmaeng *dmaeng = (void *)engine; union { struct gf100_dma_v0 v0; } *args; - struct nvc0_dmaobj_priv *priv; + struct gf100_dmaobj_priv *priv; u32 kind, user, unkn; int ret; @@ -149,31 +146,31 @@ nvc0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject); } -static struct nouveau_ofuncs -nvc0_dmaobj_ofuncs = { - .ctor = nvc0_dmaobj_ctor, +static struct nvkm_ofuncs +gf100_dmaobj_ofuncs = { + .ctor = gf100_dmaobj_ctor, .dtor = _nvkm_dmaobj_dtor, .init = _nvkm_dmaobj_init, .fini = _nvkm_dmaobj_fini, }; -static struct nouveau_oclass -nvc0_dmaeng_sclass[] = { - { NV_DMA_FROM_MEMORY, &nvc0_dmaobj_ofuncs }, - { NV_DMA_TO_MEMORY, &nvc0_dmaobj_ofuncs }, - { NV_DMA_IN_MEMORY, &nvc0_dmaobj_ofuncs }, +static struct nvkm_oclass +gf100_dmaeng_sclass[] = { + { NV_DMA_FROM_MEMORY, &gf100_dmaobj_ofuncs }, + { NV_DMA_TO_MEMORY, &gf100_dmaobj_ofuncs }, + { NV_DMA_IN_MEMORY, &gf100_dmaobj_ofuncs }, {} }; -struct nouveau_oclass * -nvc0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { +struct nvkm_oclass * +gf100_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { .base.handle = NV_ENGINE(DMAOBJ, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_dmaeng_ctor, .dtor = _nvkm_dmaeng_dtor, .init = _nvkm_dmaeng_init, .fini = _nvkm_dmaeng_fini, }, - .sclass = nvc0_dmaeng_sclass, - .bind = nvc0_dmaobj_bind, + .sclass = gf100_dmaeng_sclass, + .bind = gf100_dmaobj_bind, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c index 19f5f6522962..bf8f0f20976c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c @@ -21,28 +21,25 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <core/client.h> -#include <core/device.h> #include <core/gpuobj.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - #include <subdev/fb.h> -#include "priv.h" +#include <nvif/class.h> +#include <nvif/unpack.h> -struct nvd0_dmaobj_priv { - struct nouveau_dmaobj base; +struct gf110_dmaobj_priv { + struct nvkm_dmaobj base; u32 flags0; }; static int -nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj, - struct nouveau_object *parent, - struct nouveau_gpuobj **pgpuobj) +gf110_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent, + struct nvkm_gpuobj **pgpuobj) { - struct nvd0_dmaobj_priv *priv = (void *)dmaobj; + struct gf110_dmaobj_priv *priv = (void *)dmaobj; int ret; if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { @@ -64,7 +61,7 @@ nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj, } else return 0; - ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); + ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); if (ret == 0) { nv_wo32(*pgpuobj, 0x00, priv->flags0); nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8); @@ -78,15 +75,15 @@ nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj, } static int -nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_dmaeng *dmaeng = (void *)engine; + struct nvkm_dmaeng *dmaeng = (void *)engine; union { struct gf110_dma_v0 v0; } *args; - struct nvd0_dmaobj_priv *priv; + struct gf110_dmaobj_priv *priv; u32 kind, page; int ret; @@ -138,31 +135,31 @@ nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject); } -static struct nouveau_ofuncs -nvd0_dmaobj_ofuncs = { - .ctor = nvd0_dmaobj_ctor, +static struct nvkm_ofuncs +gf110_dmaobj_ofuncs = { + .ctor = gf110_dmaobj_ctor, .dtor = _nvkm_dmaobj_dtor, .init = _nvkm_dmaobj_init, .fini = _nvkm_dmaobj_fini, }; -static struct nouveau_oclass -nvd0_dmaeng_sclass[] = { - { NV_DMA_FROM_MEMORY, &nvd0_dmaobj_ofuncs }, - { NV_DMA_TO_MEMORY, &nvd0_dmaobj_ofuncs }, - { NV_DMA_IN_MEMORY, &nvd0_dmaobj_ofuncs }, +static struct nvkm_oclass +gf110_dmaeng_sclass[] = { + { NV_DMA_FROM_MEMORY, &gf110_dmaobj_ofuncs }, + { NV_DMA_TO_MEMORY, &gf110_dmaobj_ofuncs }, + { NV_DMA_IN_MEMORY, &gf110_dmaobj_ofuncs }, {} }; -struct nouveau_oclass * -nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { +struct nvkm_oclass * +gf110_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { .base.handle = NV_ENGINE(DMAOBJ, 0xd0), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_dmaeng_ctor, .dtor = _nvkm_dmaeng_dtor, .init = _nvkm_dmaeng_init, .fini = _nvkm_dmaeng_fini, }, - .sclass = nvd0_dmaeng_sclass, - .bind = nvd0_dmaobj_bind, + .sclass = gf110_dmaeng_sclass, + .bind = gf110_dmaobj_bind, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c index 20c9dbfe3b2e..b4379c2a2fb5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c @@ -21,29 +21,27 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <core/gpuobj.h> -#include <nvif/class.h> - #include <subdev/fb.h> -#include <subdev/vm/nv04.h> +#include <subdev/mmu/nv04.h> -#include "priv.h" +#include <nvif/class.h> struct nv04_dmaobj_priv { - struct nouveau_dmaobj base; + struct nvkm_dmaobj base; bool clone; u32 flags0; u32 flags2; }; static int -nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj, - struct nouveau_object *parent, - struct nouveau_gpuobj **pgpuobj) +nv04_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent, + struct nvkm_gpuobj **pgpuobj) { struct nv04_dmaobj_priv *priv = (void *)dmaobj; - struct nouveau_gpuobj *gpuobj; + struct nvkm_gpuobj *gpuobj; u64 offset = priv->base.start & 0xfffff000; u64 adjust = priv->base.start & 0x00000fff; u32 length = priv->base.limit - priv->base.start; @@ -62,15 +60,15 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj, } if (priv->clone) { - struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaobj); - struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0]; + struct nv04_mmu_priv *mmu = nv04_mmu(dmaobj); + struct nvkm_gpuobj *pgt = mmu->vm->pgt[0].obj[0]; if (!dmaobj->start) - return nouveau_gpuobj_dup(parent, pgt, pgpuobj); + return nvkm_gpuobj_dup(parent, pgt, pgpuobj); offset = nv_ro32(pgt, 8 + (offset >> 10)); offset &= 0xfffff000; } - ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj); + ret = nvkm_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj); *pgpuobj = gpuobj; if (ret == 0) { nv_wo32(*pgpuobj, 0x00, priv->flags0 | (adjust << 20)); @@ -83,12 +81,12 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj, } static int -nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_dmaeng *dmaeng = (void *)engine; - struct nv04_vmmgr_priv *vmm = nv04_vmmgr(engine); + struct nvkm_dmaeng *dmaeng = (void *)engine; + struct nv04_mmu_priv *mmu = nv04_mmu(engine); struct nv04_dmaobj_priv *priv; int ret; @@ -98,7 +96,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; if (priv->base.target == NV_MEM_TARGET_VM) { - if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) + if (nv_object(mmu)->oclass == &nv04_mmu_oclass) priv->clone = true; priv->base.target = NV_MEM_TARGET_PCI; priv->base.access = NV_MEM_ACCESS_RW; @@ -135,7 +133,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject); } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv04_dmaobj_ofuncs = { .ctor = nv04_dmaobj_ctor, .dtor = _nvkm_dmaobj_dtor, @@ -143,7 +141,7 @@ nv04_dmaobj_ofuncs = { .fini = _nvkm_dmaobj_fini, }; -static struct nouveau_oclass +static struct nvkm_oclass nv04_dmaeng_sclass[] = { { NV_DMA_FROM_MEMORY, &nv04_dmaobj_ofuncs }, { NV_DMA_TO_MEMORY, &nv04_dmaobj_ofuncs }, @@ -151,10 +149,10 @@ nv04_dmaeng_sclass[] = { {} }; -struct nouveau_oclass * +struct nvkm_oclass * nv04_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { .base.handle = NV_ENGINE(DMAOBJ, 0x04), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_dmaeng_ctor, .dtor = _nvkm_dmaeng_dtor, .init = _nvkm_dmaeng_init, diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c index a740ddba2ee2..4d3c828fe0e6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c @@ -21,26 +21,24 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <core/client.h> #include <core/gpuobj.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - #include <subdev/fb.h> -#include "priv.h" +#include <nvif/class.h> +#include <nvif/unpack.h> struct nv50_dmaobj_priv { - struct nouveau_dmaobj base; + struct nvkm_dmaobj base; u32 flags0; u32 flags5; }; static int -nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj, - struct nouveau_object *parent, - struct nouveau_gpuobj **pgpuobj) +nv50_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent, + struct nvkm_gpuobj **pgpuobj) { struct nv50_dmaobj_priv *priv = (void *)dmaobj; int ret; @@ -69,7 +67,7 @@ nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj, } } - ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); + ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); if (ret == 0) { nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj)); nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit)); @@ -84,11 +82,11 @@ nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj, } static int -nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_dmaeng *dmaeng = (void *)engine; + struct nvkm_dmaeng *dmaeng = (void *)engine; union { struct nv50_dma_v0 v0; } *args; @@ -167,7 +165,7 @@ nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject); } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv50_dmaobj_ofuncs = { .ctor = nv50_dmaobj_ctor, .dtor = _nvkm_dmaobj_dtor, @@ -175,7 +173,7 @@ nv50_dmaobj_ofuncs = { .fini = _nvkm_dmaobj_fini, }; -static struct nouveau_oclass +static struct nvkm_oclass nv50_dmaeng_sclass[] = { { NV_DMA_FROM_MEMORY, &nv50_dmaobj_ofuncs }, { NV_DMA_TO_MEMORY, &nv50_dmaobj_ofuncs }, @@ -183,10 +181,10 @@ nv50_dmaeng_sclass[] = { {} }; -struct nouveau_oclass * +struct nvkm_oclass * nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { .base.handle = NV_ENGINE(DMAOBJ, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_dmaeng_ctor, .dtor = _nvkm_dmaeng_dtor, .init = _nvkm_dmaeng_init, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h new file mode 100644 index 000000000000..44ae8a0ca65c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h @@ -0,0 +1,28 @@ +#ifndef __NVKM_DMAOBJ_PRIV_H__ +#define __NVKM_DMAOBJ_PRIV_H__ +#include <engine/dmaobj.h> + +#define nvkm_dmaobj_create(p,e,c,pa,sa,d) \ + nvkm_dmaobj_create_((p), (e), (c), (pa), (sa), sizeof(**d), (void **)d) + +int nvkm_dmaobj_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void **, u32 *, + int, void **); +#define _nvkm_dmaobj_dtor nvkm_object_destroy +#define _nvkm_dmaobj_init nvkm_object_init +#define _nvkm_dmaobj_fini nvkm_object_fini + +int _nvkm_dmaeng_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +#define _nvkm_dmaeng_dtor _nvkm_engine_dtor +#define _nvkm_dmaeng_init _nvkm_engine_init +#define _nvkm_dmaeng_fini _nvkm_engine_fini + +struct nvkm_dmaeng_impl { + struct nvkm_oclass base; + struct nvkm_oclass *sclass; + int (*bind)(struct nvkm_dmaobj *, struct nvkm_object *, + struct nvkm_gpuobj **); +}; +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index 2914646c8709..30958c19e61d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c @@ -19,14 +19,15 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ - #include <engine/falcon.h> + +#include <core/device.h> #include <subdev/timer.h> void -nouveau_falcon_intr(struct nouveau_subdev *subdev) +nvkm_falcon_intr(struct nvkm_subdev *subdev) { - struct nouveau_falcon *falcon = (void *)subdev; + struct nvkm_falcon *falcon = (void *)subdev; u32 dispatch = nv_ro32(falcon, 0x01c); u32 intr = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); @@ -43,16 +44,16 @@ nouveau_falcon_intr(struct nouveau_subdev *subdev) } u32 -_nouveau_falcon_rd32(struct nouveau_object *object, u64 addr) +_nvkm_falcon_rd32(struct nvkm_object *object, u64 addr) { - struct nouveau_falcon *falcon = (void *)object; + struct nvkm_falcon *falcon = (void *)object; return nv_rd32(falcon, falcon->addr + addr); } void -_nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data) +_nvkm_falcon_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nouveau_falcon *falcon = (void *)object; + struct nvkm_falcon *falcon = (void *)object; nv_wr32(falcon, falcon->addr + addr, data); } @@ -67,17 +68,17 @@ vmemdup(const void *src, size_t len) } int -_nouveau_falcon_init(struct nouveau_object *object) +_nvkm_falcon_init(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); - struct nouveau_falcon *falcon = (void *)object; + struct nvkm_device *device = nv_device(object); + struct nvkm_falcon *falcon = (void *)object; const struct firmware *fw; char name[32] = "internal"; int ret, i; u32 caps; /* enable engine, and determine its capabilities */ - ret = nouveau_engine_init(&falcon->base); + ret = nvkm_engine_init(&falcon->base); if (ret) return ret; @@ -171,9 +172,8 @@ _nouveau_falcon_init(struct nouveau_object *object) /* ensure any "self-bootstrapping" firmware image is in vram */ if (!falcon->data.data && !falcon->core) { - ret = nouveau_gpuobj_new(object->parent, NULL, - falcon->code.size, 256, 0, - &falcon->core); + ret = nvkm_gpuobj_new(object->parent, NULL, falcon->code.size, + 256, 0, &falcon->core); if (ret) { nv_error(falcon, "core allocation failed, %d\n", ret); return ret; @@ -238,12 +238,12 @@ _nouveau_falcon_init(struct nouveau_object *object) } int -_nouveau_falcon_fini(struct nouveau_object *object, bool suspend) +_nvkm_falcon_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_falcon *falcon = (void *)object; + struct nvkm_falcon *falcon = (void *)object; if (!suspend) { - nouveau_gpuobj_ref(NULL, &falcon->core); + nvkm_gpuobj_ref(NULL, &falcon->core); if (falcon->external) { vfree(falcon->data.data); vfree(falcon->code.data); @@ -254,21 +254,20 @@ _nouveau_falcon_fini(struct nouveau_object *object, bool suspend) nv_mo32(falcon, 0x048, 0x00000003, 0x00000000); nv_wo32(falcon, 0x014, 0xffffffff); - return nouveau_engine_fini(&falcon->base, suspend); + return nvkm_engine_fini(&falcon->base, suspend); } int -nouveau_falcon_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 addr, bool enable, - const char *iname, const char *fname, - int length, void **pobject) +nvkm_falcon_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 addr, bool enable, + const char *iname, const char *fname, + int length, void **pobject) { - struct nouveau_falcon *falcon; + struct nvkm_falcon *falcon; int ret; - ret = nouveau_engine_create_(parent, engine, oclass, enable, iname, - fname, length, pobject); + ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, + fname, length, pobject); falcon = *pobject; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild new file mode 100644 index 000000000000..c5a2d8718c5b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild @@ -0,0 +1,11 @@ +nvkm-y += nvkm/engine/fifo/base.o +nvkm-y += nvkm/engine/fifo/nv04.o +nvkm-y += nvkm/engine/fifo/nv10.o +nvkm-y += nvkm/engine/fifo/nv17.o +nvkm-y += nvkm/engine/fifo/nv40.o +nvkm-y += nvkm/engine/fifo/nv50.o +nvkm-y += nvkm/engine/fifo/g84.o +nvkm-y += nvkm/engine/fifo/gf100.o +nvkm-y += nvkm/engine/fifo/gk104.o +nvkm-y += nvkm/engine/fifo/gk20a.o +nvkm-y += nvkm/engine/fifo/gk208.o diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index ac8375cf4eef..fa223f88d25e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -21,21 +21,21 @@ * * Authors: Ben Skeggs */ +#include <engine/fifo.h> #include <core/client.h> -#include <core/object.h> +#include <core/device.h> #include <core/handle.h> -#include <core/event.h> -#include <nvif/unpack.h> +#include <core/notify.h> +#include <engine/dmaobj.h> + #include <nvif/class.h> #include <nvif/event.h> - -#include <engine/dmaobj.h> -#include <engine/fifo.h> +#include <nvif/unpack.h> static int -nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_fifo_event_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { if (size == 0) { notify->size = 0; @@ -47,33 +47,33 @@ nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size, } static const struct nvkm_event_func -nouveau_fifo_event_func = { - .ctor = nouveau_fifo_event_ctor, +nvkm_fifo_event_func = { + .ctor = nvkm_fifo_event_ctor, }; int -nouveau_fifo_channel_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int bar, u32 addr, u32 size, u32 pushbuf, - u64 engmask, int len, void **ptr) +nvkm_fifo_channel_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, + int bar, u32 addr, u32 size, u32 pushbuf, + u64 engmask, int len, void **ptr) { - struct nouveau_device *device = nv_device(engine); - struct nouveau_fifo *priv = (void *)engine; - struct nouveau_fifo_chan *chan; - struct nouveau_dmaeng *dmaeng; + struct nvkm_device *device = nv_device(engine); + struct nvkm_fifo *priv = (void *)engine; + struct nvkm_fifo_chan *chan; + struct nvkm_dmaeng *dmaeng; unsigned long flags; int ret; /* create base object class */ - ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL, - engmask, len, ptr); + ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, + engmask, len, ptr); chan = *ptr; if (ret) return ret; /* validate dma object representing push buffer */ - chan->pushdma = (void *)nouveau_handle_ref(parent, pushbuf); + chan->pushdma = (void *)nvkm_handle_ref(parent, pushbuf); if (!chan->pushdma) return -ENOENT; @@ -113,9 +113,9 @@ nouveau_fifo_channel_create_(struct nouveau_object *parent, } void -nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan) +nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *chan) { - struct nouveau_fifo *priv = (void *)nv_object(chan)->engine; + struct nvkm_fifo *priv = (void *)nv_object(chan)->engine; unsigned long flags; if (chan->user) @@ -125,31 +125,31 @@ nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan) priv->channel[chan->chid] = NULL; spin_unlock_irqrestore(&priv->lock, flags); - nouveau_gpuobj_ref(NULL, &chan->pushgpu); - nouveau_object_ref(NULL, (struct nouveau_object **)&chan->pushdma); - nouveau_namedb_destroy(&chan->base); + nvkm_gpuobj_ref(NULL, &chan->pushgpu); + nvkm_object_ref(NULL, (struct nvkm_object **)&chan->pushdma); + nvkm_namedb_destroy(&chan->namedb); } void -_nouveau_fifo_channel_dtor(struct nouveau_object *object) +_nvkm_fifo_channel_dtor(struct nvkm_object *object) { - struct nouveau_fifo_chan *chan = (void *)object; - nouveau_fifo_channel_destroy(chan); + struct nvkm_fifo_chan *chan = (void *)object; + nvkm_fifo_channel_destroy(chan); } int -_nouveau_fifo_channel_map(struct nouveau_object *object, u64 *addr, u32 *size) +_nvkm_fifo_channel_map(struct nvkm_object *object, u64 *addr, u32 *size) { - struct nouveau_fifo_chan *chan = (void *)object; + struct nvkm_fifo_chan *chan = (void *)object; *addr = chan->addr; *size = chan->size; return 0; } u32 -_nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr) +_nvkm_fifo_channel_rd32(struct nvkm_object *object, u64 addr) { - struct nouveau_fifo_chan *chan = (void *)object; + struct nvkm_fifo_chan *chan = (void *)object; if (unlikely(!chan->user)) { chan->user = ioremap(chan->addr, chan->size); if (WARN_ON_ONCE(chan->user == NULL)) @@ -159,9 +159,9 @@ _nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr) } void -_nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data) +_nvkm_fifo_channel_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nouveau_fifo_chan *chan = (void *)object; + struct nvkm_fifo_chan *chan = (void *)object; if (unlikely(!chan->user)) { chan->user = ioremap(chan->addr, chan->size); if (WARN_ON_ONCE(chan->user == NULL)) @@ -171,8 +171,8 @@ _nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data) } int -nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { union { struct nvif_notify_uevent_req none; @@ -189,7 +189,7 @@ nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size, } void -nouveau_fifo_uevent(struct nouveau_fifo *fifo) +nvkm_fifo_uevent(struct nvkm_fifo *fifo) { struct nvif_notify_uevent_rep rep = { }; @@ -197,10 +197,10 @@ nouveau_fifo_uevent(struct nouveau_fifo *fifo) } int -_nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type, - struct nvkm_event **event) +_nvkm_fifo_channel_ntfy(struct nvkm_object *object, u32 type, + struct nvkm_event **event) { - struct nouveau_fifo *fifo = (void *)object->engine; + struct nvkm_fifo *fifo = (void *)object->engine; switch (type) { case G82_CHANNEL_DMA_V0_NTFY_UEVENT: if (nv_mclass(object) >= G82_CHANNEL_DMA) { @@ -215,14 +215,14 @@ _nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type, } static int -nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object) +nvkm_fifo_chid(struct nvkm_fifo *priv, struct nvkm_object *object) { int engidx = nv_hclass(priv) & 0xff; while (object && object->parent) { if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) && (nv_hclass(object->parent) & 0xff) == engidx) - return nouveau_fifo_chan(object)->chid; + return nvkm_fifo_chan(object)->chid; object = object->parent; } @@ -230,9 +230,9 @@ nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object) } const char * -nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid) +nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid) { - struct nouveau_fifo_chan *chan = NULL; + struct nvkm_fifo_chan *chan = NULL; unsigned long flags; spin_lock_irqsave(&fifo->lock, flags); @@ -240,29 +240,28 @@ nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid) chan = (void *)fifo->channel[chid]; spin_unlock_irqrestore(&fifo->lock, flags); - return nouveau_client_name(chan); + return nvkm_client_name(chan); } void -nouveau_fifo_destroy(struct nouveau_fifo *priv) +nvkm_fifo_destroy(struct nvkm_fifo *priv) { kfree(priv->channel); nvkm_event_fini(&priv->uevent); nvkm_event_fini(&priv->cevent); - nouveau_engine_destroy(&priv->base); + nvkm_engine_destroy(&priv->base); } int -nouveau_fifo_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int min, int max, int length, void **pobject) +nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, + int min, int max, int length, void **pobject) { - struct nouveau_fifo *priv; + struct nvkm_fifo *priv; int ret; - ret = nouveau_engine_create_(parent, engine, oclass, true, "PFIFO", - "fifo", length, pobject); + ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO", + "fifo", length, pobject); priv = *pobject; if (ret) return ret; @@ -273,11 +272,11 @@ nouveau_fifo_create_(struct nouveau_object *parent, if (!priv->channel) return -ENOMEM; - ret = nvkm_event_init(&nouveau_fifo_event_func, 1, 1, &priv->cevent); + ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &priv->cevent); if (ret) return ret; - priv->chid = nouveau_fifo_chid; + priv->chid = nvkm_fifo_chid; spin_lock_init(&priv->lock); return 0; } diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c index 1f42996b354a..a04920b3cf84 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c @@ -21,48 +21,45 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "nv04.h" -#include <core/os.h> #include <core/client.h> #include <core/engctx.h> #include <core/ramht.h> -#include <core/event.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <subdev/timer.h> #include <subdev/bar.h> +#include <subdev/mmu.h> +#include <subdev/timer.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> - -#include "nv04.h" -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> /******************************************************************************* * FIFO channel objects ******************************************************************************/ static int -nv84_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent->parent; - struct nouveau_gpuobj *ectx = (void *)object; + struct nvkm_gpuobj *ectx = (void *)object; u64 limit = ectx->addr + ectx->size - 1; u64 start = ectx->addr; u32 addr; switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0020; break; - case NVDEV_ENGINE_VP : addr = 0x0040; break; - case NVDEV_ENGINE_PPP : - case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - case NVDEV_ENGINE_BSP : addr = 0x0080; break; - case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break; - case NVDEV_ENGINE_COPY0: addr = 0x00c0; break; + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : addr = 0x0020; break; + case NVDEV_ENGINE_VP : + case NVDEV_ENGINE_MSPDEC: addr = 0x0040; break; + case NVDEV_ENGINE_MSPPP : + case NVDEV_ENGINE_MPEG : addr = 0x0060; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : addr = 0x0080; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : addr = 0x00a0; break; + case NVDEV_ENGINE_CE0 : addr = 0x00c0; break; default: return -EINVAL; } @@ -80,10 +77,10 @@ nv84_fifo_context_attach(struct nouveau_object *parent, } static int -nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *object) +g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_priv *priv = (void *)parent->engine; struct nv50_fifo_base *base = (void *)parent->parent; struct nv50_fifo_chan *chan = (void *)parent; @@ -91,14 +88,17 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, bool done; switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; - case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break; - case NVDEV_ENGINE_PPP : - case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; - case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break; - case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break; - case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break; + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; + case NVDEV_ENGINE_VP : + case NVDEV_ENGINE_MSPDEC: engn = 3; addr = 0x0040; break; + case NVDEV_ENGINE_MSPPP : + case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break; + case NVDEV_ENGINE_CE0 : engn = 2; addr = 0x00c0; break; default: return -EINVAL; } @@ -109,7 +109,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, nv_wr32(priv, 0x002520, save); if (!done) { nv_error(priv, "channel %d [%s] unload timeout\n", - chan->base.chid, nouveau_client_name(chan)); + chan->base.chid, nvkm_client_name(chan)); if (suspend) return -EBUSY; } @@ -125,8 +125,8 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nv84_fifo_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 handle) +g84_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) { struct nv50_fifo_chan *chan = (void *)parent; u32 context; @@ -141,30 +141,32 @@ nv84_fifo_object_attach(struct nouveau_object *parent, case NVDEV_ENGINE_SW : context |= 0x00000000; break; case NVDEV_ENGINE_GR : context |= 0x00100000; break; case NVDEV_ENGINE_MPEG : - case NVDEV_ENGINE_PPP : context |= 0x00200000; break; + case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break; case NVDEV_ENGINE_ME : - case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break; - case NVDEV_ENGINE_VP : context |= 0x00400000; break; - case NVDEV_ENGINE_CRYPT : + case NVDEV_ENGINE_CE0 : context |= 0x00300000; break; + case NVDEV_ENGINE_VP : + case NVDEV_ENGINE_MSPDEC: context |= 0x00400000; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : case NVDEV_ENGINE_VIC : context |= 0x00500000; break; - case NVDEV_ENGINE_BSP : context |= 0x00600000; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break; default: return -EINVAL; } - return nouveau_ramht_insert(chan->ramht, 0, handle, context); + return nvkm_ramht_insert(chan->ramht, 0, handle, context); } static int -nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; int ret; @@ -177,33 +179,36 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_ME) | - (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CRYPT) | - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_PPP) | - (1ULL << NVDEV_ENGINE_COPY0) | - (1ULL << NVDEV_ENGINE_VIC), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG) | + (1ULL << NVDEV_ENGINE_ME) | + (1ULL << NVDEV_ENGINE_VP) | + (1ULL << NVDEV_ENGINE_CIPHER) | + (1ULL << NVDEV_ENGINE_SEC) | + (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_VIC), &chan); *pobject = nv_object(chan); if (ret) return ret; args->v0.chid = chan->base.chid; - ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, - &chan->ramht); + ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, + &chan->ramht); if (ret) return ret; - nv_parent(chan)->context_attach = nv84_fifo_context_attach; - nv_parent(chan)->context_detach = nv84_fifo_context_detach; - nv_parent(chan)->object_attach = nv84_fifo_object_attach; + nv_parent(chan)->context_attach = g84_fifo_context_attach; + nv_parent(chan)->context_detach = g84_fifo_context_detach; + nv_parent(chan)->object_attach = g84_fifo_object_attach; nv_parent(chan)->object_detach = nv50_fifo_object_detach; nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); @@ -219,7 +224,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, nv_wo32(base->ramfc, 0x7c, 0x30000001); nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->base.node->offset >> 4)); + (chan->ramht->gpuobj.node->offset >> 4)); nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10); nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); bar->flush(bar); @@ -227,15 +232,14 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, } static int -nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; u64 ioffset, ilength; @@ -250,33 +254,36 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_ME) | - (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CRYPT) | - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_PPP) | - (1ULL << NVDEV_ENGINE_COPY0) | - (1ULL << NVDEV_ENGINE_VIC), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG) | + (1ULL << NVDEV_ENGINE_ME) | + (1ULL << NVDEV_ENGINE_VP) | + (1ULL << NVDEV_ENGINE_CIPHER) | + (1ULL << NVDEV_ENGINE_SEC) | + (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_VIC), &chan); *pobject = nv_object(chan); if (ret) return ret; args->v0.chid = chan->base.chid; - ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, - &chan->ramht); + ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, + &chan->ramht); if (ret) return ret; - nv_parent(chan)->context_attach = nv84_fifo_context_attach; - nv_parent(chan)->context_detach = nv84_fifo_context_detach; - nv_parent(chan)->object_attach = nv84_fifo_object_attach; + nv_parent(chan)->context_attach = g84_fifo_context_attach; + nv_parent(chan)->context_detach = g84_fifo_context_detach; + nv_parent(chan)->object_attach = g84_fifo_object_attach; nv_parent(chan)->object_detach = nv50_fifo_object_detach; ioffset = args->v0.ioffset; @@ -292,7 +299,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, nv_wo32(base->ramfc, 0x7c, 0x30000001); nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->base.node->offset >> 4)); + (chan->ramht->gpuobj.node->offset >> 4)); nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10); nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); bar->flush(bar); @@ -300,16 +307,16 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, } static int -nv84_fifo_chan_init(struct nouveau_object *object) +g84_fifo_chan_init(struct nvkm_object *object) { struct nv50_fifo_priv *priv = (void *)object->engine; struct nv50_fifo_base *base = (void *)object->parent; struct nv50_fifo_chan *chan = (void *)object; - struct nouveau_gpuobj *ramfc = base->ramfc; + struct nvkm_gpuobj *ramfc = base->ramfc; u32 chid = chan->base.chid; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -318,34 +325,34 @@ nv84_fifo_chan_init(struct nouveau_object *object) return 0; } -static struct nouveau_ofuncs -nv84_fifo_ofuncs_dma = { - .ctor = nv84_fifo_chan_ctor_dma, +static struct nvkm_ofuncs +g84_fifo_ofuncs_dma = { + .ctor = g84_fifo_chan_ctor_dma, .dtor = nv50_fifo_chan_dtor, - .init = nv84_fifo_chan_init, + .init = g84_fifo_chan_init, .fini = nv50_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_ofuncs -nv84_fifo_ofuncs_ind = { - .ctor = nv84_fifo_chan_ctor_ind, +static struct nvkm_ofuncs +g84_fifo_ofuncs_ind = { + .ctor = g84_fifo_chan_ctor_ind, .dtor = nv50_fifo_chan_dtor, - .init = nv84_fifo_chan_init, + .init = g84_fifo_chan_init, .fini = nv50_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass -nv84_fifo_sclass[] = { - { G82_CHANNEL_DMA, &nv84_fifo_ofuncs_dma }, - { G82_CHANNEL_GPFIFO, &nv84_fifo_ofuncs_ind }, +static struct nvkm_oclass +g84_fifo_sclass[] = { + { G82_CHANNEL_DMA, &g84_fifo_ofuncs_dma }, + { G82_CHANNEL_GPFIFO, &g84_fifo_ofuncs_ind }, {} }; @@ -354,57 +361,56 @@ nv84_fifo_sclass[] = { ******************************************************************************/ static int -nv84_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000, - 0x1000, NVOBJ_FLAG_HEAP, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, + 0x1000, NVOBJ_FLAG_HEAP, &base); *pobject = nv_object(base); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0, - NVOBJ_FLAG_ZERO_ALLOC, &base->eng); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0, + NVOBJ_FLAG_ZERO_ALLOC, &base->eng); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, - 0, &base->pgd); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, + 0, &base->pgd); if (ret) return ret; - ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000, - 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1000, + 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100, - 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0100, + 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); if (ret) return ret; return 0; } -static struct nouveau_oclass -nv84_fifo_cclass = { +static struct nvkm_oclass +g84_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_fifo_context_ctor, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_fifo_context_ctor, .dtor = nv50_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -413,69 +419,69 @@ nv84_fifo_cclass = { ******************************************************************************/ static void -nv84_fifo_uevent_init(struct nvkm_event *event, int type, int index) +g84_fifo_uevent_init(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x40000000, 0x40000000); } static void -nv84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x40000000, 0x00000000); } static const struct nvkm_event_func -nv84_fifo_uevent_func = { - .ctor = nouveau_fifo_uevent_ctor, - .init = nv84_fifo_uevent_init, - .fini = nv84_fifo_uevent_fini, +g84_fifo_uevent_func = { + .ctor = nvkm_fifo_uevent_ctor, + .init = g84_fifo_uevent_init, + .fini = g84_fifo_uevent_fini, }; static int -nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, + &priv->playlist[0]); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[1]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, + &priv->playlist[1]); if (ret) return ret; - ret = nvkm_event_init(&nv84_fifo_uevent_func, 1, 1, &priv->base.uevent); + ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &priv->base.uevent); if (ret) return ret; nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; - nv_engine(priv)->cclass = &nv84_fifo_cclass; - nv_engine(priv)->sclass = nv84_fifo_sclass; + nv_engine(priv)->cclass = &g84_fifo_cclass; + nv_engine(priv)->sclass = g84_fifo_sclass; priv->base.pause = nv04_fifo_pause; priv->base.start = nv04_fifo_start; return 0; } -struct nouveau_oclass * -nv84_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +g84_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_fifo_ctor, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_fifo_ctor, .dtor = nv50_fifo_dtor, .init = nv50_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index 074d434c3077..b745252f2261 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -21,52 +21,47 @@ * * Authors: Ben Skeggs */ +#include <engine/fifo.h> #include <core/client.h> -#include <core/handle.h> -#include <core/namedb.h> -#include <core/gpuobj.h> #include <core/engctx.h> -#include <core/event.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/enum.h> - -#include <subdev/timer.h> +#include <core/handle.h> #include <subdev/bar.h> #include <subdev/fb.h> -#include <subdev/vm.h> +#include <subdev/mmu.h> +#include <subdev/timer.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> +#include <nvif/class.h> +#include <nvif/unpack.h> -struct nvc0_fifo_priv { - struct nouveau_fifo base; +struct gf100_fifo_priv { + struct nvkm_fifo base; struct work_struct fault; u64 mask; struct { - struct nouveau_gpuobj *mem[2]; + struct nvkm_gpuobj *mem[2]; int active; wait_queue_head_t wait; } runlist; struct { - struct nouveau_gpuobj *mem; - struct nouveau_vma bar; + struct nvkm_gpuobj *mem; + struct nvkm_vma bar; } user; int spoon_nr; }; -struct nvc0_fifo_base { - struct nouveau_fifo_base base; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *vm; +struct gf100_fifo_base { + struct nvkm_fifo_base base; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; }; -struct nvc0_fifo_chan { - struct nouveau_fifo_chan base; +struct gf100_fifo_chan { + struct nvkm_fifo_chan base; enum { STOPPED, RUNNING, @@ -79,10 +74,10 @@ struct nvc0_fifo_chan { ******************************************************************************/ static void -nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv) +gf100_fifo_runlist_update(struct gf100_fifo_priv *priv) { - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_gpuobj *cur; + struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_gpuobj *cur; int i, p; mutex_lock(&nv_subdev(priv)->mutex); @@ -90,7 +85,7 @@ nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv) priv->runlist.active = !priv->runlist.active; for (i = 0, p = 0; i < 128; i++) { - struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i]; + struct gf100_fifo_chan *chan = (void *)priv->base.channel[i]; if (chan && chan->state == RUNNING) { nv_wo32(cur, p + 0, i); nv_wo32(cur, p + 4, 0x00000004); @@ -110,30 +105,30 @@ nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv) } static int -nvc0_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +gf100_fifo_context_attach(struct nvkm_object *parent, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); - struct nvc0_fifo_base *base = (void *)parent->parent; - struct nouveau_engctx *ectx = (void *)object; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gf100_fifo_base *base = (void *)parent->parent; + struct nvkm_engctx *ectx = (void *)object; u32 addr; int ret; switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_COPY0: addr = 0x0230; break; - case NVDEV_ENGINE_COPY1: addr = 0x0240; break; - case NVDEV_ENGINE_BSP : addr = 0x0270; break; - case NVDEV_ENGINE_VP : addr = 0x0250; break; - case NVDEV_ENGINE_PPP : addr = 0x0260; break; + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : addr = 0x0210; break; + case NVDEV_ENGINE_CE0 : addr = 0x0230; break; + case NVDEV_ENGINE_CE1 : addr = 0x0240; break; + case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; + case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; + case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; default: return -EINVAL; } if (!ectx->vma.node) { - ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, - NV_MEM_ACCESS_RW, &ectx->vma); + ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, + NV_MEM_ACCESS_RW, &ectx->vma); if (ret) return ret; @@ -147,23 +142,23 @@ nvc0_fifo_context_attach(struct nouveau_object *parent, } static int -nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *object) +gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); - struct nvc0_fifo_priv *priv = (void *)parent->engine; - struct nvc0_fifo_base *base = (void *)parent->parent; - struct nvc0_fifo_chan *chan = (void *)parent; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gf100_fifo_priv *priv = (void *)parent->engine; + struct gf100_fifo_base *base = (void *)parent->parent; + struct gf100_fifo_chan *chan = (void *)parent; u32 addr; switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_COPY0: addr = 0x0230; break; - case NVDEV_ENGINE_COPY1: addr = 0x0240; break; - case NVDEV_ENGINE_BSP : addr = 0x0270; break; - case NVDEV_ENGINE_VP : addr = 0x0250; break; - case NVDEV_ENGINE_PPP : addr = 0x0260; break; + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : addr = 0x0210; break; + case NVDEV_ENGINE_CE0 : addr = 0x0230; break; + case NVDEV_ENGINE_CE1 : addr = 0x0240; break; + case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; + case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; + case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; default: return -EINVAL; } @@ -171,7 +166,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, nv_wr32(priv, 0x002634, chan->base.chid); if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { nv_error(priv, "channel %d [%s] kick timeout\n", - chan->base.chid, nouveau_client_name(chan)); + chan->base.chid, nvkm_client_name(chan)); if (suspend) return -EBUSY; } @@ -183,18 +178,17 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nvc0_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); - struct nvc0_fifo_priv *priv = (void *)engine; - struct nvc0_fifo_base *base = (void *)parent; - struct nvc0_fifo_chan *chan; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gf100_fifo_priv *priv = (void *)engine; + struct gf100_fifo_base *base = (void *)parent; + struct gf100_fifo_chan *chan; u64 usermem, ioffset, ilength; int ret, i; @@ -207,24 +201,24 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, - priv->user.bar.offset, 0x1000, - args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_COPY0) | - (1ULL << NVDEV_ENGINE_COPY1) | - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_PPP), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, + priv->user.bar.offset, 0x1000, + args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_CE1) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP), &chan); *pobject = nv_object(chan); if (ret) return ret; args->v0.chid = chan->base.chid; - nv_parent(chan)->context_attach = nvc0_fifo_context_attach; - nv_parent(chan)->context_detach = nvc0_fifo_context_detach; + nv_parent(chan)->context_attach = gf100_fifo_context_attach; + nv_parent(chan)->context_detach = gf100_fifo_context_detach; usermem = chan->base.chid * 0x1000; ioffset = args->v0.ioffset; @@ -254,15 +248,15 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent, } static int -nvc0_fifo_chan_init(struct nouveau_object *object) +gf100_fifo_chan_init(struct nvkm_object *object) { - struct nouveau_gpuobj *base = nv_gpuobj(object->parent); - struct nvc0_fifo_priv *priv = (void *)object->engine; - struct nvc0_fifo_chan *chan = (void *)object; + struct nvkm_gpuobj *base = nv_gpuobj(object->parent); + struct gf100_fifo_priv *priv = (void *)object->engine; + struct gf100_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -270,47 +264,47 @@ nvc0_fifo_chan_init(struct nouveau_object *object) if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001); - nvc0_fifo_runlist_update(priv); + gf100_fifo_runlist_update(priv); } return 0; } -static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv); +static void gf100_fifo_intr_engine(struct gf100_fifo_priv *priv); static int -nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend) +gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend) { - struct nvc0_fifo_priv *priv = (void *)object->engine; - struct nvc0_fifo_chan *chan = (void *)object; + struct gf100_fifo_priv *priv = (void *)object->engine; + struct gf100_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); - nvc0_fifo_runlist_update(priv); + gf100_fifo_runlist_update(priv); } - nvc0_fifo_intr_engine(priv); + gf100_fifo_intr_engine(priv); nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); - return nouveau_fifo_channel_fini(&chan->base, suspend); + return nvkm_fifo_channel_fini(&chan->base, suspend); } -static struct nouveau_ofuncs -nvc0_fifo_ofuncs = { - .ctor = nvc0_fifo_chan_ctor, - .dtor = _nouveau_fifo_channel_dtor, - .init = nvc0_fifo_chan_init, - .fini = nvc0_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy +static struct nvkm_ofuncs +gf100_fifo_ofuncs = { + .ctor = gf100_fifo_chan_ctor, + .dtor = _nvkm_fifo_channel_dtor, + .init = gf100_fifo_chan_init, + .fini = gf100_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass -nvc0_fifo_sclass[] = { - { FERMI_CHANNEL_GPFIFO, &nvc0_fifo_ofuncs }, +static struct nvkm_oclass +gf100_fifo_sclass[] = { + { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs }, {} }; @@ -319,23 +313,22 @@ nvc0_fifo_sclass[] = { ******************************************************************************/ static int -nvc0_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_fifo_base *base; + struct gf100_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_HEAP, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_HEAP, &base); *pobject = nv_object(base); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, - &base->pgd); + ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, + &base->pgd); if (ret) return ret; @@ -344,7 +337,7 @@ nvc0_fifo_context_ctor(struct nouveau_object *parent, nv_wo32(base, 0x0208, 0xffffffff); nv_wo32(base, 0x020c, 0x000000ff); - ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); if (ret) return ret; @@ -352,24 +345,24 @@ nvc0_fifo_context_ctor(struct nouveau_object *parent, } static void -nvc0_fifo_context_dtor(struct nouveau_object *object) +gf100_fifo_context_dtor(struct nvkm_object *object) { - struct nvc0_fifo_base *base = (void *)object; - nouveau_vm_ref(NULL, &base->vm, base->pgd); - nouveau_gpuobj_ref(NULL, &base->pgd); - nouveau_fifo_context_destroy(&base->base); + struct gf100_fifo_base *base = (void *)object; + nvkm_vm_ref(NULL, &base->vm, base->pgd); + nvkm_gpuobj_ref(NULL, &base->pgd); + nvkm_fifo_context_destroy(&base->base); } -static struct nouveau_oclass -nvc0_fifo_cclass = { +static struct nvkm_oclass +gf100_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fifo_context_ctor, - .dtor = nvc0_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fifo_context_ctor, + .dtor = gf100_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -378,15 +371,15 @@ nvc0_fifo_cclass = { ******************************************************************************/ static inline int -nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn) +gf100_fifo_engidx(struct gf100_fifo_priv *priv, u32 engn) { switch (engn) { - case NVDEV_ENGINE_GR : engn = 0; break; - case NVDEV_ENGINE_BSP : engn = 1; break; - case NVDEV_ENGINE_PPP : engn = 2; break; - case NVDEV_ENGINE_VP : engn = 3; break; - case NVDEV_ENGINE_COPY0: engn = 4; break; - case NVDEV_ENGINE_COPY1: engn = 5; break; + case NVDEV_ENGINE_GR : engn = 0; break; + case NVDEV_ENGINE_MSVLD : engn = 1; break; + case NVDEV_ENGINE_MSPPP : engn = 2; break; + case NVDEV_ENGINE_MSPDEC: engn = 3; break; + case NVDEV_ENGINE_CE0 : engn = 4; break; + case NVDEV_ENGINE_CE1 : engn = 5; break; default: return -1; } @@ -394,28 +387,28 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn) return engn; } -static inline struct nouveau_engine * -nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn) +static inline struct nvkm_engine * +gf100_fifo_engine(struct gf100_fifo_priv *priv, u32 engn) { switch (engn) { case 0: engn = NVDEV_ENGINE_GR; break; - case 1: engn = NVDEV_ENGINE_BSP; break; - case 2: engn = NVDEV_ENGINE_PPP; break; - case 3: engn = NVDEV_ENGINE_VP; break; - case 4: engn = NVDEV_ENGINE_COPY0; break; - case 5: engn = NVDEV_ENGINE_COPY1; break; + case 1: engn = NVDEV_ENGINE_MSVLD; break; + case 2: engn = NVDEV_ENGINE_MSPPP; break; + case 3: engn = NVDEV_ENGINE_MSPDEC; break; + case 4: engn = NVDEV_ENGINE_CE0; break; + case 5: engn = NVDEV_ENGINE_CE1; break; default: return NULL; } - return nouveau_engine(priv, engn); + return nvkm_engine(priv, engn); } static void -nvc0_fifo_recover_work(struct work_struct *work) +gf100_fifo_recover_work(struct work_struct *work) { - struct nvc0_fifo_priv *priv = container_of(work, typeof(*priv), fault); - struct nouveau_object *engine; + struct gf100_fifo_priv *priv = container_of(work, typeof(*priv), fault); + struct nvkm_object *engine; unsigned long flags; u32 engn, engm = 0; u64 mask, todo; @@ -426,26 +419,25 @@ nvc0_fifo_recover_work(struct work_struct *work) spin_unlock_irqrestore(&priv->base.lock, flags); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) - engm |= 1 << nvc0_fifo_engidx(priv, engn); + engm |= 1 << gf100_fifo_engidx(priv, engn); nv_mask(priv, 0x002630, engm, engm); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { - if ((engine = (void *)nouveau_engine(priv, engn))) { + if ((engine = (void *)nvkm_engine(priv, engn))) { nv_ofuncs(engine)->fini(engine, false); WARN_ON(nv_ofuncs(engine)->init(engine)); } } - nvc0_fifo_runlist_update(priv); + gf100_fifo_runlist_update(priv); nv_wr32(priv, 0x00262c, engm); nv_mask(priv, 0x002630, engm, 0x00000000); } static void -nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine, - struct nvc0_fifo_chan *chan) +gf100_fifo_recover(struct gf100_fifo_priv *priv, struct nvkm_engine *engine, + struct gf100_fifo_chan *chan) { - struct nouveau_object *engobj = nv_object(engine); u32 chid = chan->base.chid; unsigned long flags; @@ -456,16 +448,16 @@ nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine, chan->state = KILLED; spin_lock_irqsave(&priv->base.lock, flags); - priv->mask |= 1ULL << nv_engidx(engobj); + priv->mask |= 1ULL << nv_engidx(engine); spin_unlock_irqrestore(&priv->base.lock, flags); schedule_work(&priv->fault); } static int -nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) +gf100_fifo_swmthd(struct gf100_fifo_priv *priv, u32 chid, u32 mthd, u32 data) { - struct nvc0_fifo_chan *chan = NULL; - struct nouveau_handle *bind; + struct gf100_fifo_chan *chan = NULL; + struct nvkm_handle *bind; unsigned long flags; int ret = -EINVAL; @@ -475,11 +467,11 @@ nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) if (unlikely(!chan)) goto out; - bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); + bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e); if (likely(bind)) { if (!mthd || !nv_call(bind->object, mthd, data)) ret = 0; - nouveau_namedb_put(bind); + nvkm_namedb_put(bind); } out: @@ -487,17 +479,17 @@ out: return ret; } -static const struct nouveau_enum -nvc0_fifo_sched_reason[] = { +static const struct nvkm_enum +gf100_fifo_sched_reason[] = { { 0x0a, "CTXSW_TIMEOUT" }, {} }; static void -nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv) +gf100_fifo_intr_sched_ctxsw(struct gf100_fifo_priv *priv) { - struct nouveau_engine *engine; - struct nvc0_fifo_chan *chan; + struct nvkm_engine *engine; + struct gf100_fifo_chan *chan; u32 engn; for (engn = 0; engn < 6; engn++) { @@ -512,22 +504,22 @@ nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv) if (busy && unk0 && unk1) { if (!(chan = (void *)priv->base.channel[chid])) continue; - if (!(engine = nvc0_fifo_engine(priv, engn))) + if (!(engine = gf100_fifo_engine(priv, engn))) continue; - nvc0_fifo_recover(priv, engine, chan); + gf100_fifo_recover(priv, engine, chan); } } } static void -nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv) +gf100_fifo_intr_sched(struct gf100_fifo_priv *priv) { u32 intr = nv_rd32(priv, 0x00254c); u32 code = intr & 0x000000ff; - const struct nouveau_enum *en; + const struct nvkm_enum *en; char enunk[6] = ""; - en = nouveau_enum_find(nvc0_fifo_sched_reason, code); + en = nvkm_enum_find(gf100_fifo_sched_reason, code); if (!en) snprintf(enunk, sizeof(enunk), "UNK%02x", code); @@ -535,32 +527,32 @@ nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv) switch (code) { case 0x0a: - nvc0_fifo_intr_sched_ctxsw(priv); + gf100_fifo_intr_sched_ctxsw(priv); break; default: break; } } -static const struct nouveau_enum -nvc0_fifo_fault_engine[] = { +static const struct nvkm_enum +gf100_fifo_fault_engine[] = { { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB }, { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, - { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP }, - { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP }, + { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD }, + { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP }, { 0x13, "PCOUNTER" }, - { 0x14, "PVP", NULL, NVDEV_ENGINE_VP }, - { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 }, - { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 }, + { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC }, + { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 }, + { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 }, { 0x17, "PDAEMON" }, {} }; -static const struct nouveau_enum -nvc0_fifo_fault_reason[] = { +static const struct nvkm_enum +gf100_fifo_fault_reason[] = { { 0x00, "PT_NOT_PRESENT" }, { 0x01, "PT_TOO_SHORT" }, { 0x02, "PAGE_NOT_PRESENT" }, @@ -573,8 +565,8 @@ nvc0_fifo_fault_reason[] = { {} }; -static const struct nouveau_enum -nvc0_fifo_fault_hubclient[] = { +static const struct nvkm_enum +gf100_fifo_fault_hubclient[] = { { 0x01, "PCOPY0" }, { 0x02, "PCOPY1" }, { 0x04, "DISPATCH" }, @@ -583,8 +575,8 @@ nvc0_fifo_fault_hubclient[] = { { 0x07, "BAR_READ" }, { 0x08, "BAR_WRITE" }, { 0x0b, "PVP" }, - { 0x0c, "PPPP" }, - { 0x0d, "PBSP" }, + { 0x0c, "PMSPPP" }, + { 0x0d, "PMSVLD" }, { 0x11, "PCOUNTER" }, { 0x12, "PDAEMON" }, { 0x14, "CCACHE" }, @@ -592,8 +584,8 @@ nvc0_fifo_fault_hubclient[] = { {} }; -static const struct nouveau_enum -nvc0_fifo_fault_gpcclient[] = { +static const struct nvkm_enum +gf100_fifo_fault_gpcclient[] = { { 0x01, "TEX" }, { 0x0c, "ESETUP" }, { 0x0e, "CTXCTL" }, @@ -602,7 +594,7 @@ nvc0_fifo_fault_gpcclient[] = { }; static void -nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) +gf100_fifo_intr_fault(struct gf100_fifo_priv *priv, int unit) { u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); @@ -613,19 +605,19 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) u32 write = (stat & 0x00000080); u32 hub = (stat & 0x00000040); u32 reason = (stat & 0x0000000f); - struct nouveau_object *engctx = NULL, *object; - struct nouveau_engine *engine = NULL; - const struct nouveau_enum *er, *eu, *ec; + struct nvkm_object *engctx = NULL, *object; + struct nvkm_engine *engine = NULL; + const struct nvkm_enum *er, *eu, *ec; char erunk[6] = ""; char euunk[6] = ""; char ecunk[6] = ""; char gpcid[3] = ""; - er = nouveau_enum_find(nvc0_fifo_fault_reason, reason); + er = nvkm_enum_find(gf100_fifo_fault_reason, reason); if (!er) snprintf(erunk, sizeof(erunk), "UNK%02X", reason); - eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit); + eu = nvkm_enum_find(gf100_fifo_fault_engine, unit); if (eu) { switch (eu->data2) { case NVDEV_SUBDEV_BAR: @@ -638,9 +630,9 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) nv_mask(priv, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nouveau_engine(priv, eu->data2); + engine = nvkm_engine(priv, eu->data2); if (engine) - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); break; } } else { @@ -648,9 +640,9 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) } if (hub) { - ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client); + ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client); } else { - ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client); + ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client); snprintf(gpcid, sizeof(gpcid), "%d", gpc); } @@ -662,23 +654,23 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) (u64)vahi << 32 | valo, er ? er->name : erunk, eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", ec ? ec->name : ecunk, (u64)inst << 12, - nouveau_client_name(engctx)); + nvkm_client_name(engctx)); object = engctx; while (object) { switch (nv_mclass(object)) { case FERMI_CHANNEL_GPFIFO: - nvc0_fifo_recover(priv, engine, (void *)object); + gf100_fifo_recover(priv, engine, (void *)object); break; } object = object->parent; } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } -static const struct nouveau_bitfield -nvc0_fifo_pbdma_intr[] = { +static const struct nvkm_bitfield +gf100_fifo_pbdma_intr[] = { /* { 0x00008000, "" } seen with null ib push */ { 0x00200000, "ILLEGAL_MTHD" }, { 0x00800000, "EMPTY_SUBC" }, @@ -686,7 +678,7 @@ nvc0_fifo_pbdma_intr[] = { }; static void -nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit) +gf100_fifo_intr_pbdma(struct gf100_fifo_priv *priv, int unit) { u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); @@ -697,18 +689,18 @@ nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit) u32 show = stat; if (stat & 0x00800000) { - if (!nvc0_fifo_swmthd(priv, chid, mthd, data)) + if (!gf100_fifo_swmthd(priv, chid, mthd, data)) show &= ~0x00800000; } if (show) { nv_error(priv, "PBDMA%d:", unit); - nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show); + nvkm_bitfield_print(gf100_fifo_pbdma_intr, show); pr_cont("\n"); nv_error(priv, "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", unit, chid, - nouveau_client_name_for_fifo_chid(&priv->base, chid), + nvkm_client_name_for_fifo_chid(&priv->base, chid), subc, mthd, data); } @@ -717,7 +709,7 @@ nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit) } static void -nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv) +gf100_fifo_intr_runlist(struct gf100_fifo_priv *priv) { u32 intr = nv_rd32(priv, 0x002a00); @@ -734,7 +726,7 @@ nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv) } static void -nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) +gf100_fifo_intr_engine_unit(struct gf100_fifo_priv *priv, int engn) { u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04)); u32 inte = nv_rd32(priv, 0x002628); @@ -745,7 +737,7 @@ nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) for (unkn = 0; unkn < 8; unkn++) { u32 ints = (intr >> (unkn * 0x04)) & inte; if (ints & 0x1) { - nouveau_fifo_uevent(&priv->base); + nvkm_fifo_uevent(&priv->base); ints &= ~1; } if (ints) { @@ -756,20 +748,20 @@ nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) } static void -nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv) +gf100_fifo_intr_engine(struct gf100_fifo_priv *priv) { u32 mask = nv_rd32(priv, 0x0025a4); while (mask) { u32 unit = __ffs(mask); - nvc0_fifo_intr_engine_unit(priv, unit); + gf100_fifo_intr_engine_unit(priv, unit); mask &= ~(1 << unit); } } static void -nvc0_fifo_intr(struct nouveau_subdev *subdev) +gf100_fifo_intr(struct nvkm_subdev *subdev) { - struct nvc0_fifo_priv *priv = (void *)subdev; + struct gf100_fifo_priv *priv = (void *)subdev; u32 mask = nv_rd32(priv, 0x002140); u32 stat = nv_rd32(priv, 0x002100) & mask; @@ -781,7 +773,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x00000100) { - nvc0_fifo_intr_sched(priv); + gf100_fifo_intr_sched(priv); nv_wr32(priv, 0x002100, 0x00000100); stat &= ~0x00000100; } @@ -804,7 +796,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) u32 mask = nv_rd32(priv, 0x00259c); while (mask) { u32 unit = __ffs(mask); - nvc0_fifo_intr_fault(priv, unit); + gf100_fifo_intr_fault(priv, unit); nv_wr32(priv, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } @@ -815,7 +807,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) u32 mask = nv_rd32(priv, 0x0025a0); while (mask) { u32 unit = __ffs(mask); - nvc0_fifo_intr_pbdma(priv, unit); + gf100_fifo_intr_pbdma(priv, unit); nv_wr32(priv, 0x0025a0, (1 << unit)); mask &= ~(1 << unit); } @@ -823,12 +815,12 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x40000000) { - nvc0_fifo_intr_runlist(priv); + gf100_fifo_intr_runlist(priv); stat &= ~0x40000000; } if (stat & 0x80000000) { - nvc0_fifo_intr_engine(priv); + gf100_fifo_intr_engine(priv); stat &= ~0x80000000; } @@ -840,94 +832,94 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) } static void -nvc0_fifo_uevent_init(struct nvkm_event *event, int type, int index) +gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x80000000, 0x80000000); } static void -nvc0_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); } static const struct nvkm_event_func -nvc0_fifo_uevent_func = { - .ctor = nouveau_fifo_uevent_ctor, - .init = nvc0_fifo_uevent_init, - .fini = nvc0_fifo_uevent_fini, +gf100_fifo_uevent_func = { + .ctor = nvkm_fifo_uevent_ctor, + .init = gf100_fifo_uevent_init, + .fini = gf100_fifo_uevent_fini, }; static int -nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_fifo_priv *priv; + struct gf100_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &priv); *pobject = nv_object(priv); if (ret) return ret; - INIT_WORK(&priv->fault, nvc0_fifo_recover_work); + INIT_WORK(&priv->fault, gf100_fifo_recover_work); - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, - &priv->runlist.mem[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, + &priv->runlist.mem[0]); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, - &priv->runlist.mem[1]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, + &priv->runlist.mem[1]); if (ret) return ret; init_waitqueue_head(&priv->runlist.wait); - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0, - &priv->user.mem); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0, + &priv->user.mem); if (ret) return ret; - ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, - &priv->user.bar); + ret = nvkm_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, + &priv->user.bar); if (ret) return ret; - ret = nvkm_event_init(&nvc0_fifo_uevent_func, 1, 1, &priv->base.uevent); + ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &priv->base.uevent); if (ret) return ret; nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nvc0_fifo_intr; - nv_engine(priv)->cclass = &nvc0_fifo_cclass; - nv_engine(priv)->sclass = nvc0_fifo_sclass; + nv_subdev(priv)->intr = gf100_fifo_intr; + nv_engine(priv)->cclass = &gf100_fifo_cclass; + nv_engine(priv)->sclass = gf100_fifo_sclass; return 0; } static void -nvc0_fifo_dtor(struct nouveau_object *object) +gf100_fifo_dtor(struct nvkm_object *object) { - struct nvc0_fifo_priv *priv = (void *)object; + struct gf100_fifo_priv *priv = (void *)object; - nouveau_gpuobj_unmap(&priv->user.bar); - nouveau_gpuobj_ref(NULL, &priv->user.mem); - nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]); - nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]); + nvkm_gpuobj_unmap(&priv->user.bar); + nvkm_gpuobj_ref(NULL, &priv->user.mem); + nvkm_gpuobj_ref(NULL, &priv->runlist.mem[0]); + nvkm_gpuobj_ref(NULL, &priv->runlist.mem[1]); - nouveau_fifo_destroy(&priv->base); + nvkm_fifo_destroy(&priv->base); } static int -nvc0_fifo_init(struct nouveau_object *object) +gf100_fifo_init(struct nvkm_object *object) { - struct nvc0_fifo_priv *priv = (void *)object; + struct gf100_fifo_priv *priv = (void *)object; int ret, i; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -941,8 +933,8 @@ nvc0_fifo_init(struct nouveau_object *object) if (priv->spoon_nr >= 3) { nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */ nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */ - nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */ - nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */ + nv_wr32(priv, 0x002210, ~(1 << 1)); /* PMSPP */ + nv_wr32(priv, 0x002214, ~(1 << 1)); /* PMSVLD */ nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */ nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */ } @@ -963,13 +955,13 @@ nvc0_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nvc0_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +gf100_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fifo_ctor, - .dtor = nvc0_fifo_dtor, - .init = nvc0_fifo_init, - .fini = _nouveau_fifo_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fifo_ctor, + .dtor = gf100_fifo_dtor, + .init = gf100_fifo_init, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 6a8db7c80bd1..9585539e59f2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -21,25 +21,19 @@ * * Authors: Ben Skeggs */ +#include "gk104.h" #include <core/client.h> -#include <core/handle.h> -#include <core/namedb.h> -#include <core/gpuobj.h> #include <core/engctx.h> -#include <core/event.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/enum.h> - -#include <subdev/timer.h> +#include <core/handle.h> #include <subdev/bar.h> #include <subdev/fb.h> -#include <subdev/vm.h> - -#include <engine/dmaobj.h> +#include <subdev/mmu.h> +#include <subdev/timer.h> -#include "nve0.h" +#include <nvif/class.h> +#include <nvif/unpack.h> #define _(a,b) { (a), ((1ULL << (a)) | (b)) } static const struct { @@ -47,45 +41,45 @@ static const struct { u64 mask; } fifo_engine[] = { _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_COPY2)), - _(NVDEV_ENGINE_VP , 0), - _(NVDEV_ENGINE_PPP , 0), - _(NVDEV_ENGINE_BSP , 0), - _(NVDEV_ENGINE_COPY0 , 0), - _(NVDEV_ENGINE_COPY1 , 0), - _(NVDEV_ENGINE_VENC , 0), + (1ULL << NVDEV_ENGINE_CE2)), + _(NVDEV_ENGINE_MSPDEC , 0), + _(NVDEV_ENGINE_MSPPP , 0), + _(NVDEV_ENGINE_MSVLD , 0), + _(NVDEV_ENGINE_CE0 , 0), + _(NVDEV_ENGINE_CE1 , 0), + _(NVDEV_ENGINE_MSENC , 0), }; #undef _ #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) -struct nve0_fifo_engn { - struct nouveau_gpuobj *runlist[2]; +struct gk104_fifo_engn { + struct nvkm_gpuobj *runlist[2]; int cur_runlist; wait_queue_head_t wait; }; -struct nve0_fifo_priv { - struct nouveau_fifo base; +struct gk104_fifo_priv { + struct nvkm_fifo base; struct work_struct fault; u64 mask; - struct nve0_fifo_engn engine[FIFO_ENGINE_NR]; + struct gk104_fifo_engn engine[FIFO_ENGINE_NR]; struct { - struct nouveau_gpuobj *mem; - struct nouveau_vma bar; + struct nvkm_gpuobj *mem; + struct nvkm_vma bar; } user; int spoon_nr; }; -struct nve0_fifo_base { - struct nouveau_fifo_base base; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *vm; +struct gk104_fifo_base { + struct nvkm_fifo_base base; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; }; -struct nve0_fifo_chan { - struct nouveau_fifo_chan base; +struct gk104_fifo_chan { + struct nvkm_fifo_chan base; u32 engine; enum { STOPPED, @@ -99,11 +93,11 @@ struct nve0_fifo_chan { ******************************************************************************/ static void -nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine) +gk104_fifo_runlist_update(struct gk104_fifo_priv *priv, u32 engine) { - struct nouveau_bar *bar = nouveau_bar(priv); - struct nve0_fifo_engn *engn = &priv->engine[engine]; - struct nouveau_gpuobj *cur; + struct nvkm_bar *bar = nvkm_bar(priv); + struct gk104_fifo_engn *engn = &priv->engine[engine]; + struct nvkm_gpuobj *cur; int i, p; mutex_lock(&nv_subdev(priv)->mutex); @@ -111,7 +105,7 @@ nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine) engn->cur_runlist = !engn->cur_runlist; for (i = 0, p = 0; i < priv->base.max; i++) { - struct nve0_fifo_chan *chan = (void *)priv->base.channel[i]; + struct gk104_fifo_chan *chan = (void *)priv->base.channel[i]; if (chan && chan->state == RUNNING && chan->engine == engine) { nv_wo32(cur, p + 0, i); nv_wo32(cur, p + 4, 0x00000000); @@ -131,34 +125,34 @@ nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine) } static int -nve0_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +gk104_fifo_context_attach(struct nvkm_object *parent, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); - struct nve0_fifo_base *base = (void *)parent->parent; - struct nouveau_engctx *ectx = (void *)object; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gk104_fifo_base *base = (void *)parent->parent; + struct nvkm_engctx *ectx = (void *)object; u32 addr; int ret; switch (nv_engidx(object->engine)) { case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_COPY0: - case NVDEV_ENGINE_COPY1: - case NVDEV_ENGINE_COPY2: + case NVDEV_ENGINE_CE0: + case NVDEV_ENGINE_CE1: + case NVDEV_ENGINE_CE2: nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; return 0; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_BSP : addr = 0x0270; break; - case NVDEV_ENGINE_VP : addr = 0x0250; break; - case NVDEV_ENGINE_PPP : addr = 0x0260; break; + case NVDEV_ENGINE_GR : addr = 0x0210; break; + case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; + case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; + case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; default: return -EINVAL; } if (!ectx->vma.node) { - ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, - NV_MEM_ACCESS_RW, &ectx->vma); + ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, + NV_MEM_ACCESS_RW, &ectx->vma); if (ret) return ret; @@ -172,24 +166,24 @@ nve0_fifo_context_attach(struct nouveau_object *parent, } static int -nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *object) +gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); - struct nve0_fifo_priv *priv = (void *)parent->engine; - struct nve0_fifo_base *base = (void *)parent->parent; - struct nve0_fifo_chan *chan = (void *)parent; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gk104_fifo_priv *priv = (void *)parent->engine; + struct gk104_fifo_base *base = (void *)parent->parent; + struct gk104_fifo_chan *chan = (void *)parent; u32 addr; switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_COPY0: - case NVDEV_ENGINE_COPY1: - case NVDEV_ENGINE_COPY2: addr = 0x0000; break; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_BSP : addr = 0x0270; break; - case NVDEV_ENGINE_VP : addr = 0x0250; break; - case NVDEV_ENGINE_PPP : addr = 0x0260; break; + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_CE0 : + case NVDEV_ENGINE_CE1 : + case NVDEV_ENGINE_CE2 : addr = 0x0000; break; + case NVDEV_ENGINE_GR : addr = 0x0210; break; + case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; + case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; + case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; default: return -EINVAL; } @@ -197,7 +191,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, nv_wr32(priv, 0x002634, chan->base.chid); if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { nv_error(priv, "channel %d [%s] kick timeout\n", - chan->base.chid, nouveau_client_name(chan)); + chan->base.chid, nvkm_client_name(chan)); if (suspend) return -EBUSY; } @@ -212,18 +206,17 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nve0_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct kepler_channel_gpfifo_a_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); - struct nve0_fifo_priv *priv = (void *)engine; - struct nve0_fifo_base *base = (void *)parent; - struct nve0_fifo_chan *chan; + struct nvkm_bar *bar = nvkm_bar(parent); + struct gk104_fifo_priv *priv = (void *)engine; + struct gk104_fifo_base *base = (void *)parent; + struct gk104_fifo_chan *chan; u64 usermem, ioffset, ilength; int ret, i; @@ -238,7 +231,7 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent, for (i = 0; i < FIFO_ENGINE_NR; i++) { if (args->v0.engine & (1 << i)) { - if (nouveau_engine(parent, fifo_engine[i].subdev)) { + if (nvkm_engine(parent, fifo_engine[i].subdev)) { args->v0.engine = (1 << i); break; } @@ -250,18 +243,18 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent, return -ENODEV; } - ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, - priv->user.bar.offset, 0x200, - args->v0.pushbuf, - fifo_engine[i].mask, &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, + priv->user.bar.offset, 0x200, + args->v0.pushbuf, + fifo_engine[i].mask, &chan); *pobject = nv_object(chan); if (ret) return ret; args->v0.chid = chan->base.chid; - nv_parent(chan)->context_attach = nve0_fifo_context_attach; - nv_parent(chan)->context_detach = nve0_fifo_context_detach; + nv_parent(chan)->context_attach = gk104_fifo_context_attach; + nv_parent(chan)->context_detach = gk104_fifo_context_detach; chan->engine = i; usermem = chan->base.chid * 0x200; @@ -290,15 +283,15 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent, } static int -nve0_fifo_chan_init(struct nouveau_object *object) +gk104_fifo_chan_init(struct nvkm_object *object) { - struct nouveau_gpuobj *base = nv_gpuobj(object->parent); - struct nve0_fifo_priv *priv = (void *)object->engine; - struct nve0_fifo_chan *chan = (void *)object; + struct nvkm_gpuobj *base = nv_gpuobj(object->parent); + struct gk104_fifo_priv *priv = (void *)object->engine; + struct gk104_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -307,7 +300,7 @@ nve0_fifo_chan_init(struct nouveau_object *object) if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); - nve0_fifo_runlist_update(priv, chan->engine); + gk104_fifo_runlist_update(priv, chan->engine); nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); } @@ -315,36 +308,36 @@ nve0_fifo_chan_init(struct nouveau_object *object) } static int -nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend) +gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend) { - struct nve0_fifo_priv *priv = (void *)object->engine; - struct nve0_fifo_chan *chan = (void *)object; + struct gk104_fifo_priv *priv = (void *)object->engine; + struct gk104_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); - nve0_fifo_runlist_update(priv, chan->engine); + gk104_fifo_runlist_update(priv, chan->engine); } nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); - return nouveau_fifo_channel_fini(&chan->base, suspend); + return nvkm_fifo_channel_fini(&chan->base, suspend); } -static struct nouveau_ofuncs -nve0_fifo_ofuncs = { - .ctor = nve0_fifo_chan_ctor, - .dtor = _nouveau_fifo_channel_dtor, - .init = nve0_fifo_chan_init, - .fini = nve0_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy +static struct nvkm_ofuncs +gk104_fifo_ofuncs = { + .ctor = gk104_fifo_chan_ctor, + .dtor = _nvkm_fifo_channel_dtor, + .init = gk104_fifo_chan_init, + .fini = gk104_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass -nve0_fifo_sclass[] = { - { KEPLER_CHANNEL_GPFIFO_A, &nve0_fifo_ofuncs }, +static struct nvkm_oclass +gk104_fifo_sclass[] = { + { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_ofuncs }, {} }; @@ -353,22 +346,21 @@ nve0_fifo_sclass[] = { ******************************************************************************/ static int -nve0_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_fifo_base *base; + struct gk104_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base); *pobject = nv_object(base); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, - &base->pgd); + ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, + &base->pgd); if (ret) return ret; @@ -377,7 +369,7 @@ nve0_fifo_context_ctor(struct nouveau_object *parent, nv_wo32(base, 0x0208, 0xffffffff); nv_wo32(base, 0x020c, 0x000000ff); - ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); if (ret) return ret; @@ -385,24 +377,24 @@ nve0_fifo_context_ctor(struct nouveau_object *parent, } static void -nve0_fifo_context_dtor(struct nouveau_object *object) +gk104_fifo_context_dtor(struct nvkm_object *object) { - struct nve0_fifo_base *base = (void *)object; - nouveau_vm_ref(NULL, &base->vm, base->pgd); - nouveau_gpuobj_ref(NULL, &base->pgd); - nouveau_fifo_context_destroy(&base->base); + struct gk104_fifo_base *base = (void *)object; + nvkm_vm_ref(NULL, &base->vm, base->pgd); + nvkm_gpuobj_ref(NULL, &base->pgd); + nvkm_fifo_context_destroy(&base->base); } -static struct nouveau_oclass -nve0_fifo_cclass = { +static struct nvkm_oclass +gk104_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_fifo_context_ctor, - .dtor = nve0_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_fifo_context_ctor, + .dtor = gk104_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -411,17 +403,17 @@ nve0_fifo_cclass = { ******************************************************************************/ static inline int -nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn) +gk104_fifo_engidx(struct gk104_fifo_priv *priv, u32 engn) { switch (engn) { - case NVDEV_ENGINE_GR : - case NVDEV_ENGINE_COPY2: engn = 0; break; - case NVDEV_ENGINE_BSP : engn = 1; break; - case NVDEV_ENGINE_PPP : engn = 2; break; - case NVDEV_ENGINE_VP : engn = 3; break; - case NVDEV_ENGINE_COPY0: engn = 4; break; - case NVDEV_ENGINE_COPY1: engn = 5; break; - case NVDEV_ENGINE_VENC : engn = 6; break; + case NVDEV_ENGINE_GR : + case NVDEV_ENGINE_CE2 : engn = 0; break; + case NVDEV_ENGINE_MSVLD : engn = 1; break; + case NVDEV_ENGINE_MSPPP : engn = 2; break; + case NVDEV_ENGINE_MSPDEC: engn = 3; break; + case NVDEV_ENGINE_CE0 : engn = 4; break; + case NVDEV_ENGINE_CE1 : engn = 5; break; + case NVDEV_ENGINE_MSENC : engn = 6; break; default: return -1; } @@ -429,19 +421,19 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn) return engn; } -static inline struct nouveau_engine * -nve0_fifo_engine(struct nve0_fifo_priv *priv, u32 engn) +static inline struct nvkm_engine * +gk104_fifo_engine(struct gk104_fifo_priv *priv, u32 engn) { if (engn >= ARRAY_SIZE(fifo_engine)) return NULL; - return nouveau_engine(priv, fifo_engine[engn].subdev); + return nvkm_engine(priv, fifo_engine[engn].subdev); } static void -nve0_fifo_recover_work(struct work_struct *work) +gk104_fifo_recover_work(struct work_struct *work) { - struct nve0_fifo_priv *priv = container_of(work, typeof(*priv), fault); - struct nouveau_object *engine; + struct gk104_fifo_priv *priv = container_of(work, typeof(*priv), fault); + struct nvkm_object *engine; unsigned long flags; u32 engn, engm = 0; u64 mask, todo; @@ -452,15 +444,15 @@ nve0_fifo_recover_work(struct work_struct *work) spin_unlock_irqrestore(&priv->base.lock, flags); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) - engm |= 1 << nve0_fifo_engidx(priv, engn); + engm |= 1 << gk104_fifo_engidx(priv, engn); nv_mask(priv, 0x002630, engm, engm); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { - if ((engine = (void *)nouveau_engine(priv, engn))) { + if ((engine = (void *)nvkm_engine(priv, engn))) { nv_ofuncs(engine)->fini(engine, false); WARN_ON(nv_ofuncs(engine)->init(engine)); } - nve0_fifo_runlist_update(priv, nve0_fifo_engidx(priv, engn)); + gk104_fifo_runlist_update(priv, gk104_fifo_engidx(priv, engn)); } nv_wr32(priv, 0x00262c, engm); @@ -468,10 +460,9 @@ nve0_fifo_recover_work(struct work_struct *work) } static void -nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine, - struct nve0_fifo_chan *chan) +gk104_fifo_recover(struct gk104_fifo_priv *priv, struct nvkm_engine *engine, + struct gk104_fifo_chan *chan) { - struct nouveau_object *engobj = nv_object(engine); u32 chid = chan->base.chid; unsigned long flags; @@ -482,16 +473,16 @@ nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine, chan->state = KILLED; spin_lock_irqsave(&priv->base.lock, flags); - priv->mask |= 1ULL << nv_engidx(engobj); + priv->mask |= 1ULL << nv_engidx(engine); spin_unlock_irqrestore(&priv->base.lock, flags); schedule_work(&priv->fault); } static int -nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) +gk104_fifo_swmthd(struct gk104_fifo_priv *priv, u32 chid, u32 mthd, u32 data) { - struct nve0_fifo_chan *chan = NULL; - struct nouveau_handle *bind; + struct gk104_fifo_chan *chan = NULL; + struct nvkm_handle *bind; unsigned long flags; int ret = -EINVAL; @@ -501,11 +492,11 @@ nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) if (unlikely(!chan)) goto out; - bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); + bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e); if (likely(bind)) { if (!mthd || !nv_call(bind->object, mthd, data)) ret = 0; - nouveau_namedb_put(bind); + nvkm_namedb_put(bind); } out: @@ -513,8 +504,8 @@ out: return ret; } -static const struct nouveau_enum -nve0_fifo_bind_reason[] = { +static const struct nvkm_enum +gk104_fifo_bind_reason[] = { { 0x01, "BIND_NOT_UNBOUND" }, { 0x02, "SNOOP_WITHOUT_BAR1" }, { 0x03, "UNBIND_WHILE_RUNNING" }, @@ -525,31 +516,31 @@ nve0_fifo_bind_reason[] = { }; static void -nve0_fifo_intr_bind(struct nve0_fifo_priv *priv) +gk104_fifo_intr_bind(struct gk104_fifo_priv *priv) { u32 intr = nv_rd32(priv, 0x00252c); u32 code = intr & 0x000000ff; - const struct nouveau_enum *en; + const struct nvkm_enum *en; char enunk[6] = ""; - en = nouveau_enum_find(nve0_fifo_bind_reason, code); + en = nvkm_enum_find(gk104_fifo_bind_reason, code); if (!en) snprintf(enunk, sizeof(enunk), "UNK%02x", code); nv_error(priv, "BIND_ERROR [ %s ]\n", en ? en->name : enunk); } -static const struct nouveau_enum -nve0_fifo_sched_reason[] = { +static const struct nvkm_enum +gk104_fifo_sched_reason[] = { { 0x0a, "CTXSW_TIMEOUT" }, {} }; static void -nve0_fifo_intr_sched_ctxsw(struct nve0_fifo_priv *priv) +gk104_fifo_intr_sched_ctxsw(struct gk104_fifo_priv *priv) { - struct nouveau_engine *engine; - struct nve0_fifo_chan *chan; + struct nvkm_engine *engine; + struct gk104_fifo_chan *chan; u32 engn; for (engn = 0; engn < ARRAY_SIZE(fifo_engine); engn++) { @@ -566,22 +557,22 @@ nve0_fifo_intr_sched_ctxsw(struct nve0_fifo_priv *priv) if (busy && chsw) { if (!(chan = (void *)priv->base.channel[chid])) continue; - if (!(engine = nve0_fifo_engine(priv, engn))) + if (!(engine = gk104_fifo_engine(priv, engn))) continue; - nve0_fifo_recover(priv, engine, chan); + gk104_fifo_recover(priv, engine, chan); } } } static void -nve0_fifo_intr_sched(struct nve0_fifo_priv *priv) +gk104_fifo_intr_sched(struct gk104_fifo_priv *priv) { u32 intr = nv_rd32(priv, 0x00254c); u32 code = intr & 0x000000ff; - const struct nouveau_enum *en; + const struct nvkm_enum *en; char enunk[6] = ""; - en = nouveau_enum_find(nve0_fifo_sched_reason, code); + en = nvkm_enum_find(gk104_fifo_sched_reason, code); if (!en) snprintf(enunk, sizeof(enunk), "UNK%02x", code); @@ -589,7 +580,7 @@ nve0_fifo_intr_sched(struct nve0_fifo_priv *priv) switch (code) { case 0x0a: - nve0_fifo_intr_sched_ctxsw(priv); + gk104_fifo_intr_sched_ctxsw(priv); break; default: break; @@ -597,7 +588,7 @@ nve0_fifo_intr_sched(struct nve0_fifo_priv *priv) } static void -nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv) +gk104_fifo_intr_chsw(struct gk104_fifo_priv *priv) { u32 stat = nv_rd32(priv, 0x00256c); nv_error(priv, "CHSW_ERROR 0x%08x\n", stat); @@ -605,14 +596,14 @@ nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv) } static void -nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv) +gk104_fifo_intr_dropped_fault(struct gk104_fifo_priv *priv) { u32 stat = nv_rd32(priv, 0x00259c); nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat); } -static const struct nouveau_enum -nve0_fifo_fault_engine[] = { +static const struct nvkm_enum +gk104_fifo_fault_engine[] = { { 0x00, "GR", NULL, NVDEV_ENGINE_GR }, { 0x03, "IFB", NULL, NVDEV_ENGINE_IFB }, { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, @@ -620,20 +611,20 @@ nve0_fifo_fault_engine[] = { { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO }, { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO }, { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO }, - { 0x10, "MSVLD", NULL, NVDEV_ENGINE_BSP }, - { 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP }, + { 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD }, + { 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP }, { 0x13, "PERF" }, - { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP }, - { 0x15, "CE0", NULL, NVDEV_ENGINE_COPY0 }, - { 0x16, "CE1", NULL, NVDEV_ENGINE_COPY1 }, + { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_MSPDEC }, + { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 }, + { 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 }, { 0x17, "PMU" }, - { 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC }, - { 0x1b, "CE2", NULL, NVDEV_ENGINE_COPY2 }, + { 0x19, "MSENC", NULL, NVDEV_ENGINE_MSENC }, + { 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 }, {} }; -static const struct nouveau_enum -nve0_fifo_fault_reason[] = { +static const struct nvkm_enum +gk104_fifo_fault_reason[] = { { 0x00, "PDE" }, { 0x01, "PDE_SIZE" }, { 0x02, "PTE" }, @@ -653,8 +644,8 @@ nve0_fifo_fault_reason[] = { {} }; -static const struct nouveau_enum -nve0_fifo_fault_hubclient[] = { +static const struct nvkm_enum +gk104_fifo_fault_hubclient[] = { { 0x00, "VIP" }, { 0x01, "CE0" }, { 0x02, "CE1" }, @@ -679,7 +670,7 @@ nve0_fifo_fault_hubclient[] = { { 0x15, "SCC_NB" }, { 0x16, "SEC" }, { 0x17, "SSYNC" }, - { 0x18, "GR_COPY" }, + { 0x18, "GR_CE" }, { 0x19, "CE2" }, { 0x1a, "XV" }, { 0x1b, "MMU_NB" }, @@ -690,8 +681,8 @@ nve0_fifo_fault_hubclient[] = { {} }; -static const struct nouveau_enum -nve0_fifo_fault_gpcclient[] = { +static const struct nvkm_enum +gk104_fifo_fault_gpcclient[] = { { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" }, { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" }, { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" }, @@ -717,7 +708,7 @@ nve0_fifo_fault_gpcclient[] = { }; static void -nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) +gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit) { u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); @@ -728,19 +719,19 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) u32 write = (stat & 0x00000080); u32 hub = (stat & 0x00000040); u32 reason = (stat & 0x0000000f); - struct nouveau_object *engctx = NULL, *object; - struct nouveau_engine *engine = NULL; - const struct nouveau_enum *er, *eu, *ec; + struct nvkm_object *engctx = NULL, *object; + struct nvkm_engine *engine = NULL; + const struct nvkm_enum *er, *eu, *ec; char erunk[6] = ""; char euunk[6] = ""; char ecunk[6] = ""; char gpcid[3] = ""; - er = nouveau_enum_find(nve0_fifo_fault_reason, reason); + er = nvkm_enum_find(gk104_fifo_fault_reason, reason); if (!er) snprintf(erunk, sizeof(erunk), "UNK%02X", reason); - eu = nouveau_enum_find(nve0_fifo_fault_engine, unit); + eu = nvkm_enum_find(gk104_fifo_fault_engine, unit); if (eu) { switch (eu->data2) { case NVDEV_SUBDEV_BAR: @@ -753,9 +744,9 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) nv_mask(priv, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nouveau_engine(priv, eu->data2); + engine = nvkm_engine(priv, eu->data2); if (engine) - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); break; } } else { @@ -763,9 +754,9 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) } if (hub) { - ec = nouveau_enum_find(nve0_fifo_fault_hubclient, client); + ec = nvkm_enum_find(gk104_fifo_fault_hubclient, client); } else { - ec = nouveau_enum_find(nve0_fifo_fault_gpcclient, client); + ec = nvkm_enum_find(gk104_fifo_fault_gpcclient, client); snprintf(gpcid, sizeof(gpcid), "%d", gpc); } @@ -777,22 +768,22 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) (u64)vahi << 32 | valo, er ? er->name : erunk, eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", ec ? ec->name : ecunk, (u64)inst << 12, - nouveau_client_name(engctx)); + nvkm_client_name(engctx)); object = engctx; while (object) { switch (nv_mclass(object)) { case KEPLER_CHANNEL_GPFIFO_A: - nve0_fifo_recover(priv, engine, (void *)object); + gk104_fifo_recover(priv, engine, (void *)object); break; } object = object->parent; } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } -static const struct nouveau_bitfield nve0_fifo_pbdma_intr_0[] = { +static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { { 0x00000001, "MEMREQ" }, { 0x00000002, "MEMACK_TIMEOUT" }, { 0x00000004, "MEMACK_EXTRA" }, @@ -827,7 +818,7 @@ static const struct nouveau_bitfield nve0_fifo_pbdma_intr_0[] = { }; static void -nve0_fifo_intr_pbdma_0(struct nve0_fifo_priv *priv, int unit) +gk104_fifo_intr_pbdma_0(struct gk104_fifo_priv *priv, int unit) { u32 mask = nv_rd32(priv, 0x04010c + (unit * 0x2000)); u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)) & mask; @@ -839,26 +830,26 @@ nve0_fifo_intr_pbdma_0(struct nve0_fifo_priv *priv, int unit) u32 show = stat; if (stat & 0x00800000) { - if (!nve0_fifo_swmthd(priv, chid, mthd, data)) + if (!gk104_fifo_swmthd(priv, chid, mthd, data)) show &= ~0x00800000; nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); } if (show) { nv_error(priv, "PBDMA%d:", unit); - nouveau_bitfield_print(nve0_fifo_pbdma_intr_0, show); + nvkm_bitfield_print(gk104_fifo_pbdma_intr_0, show); pr_cont("\n"); nv_error(priv, "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", unit, chid, - nouveau_client_name_for_fifo_chid(&priv->base, chid), + nvkm_client_name_for_fifo_chid(&priv->base, chid), subc, mthd, data); } nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); } -static const struct nouveau_bitfield nve0_fifo_pbdma_intr_1[] = { +static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = { { 0x00000001, "HCE_RE_ILLEGAL_OP" }, { 0x00000002, "HCE_RE_ALIGNB" }, { 0x00000004, "HCE_PRIV" }, @@ -868,7 +859,7 @@ static const struct nouveau_bitfield nve0_fifo_pbdma_intr_1[] = { }; static void -nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit) +gk104_fifo_intr_pbdma_1(struct gk104_fifo_priv *priv, int unit) { u32 mask = nv_rd32(priv, 0x04014c + (unit * 0x2000)); u32 stat = nv_rd32(priv, 0x040148 + (unit * 0x2000)) & mask; @@ -876,7 +867,7 @@ nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit) if (stat) { nv_error(priv, "PBDMA%d:", unit); - nouveau_bitfield_print(nve0_fifo_pbdma_intr_1, stat); + nvkm_bitfield_print(gk104_fifo_pbdma_intr_1, stat); pr_cont("\n"); nv_error(priv, "PBDMA%d: ch %d %08x %08x\n", unit, chid, nv_rd32(priv, 0x040150 + (unit * 0x2000)), @@ -887,7 +878,7 @@ nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit) } static void -nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv) +gk104_fifo_intr_runlist(struct gk104_fifo_priv *priv) { u32 mask = nv_rd32(priv, 0x002a00); while (mask) { @@ -899,20 +890,20 @@ nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv) } static void -nve0_fifo_intr_engine(struct nve0_fifo_priv *priv) +gk104_fifo_intr_engine(struct gk104_fifo_priv *priv) { - nouveau_fifo_uevent(&priv->base); + nvkm_fifo_uevent(&priv->base); } static void -nve0_fifo_intr(struct nouveau_subdev *subdev) +gk104_fifo_intr(struct nvkm_subdev *subdev) { - struct nve0_fifo_priv *priv = (void *)subdev; + struct gk104_fifo_priv *priv = (void *)subdev; u32 mask = nv_rd32(priv, 0x002140); u32 stat = nv_rd32(priv, 0x002100) & mask; if (stat & 0x00000001) { - nve0_fifo_intr_bind(priv); + gk104_fifo_intr_bind(priv); nv_wr32(priv, 0x002100, 0x00000001); stat &= ~0x00000001; } @@ -924,13 +915,13 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x00000100) { - nve0_fifo_intr_sched(priv); + gk104_fifo_intr_sched(priv); nv_wr32(priv, 0x002100, 0x00000100); stat &= ~0x00000100; } if (stat & 0x00010000) { - nve0_fifo_intr_chsw(priv); + gk104_fifo_intr_chsw(priv); nv_wr32(priv, 0x002100, 0x00010000); stat &= ~0x00010000; } @@ -948,7 +939,7 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x08000000) { - nve0_fifo_intr_dropped_fault(priv); + gk104_fifo_intr_dropped_fault(priv); nv_wr32(priv, 0x002100, 0x08000000); stat &= ~0x08000000; } @@ -957,7 +948,7 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) u32 mask = nv_rd32(priv, 0x00259c); while (mask) { u32 unit = __ffs(mask); - nve0_fifo_intr_fault(priv, unit); + gk104_fifo_intr_fault(priv, unit); nv_wr32(priv, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } @@ -968,8 +959,8 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) u32 mask = nv_rd32(priv, 0x0025a0); while (mask) { u32 unit = __ffs(mask); - nve0_fifo_intr_pbdma_0(priv, unit); - nve0_fifo_intr_pbdma_1(priv, unit); + gk104_fifo_intr_pbdma_0(priv, unit); + gk104_fifo_intr_pbdma_1(priv, unit); nv_wr32(priv, 0x0025a0, (1 << unit)); mask &= ~(1 << unit); } @@ -977,13 +968,13 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x40000000) { - nve0_fifo_intr_runlist(priv); + gk104_fifo_intr_runlist(priv); stat &= ~0x40000000; } if (stat & 0x80000000) { nv_wr32(priv, 0x002100, 0x80000000); - nve0_fifo_intr_engine(priv); + gk104_fifo_intr_engine(priv); stat &= ~0x80000000; } @@ -995,33 +986,33 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) } static void -nve0_fifo_uevent_init(struct nvkm_event *event, int type, int index) +gk104_fifo_uevent_init(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x80000000, 0x80000000); } static void -nve0_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); } static const struct nvkm_event_func -nve0_fifo_uevent_func = { - .ctor = nouveau_fifo_uevent_ctor, - .init = nve0_fifo_uevent_init, - .fini = nve0_fifo_uevent_fini, +gk104_fifo_uevent_func = { + .ctor = nvkm_fifo_uevent_ctor, + .init = gk104_fifo_uevent_init, + .fini = gk104_fifo_uevent_fini, }; int -nve0_fifo_fini(struct nouveau_object *object, bool suspend) +gk104_fifo_fini(struct nvkm_object *object, bool suspend) { - struct nve0_fifo_priv *priv = (void *)object; + struct gk104_fifo_priv *priv = (void *)object; int ret; - ret = nouveau_fifo_fini(&priv->base, suspend); + ret = nvkm_fifo_fini(&priv->base, suspend); if (ret) return ret; @@ -1031,12 +1022,12 @@ nve0_fifo_fini(struct nouveau_object *object, bool suspend) } int -nve0_fifo_init(struct nouveau_object *object) +gk104_fifo_init(struct nvkm_object *object) { - struct nve0_fifo_priv *priv = (void *)object; + struct gk104_fifo_priv *priv = (void *)object; int ret, i; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -1066,82 +1057,82 @@ nve0_fifo_init(struct nouveau_object *object) } void -nve0_fifo_dtor(struct nouveau_object *object) +gk104_fifo_dtor(struct nvkm_object *object) { - struct nve0_fifo_priv *priv = (void *)object; + struct gk104_fifo_priv *priv = (void *)object; int i; - nouveau_gpuobj_unmap(&priv->user.bar); - nouveau_gpuobj_ref(NULL, &priv->user.mem); + nvkm_gpuobj_unmap(&priv->user.bar); + nvkm_gpuobj_ref(NULL, &priv->user.mem); for (i = 0; i < FIFO_ENGINE_NR; i++) { - nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[1]); - nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[0]); + nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[1]); + nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[0]); } - nouveau_fifo_destroy(&priv->base); + nvkm_fifo_destroy(&priv->base); } int -nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_fifo_impl *impl = (void *)oclass; - struct nve0_fifo_priv *priv; + struct gk104_fifo_impl *impl = (void *)oclass; + struct gk104_fifo_priv *priv; int ret, i; - ret = nouveau_fifo_create(parent, engine, oclass, 0, - impl->channels - 1, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, + impl->channels - 1, &priv); *pobject = nv_object(priv); if (ret) return ret; - INIT_WORK(&priv->fault, nve0_fifo_recover_work); + INIT_WORK(&priv->fault, gk104_fifo_recover_work); for (i = 0; i < FIFO_ENGINE_NR; i++) { - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, - 0, &priv->engine[i].runlist[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, + 0, &priv->engine[i].runlist[0]); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, - 0, &priv->engine[i].runlist[1]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, + 0, &priv->engine[i].runlist[1]); if (ret) return ret; init_waitqueue_head(&priv->engine[i].wait); } - ret = nouveau_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); if (ret) return ret; - ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, - &priv->user.bar); + ret = nvkm_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, + &priv->user.bar); if (ret) return ret; - ret = nvkm_event_init(&nve0_fifo_uevent_func, 1, 1, &priv->base.uevent); + ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &priv->base.uevent); if (ret) return ret; nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nve0_fifo_intr; - nv_engine(priv)->cclass = &nve0_fifo_cclass; - nv_engine(priv)->sclass = nve0_fifo_sclass; + nv_subdev(priv)->intr = gk104_fifo_intr; + nv_engine(priv)->cclass = &gk104_fifo_cclass; + nv_engine(priv)->sclass = gk104_fifo_sclass; return 0; } -struct nouveau_oclass * -nve0_fifo_oclass = &(struct nve0_fifo_impl) { +struct nvkm_oclass * +gk104_fifo_oclass = &(struct gk104_fifo_impl) { .base.handle = NV_ENGINE(FIFO, 0xe0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_fifo_ctor, - .dtor = nve0_fifo_dtor, - .init = nve0_fifo_init, - .fini = nve0_fifo_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_fifo_ctor, + .dtor = gk104_fifo_dtor, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, }, .channels = 4096, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h new file mode 100644 index 000000000000..3046e00ed6ba --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -0,0 +1,16 @@ +#ifndef __NVKM_FIFO_NVE0_H__ +#define __NVKM_FIFO_NVE0_H__ +#include <engine/fifo.h> + +int gk104_fifo_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gk104_fifo_dtor(struct nvkm_object *); +int gk104_fifo_init(struct nvkm_object *); +int gk104_fifo_fini(struct nvkm_object *, bool); + +struct gk104_fifo_impl { + struct nvkm_oclass base; + u32 channels; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c index 09362a51ba57..927092217a06 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c @@ -21,17 +21,16 @@ * * Authors: Ben Skeggs */ +#include "gk104.h" -#include "nve0.h" - -struct nouveau_oclass * -nv108_fifo_oclass = &(struct nve0_fifo_impl) { +struct nvkm_oclass * +gk208_fifo_oclass = &(struct gk104_fifo_impl) { .base.handle = NV_ENGINE(FIFO, 0x08), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_fifo_ctor, - .dtor = nve0_fifo_dtor, - .init = nve0_fifo_init, - .fini = _nouveau_fifo_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_fifo_ctor, + .dtor = gk104_fifo_dtor, + .init = gk104_fifo_init, + .fini = _nvkm_fifo_fini, }, .channels = 1024, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c index 327456eae963..b30dc87a1357 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c @@ -19,17 +19,16 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#include "gk104.h" -#include "nve0.h" - -struct nouveau_oclass * -gk20a_fifo_oclass = &(struct nve0_fifo_impl) { +struct nvkm_oclass * +gk20a_fifo_oclass = &(struct gk104_fifo_impl) { .base.handle = NV_ENGINE(FIFO, 0xea), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_fifo_ctor, - .dtor = nve0_fifo_dtor, - .init = nve0_fifo_init, - .fini = nve0_fifo_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_fifo_ctor, + .dtor = gk104_fifo_dtor, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, }, .channels = 128, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index 1931057f9962..b038b6eb51db 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -21,24 +21,18 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> +#include <core/device.h> #include <core/engctx.h> -#include <core/namedb.h> #include <core/handle.h> #include <core/ramht.h> -#include <core/event.h> - -#include <subdev/instmem.h> #include <subdev/instmem/nv04.h> #include <subdev/timer.h> -#include <subdev/fb.h> -#include <engine/fifo.h> - -#include "nv04.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static struct ramfc_desc nv04_ramfc[] = { @@ -58,8 +52,8 @@ nv04_ramfc[] = { ******************************************************************************/ int -nv04_fifo_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 handle) +nv04_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) { struct nv04_fifo_priv *priv = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; @@ -90,33 +84,33 @@ nv04_fifo_object_attach(struct nouveau_object *parent, context |= chid << 24; mutex_lock(&nv_subdev(priv)->mutex); - ret = nouveau_ramht_insert(priv->ramht, chid, handle, context); + ret = nvkm_ramht_insert(priv->ramht, chid, handle, context); mutex_unlock(&nv_subdev(priv)->mutex); return ret; } void -nv04_fifo_object_detach(struct nouveau_object *parent, int cookie) +nv04_fifo_object_detach(struct nvkm_object *parent, int cookie) { struct nv04_fifo_priv *priv = (void *)parent->engine; mutex_lock(&nv_subdev(priv)->mutex); - nouveau_ramht_remove(priv->ramht, cookie); + nvkm_ramht_remove(priv->ramht, cookie); mutex_unlock(&nv_subdev(priv)->mutex); } int -nv04_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +nv04_fifo_context_attach(struct nvkm_object *parent, + struct nvkm_object *object) { - nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid; + nv_engctx(object)->addr = nvkm_fifo_chan(parent)->chid; return 0; } static int -nv04_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_fifo_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; @@ -133,11 +127,11 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, + 0x10000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -163,7 +157,7 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, } void -nv04_fifo_chan_dtor(struct nouveau_object *object) +nv04_fifo_chan_dtor(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object->engine; struct nv04_fifo_chan *chan = (void *)object; @@ -173,11 +167,11 @@ nv04_fifo_chan_dtor(struct nouveau_object *object) nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000); } while ((++c)->bits); - nouveau_fifo_channel_destroy(&chan->base); + nvkm_fifo_channel_destroy(&chan->base); } int -nv04_fifo_chan_init(struct nouveau_object *object) +nv04_fifo_chan_init(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object->engine; struct nv04_fifo_chan *chan = (void *)object; @@ -185,7 +179,7 @@ nv04_fifo_chan_init(struct nouveau_object *object) unsigned long flags; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -196,11 +190,11 @@ nv04_fifo_chan_init(struct nouveau_object *object) } int -nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend) +nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend) { struct nv04_fifo_priv *priv = (void *)object->engine; struct nv04_fifo_chan *chan = (void *)object; - struct nouveau_gpuobj *fctx = priv->ramfc; + struct nvkm_gpuobj *fctx = priv->ramfc; struct ramfc_desc *c; unsigned long flags; u32 data = chan->ramfc; @@ -243,22 +237,22 @@ nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend) nv_wr32(priv, NV03_PFIFO_CACHES, 1); spin_unlock_irqrestore(&priv->base.lock, flags); - return nouveau_fifo_channel_fini(&chan->base, suspend); + return nvkm_fifo_channel_fini(&chan->base, suspend); } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv04_fifo_ofuncs = { .ctor = nv04_fifo_chan_ctor, .dtor = nv04_fifo_chan_dtor, .init = nv04_fifo_chan_init, .fini = nv04_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv04_fifo_sclass[] = { { NV03_CHANNEL_DMA, &nv04_fifo_ofuncs }, {} @@ -269,16 +263,16 @@ nv04_fifo_sclass[] = { ******************************************************************************/ int -nv04_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_fifo_context_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_HEAP, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, + 0x1000, NVOBJ_FLAG_HEAP, &base); *pobject = nv_object(base); if (ret) return ret; @@ -286,16 +280,16 @@ nv04_fifo_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass +static struct nvkm_oclass nv04_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_context_ctor, - .dtor = _nouveau_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .dtor = _nvkm_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -304,7 +298,7 @@ nv04_fifo_cclass = { ******************************************************************************/ void -nv04_fifo_pause(struct nouveau_fifo *pfifo, unsigned long *pflags) +nv04_fifo_pause(struct nvkm_fifo *pfifo, unsigned long *pflags) __acquires(priv->base.lock) { struct nv04_fifo_priv *priv = (void *)pfifo; @@ -337,7 +331,7 @@ __acquires(priv->base.lock) } void -nv04_fifo_start(struct nouveau_fifo *pfifo, unsigned long *pflags) +nv04_fifo_start(struct nvkm_fifo *pfifo, unsigned long *pflags) __releases(priv->base.lock) { struct nv04_fifo_priv *priv = (void *)pfifo; @@ -363,7 +357,7 @@ static bool nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) { struct nv04_fifo_chan *chan = NULL; - struct nouveau_handle *bind; + struct nvkm_handle *bind; const int subc = (addr >> 13) & 0x7; const int mthd = addr & 0x1ffc; bool handled = false; @@ -378,7 +372,7 @@ nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) switch (mthd) { case 0x0000: - bind = nouveau_namedb_get(nv_namedb(chan), data); + bind = nvkm_namedb_get(nv_namedb(chan), data); if (unlikely(!bind)) break; @@ -390,18 +384,18 @@ nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0); } - nouveau_namedb_put(bind); + nvkm_namedb_put(bind); break; default: engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE); if (unlikely(((engine >> (subc * 4)) & 0xf) != 0)) break; - bind = nouveau_namedb_get(nv_namedb(chan), chan->subc[subc]); + bind = nvkm_namedb_get(nv_namedb(chan), chan->subc[subc]); if (likely(bind)) { if (!nv_call(bind->object, mthd, data)) handled = true; - nouveau_namedb_put(bind); + nvkm_namedb_put(bind); } break; } @@ -412,8 +406,8 @@ out: } static void -nv04_fifo_cache_error(struct nouveau_device *device, - struct nv04_fifo_priv *priv, u32 chid, u32 get) +nv04_fifo_cache_error(struct nvkm_device *device, + struct nv04_fifo_priv *priv, u32 chid, u32 get) { u32 mthd, data; int ptr; @@ -435,7 +429,7 @@ nv04_fifo_cache_error(struct nouveau_device *device, if (!nv04_fifo_swmthd(priv, chid, mthd, data)) { const char *client_name = - nouveau_client_name_for_fifo_chid(&priv->base, chid); + nvkm_client_name_for_fifo_chid(&priv->base, chid); nv_error(priv, "CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc, @@ -458,8 +452,8 @@ nv04_fifo_cache_error(struct nouveau_device *device, } static void -nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, - u32 chid) +nv04_fifo_dma_pusher(struct nvkm_device *device, + struct nv04_fifo_priv *priv, u32 chid) { const char *client_name; u32 dma_get = nv_rd32(priv, 0x003244); @@ -467,7 +461,7 @@ nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, u32 push = nv_rd32(priv, 0x003220); u32 state = nv_rd32(priv, 0x003228); - client_name = nouveau_client_name_for_fifo_chid(&priv->base, chid); + client_name = nvkm_client_name_for_fifo_chid(&priv->base, chid); if (device->card_type == NV_50) { u32 ho_get = nv_rd32(priv, 0x003328); @@ -504,9 +498,9 @@ nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, } void -nv04_fifo_intr(struct nouveau_subdev *subdev) +nv04_fifo_intr(struct nvkm_subdev *subdev) { - struct nouveau_device *device = nv_device(subdev); + struct nvkm_device *device = nv_device(subdev); struct nv04_fifo_priv *priv = (void *)subdev; uint32_t status, reassign; int cnt = 0; @@ -552,7 +546,7 @@ nv04_fifo_intr(struct nouveau_subdev *subdev) if (status & 0x40000000) { nv_wr32(priv, 0x002100, 0x40000000); - nouveau_fifo_uevent(&priv->base); + nvkm_fifo_uevent(&priv->base); status &= ~0x40000000; } } @@ -577,22 +571,22 @@ nv04_fifo_intr(struct nouveau_subdev *subdev) } static int -nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_instmem_priv *imem = nv04_instmem(parent); struct nv04_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 15, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &priv); *pobject = nv_object(priv); if (ret) return ret; - nouveau_ramht_ref(imem->ramht, &priv->ramht); - nouveau_gpuobj_ref(imem->ramro, &priv->ramro); - nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); + nvkm_ramht_ref(imem->ramht, &priv->ramht); + nvkm_gpuobj_ref(imem->ramro, &priv->ramro); + nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; @@ -605,22 +599,22 @@ nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } void -nv04_fifo_dtor(struct nouveau_object *object) +nv04_fifo_dtor(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object; - nouveau_gpuobj_ref(NULL, &priv->ramfc); - nouveau_gpuobj_ref(NULL, &priv->ramro); - nouveau_ramht_ref(NULL, &priv->ramht); - nouveau_fifo_destroy(&priv->base); + nvkm_gpuobj_ref(NULL, &priv->ramfc); + nvkm_gpuobj_ref(NULL, &priv->ramro); + nvkm_ramht_ref(NULL, &priv->ramht); + nvkm_fifo_destroy(&priv->base); } int -nv04_fifo_init(struct nouveau_object *object) +nv04_fifo_init(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object; int ret; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -629,7 +623,7 @@ nv04_fifo_init(struct nouveau_object *object) nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | ((priv->ramht->bits - 9) << 16) | - (priv->ramht->base.addr >> 8)); + (priv->ramht->gpuobj.addr >> 8)); nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8); @@ -644,13 +638,13 @@ nv04_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nv04_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv04_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_ctor, .dtor = nv04_fifo_dtor, .init = nv04_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h index 496a4b4fdfaf..e0e0c47cb4ca 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h @@ -1,6 +1,5 @@ #ifndef __NV04_FIFO_H__ #define __NV04_FIFO_H__ - #include <engine/fifo.h> #define NV04_PFIFO_DELAY_0 0x00002040 @@ -141,38 +140,36 @@ struct ramfc_desc { }; struct nv04_fifo_priv { - struct nouveau_fifo base; + struct nvkm_fifo base; struct ramfc_desc *ramfc_desc; - struct nouveau_ramht *ramht; - struct nouveau_gpuobj *ramro; - struct nouveau_gpuobj *ramfc; + struct nvkm_ramht *ramht; + struct nvkm_gpuobj *ramro; + struct nvkm_gpuobj *ramfc; }; struct nv04_fifo_base { - struct nouveau_fifo_base base; + struct nvkm_fifo_base base; }; struct nv04_fifo_chan { - struct nouveau_fifo_chan base; + struct nvkm_fifo_chan base; u32 subc[8]; u32 ramfc; }; -int nv04_fifo_object_attach(struct nouveau_object *, - struct nouveau_object *, u32); -void nv04_fifo_object_detach(struct nouveau_object *, int); - -void nv04_fifo_chan_dtor(struct nouveau_object *); -int nv04_fifo_chan_init(struct nouveau_object *); -int nv04_fifo_chan_fini(struct nouveau_object *, bool suspend); +int nv04_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32); +void nv04_fifo_object_detach(struct nvkm_object *, int); -int nv04_fifo_context_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); +void nv04_fifo_chan_dtor(struct nvkm_object *); +int nv04_fifo_chan_init(struct nvkm_object *); +int nv04_fifo_chan_fini(struct nvkm_object *, bool suspend); -void nv04_fifo_dtor(struct nouveau_object *); -int nv04_fifo_init(struct nouveau_object *); -void nv04_fifo_pause(struct nouveau_fifo *, unsigned long *); -void nv04_fifo_start(struct nouveau_fifo *, unsigned long *); +int nv04_fifo_context_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nv04_fifo_dtor(struct nvkm_object *); +int nv04_fifo_init(struct nvkm_object *); +void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); +void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c index 2a32add51c81..48ce4af6f543 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c @@ -21,20 +21,15 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/engctx.h> #include <core/ramht.h> - -#include <subdev/instmem.h> #include <subdev/instmem/nv04.h> -#include <subdev/fb.h> -#include <engine/fifo.h> - -#include "nv04.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static struct ramfc_desc nv10_ramfc[] = { @@ -55,10 +50,10 @@ nv10_ramfc[] = { ******************************************************************************/ static int -nv10_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_fifo_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; @@ -75,11 +70,11 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, + 0x10000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -104,19 +99,19 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv10_fifo_ofuncs = { .ctor = nv10_fifo_chan_ctor, .dtor = nv04_fifo_chan_dtor, .init = nv04_fifo_chan_init, .fini = nv04_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv10_fifo_sclass[] = { { NV10_CHANNEL_DMA, &nv10_fifo_ofuncs }, {} @@ -126,16 +121,16 @@ nv10_fifo_sclass[] = { * FIFO context - basically just the instmem reserved for the channel ******************************************************************************/ -static struct nouveau_oclass +static struct nvkm_oclass nv10_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_context_ctor, - .dtor = _nouveau_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .dtor = _nvkm_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -144,22 +139,22 @@ nv10_fifo_cclass = { ******************************************************************************/ static int -nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_instmem_priv *imem = nv04_instmem(parent); struct nv04_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); *pobject = nv_object(priv); if (ret) return ret; - nouveau_ramht_ref(imem->ramht, &priv->ramht); - nouveau_gpuobj_ref(imem->ramro, &priv->ramro); - nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); + nvkm_ramht_ref(imem->ramht, &priv->ramht); + nvkm_gpuobj_ref(imem->ramro, &priv->ramro); + nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; @@ -171,13 +166,13 @@ nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * -nv10_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv10_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv10_fifo_ctor, .dtor = nv04_fifo_dtor, .init = nv04_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c index 12d76c8adb23..4a20a6fd3887 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c @@ -21,20 +21,15 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> #include <core/engctx.h> #include <core/ramht.h> - -#include <subdev/instmem.h> #include <subdev/instmem/nv04.h> -#include <subdev/fb.h> -#include <engine/fifo.h> - -#include "nv04.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static struct ramfc_desc nv17_ramfc[] = { @@ -60,10 +55,10 @@ nv17_ramfc[] = { ******************************************************************************/ static int -nv17_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv17_fifo_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; @@ -80,13 +75,13 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ - &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, + 0x10000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ + &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -111,19 +106,19 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv17_fifo_ofuncs = { .ctor = nv17_fifo_chan_ctor, .dtor = nv04_fifo_chan_dtor, .init = nv04_fifo_chan_init, .fini = nv04_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv17_fifo_sclass[] = { { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs }, {} @@ -133,16 +128,16 @@ nv17_fifo_sclass[] = { * FIFO context - basically just the instmem reserved for the channel ******************************************************************************/ -static struct nouveau_oclass +static struct nvkm_oclass nv17_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x17), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_context_ctor, - .dtor = _nouveau_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .dtor = _nvkm_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -151,22 +146,22 @@ nv17_fifo_cclass = { ******************************************************************************/ static int -nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_instmem_priv *imem = nv04_instmem(parent); struct nv04_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); *pobject = nv_object(priv); if (ret) return ret; - nouveau_ramht_ref(imem->ramht, &priv->ramht); - nouveau_gpuobj_ref(imem->ramro, &priv->ramro); - nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); + nvkm_ramht_ref(imem->ramht, &priv->ramht); + nvkm_gpuobj_ref(imem->ramro, &priv->ramro); + nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; @@ -179,12 +174,12 @@ nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv17_fifo_init(struct nouveau_object *object) +nv17_fifo_init(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object; int ret; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -193,7 +188,7 @@ nv17_fifo_init(struct nouveau_object *object) nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | ((priv->ramht->bits - 9) << 16) | - (priv->ramht->base.addr >> 8)); + (priv->ramht->gpuobj.addr >> 8)); nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000); @@ -208,13 +203,13 @@ nv17_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nv17_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv17_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x17), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv17_fifo_ctor, .dtor = nv04_fifo_dtor, .init = nv17_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 9f49c3a24dc6..5bfc96265f3b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -21,20 +21,17 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" #include <core/client.h> -#include <nvif/unpack.h> -#include <nvif/class.h> +#include <core/device.h> #include <core/engctx.h> #include <core/ramht.h> - -#include <subdev/instmem.h> -#include <subdev/instmem/nv04.h> #include <subdev/fb.h> +#include <subdev/instmem/nv04.h> -#include <engine/fifo.h> - -#include "nv04.h" +#include <nvif/class.h> +#include <nvif/unpack.h> static struct ramfc_desc nv40_ramfc[] = { @@ -68,8 +65,8 @@ nv40_ramfc[] = { ******************************************************************************/ static int -nv40_fifo_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 handle) +nv40_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) { struct nv04_fifo_priv *priv = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; @@ -99,14 +96,13 @@ nv40_fifo_object_attach(struct nouveau_object *parent, context |= chid << 23; mutex_lock(&nv_subdev(priv)->mutex); - ret = nouveau_ramht_insert(priv->ramht, chid, handle, context); + ret = nvkm_ramht_insert(priv->ramht, chid, handle, context); mutex_unlock(&nv_subdev(priv)->mutex); return ret; } static int -nv40_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *engctx) +nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx) { struct nv04_fifo_priv *priv = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; @@ -142,8 +138,8 @@ nv40_fifo_context_attach(struct nouveau_object *parent, } static int -nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *engctx) +nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *engctx) { struct nv04_fifo_priv *priv = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; @@ -178,10 +174,9 @@ nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nv40_fifo_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; @@ -198,12 +193,12 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x1000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x1000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -230,19 +225,19 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv40_fifo_ofuncs = { .ctor = nv40_fifo_chan_ctor, .dtor = nv04_fifo_chan_dtor, .init = nv04_fifo_chan_init, .fini = nv04_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv40_fifo_sclass[] = { { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs }, {} @@ -252,16 +247,16 @@ nv40_fifo_sclass[] = { * FIFO context - basically just the instmem reserved for the channel ******************************************************************************/ -static struct nouveau_oclass +static struct nvkm_oclass nv40_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fifo_context_ctor, - .dtor = _nouveau_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .dtor = _nvkm_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -270,22 +265,22 @@ nv40_fifo_cclass = { ******************************************************************************/ static int -nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_instmem_priv *imem = nv04_instmem(parent); struct nv04_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); *pobject = nv_object(priv); if (ret) return ret; - nouveau_ramht_ref(imem->ramht, &priv->ramht); - nouveau_gpuobj_ref(imem->ramro, &priv->ramro); - nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); + nvkm_ramht_ref(imem->ramht, &priv->ramht); + nvkm_gpuobj_ref(imem->ramro, &priv->ramro); + nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; @@ -298,13 +293,13 @@ nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv40_fifo_init(struct nouveau_object *object) +nv40_fifo_init(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object; - struct nouveau_fb *pfb = nouveau_fb(object); + struct nvkm_fb *pfb = nvkm_fb(object); int ret; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -314,7 +309,7 @@ nv40_fifo_init(struct nouveau_object *object) nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | ((priv->ramht->bits - 9) << 16) | - (priv->ramht->base.addr >> 8)); + (priv->ramht->gpuobj.addr >> 8)); nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); switch (nv_device(priv)->chipset) { @@ -349,13 +344,13 @@ nv40_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nv40_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv40_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_fifo_ctor, .dtor = nv04_fifo_dtor, .init = nv40_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c index 5d1e86bc244c..f25f0fd0655d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c @@ -21,21 +21,18 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "nv04.h" #include <core/client.h> #include <core/engctx.h> #include <core/ramht.h> -#include <nvif/unpack.h> -#include <nvif/class.h> - -#include <subdev/timer.h> #include <subdev/bar.h> +#include <subdev/mmu.h> +#include <subdev/timer.h> -#include <engine/dmaobj.h> -#include <engine/fifo.h> - -#include "nv04.h" -#include "nv50.h" +#include <nvif/class.h> +#include <nvif/unpack.h> /******************************************************************************* * FIFO channel objects @@ -44,8 +41,8 @@ static void nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv) { - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_gpuobj *cur; + struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_gpuobj *cur; int i, p; cur = priv->playlist[priv->cur_playlist]; @@ -72,12 +69,11 @@ nv50_fifo_playlist_update(struct nv50_fifo_priv *priv) } static int -nv50_fifo_context_attach(struct nouveau_object *parent, - struct nouveau_object *object) +nv50_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent->parent; - struct nouveau_gpuobj *ectx = (void *)object; + struct nvkm_gpuobj *ectx = (void *)object; u64 limit = ectx->addr + ectx->size - 1; u64 start = ectx->addr; u32 addr; @@ -103,10 +99,10 @@ nv50_fifo_context_attach(struct nouveau_object *parent, } static int -nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend, - struct nouveau_object *object) +nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_priv *priv = (void *)parent->engine; struct nv50_fifo_base *base = (void *)parent->parent; struct nv50_fifo_chan *chan = (void *)parent; @@ -139,7 +135,7 @@ nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend, nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) { nv_error(priv, "channel %d [%s] unload timeout\n", - chan->base.chid, nouveau_client_name(chan)); + chan->base.chid, nvkm_client_name(chan)); if (suspend) ret = -EBUSY; } @@ -159,8 +155,8 @@ nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend, } static int -nv50_fifo_object_attach(struct nouveau_object *parent, - struct nouveau_object *object, u32 handle) +nv50_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) { struct nv50_fifo_chan *chan = (void *)parent; u32 context; @@ -179,26 +175,25 @@ nv50_fifo_object_attach(struct nouveau_object *parent, return -EINVAL; } - return nouveau_ramht_insert(chan->ramht, 0, handle, context); + return nvkm_ramht_insert(chan->ramht, 0, handle, context); } void -nv50_fifo_object_detach(struct nouveau_object *parent, int cookie) +nv50_fifo_object_detach(struct nvkm_object *parent, int cookie) { struct nv50_fifo_chan *chan = (void *)parent; - nouveau_ramht_remove(chan->ramht, cookie); + nvkm_ramht_remove(chan->ramht, cookie); } static int -nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; int ret; @@ -211,12 +206,12 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -228,8 +223,8 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, nv_parent(chan)->object_attach = nv50_fifo_object_attach; nv_parent(chan)->object_detach = nv50_fifo_object_detach; - ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, - &chan->ramht); + ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, + &chan->ramht); if (ret) return ret; @@ -246,21 +241,20 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, nv_wo32(base->ramfc, 0x7c, 0x30000001); nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->base.node->offset >> 4)); + (chan->ramht->gpuobj.node->offset >> 4)); bar->flush(bar); return 0; } static int -nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; u64 ioffset, ilength; @@ -275,12 +269,12 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, } else return ret; - ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -292,8 +286,8 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, nv_parent(chan)->object_attach = nv50_fifo_object_attach; nv_parent(chan)->object_detach = nv50_fifo_object_detach; - ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, - &chan->ramht); + ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, + &chan->ramht); if (ret) return ret; @@ -310,30 +304,30 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, nv_wo32(base->ramfc, 0x7c, 0x30000001); nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->base.node->offset >> 4)); + (chan->ramht->gpuobj.node->offset >> 4)); bar->flush(bar); return 0; } void -nv50_fifo_chan_dtor(struct nouveau_object *object) +nv50_fifo_chan_dtor(struct nvkm_object *object) { struct nv50_fifo_chan *chan = (void *)object; - nouveau_ramht_ref(NULL, &chan->ramht); - nouveau_fifo_channel_destroy(&chan->base); + nvkm_ramht_ref(NULL, &chan->ramht); + nvkm_fifo_channel_destroy(&chan->base); } static int -nv50_fifo_chan_init(struct nouveau_object *object) +nv50_fifo_chan_init(struct nvkm_object *object) { struct nv50_fifo_priv *priv = (void *)object->engine; struct nv50_fifo_base *base = (void *)object->parent; struct nv50_fifo_chan *chan = (void *)object; - struct nouveau_gpuobj *ramfc = base->ramfc; + struct nvkm_gpuobj *ramfc = base->ramfc; u32 chid = chan->base.chid; int ret; - ret = nouveau_fifo_channel_init(&chan->base); + ret = nvkm_fifo_channel_init(&chan->base); if (ret) return ret; @@ -343,7 +337,7 @@ nv50_fifo_chan_init(struct nouveau_object *object) } int -nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend) +nv50_fifo_chan_fini(struct nvkm_object *object, bool suspend) { struct nv50_fifo_priv *priv = (void *)object->engine; struct nv50_fifo_chan *chan = (void *)object; @@ -354,34 +348,34 @@ nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend) nv50_fifo_playlist_update(priv); nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000); - return nouveau_fifo_channel_fini(&chan->base, suspend); + return nvkm_fifo_channel_fini(&chan->base, suspend); } -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv50_fifo_ofuncs_dma = { .ctor = nv50_fifo_chan_ctor_dma, .dtor = nv50_fifo_chan_dtor, .init = nv50_fifo_chan_init, .fini = nv50_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_ofuncs +static struct nvkm_ofuncs nv50_fifo_ofuncs_ind = { .ctor = nv50_fifo_chan_ctor_ind, .dtor = nv50_fifo_chan_dtor, .init = nv50_fifo_chan_init, .fini = nv50_fifo_chan_fini, - .map = _nouveau_fifo_channel_map, - .rd32 = _nouveau_fifo_channel_rd32, - .wr32 = _nouveau_fifo_channel_wr32, - .ntfy = _nouveau_fifo_channel_ntfy + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy }; -static struct nouveau_oclass +static struct nvkm_oclass nv50_fifo_sclass[] = { { NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma }, { NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind }, @@ -393,36 +387,35 @@ nv50_fifo_sclass[] = { ******************************************************************************/ static int -nv50_fifo_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_fifo_base *base; int ret; - ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000, - 0x1000, NVOBJ_FLAG_HEAP, &base); + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, + 0x1000, NVOBJ_FLAG_HEAP, &base); *pobject = nv_object(base); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0, - NVOBJ_FLAG_ZERO_ALLOC, &base->eng); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0, + NVOBJ_FLAG_ZERO_ALLOC, &base->eng); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0, - &base->pgd); + ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0, + &base->pgd); if (ret) return ret; - ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); if (ret) return ret; @@ -430,27 +423,27 @@ nv50_fifo_context_ctor(struct nouveau_object *parent, } void -nv50_fifo_context_dtor(struct nouveau_object *object) +nv50_fifo_context_dtor(struct nvkm_object *object) { struct nv50_fifo_base *base = (void *)object; - nouveau_vm_ref(NULL, &base->vm, base->pgd); - nouveau_gpuobj_ref(NULL, &base->pgd); - nouveau_gpuobj_ref(NULL, &base->eng); - nouveau_gpuobj_ref(NULL, &base->ramfc); - nouveau_gpuobj_ref(NULL, &base->cache); - nouveau_fifo_context_destroy(&base->base); + nvkm_vm_ref(NULL, &base->vm, base->pgd); + nvkm_gpuobj_ref(NULL, &base->pgd); + nvkm_gpuobj_ref(NULL, &base->eng); + nvkm_gpuobj_ref(NULL, &base->ramfc); + nvkm_gpuobj_ref(NULL, &base->cache); + nvkm_fifo_context_destroy(&base->base); } -static struct nouveau_oclass +static struct nvkm_oclass nv50_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fifo_context_ctor, .dtor = nv50_fifo_context_dtor, - .init = _nouveau_fifo_context_init, - .fini = _nouveau_fifo_context_fini, - .rd32 = _nouveau_fifo_context_rd32, - .wr32 = _nouveau_fifo_context_wr32, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, }, }; @@ -459,25 +452,25 @@ nv50_fifo_cclass = { ******************************************************************************/ static int -nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_fifo_priv *priv; int ret; - ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv); + ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, + &priv->playlist[0]); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[1]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, + &priv->playlist[1]); if (ret) return ret; @@ -491,23 +484,23 @@ nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } void -nv50_fifo_dtor(struct nouveau_object *object) +nv50_fifo_dtor(struct nvkm_object *object) { struct nv50_fifo_priv *priv = (void *)object; - nouveau_gpuobj_ref(NULL, &priv->playlist[1]); - nouveau_gpuobj_ref(NULL, &priv->playlist[0]); + nvkm_gpuobj_ref(NULL, &priv->playlist[1]); + nvkm_gpuobj_ref(NULL, &priv->playlist[0]); - nouveau_fifo_destroy(&priv->base); + nvkm_fifo_destroy(&priv->base); } int -nv50_fifo_init(struct nouveau_object *object) +nv50_fifo_init(struct nvkm_object *object) { struct nv50_fifo_priv *priv = (void *)object; int ret, i; - ret = nouveau_fifo_init(&priv->base); + ret = nvkm_fifo_init(&priv->base); if (ret) return ret; @@ -529,13 +522,13 @@ nv50_fifo_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nv50_fifo_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv50_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fifo_ctor, .dtor = nv50_fifo_dtor, .init = nv50_fifo_init, - .fini = _nouveau_fifo_fini, + .fini = _nvkm_fifo_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h new file mode 100644 index 000000000000..09ed93c66567 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h @@ -0,0 +1,36 @@ +#ifndef __NV50_FIFO_H__ +#define __NV50_FIFO_H__ +#include <engine/fifo.h> + +struct nv50_fifo_priv { + struct nvkm_fifo base; + struct nvkm_gpuobj *playlist[2]; + int cur_playlist; +}; + +struct nv50_fifo_base { + struct nvkm_fifo_base base; + struct nvkm_gpuobj *ramfc; + struct nvkm_gpuobj *cache; + struct nvkm_gpuobj *eng; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +struct nv50_fifo_chan { + struct nvkm_fifo_chan base; + u32 subc[8]; + struct nvkm_ramht *ramht; +}; + +void nv50_fifo_playlist_update(struct nv50_fifo_priv *); + +void nv50_fifo_object_detach(struct nvkm_object *, int); +void nv50_fifo_chan_dtor(struct nvkm_object *); +int nv50_fifo_chan_fini(struct nvkm_object *, bool); + +void nv50_fifo_context_dtor(struct nvkm_object *); + +void nv50_fifo_dtor(struct nvkm_object *); +int nv50_fifo_init(struct nvkm_object *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild new file mode 100644 index 000000000000..1771d944591b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild @@ -0,0 +1,36 @@ +nvkm-y += nvkm/engine/gr/ctxnv40.o +nvkm-y += nvkm/engine/gr/ctxnv50.o +nvkm-y += nvkm/engine/gr/ctxgf100.o +nvkm-y += nvkm/engine/gr/ctxgf108.o +nvkm-y += nvkm/engine/gr/ctxgf104.o +nvkm-y += nvkm/engine/gr/ctxgf110.o +nvkm-y += nvkm/engine/gr/ctxgf117.o +nvkm-y += nvkm/engine/gr/ctxgf119.o +nvkm-y += nvkm/engine/gr/ctxgk104.o +nvkm-y += nvkm/engine/gr/ctxgk20a.o +nvkm-y += nvkm/engine/gr/ctxgk110.o +nvkm-y += nvkm/engine/gr/ctxgk110b.o +nvkm-y += nvkm/engine/gr/ctxgk208.o +nvkm-y += nvkm/engine/gr/ctxgm107.o +nvkm-y += nvkm/engine/gr/nv04.o +nvkm-y += nvkm/engine/gr/nv10.o +nvkm-y += nvkm/engine/gr/nv20.o +nvkm-y += nvkm/engine/gr/nv25.o +nvkm-y += nvkm/engine/gr/nv2a.o +nvkm-y += nvkm/engine/gr/nv30.o +nvkm-y += nvkm/engine/gr/nv34.o +nvkm-y += nvkm/engine/gr/nv35.o +nvkm-y += nvkm/engine/gr/nv40.o +nvkm-y += nvkm/engine/gr/nv50.o +nvkm-y += nvkm/engine/gr/gf100.o +nvkm-y += nvkm/engine/gr/gf108.o +nvkm-y += nvkm/engine/gr/gf104.o +nvkm-y += nvkm/engine/gr/gf110.o +nvkm-y += nvkm/engine/gr/gf117.o +nvkm-y += nvkm/engine/gr/gf119.o +nvkm-y += nvkm/engine/gr/gk104.o +nvkm-y += nvkm/engine/gr/gk20a.o +nvkm-y += nvkm/engine/gr/gk110.o +nvkm-y += nvkm/engine/gr/gk110b.o +nvkm-y += nvkm/engine/gr/gk208.o +nvkm-y += nvkm/engine/gr/gm107.o diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index b8e5fe60a1eb..2e7ec389eea7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -21,15 +21,19 @@ * * Authors: Ben Skeggs */ +#include "ctxgf100.h" -#include "ctxnvc0.h" +#include <subdev/bar.h> +#include <subdev/fb.h> +#include <subdev/mc.h> +#include <subdev/timer.h> /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init -nvc0_grctx_init_icmd_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_icmd_0[] = { { 0x001000, 1, 0x01, 0x00000004 }, { 0x0000a9, 1, 0x01, 0x0000ffff }, { 0x000038, 1, 0x01, 0x0fac6881 }, @@ -266,14 +270,14 @@ nvc0_grctx_init_icmd_0[] = { {} }; -const struct nvc0_graph_pack -nvc0_grctx_pack_icmd[] = { - { nvc0_grctx_init_icmd_0 }, +const struct gf100_gr_pack +gf100_grctx_pack_icmd[] = { + { gf100_grctx_init_icmd_0 }, {} }; -static const struct nvc0_graph_init -nvc0_grctx_init_9097_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_9097_0[] = { { 0x000800, 8, 0x40, 0x00000000 }, { 0x000804, 8, 0x40, 0x00000000 }, { 0x000808, 8, 0x40, 0x00000400 }, @@ -575,8 +579,8 @@ nvc0_grctx_init_9097_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_902d_0[] = { +const struct gf100_gr_init +gf100_grctx_init_902d_0[] = { { 0x000200, 1, 0x04, 0x000000cf }, { 0x000204, 1, 0x04, 0x00000001 }, { 0x000208, 1, 0x04, 0x00000020 }, @@ -594,8 +598,8 @@ nvc0_grctx_init_902d_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_9039_0[] = { +const struct gf100_gr_init +gf100_grctx_init_9039_0[] = { { 0x00030c, 3, 0x04, 0x00000000 }, { 0x000320, 1, 0x04, 0x00000000 }, { 0x000238, 2, 0x04, 0x00000000 }, @@ -603,8 +607,8 @@ nvc0_grctx_init_9039_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_90c0_0[] = { +const struct gf100_gr_init +gf100_grctx_init_90c0_0[] = { { 0x00270c, 8, 0x20, 0x00000000 }, { 0x00030c, 1, 0x04, 0x00000001 }, { 0x001944, 1, 0x04, 0x00000000 }, @@ -621,23 +625,23 @@ nvc0_grctx_init_90c0_0[] = { {} }; -const struct nvc0_graph_pack -nvc0_grctx_pack_mthd[] = { - { nvc0_grctx_init_9097_0, 0x9097 }, - { nvc0_grctx_init_902d_0, 0x902d }, - { nvc0_grctx_init_9039_0, 0x9039 }, - { nvc0_grctx_init_90c0_0, 0x90c0 }, +const struct gf100_gr_pack +gf100_grctx_pack_mthd[] = { + { gf100_grctx_init_9097_0, 0x9097 }, + { gf100_grctx_init_902d_0, 0x902d }, + { gf100_grctx_init_9039_0, 0x9039 }, + { gf100_grctx_init_90c0_0, 0x90c0 }, {} }; -const struct nvc0_graph_init -nvc0_grctx_init_main_0[] = { +const struct gf100_gr_init +gf100_grctx_init_main_0[] = { { 0x400204, 2, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_grctx_init_fe_0[] = { +const struct gf100_gr_init +gf100_grctx_init_fe_0[] = { { 0x404004, 11, 0x04, 0x00000000 }, { 0x404044, 1, 0x04, 0x00000000 }, { 0x404094, 13, 0x04, 0x00000000 }, @@ -657,8 +661,8 @@ nvc0_grctx_init_fe_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_pri_0[] = { +const struct gf100_gr_init +gf100_grctx_init_pri_0[] = { { 0x404404, 14, 0x04, 0x00000000 }, { 0x404460, 2, 0x04, 0x00000000 }, { 0x404468, 1, 0x04, 0x00ffffff }, @@ -668,8 +672,8 @@ nvc0_grctx_init_pri_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_memfmt_0[] = { +const struct gf100_gr_init +gf100_grctx_init_memfmt_0[] = { { 0x404604, 1, 0x04, 0x00000015 }, { 0x404608, 1, 0x04, 0x00000000 }, { 0x40460c, 1, 0x04, 0x00002e00 }, @@ -690,8 +694,8 @@ nvc0_grctx_init_memfmt_0[] = { {} }; -static const struct nvc0_graph_init -nvc0_grctx_init_ds_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_ds_0[] = { { 0x405800, 1, 0x04, 0x078000bf }, { 0x405830, 1, 0x04, 0x02180000 }, { 0x405834, 2, 0x04, 0x00000000 }, @@ -702,8 +706,8 @@ nvc0_grctx_init_ds_0[] = { {} }; -static const struct nvc0_graph_init -nvc0_grctx_init_pd_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_pd_0[] = { { 0x406020, 1, 0x04, 0x000103c1 }, { 0x406028, 4, 0x04, 0x00000001 }, { 0x4064a8, 1, 0x04, 0x00000000 }, @@ -712,8 +716,8 @@ nvc0_grctx_init_pd_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_rstr2d_0[] = { +const struct gf100_gr_init +gf100_grctx_init_rstr2d_0[] = { { 0x407804, 1, 0x04, 0x00000023 }, { 0x40780c, 1, 0x04, 0x0a418820 }, { 0x407810, 1, 0x04, 0x062080e6 }, @@ -725,8 +729,8 @@ nvc0_grctx_init_rstr2d_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_scc_0[] = { +const struct gf100_gr_init +gf100_grctx_init_scc_0[] = { { 0x408000, 2, 0x04, 0x00000000 }, { 0x408008, 1, 0x04, 0x00000018 }, { 0x40800c, 2, 0x04, 0x00000000 }, @@ -736,8 +740,8 @@ nvc0_grctx_init_scc_0[] = { {} }; -static const struct nvc0_graph_init -nvc0_grctx_init_be_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_be_0[] = { { 0x408800, 1, 0x04, 0x02802a3c }, { 0x408804, 1, 0x04, 0x00000040 }, { 0x408808, 1, 0x04, 0x0003e00d }, @@ -748,28 +752,28 @@ nvc0_grctx_init_be_0[] = { {} }; -const struct nvc0_graph_pack -nvc0_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvc0_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nvc0_grctx_init_memfmt_0 }, - { nvc0_grctx_init_ds_0 }, - { nvc0_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nvc0_grctx_init_scc_0 }, - { nvc0_grctx_init_be_0 }, +const struct gf100_gr_pack +gf100_grctx_pack_hub[] = { + { gf100_grctx_init_main_0 }, + { gf100_grctx_init_fe_0 }, + { gf100_grctx_init_pri_0 }, + { gf100_grctx_init_memfmt_0 }, + { gf100_grctx_init_ds_0 }, + { gf100_grctx_init_pd_0 }, + { gf100_grctx_init_rstr2d_0 }, + { gf100_grctx_init_scc_0 }, + { gf100_grctx_init_be_0 }, {} }; -const struct nvc0_graph_init -nvc0_grctx_init_gpc_unk_0[] = { +const struct gf100_gr_init +gf100_grctx_init_gpc_unk_0[] = { { 0x418380, 1, 0x04, 0x00000016 }, {} }; -const struct nvc0_graph_init -nvc0_grctx_init_prop_0[] = { +const struct gf100_gr_init +gf100_grctx_init_prop_0[] = { { 0x418400, 1, 0x04, 0x38004e00 }, { 0x418404, 1, 0x04, 0x71e0ffff }, { 0x418408, 1, 0x04, 0x00000000 }, @@ -782,8 +786,8 @@ nvc0_grctx_init_prop_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_gpc_unk_1[] = { +const struct gf100_gr_init +gf100_grctx_init_gpc_unk_1[] = { { 0x418600, 1, 0x04, 0x0000001f }, { 0x418684, 1, 0x04, 0x0000000f }, { 0x418700, 1, 0x04, 0x00000002 }, @@ -794,8 +798,8 @@ nvc0_grctx_init_gpc_unk_1[] = { {} }; -static const struct nvc0_graph_init -nvc0_grctx_init_setup_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_setup_0[] = { { 0x418800, 1, 0x04, 0x0006860a }, { 0x418808, 3, 0x04, 0x00000000 }, { 0x418828, 1, 0x04, 0x00008442 }, @@ -807,8 +811,8 @@ nvc0_grctx_init_setup_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_zcull_0[] = { +const struct gf100_gr_init +gf100_grctx_init_zcull_0[] = { { 0x41891c, 1, 0x04, 0x00ff00ff }, { 0x418924, 1, 0x04, 0x00000000 }, { 0x418928, 1, 0x04, 0x00ffff00 }, @@ -816,8 +820,8 @@ nvc0_grctx_init_zcull_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_crstr_0[] = { +const struct gf100_gr_init +gf100_grctx_init_crstr_0[] = { { 0x418b00, 1, 0x04, 0x00000000 }, { 0x418b08, 1, 0x04, 0x0a418820 }, { 0x418b0c, 1, 0x04, 0x062080e6 }, @@ -829,8 +833,8 @@ nvc0_grctx_init_crstr_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_gpm_0[] = { +const struct gf100_gr_init +gf100_grctx_init_gpm_0[] = { { 0x418c08, 1, 0x04, 0x00000001 }, { 0x418c10, 8, 0x04, 0x00000000 }, { 0x418c80, 1, 0x04, 0x20200004 }, @@ -838,29 +842,29 @@ nvc0_grctx_init_gpm_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_gcc_0[] = { +const struct gf100_gr_init +gf100_grctx_init_gcc_0[] = { { 0x419000, 1, 0x04, 0x00000780 }, { 0x419004, 2, 0x04, 0x00000000 }, { 0x419014, 1, 0x04, 0x00000004 }, {} }; -const struct nvc0_graph_pack -nvc0_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvc0_grctx_init_prop_0 }, - { nvc0_grctx_init_gpc_unk_1 }, - { nvc0_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvc0_grctx_init_crstr_0 }, - { nvc0_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, +const struct gf100_gr_pack +gf100_grctx_pack_gpc[] = { + { gf100_grctx_init_gpc_unk_0 }, + { gf100_grctx_init_prop_0 }, + { gf100_grctx_init_gpc_unk_1 }, + { gf100_grctx_init_setup_0 }, + { gf100_grctx_init_zcull_0 }, + { gf100_grctx_init_crstr_0 }, + { gf100_grctx_init_gpm_0 }, + { gf100_grctx_init_gcc_0 }, {} }; -static const struct nvc0_graph_init -nvc0_grctx_init_zcullr_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_zcullr_0[] = { { 0x418a00, 3, 0x04, 0x00000000 }, { 0x418a0c, 1, 0x04, 0x00010000 }, { 0x418a10, 3, 0x04, 0x00000000 }, @@ -888,14 +892,14 @@ nvc0_grctx_init_zcullr_0[] = { {} }; -const struct nvc0_graph_pack -nvc0_grctx_pack_zcull[] = { - { nvc0_grctx_init_zcullr_0 }, +const struct gf100_gr_pack +gf100_grctx_pack_zcull[] = { + { gf100_grctx_init_zcullr_0 }, {} }; -const struct nvc0_graph_init -nvc0_grctx_init_pe_0[] = { +const struct gf100_gr_init +gf100_grctx_init_pe_0[] = { { 0x419818, 1, 0x04, 0x00000000 }, { 0x41983c, 1, 0x04, 0x00038bc7 }, { 0x419848, 1, 0x04, 0x00000000 }, @@ -904,8 +908,8 @@ nvc0_grctx_init_pe_0[] = { {} }; -static const struct nvc0_graph_init -nvc0_grctx_init_tex_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_tex_0[] = { { 0x419a00, 1, 0x04, 0x000001f0 }, { 0x419a04, 1, 0x04, 0x00000001 }, { 0x419a08, 1, 0x04, 0x00000023 }, @@ -915,8 +919,8 @@ nvc0_grctx_init_tex_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_wwdx_0[] = { +const struct gf100_gr_init +gf100_grctx_init_wwdx_0[] = { { 0x419b00, 1, 0x04, 0x0a418820 }, { 0x419b04, 1, 0x04, 0x062080e6 }, { 0x419b08, 1, 0x04, 0x020398a4 }, @@ -929,8 +933,8 @@ nvc0_grctx_init_wwdx_0[] = { {} }; -const struct nvc0_graph_init -nvc0_grctx_init_mpc_0[] = { +const struct gf100_gr_init +gf100_grctx_init_mpc_0[] = { { 0x419c00, 1, 0x04, 0x00000002 }, { 0x419c04, 1, 0x04, 0x00000006 }, { 0x419c08, 1, 0x04, 0x00000002 }, @@ -938,23 +942,23 @@ nvc0_grctx_init_mpc_0[] = { {} }; -static const struct nvc0_graph_init -nvc0_grctx_init_l1c_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_l1c_0[] = { { 0x419cb0, 1, 0x04, 0x00060048 }, { 0x419ce8, 1, 0x04, 0x00000000 }, { 0x419cf4, 1, 0x04, 0x00000183 }, {} }; -const struct nvc0_graph_init -nvc0_grctx_init_tpccs_0[] = { +const struct gf100_gr_init +gf100_grctx_init_tpccs_0[] = { { 0x419d20, 1, 0x04, 0x02180000 }, { 0x419d24, 1, 0x04, 0x00001fff }, {} }; -static const struct nvc0_graph_init -nvc0_grctx_init_sm_0[] = { +static const struct gf100_gr_init +gf100_grctx_init_sm_0[] = { { 0x419e04, 3, 0x04, 0x00000000 }, { 0x419e10, 1, 0x04, 0x00000002 }, { 0x419e44, 1, 0x04, 0x001beff2 }, @@ -966,15 +970,15 @@ nvc0_grctx_init_sm_0[] = { {} }; -const struct nvc0_graph_pack -nvc0_grctx_pack_tpc[] = { - { nvc0_grctx_init_pe_0 }, - { nvc0_grctx_init_tex_0 }, - { nvc0_grctx_init_wwdx_0 }, - { nvc0_grctx_init_mpc_0 }, - { nvc0_grctx_init_l1c_0 }, - { nvc0_grctx_init_tpccs_0 }, - { nvc0_grctx_init_sm_0 }, +const struct gf100_gr_pack +gf100_grctx_pack_tpc[] = { + { gf100_grctx_init_pe_0 }, + { gf100_grctx_init_tex_0 }, + { gf100_grctx_init_wwdx_0 }, + { gf100_grctx_init_mpc_0 }, + { gf100_grctx_init_l1c_0 }, + { gf100_grctx_init_tpccs_0 }, + { gf100_grctx_init_sm_0 }, {} }; @@ -983,7 +987,7 @@ nvc0_grctx_pack_tpc[] = { ******************************************************************************/ int -nvc0_grctx_mmio_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access) +gf100_grctx_mmio_data(struct gf100_grctx *info, u32 size, u32 align, u32 access) { if (info->data) { info->buffer[info->buffer_nr] = round_up(info->addr, align); @@ -998,8 +1002,8 @@ nvc0_grctx_mmio_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access) } void -nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data, - int shift, int buffer) +gf100_grctx_mmio_item(struct gf100_grctx *info, u32 addr, u32 data, + int shift, int buffer) { if (info->data) { if (shift >= 0) { @@ -1021,9 +1025,9 @@ nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data, } void -nvc0_grctx_generate_bundle(struct nvc0_grctx *info) +gf100_grctx_generate_bundle(struct gf100_grctx *info) { - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); @@ -1034,9 +1038,9 @@ nvc0_grctx_generate_bundle(struct nvc0_grctx *info) } void -nvc0_grctx_generate_pagepool(struct nvc0_grctx *info) +gf100_grctx_generate_pagepool(struct gf100_grctx *info) { - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); @@ -1047,10 +1051,10 @@ nvc0_grctx_generate_pagepool(struct nvc0_grctx *info) } void -nvc0_grctx_generate_attrib(struct nvc0_grctx *info) +gf100_grctx_generate_attrib(struct gf100_grctx *info) { - struct nvc0_graph_priv *priv = info->priv; - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); + struct gf100_gr_priv *priv = info->priv; + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv); const u32 attrib = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; @@ -1074,12 +1078,12 @@ nvc0_grctx_generate_attrib(struct nvc0_grctx *info) } void -nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv) +gf100_grctx_generate_unkn(struct gf100_gr_priv *priv) { } void -nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv) +gf100_grctx_generate_tpcid(struct gf100_gr_priv *priv) { int gpc, tpc, id; @@ -1100,7 +1104,7 @@ nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv) } void -nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv) +gf100_grctx_generate_r406028(struct gf100_gr_priv *priv) { u32 tmp[GPC_MAX / 8] = {}, i = 0; for (i = 0; i < priv->gpc_nr; i++) @@ -1112,7 +1116,7 @@ nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv) } void -nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv) +gf100_grctx_generate_r4060a8(struct gf100_gr_priv *priv) { u8 tpcnr[GPC_MAX], data[TPC_MAX]; int gpc, tpc, i; @@ -1134,7 +1138,7 @@ nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv) } void -nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) +gf100_grctx_generate_r418bb8(struct gf100_gr_priv *priv) { u32 data[6] = {}, data2[2] = {}; u8 tpcnr[GPC_MAX]; @@ -1192,7 +1196,7 @@ nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) } void -nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) +gf100_grctx_generate_r406800(struct gf100_gr_priv *priv) { u64 tpc_mask = 0, tpc_set = 0; u8 tpcnr[GPC_MAX]; @@ -1225,17 +1229,17 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) } void -nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +gf100_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) { - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); - nvc0_graph_mmio(priv, oclass->hub); - nvc0_graph_mmio(priv, oclass->gpc); - nvc0_graph_mmio(priv, oclass->zcull); - nvc0_graph_mmio(priv, oclass->tpc); - nvc0_graph_mmio(priv, oclass->ppc); + gf100_gr_mmio(priv, oclass->hub); + gf100_gr_mmio(priv, oclass->gpc); + gf100_gr_mmio(priv, oclass->zcull); + gf100_gr_mmio(priv, oclass->tpc); + gf100_gr_mmio(priv, oclass->ppc); nv_wr32(priv, 0x404154, 0x00000000); @@ -1244,32 +1248,32 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) oclass->attrib(info); oclass->unkn(priv); - nvc0_grctx_generate_tpcid(priv); - nvc0_grctx_generate_r406028(priv); - nvc0_grctx_generate_r4060a8(priv); - nvc0_grctx_generate_r418bb8(priv); - nvc0_grctx_generate_r406800(priv); + gf100_grctx_generate_tpcid(priv); + gf100_grctx_generate_r406028(priv); + gf100_grctx_generate_r4060a8(priv); + gf100_grctx_generate_r418bb8(priv); + gf100_grctx_generate_r406800(priv); - nvc0_graph_icmd(priv, oclass->icmd); + gf100_gr_icmd(priv, oclass->icmd); nv_wr32(priv, 0x404154, 0x00000400); - nvc0_graph_mthd(priv, oclass->mthd); - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); + gf100_gr_mthd(priv, oclass->mthd); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); } int -nvc0_grctx_generate(struct nvc0_graph_priv *priv) +gf100_grctx_generate(struct gf100_gr_priv *priv) { - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_gpuobj *chan; - struct nvc0_grctx info; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_gpuobj *chan; + struct gf100_grctx info; int ret, i; /* allocate memory to for a "channel", which we'll use to generate * the default context values */ - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan); if (ret) { nv_error(priv, "failed to allocate channel memory, %d\n", ret); return ret; @@ -1353,34 +1357,34 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) } done: - nouveau_gpuobj_ref(NULL, &chan); + nvkm_gpuobj_ref(NULL, &chan); return ret; } -struct nouveau_oclass * -nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gf100_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nvc0_grctx_generate_main, - .unkn = nvc0_grctx_generate_unkn, - .hub = nvc0_grctx_pack_hub, - .gpc = nvc0_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvc0_grctx_pack_tpc, - .icmd = nvc0_grctx_pack_icmd, - .mthd = nvc0_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, + .main = gf100_grctx_generate_main, + .unkn = gf100_grctx_generate_unkn, + .hub = gf100_grctx_pack_hub, + .gpc = gf100_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gf100_grctx_pack_tpc, + .icmd = gf100_grctx_pack_icmd, + .mthd = gf100_grctx_pack_mthd, + .bundle = gf100_grctx_generate_bundle, .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, + .pagepool = gf100_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvc0_grctx_generate_attrib, + .attrib = gf100_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h new file mode 100644 index 000000000000..1166b1aa1525 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h @@ -0,0 +1,199 @@ +#ifndef __NVKM_GRCTX_NVC0_H__ +#define __NVKM_GRCTX_NVC0_H__ +#include "gf100.h" + +struct gf100_grctx { + struct gf100_gr_priv *priv; + struct gf100_gr_data *data; + struct gf100_gr_mmio *mmio; + int buffer_nr; + u64 buffer[4]; + u64 addr; +}; + +int gf100_grctx_mmio_data(struct gf100_grctx *, u32 size, u32 align, u32 access); +void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int); + +#define mmio_vram(a,b,c,d) gf100_grctx_mmio_data((a), (b), (c), (d)) +#define mmio_refn(a,b,c,d,e) gf100_grctx_mmio_item((a), (b), (c), (d), (e)) +#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1) +#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1) + +struct gf100_grctx_oclass { + struct nvkm_oclass base; + /* main context generation function */ + void (*main)(struct gf100_gr_priv *, struct gf100_grctx *); + /* context-specific modify-on-first-load list generation function */ + void (*unkn)(struct gf100_gr_priv *); + /* mmio context data */ + const struct gf100_gr_pack *hub; + const struct gf100_gr_pack *gpc; + const struct gf100_gr_pack *zcull; + const struct gf100_gr_pack *tpc; + const struct gf100_gr_pack *ppc; + /* indirect context data, generated with icmds/mthds */ + const struct gf100_gr_pack *icmd; + const struct gf100_gr_pack *mthd; + /* bundle circular buffer */ + void (*bundle)(struct gf100_grctx *); + u32 bundle_size; + u32 bundle_min_gpm_fifo_depth; + u32 bundle_token_limit; + /* pagepool */ + void (*pagepool)(struct gf100_grctx *); + u32 pagepool_size; + /* attribute(/alpha) circular buffer */ + void (*attrib)(struct gf100_grctx *); + u32 attrib_nr_max; + u32 attrib_nr; + u32 alpha_nr_max; + u32 alpha_nr; +}; + +static inline const struct gf100_grctx_oclass * +gf100_grctx_impl(struct gf100_gr_priv *priv) +{ + return (void *)nv_engine(priv)->cclass; +} + +extern struct nvkm_oclass *gf100_grctx_oclass; +int gf100_grctx_generate(struct gf100_gr_priv *); +void gf100_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *); +void gf100_grctx_generate_bundle(struct gf100_grctx *); +void gf100_grctx_generate_pagepool(struct gf100_grctx *); +void gf100_grctx_generate_attrib(struct gf100_grctx *); +void gf100_grctx_generate_unkn(struct gf100_gr_priv *); +void gf100_grctx_generate_tpcid(struct gf100_gr_priv *); +void gf100_grctx_generate_r406028(struct gf100_gr_priv *); +void gf100_grctx_generate_r4060a8(struct gf100_gr_priv *); +void gf100_grctx_generate_r418bb8(struct gf100_gr_priv *); +void gf100_grctx_generate_r406800(struct gf100_gr_priv *); + +extern struct nvkm_oclass *gf108_grctx_oclass; +void gf108_grctx_generate_attrib(struct gf100_grctx *); +void gf108_grctx_generate_unkn(struct gf100_gr_priv *); + +extern struct nvkm_oclass *gf104_grctx_oclass; +extern struct nvkm_oclass *gf110_grctx_oclass; + +extern struct nvkm_oclass *gf117_grctx_oclass; +void gf117_grctx_generate_attrib(struct gf100_grctx *); + +extern struct nvkm_oclass *gf119_grctx_oclass; + +extern struct nvkm_oclass *gk104_grctx_oclass; +extern struct nvkm_oclass *gk20a_grctx_oclass; +void gk104_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *); +void gk104_grctx_generate_bundle(struct gf100_grctx *); +void gk104_grctx_generate_pagepool(struct gf100_grctx *); +void gk104_grctx_generate_unkn(struct gf100_gr_priv *); +void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *); + +extern struct nvkm_oclass *gk110_grctx_oclass; +extern struct nvkm_oclass *gk110b_grctx_oclass; +extern struct nvkm_oclass *gk208_grctx_oclass; +extern struct nvkm_oclass *gm107_grctx_oclass; + +/* context init value lists */ + +extern const struct gf100_gr_pack gf100_grctx_pack_icmd[]; + +extern const struct gf100_gr_pack gf100_grctx_pack_mthd[]; +extern const struct gf100_gr_init gf100_grctx_init_902d_0[]; +extern const struct gf100_gr_init gf100_grctx_init_9039_0[]; +extern const struct gf100_gr_init gf100_grctx_init_90c0_0[]; + +extern const struct gf100_gr_pack gf100_grctx_pack_hub[]; +extern const struct gf100_gr_init gf100_grctx_init_main_0[]; +extern const struct gf100_gr_init gf100_grctx_init_fe_0[]; +extern const struct gf100_gr_init gf100_grctx_init_pri_0[]; +extern const struct gf100_gr_init gf100_grctx_init_memfmt_0[]; +extern const struct gf100_gr_init gf100_grctx_init_rstr2d_0[]; +extern const struct gf100_gr_init gf100_grctx_init_scc_0[]; + +extern const struct gf100_gr_pack gf100_grctx_pack_gpc[]; +extern const struct gf100_gr_init gf100_grctx_init_gpc_unk_0[]; +extern const struct gf100_gr_init gf100_grctx_init_prop_0[]; +extern const struct gf100_gr_init gf100_grctx_init_gpc_unk_1[]; +extern const struct gf100_gr_init gf100_grctx_init_zcull_0[]; +extern const struct gf100_gr_init gf100_grctx_init_crstr_0[]; +extern const struct gf100_gr_init gf100_grctx_init_gpm_0[]; +extern const struct gf100_gr_init gf100_grctx_init_gcc_0[]; + +extern const struct gf100_gr_pack gf100_grctx_pack_zcull[]; + +extern const struct gf100_gr_pack gf100_grctx_pack_tpc[]; +extern const struct gf100_gr_init gf100_grctx_init_pe_0[]; +extern const struct gf100_gr_init gf100_grctx_init_wwdx_0[]; +extern const struct gf100_gr_init gf100_grctx_init_mpc_0[]; +extern const struct gf100_gr_init gf100_grctx_init_tpccs_0[]; + +extern const struct gf100_gr_init gf104_grctx_init_tex_0[]; +extern const struct gf100_gr_init gf104_grctx_init_l1c_0[]; +extern const struct gf100_gr_init gf104_grctx_init_sm_0[]; + +extern const struct gf100_gr_init gf108_grctx_init_9097_0[]; + +extern const struct gf100_gr_init gf108_grctx_init_gpm_0[]; + +extern const struct gf100_gr_init gf108_grctx_init_pe_0[]; +extern const struct gf100_gr_init gf108_grctx_init_wwdx_0[]; +extern const struct gf100_gr_init gf108_grctx_init_tpccs_0[]; + +extern const struct gf100_gr_init gf110_grctx_init_9197_0[]; +extern const struct gf100_gr_init gf110_grctx_init_9297_0[]; + +extern const struct gf100_gr_pack gf119_grctx_pack_icmd[]; + +extern const struct gf100_gr_pack gf119_grctx_pack_mthd[]; + +extern const struct gf100_gr_init gf119_grctx_init_fe_0[]; +extern const struct gf100_gr_init gf119_grctx_init_be_0[]; + +extern const struct gf100_gr_init gf119_grctx_init_prop_0[]; +extern const struct gf100_gr_init gf119_grctx_init_gpc_unk_1[]; +extern const struct gf100_gr_init gf119_grctx_init_crstr_0[]; + +extern const struct gf100_gr_init gf119_grctx_init_sm_0[]; + +extern const struct gf100_gr_init gf117_grctx_init_pe_0[]; + +extern const struct gf100_gr_init gf117_grctx_init_wwdx_0[]; + +extern const struct gf100_gr_init gk104_grctx_init_memfmt_0[]; +extern const struct gf100_gr_init gk104_grctx_init_ds_0[]; +extern const struct gf100_gr_init gk104_grctx_init_scc_0[]; + +extern const struct gf100_gr_init gk104_grctx_init_gpm_0[]; + +extern const struct gf100_gr_init gk104_grctx_init_pes_0[]; + +extern const struct gf100_gr_pack gk104_grctx_pack_hub[]; +extern const struct gf100_gr_pack gk104_grctx_pack_gpc[]; +extern const struct gf100_gr_pack gk104_grctx_pack_tpc[]; +extern const struct gf100_gr_pack gk104_grctx_pack_ppc[]; +extern const struct gf100_gr_pack gk104_grctx_pack_icmd[]; +extern const struct gf100_gr_init gk104_grctx_init_a097_0[]; + +extern const struct gf100_gr_pack gk110_grctx_pack_icmd[]; + +extern const struct gf100_gr_pack gk110_grctx_pack_mthd[]; + +extern const struct gf100_gr_pack gk110_grctx_pack_hub[]; +extern const struct gf100_gr_init gk110_grctx_init_pri_0[]; +extern const struct gf100_gr_init gk110_grctx_init_cwd_0[]; + +extern const struct gf100_gr_pack gk110_grctx_pack_gpc[]; +extern const struct gf100_gr_init gk110_grctx_init_gpc_unk_2[]; + +extern const struct gf100_gr_init gk110_grctx_init_tex_0[]; +extern const struct gf100_gr_init gk110_grctx_init_mpc_0[]; +extern const struct gf100_gr_init gk110_grctx_init_l1c_0[]; + +extern const struct gf100_gr_pack gk110_grctx_pack_ppc[]; + +extern const struct gf100_gr_init gk208_grctx_init_rstr2d_0[]; + +extern const struct gf100_gr_init gk208_grctx_init_prop_0[]; +extern const struct gf100_gr_init gk208_grctx_init_crstr_0[]; +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c index 41705c60cc47..c5a8d55e2cac 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c @@ -21,15 +21,14 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "ctxnvc0.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -const struct nvc0_graph_init -nvc4_grctx_init_tex_0[] = { +const struct gf100_gr_init +gf104_grctx_init_tex_0[] = { { 0x419a00, 1, 0x04, 0x000001f0 }, { 0x419a04, 1, 0x04, 0x00000001 }, { 0x419a08, 1, 0x04, 0x00000023 }, @@ -42,16 +41,16 @@ nvc4_grctx_init_tex_0[] = { {} }; -const struct nvc0_graph_init -nvc4_grctx_init_l1c_0[] = { +const struct gf100_gr_init +gf104_grctx_init_l1c_0[] = { { 0x419cb0, 1, 0x04, 0x00020048 }, { 0x419ce8, 1, 0x04, 0x00000000 }, { 0x419cf4, 1, 0x04, 0x00000183 }, {} }; -const struct nvc0_graph_init -nvc4_grctx_init_sm_0[] = { +const struct gf100_gr_init +gf104_grctx_init_sm_0[] = { { 0x419e04, 3, 0x04, 0x00000000 }, { 0x419e10, 1, 0x04, 0x00000002 }, { 0x419e44, 1, 0x04, 0x001beff2 }, @@ -64,15 +63,15 @@ nvc4_grctx_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack -nvc4_grctx_pack_tpc[] = { - { nvc0_grctx_init_pe_0 }, - { nvc4_grctx_init_tex_0 }, - { nvc0_grctx_init_wwdx_0 }, - { nvc0_grctx_init_mpc_0 }, - { nvc4_grctx_init_l1c_0 }, - { nvc0_grctx_init_tpccs_0 }, - { nvc4_grctx_init_sm_0 }, +static const struct gf100_gr_pack +gf104_grctx_pack_tpc[] = { + { gf100_grctx_init_pe_0 }, + { gf104_grctx_init_tex_0 }, + { gf100_grctx_init_wwdx_0 }, + { gf100_grctx_init_mpc_0 }, + { gf104_grctx_init_l1c_0 }, + { gf100_grctx_init_tpccs_0 }, + { gf104_grctx_init_sm_0 }, {} }; @@ -80,30 +79,30 @@ nvc4_grctx_pack_tpc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nouveau_oclass * -nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gf104_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xc3), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nvc0_grctx_generate_main, - .unkn = nvc0_grctx_generate_unkn, - .hub = nvc0_grctx_pack_hub, - .gpc = nvc0_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvc4_grctx_pack_tpc, - .icmd = nvc0_grctx_pack_icmd, - .mthd = nvc0_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, + .main = gf100_grctx_generate_main, + .unkn = gf100_grctx_generate_unkn, + .hub = gf100_grctx_pack_hub, + .gpc = gf100_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gf104_grctx_pack_tpc, + .icmd = gf100_grctx_pack_icmd, + .mthd = gf100_grctx_pack_mthd, + .bundle = gf100_grctx_generate_bundle, .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, + .pagepool = gf100_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvc0_grctx_generate_attrib, + .attrib = gf100_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c index c6ba8fed18f1..87c844a5f34b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c @@ -21,15 +21,16 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "ctxgf100.h" -#include "ctxnvc0.h" +#include <subdev/fb.h> /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init -nvc1_grctx_init_icmd_0[] = { +static const struct gf100_gr_init +gf108_grctx_init_icmd_0[] = { { 0x001000, 1, 0x01, 0x00000004 }, { 0x0000a9, 1, 0x01, 0x0000ffff }, { 0x000038, 1, 0x01, 0x0fac6881 }, @@ -267,14 +268,14 @@ nvc1_grctx_init_icmd_0[] = { {} }; -static const struct nvc0_graph_pack -nvc1_grctx_pack_icmd[] = { - { nvc1_grctx_init_icmd_0 }, +static const struct gf100_gr_pack +gf108_grctx_pack_icmd[] = { + { gf108_grctx_init_icmd_0 }, {} }; -const struct nvc0_graph_init -nvc1_grctx_init_9097_0[] = { +const struct gf100_gr_init +gf108_grctx_init_9097_0[] = { { 0x000800, 8, 0x40, 0x00000000 }, { 0x000804, 8, 0x40, 0x00000000 }, { 0x000808, 8, 0x40, 0x00000400 }, @@ -575,25 +576,25 @@ nvc1_grctx_init_9097_0[] = { {} }; -static const struct nvc0_graph_init -nvc1_grctx_init_9197_0[] = { +static const struct gf100_gr_init +gf108_grctx_init_9197_0[] = { { 0x003400, 128, 0x04, 0x00000000 }, { 0x0002e4, 1, 0x04, 0x0000b001 }, {} }; -static const struct nvc0_graph_pack -nvc1_grctx_pack_mthd[] = { - { nvc1_grctx_init_9097_0, 0x9097 }, - { nvc1_grctx_init_9197_0, 0x9197 }, - { nvc0_grctx_init_902d_0, 0x902d }, - { nvc0_grctx_init_9039_0, 0x9039 }, - { nvc0_grctx_init_90c0_0, 0x90c0 }, +static const struct gf100_gr_pack +gf108_grctx_pack_mthd[] = { + { gf108_grctx_init_9097_0, 0x9097 }, + { gf108_grctx_init_9197_0, 0x9197 }, + { gf100_grctx_init_902d_0, 0x902d }, + { gf100_grctx_init_9039_0, 0x9039 }, + { gf100_grctx_init_90c0_0, 0x90c0 }, {} }; -static const struct nvc0_graph_init -nvc1_grctx_init_ds_0[] = { +static const struct gf100_gr_init +gf108_grctx_init_ds_0[] = { { 0x405800, 1, 0x04, 0x0f8000bf }, { 0x405830, 1, 0x04, 0x02180218 }, { 0x405834, 2, 0x04, 0x00000000 }, @@ -604,8 +605,8 @@ nvc1_grctx_init_ds_0[] = { {} }; -static const struct nvc0_graph_init -nvc1_grctx_init_pd_0[] = { +static const struct gf100_gr_init +gf108_grctx_init_pd_0[] = { { 0x406020, 1, 0x04, 0x000103c1 }, { 0x406028, 4, 0x04, 0x00000001 }, { 0x4064a8, 1, 0x04, 0x00000000 }, @@ -616,8 +617,8 @@ nvc1_grctx_init_pd_0[] = { {} }; -static const struct nvc0_graph_init -nvc1_grctx_init_be_0[] = { +static const struct gf100_gr_init +gf108_grctx_init_be_0[] = { { 0x408800, 1, 0x04, 0x02802a3c }, { 0x408804, 1, 0x04, 0x00000040 }, { 0x408808, 1, 0x04, 0x1003e005 }, @@ -628,22 +629,22 @@ nvc1_grctx_init_be_0[] = { {} }; -static const struct nvc0_graph_pack -nvc1_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvc0_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nvc0_grctx_init_memfmt_0 }, - { nvc1_grctx_init_ds_0 }, - { nvc1_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nvc0_grctx_init_scc_0 }, - { nvc1_grctx_init_be_0 }, +static const struct gf100_gr_pack +gf108_grctx_pack_hub[] = { + { gf100_grctx_init_main_0 }, + { gf100_grctx_init_fe_0 }, + { gf100_grctx_init_pri_0 }, + { gf100_grctx_init_memfmt_0 }, + { gf108_grctx_init_ds_0 }, + { gf108_grctx_init_pd_0 }, + { gf100_grctx_init_rstr2d_0 }, + { gf100_grctx_init_scc_0 }, + { gf108_grctx_init_be_0 }, {} }; -static const struct nvc0_graph_init -nvc1_grctx_init_setup_0[] = { +static const struct gf100_gr_init +gf108_grctx_init_setup_0[] = { { 0x418800, 1, 0x04, 0x0006860a }, { 0x418808, 3, 0x04, 0x00000000 }, { 0x418828, 1, 0x04, 0x00008442 }, @@ -655,8 +656,8 @@ nvc1_grctx_init_setup_0[] = { {} }; -const struct nvc0_graph_init -nvc1_grctx_init_gpm_0[] = { +const struct gf100_gr_init +gf108_grctx_init_gpm_0[] = { { 0x418c08, 1, 0x04, 0x00000001 }, { 0x418c10, 8, 0x04, 0x00000000 }, { 0x418c6c, 1, 0x04, 0x00000001 }, @@ -665,21 +666,21 @@ nvc1_grctx_init_gpm_0[] = { {} }; -static const struct nvc0_graph_pack -nvc1_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvc0_grctx_init_prop_0 }, - { nvc0_grctx_init_gpc_unk_1 }, - { nvc1_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvc0_grctx_init_crstr_0 }, - { nvc1_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, +static const struct gf100_gr_pack +gf108_grctx_pack_gpc[] = { + { gf100_grctx_init_gpc_unk_0 }, + { gf100_grctx_init_prop_0 }, + { gf100_grctx_init_gpc_unk_1 }, + { gf108_grctx_init_setup_0 }, + { gf100_grctx_init_zcull_0 }, + { gf100_grctx_init_crstr_0 }, + { gf108_grctx_init_gpm_0 }, + { gf100_grctx_init_gcc_0 }, {} }; -const struct nvc0_graph_init -nvc1_grctx_init_pe_0[] = { +const struct gf100_gr_init +gf108_grctx_init_pe_0[] = { { 0x419818, 1, 0x04, 0x00000000 }, { 0x41983c, 1, 0x04, 0x00038bc7 }, { 0x419848, 1, 0x04, 0x00000000 }, @@ -688,8 +689,8 @@ nvc1_grctx_init_pe_0[] = { {} }; -const struct nvc0_graph_init -nvc1_grctx_init_wwdx_0[] = { +const struct gf100_gr_init +gf108_grctx_init_wwdx_0[] = { { 0x419b00, 1, 0x04, 0x0a418820 }, { 0x419b04, 1, 0x04, 0x062080e6 }, { 0x419b08, 1, 0x04, 0x020398a4 }, @@ -702,23 +703,23 @@ nvc1_grctx_init_wwdx_0[] = { {} }; -const struct nvc0_graph_init -nvc1_grctx_init_tpccs_0[] = { +const struct gf100_gr_init +gf108_grctx_init_tpccs_0[] = { { 0x419d20, 1, 0x04, 0x12180000 }, { 0x419d24, 1, 0x04, 0x00001fff }, { 0x419d44, 1, 0x04, 0x02180218 }, {} }; -static const struct nvc0_graph_pack -nvc1_grctx_pack_tpc[] = { - { nvc1_grctx_init_pe_0 }, - { nvc4_grctx_init_tex_0 }, - { nvc1_grctx_init_wwdx_0 }, - { nvc0_grctx_init_mpc_0 }, - { nvc4_grctx_init_l1c_0 }, - { nvc1_grctx_init_tpccs_0 }, - { nvc4_grctx_init_sm_0 }, +static const struct gf100_gr_pack +gf108_grctx_pack_tpc[] = { + { gf108_grctx_init_pe_0 }, + { gf104_grctx_init_tex_0 }, + { gf108_grctx_init_wwdx_0 }, + { gf100_grctx_init_mpc_0 }, + { gf104_grctx_init_l1c_0 }, + { gf108_grctx_init_tpccs_0 }, + { gf104_grctx_init_sm_0 }, {} }; @@ -727,10 +728,10 @@ nvc1_grctx_pack_tpc[] = { ******************************************************************************/ void -nvc1_grctx_generate_attrib(struct nvc0_grctx *info) +gf108_grctx_generate_attrib(struct gf100_grctx *info) { - struct nvc0_graph_priv *priv = info->priv; - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); + struct gf100_gr_priv *priv = info->priv; + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv); const u32 alpha = impl->alpha_nr; const u32 beta = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); @@ -764,7 +765,7 @@ nvc1_grctx_generate_attrib(struct nvc0_grctx *info) } void -nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv) +gf108_grctx_generate_unkn(struct gf100_gr_priv *priv) { nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); @@ -774,30 +775,30 @@ nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv) nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); } -struct nouveau_oclass * -nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gf108_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xc1), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nvc0_grctx_generate_main, - .unkn = nvc1_grctx_generate_unkn, - .hub = nvc1_grctx_pack_hub, - .gpc = nvc1_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvc1_grctx_pack_tpc, - .icmd = nvc1_grctx_pack_icmd, - .mthd = nvc1_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, + .main = gf100_grctx_generate_main, + .unkn = gf108_grctx_generate_unkn, + .hub = gf108_grctx_pack_hub, + .gpc = gf108_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gf108_grctx_pack_tpc, + .icmd = gf108_grctx_pack_icmd, + .mthd = gf108_grctx_pack_mthd, + .bundle = gf100_grctx_generate_bundle, .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, + .pagepool = gf100_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvc1_grctx_generate_attrib, + .attrib = gf108_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, .alpha_nr_max = 0x324, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c index 8f804cd8f9c7..b3acd931b978 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c @@ -21,15 +21,14 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "ctxnvc0.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init -nvc8_grctx_init_icmd_0[] = { +static const struct gf100_gr_init +gf110_grctx_init_icmd_0[] = { { 0x001000, 1, 0x01, 0x00000004 }, { 0x0000a9, 1, 0x01, 0x0000ffff }, { 0x000038, 1, 0x01, 0x0fac6881 }, @@ -268,20 +267,20 @@ nvc8_grctx_init_icmd_0[] = { {} }; -static const struct nvc0_graph_pack -nvc8_grctx_pack_icmd[] = { - { nvc8_grctx_init_icmd_0 }, +static const struct gf100_gr_pack +gf110_grctx_pack_icmd[] = { + { gf110_grctx_init_icmd_0 }, {} }; -const struct nvc0_graph_init -nvc8_grctx_init_9197_0[] = { +const struct gf100_gr_init +gf110_grctx_init_9197_0[] = { { 0x0002e4, 1, 0x04, 0x0000b001 }, {} }; -const struct nvc0_graph_init -nvc8_grctx_init_9297_0[] = { +const struct gf100_gr_init +gf110_grctx_init_9297_0[] = { { 0x003400, 128, 0x04, 0x00000000 }, { 0x00036c, 2, 0x04, 0x00000000 }, { 0x0007a4, 2, 0x04, 0x00000000 }, @@ -290,19 +289,19 @@ nvc8_grctx_init_9297_0[] = { {} }; -static const struct nvc0_graph_pack -nvc8_grctx_pack_mthd[] = { - { nvc1_grctx_init_9097_0, 0x9097 }, - { nvc8_grctx_init_9197_0, 0x9197 }, - { nvc8_grctx_init_9297_0, 0x9297 }, - { nvc0_grctx_init_902d_0, 0x902d }, - { nvc0_grctx_init_9039_0, 0x9039 }, - { nvc0_grctx_init_90c0_0, 0x90c0 }, +static const struct gf100_gr_pack +gf110_grctx_pack_mthd[] = { + { gf108_grctx_init_9097_0, 0x9097 }, + { gf110_grctx_init_9197_0, 0x9197 }, + { gf110_grctx_init_9297_0, 0x9297 }, + { gf100_grctx_init_902d_0, 0x902d }, + { gf100_grctx_init_9039_0, 0x9039 }, + { gf100_grctx_init_90c0_0, 0x90c0 }, {} }; -static const struct nvc0_graph_init -nvc8_grctx_init_setup_0[] = { +static const struct gf100_gr_init +gf110_grctx_init_setup_0[] = { { 0x418800, 1, 0x04, 0x0006860a }, { 0x418808, 3, 0x04, 0x00000000 }, { 0x418828, 1, 0x04, 0x00008442 }, @@ -314,16 +313,16 @@ nvc8_grctx_init_setup_0[] = { {} }; -static const struct nvc0_graph_pack -nvc8_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvc0_grctx_init_prop_0 }, - { nvc0_grctx_init_gpc_unk_1 }, - { nvc8_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvc0_grctx_init_crstr_0 }, - { nvc0_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, +static const struct gf100_gr_pack +gf110_grctx_pack_gpc[] = { + { gf100_grctx_init_gpc_unk_0 }, + { gf100_grctx_init_prop_0 }, + { gf100_grctx_init_gpc_unk_1 }, + { gf110_grctx_init_setup_0 }, + { gf100_grctx_init_zcull_0 }, + { gf100_grctx_init_crstr_0 }, + { gf100_grctx_init_gpm_0 }, + { gf100_grctx_init_gcc_0 }, {} }; @@ -331,30 +330,30 @@ nvc8_grctx_pack_gpc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nouveau_oclass * -nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gf110_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xc8), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nvc0_grctx_generate_main, - .unkn = nvc0_grctx_generate_unkn, - .hub = nvc0_grctx_pack_hub, - .gpc = nvc8_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvc0_grctx_pack_tpc, - .icmd = nvc8_grctx_pack_icmd, - .mthd = nvc8_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, + .main = gf100_grctx_generate_main, + .unkn = gf100_grctx_generate_unkn, + .hub = gf100_grctx_pack_hub, + .gpc = gf110_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gf100_grctx_pack_tpc, + .icmd = gf110_grctx_pack_icmd, + .mthd = gf110_grctx_pack_mthd, + .bundle = gf100_grctx_generate_bundle, .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, + .pagepool = gf100_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvc0_grctx_generate_attrib, + .attrib = gf100_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c index fcf534fd9e65..9bbe2c97552e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c @@ -21,15 +21,17 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "ctxgf100.h" -#include "ctxnvc0.h" +#include <subdev/fb.h> +#include <subdev/mc.h> /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init -nvd7_grctx_init_ds_0[] = { +static const struct gf100_gr_init +gf117_grctx_init_ds_0[] = { { 0x405800, 1, 0x04, 0x0f8000bf }, { 0x405830, 1, 0x04, 0x02180324 }, { 0x405834, 1, 0x04, 0x08000000 }, @@ -41,8 +43,8 @@ nvd7_grctx_init_ds_0[] = { {} }; -static const struct nvc0_graph_init -nvd7_grctx_init_pd_0[] = { +static const struct gf100_gr_init +gf117_grctx_init_pd_0[] = { { 0x406020, 1, 0x04, 0x000103c1 }, { 0x406028, 4, 0x04, 0x00000001 }, { 0x4064a8, 1, 0x04, 0x00000000 }, @@ -54,22 +56,22 @@ nvd7_grctx_init_pd_0[] = { {} }; -static const struct nvc0_graph_pack -nvd7_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvd9_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nvc0_grctx_init_memfmt_0 }, - { nvd7_grctx_init_ds_0 }, - { nvd7_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nvc0_grctx_init_scc_0 }, - { nvd9_grctx_init_be_0 }, +static const struct gf100_gr_pack +gf117_grctx_pack_hub[] = { + { gf100_grctx_init_main_0 }, + { gf119_grctx_init_fe_0 }, + { gf100_grctx_init_pri_0 }, + { gf100_grctx_init_memfmt_0 }, + { gf117_grctx_init_ds_0 }, + { gf117_grctx_init_pd_0 }, + { gf100_grctx_init_rstr2d_0 }, + { gf100_grctx_init_scc_0 }, + { gf119_grctx_init_be_0 }, {} }; -static const struct nvc0_graph_init -nvd7_grctx_init_setup_0[] = { +static const struct gf100_gr_init +gf117_grctx_init_setup_0[] = { { 0x418800, 1, 0x04, 0x7006860a }, { 0x418808, 3, 0x04, 0x00000000 }, { 0x418828, 1, 0x04, 0x00008442 }, @@ -81,29 +83,29 @@ nvd7_grctx_init_setup_0[] = { {} }; -static const struct nvc0_graph_pack -nvd7_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvd9_grctx_init_prop_0 }, - { nvd9_grctx_init_gpc_unk_1 }, - { nvd7_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvd9_grctx_init_crstr_0 }, - { nvc1_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, +static const struct gf100_gr_pack +gf117_grctx_pack_gpc[] = { + { gf100_grctx_init_gpc_unk_0 }, + { gf119_grctx_init_prop_0 }, + { gf119_grctx_init_gpc_unk_1 }, + { gf117_grctx_init_setup_0 }, + { gf100_grctx_init_zcull_0 }, + { gf119_grctx_init_crstr_0 }, + { gf108_grctx_init_gpm_0 }, + { gf100_grctx_init_gcc_0 }, {} }; -const struct nvc0_graph_init -nvd7_grctx_init_pe_0[] = { +const struct gf100_gr_init +gf117_grctx_init_pe_0[] = { { 0x419848, 1, 0x04, 0x00000000 }, { 0x419864, 1, 0x04, 0x00000129 }, { 0x419888, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -nvd7_grctx_init_tex_0[] = { +static const struct gf100_gr_init +gf117_grctx_init_tex_0[] = { { 0x419a00, 1, 0x04, 0x000001f0 }, { 0x419a04, 1, 0x04, 0x00000001 }, { 0x419a08, 1, 0x04, 0x00000023 }, @@ -116,8 +118,8 @@ nvd7_grctx_init_tex_0[] = { {} }; -static const struct nvc0_graph_init -nvd7_grctx_init_mpc_0[] = { +static const struct gf100_gr_init +gf117_grctx_init_mpc_0[] = { { 0x419c00, 1, 0x04, 0x0000000a }, { 0x419c04, 1, 0x04, 0x00000006 }, { 0x419c08, 1, 0x04, 0x00000002 }, @@ -127,32 +129,32 @@ nvd7_grctx_init_mpc_0[] = { {} }; -static const struct nvc0_graph_pack -nvd7_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nvd7_grctx_init_tex_0 }, - { nvd7_grctx_init_mpc_0 }, - { nvc4_grctx_init_l1c_0 }, - { nvd9_grctx_init_sm_0 }, +static const struct gf100_gr_pack +gf117_grctx_pack_tpc[] = { + { gf117_grctx_init_pe_0 }, + { gf117_grctx_init_tex_0 }, + { gf117_grctx_init_mpc_0 }, + { gf104_grctx_init_l1c_0 }, + { gf119_grctx_init_sm_0 }, {} }; -static const struct nvc0_graph_init -nvd7_grctx_init_pes_0[] = { +static const struct gf100_gr_init +gf117_grctx_init_pes_0[] = { { 0x41be24, 1, 0x04, 0x00000002 }, {} }; -static const struct nvc0_graph_init -nvd7_grctx_init_cbm_0[] = { +static const struct gf100_gr_init +gf117_grctx_init_cbm_0[] = { { 0x41bec0, 1, 0x04, 0x12180000 }, { 0x41bec4, 1, 0x04, 0x00003fff }, { 0x41bee4, 1, 0x04, 0x03240218 }, {} }; -const struct nvc0_graph_init -nvd7_grctx_init_wwdx_0[] = { +const struct gf100_gr_init +gf117_grctx_init_wwdx_0[] = { { 0x41bf00, 1, 0x04, 0x0a418820 }, { 0x41bf04, 1, 0x04, 0x062080e6 }, { 0x41bf08, 1, 0x04, 0x020398a4 }, @@ -165,11 +167,11 @@ nvd7_grctx_init_wwdx_0[] = { {} }; -static const struct nvc0_graph_pack -nvd7_grctx_pack_ppc[] = { - { nvd7_grctx_init_pes_0 }, - { nvd7_grctx_init_cbm_0 }, - { nvd7_grctx_init_wwdx_0 }, +static const struct gf100_gr_pack +gf117_grctx_pack_ppc[] = { + { gf117_grctx_init_pes_0 }, + { gf117_grctx_init_cbm_0 }, + { gf117_grctx_init_wwdx_0 }, {} }; @@ -178,10 +180,10 @@ nvd7_grctx_pack_ppc[] = { ******************************************************************************/ void -nvd7_grctx_generate_attrib(struct nvc0_grctx *info) +gf117_grctx_generate_attrib(struct gf100_grctx *info) { - struct nvc0_graph_priv *priv = info->priv; - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); + struct gf100_gr_priv *priv = info->priv; + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv); const u32 alpha = impl->alpha_nr; const u32 beta = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); @@ -215,18 +217,18 @@ nvd7_grctx_generate_attrib(struct nvc0_grctx *info) } void -nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +gf117_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) { - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; int i; - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); - nvc0_graph_mmio(priv, oclass->hub); - nvc0_graph_mmio(priv, oclass->gpc); - nvc0_graph_mmio(priv, oclass->zcull); - nvc0_graph_mmio(priv, oclass->tpc); - nvc0_graph_mmio(priv, oclass->ppc); + gf100_gr_mmio(priv, oclass->hub); + gf100_gr_mmio(priv, oclass->gpc); + gf100_gr_mmio(priv, oclass->zcull); + gf100_gr_mmio(priv, oclass->tpc); + gf100_gr_mmio(priv, oclass->ppc); nv_wr32(priv, 0x404154, 0x00000000); @@ -235,46 +237,46 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) oclass->attrib(info); oclass->unkn(priv); - nvc0_grctx_generate_tpcid(priv); - nvc0_grctx_generate_r406028(priv); - nvc0_grctx_generate_r4060a8(priv); - nve4_grctx_generate_r418bb8(priv); - nvc0_grctx_generate_r406800(priv); + gf100_grctx_generate_tpcid(priv); + gf100_grctx_generate_r406028(priv); + gf100_grctx_generate_r4060a8(priv); + gk104_grctx_generate_r418bb8(priv); + gf100_grctx_generate_r406800(priv); for (i = 0; i < 8; i++) nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); - nvc0_graph_icmd(priv, oclass->icmd); + gf100_gr_icmd(priv, oclass->icmd); nv_wr32(priv, 0x404154, 0x00000400); - nvc0_graph_mthd(priv, oclass->mthd); - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); + gf100_gr_mthd(priv, oclass->mthd); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); } -struct nouveau_oclass * -nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gf117_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xd7), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nvd7_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nvd7_grctx_pack_hub, - .gpc = nvd7_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvd7_grctx_pack_tpc, - .ppc = nvd7_grctx_pack_ppc, - .icmd = nvd9_grctx_pack_icmd, - .mthd = nvd9_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, + .main = gf117_grctx_generate_main, + .unkn = gk104_grctx_generate_unkn, + .hub = gf117_grctx_pack_hub, + .gpc = gf117_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gf117_grctx_pack_tpc, + .ppc = gf117_grctx_pack_ppc, + .icmd = gf119_grctx_pack_icmd, + .mthd = gf119_grctx_pack_mthd, + .bundle = gf100_grctx_generate_bundle, .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, + .pagepool = gf100_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, + .attrib = gf117_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c index b9a301b6fd9f..8d8761443809 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c @@ -21,15 +21,14 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "ctxnvc0.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init -nvd9_grctx_init_icmd_0[] = { +static const struct gf100_gr_init +gf119_grctx_init_icmd_0[] = { { 0x001000, 1, 0x01, 0x00000004 }, { 0x0000a9, 1, 0x01, 0x0000ffff }, { 0x000038, 1, 0x01, 0x0fac6881 }, @@ -270,14 +269,14 @@ nvd9_grctx_init_icmd_0[] = { {} }; -const struct nvc0_graph_pack -nvd9_grctx_pack_icmd[] = { - { nvd9_grctx_init_icmd_0 }, +const struct gf100_gr_pack +gf119_grctx_pack_icmd[] = { + { gf119_grctx_init_icmd_0 }, {} }; -static const struct nvc0_graph_init -nvd9_grctx_init_90c0_0[] = { +static const struct gf100_gr_init +gf119_grctx_init_90c0_0[] = { { 0x002700, 8, 0x20, 0x00000000 }, { 0x002704, 8, 0x20, 0x00000000 }, { 0x002708, 8, 0x20, 0x00000000 }, @@ -299,19 +298,19 @@ nvd9_grctx_init_90c0_0[] = { {} }; -const struct nvc0_graph_pack -nvd9_grctx_pack_mthd[] = { - { nvc1_grctx_init_9097_0, 0x9097 }, - { nvc8_grctx_init_9197_0, 0x9197 }, - { nvc8_grctx_init_9297_0, 0x9297 }, - { nvc0_grctx_init_902d_0, 0x902d }, - { nvc0_grctx_init_9039_0, 0x9039 }, - { nvd9_grctx_init_90c0_0, 0x90c0 }, +const struct gf100_gr_pack +gf119_grctx_pack_mthd[] = { + { gf108_grctx_init_9097_0, 0x9097 }, + { gf110_grctx_init_9197_0, 0x9197 }, + { gf110_grctx_init_9297_0, 0x9297 }, + { gf100_grctx_init_902d_0, 0x902d }, + { gf100_grctx_init_9039_0, 0x9039 }, + { gf119_grctx_init_90c0_0, 0x90c0 }, {} }; -const struct nvc0_graph_init -nvd9_grctx_init_fe_0[] = { +const struct gf100_gr_init +gf119_grctx_init_fe_0[] = { { 0x404004, 10, 0x04, 0x00000000 }, { 0x404044, 1, 0x04, 0x00000000 }, { 0x404094, 13, 0x04, 0x00000000 }, @@ -331,8 +330,8 @@ nvd9_grctx_init_fe_0[] = { {} }; -static const struct nvc0_graph_init -nvd9_grctx_init_ds_0[] = { +static const struct gf100_gr_init +gf119_grctx_init_ds_0[] = { { 0x405800, 1, 0x04, 0x0f8000bf }, { 0x405830, 1, 0x04, 0x02180218 }, { 0x405834, 1, 0x04, 0x08000000 }, @@ -344,8 +343,8 @@ nvd9_grctx_init_ds_0[] = { {} }; -static const struct nvc0_graph_init -nvd9_grctx_init_pd_0[] = { +static const struct gf100_gr_init +gf119_grctx_init_pd_0[] = { { 0x406020, 1, 0x04, 0x000103c1 }, { 0x406028, 4, 0x04, 0x00000001 }, { 0x4064a8, 1, 0x04, 0x00000000 }, @@ -356,8 +355,8 @@ nvd9_grctx_init_pd_0[] = { {} }; -const struct nvc0_graph_init -nvd9_grctx_init_be_0[] = { +const struct gf100_gr_init +gf119_grctx_init_be_0[] = { { 0x408800, 1, 0x04, 0x02802a3c }, { 0x408804, 1, 0x04, 0x00000040 }, { 0x408808, 1, 0x04, 0x1043e005 }, @@ -368,22 +367,22 @@ nvd9_grctx_init_be_0[] = { {} }; -static const struct nvc0_graph_pack -nvd9_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvd9_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nvc0_grctx_init_memfmt_0 }, - { nvd9_grctx_init_ds_0 }, - { nvd9_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nvc0_grctx_init_scc_0 }, - { nvd9_grctx_init_be_0 }, +static const struct gf100_gr_pack +gf119_grctx_pack_hub[] = { + { gf100_grctx_init_main_0 }, + { gf119_grctx_init_fe_0 }, + { gf100_grctx_init_pri_0 }, + { gf100_grctx_init_memfmt_0 }, + { gf119_grctx_init_ds_0 }, + { gf119_grctx_init_pd_0 }, + { gf100_grctx_init_rstr2d_0 }, + { gf100_grctx_init_scc_0 }, + { gf119_grctx_init_be_0 }, {} }; -const struct nvc0_graph_init -nvd9_grctx_init_prop_0[] = { +const struct gf100_gr_init +gf119_grctx_init_prop_0[] = { { 0x418400, 1, 0x04, 0x38004e00 }, { 0x418404, 1, 0x04, 0x71e0ffff }, { 0x41840c, 1, 0x04, 0x00001008 }, @@ -395,8 +394,8 @@ nvd9_grctx_init_prop_0[] = { {} }; -const struct nvc0_graph_init -nvd9_grctx_init_gpc_unk_1[] = { +const struct gf100_gr_init +gf119_grctx_init_gpc_unk_1[] = { { 0x418600, 1, 0x04, 0x0000001f }, { 0x418684, 1, 0x04, 0x0000000f }, { 0x418700, 1, 0x04, 0x00000002 }, @@ -405,8 +404,8 @@ nvd9_grctx_init_gpc_unk_1[] = { {} }; -static const struct nvc0_graph_init -nvd9_grctx_init_setup_0[] = { +static const struct gf100_gr_init +gf119_grctx_init_setup_0[] = { { 0x418800, 1, 0x04, 0x7006860a }, { 0x418808, 3, 0x04, 0x00000000 }, { 0x418828, 1, 0x04, 0x00008442 }, @@ -418,8 +417,8 @@ nvd9_grctx_init_setup_0[] = { {} }; -const struct nvc0_graph_init -nvd9_grctx_init_crstr_0[] = { +const struct gf100_gr_init +gf119_grctx_init_crstr_0[] = { { 0x418b00, 1, 0x04, 0x00000006 }, { 0x418b08, 1, 0x04, 0x0a418820 }, { 0x418b0c, 1, 0x04, 0x062080e6 }, @@ -431,21 +430,21 @@ nvd9_grctx_init_crstr_0[] = { {} }; -static const struct nvc0_graph_pack -nvd9_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvd9_grctx_init_prop_0 }, - { nvd9_grctx_init_gpc_unk_1 }, - { nvd9_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvd9_grctx_init_crstr_0 }, - { nvc1_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, +static const struct gf100_gr_pack +gf119_grctx_pack_gpc[] = { + { gf100_grctx_init_gpc_unk_0 }, + { gf119_grctx_init_prop_0 }, + { gf119_grctx_init_gpc_unk_1 }, + { gf119_grctx_init_setup_0 }, + { gf100_grctx_init_zcull_0 }, + { gf119_grctx_init_crstr_0 }, + { gf108_grctx_init_gpm_0 }, + { gf100_grctx_init_gcc_0 }, {} }; -static const struct nvc0_graph_init -nvd9_grctx_init_tex_0[] = { +static const struct gf100_gr_init +gf119_grctx_init_tex_0[] = { { 0x419a00, 1, 0x04, 0x000001f0 }, { 0x419a04, 1, 0x04, 0x00000001 }, { 0x419a08, 1, 0x04, 0x00000023 }, @@ -458,8 +457,8 @@ nvd9_grctx_init_tex_0[] = { {} }; -static const struct nvc0_graph_init -nvd9_grctx_init_mpc_0[] = { +static const struct gf100_gr_init +gf119_grctx_init_mpc_0[] = { { 0x419c00, 1, 0x04, 0x0000000a }, { 0x419c04, 1, 0x04, 0x00000006 }, { 0x419c08, 1, 0x04, 0x00000002 }, @@ -469,8 +468,8 @@ nvd9_grctx_init_mpc_0[] = { {} }; -const struct nvc0_graph_init -nvd9_grctx_init_sm_0[] = { +const struct gf100_gr_init +gf119_grctx_init_sm_0[] = { { 0x419e04, 3, 0x04, 0x00000000 }, { 0x419e10, 1, 0x04, 0x00000002 }, { 0x419e44, 1, 0x04, 0x001beff2 }, @@ -483,15 +482,15 @@ nvd9_grctx_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack -nvd9_grctx_pack_tpc[] = { - { nvc1_grctx_init_pe_0 }, - { nvd9_grctx_init_tex_0 }, - { nvc1_grctx_init_wwdx_0 }, - { nvd9_grctx_init_mpc_0 }, - { nvc4_grctx_init_l1c_0 }, - { nvc1_grctx_init_tpccs_0 }, - { nvd9_grctx_init_sm_0 }, +static const struct gf100_gr_pack +gf119_grctx_pack_tpc[] = { + { gf108_grctx_init_pe_0 }, + { gf119_grctx_init_tex_0 }, + { gf108_grctx_init_wwdx_0 }, + { gf119_grctx_init_mpc_0 }, + { gf104_grctx_init_l1c_0 }, + { gf108_grctx_init_tpccs_0 }, + { gf119_grctx_init_sm_0 }, {} }; @@ -499,30 +498,30 @@ nvd9_grctx_pack_tpc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nouveau_oclass * -nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gf119_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xd9), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nvc0_grctx_generate_main, - .unkn = nvc1_grctx_generate_unkn, - .hub = nvd9_grctx_pack_hub, - .gpc = nvd9_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvd9_grctx_pack_tpc, - .icmd = nvd9_grctx_pack_icmd, - .mthd = nvd9_grctx_pack_mthd, - .bundle = nvc0_grctx_generate_bundle, + .main = gf100_grctx_generate_main, + .unkn = gf108_grctx_generate_unkn, + .hub = gf119_grctx_pack_hub, + .gpc = gf119_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gf119_grctx_pack_tpc, + .icmd = gf119_grctx_pack_icmd, + .mthd = gf119_grctx_pack_mthd, + .bundle = gf100_grctx_generate_bundle, .bundle_size = 0x1800, - .pagepool = nvc0_grctx_generate_pagepool, + .pagepool = gf100_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvc1_grctx_generate_attrib, + .attrib = gf108_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, .alpha_nr_max = 0x324, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index ccac2ee1a1cb..b52300d8861a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c @@ -21,15 +21,17 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "ctxgf100.h" -#include "ctxnvc0.h" +#include <subdev/fb.h> +#include <subdev/mc.h> /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init -nve4_grctx_init_icmd_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_icmd_0[] = { { 0x001000, 1, 0x01, 0x00000004 }, { 0x000039, 3, 0x01, 0x00000000 }, { 0x0000a9, 1, 0x01, 0x0000ffff }, @@ -272,14 +274,14 @@ nve4_grctx_init_icmd_0[] = { {} }; -const struct nvc0_graph_pack -nve4_grctx_pack_icmd[] = { - { nve4_grctx_init_icmd_0 }, +const struct gf100_gr_pack +gk104_grctx_pack_icmd[] = { + { gk104_grctx_init_icmd_0 }, {} }; -const struct nvc0_graph_init -nve4_grctx_init_a097_0[] = { +const struct gf100_gr_init +gk104_grctx_init_a097_0[] = { { 0x000800, 8, 0x40, 0x00000000 }, { 0x000804, 8, 0x40, 0x00000000 }, { 0x000808, 8, 0x40, 0x00000400 }, @@ -578,15 +580,15 @@ nve4_grctx_init_a097_0[] = { {} }; -static const struct nvc0_graph_pack -nve4_grctx_pack_mthd[] = { - { nve4_grctx_init_a097_0, 0xa097 }, - { nvc0_grctx_init_902d_0, 0x902d }, +static const struct gf100_gr_pack +gk104_grctx_pack_mthd[] = { + { gk104_grctx_init_a097_0, 0xa097 }, + { gf100_grctx_init_902d_0, 0x902d }, {} }; -static const struct nvc0_graph_init -nve4_grctx_init_fe_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_fe_0[] = { { 0x404010, 5, 0x04, 0x00000000 }, { 0x404024, 1, 0x04, 0x0000e000 }, { 0x404028, 1, 0x04, 0x00000000 }, @@ -606,8 +608,8 @@ nve4_grctx_init_fe_0[] = { {} }; -const struct nvc0_graph_init -nve4_grctx_init_memfmt_0[] = { +const struct gf100_gr_init +gk104_grctx_init_memfmt_0[] = { { 0x404604, 1, 0x04, 0x00000014 }, { 0x404608, 1, 0x04, 0x00000000 }, { 0x40460c, 1, 0x04, 0x00003fff }, @@ -632,8 +634,8 @@ nve4_grctx_init_memfmt_0[] = { {} }; -const struct nvc0_graph_init -nve4_grctx_init_ds_0[] = { +const struct gf100_gr_init +gk104_grctx_init_ds_0[] = { { 0x405800, 1, 0x04, 0x0f8000bf }, { 0x405830, 1, 0x04, 0x02180648 }, { 0x405834, 1, 0x04, 0x08000000 }, @@ -645,15 +647,15 @@ nve4_grctx_init_ds_0[] = { {} }; -static const struct nvc0_graph_init -nve4_grctx_init_cwd_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_cwd_0[] = { { 0x405b00, 1, 0x04, 0x00000000 }, { 0x405b10, 1, 0x04, 0x00001000 }, {} }; -static const struct nvc0_graph_init -nve4_grctx_init_pd_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_pd_0[] = { { 0x406020, 1, 0x04, 0x004103c1 }, { 0x406028, 4, 0x04, 0x00000001 }, { 0x4064a8, 1, 0x04, 0x00000000 }, @@ -667,14 +669,14 @@ nve4_grctx_init_pd_0[] = { {} }; -static const struct nvc0_graph_init -nve4_grctx_init_sked_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_sked_0[] = { { 0x407040, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nve4_grctx_init_scc_0[] = { +const struct gf100_gr_init +gk104_grctx_init_scc_0[] = { { 0x408000, 2, 0x04, 0x00000000 }, { 0x408008, 1, 0x04, 0x00000030 }, { 0x40800c, 2, 0x04, 0x00000000 }, @@ -684,8 +686,8 @@ nve4_grctx_init_scc_0[] = { {} }; -static const struct nvc0_graph_init -nve4_grctx_init_be_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_be_0[] = { { 0x408800, 1, 0x04, 0x02802a3c }, { 0x408804, 1, 0x04, 0x00000040 }, { 0x408808, 1, 0x04, 0x1043e005 }, @@ -697,24 +699,24 @@ nve4_grctx_init_be_0[] = { {} }; -const struct nvc0_graph_pack -nve4_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nve4_grctx_init_fe_0 }, - { nvc0_grctx_init_pri_0 }, - { nve4_grctx_init_memfmt_0 }, - { nve4_grctx_init_ds_0 }, - { nve4_grctx_init_cwd_0 }, - { nve4_grctx_init_pd_0 }, - { nve4_grctx_init_sked_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nve4_grctx_init_scc_0 }, - { nve4_grctx_init_be_0 }, +const struct gf100_gr_pack +gk104_grctx_pack_hub[] = { + { gf100_grctx_init_main_0 }, + { gk104_grctx_init_fe_0 }, + { gf100_grctx_init_pri_0 }, + { gk104_grctx_init_memfmt_0 }, + { gk104_grctx_init_ds_0 }, + { gk104_grctx_init_cwd_0 }, + { gk104_grctx_init_pd_0 }, + { gk104_grctx_init_sked_0 }, + { gf100_grctx_init_rstr2d_0 }, + { gk104_grctx_init_scc_0 }, + { gk104_grctx_init_be_0 }, {} }; -static const struct nvc0_graph_init -nve4_grctx_init_setup_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_setup_0[] = { { 0x418800, 1, 0x04, 0x7006860a }, { 0x418808, 3, 0x04, 0x00000000 }, { 0x418828, 1, 0x04, 0x00000044 }, @@ -726,8 +728,8 @@ nve4_grctx_init_setup_0[] = { {} }; -const struct nvc0_graph_init -nve4_grctx_init_gpm_0[] = { +const struct gf100_gr_init +gk104_grctx_init_gpm_0[] = { { 0x418c08, 1, 0x04, 0x00000001 }, { 0x418c10, 8, 0x04, 0x00000000 }, { 0x418c40, 1, 0x04, 0xffffffff }, @@ -737,21 +739,21 @@ nve4_grctx_init_gpm_0[] = { {} }; -const struct nvc0_graph_pack -nve4_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvd9_grctx_init_prop_0 }, - { nvd9_grctx_init_gpc_unk_1 }, - { nve4_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvd9_grctx_init_crstr_0 }, - { nve4_grctx_init_gpm_0 }, - { nvc0_grctx_init_gcc_0 }, +const struct gf100_gr_pack +gk104_grctx_pack_gpc[] = { + { gf100_grctx_init_gpc_unk_0 }, + { gf119_grctx_init_prop_0 }, + { gf119_grctx_init_gpc_unk_1 }, + { gk104_grctx_init_setup_0 }, + { gf100_grctx_init_zcull_0 }, + { gf119_grctx_init_crstr_0 }, + { gk104_grctx_init_gpm_0 }, + { gf100_grctx_init_gcc_0 }, {} }; -static const struct nvc0_graph_init -nve4_grctx_init_tex_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_tex_0[] = { { 0x419a00, 1, 0x04, 0x000000f0 }, { 0x419a04, 1, 0x04, 0x00000001 }, { 0x419a08, 1, 0x04, 0x00000021 }, @@ -765,8 +767,8 @@ nve4_grctx_init_tex_0[] = { {} }; -static const struct nvc0_graph_init -nve4_grctx_init_mpc_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_mpc_0[] = { { 0x419c00, 1, 0x04, 0x0000000a }, { 0x419c04, 1, 0x04, 0x80000006 }, { 0x419c08, 1, 0x04, 0x00000002 }, @@ -776,15 +778,15 @@ nve4_grctx_init_mpc_0[] = { {} }; -static const struct nvc0_graph_init -nve4_grctx_init_l1c_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_l1c_0[] = { { 0x419ce8, 1, 0x04, 0x00000000 }, { 0x419cf4, 1, 0x04, 0x00003203 }, {} }; -static const struct nvc0_graph_init -nve4_grctx_init_sm_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_sm_0[] = { { 0x419e04, 3, 0x04, 0x00000000 }, { 0x419e10, 1, 0x04, 0x00000402 }, { 0x419e44, 1, 0x04, 0x0013eff2 }, @@ -802,35 +804,35 @@ nve4_grctx_init_sm_0[] = { {} }; -const struct nvc0_graph_pack -nve4_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nve4_grctx_init_tex_0 }, - { nve4_grctx_init_mpc_0 }, - { nve4_grctx_init_l1c_0 }, - { nve4_grctx_init_sm_0 }, +const struct gf100_gr_pack +gk104_grctx_pack_tpc[] = { + { gf117_grctx_init_pe_0 }, + { gk104_grctx_init_tex_0 }, + { gk104_grctx_init_mpc_0 }, + { gk104_grctx_init_l1c_0 }, + { gk104_grctx_init_sm_0 }, {} }; -const struct nvc0_graph_init -nve4_grctx_init_pes_0[] = { +const struct gf100_gr_init +gk104_grctx_init_pes_0[] = { { 0x41be24, 1, 0x04, 0x00000006 }, {} }; -static const struct nvc0_graph_init -nve4_grctx_init_cbm_0[] = { +static const struct gf100_gr_init +gk104_grctx_init_cbm_0[] = { { 0x41bec0, 1, 0x04, 0x12180000 }, { 0x41bec4, 1, 0x04, 0x00037f7f }, { 0x41bee4, 1, 0x04, 0x06480430 }, {} }; -const struct nvc0_graph_pack -nve4_grctx_pack_ppc[] = { - { nve4_grctx_init_pes_0 }, - { nve4_grctx_init_cbm_0 }, - { nvd7_grctx_init_wwdx_0 }, +const struct gf100_gr_pack +gk104_grctx_pack_ppc[] = { + { gk104_grctx_init_pes_0 }, + { gk104_grctx_init_cbm_0 }, + { gf117_grctx_init_wwdx_0 }, {} }; @@ -839,9 +841,9 @@ nve4_grctx_pack_ppc[] = { ******************************************************************************/ void -nve4_grctx_generate_bundle(struct nvc0_grctx *info) +gk104_grctx_generate_bundle(struct gf100_grctx *info) { - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, impl->bundle_size / 0x20); const u32 token_limit = impl->bundle_token_limit; @@ -856,9 +858,9 @@ nve4_grctx_generate_bundle(struct nvc0_grctx *info) } void -nve4_grctx_generate_pagepool(struct nvc0_grctx *info) +gk104_grctx_generate_pagepool(struct gf100_grctx *info) { - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); @@ -870,7 +872,7 @@ nve4_grctx_generate_pagepool(struct nvc0_grctx *info) } void -nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv) +gk104_grctx_generate_unkn(struct gf100_gr_priv *priv) { nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); @@ -881,7 +883,7 @@ nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv) } void -nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) +gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv) { u32 data[6] = {}, data2[2] = {}; u8 tpcnr[GPC_MAX]; @@ -939,18 +941,18 @@ nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) } void -nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) { - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; int i; - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); - nvc0_graph_mmio(priv, oclass->hub); - nvc0_graph_mmio(priv, oclass->gpc); - nvc0_graph_mmio(priv, oclass->zcull); - nvc0_graph_mmio(priv, oclass->tpc); - nvc0_graph_mmio(priv, oclass->ppc); + gf100_gr_mmio(priv, oclass->hub); + gf100_gr_mmio(priv, oclass->gpc); + gf100_gr_mmio(priv, oclass->zcull); + gf100_gr_mmio(priv, oclass->tpc); + gf100_gr_mmio(priv, oclass->ppc); nv_wr32(priv, 0x404154, 0x00000000); @@ -959,10 +961,10 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) oclass->attrib(info); oclass->unkn(priv); - nvc0_grctx_generate_tpcid(priv); - nvc0_grctx_generate_r406028(priv); - nve4_grctx_generate_r418bb8(priv); - nvc0_grctx_generate_r406800(priv); + gf100_grctx_generate_tpcid(priv); + gf100_grctx_generate_r406028(priv); + gk104_grctx_generate_r418bb8(priv); + gf100_grctx_generate_r406800(priv); for (i = 0; i < 8; i++) nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); @@ -977,42 +979,42 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) } nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); - nvc0_graph_icmd(priv, oclass->icmd); + gf100_gr_icmd(priv, oclass->icmd); nv_wr32(priv, 0x404154, 0x00000400); - nvc0_graph_mthd(priv, oclass->mthd); - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); + gf100_gr_mthd(priv, oclass->mthd); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); nv_mask(priv, 0x418800, 0x00200000, 0x00200000); nv_mask(priv, 0x41be10, 0x00800000, 0x00800000); } -struct nouveau_oclass * -nve4_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gk104_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xe4), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nve4_grctx_pack_hub, - .gpc = nve4_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nve4_grctx_pack_tpc, - .ppc = nve4_grctx_pack_ppc, - .icmd = nve4_grctx_pack_icmd, - .mthd = nve4_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, + .main = gk104_grctx_generate_main, + .unkn = gk104_grctx_generate_unkn, + .hub = gk104_grctx_pack_hub, + .gpc = gk104_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gk104_grctx_pack_tpc, + .ppc = gk104_grctx_pack_ppc, + .icmd = gk104_grctx_pack_icmd, + .mthd = gk104_grctx_pack_mthd, + .bundle = gk104_grctx_generate_bundle, .bundle_size = 0x3000, .bundle_min_gpm_fifo_depth = 0x180, .bundle_token_limit = 0x600, - .pagepool = nve4_grctx_generate_pagepool, + .pagepool = gk104_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, + .attrib = gf117_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c index e9b0dcf95a49..b3f58be04e9c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c @@ -21,15 +21,14 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "ctxnvc0.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init -nvf0_grctx_init_icmd_0[] = { +static const struct gf100_gr_init +gk110_grctx_init_icmd_0[] = { { 0x001000, 1, 0x01, 0x00000004 }, { 0x000039, 3, 0x01, 0x00000000 }, { 0x0000a9, 1, 0x01, 0x0000ffff }, @@ -279,14 +278,14 @@ nvf0_grctx_init_icmd_0[] = { {} }; -const struct nvc0_graph_pack -nvf0_grctx_pack_icmd[] = { - { nvf0_grctx_init_icmd_0 }, +const struct gf100_gr_pack +gk110_grctx_pack_icmd[] = { + { gk110_grctx_init_icmd_0 }, {} }; -static const struct nvc0_graph_init -nvf0_grctx_init_a197_0[] = { +static const struct gf100_gr_init +gk110_grctx_init_a197_0[] = { { 0x000800, 8, 0x40, 0x00000000 }, { 0x000804, 8, 0x40, 0x00000000 }, { 0x000808, 8, 0x40, 0x00000400 }, @@ -587,15 +586,15 @@ nvf0_grctx_init_a197_0[] = { {} }; -const struct nvc0_graph_pack -nvf0_grctx_pack_mthd[] = { - { nvf0_grctx_init_a197_0, 0xa197 }, - { nvc0_grctx_init_902d_0, 0x902d }, +const struct gf100_gr_pack +gk110_grctx_pack_mthd[] = { + { gk110_grctx_init_a197_0, 0xa197 }, + { gf100_grctx_init_902d_0, 0x902d }, {} }; -static const struct nvc0_graph_init -nvf0_grctx_init_fe_0[] = { +static const struct gf100_gr_init +gk110_grctx_init_fe_0[] = { { 0x404004, 8, 0x04, 0x00000000 }, { 0x404024, 1, 0x04, 0x0000e000 }, { 0x404028, 8, 0x04, 0x00000000 }, @@ -620,8 +619,8 @@ nvf0_grctx_init_fe_0[] = { {} }; -const struct nvc0_graph_init -nvf0_grctx_init_pri_0[] = { +const struct gf100_gr_init +gk110_grctx_init_pri_0[] = { { 0x404404, 12, 0x04, 0x00000000 }, { 0x404438, 1, 0x04, 0x00000000 }, { 0x404460, 2, 0x04, 0x00000000 }, @@ -632,16 +631,16 @@ nvf0_grctx_init_pri_0[] = { {} }; -const struct nvc0_graph_init -nvf0_grctx_init_cwd_0[] = { +const struct gf100_gr_init +gk110_grctx_init_cwd_0[] = { { 0x405b00, 1, 0x04, 0x00000000 }, { 0x405b10, 1, 0x04, 0x00001000 }, { 0x405b20, 1, 0x04, 0x04000000 }, {} }; -static const struct nvc0_graph_init -nvf0_grctx_init_pd_0[] = { +static const struct gf100_gr_init +gk110_grctx_init_pd_0[] = { { 0x406020, 1, 0x04, 0x034103c1 }, { 0x406028, 4, 0x04, 0x00000001 }, { 0x4064a8, 1, 0x04, 0x00000000 }, @@ -655,8 +654,8 @@ nvf0_grctx_init_pd_0[] = { {} }; -static const struct nvc0_graph_init -nvf0_grctx_init_be_0[] = { +static const struct gf100_gr_init +gk110_grctx_init_be_0[] = { { 0x408800, 1, 0x04, 0x12802a3c }, { 0x408804, 1, 0x04, 0x00000040 }, { 0x408808, 1, 0x04, 0x1003e005 }, @@ -668,23 +667,23 @@ nvf0_grctx_init_be_0[] = { {} }; -const struct nvc0_graph_pack -nvf0_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nvf0_grctx_init_fe_0 }, - { nvf0_grctx_init_pri_0 }, - { nve4_grctx_init_memfmt_0 }, - { nve4_grctx_init_ds_0 }, - { nvf0_grctx_init_cwd_0 }, - { nvf0_grctx_init_pd_0 }, - { nvc0_grctx_init_rstr2d_0 }, - { nve4_grctx_init_scc_0 }, - { nvf0_grctx_init_be_0 }, +const struct gf100_gr_pack +gk110_grctx_pack_hub[] = { + { gf100_grctx_init_main_0 }, + { gk110_grctx_init_fe_0 }, + { gk110_grctx_init_pri_0 }, + { gk104_grctx_init_memfmt_0 }, + { gk104_grctx_init_ds_0 }, + { gk110_grctx_init_cwd_0 }, + { gk110_grctx_init_pd_0 }, + { gf100_grctx_init_rstr2d_0 }, + { gk104_grctx_init_scc_0 }, + { gk110_grctx_init_be_0 }, {} }; -static const struct nvc0_graph_init -nvf0_grctx_init_setup_0[] = { +static const struct gf100_gr_init +gk110_grctx_init_setup_0[] = { { 0x418800, 1, 0x04, 0x7006860a }, { 0x418808, 1, 0x04, 0x00000000 }, { 0x41880c, 1, 0x04, 0x00000030 }, @@ -698,28 +697,28 @@ nvf0_grctx_init_setup_0[] = { {} }; -const struct nvc0_graph_init -nvf0_grctx_init_gpc_unk_2[] = { +const struct gf100_gr_init +gk110_grctx_init_gpc_unk_2[] = { { 0x418d24, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_pack -nvf0_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nvd9_grctx_init_prop_0 }, - { nvd9_grctx_init_gpc_unk_1 }, - { nvf0_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nvd9_grctx_init_crstr_0 }, - { nve4_grctx_init_gpm_0 }, - { nvf0_grctx_init_gpc_unk_2 }, - { nvc0_grctx_init_gcc_0 }, +const struct gf100_gr_pack +gk110_grctx_pack_gpc[] = { + { gf100_grctx_init_gpc_unk_0 }, + { gf119_grctx_init_prop_0 }, + { gf119_grctx_init_gpc_unk_1 }, + { gk110_grctx_init_setup_0 }, + { gf100_grctx_init_zcull_0 }, + { gf119_grctx_init_crstr_0 }, + { gk104_grctx_init_gpm_0 }, + { gk110_grctx_init_gpc_unk_2 }, + { gf100_grctx_init_gcc_0 }, {} }; -const struct nvc0_graph_init -nvf0_grctx_init_tex_0[] = { +const struct gf100_gr_init +gk110_grctx_init_tex_0[] = { { 0x419a00, 1, 0x04, 0x000000f0 }, { 0x419a04, 1, 0x04, 0x00000001 }, { 0x419a08, 1, 0x04, 0x00000021 }, @@ -733,8 +732,8 @@ nvf0_grctx_init_tex_0[] = { {} }; -const struct nvc0_graph_init -nvf0_grctx_init_mpc_0[] = { +const struct gf100_gr_init +gk110_grctx_init_mpc_0[] = { { 0x419c00, 1, 0x04, 0x0000001a }, { 0x419c04, 1, 0x04, 0x80000006 }, { 0x419c08, 1, 0x04, 0x00000002 }, @@ -744,15 +743,15 @@ nvf0_grctx_init_mpc_0[] = { {} }; -const struct nvc0_graph_init -nvf0_grctx_init_l1c_0[] = { +const struct gf100_gr_init +gk110_grctx_init_l1c_0[] = { { 0x419ce8, 1, 0x04, 0x00000000 }, { 0x419cf4, 1, 0x04, 0x00000203 }, {} }; -static const struct nvc0_graph_init -nvf0_grctx_init_sm_0[] = { +static const struct gf100_gr_init +gk110_grctx_init_sm_0[] = { { 0x419e04, 1, 0x04, 0x00000000 }, { 0x419e08, 1, 0x04, 0x0000001d }, { 0x419e0c, 1, 0x04, 0x00000000 }, @@ -779,29 +778,29 @@ nvf0_grctx_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack -nvf0_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nvf0_grctx_init_tex_0 }, - { nvf0_grctx_init_mpc_0 }, - { nvf0_grctx_init_l1c_0 }, - { nvf0_grctx_init_sm_0 }, +static const struct gf100_gr_pack +gk110_grctx_pack_tpc[] = { + { gf117_grctx_init_pe_0 }, + { gk110_grctx_init_tex_0 }, + { gk110_grctx_init_mpc_0 }, + { gk110_grctx_init_l1c_0 }, + { gk110_grctx_init_sm_0 }, {} }; -static const struct nvc0_graph_init -nvf0_grctx_init_cbm_0[] = { +static const struct gf100_gr_init +gk110_grctx_init_cbm_0[] = { { 0x41bec0, 1, 0x04, 0x10000000 }, { 0x41bec4, 1, 0x04, 0x00037f7f }, { 0x41bee4, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_pack -nvf0_grctx_pack_ppc[] = { - { nve4_grctx_init_pes_0 }, - { nvf0_grctx_init_cbm_0 }, - { nvd7_grctx_init_wwdx_0 }, +const struct gf100_gr_pack +gk110_grctx_pack_ppc[] = { + { gk104_grctx_init_pes_0 }, + { gk110_grctx_init_cbm_0 }, + { gf117_grctx_init_wwdx_0 }, {} }; @@ -809,33 +808,33 @@ nvf0_grctx_pack_ppc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nouveau_oclass * -nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gk110_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xf0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nvf0_grctx_pack_hub, - .gpc = nvf0_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nvf0_grctx_pack_tpc, - .ppc = nvf0_grctx_pack_ppc, - .icmd = nvf0_grctx_pack_icmd, - .mthd = nvf0_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, + .main = gk104_grctx_generate_main, + .unkn = gk104_grctx_generate_unkn, + .hub = gk110_grctx_pack_hub, + .gpc = gk110_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gk110_grctx_pack_tpc, + .ppc = gk110_grctx_pack_ppc, + .icmd = gk110_grctx_pack_icmd, + .mthd = gk110_grctx_pack_mthd, + .bundle = gk104_grctx_generate_bundle, .bundle_size = 0x3000, .bundle_min_gpm_fifo_depth = 0x180, .bundle_token_limit = 0x7c0, - .pagepool = nve4_grctx_generate_pagepool, + .pagepool = gk104_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, + .attrib = gf117_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c index 3adb7fe91772..b11c26794fde 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c @@ -21,14 +21,13 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "ctxnvc0.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init +static const struct gf100_gr_init gk110b_grctx_init_sm_0[] = { { 0x419e04, 1, 0x04, 0x00000000 }, { 0x419e08, 1, 0x04, 0x0000001d }, @@ -56,12 +55,12 @@ gk110b_grctx_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack +static const struct gf100_gr_pack gk110b_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nvf0_grctx_init_tex_0 }, - { nvf0_grctx_init_mpc_0 }, - { nvf0_grctx_init_l1c_0 }, + { gf117_grctx_init_pe_0 }, + { gk110_grctx_init_tex_0 }, + { gk110_grctx_init_mpc_0 }, + { gk110_grctx_init_l1c_0 }, { gk110b_grctx_init_sm_0 }, {} }; @@ -70,33 +69,33 @@ gk110b_grctx_pack_tpc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nouveau_oclass * -gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gk110b_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xf1), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nvf0_grctx_pack_hub, - .gpc = nvf0_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, + .main = gk104_grctx_generate_main, + .unkn = gk104_grctx_generate_unkn, + .hub = gk110_grctx_pack_hub, + .gpc = gk110_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, .tpc = gk110b_grctx_pack_tpc, - .ppc = nvf0_grctx_pack_ppc, - .icmd = nvf0_grctx_pack_icmd, - .mthd = nvf0_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, + .ppc = gk110_grctx_pack_ppc, + .icmd = gk110_grctx_pack_icmd, + .mthd = gk110_grctx_pack_mthd, + .bundle = gk104_grctx_generate_bundle, .bundle_size = 0x3000, .bundle_min_gpm_fifo_depth = 0x180, .bundle_token_limit = 0x600, - .pagepool = nve4_grctx_generate_pagepool, + .pagepool = gk104_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, + .attrib = gf117_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c index ce252adbef81..6e8ce9fc311a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c @@ -21,15 +21,14 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "ctxnvc0.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init -nv108_grctx_init_icmd_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_icmd_0[] = { { 0x001000, 1, 0x01, 0x00000004 }, { 0x000039, 3, 0x01, 0x00000000 }, { 0x0000a9, 1, 0x01, 0x0000ffff }, @@ -278,14 +277,14 @@ nv108_grctx_init_icmd_0[] = { {} }; -static const struct nvc0_graph_pack -nv108_grctx_pack_icmd[] = { - { nv108_grctx_init_icmd_0 }, +static const struct gf100_gr_pack +gk208_grctx_pack_icmd[] = { + { gk208_grctx_init_icmd_0 }, {} }; -static const struct nvc0_graph_init -nv108_grctx_init_fe_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_fe_0[] = { { 0x404004, 8, 0x04, 0x00000000 }, { 0x404024, 1, 0x04, 0x0000e000 }, { 0x404028, 8, 0x04, 0x00000000 }, @@ -311,8 +310,8 @@ nv108_grctx_init_fe_0[] = { {} }; -static const struct nvc0_graph_init -nv108_grctx_init_ds_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_ds_0[] = { { 0x405800, 1, 0x04, 0x0f8000bf }, { 0x405830, 1, 0x04, 0x02180648 }, { 0x405834, 1, 0x04, 0x08000000 }, @@ -325,8 +324,8 @@ nv108_grctx_init_ds_0[] = { {} }; -static const struct nvc0_graph_init -nv108_grctx_init_pd_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_pd_0[] = { { 0x406020, 1, 0x04, 0x034103c1 }, { 0x406028, 4, 0x04, 0x00000001 }, { 0x4064a8, 1, 0x04, 0x00000000 }, @@ -340,8 +339,8 @@ nv108_grctx_init_pd_0[] = { {} }; -const struct nvc0_graph_init -nv108_grctx_init_rstr2d_0[] = { +const struct gf100_gr_init +gk208_grctx_init_rstr2d_0[] = { { 0x407804, 1, 0x04, 0x00000063 }, { 0x40780c, 1, 0x04, 0x0a418820 }, { 0x407810, 1, 0x04, 0x062080e6 }, @@ -353,8 +352,8 @@ nv108_grctx_init_rstr2d_0[] = { {} }; -static const struct nvc0_graph_init -nv108_grctx_init_be_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_be_0[] = { { 0x408800, 1, 0x04, 0x32802a3c }, { 0x408804, 1, 0x04, 0x00000040 }, { 0x408808, 1, 0x04, 0x1003e005 }, @@ -366,23 +365,23 @@ nv108_grctx_init_be_0[] = { {} }; -static const struct nvc0_graph_pack -nv108_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, - { nv108_grctx_init_fe_0 }, - { nvf0_grctx_init_pri_0 }, - { nve4_grctx_init_memfmt_0 }, - { nv108_grctx_init_ds_0 }, - { nvf0_grctx_init_cwd_0 }, - { nv108_grctx_init_pd_0 }, - { nv108_grctx_init_rstr2d_0 }, - { nve4_grctx_init_scc_0 }, - { nv108_grctx_init_be_0 }, +static const struct gf100_gr_pack +gk208_grctx_pack_hub[] = { + { gf100_grctx_init_main_0 }, + { gk208_grctx_init_fe_0 }, + { gk110_grctx_init_pri_0 }, + { gk104_grctx_init_memfmt_0 }, + { gk208_grctx_init_ds_0 }, + { gk110_grctx_init_cwd_0 }, + { gk208_grctx_init_pd_0 }, + { gk208_grctx_init_rstr2d_0 }, + { gk104_grctx_init_scc_0 }, + { gk208_grctx_init_be_0 }, {} }; -const struct nvc0_graph_init -nv108_grctx_init_prop_0[] = { +const struct gf100_gr_init +gk208_grctx_init_prop_0[] = { { 0x418400, 1, 0x04, 0x38005e00 }, { 0x418404, 1, 0x04, 0x71e0ffff }, { 0x41840c, 1, 0x04, 0x00001008 }, @@ -394,8 +393,8 @@ nv108_grctx_init_prop_0[] = { {} }; -static const struct nvc0_graph_init -nv108_grctx_init_gpc_unk_1[] = { +static const struct gf100_gr_init +gk208_grctx_init_gpc_unk_1[] = { { 0x418600, 1, 0x04, 0x0000007f }, { 0x418684, 1, 0x04, 0x0000001f }, { 0x418700, 1, 0x04, 0x00000002 }, @@ -404,8 +403,8 @@ nv108_grctx_init_gpc_unk_1[] = { {} }; -static const struct nvc0_graph_init -nv108_grctx_init_setup_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_setup_0[] = { { 0x418800, 1, 0x04, 0x7006863a }, { 0x418808, 1, 0x04, 0x00000000 }, { 0x41880c, 1, 0x04, 0x00000030 }, @@ -419,8 +418,8 @@ nv108_grctx_init_setup_0[] = { {} }; -const struct nvc0_graph_init -nv108_grctx_init_crstr_0[] = { +const struct gf100_gr_init +gk208_grctx_init_crstr_0[] = { { 0x418b00, 1, 0x04, 0x0000001e }, { 0x418b08, 1, 0x04, 0x0a418820 }, { 0x418b0c, 1, 0x04, 0x062080e6 }, @@ -432,8 +431,8 @@ nv108_grctx_init_crstr_0[] = { {} }; -static const struct nvc0_graph_init -nv108_grctx_init_gpm_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_gpm_0[] = { { 0x418c08, 1, 0x04, 0x00000001 }, { 0x418c10, 8, 0x04, 0x00000000 }, { 0x418c40, 1, 0x04, 0xffffffff }, @@ -443,22 +442,22 @@ nv108_grctx_init_gpm_0[] = { {} }; -static const struct nvc0_graph_pack -nv108_grctx_pack_gpc[] = { - { nvc0_grctx_init_gpc_unk_0 }, - { nv108_grctx_init_prop_0 }, - { nv108_grctx_init_gpc_unk_1 }, - { nv108_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nv108_grctx_init_crstr_0 }, - { nv108_grctx_init_gpm_0 }, - { nvf0_grctx_init_gpc_unk_2 }, - { nvc0_grctx_init_gcc_0 }, +static const struct gf100_gr_pack +gk208_grctx_pack_gpc[] = { + { gf100_grctx_init_gpc_unk_0 }, + { gk208_grctx_init_prop_0 }, + { gk208_grctx_init_gpc_unk_1 }, + { gk208_grctx_init_setup_0 }, + { gf100_grctx_init_zcull_0 }, + { gk208_grctx_init_crstr_0 }, + { gk208_grctx_init_gpm_0 }, + { gk110_grctx_init_gpc_unk_2 }, + { gf100_grctx_init_gcc_0 }, {} }; -static const struct nvc0_graph_init -nv108_grctx_init_tex_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_tex_0[] = { { 0x419a00, 1, 0x04, 0x000100f0 }, { 0x419a04, 1, 0x04, 0x00000001 }, { 0x419a08, 1, 0x04, 0x00000421 }, @@ -472,8 +471,8 @@ nv108_grctx_init_tex_0[] = { {} }; -static const struct nvc0_graph_init -nv108_grctx_init_sm_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_sm_0[] = { { 0x419e04, 1, 0x04, 0x00000000 }, { 0x419e08, 1, 0x04, 0x0000001d }, { 0x419e0c, 1, 0x04, 0x00000000 }, @@ -500,18 +499,18 @@ nv108_grctx_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack -nv108_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, - { nv108_grctx_init_tex_0 }, - { nvf0_grctx_init_mpc_0 }, - { nvf0_grctx_init_l1c_0 }, - { nv108_grctx_init_sm_0 }, +static const struct gf100_gr_pack +gk208_grctx_pack_tpc[] = { + { gf117_grctx_init_pe_0 }, + { gk208_grctx_init_tex_0 }, + { gk110_grctx_init_mpc_0 }, + { gk110_grctx_init_l1c_0 }, + { gk208_grctx_init_sm_0 }, {} }; -static const struct nvc0_graph_init -nv108_grctx_init_cbm_0[] = { +static const struct gf100_gr_init +gk208_grctx_init_cbm_0[] = { { 0x41bec0, 1, 0x04, 0x10000000 }, { 0x41bec4, 1, 0x04, 0x00037f7f }, { 0x41bee4, 1, 0x04, 0x00000000 }, @@ -519,11 +518,11 @@ nv108_grctx_init_cbm_0[] = { {} }; -static const struct nvc0_graph_pack -nv108_grctx_pack_ppc[] = { - { nve4_grctx_init_pes_0 }, - { nv108_grctx_init_cbm_0 }, - { nvd7_grctx_init_wwdx_0 }, +static const struct gf100_gr_pack +gk208_grctx_pack_ppc[] = { + { gk104_grctx_init_pes_0 }, + { gk208_grctx_init_cbm_0 }, + { gf117_grctx_init_wwdx_0 }, {} }; @@ -531,33 +530,33 @@ nv108_grctx_pack_ppc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nouveau_oclass * -nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gk208_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0x08), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nv108_grctx_pack_hub, - .gpc = nv108_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nv108_grctx_pack_tpc, - .ppc = nv108_grctx_pack_ppc, - .icmd = nv108_grctx_pack_icmd, - .mthd = nvf0_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, + .main = gk104_grctx_generate_main, + .unkn = gk104_grctx_generate_unkn, + .hub = gk208_grctx_pack_hub, + .gpc = gk208_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gk208_grctx_pack_tpc, + .ppc = gk208_grctx_pack_ppc, + .icmd = gk208_grctx_pack_icmd, + .mthd = gk110_grctx_pack_mthd, + .bundle = gk104_grctx_generate_bundle, .bundle_size = 0x3000, .bundle_min_gpm_fifo_depth = 0xc2, .bundle_token_limit = 0x200, - .pagepool = nve4_grctx_generate_pagepool, + .pagepool = gk104_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, + .attrib = gf117_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index 36fc9831cc93..2f241f6f0f0a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -19,43 +19,42 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#include "ctxgf100.h" -#include "ctxnvc0.h" - -static const struct nvc0_graph_pack +static const struct gf100_gr_pack gk20a_grctx_pack_mthd[] = { - { nve4_grctx_init_a097_0, 0xa297 }, - { nvc0_grctx_init_902d_0, 0x902d }, + { gk104_grctx_init_a097_0, 0xa297 }, + { gf100_grctx_init_902d_0, 0x902d }, {} }; -struct nouveau_oclass * -gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gk20a_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0xea), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, - .main = nve4_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, - .hub = nve4_grctx_pack_hub, - .gpc = nve4_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, - .tpc = nve4_grctx_pack_tpc, - .ppc = nve4_grctx_pack_ppc, - .icmd = nve4_grctx_pack_icmd, + .main = gk104_grctx_generate_main, + .unkn = gk104_grctx_generate_unkn, + .hub = gk104_grctx_pack_hub, + .gpc = gk104_grctx_pack_gpc, + .zcull = gf100_grctx_pack_zcull, + .tpc = gk104_grctx_pack_tpc, + .ppc = gk104_grctx_pack_ppc, + .icmd = gk104_grctx_pack_icmd, .mthd = gk20a_grctx_pack_mthd, - .bundle = nve4_grctx_generate_bundle, + .bundle = gk104_grctx_generate_bundle, .bundle_size = 0x1800, .bundle_min_gpm_fifo_depth = 0x62, .bundle_token_limit = 0x100, - .pagepool = nve4_grctx_generate_pagepool, + .pagepool = gk104_grctx_generate_pagepool, .pagepool_size = 0x8000, - .attrib = nvd7_grctx_generate_attrib, + .attrib = gf117_grctx_generate_attrib, .attrib_nr_max = 0x240, .attrib_nr = 0x240, .alpha_nr_max = 0x648 + (0x648 / 2), diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index 62e918b9fa81..956f4dce960c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c @@ -21,14 +21,16 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "ctxgf100.h" -#include "ctxnvc0.h" +#include <subdev/fb.h> +#include <subdev/mc.h> /******************************************************************************* * PGRAPH context register lists ******************************************************************************/ -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_icmd_0[] = { { 0x001000, 1, 0x01, 0x00000004 }, { 0x000039, 3, 0x01, 0x00000000 }, @@ -287,13 +289,13 @@ gm107_grctx_init_icmd_0[] = { {} }; -static const struct nvc0_graph_pack +static const struct gf100_gr_pack gm107_grctx_pack_icmd[] = { { gm107_grctx_init_icmd_0 }, {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_b097_0[] = { { 0x000800, 8, 0x40, 0x00000000 }, { 0x000804, 8, 0x40, 0x00000000 }, @@ -610,14 +612,14 @@ gm107_grctx_init_b097_0[] = { {} }; -static const struct nvc0_graph_pack +static const struct gf100_gr_pack gm107_grctx_pack_mthd[] = { { gm107_grctx_init_b097_0, 0xb097 }, - { nvc0_grctx_init_902d_0, 0x902d }, + { gf100_grctx_init_902d_0, 0x902d }, {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_fe_0[] = { { 0x404004, 8, 0x04, 0x00000000 }, { 0x404024, 1, 0x04, 0x0000e000 }, @@ -639,7 +641,7 @@ gm107_grctx_init_fe_0[] = { {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_ds_0[] = { { 0x405800, 1, 0x04, 0x0f8001bf }, { 0x405830, 1, 0x04, 0x0aa01000 }, @@ -653,7 +655,7 @@ gm107_grctx_init_ds_0[] = { {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_pd_0[] = { { 0x406020, 1, 0x04, 0x07410001 }, { 0x406028, 4, 0x04, 0x00000001 }, @@ -669,7 +671,7 @@ gm107_grctx_init_pd_0[] = { {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_be_0[] = { { 0x408800, 1, 0x04, 0x32802a3c }, { 0x408804, 1, 0x04, 0x00000040 }, @@ -682,28 +684,28 @@ gm107_grctx_init_be_0[] = { {} }; -static const struct nvc0_graph_pack +static const struct gf100_gr_pack gm107_grctx_pack_hub[] = { - { nvc0_grctx_init_main_0 }, + { gf100_grctx_init_main_0 }, { gm107_grctx_init_fe_0 }, - { nvf0_grctx_init_pri_0 }, - { nve4_grctx_init_memfmt_0 }, + { gk110_grctx_init_pri_0 }, + { gk104_grctx_init_memfmt_0 }, { gm107_grctx_init_ds_0 }, - { nvf0_grctx_init_cwd_0 }, + { gk110_grctx_init_cwd_0 }, { gm107_grctx_init_pd_0 }, - { nv108_grctx_init_rstr2d_0 }, - { nve4_grctx_init_scc_0 }, + { gk208_grctx_init_rstr2d_0 }, + { gk104_grctx_init_scc_0 }, { gm107_grctx_init_be_0 }, {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_gpc_unk_0[] = { { 0x418380, 1, 0x04, 0x00000056 }, {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_gpc_unk_1[] = { { 0x418600, 1, 0x04, 0x0000007f }, { 0x418684, 1, 0x04, 0x0000001f }, @@ -714,7 +716,7 @@ gm107_grctx_init_gpc_unk_1[] = { {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_setup_0[] = { { 0x418800, 1, 0x04, 0x7006863a }, { 0x418810, 1, 0x04, 0x00000000 }, @@ -727,7 +729,7 @@ gm107_grctx_init_setup_0[] = { {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_gpc_unk_2[] = { { 0x418d24, 1, 0x04, 0x00000000 }, { 0x418e00, 1, 0x04, 0x90000000 }, @@ -741,21 +743,21 @@ gm107_grctx_init_gpc_unk_2[] = { {} }; -static const struct nvc0_graph_pack +static const struct gf100_gr_pack gm107_grctx_pack_gpc[] = { { gm107_grctx_init_gpc_unk_0 }, - { nv108_grctx_init_prop_0 }, + { gk208_grctx_init_prop_0 }, { gm107_grctx_init_gpc_unk_1 }, { gm107_grctx_init_setup_0 }, - { nvc0_grctx_init_zcull_0 }, - { nv108_grctx_init_crstr_0 }, - { nve4_grctx_init_gpm_0 }, + { gf100_grctx_init_zcull_0 }, + { gk208_grctx_init_crstr_0 }, + { gk104_grctx_init_gpm_0 }, { gm107_grctx_init_gpc_unk_2 }, - { nvc0_grctx_init_gcc_0 }, + { gf100_grctx_init_gcc_0 }, {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_tex_0[] = { { 0x419a00, 1, 0x04, 0x000300f0 }, { 0x419a04, 1, 0x04, 0x00000005 }, @@ -771,7 +773,7 @@ gm107_grctx_init_tex_0[] = { {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_mpc_0[] = { { 0x419c00, 1, 0x04, 0x0000001a }, { 0x419c04, 1, 0x04, 0x80000006 }, @@ -785,13 +787,13 @@ gm107_grctx_init_mpc_0[] = { {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_l1c_0[] = { { 0x419c84, 1, 0x04, 0x00000020 }, {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_sm_0[] = { { 0x419e04, 3, 0x04, 0x00000000 }, { 0x419e10, 1, 0x04, 0x00001c02 }, @@ -812,9 +814,9 @@ gm107_grctx_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack +static const struct gf100_gr_pack gm107_grctx_pack_tpc[] = { - { nvd7_grctx_init_pe_0 }, + { gf117_grctx_init_pe_0 }, { gm107_grctx_init_tex_0 }, { gm107_grctx_init_mpc_0 }, { gm107_grctx_init_l1c_0 }, @@ -822,7 +824,7 @@ gm107_grctx_pack_tpc[] = { {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_cbm_0[] = { { 0x41bec0, 1, 0x04, 0x00000000 }, { 0x41bec4, 1, 0x04, 0x01050000 }, @@ -832,7 +834,7 @@ gm107_grctx_init_cbm_0[] = { {} }; -static const struct nvc0_graph_init +static const struct gf100_gr_init gm107_grctx_init_wwdx_0[] = { { 0x41bf00, 1, 0x04, 0x0a418820 }, { 0x41bf04, 1, 0x04, 0x062080e6 }, @@ -846,9 +848,9 @@ gm107_grctx_init_wwdx_0[] = { {} }; -static const struct nvc0_graph_pack +static const struct gf100_gr_pack gm107_grctx_pack_ppc[] = { - { nve4_grctx_init_pes_0 }, + { gk104_grctx_init_pes_0 }, { gm107_grctx_init_cbm_0 }, { gm107_grctx_init_wwdx_0 }, {} @@ -859,9 +861,9 @@ gm107_grctx_pack_ppc[] = { ******************************************************************************/ static void -gm107_grctx_generate_bundle(struct nvc0_grctx *info) +gm107_grctx_generate_bundle(struct gf100_grctx *info) { - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, impl->bundle_size / 0x20); const u32 token_limit = impl->bundle_token_limit; @@ -876,9 +878,9 @@ gm107_grctx_generate_bundle(struct nvc0_grctx *info) } static void -gm107_grctx_generate_pagepool(struct nvc0_grctx *info) +gm107_grctx_generate_pagepool(struct gf100_grctx *info) { - const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); @@ -891,10 +893,10 @@ gm107_grctx_generate_pagepool(struct nvc0_grctx *info) } static void -gm107_grctx_generate_attrib(struct nvc0_grctx *info) +gm107_grctx_generate_attrib(struct gf100_grctx *info) { - struct nvc0_graph_priv *priv = info->priv; - const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv); + struct gf100_gr_priv *priv = info->priv; + const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(priv); const u32 alpha = impl->alpha_nr; const u32 attrib = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); @@ -930,7 +932,7 @@ gm107_grctx_generate_attrib(struct nvc0_grctx *info) } static void -gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv) +gm107_grctx_generate_tpcid(struct gf100_gr_priv *priv) { int gpc, tpc, id; @@ -950,16 +952,16 @@ gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv) } static void -gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) { - struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; int i; - nvc0_graph_mmio(priv, oclass->hub); - nvc0_graph_mmio(priv, oclass->gpc); - nvc0_graph_mmio(priv, oclass->zcull); - nvc0_graph_mmio(priv, oclass->tpc); - nvc0_graph_mmio(priv, oclass->ppc); + gf100_gr_mmio(priv, oclass->hub); + gf100_gr_mmio(priv, oclass->gpc); + gf100_gr_mmio(priv, oclass->zcull); + gf100_gr_mmio(priv, oclass->tpc); + gf100_gr_mmio(priv, oclass->ppc); nv_wr32(priv, 0x404154, 0x00000000); @@ -969,9 +971,9 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) oclass->unkn(priv); gm107_grctx_generate_tpcid(priv); - nvc0_grctx_generate_r406028(priv); - nve4_grctx_generate_r418bb8(priv); - nvc0_grctx_generate_r406800(priv); + gf100_grctx_generate_r406028(priv); + gk104_grctx_generate_r418bb8(priv); + gf100_grctx_generate_r406800(priv); nv_wr32(priv, 0x4064d0, 0x00000001); for (i = 1; i < 8; i++) @@ -988,9 +990,9 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr); } - nvc0_graph_icmd(priv, oclass->icmd); + gf100_gr_icmd(priv, oclass->icmd); nv_wr32(priv, 0x404154, 0x00000400); - nvc0_graph_mthd(priv, oclass->mthd); + gf100_gr_mthd(priv, oclass->mthd); nv_mask(priv, 0x419e00, 0x00808080, 0x00808080); nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000); @@ -998,22 +1000,22 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nv_mask(priv, 0x419f88, 0x80000000, 0x80000000); } -struct nouveau_oclass * -gm107_grctx_oclass = &(struct nvc0_grctx_oclass) { +struct nvkm_oclass * +gm107_grctx_oclass = &(struct gf100_grctx_oclass) { .base.handle = NV_ENGCTX(GR, 0x08), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, .main = gm107_grctx_generate_main, - .unkn = nve4_grctx_generate_unkn, + .unkn = gk104_grctx_generate_unkn, .hub = gm107_grctx_pack_hub, .gpc = gm107_grctx_pack_gpc, - .zcull = nvc0_grctx_pack_zcull, + .zcull = gf100_grctx_pack_zcull, .tpc = gm107_grctx_pack_tpc, .ppc = gm107_grctx_pack_ppc, .icmd = gm107_grctx_pack_icmd, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c index 7bbb1e1b7a8d..dc31462afe65 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c @@ -22,8 +22,6 @@ * Authors: Ben Skeggs */ -#include <core/gpuobj.h> - /* NVIDIA context programs handle a number of other conditions which are * not implemented in our versions. It's not clear why NVIDIA context * programs have this code, nor whether it's strictly necessary for @@ -111,15 +109,16 @@ #define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */ #define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */ +#include "ctxnv40.h" #include "nv40.h" -#include "ctx.h" +#include <core/device.h> /* TODO: * - get vs count from 0x1540 */ static int -nv40_graph_vs_count(struct nouveau_device *device) +nv40_gr_vs_count(struct nvkm_device *device) { switch (device->chipset) { @@ -158,9 +157,9 @@ enum cp_label { }; static void -nv40_graph_construct_general(struct nouveau_grctx *ctx) +nv40_gr_construct_general(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int i; cp_ctx(ctx, 0x4000a4, 1); @@ -208,7 +207,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx) gr_def(ctx, 0x4009dc, 0x80000000); } else { cp_ctx(ctx, 0x400840, 20); - if (nv44_graph_class(ctx->device)) { + if (nv44_gr_class(ctx->device)) { for (i = 0; i < 8; i++) gr_def(ctx, 0x400860 + (i * 4), 0x00000001); } @@ -217,7 +216,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx) gr_def(ctx, 0x400888, 0x00000040); cp_ctx(ctx, 0x400894, 11); gr_def(ctx, 0x400894, 0x00000040); - if (!nv44_graph_class(ctx->device)) { + if (!nv44_gr_class(ctx->device)) { for (i = 0; i < 8; i++) gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); } @@ -264,9 +263,9 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx) } static void -nv40_graph_construct_state3d(struct nouveau_grctx *ctx) +nv40_gr_construct_state3d(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int i; if (device->chipset == 0x40) { @@ -369,9 +368,9 @@ nv40_graph_construct_state3d(struct nouveau_grctx *ctx) } static void -nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx) +nv40_gr_construct_state3d_2(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int i; cp_ctx(ctx, 0x402000, 1); @@ -504,8 +503,8 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx) cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); - cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->device)); - for (i = 0; i < nv40_graph_vs_count(ctx->device); i++) + cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device)); + for (i = 0; i < nv40_gr_vs_count(ctx->device); i++) gr_def(ctx, 0x403420 + (i * 4), 0x00005555); if (device->chipset != 0x40) { @@ -533,9 +532,9 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx) } static void -nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx) +nv40_gr_construct_state3d_3(struct nvkm_grctx *ctx) { - int len = nv44_graph_class(ctx->device) ? 0x0084 : 0x0684; + int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684; cp_out (ctx, 0x300000); cp_lsr (ctx, len - 4); @@ -548,14 +547,14 @@ nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx) } static void -nv40_graph_construct_shader(struct nouveau_grctx *ctx) +nv40_gr_construct_shader(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; - struct nouveau_gpuobj *obj = ctx->data; + struct nvkm_device *device = ctx->device; + struct nvkm_gpuobj *obj = ctx->data; int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset; int offset, i; - vs_nr = nv40_graph_vs_count(ctx->device); + vs_nr = nv40_gr_vs_count(ctx->device); vs_nr_b0 = 363; vs_nr_b1 = device->chipset == 0x40 ? 128 : 64; if (device->chipset == 0x40) { @@ -570,16 +569,16 @@ nv40_graph_construct_shader(struct nouveau_grctx *ctx) } else { b0_offset = 0x1d40/4; /* 2200 */ b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ - vs_len = nv44_graph_class(device) ? 0x4980/4 : 0x4a40/4; + vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4; } cp_lsr(ctx, vs_len * vs_nr + 0x300/4); - cp_out(ctx, nv44_graph_class(device) ? 0x800029 : 0x800041); + cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041); offset = ctx->ctxvals_pos; ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); - if (ctx->mode != NOUVEAU_GRCTX_VALS) + if (ctx->mode != NVKM_GRCTX_VALS) return; offset += 0x0280/4; @@ -595,7 +594,7 @@ nv40_graph_construct_shader(struct nouveau_grctx *ctx) } static void -nv40_grctx_generate(struct nouveau_grctx *ctx) +nv40_grctx_generate(struct nvkm_grctx *ctx) { /* decide whether we're loading/unloading the context */ cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); @@ -629,23 +628,23 @@ nv40_grctx_generate(struct nouveau_grctx *ctx) /* general PGRAPH state */ cp_name(ctx, cp_swap_state); cp_pos (ctx, 0x00020/4); - nv40_graph_construct_general(ctx); + nv40_gr_construct_general(ctx); cp_wait(ctx, STATUS, IDLE); /* 3D state, block 1 */ cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); - nv40_graph_construct_state3d(ctx); + nv40_gr_construct_state3d(ctx); cp_wait(ctx, STATUS, IDLE); /* 3D state, block 2 */ - nv40_graph_construct_state3d_2(ctx); + nv40_gr_construct_state3d_2(ctx); /* Some other block of "random" state */ - nv40_graph_construct_state3d_3(ctx); + nv40_gr_construct_state3d_3(ctx); /* Per-vertex shader state */ cp_pos (ctx, ctx->ctxvals_pos); - nv40_graph_construct_shader(ctx); + nv40_gr_construct_shader(ctx); /* pre-exit state updates */ cp_name(ctx, cp_prepare_exit); @@ -660,22 +659,22 @@ nv40_grctx_generate(struct nouveau_grctx *ctx) } void -nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) +nv40_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem) { - nv40_grctx_generate(&(struct nouveau_grctx) { + nv40_grctx_generate(&(struct nvkm_grctx) { .device = device, - .mode = NOUVEAU_GRCTX_VALS, + .mode = NVKM_GRCTX_VALS, .data = mem, }); } int -nv40_grctx_init(struct nouveau_device *device, u32 *size) +nv40_grctx_init(struct nvkm_device *device, u32 *size) { u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; - struct nouveau_grctx ctx = { + struct nvkm_grctx ctx = { .device = device, - .mode = NOUVEAU_GRCTX_PROG, + .mode = NVKM_GRCTX_PROG, .data = ctxprog, .ctxprog_max = 256, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctx.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h index e1947013d3bc..8a89961956af 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctx.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h @@ -1,12 +1,13 @@ -#ifndef __NOUVEAU_GRCTX_H__ -#define __NOUVEAU_GRCTX_H__ +#ifndef __NVKM_GRCTX_H__ +#define __NVKM_GRCTX_H__ +#include <core/gpuobj.h> -struct nouveau_grctx { - struct nouveau_device *device; +struct nvkm_grctx { + struct nvkm_device *device; enum { - NOUVEAU_GRCTX_PROG, - NOUVEAU_GRCTX_VALS + NVKM_GRCTX_PROG, + NVKM_GRCTX_VALS } mode; void *data; @@ -19,11 +20,11 @@ struct nouveau_grctx { }; static inline void -cp_out(struct nouveau_grctx *ctx, u32 inst) +cp_out(struct nvkm_grctx *ctx, u32 inst) { u32 *ctxprog = ctx->data; - if (ctx->mode != NOUVEAU_GRCTX_PROG) + if (ctx->mode != NVKM_GRCTX_PROG) return; BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max); @@ -31,13 +32,13 @@ cp_out(struct nouveau_grctx *ctx, u32 inst) } static inline void -cp_lsr(struct nouveau_grctx *ctx, u32 val) +cp_lsr(struct nvkm_grctx *ctx, u32 val) { cp_out(ctx, CP_LOAD_SR | val); } static inline void -cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length) +cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length) { ctx->ctxprog_reg = (reg - 0x00400000) >> 2; @@ -53,12 +54,12 @@ cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length) } static inline void -cp_name(struct nouveau_grctx *ctx, int name) +cp_name(struct nvkm_grctx *ctx, int name) { u32 *ctxprog = ctx->data; int i; - if (ctx->mode != NOUVEAU_GRCTX_PROG) + if (ctx->mode != NVKM_GRCTX_PROG) return; ctx->ctxprog_label[name] = ctx->ctxprog_len; @@ -73,7 +74,7 @@ cp_name(struct nouveau_grctx *ctx, int name) } static inline void -_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name) +_cp_bra(struct nvkm_grctx *ctx, u32 mod, int flag, int state, int name) { int ip = 0; @@ -91,21 +92,21 @@ _cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name) #define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0) static inline void -_cp_wait(struct nouveau_grctx *ctx, int flag, int state) +_cp_wait(struct nvkm_grctx *ctx, int flag, int state) { cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0)); } #define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s) static inline void -_cp_set(struct nouveau_grctx *ctx, int flag, int state) +_cp_set(struct nvkm_grctx *ctx, int flag, int state) { cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0)); } #define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s) static inline void -cp_pos(struct nouveau_grctx *ctx, int offset) +cp_pos(struct nvkm_grctx *ctx, int offset) { ctx->ctxvals_pos = offset; ctx->ctxvals_base = ctx->ctxvals_pos; @@ -115,9 +116,9 @@ cp_pos(struct nouveau_grctx *ctx, int offset) } static inline void -gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val) +gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val) { - if (ctx->mode != NOUVEAU_GRCTX_VALS) + if (ctx->mode != NVKM_GRCTX_VALS) return; reg = (reg - 0x00400000) / 4; @@ -125,5 +126,4 @@ gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val) nv_wo32(ctx->data, reg * 4, val); } - #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c index 1d0e33fb5f61..9c9528d2cd90 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c @@ -20,8 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <core/gpuobj.h> - #define CP_FLAG_CLEAR 0 #define CP_FLAG_SET 1 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) @@ -107,14 +105,14 @@ #define CP_SEEK_1 0x00c000ff #define CP_SEEK_2 0x00c800ff -#include "nv50.h" -#include "ctx.h" +#include "ctxnv40.h" + +#include <core/device.h> +#include <subdev/fb.h> #define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf) #define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac) -#include <subdev/fb.h> - /* * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's * the GPU itself that does context-switching, but it needs a special @@ -169,14 +167,14 @@ enum cp_label { cp_exit, }; -static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx); -static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx); -static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx); +static void nv50_gr_construct_mmio(struct nvkm_grctx *ctx); +static void nv50_gr_construct_xfer1(struct nvkm_grctx *ctx); +static void nv50_gr_construct_xfer2(struct nvkm_grctx *ctx); /* Main function: construct the ctxprog skeleton, call the other functions. */ static int -nv50_grctx_generate(struct nouveau_grctx *ctx) +nv50_grctx_generate(struct nvkm_grctx *ctx) { cp_set (ctx, STATE, RUNNING); cp_set (ctx, XFER_SWITCH, ENABLE); @@ -219,9 +217,9 @@ nv50_grctx_generate(struct nouveau_grctx *ctx) cp_pos (ctx, 0x00004/4); cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */ cp_pos (ctx, 0x00100/4); - nv50_graph_construct_mmio(ctx); - nv50_graph_construct_xfer1(ctx); - nv50_graph_construct_xfer2(ctx); + nv50_gr_construct_mmio(ctx); + nv50_gr_construct_xfer1(ctx); + nv50_gr_construct_xfer2(ctx); cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); @@ -255,22 +253,22 @@ nv50_grctx_generate(struct nouveau_grctx *ctx) } void -nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) +nv50_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem) { - nv50_grctx_generate(&(struct nouveau_grctx) { + nv50_grctx_generate(&(struct nvkm_grctx) { .device = device, - .mode = NOUVEAU_GRCTX_VALS, + .mode = NVKM_GRCTX_VALS, .data = mem, }); } int -nv50_grctx_init(struct nouveau_device *device, u32 *size) +nv50_grctx_init(struct nvkm_device *device, u32 *size) { u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i; - struct nouveau_grctx ctx = { + struct nvkm_grctx ctx = { .device = device, - .mode = NOUVEAU_GRCTX_PROG, + .mode = NVKM_GRCTX_PROG, .data = ctxprog, .ctxprog_max = 512, }; @@ -293,12 +291,12 @@ nv50_grctx_init(struct nouveau_device *device, u32 *size) */ static void -nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx); +nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx); static void -nv50_graph_construct_mmio(struct nouveau_grctx *ctx) +nv50_gr_construct_mmio(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int i, j; int offset, base; u32 units = nv_rd32 (ctx->device, 0x1540); @@ -334,7 +332,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx) gr_def(ctx, 0x400b20, 0x0001629d); } - nv50_graph_construct_mmio_ddata(ctx); + nv50_gr_construct_mmio_ddata(ctx); /* 0C00: VFETCH */ cp_ctx(ctx, 0x400c08, 0x2); @@ -572,7 +570,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx) else if (device->chipset < 0xa0) gr_def(ctx, 0x407d08, 0x00390040); else { - if (nouveau_fb(device)->ram->type != NV_MEM_TYPE_GDDR5) + if (nvkm_fb(device)->ram->type != NV_MEM_TYPE_GDDR5) gr_def(ctx, 0x407d08, 0x003d0040); else gr_def(ctx, 0x407d08, 0x003c0040); @@ -784,18 +782,18 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx) } static void -dd_emit(struct nouveau_grctx *ctx, int num, u32 val) { +dd_emit(struct nvkm_grctx *ctx, int num, u32 val) { int i; - if (val && ctx->mode == NOUVEAU_GRCTX_VALS) + if (val && ctx->mode == NVKM_GRCTX_VALS) for (i = 0; i < num; i++) nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); ctx->ctxvals_pos += num; } static void -nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx) +nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int base, num; base = ctx->ctxvals_pos; @@ -1156,9 +1154,9 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx) */ static void -xf_emit(struct nouveau_grctx *ctx, int num, u32 val) { +xf_emit(struct nvkm_grctx *ctx, int num, u32 val) { int i; - if (val && ctx->mode == NOUVEAU_GRCTX_VALS) + if (val && ctx->mode == NVKM_GRCTX_VALS) for (i = 0; i < num; i++) nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); ctx->ctxvals_pos += num << 3; @@ -1166,29 +1164,29 @@ xf_emit(struct nouveau_grctx *ctx, int num, u32 val) { /* Gene declarations... */ -static void nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx); -static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx); -static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx); +static void nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx); +static void nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx); +static void nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx); static void -nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) +nv50_gr_construct_xfer1(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int i; int offset; int size = 0; @@ -1200,32 +1198,32 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) if (device->chipset < 0xa0) { /* Strand 0 */ ctx->ctxvals_pos = offset; - nv50_graph_construct_gene_dispatch(ctx); - nv50_graph_construct_gene_m2mf(ctx); - nv50_graph_construct_gene_unk24xx(ctx); - nv50_graph_construct_gene_clipid(ctx); - nv50_graph_construct_gene_zcull(ctx); + nv50_gr_construct_gene_dispatch(ctx); + nv50_gr_construct_gene_m2mf(ctx); + nv50_gr_construct_gene_unk24xx(ctx); + nv50_gr_construct_gene_clipid(ctx); + nv50_gr_construct_gene_zcull(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 1 */ ctx->ctxvals_pos = offset + 0x1; - nv50_graph_construct_gene_vfetch(ctx); - nv50_graph_construct_gene_eng2d(ctx); - nv50_graph_construct_gene_csched(ctx); - nv50_graph_construct_gene_ropm1(ctx); - nv50_graph_construct_gene_ropm2(ctx); + nv50_gr_construct_gene_vfetch(ctx); + nv50_gr_construct_gene_eng2d(ctx); + nv50_gr_construct_gene_csched(ctx); + nv50_gr_construct_gene_ropm1(ctx); + nv50_gr_construct_gene_ropm2(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 2 */ ctx->ctxvals_pos = offset + 0x2; - nv50_graph_construct_gene_ccache(ctx); - nv50_graph_construct_gene_unk1cxx(ctx); - nv50_graph_construct_gene_strmout(ctx); - nv50_graph_construct_gene_unk14xx(ctx); - nv50_graph_construct_gene_unk10xx(ctx); - nv50_graph_construct_gene_unk34xx(ctx); + nv50_gr_construct_gene_ccache(ctx); + nv50_gr_construct_gene_unk1cxx(ctx); + nv50_gr_construct_gene_strmout(ctx); + nv50_gr_construct_gene_unk14xx(ctx); + nv50_gr_construct_gene_unk10xx(ctx); + nv50_gr_construct_gene_unk34xx(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; @@ -1233,7 +1231,7 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) ctx->ctxvals_pos = offset + 3; for (i = 0; i < 6; i++) if (units & (1 << (i + 16))) - nv50_graph_construct_gene_ropc(ctx); + nv50_gr_construct_gene_ropc(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; @@ -1241,74 +1239,74 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) for (i = 0; i < 4; i++) { ctx->ctxvals_pos = offset + 4 + i; if (units & (1 << (2 * i))) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if (units & (1 << (2 * i + 1))) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; } } else { /* Strand 0 */ ctx->ctxvals_pos = offset; - nv50_graph_construct_gene_dispatch(ctx); - nv50_graph_construct_gene_m2mf(ctx); - nv50_graph_construct_gene_unk34xx(ctx); - nv50_graph_construct_gene_csched(ctx); - nv50_graph_construct_gene_unk1cxx(ctx); - nv50_graph_construct_gene_strmout(ctx); + nv50_gr_construct_gene_dispatch(ctx); + nv50_gr_construct_gene_m2mf(ctx); + nv50_gr_construct_gene_unk34xx(ctx); + nv50_gr_construct_gene_csched(ctx); + nv50_gr_construct_gene_unk1cxx(ctx); + nv50_gr_construct_gene_strmout(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 1 */ ctx->ctxvals_pos = offset + 1; - nv50_graph_construct_gene_unk10xx(ctx); + nv50_gr_construct_gene_unk10xx(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 2 */ ctx->ctxvals_pos = offset + 2; if (device->chipset == 0xa0) - nv50_graph_construct_gene_unk14xx(ctx); - nv50_graph_construct_gene_unk24xx(ctx); + nv50_gr_construct_gene_unk14xx(ctx); + nv50_gr_construct_gene_unk24xx(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 3 */ ctx->ctxvals_pos = offset + 3; - nv50_graph_construct_gene_vfetch(ctx); + nv50_gr_construct_gene_vfetch(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 4 */ ctx->ctxvals_pos = offset + 4; - nv50_graph_construct_gene_ccache(ctx); + nv50_gr_construct_gene_ccache(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 5 */ ctx->ctxvals_pos = offset + 5; - nv50_graph_construct_gene_ropm2(ctx); - nv50_graph_construct_gene_ropm1(ctx); + nv50_gr_construct_gene_ropm2(ctx); + nv50_gr_construct_gene_ropm1(ctx); /* per-ROP context */ for (i = 0; i < 8; i++) if (units & (1<<(i+16))) - nv50_graph_construct_gene_ropc(ctx); + nv50_gr_construct_gene_ropc(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 6 */ ctx->ctxvals_pos = offset + 6; - nv50_graph_construct_gene_zcull(ctx); - nv50_graph_construct_gene_clipid(ctx); - nv50_graph_construct_gene_eng2d(ctx); + nv50_gr_construct_gene_zcull(ctx); + nv50_gr_construct_gene_clipid(ctx); + nv50_gr_construct_gene_eng2d(ctx); if (units & (1 << 0)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if (units & (1 << 1)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if (units & (1 << 2)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if (units & (1 << 3)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; @@ -1316,19 +1314,19 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) ctx->ctxvals_pos = offset + 7; if (device->chipset == 0xa0) { if (units & (1 << 4)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if (units & (1 << 5)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if (units & (1 << 6)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if (units & (1 << 7)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if (units & (1 << 8)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); if (units & (1 << 9)) - nv50_graph_construct_xfer_tp(ctx); + nv50_gr_construct_xfer_tp(ctx); } else { - nv50_graph_construct_gene_unk14xx(ctx); + nv50_gr_construct_gene_unk14xx(ctx); } if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; @@ -1349,10 +1347,10 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) */ static void -nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx) { /* start of strand 0 */ - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; /* SEEK */ if (device->chipset == 0x50) xf_emit(ctx, 5, 0); @@ -1405,10 +1403,10 @@ nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx) { /* Strand 0, right after dispatch */ - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int smallm2mf = 0; if (device->chipset < 0x92 || device->chipset == 0x98) smallm2mf = 1; @@ -1457,9 +1455,9 @@ nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; xf_emit(ctx, 2, 0); /* RO */ xf_emit(ctx, 0x800, 0); /* ffffffff */ switch (device->chipset) { @@ -1525,9 +1523,9 @@ nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int i; /* end of area 2 on pre-NVA0, area 1 on NVAx */ xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ @@ -1585,9 +1583,9 @@ nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; /* end of area 2 on pre-NVA0, area 1 on NVAx */ xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */ @@ -1610,9 +1608,9 @@ nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */ if (device->chipset != 0x50) { xf_emit(ctx, 5, 0); /* ffffffff */ @@ -1721,9 +1719,9 @@ nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */ /* SEEK */ xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ @@ -1782,7 +1780,7 @@ nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx) { /* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */ /* SEEK */ @@ -1802,9 +1800,9 @@ nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int i; /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */ /* SEEK */ @@ -1885,9 +1883,9 @@ nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int acnt = 0x10, rep, i; /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */ if (IS_NVA3F(device->chipset)) @@ -2071,9 +2069,9 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */ /* SEEK */ xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */ @@ -2133,9 +2131,9 @@ nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */ /* SEEK */ xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */ @@ -2232,9 +2230,9 @@ nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ @@ -2328,9 +2326,9 @@ nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ @@ -2370,9 +2368,9 @@ nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ xf_emit(ctx, 1, 0); /* 00000007 */ @@ -2383,9 +2381,9 @@ nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; /* SEEK */ xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ @@ -2409,9 +2407,9 @@ nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx) +nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int magic2; if (device->chipset == 0x50) { magic2 = 0x00003e60; @@ -2644,9 +2642,9 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx) +nv50_gr_construct_xfer_unk84xx(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int magic3; switch (device->chipset) { case 0x50: @@ -2736,9 +2734,9 @@ nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx) +nv50_gr_construct_xfer_tprop(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int magic1, magic2; if (device->chipset == 0x50) { magic1 = 0x3ff; @@ -3036,9 +3034,9 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx) +nv50_gr_construct_xfer_tex(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */ if (device->chipset != 0x50) xf_emit(ctx, 1, 0); /* 3 */ @@ -3082,9 +3080,9 @@ nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx) +nv50_gr_construct_xfer_unk8cxx(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */ @@ -3121,26 +3119,26 @@ nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx) +nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; if (device->chipset < 0xa0) { - nv50_graph_construct_xfer_unk84xx(ctx); - nv50_graph_construct_xfer_tprop(ctx); - nv50_graph_construct_xfer_tex(ctx); - nv50_graph_construct_xfer_unk8cxx(ctx); + nv50_gr_construct_xfer_unk84xx(ctx); + nv50_gr_construct_xfer_tprop(ctx); + nv50_gr_construct_xfer_tex(ctx); + nv50_gr_construct_xfer_unk8cxx(ctx); } else { - nv50_graph_construct_xfer_tex(ctx); - nv50_graph_construct_xfer_tprop(ctx); - nv50_graph_construct_xfer_unk8cxx(ctx); - nv50_graph_construct_xfer_unk84xx(ctx); + nv50_gr_construct_xfer_tex(ctx); + nv50_gr_construct_xfer_tprop(ctx); + nv50_gr_construct_xfer_unk8cxx(ctx); + nv50_gr_construct_xfer_unk84xx(ctx); } } static void -nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx) +nv50_gr_construct_xfer_mpc(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int i, mpcnt = 2; switch (device->chipset) { case 0x98: @@ -3270,9 +3268,9 @@ nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx) } static void -nv50_graph_construct_xfer2(struct nouveau_grctx *ctx) +nv50_gr_construct_xfer2(struct nvkm_grctx *ctx) { - struct nouveau_device *device = ctx->device; + struct nvkm_device *device = ctx->device; int i; u32 offset; u32 units = nv_rd32 (ctx->device, 0x1540); @@ -3288,7 +3286,7 @@ nv50_graph_construct_xfer2(struct nouveau_grctx *ctx) if (i == 0) xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ if (units & (1 << i)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; } @@ -3299,40 +3297,40 @@ nv50_graph_construct_xfer2(struct nouveau_grctx *ctx) * what it's doing here. */ xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ if (units & (1 << 0)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if (units & (1 << 1)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 1: TPs 2, 3 */ ctx->ctxvals_pos = offset + 1; if (units & (1 << 2)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if (units & (1 << 3)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 2: TPs 4, 5, 6 */ ctx->ctxvals_pos = offset + 2; if (units & (1 << 4)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if (units & (1 << 5)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if (units & (1 << 6)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; /* Strand 3: TPs 7, 8, 9 */ ctx->ctxvals_pos = offset + 3; if (units & (1 << 7)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if (units & (1 << 8)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if (units & (1 << 9)) - nv50_graph_construct_xfer_mpc(ctx); + nv50_gr_construct_xfer_mpc(ctx); if ((ctx->ctxvals_pos-offset)/8 > size) size = (ctx->ctxvals_pos-offset)/8; } diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc index e37d8106ae1a..64208bf954cf 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc @@ -1,4 +1,4 @@ -/* fuc microcode util functions for nvc0 PGRAPH +/* fuc microcode util functions for gf100 PGRAPH * * Copyright 2011 Red Hat Inc. * diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc index 7445f12b1d9e..eaed1599b90f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc @@ -1,4 +1,4 @@ -/* fuc microcode for nvc0 PGRAPH/GPC +/* fuc microcode for gf100 PGRAPH/GPC * * Copyright 2011 Red Hat Inc. * diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3 index 5ae06a2d64c9..7cf2bf9d95a2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3 @@ -27,13 +27,13 @@ #define CHIPSET GF100 #include "macros.fuc" -.section #nvc0_grgpc_data +.section #gf100_grgpc_data #define INCLUDE_DATA #include "com.fuc" #include "gpc.fuc" #undef INCLUDE_DATA -.section #nvc0_grgpc_code +.section #gf100_grgpc_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h index 325cc7b7b2fb..ea32f56c0a92 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nvc0_grgpc_data[] = { +uint32_t gf100_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x00000064, /* 0x0004: gpc_mmio_list_tail */ @@ -36,7 +36,7 @@ uint32_t nvc0_grgpc_data[] = { 0x00000000, }; -uint32_t nvc0_grgpc_code[] = { +uint32_t gf100_grgpc_code[] = { 0x03a10ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3 index c2f754edbd7d..c918f7d60004 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3 @@ -27,13 +27,13 @@ #define CHIPSET GF117 #include "macros.fuc" -.section #nvd7_grgpc_data +.section #gf117_grgpc_data #define INCLUDE_DATA #include "com.fuc" #include "gpc.fuc" #undef INCLUDE_DATA -.section #nvd7_grgpc_code +.section #gf117_grgpc_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h index 855b220378f9..9a36d9cbb8a5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nve0_grgpc_data[] = { +uint32_t gf117_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x0000006c, /* 0x0004: gpc_mmio_list_tail */ @@ -40,7 +40,7 @@ uint32_t nve0_grgpc_data[] = { 0x00000000, }; -uint32_t nve0_grgpc_code[] = { +uint32_t gf117_grgpc_code[] = { 0x03a10ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3 index 6b906cd2a31f..b80cdfd337a9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3 @@ -27,13 +27,13 @@ #define CHIPSET GK100 #include "macros.fuc" -.section #nve0_grgpc_data +.section #gk104_grgpc_data #define INCLUDE_DATA #include "com.fuc" #include "gpc.fuc" #undef INCLUDE_DATA -.section #nve0_grgpc_code +.section #gk104_grgpc_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h index d1504a4059c6..49020fff4317 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nvd7_grgpc_data[] = { +uint32_t gk104_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x0000006c, /* 0x0004: gpc_mmio_list_tail */ @@ -40,7 +40,7 @@ uint32_t nvd7_grgpc_data[] = { 0x00000000, }; -uint32_t nvd7_grgpc_code[] = { +uint32_t gk104_grgpc_code[] = { 0x03a10ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3 index 90bbe525b626..98d85fe210e8 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3 @@ -27,13 +27,13 @@ #define CHIPSET GK110 #include "macros.fuc" -.section #nvf0_grgpc_data +.section #gk110_grgpc_data #define INCLUDE_DATA #include "com.fuc" #include "gpc.fuc" #undef INCLUDE_DATA -.section #nvf0_grgpc_code +.section #gk110_grgpc_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h index 1b803197d28b..c95b07e3bce5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nvf0_grgpc_data[] = { +uint32_t gk110_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x0000006c, /* 0x0004: gpc_mmio_list_tail */ @@ -40,7 +40,7 @@ uint32_t nvf0_grgpc_data[] = { 0x00000000, }; -uint32_t nvf0_grgpc_code[] = { +uint32_t gk110_grgpc_code[] = { 0x03a10ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5 index bd30262d635b..8f64299a3b91 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5 @@ -27,13 +27,13 @@ #define CHIPSET GK208 #include "macros.fuc" -.section #nv108_grgpc_data +.section #gk208_grgpc_data #define INCLUDE_DATA #include "com.fuc" #include "gpc.fuc" #undef INCLUDE_DATA -.section #nv108_grgpc_code +.section #gk208_grgpc_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h index 31922707794f..7e1c28ee7591 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h @@ -1,4 +1,4 @@ -uint32_t nv108_grgpc_data[] = { +uint32_t gk208_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x0000006c, /* 0x0004: gpc_mmio_list_tail */ @@ -40,7 +40,7 @@ uint32_t nv108_grgpc_data[] = { 0x00000000, }; -uint32_t nv108_grgpc_code[] = { +uint32_t gk208_grgpc_code[] = { 0x03140ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5 index e730603891d7..e730603891d7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5 +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5 diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h index 6d53b67dd3c4..6d53b67dd3c4 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc index b4ad18bf5a26..87f99e38acbf 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc @@ -1,4 +1,4 @@ -/* fuc microcode for nvc0 PGRAPH/HUB +/* fuc microcode for gf100 PGRAPH/HUB * * Copyright 2011 Red Hat Inc. * diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3 index 3ff52badf932..2c28e7199b7f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3 @@ -25,13 +25,13 @@ #define CHIPSET GF100 #include "macros.fuc" -.section #nvc0_grhub_data +.section #gf100_grhub_data #define INCLUDE_DATA #include "com.fuc" #include "hub.fuc" #undef INCLUDE_DATA -.section #nvc0_grhub_code +.section #gf100_grhub_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h index 92dfe6a4ac87..f6acda505677 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nvc0_grhub_data[] = { +uint32_t gf100_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, /* 0x0004: hub_mmio_list_tail */ @@ -205,7 +205,7 @@ uint32_t nvc0_grhub_data[] = { 0x0417e91c, }; -uint32_t nvc0_grhub_code[] = { +uint32_t gf100_grhub_code[] = { 0x039b0ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3 index afbe03ac9077..581b2d53ab0c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3 @@ -25,13 +25,13 @@ #define CHIPSET GF117 #include "macros.fuc" -.section #nvd7_grhub_data +.section #gf117_grhub_data #define INCLUDE_DATA #include "com.fuc" #include "hub.fuc" #undef INCLUDE_DATA -.section #nvd7_grhub_code +.section #gf117_grhub_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h index 62b0c7601d8b..7cb14e59dea1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nvd7_grhub_data[] = { +uint32_t gf117_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, /* 0x0004: hub_mmio_list_tail */ @@ -205,7 +205,7 @@ uint32_t nvd7_grhub_data[] = { 0x0417e91c, }; -uint32_t nvd7_grhub_code[] = { +uint32_t gf117_grhub_code[] = { 0x039b0ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3 index d4840f1879fd..d977d393b679 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3 @@ -25,13 +25,13 @@ #define CHIPSET GK100 #include "macros.fuc" -.section #nve0_grhub_data +.section #gk104_grhub_data #define INCLUDE_DATA #include "com.fuc" #include "hub.fuc" #undef INCLUDE_DATA -.section #nve0_grhub_code +.section #gk104_grhub_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h index 51c3797d8537..95ac15110049 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nve0_grhub_data[] = { +uint32_t gk104_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, /* 0x0004: hub_mmio_list_tail */ @@ -205,7 +205,7 @@ uint32_t nve0_grhub_data[] = { 0x0417e91c, }; -uint32_t nve0_grhub_code[] = { +uint32_t gk104_grhub_code[] = { 0x039b0ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3 index ec42ed29b50d..760b4632f22d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3 @@ -25,13 +25,13 @@ #define CHIPSET GK110 #include "macros.fuc" -.section #nvf0_grhub_data +.section #gk110_grhub_data #define INCLUDE_DATA #include "com.fuc" #include "hub.fuc" #undef INCLUDE_DATA -.section #nvf0_grhub_code +.section #gk110_grhub_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h index a0af4b703a8e..89986878480f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nvf0_grhub_data[] = { +uint32_t gk110_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, /* 0x0004: hub_mmio_list_tail */ @@ -205,7 +205,7 @@ uint32_t nvf0_grhub_data[] = { 0x0417e91c, }; -uint32_t nvf0_grhub_code[] = { +uint32_t gk110_grhub_code[] = { 0x039b0ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5 index 7c5d25630fa8..43243a35f6dc 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5 @@ -25,13 +25,13 @@ #define CHIPSET GK208 #include "macros.fuc" -.section #nv108_grhub_data +.section #gk208_grhub_data #define INCLUDE_DATA #include "com.fuc" #include "hub.fuc" #undef INCLUDE_DATA -.section #nv108_grhub_code +.section #gk208_grhub_code #define INCLUDE_CODE bra #init #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h index e49b5a877ae4..0e98fa4a386e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h @@ -1,4 +1,4 @@ -uint32_t nv108_grhub_data[] = { +uint32_t gk208_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, /* 0x0004: hub_mmio_list_tail */ @@ -205,7 +205,7 @@ uint32_t nv108_grhub_data[] = { 0x0417e91c, }; -uint32_t nv108_grhub_code[] = { +uint32_t gk208_grhub_code[] = { 0x030e0ef5, /* 0x0004: queue_put */ 0x9800d898, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5 index 27591b3086a5..27591b3086a5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5 +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5 diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h index 5f953c5c20b7..5f953c5c20b7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc index 2a0b0f844299..2a0b0f844299 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h index 1718ae4e8224..1718ae4e8224 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 17251e4b9e86..1dd482e9da77 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -21,16 +21,28 @@ * * Authors: Ben Skeggs */ - -#include "nvc0.h" -#include "ctxnvc0.h" +#include "gf100.h" +#include "ctxgf100.h" +#include "fuc/os.h" + +#include <core/client.h> +#include <core/device.h> +#include <core/handle.h> +#include <core/option.h> +#include <engine/fifo.h> +#include <subdev/fb.h> +#include <subdev/mc.h> +#include <subdev/timer.h> + +#include <nvif/class.h> +#include <nvif/unpack.h> /******************************************************************************* * Zero Bandwidth Clear ******************************************************************************/ static void -nvc0_graph_zbc_clear_color(struct nvc0_graph_priv *priv, int zbc) +gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc) { if (priv->zbc_color[zbc].format) { nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]); @@ -44,10 +56,10 @@ nvc0_graph_zbc_clear_color(struct nvc0_graph_priv *priv, int zbc) } static int -nvc0_graph_zbc_color_get(struct nvc0_graph_priv *priv, int format, - const u32 ds[4], const u32 l2[4]) +gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format, + const u32 ds[4], const u32 l2[4]) { - struct nouveau_ltc *ltc = nouveau_ltc(priv); + struct nvkm_ltc *ltc = nvkm_ltc(priv); int zbc = -ENOSPC, i; for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { @@ -75,12 +87,12 @@ nvc0_graph_zbc_color_get(struct nvc0_graph_priv *priv, int format, memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2)); priv->zbc_color[zbc].format = format; ltc->zbc_color_get(ltc, zbc, l2); - nvc0_graph_zbc_clear_color(priv, zbc); + gf100_gr_zbc_clear_color(priv, zbc); return zbc; } static void -nvc0_graph_zbc_clear_depth(struct nvc0_graph_priv *priv, int zbc) +gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc) { if (priv->zbc_depth[zbc].format) nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds); @@ -90,10 +102,10 @@ nvc0_graph_zbc_clear_depth(struct nvc0_graph_priv *priv, int zbc) } static int -nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format, - const u32 ds, const u32 l2) +gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format, + const u32 ds, const u32 l2) { - struct nouveau_ltc *ltc = nouveau_ltc(priv); + struct nvkm_ltc *ltc = nvkm_ltc(priv); int zbc = -ENOSPC, i; for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { @@ -119,7 +131,7 @@ nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format, priv->zbc_depth[zbc].ds = ds; priv->zbc_depth[zbc].l2 = l2; ltc->zbc_depth_get(ltc, zbc, l2); - nvc0_graph_zbc_clear_depth(priv, zbc); + gf100_gr_zbc_clear_depth(priv, zbc); return zbc; } @@ -128,9 +140,9 @@ nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format, ******************************************************************************/ static int -nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size) +gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) { - struct nvc0_graph_priv *priv = (void *)object->engine; + struct gf100_gr_priv *priv = (void *)object->engine; union { struct fermi_a_zbc_color_v0 v0; } *args = data; @@ -157,9 +169,9 @@ nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size) case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: - ret = nvc0_graph_zbc_color_get(priv, args->v0.format, - args->v0.ds, - args->v0.l2); + ret = gf100_gr_zbc_color_get(priv, args->v0.format, + args->v0.ds, + args->v0.l2); if (ret >= 0) { args->v0.index = ret; return 0; @@ -174,9 +186,9 @@ nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size) } static int -nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size) +gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) { - struct nvc0_graph_priv *priv = (void *)object->engine; + struct gf100_gr_priv *priv = (void *)object->engine; union { struct fermi_a_zbc_depth_v0 v0; } *args = data; @@ -185,9 +197,9 @@ nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size) if (nvif_unpack(args->v0, 0, 0, false)) { switch (args->v0.format) { case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: - ret = nvc0_graph_zbc_depth_get(priv, args->v0.format, - args->v0.ds, - args->v0.l2); + ret = gf100_gr_zbc_depth_get(priv, args->v0.format, + args->v0.ds, + args->v0.l2); return (ret >= 0) ? 0 : -ENOSPC; default: return -EINVAL; @@ -198,33 +210,33 @@ nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size) } static int -nvc0_fermi_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size) +gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { switch (mthd) { case FERMI_A_ZBC_COLOR: - return nvc0_fermi_mthd_zbc_color(object, data, size); + return gf100_fermi_mthd_zbc_color(object, data, size); case FERMI_A_ZBC_DEPTH: - return nvc0_fermi_mthd_zbc_depth(object, data, size); + return gf100_fermi_mthd_zbc_depth(object, data, size); default: break; } return -EINVAL; } -struct nouveau_ofuncs -nvc0_fermi_ofuncs = { - .ctor = _nouveau_object_ctor, - .dtor = nouveau_object_destroy, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - .mthd = nvc0_fermi_mthd, +struct nvkm_ofuncs +gf100_fermi_ofuncs = { + .ctor = _nvkm_object_ctor, + .dtor = nvkm_object_destroy, + .init = nvkm_object_init, + .fini = nvkm_object_fini, + .mthd = gf100_fermi_mthd, }; static int -nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd, - void *pdata, u32 size) +gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, + void *pdata, u32 size) { - struct nvc0_graph_priv *priv = (void *)nv_engine(object); + struct gf100_gr_priv *priv = (void *)nv_engine(object); if (size >= sizeof(u32)) { u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; nv_wr32(priv, 0x419e44, data); @@ -234,24 +246,24 @@ nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd, return -EINVAL; } -struct nouveau_omthds -nvc0_graph_9097_omthds[] = { - { 0x1528, 0x1528, nvc0_graph_set_shader_exceptions }, +struct nvkm_omthds +gf100_gr_9097_omthds[] = { + { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, {} }; -struct nouveau_omthds -nvc0_graph_90c0_omthds[] = { - { 0x1528, 0x1528, nvc0_graph_set_shader_exceptions }, +struct nvkm_omthds +gf100_gr_90c0_omthds[] = { + { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, {} }; -struct nouveau_oclass -nvc0_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0x9039, &nouveau_object_ofuncs }, - { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +struct nvkm_oclass +gf100_gr_sclass[] = { + { 0x902d, &nvkm_object_ofuncs }, + { 0x9039, &nvkm_object_ofuncs }, + { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, {} }; @@ -260,22 +272,21 @@ nvc0_graph_sclass[] = { ******************************************************************************/ int -nvc0_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *args, u32 size, - struct nouveau_object **pobject) +gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *args, u32 size, + struct nvkm_object **pobject) { - struct nouveau_vm *vm = nouveau_client(parent)->vm; - struct nvc0_graph_priv *priv = (void *)engine; - struct nvc0_graph_data *data = priv->mmio_data; - struct nvc0_graph_mmio *mmio = priv->mmio_list; - struct nvc0_graph_chan *chan; + struct nvkm_vm *vm = nvkm_client(parent)->vm; + struct gf100_gr_priv *priv = (void *)engine; + struct gf100_gr_data *data = priv->mmio_data; + struct gf100_gr_mmio *mmio = priv->mmio_list; + struct gf100_gr_chan *chan; int ret, i; /* allocate memory for context, and fill with default values */ - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, - priv->size, 0x100, - NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, + priv->size, 0x100, + NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -284,26 +295,26 @@ nvc0_graph_context_ctor(struct nouveau_object *parent, * fuc to modify some per-context register settings on first load * of the context. */ - ret = nouveau_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, - &chan->mmio); + ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, + &chan->mmio); if (ret) return ret; - ret = nouveau_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, - NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, - &chan->mmio_vma); + ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, + NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, + &chan->mmio_vma); if (ret) return ret; /* allocate buffers referenced by mmio list */ for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) { - ret = nouveau_gpuobj_new(nv_object(chan), NULL, data->size, - data->align, 0, &chan->data[i].mem); + ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size, + data->align, 0, &chan->data[i].mem); if (ret) return ret; - ret = nouveau_gpuobj_map_vm(chan->data[i].mem, vm, data->access, - &chan->data[i].vma); + ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access, + &chan->data[i].vma); if (ret) return ret; @@ -347,28 +358,28 @@ nvc0_graph_context_ctor(struct nouveau_object *parent, } void -nvc0_graph_context_dtor(struct nouveau_object *object) +gf100_gr_context_dtor(struct nvkm_object *object) { - struct nvc0_graph_chan *chan = (void *)object; + struct gf100_gr_chan *chan = (void *)object; int i; for (i = 0; i < ARRAY_SIZE(chan->data); i++) { - nouveau_gpuobj_unmap(&chan->data[i].vma); - nouveau_gpuobj_ref(NULL, &chan->data[i].mem); + nvkm_gpuobj_unmap(&chan->data[i].vma); + nvkm_gpuobj_ref(NULL, &chan->data[i].mem); } - nouveau_gpuobj_unmap(&chan->mmio_vma); - nouveau_gpuobj_ref(NULL, &chan->mmio); + nvkm_gpuobj_unmap(&chan->mmio_vma); + nvkm_gpuobj_ref(NULL, &chan->mmio); - nouveau_graph_context_destroy(&chan->base); + nvkm_gr_context_destroy(&chan->base); } /******************************************************************************* * PGRAPH register lists ******************************************************************************/ -const struct nvc0_graph_init -nvc0_graph_init_main_0[] = { +const struct gf100_gr_init +gf100_gr_init_main_0[] = { { 0x400080, 1, 0x04, 0x003083c2 }, { 0x400088, 1, 0x04, 0x00006fe7 }, { 0x40008c, 1, 0x04, 0x00000000 }, @@ -383,53 +394,53 @@ nvc0_graph_init_main_0[] = { {} }; -const struct nvc0_graph_init -nvc0_graph_init_fe_0[] = { +const struct gf100_gr_init +gf100_gr_init_fe_0[] = { { 0x40415c, 1, 0x04, 0x00000000 }, { 0x404170, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_pri_0[] = { +const struct gf100_gr_init +gf100_gr_init_pri_0[] = { { 0x404488, 2, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_rstr2d_0[] = { +const struct gf100_gr_init +gf100_gr_init_rstr2d_0[] = { { 0x407808, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_pd_0[] = { +const struct gf100_gr_init +gf100_gr_init_pd_0[] = { { 0x406024, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_ds_0[] = { +const struct gf100_gr_init +gf100_gr_init_ds_0[] = { { 0x405844, 1, 0x04, 0x00ffffff }, { 0x405850, 1, 0x04, 0x00000000 }, { 0x405908, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_scc_0[] = { +const struct gf100_gr_init +gf100_gr_init_scc_0[] = { { 0x40803c, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_prop_0[] = { +const struct gf100_gr_init +gf100_gr_init_prop_0[] = { { 0x4184a0, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_gpc_unk_0[] = { +const struct gf100_gr_init +gf100_gr_init_gpc_unk_0[] = { { 0x418604, 1, 0x04, 0x00000000 }, { 0x418680, 1, 0x04, 0x00000000 }, { 0x418714, 1, 0x04, 0x80000000 }, @@ -437,20 +448,20 @@ nvc0_graph_init_gpc_unk_0[] = { {} }; -const struct nvc0_graph_init -nvc0_graph_init_setup_0[] = { +const struct gf100_gr_init +gf100_gr_init_setup_0[] = { { 0x418814, 3, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_crstr_0[] = { +const struct gf100_gr_init +gf100_gr_init_crstr_0[] = { { 0x418b04, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_setup_1[] = { +const struct gf100_gr_init +gf100_gr_init_setup_1[] = { { 0x4188c8, 1, 0x04, 0x80000000 }, { 0x4188cc, 1, 0x04, 0x00000000 }, { 0x4188d0, 1, 0x04, 0x00010000 }, @@ -458,8 +469,8 @@ nvc0_graph_init_setup_1[] = { {} }; -const struct nvc0_graph_init -nvc0_graph_init_zcull_0[] = { +const struct gf100_gr_init +gf100_gr_init_zcull_0[] = { { 0x418910, 1, 0x04, 0x00010001 }, { 0x418914, 1, 0x04, 0x00000301 }, { 0x418918, 1, 0x04, 0x00800000 }, @@ -468,15 +479,15 @@ nvc0_graph_init_zcull_0[] = { {} }; -const struct nvc0_graph_init -nvc0_graph_init_gpm_0[] = { +const struct gf100_gr_init +gf100_gr_init_gpm_0[] = { { 0x418c04, 1, 0x04, 0x00000000 }, { 0x418c88, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_gpc_unk_1[] = { +const struct gf100_gr_init +gf100_gr_init_gpc_unk_1[] = { { 0x418d00, 1, 0x04, 0x00000000 }, { 0x418f08, 1, 0x04, 0x00000000 }, { 0x418e00, 1, 0x04, 0x00000050 }, @@ -484,30 +495,30 @@ nvc0_graph_init_gpc_unk_1[] = { {} }; -const struct nvc0_graph_init -nvc0_graph_init_gcc_0[] = { +const struct gf100_gr_init +gf100_gr_init_gcc_0[] = { { 0x41900c, 1, 0x04, 0x00000000 }, { 0x419018, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_tpccs_0[] = { +const struct gf100_gr_init +gf100_gr_init_tpccs_0[] = { { 0x419d08, 2, 0x04, 0x00000000 }, { 0x419d10, 1, 0x04, 0x00000014 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_tex_0[] = { +const struct gf100_gr_init +gf100_gr_init_tex_0[] = { { 0x419ab0, 1, 0x04, 0x00000000 }, { 0x419ab8, 1, 0x04, 0x000000e7 }, { 0x419abc, 2, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_pe_0[] = { +const struct gf100_gr_init +gf100_gr_init_pe_0[] = { { 0x41980c, 3, 0x04, 0x00000000 }, { 0x419844, 1, 0x04, 0x00000000 }, { 0x41984c, 1, 0x04, 0x00005bc5 }, @@ -515,8 +526,8 @@ nvc0_graph_init_pe_0[] = { {} }; -const struct nvc0_graph_init -nvc0_graph_init_l1c_0[] = { +const struct gf100_gr_init +gf100_gr_init_l1c_0[] = { { 0x419c98, 1, 0x04, 0x00000000 }, { 0x419ca8, 1, 0x04, 0x80000000 }, { 0x419cb4, 1, 0x04, 0x00000000 }, @@ -526,27 +537,27 @@ nvc0_graph_init_l1c_0[] = { {} }; -const struct nvc0_graph_init -nvc0_graph_init_wwdx_0[] = { +const struct gf100_gr_init +gf100_gr_init_wwdx_0[] = { { 0x419bd4, 1, 0x04, 0x00800000 }, { 0x419bdc, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_tpccs_1[] = { +const struct gf100_gr_init +gf100_gr_init_tpccs_1[] = { { 0x419d2c, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_mpc_0[] = { +const struct gf100_gr_init +gf100_gr_init_mpc_0[] = { { 0x419c0c, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -nvc0_graph_init_sm_0[] = { +static const struct gf100_gr_init +gf100_gr_init_sm_0[] = { { 0x419e00, 1, 0x04, 0x00000000 }, { 0x419ea0, 1, 0x04, 0x00000000 }, { 0x419ea4, 1, 0x04, 0x00000100 }, @@ -563,8 +574,8 @@ nvc0_graph_init_sm_0[] = { {} }; -const struct nvc0_graph_init -nvc0_graph_init_be_0[] = { +const struct gf100_gr_init +gf100_gr_init_be_0[] = { { 0x40880c, 1, 0x04, 0x00000000 }, { 0x408910, 9, 0x04, 0x00000000 }, { 0x408950, 1, 0x04, 0x00000000 }, @@ -575,47 +586,47 @@ nvc0_graph_init_be_0[] = { {} }; -const struct nvc0_graph_init -nvc0_graph_init_fe_1[] = { +const struct gf100_gr_init +gf100_gr_init_fe_1[] = { { 0x4040f0, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvc0_graph_init_pe_1[] = { +const struct gf100_gr_init +gf100_gr_init_pe_1[] = { { 0x419880, 1, 0x04, 0x00000002 }, {} }; -static const struct nvc0_graph_pack -nvc0_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { nvc0_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvc0_graph_init_prop_0 }, - { nvc0_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc0_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { nvc0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvc0_graph_init_tex_0 }, - { nvc0_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_wwdx_0 }, - { nvc0_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvc0_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - { nvc0_graph_init_pe_1 }, +static const struct gf100_gr_pack +gf100_gr_pack_mmio[] = { + { gf100_gr_init_main_0 }, + { gf100_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf100_gr_init_pd_0 }, + { gf100_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gf100_gr_init_prop_0 }, + { gf100_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gf100_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf100_gr_init_gpm_0 }, + { gf100_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gf100_gr_init_tpccs_0 }, + { gf100_gr_init_tex_0 }, + { gf100_gr_init_pe_0 }, + { gf100_gr_init_l1c_0 }, + { gf100_gr_init_wwdx_0 }, + { gf100_gr_init_tpccs_1 }, + { gf100_gr_init_mpc_0 }, + { gf100_gr_init_sm_0 }, + { gf100_gr_init_be_0 }, + { gf100_gr_init_fe_1 }, + { gf100_gr_init_pe_1 }, {} }; @@ -624,7 +635,7 @@ nvc0_graph_pack_mmio[] = { ******************************************************************************/ void -nvc0_graph_zbc_init(struct nvc0_graph_priv *priv) +gf100_gr_zbc_init(struct gf100_gr_priv *priv) { const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; @@ -634,29 +645,29 @@ nvc0_graph_zbc_init(struct nvc0_graph_priv *priv) 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; - struct nouveau_ltc *ltc = nouveau_ltc(priv); + struct nvkm_ltc *ltc = nvkm_ltc(priv); int index; if (!priv->zbc_color[0].format) { - nvc0_graph_zbc_color_get(priv, 1, & zero[0], &zero[4]); - nvc0_graph_zbc_color_get(priv, 2, & one[0], &one[4]); - nvc0_graph_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]); - nvc0_graph_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]); - nvc0_graph_zbc_depth_get(priv, 1, 0x00000000, 0x00000000); - nvc0_graph_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000); + gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]); + gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]); + gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]); + gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]); + gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000); + gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000); } for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) - nvc0_graph_zbc_clear_color(priv, index); + gf100_gr_zbc_clear_color(priv, index); for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) - nvc0_graph_zbc_clear_depth(priv, index); + gf100_gr_zbc_clear_depth(priv, index); } void -nvc0_graph_mmio(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) +gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) { - const struct nvc0_graph_pack *pack; - const struct nvc0_graph_init *init; + const struct gf100_gr_pack *pack; + const struct gf100_gr_init *init; pack_for_each_init(init, pack, p) { u32 next = init->addr + init->count * init->pitch; @@ -669,10 +680,10 @@ nvc0_graph_mmio(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) } void -nvc0_graph_icmd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) +gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) { - const struct nvc0_graph_pack *pack; - const struct nvc0_graph_init *init; + const struct gf100_gr_pack *pack; + const struct gf100_gr_init *init; u32 data = 0; nv_wr32(priv, 0x400208, 0x80000000); @@ -697,10 +708,10 @@ nvc0_graph_icmd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) } void -nvc0_graph_mthd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) +gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) { - const struct nvc0_graph_pack *pack; - const struct nvc0_graph_init *init; + const struct gf100_gr_pack *pack; + const struct gf100_gr_init *init; u32 data = 0; pack_for_each_init(init, pack, p) { @@ -721,9 +732,9 @@ nvc0_graph_mthd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) } u64 -nvc0_graph_units(struct nouveau_graph *graph) +gf100_gr_units(struct nvkm_gr *gr) { - struct nvc0_graph_priv *priv = (void *)graph; + struct gf100_gr_priv *priv = (void *)gr; u64 cfg; cfg = (u32)priv->gpc_nr; @@ -733,7 +744,7 @@ nvc0_graph_units(struct nouveau_graph *graph) return cfg; } -static const struct nouveau_enum nve0_sked_error[] = { +static const struct nvkm_enum gk104_sked_error[] = { { 7, "CONSTANT_BUFFER_SIZE" }, { 9, "LOCAL_MEMORY_SIZE_POS" }, { 10, "LOCAL_MEMORY_SIZE_NEG" }, @@ -748,7 +759,7 @@ static const struct nouveau_enum nve0_sked_error[] = { {} }; -static const struct nouveau_enum nvc0_gpc_rop_error[] = { +static const struct nvkm_enum gf100_gpc_rop_error[] = { { 1, "RT_PITCH_OVERRUN" }, { 4, "RT_WIDTH_OVERRUN" }, { 5, "RT_HEIGHT_OVERRUN" }, @@ -759,7 +770,7 @@ static const struct nouveau_enum nvc0_gpc_rop_error[] = { }; static void -nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc) +gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc) { u32 trap[4]; int i; @@ -774,7 +785,7 @@ nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc) if (!(trap[0] & (1 << i))) continue; pr_cont(" "); - nouveau_enum_print(nvc0_gpc_rop_error, i); + nvkm_enum_print(gf100_gpc_rop_error, i); } pr_cont("\n"); @@ -784,7 +795,7 @@ nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc) nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); } -static const struct nouveau_enum nvc0_mp_warp_error[] = { +static const struct nvkm_enum gf100_mp_warp_error[] = { { 0x00, "NO_ERROR" }, { 0x01, "STACK_MISMATCH" }, { 0x05, "MISALIGNED_PC" }, @@ -797,23 +808,23 @@ static const struct nouveau_enum nvc0_mp_warp_error[] = { {} }; -static const struct nouveau_bitfield nvc0_mp_global_error[] = { +static const struct nvkm_bitfield gf100_mp_global_error[] = { { 0x00000004, "MULTIPLE_WARP_ERRORS" }, { 0x00000008, "OUT_OF_STACK_SPACE" }, {} }; static void -nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc) +gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc) { u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc); - nouveau_bitfield_print(nvc0_mp_global_error, gerr); + nvkm_bitfield_print(gf100_mp_global_error, gerr); if (werr) { pr_cont(" "); - nouveau_enum_print(nvc0_mp_warp_error, werr & 0xffff); + nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff); } pr_cont("\n"); @@ -822,7 +833,7 @@ nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc) } static void -nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc) +gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc) { u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508)); @@ -834,7 +845,7 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc) } if (stat & 0x00000002) { - nvc0_graph_trap_mp(priv, gpc, tpc); + gf100_gr_trap_mp(priv, gpc, tpc); stat &= ~0x00000002; } @@ -858,13 +869,13 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc) } static void -nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) +gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc) { u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); int tpc; if (stat & 0x00000001) { - nvc0_graph_trap_gpc_rop(priv, gpc); + gf100_gr_trap_gpc_rop(priv, gpc); stat &= ~0x00000001; } @@ -892,7 +903,7 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { u32 mask = 0x00010000 << tpc; if (stat & mask) { - nvc0_graph_trap_tpc(priv, gpc, tpc); + gf100_gr_trap_tpc(priv, gpc, tpc); nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask); stat &= ~mask; } @@ -904,7 +915,7 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) } static void -nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) +gf100_gr_trap_intr(struct gf100_gr_priv *priv) { u32 trap = nv_rd32(priv, 0x400108); int rop, gpc, i; @@ -965,7 +976,7 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) if (!(stat & (1 << i))) continue; pr_cont(" "); - nouveau_enum_print(nve0_sked_error, i); + nvkm_enum_print(gk104_sked_error, i); } pr_cont("\n"); @@ -980,7 +991,7 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { u32 mask = 0x00000001 << gpc; if (stat & mask) { - nvc0_graph_trap_gpc(priv, gpc); + gf100_gr_trap_gpc(priv, gpc); nv_wr32(priv, 0x400118, mask); stat &= ~mask; } @@ -1009,7 +1020,7 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) } static void -nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base) +gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base) { nv_error(priv, "%06x - done 0x%08x\n", base, nv_rd32(priv, base + 0x400)); @@ -1022,18 +1033,18 @@ nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base) } void -nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv) +gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv) { u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; u32 gpc; - nvc0_graph_ctxctl_debug_unit(priv, 0x409000); + gf100_gr_ctxctl_debug_unit(priv, 0x409000); for (gpc = 0; gpc < gpcnr; gpc++) - nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); + gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); } static void -nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) +gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv) { u32 stat = nv_rd32(priv, 0x409c18); @@ -1059,26 +1070,26 @@ nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) if (stat & 0x00080000) { nv_error(priv, "FECS watchdog timeout\n"); - nvc0_graph_ctxctl_debug(priv); + gf100_gr_ctxctl_debug(priv); nv_wr32(priv, 0x409c20, 0x00080000); stat &= ~0x00080000; } if (stat) { nv_error(priv, "FECS 0x%08x\n", stat); - nvc0_graph_ctxctl_debug(priv); + gf100_gr_ctxctl_debug(priv); nv_wr32(priv, 0x409c20, stat); } } static void -nvc0_graph_intr(struct nouveau_subdev *subdev) +gf100_gr_intr(struct nvkm_subdev *subdev) { - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle; - struct nvc0_graph_priv *priv = (void *)subdev; + struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_engine *engine = nv_engine(subdev); + struct nvkm_object *engctx; + struct nvkm_handle *handle; + struct gf100_gr_priv *priv = (void *)subdev; u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff; u32 stat = nv_rd32(priv, 0x400100); u32 addr = nv_rd32(priv, 0x400704); @@ -1089,18 +1100,18 @@ nvc0_graph_intr(struct nouveau_subdev *subdev) u32 class = nv_rd32(priv, 0x404200 + (subc * 4)); int chid; - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); chid = pfifo->chid(pfifo, engctx); if (stat & 0x00000010) { - handle = nouveau_handle_get_class(engctx, class); + handle = nvkm_handle_get_class(engctx, class); if (!handle || nv_call(handle->object, mthd, data)) { nv_error(priv, "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nouveau_client_name(engctx), + chid, inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); } - nouveau_handle_put(handle); + nvkm_handle_put(handle); nv_wr32(priv, 0x400100, 0x00000010); stat &= ~0x00000010; } @@ -1108,7 +1119,7 @@ nvc0_graph_intr(struct nouveau_subdev *subdev) if (stat & 0x00000020) { nv_error(priv, "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nouveau_client_name(engctx), subc, + chid, inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); nv_wr32(priv, 0x400100, 0x00000020); stat &= ~0x00000020; @@ -1116,9 +1127,9 @@ nvc0_graph_intr(struct nouveau_subdev *subdev) if (stat & 0x00100000) { nv_error(priv, "DATA_ERROR ["); - nouveau_enum_print(nv50_data_error_names, code); + nvkm_enum_print(nv50_data_error_names, code); pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nouveau_client_name(engctx), subc, + chid, inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); nv_wr32(priv, 0x400100, 0x00100000); stat &= ~0x00100000; @@ -1126,14 +1137,14 @@ nvc0_graph_intr(struct nouveau_subdev *subdev) if (stat & 0x00200000) { nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, - nouveau_client_name(engctx)); - nvc0_graph_trap_intr(priv); + nvkm_client_name(engctx)); + gf100_gr_trap_intr(priv); nv_wr32(priv, 0x400100, 0x00200000); stat &= ~0x00200000; } if (stat & 0x00080000) { - nvc0_graph_ctxctl_isr(priv); + gf100_gr_ctxctl_isr(priv); nv_wr32(priv, 0x400100, 0x00080000); stat &= ~0x00080000; } @@ -1144,12 +1155,12 @@ nvc0_graph_intr(struct nouveau_subdev *subdev) } nv_wr32(priv, 0x400500, 0x00010001); - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } void -nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, - struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data) +gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base, + struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) { int i; @@ -1170,12 +1181,12 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, } static void -nvc0_graph_init_csdata(struct nvc0_graph_priv *priv, - const struct nvc0_graph_pack *pack, - u32 falcon, u32 starstar, u32 base) +gf100_gr_init_csdata(struct gf100_gr_priv *priv, + const struct gf100_gr_pack *pack, + u32 falcon, u32 starstar, u32 base) { - const struct nvc0_graph_pack *iter; - const struct nvc0_graph_init *init; + const struct gf100_gr_pack *iter; + const struct gf100_gr_init *init; u32 addr = ~0, prev = ~0, xfer = 0; u32 star, temp; @@ -1211,20 +1222,20 @@ nvc0_graph_init_csdata(struct nvc0_graph_priv *priv, } int -nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) +gf100_gr_init_ctxctl(struct gf100_gr_priv *priv) { - struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass; - struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; + struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass; + struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; int i; if (priv->firmware) { /* load fuc microcode */ - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); - nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c, - &priv->fuc409d); - nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac, - &priv->fuc41ad); - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); + gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c, + &priv->fuc409d); + gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac, + &priv->fuc41ad); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); /* start both of them running */ nv_wr32(priv, 0x409840, 0xffffffff); @@ -1297,7 +1308,7 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) } if (priv->data == NULL) { - int ret = nvc0_grctx_generate(priv); + int ret = gf100_grctx_generate(priv); if (ret) { nv_error(priv, "failed to construct context\n"); return ret; @@ -1311,7 +1322,7 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) } /* load HUB microcode */ - nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); nv_wr32(priv, 0x4091c0, 0x01000000); for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); @@ -1334,26 +1345,26 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x41a188, i >> 6); nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); } - nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); + nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); /* load register lists */ - nvc0_graph_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); - nvc0_graph_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000); - nvc0_graph_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800); - nvc0_graph_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00); + gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); + gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000); + gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800); + gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00); /* start HUB ucode running, it'll init the GPCs */ nv_wr32(priv, 0x40910c, 0x00000000); nv_wr32(priv, 0x409100, 0x00000002); if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { nv_error(priv, "HUB_INIT timed out\n"); - nvc0_graph_ctxctl_debug(priv); + gf100_gr_ctxctl_debug(priv); return -EBUSY; } priv->size = nv_rd32(priv, 0x409804); if (priv->data == NULL) { - int ret = nvc0_grctx_generate(priv); + int ret = gf100_grctx_generate(priv); if (ret) { nv_error(priv, "failed to construct context\n"); return ret; @@ -1364,17 +1375,17 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) } int -nvc0_graph_init(struct nouveau_object *object) +gf100_gr_init(struct nvkm_object *object) { - struct nvc0_graph_oclass *oclass = (void *)object->oclass; - struct nvc0_graph_priv *priv = (void *)object; + struct gf100_gr_oclass *oclass = (void *)object->oclass; + struct gf100_gr_priv *priv = (void *)object; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; int ret, i; - ret = nouveau_graph_init(&priv->base); + ret = nvkm_gr_init(&priv->base); if (ret) return ret; @@ -1387,7 +1398,7 @@ nvc0_graph_init(struct nouveau_object *object) nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); - nvc0_graph_mmio(priv, oclass->mmio); + gf100_gr_mmio(priv, oclass->mmio); memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); for (i = 0, gpc = -1; i < priv->tpc_total; i++) { @@ -1470,23 +1481,23 @@ nvc0_graph_init(struct nouveau_object *object) nv_wr32(priv, 0x400054, 0x34ce3464); - nvc0_graph_zbc_init(priv); + gf100_gr_zbc_init(priv); - return nvc0_graph_init_ctxctl(priv); + return gf100_gr_init_ctxctl(priv); } static void -nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc) +gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) { kfree(fuc->data); fuc->data = NULL; } int -nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname, - struct nvc0_graph_fuc *fuc) +gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname, + struct gf100_gr_fuc *fuc) { - struct nouveau_device *device = nv_device(priv); + struct nvkm_device *device = nv_device(priv); const struct firmware *fw; char f[32]; int ret; @@ -1509,65 +1520,65 @@ nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname, } void -nvc0_graph_dtor(struct nouveau_object *object) +gf100_gr_dtor(struct nvkm_object *object) { - struct nvc0_graph_priv *priv = (void *)object; + struct gf100_gr_priv *priv = (void *)object; kfree(priv->data); - nvc0_graph_dtor_fw(&priv->fuc409c); - nvc0_graph_dtor_fw(&priv->fuc409d); - nvc0_graph_dtor_fw(&priv->fuc41ac); - nvc0_graph_dtor_fw(&priv->fuc41ad); + gf100_gr_dtor_fw(&priv->fuc409c); + gf100_gr_dtor_fw(&priv->fuc409d); + gf100_gr_dtor_fw(&priv->fuc41ac); + gf100_gr_dtor_fw(&priv->fuc41ad); - nouveau_gpuobj_ref(NULL, &priv->unk4188b8); - nouveau_gpuobj_ref(NULL, &priv->unk4188b4); + nvkm_gpuobj_ref(NULL, &priv->unk4188b8); + nvkm_gpuobj_ref(NULL, &priv->unk4188b4); - nouveau_graph_destroy(&priv->base); + nvkm_gr_destroy(&priv->base); } int -nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *bclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *bclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_graph_oclass *oclass = (void *)bclass; - struct nouveau_device *device = nv_device(parent); - struct nvc0_graph_priv *priv; + struct gf100_gr_oclass *oclass = (void *)bclass; + struct nvkm_device *device = nv_device(parent); + struct gf100_gr_priv *priv; bool use_ext_fw, enable; int ret, i, j; - use_ext_fw = nouveau_boolopt(device->cfgopt, "NvGrUseFW", - oclass->fecs.ucode == NULL); + use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW", + oclass->fecs.ucode == NULL); enable = use_ext_fw || oclass->fecs.ucode != NULL; - ret = nouveau_graph_create(parent, engine, bclass, enable, &priv); + ret = nvkm_gr_create(parent, engine, bclass, enable, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x08001000; - nv_subdev(priv)->intr = nvc0_graph_intr; + nv_subdev(priv)->intr = gf100_gr_intr; - priv->base.units = nvc0_graph_units; + priv->base.units = gf100_gr_units; if (use_ext_fw) { nv_info(priv, "using external firmware\n"); - if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) || - nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) || - nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || - nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) + if (gf100_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) || + gf100_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) || + gf100_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || + gf100_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) return -ENODEV; priv->firmware = true; } - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b4); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, + &priv->unk4188b4); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b8); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, + &priv->unk4188b8); if (ret) return ret; @@ -1630,38 +1641,38 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -#include "fuc/hubnvc0.fuc.h" +#include "fuc/hubgf100.fuc3.h" -struct nvc0_graph_ucode -nvc0_graph_fecs_ucode = { - .code.data = nvc0_grhub_code, - .code.size = sizeof(nvc0_grhub_code), - .data.data = nvc0_grhub_data, - .data.size = sizeof(nvc0_grhub_data), +struct gf100_gr_ucode +gf100_gr_fecs_ucode = { + .code.data = gf100_grhub_code, + .code.size = sizeof(gf100_grhub_code), + .data.data = gf100_grhub_data, + .data.size = sizeof(gf100_grhub_data), }; -#include "fuc/gpcnvc0.fuc.h" +#include "fuc/gpcgf100.fuc3.h" -struct nvc0_graph_ucode -nvc0_graph_gpccs_ucode = { - .code.data = nvc0_grgpc_code, - .code.size = sizeof(nvc0_grgpc_code), - .data.data = nvc0_grgpc_data, - .data.size = sizeof(nvc0_grgpc_data), +struct gf100_gr_ucode +gf100_gr_gpccs_ucode = { + .code.data = gf100_grgpc_code, + .code.size = sizeof(gf100_grgpc_code), + .data.data = gf100_grgpc_data, + .data.size = sizeof(gf100_grgpc_data), }; -struct nouveau_oclass * -nvc0_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gf100_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gf100_gr_init, + .fini = _nvkm_gr_fini, }, - .cclass = &nvc0_grctx_oclass, - .sclass = nvc0_graph_sclass, - .mmio = nvc0_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, + .cclass = &gf100_grctx_oclass, + .sclass = gf100_gr_sclass, + .mmio = gf100_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h new file mode 100644 index 000000000000..aeeca1be9cf0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -0,0 +1,250 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#ifndef __NVC0_GR_H__ +#define __NVC0_GR_H__ +#include <engine/gr.h> + +#include <subdev/ltc.h> + +#define GPC_MAX 32 +#define TPC_MAX (GPC_MAX * 8) + +#define ROP_BCAST(r) (0x408800 + (r)) +#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r)) +#define GPC_BCAST(r) (0x418000 + (r)) +#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r)) +#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r)) +#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r)) + +struct gf100_gr_data { + u32 size; + u32 align; + u32 access; +}; + +struct gf100_gr_mmio { + u32 addr; + u32 data; + u32 shift; + int buffer; +}; + +struct gf100_gr_fuc { + u32 *data; + u32 size; +}; + +struct gf100_gr_zbc_color { + u32 format; + u32 ds[4]; + u32 l2[4]; +}; + +struct gf100_gr_zbc_depth { + u32 format; + u32 ds; + u32 l2; +}; + +struct gf100_gr_priv { + struct nvkm_gr base; + + struct gf100_gr_fuc fuc409c; + struct gf100_gr_fuc fuc409d; + struct gf100_gr_fuc fuc41ac; + struct gf100_gr_fuc fuc41ad; + bool firmware; + + struct gf100_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT]; + struct gf100_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT]; + + u8 rop_nr; + u8 gpc_nr; + u8 tpc_nr[GPC_MAX]; + u8 tpc_total; + u8 ppc_nr[GPC_MAX]; + u8 ppc_tpc_nr[GPC_MAX][4]; + + struct nvkm_gpuobj *unk4188b4; + struct nvkm_gpuobj *unk4188b8; + + struct gf100_gr_data mmio_data[4]; + struct gf100_gr_mmio mmio_list[4096/8]; + u32 size; + u32 *data; + + u8 magic_not_rop_nr; +}; + +struct gf100_gr_chan { + struct nvkm_gr_chan base; + + struct nvkm_gpuobj *mmio; + struct nvkm_vma mmio_vma; + int mmio_nr; + struct { + struct nvkm_gpuobj *mem; + struct nvkm_vma vma; + } data[4]; +}; + +int gf100_gr_context_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gf100_gr_context_dtor(struct nvkm_object *); + +void gf100_gr_ctxctl_debug(struct gf100_gr_priv *); + +u64 gf100_gr_units(struct nvkm_gr *); +int gf100_gr_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *data, u32 size, + struct nvkm_object **); +void gf100_gr_dtor(struct nvkm_object *); +int gf100_gr_init(struct nvkm_object *); +void gf100_gr_zbc_init(struct gf100_gr_priv *); + +int gk104_gr_fini(struct nvkm_object *, bool); +int gk104_gr_init(struct nvkm_object *); + +int gk110_gr_fini(struct nvkm_object *, bool); + +extern struct nvkm_ofuncs gf100_fermi_ofuncs; + +extern struct nvkm_oclass gf100_gr_sclass[]; +extern struct nvkm_omthds gf100_gr_9097_omthds[]; +extern struct nvkm_omthds gf100_gr_90c0_omthds[]; +extern struct nvkm_oclass gf110_gr_sclass[]; +extern struct nvkm_oclass gk110_gr_sclass[]; + +struct gf100_gr_init { + u32 addr; + u8 count; + u8 pitch; + u32 data; +}; + +struct gf100_gr_pack { + const struct gf100_gr_init *init; + u32 type; +}; + +#define pack_for_each_init(init, pack, head) \ + for (pack = head; pack && pack->init; pack++) \ + for (init = pack->init; init && init->count; init++) + +struct gf100_gr_ucode { + struct gf100_gr_fuc code; + struct gf100_gr_fuc data; +}; + +extern struct gf100_gr_ucode gf100_gr_fecs_ucode; +extern struct gf100_gr_ucode gf100_gr_gpccs_ucode; + +extern struct gf100_gr_ucode gk110_gr_fecs_ucode; +extern struct gf100_gr_ucode gk110_gr_gpccs_ucode; + +struct gf100_gr_oclass { + struct nvkm_oclass base; + struct nvkm_oclass **cclass; + struct nvkm_oclass *sclass; + const struct gf100_gr_pack *mmio; + struct { + struct gf100_gr_ucode *ucode; + } fecs; + struct { + struct gf100_gr_ucode *ucode; + } gpccs; + int ppc_nr; +}; + +void gf100_gr_mmio(struct gf100_gr_priv *, const struct gf100_gr_pack *); +void gf100_gr_icmd(struct gf100_gr_priv *, const struct gf100_gr_pack *); +void gf100_gr_mthd(struct gf100_gr_priv *, const struct gf100_gr_pack *); +int gf100_gr_init_ctxctl(struct gf100_gr_priv *); + +/* register init value lists */ + +extern const struct gf100_gr_init gf100_gr_init_main_0[]; +extern const struct gf100_gr_init gf100_gr_init_fe_0[]; +extern const struct gf100_gr_init gf100_gr_init_pri_0[]; +extern const struct gf100_gr_init gf100_gr_init_rstr2d_0[]; +extern const struct gf100_gr_init gf100_gr_init_pd_0[]; +extern const struct gf100_gr_init gf100_gr_init_ds_0[]; +extern const struct gf100_gr_init gf100_gr_init_scc_0[]; +extern const struct gf100_gr_init gf100_gr_init_prop_0[]; +extern const struct gf100_gr_init gf100_gr_init_gpc_unk_0[]; +extern const struct gf100_gr_init gf100_gr_init_setup_0[]; +extern const struct gf100_gr_init gf100_gr_init_crstr_0[]; +extern const struct gf100_gr_init gf100_gr_init_setup_1[]; +extern const struct gf100_gr_init gf100_gr_init_zcull_0[]; +extern const struct gf100_gr_init gf100_gr_init_gpm_0[]; +extern const struct gf100_gr_init gf100_gr_init_gpc_unk_1[]; +extern const struct gf100_gr_init gf100_gr_init_gcc_0[]; +extern const struct gf100_gr_init gf100_gr_init_tpccs_0[]; +extern const struct gf100_gr_init gf100_gr_init_tex_0[]; +extern const struct gf100_gr_init gf100_gr_init_pe_0[]; +extern const struct gf100_gr_init gf100_gr_init_l1c_0[]; +extern const struct gf100_gr_init gf100_gr_init_wwdx_0[]; +extern const struct gf100_gr_init gf100_gr_init_tpccs_1[]; +extern const struct gf100_gr_init gf100_gr_init_mpc_0[]; +extern const struct gf100_gr_init gf100_gr_init_be_0[]; +extern const struct gf100_gr_init gf100_gr_init_fe_1[]; +extern const struct gf100_gr_init gf100_gr_init_pe_1[]; + +extern const struct gf100_gr_init gf104_gr_init_ds_0[]; +extern const struct gf100_gr_init gf104_gr_init_tex_0[]; +extern const struct gf100_gr_init gf104_gr_init_sm_0[]; + +extern const struct gf100_gr_init gf108_gr_init_gpc_unk_0[]; +extern const struct gf100_gr_init gf108_gr_init_setup_1[]; + +extern const struct gf100_gr_init gf119_gr_init_pd_0[]; +extern const struct gf100_gr_init gf119_gr_init_ds_0[]; +extern const struct gf100_gr_init gf119_gr_init_prop_0[]; +extern const struct gf100_gr_init gf119_gr_init_gpm_0[]; +extern const struct gf100_gr_init gf119_gr_init_gpc_unk_1[]; +extern const struct gf100_gr_init gf119_gr_init_tex_0[]; +extern const struct gf100_gr_init gf119_gr_init_sm_0[]; +extern const struct gf100_gr_init gf119_gr_init_fe_1[]; + +extern const struct gf100_gr_init gf117_gr_init_pes_0[]; +extern const struct gf100_gr_init gf117_gr_init_wwdx_0[]; +extern const struct gf100_gr_init gf117_gr_init_cbm_0[]; + +extern const struct gf100_gr_init gk104_gr_init_main_0[]; +extern const struct gf100_gr_init gk104_gr_init_tpccs_0[]; +extern const struct gf100_gr_init gk104_gr_init_pe_0[]; +extern const struct gf100_gr_init gk104_gr_init_be_0[]; +extern const struct gf100_gr_pack gk104_gr_pack_mmio[]; + +extern const struct gf100_gr_init gk110_gr_init_fe_0[]; +extern const struct gf100_gr_init gk110_gr_init_ds_0[]; +extern const struct gf100_gr_init gk110_gr_init_sked_0[]; +extern const struct gf100_gr_init gk110_gr_init_cwd_0[]; +extern const struct gf100_gr_init gk110_gr_init_gpc_unk_1[]; +extern const struct gf100_gr_init gk110_gr_init_tex_0[]; +extern const struct gf100_gr_init gk110_gr_init_sm_0[]; + +extern const struct gf100_gr_init gk208_gr_init_gpc_unk_0[]; +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c index e82e70c53132..20d3b85db3b5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c @@ -21,16 +21,15 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "nvc0.h" -#include "ctxnvc0.h" +#include "gf100.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH register lists ******************************************************************************/ -const struct nvc0_graph_init -nvc4_graph_init_ds_0[] = { +const struct gf100_gr_init +gf104_gr_init_ds_0[] = { { 0x405844, 1, 0x04, 0x00ffffff }, { 0x405850, 1, 0x04, 0x00000000 }, { 0x405900, 1, 0x04, 0x00002834 }, @@ -38,8 +37,8 @@ nvc4_graph_init_ds_0[] = { {} }; -const struct nvc0_graph_init -nvc4_graph_init_tex_0[] = { +const struct gf100_gr_init +gf104_gr_init_tex_0[] = { { 0x419ab0, 1, 0x04, 0x00000000 }, { 0x419ac8, 1, 0x04, 0x00000000 }, { 0x419ab8, 1, 0x04, 0x000000e7 }, @@ -47,8 +46,8 @@ nvc4_graph_init_tex_0[] = { {} }; -static const struct nvc0_graph_init -nvc4_graph_init_pe_0[] = { +static const struct gf100_gr_init +gf104_gr_init_pe_0[] = { { 0x41980c, 3, 0x04, 0x00000000 }, { 0x419844, 1, 0x04, 0x00000000 }, { 0x41984c, 1, 0x04, 0x00005bc5 }, @@ -57,8 +56,8 @@ nvc4_graph_init_pe_0[] = { {} }; -const struct nvc0_graph_init -nvc4_graph_init_sm_0[] = { +const struct gf100_gr_init +gf104_gr_init_sm_0[] = { { 0x419e00, 1, 0x04, 0x00000000 }, { 0x419ea0, 1, 0x04, 0x00000000 }, { 0x419ea4, 1, 0x04, 0x00000100 }, @@ -76,34 +75,34 @@ nvc4_graph_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack -nvc4_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { nvc4_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvc0_graph_init_prop_0 }, - { nvc0_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc0_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { nvc0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvc4_graph_init_tex_0 }, - { nvc4_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_wwdx_0 }, - { nvc0_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvc4_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, +static const struct gf100_gr_pack +gf104_gr_pack_mmio[] = { + { gf100_gr_init_main_0 }, + { gf100_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf100_gr_init_pd_0 }, + { gf104_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gf100_gr_init_prop_0 }, + { gf100_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gf100_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf100_gr_init_gpm_0 }, + { gf100_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gf100_gr_init_tpccs_0 }, + { gf104_gr_init_tex_0 }, + { gf104_gr_init_pe_0 }, + { gf100_gr_init_l1c_0 }, + { gf100_gr_init_wwdx_0 }, + { gf100_gr_init_tpccs_1 }, + { gf100_gr_init_mpc_0 }, + { gf104_gr_init_sm_0 }, + { gf100_gr_init_be_0 }, + { gf100_gr_init_fe_1 }, {} }; @@ -111,18 +110,18 @@ nvc4_graph_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ -struct nouveau_oclass * -nvc4_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gf104_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xc3), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gf100_gr_init, + .fini = _nvkm_gr_fini, }, - .cclass = &nvc4_grctx_oclass, - .sclass = nvc0_graph_sclass, - .mmio = nvc4_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, + .cclass = &gf104_grctx_oclass, + .sclass = gf100_gr_sclass, + .mmio = gf104_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c index 93d58e5b82c2..5362c8176e64 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c @@ -21,21 +21,22 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "gf100.h" +#include "ctxgf100.h" -#include "nvc0.h" -#include "ctxnvc0.h" +#include <nvif/class.h> /******************************************************************************* * Graphics object classes ******************************************************************************/ -static struct nouveau_oclass -nvc1_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0x9039, &nouveau_object_ofuncs }, - { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +static struct nvkm_oclass +gf108_gr_sclass[] = { + { 0x902d, &nvkm_object_ofuncs }, + { 0x9039, &nvkm_object_ofuncs }, + { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, {} }; @@ -43,8 +44,8 @@ nvc1_graph_sclass[] = { * PGRAPH register lists ******************************************************************************/ -const struct nvc0_graph_init -nvc1_graph_init_gpc_unk_0[] = { +const struct gf100_gr_init +gf108_gr_init_gpc_unk_0[] = { { 0x418604, 1, 0x04, 0x00000000 }, { 0x418680, 1, 0x04, 0x00000000 }, { 0x418714, 1, 0x04, 0x00000000 }, @@ -52,16 +53,16 @@ nvc1_graph_init_gpc_unk_0[] = { {} }; -const struct nvc0_graph_init -nvc1_graph_init_setup_1[] = { +const struct gf100_gr_init +gf108_gr_init_setup_1[] = { { 0x4188c8, 2, 0x04, 0x00000000 }, { 0x4188d0, 1, 0x04, 0x00010000 }, { 0x4188d4, 1, 0x04, 0x00000001 }, {} }; -static const struct nvc0_graph_init -nvc1_graph_init_gpc_unk_1[] = { +static const struct gf100_gr_init +gf108_gr_init_gpc_unk_1[] = { { 0x418d00, 1, 0x04, 0x00000000 }, { 0x418f08, 1, 0x04, 0x00000000 }, { 0x418e00, 1, 0x04, 0x00000003 }, @@ -69,8 +70,8 @@ nvc1_graph_init_gpc_unk_1[] = { {} }; -static const struct nvc0_graph_init -nvc1_graph_init_pe_0[] = { +static const struct gf100_gr_init +gf108_gr_init_pe_0[] = { { 0x41980c, 1, 0x04, 0x00000010 }, { 0x419810, 1, 0x04, 0x00000000 }, { 0x419814, 1, 0x04, 0x00000004 }, @@ -81,34 +82,34 @@ nvc1_graph_init_pe_0[] = { {} }; -static const struct nvc0_graph_pack -nvc1_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { nvc4_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvc0_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { nvc1_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvc4_graph_init_tex_0 }, - { nvc1_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_wwdx_0 }, - { nvc0_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvc4_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, +static const struct gf100_gr_pack +gf108_gr_pack_mmio[] = { + { gf100_gr_init_main_0 }, + { gf100_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf100_gr_init_pd_0 }, + { gf104_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gf100_gr_init_prop_0 }, + { gf108_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gf108_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf100_gr_init_gpm_0 }, + { gf108_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gf100_gr_init_tpccs_0 }, + { gf104_gr_init_tex_0 }, + { gf108_gr_init_pe_0 }, + { gf100_gr_init_l1c_0 }, + { gf100_gr_init_wwdx_0 }, + { gf100_gr_init_tpccs_1 }, + { gf100_gr_init_mpc_0 }, + { gf104_gr_init_sm_0 }, + { gf100_gr_init_be_0 }, + { gf100_gr_init_fe_1 }, {} }; @@ -116,18 +117,18 @@ nvc1_graph_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ -struct nouveau_oclass * -nvc1_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gf108_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xc1), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gf100_gr_init, + .fini = _nvkm_gr_fini, }, - .cclass = &nvc1_grctx_oclass, - .sclass = nvc1_graph_sclass, - .mmio = nvc1_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, + .cclass = &gf108_grctx_oclass, + .sclass = gf108_gr_sclass, + .mmio = gf108_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c index 692e1eda0eb4..88beb491b7b8 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c @@ -21,22 +21,23 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "gf100.h" +#include "ctxgf100.h" -#include "nvc0.h" -#include "ctxnvc0.h" +#include <nvif/class.h> /******************************************************************************* * Graphics object classes ******************************************************************************/ -struct nouveau_oclass -nvc8_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0x9039, &nouveau_object_ofuncs }, - { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +struct nvkm_oclass +gf110_gr_sclass[] = { + { 0x902d, &nvkm_object_ofuncs }, + { 0x9039, &nvkm_object_ofuncs }, + { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { FERMI_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, {} }; @@ -44,8 +45,8 @@ nvc8_graph_sclass[] = { * PGRAPH register lists ******************************************************************************/ -static const struct nvc0_graph_init -nvc8_graph_init_sm_0[] = { +static const struct gf100_gr_init +gf110_gr_init_sm_0[] = { { 0x419e00, 1, 0x04, 0x00000000 }, { 0x419ea0, 1, 0x04, 0x00000000 }, { 0x419ea4, 1, 0x04, 0x00000100 }, @@ -62,35 +63,35 @@ nvc8_graph_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack -nvc8_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { nvc0_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvc0_graph_init_prop_0 }, - { nvc0_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { nvc0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvc0_graph_init_tex_0 }, - { nvc0_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_wwdx_0 }, - { nvc0_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvc8_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, - { nvc0_graph_init_pe_1 }, +static const struct gf100_gr_pack +gf110_gr_pack_mmio[] = { + { gf100_gr_init_main_0 }, + { gf100_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf100_gr_init_pd_0 }, + { gf100_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gf100_gr_init_prop_0 }, + { gf100_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gf108_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf100_gr_init_gpm_0 }, + { gf100_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gf100_gr_init_tpccs_0 }, + { gf100_gr_init_tex_0 }, + { gf100_gr_init_pe_0 }, + { gf100_gr_init_l1c_0 }, + { gf100_gr_init_wwdx_0 }, + { gf100_gr_init_tpccs_1 }, + { gf100_gr_init_mpc_0 }, + { gf110_gr_init_sm_0 }, + { gf100_gr_init_be_0 }, + { gf100_gr_init_fe_1 }, + { gf100_gr_init_pe_1 }, {} }; @@ -98,18 +99,18 @@ nvc8_graph_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ -struct nouveau_oclass * -nvc8_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gf110_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xc8), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gf100_gr_init, + .fini = _nvkm_gr_fini, }, - .cclass = &nvc8_grctx_oclass, - .sclass = nvc8_graph_sclass, - .mmio = nvc8_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, + .cclass = &gf110_grctx_oclass, + .sclass = gf110_gr_sclass, + .mmio = gf110_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c index 41e8445c7eea..871ac5f806f6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c @@ -21,16 +21,15 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "nvc0.h" -#include "ctxnvc0.h" +#include "gf100.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH register lists ******************************************************************************/ -static const struct nvc0_graph_init -nvd7_graph_init_pe_0[] = { +static const struct gf100_gr_init +gf117_gr_init_pe_0[] = { { 0x41980c, 1, 0x04, 0x00000010 }, { 0x419844, 1, 0x04, 0x00000000 }, { 0x41984c, 1, 0x04, 0x00005bc8 }, @@ -38,8 +37,8 @@ nvd7_graph_init_pe_0[] = { {} }; -const struct nvc0_graph_init -nvd7_graph_init_pes_0[] = { +const struct gf100_gr_init +gf117_gr_init_pes_0[] = { { 0x41be04, 1, 0x04, 0x00000000 }, { 0x41be08, 1, 0x04, 0x00000004 }, { 0x41be0c, 1, 0x04, 0x00000000 }, @@ -48,50 +47,50 @@ nvd7_graph_init_pes_0[] = { {} }; -const struct nvc0_graph_init -nvd7_graph_init_wwdx_0[] = { +const struct gf100_gr_init +gf117_gr_init_wwdx_0[] = { { 0x41bfd4, 1, 0x04, 0x00800000 }, { 0x41bfdc, 1, 0x04, 0x00000000 }, { 0x41bff8, 2, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvd7_graph_init_cbm_0[] = { +const struct gf100_gr_init +gf117_gr_init_cbm_0[] = { { 0x41becc, 1, 0x04, 0x00000000 }, { 0x41bee8, 2, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_pack -nvd7_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nvd9_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvd9_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvd9_graph_init_tex_0 }, - { nvd7_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { nvd9_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nvc0_graph_init_be_0 }, - { nvd9_graph_init_fe_1 }, +static const struct gf100_gr_pack +gf117_gr_pack_mmio[] = { + { gf100_gr_init_main_0 }, + { gf100_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf119_gr_init_pd_0 }, + { gf119_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gf119_gr_init_prop_0 }, + { gf108_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gf108_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf119_gr_init_gpm_0 }, + { gf119_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gf100_gr_init_tpccs_0 }, + { gf119_gr_init_tex_0 }, + { gf117_gr_init_pe_0 }, + { gf100_gr_init_l1c_0 }, + { gf100_gr_init_mpc_0 }, + { gf119_gr_init_sm_0 }, + { gf117_gr_init_pes_0 }, + { gf117_gr_init_wwdx_0 }, + { gf117_gr_init_cbm_0 }, + { gf100_gr_init_be_0 }, + { gf119_gr_init_fe_1 }, {} }; @@ -99,39 +98,39 @@ nvd7_graph_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ -#include "fuc/hubnvd7.fuc.h" +#include "fuc/hubgf117.fuc3.h" -struct nvc0_graph_ucode -nvd7_graph_fecs_ucode = { - .code.data = nvd7_grhub_code, - .code.size = sizeof(nvd7_grhub_code), - .data.data = nvd7_grhub_data, - .data.size = sizeof(nvd7_grhub_data), +struct gf100_gr_ucode +gf117_gr_fecs_ucode = { + .code.data = gf117_grhub_code, + .code.size = sizeof(gf117_grhub_code), + .data.data = gf117_grhub_data, + .data.size = sizeof(gf117_grhub_data), }; -#include "fuc/gpcnvd7.fuc.h" +#include "fuc/gpcgf117.fuc3.h" -struct nvc0_graph_ucode -nvd7_graph_gpccs_ucode = { - .code.data = nvd7_grgpc_code, - .code.size = sizeof(nvd7_grgpc_code), - .data.data = nvd7_grgpc_data, - .data.size = sizeof(nvd7_grgpc_data), +struct gf100_gr_ucode +gf117_gr_gpccs_ucode = { + .code.data = gf117_grgpc_code, + .code.size = sizeof(gf117_grgpc_code), + .data.data = gf117_grgpc_data, + .data.size = sizeof(gf117_grgpc_data), }; -struct nouveau_oclass * -nvd7_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gf117_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xd7), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gf100_gr_init, + .fini = _nvkm_gr_fini, }, - .cclass = &nvd7_grctx_oclass, - .sclass = nvc8_graph_sclass, - .mmio = nvd7_graph_pack_mmio, - .fecs.ucode = &nvd7_graph_fecs_ucode, - .gpccs.ucode = &nvd7_graph_gpccs_ucode, + .cclass = &gf117_grctx_oclass, + .sclass = gf110_gr_sclass, + .mmio = gf117_gr_pack_mmio, + .fecs.ucode = &gf117_gr_fecs_ucode, + .gpccs.ucode = &gf117_gr_gpccs_ucode, .ppc_nr = 1, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c index 00fdf202fb92..e6dd651e2636 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c @@ -21,23 +21,22 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "nvc0.h" -#include "ctxnvc0.h" +#include "gf100.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH register lists ******************************************************************************/ -const struct nvc0_graph_init -nvd9_graph_init_pd_0[] = { +const struct gf100_gr_init +gf119_gr_init_pd_0[] = { { 0x406024, 1, 0x04, 0x00000000 }, { 0x4064f0, 3, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvd9_graph_init_ds_0[] = { +const struct gf100_gr_init +gf119_gr_init_ds_0[] = { { 0x405844, 1, 0x04, 0x00ffffff }, { 0x405850, 1, 0x04, 0x00000000 }, { 0x405900, 1, 0x04, 0x00002834 }, @@ -46,15 +45,15 @@ nvd9_graph_init_ds_0[] = { {} }; -const struct nvc0_graph_init -nvd9_graph_init_prop_0[] = { +const struct gf100_gr_init +gf119_gr_init_prop_0[] = { { 0x418408, 1, 0x04, 0x00000000 }, { 0x4184a0, 3, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvd9_graph_init_gpm_0[] = { +const struct gf100_gr_init +gf119_gr_init_gpm_0[] = { { 0x418c04, 1, 0x04, 0x00000000 }, { 0x418c64, 2, 0x04, 0x00000000 }, { 0x418c88, 1, 0x04, 0x00000000 }, @@ -62,8 +61,8 @@ nvd9_graph_init_gpm_0[] = { {} }; -const struct nvc0_graph_init -nvd9_graph_init_gpc_unk_1[] = { +const struct gf100_gr_init +gf119_gr_init_gpc_unk_1[] = { { 0x418d00, 1, 0x04, 0x00000000 }, { 0x418d28, 2, 0x04, 0x00000000 }, { 0x418f00, 1, 0x04, 0x00000000 }, @@ -75,8 +74,8 @@ nvd9_graph_init_gpc_unk_1[] = { {} }; -const struct nvc0_graph_init -nvd9_graph_init_tex_0[] = { +const struct gf100_gr_init +gf119_gr_init_tex_0[] = { { 0x419ab0, 1, 0x04, 0x00000000 }, { 0x419ac8, 1, 0x04, 0x00000000 }, { 0x419ab8, 1, 0x04, 0x000000e7 }, @@ -85,8 +84,8 @@ nvd9_graph_init_tex_0[] = { {} }; -static const struct nvc0_graph_init -nvd9_graph_init_pe_0[] = { +static const struct gf100_gr_init +gf119_gr_init_pe_0[] = { { 0x41980c, 1, 0x04, 0x00000010 }, { 0x419810, 1, 0x04, 0x00000000 }, { 0x419814, 1, 0x04, 0x00000004 }, @@ -97,23 +96,23 @@ nvd9_graph_init_pe_0[] = { {} }; -static const struct nvc0_graph_init -nvd9_graph_init_wwdx_0[] = { +static const struct gf100_gr_init +gf119_gr_init_wwdx_0[] = { { 0x419bd4, 1, 0x04, 0x00800000 }, { 0x419bdc, 1, 0x04, 0x00000000 }, { 0x419bf8, 2, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -nvd9_graph_init_tpccs_1[] = { +static const struct gf100_gr_init +gf119_gr_init_tpccs_1[] = { { 0x419d2c, 1, 0x04, 0x00000000 }, { 0x419d48, 2, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvd9_graph_init_sm_0[] = { +const struct gf100_gr_init +gf119_gr_init_sm_0[] = { { 0x419e00, 1, 0x04, 0x00000000 }, { 0x419ea0, 1, 0x04, 0x00000000 }, { 0x419ea4, 1, 0x04, 0x00000100 }, @@ -131,42 +130,42 @@ nvd9_graph_init_sm_0[] = { {} }; -const struct nvc0_graph_init -nvd9_graph_init_fe_1[] = { +const struct gf100_gr_init +gf119_gr_init_fe_1[] = { { 0x40402c, 1, 0x04, 0x00000000 }, { 0x4040f0, 1, 0x04, 0x00000000 }, { 0x404174, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_pack -nvd9_graph_pack_mmio[] = { - { nvc0_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nvd9_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvd9_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nvc0_graph_init_tpccs_0 }, - { nvd9_graph_init_tex_0 }, - { nvd9_graph_init_pe_0 }, - { nvc0_graph_init_l1c_0 }, - { nvd9_graph_init_wwdx_0 }, - { nvd9_graph_init_tpccs_1 }, - { nvc0_graph_init_mpc_0 }, - { nvd9_graph_init_sm_0 }, - { nvc0_graph_init_be_0 }, - { nvd9_graph_init_fe_1 }, +static const struct gf100_gr_pack +gf119_gr_pack_mmio[] = { + { gf100_gr_init_main_0 }, + { gf100_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf119_gr_init_pd_0 }, + { gf119_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gf119_gr_init_prop_0 }, + { gf108_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gf108_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf119_gr_init_gpm_0 }, + { gf119_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gf100_gr_init_tpccs_0 }, + { gf119_gr_init_tex_0 }, + { gf119_gr_init_pe_0 }, + { gf100_gr_init_l1c_0 }, + { gf119_gr_init_wwdx_0 }, + { gf119_gr_init_tpccs_1 }, + { gf100_gr_init_mpc_0 }, + { gf119_gr_init_sm_0 }, + { gf100_gr_init_be_0 }, + { gf119_gr_init_fe_1 }, {} }; @@ -174,18 +173,18 @@ nvd9_graph_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ -struct nouveau_oclass * -nvd9_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gf119_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xd9), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nvc0_graph_init, - .fini = _nouveau_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gf100_gr_init, + .fini = _nvkm_gr_fini, }, - .cclass = &nvd9_grctx_oclass, - .sclass = nvc8_graph_sclass, - .mmio = nvd9_graph_pack_mmio, - .fecs.ucode = &nvc0_graph_fecs_ucode, - .gpccs.ucode = &nvc0_graph_gpccs_ucode, + .cclass = &gf119_grctx_oclass, + .sclass = gf110_gr_sclass, + .mmio = gf119_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index 0c71f5c67ae0..489fdd94b885 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -21,22 +21,23 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "gf100.h" +#include "ctxgf100.h" -#include <subdev/pwr.h> +#include <subdev/pmu.h> -#include "nvc0.h" -#include "ctxnvc0.h" +#include <nvif/class.h> /******************************************************************************* * Graphics object classes ******************************************************************************/ -static struct nouveau_oclass -nve4_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa040, &nouveau_object_ofuncs }, - { KEPLER_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +static struct nvkm_oclass +gk104_gr_sclass[] = { + { 0x902d, &nvkm_object_ofuncs }, + { 0xa040, &nvkm_object_ofuncs }, + { KEPLER_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, {} }; @@ -44,8 +45,8 @@ nve4_graph_sclass[] = { * PGRAPH register lists ******************************************************************************/ -const struct nvc0_graph_init -nve4_graph_init_main_0[] = { +const struct gf100_gr_init +gk104_gr_init_main_0[] = { { 0x400080, 1, 0x04, 0x003083c2 }, { 0x400088, 1, 0x04, 0x0001ffe7 }, { 0x40008c, 1, 0x04, 0x00000000 }, @@ -60,8 +61,8 @@ nve4_graph_init_main_0[] = { {} }; -static const struct nvc0_graph_init -nve4_graph_init_ds_0[] = { +static const struct gf100_gr_init +gk104_gr_init_ds_0[] = { { 0x405844, 1, 0x04, 0x00ffffff }, { 0x405850, 1, 0x04, 0x00000000 }, { 0x405900, 1, 0x04, 0x0000ff34 }, @@ -70,20 +71,20 @@ nve4_graph_init_ds_0[] = { {} }; -static const struct nvc0_graph_init -nve4_graph_init_sked_0[] = { +static const struct gf100_gr_init +gk104_gr_init_sked_0[] = { { 0x407010, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -nve4_graph_init_cwd_0[] = { +static const struct gf100_gr_init +gk104_gr_init_cwd_0[] = { { 0x405b50, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -nve4_graph_init_gpc_unk_1[] = { +static const struct gf100_gr_init +gk104_gr_init_gpc_unk_1[] = { { 0x418d00, 1, 0x04, 0x00000000 }, { 0x418d28, 2, 0x04, 0x00000000 }, { 0x418f00, 1, 0x04, 0x00000000 }, @@ -95,15 +96,15 @@ nve4_graph_init_gpc_unk_1[] = { {} }; -const struct nvc0_graph_init -nve4_graph_init_tpccs_0[] = { +const struct gf100_gr_init +gk104_gr_init_tpccs_0[] = { { 0x419d0c, 1, 0x04, 0x00000000 }, { 0x419d10, 1, 0x04, 0x00000014 }, {} }; -const struct nvc0_graph_init -nve4_graph_init_pe_0[] = { +const struct gf100_gr_init +gk104_gr_init_pe_0[] = { { 0x41980c, 1, 0x04, 0x00000010 }, { 0x419844, 1, 0x04, 0x00000000 }, { 0x419850, 1, 0x04, 0x00000004 }, @@ -111,8 +112,8 @@ nve4_graph_init_pe_0[] = { {} }; -static const struct nvc0_graph_init -nve4_graph_init_l1c_0[] = { +static const struct gf100_gr_init +gk104_gr_init_l1c_0[] = { { 0x419c98, 1, 0x04, 0x00000000 }, { 0x419ca8, 1, 0x04, 0x00000000 }, { 0x419cb0, 1, 0x04, 0x01000000 }, @@ -125,8 +126,8 @@ nve4_graph_init_l1c_0[] = { {} }; -static const struct nvc0_graph_init -nve4_graph_init_sm_0[] = { +static const struct gf100_gr_init +gk104_gr_init_sm_0[] = { { 0x419e00, 1, 0x04, 0x00000000 }, { 0x419ea0, 1, 0x04, 0x00000000 }, { 0x419ee4, 1, 0x04, 0x00000000 }, @@ -139,8 +140,8 @@ nve4_graph_init_sm_0[] = { {} }; -const struct nvc0_graph_init -nve4_graph_init_be_0[] = { +const struct gf100_gr_init +gk104_gr_init_be_0[] = { { 0x40880c, 1, 0x04, 0x00000000 }, { 0x408850, 1, 0x04, 0x00000004 }, { 0x408910, 9, 0x04, 0x00000000 }, @@ -153,37 +154,37 @@ nve4_graph_init_be_0[] = { {} }; -const struct nvc0_graph_pack -nve4_graph_pack_mmio[] = { - { nve4_graph_init_main_0 }, - { nvc0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nve4_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nve4_graph_init_sked_0 }, - { nve4_graph_init_cwd_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nve4_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nve4_graph_init_tpccs_0 }, - { nvd9_graph_init_tex_0 }, - { nve4_graph_init_pe_0 }, - { nve4_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { nve4_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nve4_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, +const struct gf100_gr_pack +gk104_gr_pack_mmio[] = { + { gk104_gr_init_main_0 }, + { gf100_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf119_gr_init_pd_0 }, + { gk104_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gk104_gr_init_sked_0 }, + { gk104_gr_init_cwd_0 }, + { gf119_gr_init_prop_0 }, + { gf108_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gf108_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf119_gr_init_gpm_0 }, + { gk104_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gk104_gr_init_tpccs_0 }, + { gf119_gr_init_tex_0 }, + { gk104_gr_init_pe_0 }, + { gk104_gr_init_l1c_0 }, + { gf100_gr_init_mpc_0 }, + { gk104_gr_init_sm_0 }, + { gf117_gr_init_pes_0 }, + { gf117_gr_init_wwdx_0 }, + { gf117_gr_init_cbm_0 }, + { gk104_gr_init_be_0 }, + { gf100_gr_init_fe_1 }, {} }; @@ -192,21 +193,21 @@ nve4_graph_pack_mmio[] = { ******************************************************************************/ int -nve4_graph_init(struct nouveau_object *object) +gk104_gr_init(struct nvkm_object *object) { - struct nvc0_graph_oclass *oclass = (void *)object->oclass; - struct nvc0_graph_priv *priv = (void *)object; - struct nouveau_pwr *ppwr = nouveau_pwr(priv); + struct gf100_gr_oclass *oclass = (void *)object->oclass; + struct gf100_gr_priv *priv = (void *)object; + struct nvkm_pmu *pmu = nvkm_pmu(priv); const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; int ret, i; - if (ppwr) - ppwr->pgob(ppwr, false); + if (pmu) + pmu->pgob(pmu, false); - ret = nouveau_graph_init(&priv->base); + ret = nvkm_gr_init(&priv->base); if (ret) return ret; @@ -219,7 +220,7 @@ nve4_graph_init(struct nouveau_object *object) nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); - nvc0_graph_mmio(priv, oclass->mmio); + gf100_gr_mmio(priv, oclass->mmio); nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); @@ -304,44 +305,44 @@ nve4_graph_init(struct nouveau_object *object) nv_wr32(priv, 0x400054, 0x34ce3464); - nvc0_graph_zbc_init(priv); + gf100_gr_zbc_init(priv); - return nvc0_graph_init_ctxctl(priv); + return gf100_gr_init_ctxctl(priv); } -#include "fuc/hubnve0.fuc.h" +#include "fuc/hubgk104.fuc3.h" -static struct nvc0_graph_ucode -nve4_graph_fecs_ucode = { - .code.data = nve0_grhub_code, - .code.size = sizeof(nve0_grhub_code), - .data.data = nve0_grhub_data, - .data.size = sizeof(nve0_grhub_data), +static struct gf100_gr_ucode +gk104_gr_fecs_ucode = { + .code.data = gk104_grhub_code, + .code.size = sizeof(gk104_grhub_code), + .data.data = gk104_grhub_data, + .data.size = sizeof(gk104_grhub_data), }; -#include "fuc/gpcnve0.fuc.h" +#include "fuc/gpcgk104.fuc3.h" -static struct nvc0_graph_ucode -nve4_graph_gpccs_ucode = { - .code.data = nve0_grgpc_code, - .code.size = sizeof(nve0_grgpc_code), - .data.data = nve0_grgpc_data, - .data.size = sizeof(nve0_grgpc_data), +static struct gf100_gr_ucode +gk104_gr_gpccs_ucode = { + .code.data = gk104_grgpc_code, + .code.size = sizeof(gk104_grgpc_code), + .data.data = gk104_grgpc_data, + .data.size = sizeof(gk104_grgpc_data), }; -struct nouveau_oclass * -nve4_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gk104_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xe4), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = _nouveau_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gk104_gr_init, + .fini = _nvkm_gr_fini, }, - .cclass = &nve4_grctx_oclass, - .sclass = nve4_graph_sclass, - .mmio = nve4_graph_pack_mmio, - .fecs.ucode = &nve4_graph_fecs_ucode, - .gpccs.ucode = &nve4_graph_gpccs_ucode, + .cclass = &gk104_grctx_oclass, + .sclass = gk104_gr_sclass, + .mmio = gk104_gr_pack_mmio, + .fecs.ucode = &gk104_gr_fecs_ucode, + .gpccs.ucode = &gk104_gr_gpccs_ucode, .ppc_nr = 1, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index c306c0f2fc84..78e03ab1608e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c @@ -21,20 +21,23 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "gf100.h" +#include "ctxgf100.h" -#include "nvc0.h" -#include "ctxnvc0.h" +#include <subdev/timer.h> + +#include <nvif/class.h> /******************************************************************************* * Graphics object classes ******************************************************************************/ -struct nouveau_oclass -nvf0_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa140, &nouveau_object_ofuncs }, - { KEPLER_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +struct nvkm_oclass +gk110_gr_sclass[] = { + { 0x902d, &nvkm_object_ofuncs }, + { 0xa140, &nvkm_object_ofuncs }, + { KEPLER_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { KEPLER_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, {} }; @@ -42,16 +45,16 @@ nvf0_graph_sclass[] = { * PGRAPH register lists ******************************************************************************/ -const struct nvc0_graph_init -nvf0_graph_init_fe_0[] = { +const struct gf100_gr_init +gk110_gr_init_fe_0[] = { { 0x40415c, 1, 0x04, 0x00000000 }, { 0x404170, 1, 0x04, 0x00000000 }, { 0x4041b4, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvf0_graph_init_ds_0[] = { +const struct gf100_gr_init +gk110_gr_init_ds_0[] = { { 0x405844, 1, 0x04, 0x00ffffff }, { 0x405850, 1, 0x04, 0x00000000 }, { 0x405900, 1, 0x04, 0x0000ff00 }, @@ -60,23 +63,23 @@ nvf0_graph_init_ds_0[] = { {} }; -const struct nvc0_graph_init -nvf0_graph_init_sked_0[] = { +const struct gf100_gr_init +gk110_gr_init_sked_0[] = { { 0x407010, 1, 0x04, 0x00000000 }, { 0x407040, 1, 0x04, 0x80440424 }, { 0x407048, 1, 0x04, 0x0000000a }, {} }; -const struct nvc0_graph_init -nvf0_graph_init_cwd_0[] = { +const struct gf100_gr_init +gk110_gr_init_cwd_0[] = { { 0x405b44, 1, 0x04, 0x00000000 }, { 0x405b50, 1, 0x04, 0x00000000 }, {} }; -const struct nvc0_graph_init -nvf0_graph_init_gpc_unk_1[] = { +const struct gf100_gr_init +gk110_gr_init_gpc_unk_1[] = { { 0x418d00, 1, 0x04, 0x00000000 }, { 0x418d28, 2, 0x04, 0x00000000 }, { 0x418f00, 1, 0x04, 0x00000400 }, @@ -88,8 +91,8 @@ nvf0_graph_init_gpc_unk_1[] = { {} }; -const struct nvc0_graph_init -nvf0_graph_init_tex_0[] = { +const struct gf100_gr_init +gk110_gr_init_tex_0[] = { { 0x419ab0, 1, 0x04, 0x00000000 }, { 0x419ac8, 1, 0x04, 0x00000000 }, { 0x419ab8, 1, 0x04, 0x000000e7 }, @@ -100,8 +103,8 @@ nvf0_graph_init_tex_0[] = { {} }; -static const struct nvc0_graph_init -nvf0_graph_init_l1c_0[] = { +static const struct gf100_gr_init +gk110_gr_init_l1c_0[] = { { 0x419c98, 1, 0x04, 0x00000000 }, { 0x419ca8, 1, 0x04, 0x00000000 }, { 0x419cb0, 1, 0x04, 0x01000000 }, @@ -115,8 +118,8 @@ nvf0_graph_init_l1c_0[] = { {} }; -const struct nvc0_graph_init -nvf0_graph_init_sm_0[] = { +const struct gf100_gr_init +gk110_gr_init_sm_0[] = { { 0x419e00, 1, 0x04, 0x00000080 }, { 0x419ea0, 1, 0x04, 0x00000000 }, { 0x419ee4, 1, 0x04, 0x00000000 }, @@ -132,37 +135,37 @@ nvf0_graph_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack -nvf0_graph_pack_mmio[] = { - { nve4_graph_init_main_0 }, - { nvf0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nvf0_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvf0_graph_init_sked_0 }, - { nvf0_graph_init_cwd_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvf0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nve4_graph_init_tpccs_0 }, - { nvf0_graph_init_tex_0 }, - { nve4_graph_init_pe_0 }, - { nvf0_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { nvf0_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nve4_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, +static const struct gf100_gr_pack +gk110_gr_pack_mmio[] = { + { gk104_gr_init_main_0 }, + { gk110_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf119_gr_init_pd_0 }, + { gk110_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gk110_gr_init_sked_0 }, + { gk110_gr_init_cwd_0 }, + { gf119_gr_init_prop_0 }, + { gf108_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gf108_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf119_gr_init_gpm_0 }, + { gk110_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gk104_gr_init_tpccs_0 }, + { gk110_gr_init_tex_0 }, + { gk104_gr_init_pe_0 }, + { gk110_gr_init_l1c_0 }, + { gf100_gr_init_mpc_0 }, + { gk110_gr_init_sm_0 }, + { gf117_gr_init_pes_0 }, + { gf117_gr_init_wwdx_0 }, + { gf117_gr_init_cbm_0 }, + { gk104_gr_init_be_0 }, + { gf100_gr_init_fe_1 }, {} }; @@ -171,9 +174,9 @@ nvf0_graph_pack_mmio[] = { ******************************************************************************/ int -nvf0_graph_fini(struct nouveau_object *object, bool suspend) +gk110_gr_fini(struct nvkm_object *object, bool suspend) { - struct nvc0_graph_priv *priv = (void *)object; + struct gf100_gr_priv *priv = (void *)object; static const struct { u32 addr; u32 data; @@ -204,42 +207,42 @@ nvf0_graph_fini(struct nouveau_object *object, bool suspend) nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); } - return nouveau_graph_fini(&priv->base, suspend); + return nvkm_gr_fini(&priv->base, suspend); } -#include "fuc/hubnvf0.fuc.h" +#include "fuc/hubgk110.fuc3.h" -struct nvc0_graph_ucode -nvf0_graph_fecs_ucode = { - .code.data = nvf0_grhub_code, - .code.size = sizeof(nvf0_grhub_code), - .data.data = nvf0_grhub_data, - .data.size = sizeof(nvf0_grhub_data), +struct gf100_gr_ucode +gk110_gr_fecs_ucode = { + .code.data = gk110_grhub_code, + .code.size = sizeof(gk110_grhub_code), + .data.data = gk110_grhub_data, + .data.size = sizeof(gk110_grhub_data), }; -#include "fuc/gpcnvf0.fuc.h" +#include "fuc/gpcgk110.fuc3.h" -struct nvc0_graph_ucode -nvf0_graph_gpccs_ucode = { - .code.data = nvf0_grgpc_code, - .code.size = sizeof(nvf0_grgpc_code), - .data.data = nvf0_grgpc_data, - .data.size = sizeof(nvf0_grgpc_data), +struct gf100_gr_ucode +gk110_gr_gpccs_ucode = { + .code.data = gk110_grgpc_code, + .code.size = sizeof(gk110_grgpc_code), + .data.data = gk110_grgpc_data, + .data.size = sizeof(gk110_grgpc_data), }; -struct nouveau_oclass * -nvf0_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gk110_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xf0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = nvf0_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gk104_gr_init, + .fini = gk110_gr_fini, }, - .cclass = &nvf0_grctx_oclass, - .sclass = nvf0_graph_sclass, - .mmio = nvf0_graph_pack_mmio, - .fecs.ucode = &nvf0_graph_fecs_ucode, - .gpccs.ucode = &nvf0_graph_gpccs_ucode, + .cclass = &gk110_grctx_oclass, + .sclass = gk110_gr_sclass, + .mmio = gk110_gr_pack_mmio, + .fecs.ucode = &gk110_gr_fecs_ucode, + .gpccs.ucode = &gk110_gr_gpccs_ucode, .ppc_nr = 2, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c index d07b19dc168d..5292c5a9a38c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c @@ -21,16 +21,15 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include "nvc0.h" -#include "ctxnvc0.h" +#include "gf100.h" +#include "ctxgf100.h" /******************************************************************************* * PGRAPH register lists ******************************************************************************/ -static const struct nvc0_graph_init -gk110b_graph_init_l1c_0[] = { +static const struct gf100_gr_init +gk110b_gr_init_l1c_0[] = { { 0x419c98, 1, 0x04, 0x00000000 }, { 0x419ca8, 1, 0x04, 0x00000000 }, { 0x419cb0, 1, 0x04, 0x09000000 }, @@ -44,8 +43,8 @@ gk110b_graph_init_l1c_0[] = { {} }; -static const struct nvc0_graph_init -gk110b_graph_init_sm_0[] = { +static const struct gf100_gr_init +gk110b_gr_init_sm_0[] = { { 0x419e00, 1, 0x04, 0x00000080 }, { 0x419ea0, 1, 0x04, 0x00000000 }, { 0x419ee4, 1, 0x04, 0x00000000 }, @@ -61,37 +60,37 @@ gk110b_graph_init_sm_0[] = { {} }; -static const struct nvc0_graph_pack -gk110b_graph_pack_mmio[] = { - { nve4_graph_init_main_0 }, - { nvf0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nvf0_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvf0_graph_init_sked_0 }, - { nvf0_graph_init_cwd_0 }, - { nvd9_graph_init_prop_0 }, - { nvc1_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nvc1_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvf0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nve4_graph_init_tpccs_0 }, - { nvf0_graph_init_tex_0 }, - { nve4_graph_init_pe_0 }, - { gk110b_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { gk110b_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nve4_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, +static const struct gf100_gr_pack +gk110b_gr_pack_mmio[] = { + { gk104_gr_init_main_0 }, + { gk110_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf119_gr_init_pd_0 }, + { gk110_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gk110_gr_init_sked_0 }, + { gk110_gr_init_cwd_0 }, + { gf119_gr_init_prop_0 }, + { gf108_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gf108_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf119_gr_init_gpm_0 }, + { gk110_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gk104_gr_init_tpccs_0 }, + { gk110_gr_init_tex_0 }, + { gk104_gr_init_pe_0 }, + { gk110b_gr_init_l1c_0 }, + { gf100_gr_init_mpc_0 }, + { gk110b_gr_init_sm_0 }, + { gf117_gr_init_pes_0 }, + { gf117_gr_init_wwdx_0 }, + { gf117_gr_init_cbm_0 }, + { gk104_gr_init_be_0 }, + { gf100_gr_init_fe_1 }, {} }; @@ -99,19 +98,19 @@ gk110b_graph_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ -struct nouveau_oclass * -gk110b_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gk110b_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xf1), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = nvf0_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gk104_gr_init, + .fini = gk110_gr_fini, }, .cclass = &gk110b_grctx_oclass, - .sclass = nvf0_graph_sclass, - .mmio = gk110b_graph_pack_mmio, - .fecs.ucode = &nvf0_graph_fecs_ucode, - .gpccs.ucode = &nvf0_graph_gpccs_ucode, + .sclass = gk110_gr_sclass, + .mmio = gk110b_gr_pack_mmio, + .fecs.ucode = &gk110_gr_fecs_ucode, + .gpccs.ucode = &gk110_gr_gpccs_ucode, .ppc_nr = 2, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c index 2b0e8f48c029..ae6b853173b6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c @@ -21,20 +21,23 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "gf100.h" +#include "ctxgf100.h" -#include "nvc0.h" -#include "ctxnvc0.h" +#include <subdev/timer.h> + +#include <nvif/class.h> /******************************************************************************* * Graphics object classes ******************************************************************************/ -static struct nouveau_oclass -nv108_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa140, &nouveau_object_ofuncs }, - { KEPLER_B, &nvc0_fermi_ofuncs }, - { 0xa1c0, &nouveau_object_ofuncs }, +static struct nvkm_oclass +gk208_gr_sclass[] = { + { 0x902d, &nvkm_object_ofuncs }, + { 0xa140, &nvkm_object_ofuncs }, + { KEPLER_B, &gf100_fermi_ofuncs }, + { 0xa1c0, &nvkm_object_ofuncs }, {} }; @@ -42,8 +45,8 @@ nv108_graph_sclass[] = { * PGRAPH register lists ******************************************************************************/ -static const struct nvc0_graph_init -nv108_graph_init_main_0[] = { +static const struct gf100_gr_init +gk208_gr_init_main_0[] = { { 0x400080, 1, 0x04, 0x003083c2 }, { 0x400088, 1, 0x04, 0x0001bfe7 }, { 0x40008c, 1, 0x04, 0x00000000 }, @@ -58,8 +61,8 @@ nv108_graph_init_main_0[] = { {} }; -static const struct nvc0_graph_init -nv108_graph_init_ds_0[] = { +static const struct gf100_gr_init +gk208_gr_init_ds_0[] = { { 0x405844, 1, 0x04, 0x00ffffff }, { 0x405850, 1, 0x04, 0x00000000 }, { 0x405900, 1, 0x04, 0x00000000 }, @@ -68,8 +71,8 @@ nv108_graph_init_ds_0[] = { {} }; -const struct nvc0_graph_init -nv108_graph_init_gpc_unk_0[] = { +const struct gf100_gr_init +gk208_gr_init_gpc_unk_0[] = { { 0x418604, 1, 0x04, 0x00000000 }, { 0x418680, 1, 0x04, 0x00000000 }, { 0x418714, 1, 0x04, 0x00000000 }, @@ -77,16 +80,16 @@ nv108_graph_init_gpc_unk_0[] = { {} }; -static const struct nvc0_graph_init -nv108_graph_init_setup_1[] = { +static const struct gf100_gr_init +gk208_gr_init_setup_1[] = { { 0x4188c8, 2, 0x04, 0x00000000 }, { 0x4188d0, 1, 0x04, 0x00010000 }, { 0x4188d4, 1, 0x04, 0x00000201 }, {} }; -static const struct nvc0_graph_init -nv108_graph_init_tex_0[] = { +static const struct gf100_gr_init +gk208_gr_init_tex_0[] = { { 0x419ab0, 1, 0x04, 0x00000000 }, { 0x419ac8, 1, 0x04, 0x00000000 }, { 0x419ab8, 1, 0x04, 0x000000e7 }, @@ -96,8 +99,8 @@ nv108_graph_init_tex_0[] = { {} }; -static const struct nvc0_graph_init -nv108_graph_init_l1c_0[] = { +static const struct gf100_gr_init +gk208_gr_init_l1c_0[] = { { 0x419c98, 1, 0x04, 0x00000000 }, { 0x419ca8, 1, 0x04, 0x00000000 }, { 0x419cb0, 1, 0x04, 0x01000000 }, @@ -111,37 +114,37 @@ nv108_graph_init_l1c_0[] = { {} }; -static const struct nvc0_graph_pack -nv108_graph_pack_mmio[] = { - { nv108_graph_init_main_0 }, - { nvf0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvd9_graph_init_pd_0 }, - { nv108_graph_init_ds_0 }, - { nvc0_graph_init_scc_0 }, - { nvf0_graph_init_sked_0 }, - { nvf0_graph_init_cwd_0 }, - { nvd9_graph_init_prop_0 }, - { nv108_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { nv108_graph_init_setup_1 }, - { nvc0_graph_init_zcull_0 }, - { nvd9_graph_init_gpm_0 }, - { nvf0_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { nve4_graph_init_tpccs_0 }, - { nv108_graph_init_tex_0 }, - { nve4_graph_init_pe_0 }, - { nv108_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { nvf0_graph_init_sm_0 }, - { nvd7_graph_init_pes_0 }, - { nvd7_graph_init_wwdx_0 }, - { nvd7_graph_init_cbm_0 }, - { nve4_graph_init_be_0 }, - { nvc0_graph_init_fe_1 }, +static const struct gf100_gr_pack +gk208_gr_pack_mmio[] = { + { gk208_gr_init_main_0 }, + { gk110_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf119_gr_init_pd_0 }, + { gk208_gr_init_ds_0 }, + { gf100_gr_init_scc_0 }, + { gk110_gr_init_sked_0 }, + { gk110_gr_init_cwd_0 }, + { gf119_gr_init_prop_0 }, + { gk208_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gk208_gr_init_setup_1 }, + { gf100_gr_init_zcull_0 }, + { gf119_gr_init_gpm_0 }, + { gk110_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gk104_gr_init_tpccs_0 }, + { gk208_gr_init_tex_0 }, + { gk104_gr_init_pe_0 }, + { gk208_gr_init_l1c_0 }, + { gf100_gr_init_mpc_0 }, + { gk110_gr_init_sm_0 }, + { gf117_gr_init_pes_0 }, + { gf117_gr_init_wwdx_0 }, + { gf117_gr_init_cbm_0 }, + { gk104_gr_init_be_0 }, + { gf100_gr_init_fe_1 }, {} }; @@ -150,9 +153,9 @@ nv108_graph_pack_mmio[] = { ******************************************************************************/ static int -nv108_graph_fini(struct nouveau_object *object, bool suspend) +gk208_gr_fini(struct nvkm_object *object, bool suspend) { - struct nvc0_graph_priv *priv = (void *)object; + struct gf100_gr_priv *priv = (void *)object; static const struct { u32 addr; u32 data; @@ -183,42 +186,42 @@ nv108_graph_fini(struct nouveau_object *object, bool suspend) nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); } - return nouveau_graph_fini(&priv->base, suspend); + return nvkm_gr_fini(&priv->base, suspend); } -#include "fuc/hubnv108.fuc5.h" +#include "fuc/hubgk208.fuc5.h" -static struct nvc0_graph_ucode -nv108_graph_fecs_ucode = { - .code.data = nv108_grhub_code, - .code.size = sizeof(nv108_grhub_code), - .data.data = nv108_grhub_data, - .data.size = sizeof(nv108_grhub_data), +static struct gf100_gr_ucode +gk208_gr_fecs_ucode = { + .code.data = gk208_grhub_code, + .code.size = sizeof(gk208_grhub_code), + .data.data = gk208_grhub_data, + .data.size = sizeof(gk208_grhub_data), }; -#include "fuc/gpcnv108.fuc5.h" +#include "fuc/gpcgk208.fuc5.h" -static struct nvc0_graph_ucode -nv108_graph_gpccs_ucode = { - .code.data = nv108_grgpc_code, - .code.size = sizeof(nv108_grgpc_code), - .data.data = nv108_grgpc_data, - .data.size = sizeof(nv108_grgpc_data), +static struct gf100_gr_ucode +gk208_gr_gpccs_ucode = { + .code.data = gk208_grgpc_code, + .code.size = sizeof(gk208_grgpc_code), + .data.data = gk208_grgpc_data, + .data.size = sizeof(gk208_grgpc_data), }; -struct nouveau_oclass * -nv108_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gk208_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0x08), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = nv108_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gk104_gr_init, + .fini = gk208_gr_fini, }, - .cclass = &nv108_grctx_oclass, - .sclass = nv108_graph_sclass, - .mmio = nv108_graph_pack_mmio, - .fecs.ucode = &nv108_graph_fecs_ucode, - .gpccs.ucode = &nv108_graph_gpccs_ucode, + .cclass = &gk208_grctx_oclass, + .sclass = gk208_gr_sclass, + .mmio = gk208_gr_pack_mmio, + .fecs.ucode = &gk208_gr_fecs_ucode, + .gpccs.ucode = &gk208_gr_gpccs_ucode, .ppc_nr = 1, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index 7d0abe9f3fe7..213755534084 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -19,30 +19,31 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#include "gf100.h" +#include "ctxgf100.h" -#include "nvc0.h" -#include "ctxnvc0.h" +#include <nvif/class.h> -static struct nouveau_oclass -gk20a_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa040, &nouveau_object_ofuncs }, - { KEPLER_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +static struct nvkm_oclass +gk20a_gr_sclass[] = { + { 0x902d, &nvkm_object_ofuncs }, + { 0xa040, &nvkm_object_ofuncs }, + { KEPLER_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, {} }; -struct nouveau_oclass * -gk20a_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gk20a_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xea), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve4_graph_init, - .fini = _nouveau_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gk104_gr_init, + .fini = _nvkm_gr_fini, }, .cclass = &gk20a_grctx_oclass, - .sclass = gk20a_graph_sclass, - .mmio = nve4_graph_pack_mmio, + .sclass = gk20a_gr_sclass, + .mmio = gk104_gr_pack_mmio, .ppc_nr = 1, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index 4bdbdab2fd9a..124492b8a2d6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -21,23 +21,24 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ +#include "gf100.h" +#include "ctxgf100.h" #include <subdev/bios.h> #include <subdev/bios/P0260.h> -#include "nvc0.h" -#include "ctxnvc0.h" +#include <nvif/class.h> /******************************************************************************* * Graphics object classes ******************************************************************************/ -static struct nouveau_oclass -gm107_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa140, &nouveau_object_ofuncs }, - { MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, - { MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +static struct nvkm_oclass +gm107_gr_sclass[] = { + { 0x902d, &nvkm_object_ofuncs }, + { 0xa140, &nvkm_object_ofuncs }, + { MAXWELL_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { MAXWELL_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, {} }; @@ -45,8 +46,8 @@ gm107_graph_sclass[] = { * PGRAPH register lists ******************************************************************************/ -static const struct nvc0_graph_init -gm107_graph_init_main_0[] = { +static const struct gf100_gr_init +gm107_gr_init_main_0[] = { { 0x400080, 1, 0x04, 0x003003c2 }, { 0x400088, 1, 0x04, 0x0001bfe7 }, { 0x40008c, 1, 0x04, 0x00060000 }, @@ -61,8 +62,8 @@ gm107_graph_init_main_0[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_ds_0[] = { +static const struct gf100_gr_init +gm107_gr_init_ds_0[] = { { 0x405844, 1, 0x04, 0x00ffffff }, { 0x405850, 1, 0x04, 0x00000000 }, { 0x405900, 1, 0x04, 0x00000000 }, @@ -70,37 +71,37 @@ gm107_graph_init_ds_0[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_scc_0[] = { +static const struct gf100_gr_init +gm107_gr_init_scc_0[] = { { 0x40803c, 1, 0x04, 0x00000010 }, {} }; -static const struct nvc0_graph_init -gm107_graph_init_sked_0[] = { +static const struct gf100_gr_init +gm107_gr_init_sked_0[] = { { 0x407010, 1, 0x04, 0x00000000 }, { 0x407040, 1, 0x04, 0x40440424 }, { 0x407048, 1, 0x04, 0x0000000a }, {} }; -static const struct nvc0_graph_init -gm107_graph_init_prop_0[] = { +static const struct gf100_gr_init +gm107_gr_init_prop_0[] = { { 0x418408, 1, 0x04, 0x00000000 }, { 0x4184a0, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -gm107_graph_init_setup_1[] = { +static const struct gf100_gr_init +gm107_gr_init_setup_1[] = { { 0x4188c8, 2, 0x04, 0x00000000 }, { 0x4188d0, 1, 0x04, 0x00010000 }, { 0x4188d4, 1, 0x04, 0x00010201 }, {} }; -static const struct nvc0_graph_init -gm107_graph_init_zcull_0[] = { +static const struct gf100_gr_init +gm107_gr_init_zcull_0[] = { { 0x418910, 1, 0x04, 0x00010001 }, { 0x418914, 1, 0x04, 0x00000301 }, { 0x418918, 1, 0x04, 0x00800000 }, @@ -110,8 +111,8 @@ gm107_graph_init_zcull_0[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_gpc_unk_1[] = { +static const struct gf100_gr_init +gm107_gr_init_gpc_unk_1[] = { { 0x418d00, 1, 0x04, 0x00000000 }, { 0x418f00, 1, 0x04, 0x00000400 }, { 0x418f08, 1, 0x04, 0x00000000 }, @@ -119,8 +120,8 @@ gm107_graph_init_gpc_unk_1[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_tpccs_0[] = { +static const struct gf100_gr_init +gm107_gr_init_tpccs_0[] = { { 0x419dc4, 1, 0x04, 0x00000000 }, { 0x419dc8, 1, 0x04, 0x00000501 }, { 0x419dd0, 1, 0x04, 0x00000000 }, @@ -133,8 +134,8 @@ gm107_graph_init_tpccs_0[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_tex_0[] = { +static const struct gf100_gr_init +gm107_gr_init_tex_0[] = { { 0x419ab0, 1, 0x04, 0x00000000 }, { 0x419ab8, 1, 0x04, 0x000000e7 }, { 0x419abc, 1, 0x04, 0x00000000 }, @@ -147,8 +148,8 @@ gm107_graph_init_tex_0[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_pe_0[] = { +static const struct gf100_gr_init +gm107_gr_init_pe_0[] = { { 0x419900, 1, 0x04, 0x000000ff }, { 0x41980c, 1, 0x04, 0x00000010 }, { 0x419844, 1, 0x04, 0x00000000 }, @@ -159,15 +160,15 @@ gm107_graph_init_pe_0[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_l1c_0[] = { +static const struct gf100_gr_init +gm107_gr_init_l1c_0[] = { { 0x419c98, 1, 0x04, 0x00000000 }, { 0x419cc0, 2, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -gm107_graph_init_sm_0[] = { +static const struct gf100_gr_init +gm107_gr_init_sm_0[] = { { 0x419e30, 1, 0x04, 0x000000ff }, { 0x419e00, 1, 0x04, 0x00000000 }, { 0x419ea0, 1, 0x04, 0x00000000 }, @@ -185,16 +186,16 @@ gm107_graph_init_sm_0[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_l1c_1[] = { +static const struct gf100_gr_init +gm107_gr_init_l1c_1[] = { { 0x419ccc, 2, 0x04, 0x00000000 }, { 0x419c80, 1, 0x04, 0x3f006022 }, { 0x419c88, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -gm107_graph_init_pes_0[] = { +static const struct gf100_gr_init +gm107_gr_init_pes_0[] = { { 0x41be50, 1, 0x04, 0x000000ff }, { 0x41be04, 1, 0x04, 0x00000000 }, { 0x41be08, 1, 0x04, 0x00000004 }, @@ -205,21 +206,21 @@ gm107_graph_init_pes_0[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_wwdx_0[] = { +static const struct gf100_gr_init +gm107_gr_init_wwdx_0[] = { { 0x41bfd4, 1, 0x04, 0x00800000 }, { 0x41bfdc, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -gm107_graph_init_cbm_0[] = { +static const struct gf100_gr_init +gm107_gr_init_cbm_0[] = { { 0x41becc, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_init -gm107_graph_init_be_0[] = { +static const struct gf100_gr_init +gm107_gr_init_be_0[] = { { 0x408890, 1, 0x04, 0x000000ff }, { 0x40880c, 1, 0x04, 0x00000000 }, { 0x408850, 1, 0x04, 0x00000004 }, @@ -244,45 +245,45 @@ gm107_graph_init_be_0[] = { {} }; -static const struct nvc0_graph_init -gm107_graph_init_sm_1[] = { +static const struct gf100_gr_init +gm107_gr_init_sm_1[] = { { 0x419e5c, 1, 0x04, 0x00000000 }, { 0x419e58, 1, 0x04, 0x00000000 }, {} }; -static const struct nvc0_graph_pack -gm107_graph_pack_mmio[] = { - { gm107_graph_init_main_0 }, - { nvf0_graph_init_fe_0 }, - { nvc0_graph_init_pri_0 }, - { nvc0_graph_init_rstr2d_0 }, - { nvc0_graph_init_pd_0 }, - { gm107_graph_init_ds_0 }, - { gm107_graph_init_scc_0 }, - { gm107_graph_init_sked_0 }, - { nvf0_graph_init_cwd_0 }, - { gm107_graph_init_prop_0 }, - { nv108_graph_init_gpc_unk_0 }, - { nvc0_graph_init_setup_0 }, - { nvc0_graph_init_crstr_0 }, - { gm107_graph_init_setup_1 }, - { gm107_graph_init_zcull_0 }, - { nvc0_graph_init_gpm_0 }, - { gm107_graph_init_gpc_unk_1 }, - { nvc0_graph_init_gcc_0 }, - { gm107_graph_init_tpccs_0 }, - { gm107_graph_init_tex_0 }, - { gm107_graph_init_pe_0 }, - { gm107_graph_init_l1c_0 }, - { nvc0_graph_init_mpc_0 }, - { gm107_graph_init_sm_0 }, - { gm107_graph_init_l1c_1 }, - { gm107_graph_init_pes_0 }, - { gm107_graph_init_wwdx_0 }, - { gm107_graph_init_cbm_0 }, - { gm107_graph_init_be_0 }, - { gm107_graph_init_sm_1 }, +static const struct gf100_gr_pack +gm107_gr_pack_mmio[] = { + { gm107_gr_init_main_0 }, + { gk110_gr_init_fe_0 }, + { gf100_gr_init_pri_0 }, + { gf100_gr_init_rstr2d_0 }, + { gf100_gr_init_pd_0 }, + { gm107_gr_init_ds_0 }, + { gm107_gr_init_scc_0 }, + { gm107_gr_init_sked_0 }, + { gk110_gr_init_cwd_0 }, + { gm107_gr_init_prop_0 }, + { gk208_gr_init_gpc_unk_0 }, + { gf100_gr_init_setup_0 }, + { gf100_gr_init_crstr_0 }, + { gm107_gr_init_setup_1 }, + { gm107_gr_init_zcull_0 }, + { gf100_gr_init_gpm_0 }, + { gm107_gr_init_gpc_unk_1 }, + { gf100_gr_init_gcc_0 }, + { gm107_gr_init_tpccs_0 }, + { gm107_gr_init_tex_0 }, + { gm107_gr_init_pe_0 }, + { gm107_gr_init_l1c_0 }, + { gf100_gr_init_mpc_0 }, + { gm107_gr_init_sm_0 }, + { gm107_gr_init_l1c_1 }, + { gm107_gr_init_pes_0 }, + { gm107_gr_init_wwdx_0 }, + { gm107_gr_init_cbm_0 }, + { gm107_gr_init_be_0 }, + { gm107_gr_init_sm_1 }, {} }; @@ -291,7 +292,7 @@ gm107_graph_pack_mmio[] = { ******************************************************************************/ static void -gm107_graph_init_bios(struct nvc0_graph_priv *priv) +gm107_gr_init_bios(struct gf100_gr_priv *priv) { static const struct { u32 ctrl; @@ -303,7 +304,7 @@ gm107_graph_init_bios(struct nvc0_graph_priv *priv) { 0x419af0, 0x419af4 }, { 0x419af8, 0x419afc }, }; - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_P0260E infoE; struct nvbios_P0260X infoX; int E = -1, X; @@ -319,17 +320,17 @@ gm107_graph_init_bios(struct nvc0_graph_priv *priv) } int -gm107_graph_init(struct nouveau_object *object) +gm107_gr_init(struct nvkm_object *object) { - struct nvc0_graph_oclass *oclass = (void *)object->oclass; - struct nvc0_graph_priv *priv = (void *)object; + struct gf100_gr_oclass *oclass = (void *)object->oclass; + struct gf100_gr_priv *priv = (void *)object; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, ppc, rop; int ret, i; - ret = nouveau_graph_init(&priv->base); + ret = nvkm_gr_init(&priv->base); if (ret) return ret; @@ -339,9 +340,9 @@ gm107_graph_init(struct nouveau_object *object) nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); - nvc0_graph_mmio(priv, oclass->mmio); + gf100_gr_mmio(priv, oclass->mmio); - gm107_graph_init_bios(priv); + gm107_gr_init_bios(priv); nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); @@ -426,15 +427,15 @@ gm107_graph_init(struct nouveau_object *object) nv_wr32(priv, 0x400054, 0x2c350f63); - nvc0_graph_zbc_init(priv); + gf100_gr_zbc_init(priv); - return nvc0_graph_init_ctxctl(priv); + return gf100_gr_init_ctxctl(priv); } #include "fuc/hubgm107.fuc5.h" -static struct nvc0_graph_ucode -gm107_graph_fecs_ucode = { +static struct gf100_gr_ucode +gm107_gr_fecs_ucode = { .code.data = gm107_grhub_code, .code.size = sizeof(gm107_grhub_code), .data.data = gm107_grhub_data, @@ -443,27 +444,27 @@ gm107_graph_fecs_ucode = { #include "fuc/gpcgm107.fuc5.h" -static struct nvc0_graph_ucode -gm107_graph_gpccs_ucode = { +static struct gf100_gr_ucode +gm107_gr_gpccs_ucode = { .code.data = gm107_grgpc_code, .code.size = sizeof(gm107_grgpc_code), .data.data = gm107_grgpc_data, .data.size = sizeof(gm107_grgpc_data), }; -struct nouveau_oclass * -gm107_graph_oclass = &(struct nvc0_graph_oclass) { +struct nvkm_oclass * +gm107_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0x07), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = gm107_graph_init, - .fini = _nouveau_graph_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gm107_gr_init, + .fini = _nvkm_gr_fini, }, .cclass = &gm107_grctx_oclass, - .sclass = gm107_graph_sclass, - .mmio = gm107_graph_pack_mmio, - .fecs.ucode = 0 ? &gm107_graph_fecs_ucode : NULL, - .gpccs.ucode = &gm107_graph_gpccs_ucode, + .sclass = gm107_gr_sclass, + .mmio = gm107_gr_pack_mmio, + .fecs.ucode = 0 ? &gm107_gr_fecs_ucode : NULL, + .gpccs.ucode = &gm107_gr_gpccs_ucode, .ppc_nr = 2, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index f70e2f67a4dd..2614510c28d0 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -10,7 +10,7 @@ * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the + * paragr) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR @@ -21,23 +21,18 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#include <engine/gr.h> +#include "regs.h" #include <core/client.h> -#include <core/os.h> +#include <core/device.h> #include <core/handle.h> -#include <core/namedb.h> - -#include <subdev/fb.h> +#include <engine/fifo.h> #include <subdev/instmem.h> #include <subdev/timer.h> -#include <engine/fifo.h> -#include <engine/graph.h> - -#include "regs.h" - static u32 -nv04_graph_ctx_regs[] = { +nv04_gr_ctx_regs[] = { 0x0040053c, 0x00400544, 0x00400540, @@ -351,21 +346,21 @@ nv04_graph_ctx_regs[] = { NV04_PGRAPH_DEBUG_3 }; -struct nv04_graph_priv { - struct nouveau_graph base; - struct nv04_graph_chan *chan[16]; +struct nv04_gr_priv { + struct nvkm_gr base; + struct nv04_gr_chan *chan[16]; spinlock_t lock; }; -struct nv04_graph_chan { - struct nouveau_object base; +struct nv04_gr_chan { + struct nvkm_object base; int chid; - u32 nv04[ARRAY_SIZE(nv04_graph_ctx_regs)]; + u32 nv04[ARRAY_SIZE(nv04_gr_ctx_regs)]; }; -static inline struct nv04_graph_priv * -nv04_graph_priv(struct nv04_graph_chan *chan) +static inline struct nv04_gr_priv * +nv04_gr_priv(struct nv04_gr_chan *chan) { return (void *)nv_object(chan)->engine; } @@ -449,9 +444,9 @@ nv04_graph_priv(struct nv04_graph_chan *chan) */ static void -nv04_graph_set_ctx1(struct nouveau_object *object, u32 mask, u32 value) +nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value) { - struct nv04_graph_priv *priv = (void *)object->engine; + struct nv04_gr_priv *priv = (void *)object->engine; int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; u32 tmp; @@ -465,7 +460,7 @@ nv04_graph_set_ctx1(struct nouveau_object *object, u32 mask, u32 value) } static void -nv04_graph_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value) +nv04_gr_set_ctx_val(struct nvkm_object *object, u32 mask, u32 value) { int class, op, valid = 1; u32 tmp, ctx1; @@ -509,12 +504,12 @@ nv04_graph_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value) break; } - nv04_graph_set_ctx1(object, 0x01000000, valid << 24); + nv04_gr_set_ctx1(object, 0x01000000, valid << 24); } static int -nv04_graph_mthd_set_operation(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_set_operation(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { u32 class = nv_ro32(object, 0) & 0xff; u32 data = *(u32 *)args; @@ -523,17 +518,17 @@ nv04_graph_mthd_set_operation(struct nouveau_object *object, u32 mthd, /* Old versions of the objects only accept first three operations. */ if (data > 2 && class < 0x40) return 1; - nv04_graph_set_ctx1(object, 0x00038000, data << 15); + nv04_gr_set_ctx1(object, 0x00038000, data << 15); /* changing operation changes set of objects needed for validation */ - nv04_graph_set_ctx_val(object, 0, 0); + nv04_gr_set_ctx_val(object, 0, 0); return 0; } static int -nv04_graph_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv04_graph_priv *priv = (void *)object->engine; + struct nv04_gr_priv *priv = (void *)object->engine; u32 data = *(u32 *)args; u32 min = data & 0xffff, max; u32 w = data >> 16; @@ -551,10 +546,10 @@ nv04_graph_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd, } static int -nv04_graph_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv04_graph_priv *priv = (void *)object->engine; + struct nv04_gr_priv *priv = (void *)object->engine; u32 data = *(u32 *)args; u32 min = data & 0xffff, max; u32 w = data >> 16; @@ -572,397 +567,396 @@ nv04_graph_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd, } static u16 -nv04_graph_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size) +nv04_gr_mthd_bind_class(struct nvkm_object *object, u32 *args, u32 size) { - struct nouveau_instmem *imem = nouveau_instmem(object); + struct nvkm_instmem *imem = nvkm_instmem(object); u32 inst = *(u32 *)args << 4; return nv_ro32(imem, inst); } static int -nv04_graph_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd, +nv04_gr_mthd_bind_surf2d(struct nvkm_object *object, u32 mthd, void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx1(object, 0x00004000, 0); - nv04_graph_set_ctx_val(object, 0x02000000, 0); + nv04_gr_set_ctx1(object, 0x00004000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0); return 0; case 0x42: - nv04_graph_set_ctx1(object, 0x00004000, 0); - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); + nv04_gr_set_ctx1(object, 0x00004000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); return 0; } return 1; } static int -nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_bind_surf2d_swzsurf(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx1(object, 0x00004000, 0); - nv04_graph_set_ctx_val(object, 0x02000000, 0); + nv04_gr_set_ctx1(object, 0x00004000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0); return 0; case 0x42: - nv04_graph_set_ctx1(object, 0x00004000, 0); - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); + nv04_gr_set_ctx1(object, 0x00004000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); return 0; case 0x52: - nv04_graph_set_ctx1(object, 0x00004000, 0x00004000); - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); + nv04_gr_set_ctx1(object, 0x00004000, 0x00004000); + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); return 0; } return 1; } static int -nv01_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv01_gr_mthd_bind_patt(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx_val(object, 0x08000000, 0); + nv04_gr_set_ctx_val(object, 0x08000000, 0); return 0; case 0x18: - nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000); + nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000); return 0; } return 1; } static int -nv04_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_bind_patt(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx_val(object, 0x08000000, 0); + nv04_gr_set_ctx_val(object, 0x08000000, 0); return 0; case 0x44: - nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000); + nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000); return 0; } return 1; } static int -nv04_graph_mthd_bind_rop(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_bind_rop(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx_val(object, 0x10000000, 0); + nv04_gr_set_ctx_val(object, 0x10000000, 0); return 0; case 0x43: - nv04_graph_set_ctx_val(object, 0x10000000, 0x10000000); + nv04_gr_set_ctx_val(object, 0x10000000, 0x10000000); return 0; } return 1; } static int -nv04_graph_mthd_bind_beta1(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_bind_beta1(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx_val(object, 0x20000000, 0); + nv04_gr_set_ctx_val(object, 0x20000000, 0); return 0; case 0x12: - nv04_graph_set_ctx_val(object, 0x20000000, 0x20000000); + nv04_gr_set_ctx_val(object, 0x20000000, 0x20000000); return 0; } return 1; } static int -nv04_graph_mthd_bind_beta4(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_bind_beta4(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx_val(object, 0x40000000, 0); + nv04_gr_set_ctx_val(object, 0x40000000, 0); return 0; case 0x72: - nv04_graph_set_ctx_val(object, 0x40000000, 0x40000000); + nv04_gr_set_ctx_val(object, 0x40000000, 0x40000000); return 0; } return 1; } static int -nv04_graph_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_bind_surf_dst(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx_val(object, 0x02000000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0); return 0; case 0x58: - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); return 0; } return 1; } static int -nv04_graph_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_bind_surf_src(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx_val(object, 0x04000000, 0); + nv04_gr_set_ctx_val(object, 0x04000000, 0); return 0; case 0x59: - nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000); + nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000); return 0; } return 1; } static int -nv04_graph_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_bind_surf_color(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx_val(object, 0x02000000, 0); + nv04_gr_set_ctx_val(object, 0x02000000, 0); return 0; case 0x5a: - nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); + nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); return 0; } return 1; } static int -nv04_graph_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_gr_mthd_bind_surf_zeta(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx_val(object, 0x04000000, 0); + nv04_gr_set_ctx_val(object, 0x04000000, 0); return 0; case 0x5b: - nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000); + nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000); return 0; } return 1; } static int -nv01_graph_mthd_bind_clip(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv01_gr_mthd_bind_clip(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx1(object, 0x2000, 0); + nv04_gr_set_ctx1(object, 0x2000, 0); return 0; case 0x19: - nv04_graph_set_ctx1(object, 0x2000, 0x2000); + nv04_gr_set_ctx1(object, 0x2000, 0x2000); return 0; } return 1; } static int -nv01_graph_mthd_bind_chroma(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv01_gr_mthd_bind_chroma(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - switch (nv04_graph_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(object, args, size)) { case 0x30: - nv04_graph_set_ctx1(object, 0x1000, 0); + nv04_gr_set_ctx1(object, 0x1000, 0); return 0; /* Yes, for some reason even the old versions of objects * accept 0x57 and not 0x17. Consistency be damned. */ case 0x57: - nv04_graph_set_ctx1(object, 0x1000, 0x1000); + nv04_gr_set_ctx1(object, 0x1000, 0x1000); return 0; } return 1; } -static struct nouveau_omthds -nv03_graph_gdi_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_patt }, - { 0x0188, 0x0188, nv04_graph_mthd_bind_rop }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_beta1 }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv03_gr_gdi_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_patt }, + { 0x0188, 0x0188, nv04_gr_mthd_bind_rop }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_beta1 }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_surf_dst }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv04_graph_gdi_omthds[] = { - { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv04_gr_gdi_omthds[] = { + { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv01_graph_blit_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, - { 0x019c, 0x019c, nv04_graph_mthd_bind_surf_src }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv01_gr_blit_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv01_gr_mthd_bind_patt }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst }, + { 0x019c, 0x019c, nv04_gr_mthd_bind_surf_src }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv04_graph_blit_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, - { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv04_gr_blit_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_patt }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 }, + { 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv04_graph_iifc_omthds[] = { - { 0x0188, 0x0188, nv01_graph_mthd_bind_chroma }, - { 0x018c, 0x018c, nv01_graph_mthd_bind_clip }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_patt }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_rop }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_beta1 }, - { 0x019c, 0x019c, nv04_graph_mthd_bind_beta4 }, - { 0x01a0, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf }, - { 0x03e4, 0x03e4, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv04_gr_iifc_omthds[] = { + { 0x0188, 0x0188, nv01_gr_mthd_bind_chroma }, + { 0x018c, 0x018c, nv01_gr_mthd_bind_clip }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_patt }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_rop }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_beta1 }, + { 0x019c, 0x019c, nv04_gr_mthd_bind_beta4 }, + { 0x01a0, 0x01a0, nv04_gr_mthd_bind_surf2d_swzsurf }, + { 0x03e4, 0x03e4, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv01_graph_ifc_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv01_gr_ifc_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv01_gr_mthd_bind_patt }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv04_graph_ifc_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, - { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv04_gr_ifc_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_patt }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 }, + { 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv03_graph_sifc_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv03_gr_sifc_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv04_graph_sifc_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, - { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv04_gr_sifc_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, + { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv03_graph_sifm_omthds[] = { - { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, - { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv03_gr_sifm_omthds[] = { + { 0x0188, 0x0188, nv01_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst }, + { 0x0304, 0x0304, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv04_graph_sifm_omthds[] = { - { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, - { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv04_gr_sifm_omthds[] = { + { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, + { 0x0304, 0x0304, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv04_graph_surf3d_omthds[] = { - { 0x02f8, 0x02f8, nv04_graph_mthd_surf3d_clip_h }, - { 0x02fc, 0x02fc, nv04_graph_mthd_surf3d_clip_v }, +static struct nvkm_omthds +nv04_gr_surf3d_omthds[] = { + { 0x02f8, 0x02f8, nv04_gr_mthd_surf3d_clip_h }, + { 0x02fc, 0x02fc, nv04_gr_mthd_surf3d_clip_v }, {} }; -static struct nouveau_omthds -nv03_graph_ttri_omthds[] = { - { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_surf_color }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_zeta }, +static struct nvkm_omthds +nv03_gr_ttri_omthds[] = { + { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_surf_color }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_surf_zeta }, {} }; -static struct nouveau_omthds -nv01_graph_prim_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, - { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv01_gr_prim_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_clip }, + { 0x0188, 0x0188, nv01_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; -static struct nouveau_omthds -nv04_graph_prim_omthds[] = { - { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, - { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +static struct nvkm_omthds +nv04_gr_prim_omthds[] = { + { 0x0184, 0x0184, nv01_gr_mthd_bind_clip }, + { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, + { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, + { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, + { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, + { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, + { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, {} }; static int -nv04_graph_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_gpuobj *obj; + struct nvkm_gpuobj *obj; int ret; - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, - 16, 16, 0, &obj); + ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, + 16, 16, 0, &obj); *pobject = nv_object(obj); if (ret) return ret; @@ -977,59 +971,59 @@ nv04_graph_object_ctor(struct nouveau_object *parent, return 0; } -struct nouveau_ofuncs -nv04_graph_ofuncs = { - .ctor = nv04_graph_object_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, +struct nvkm_ofuncs +nv04_gr_ofuncs = { + .ctor = nv04_gr_object_ctor, + .dtor = _nvkm_gpuobj_dtor, + .init = _nvkm_gpuobj_init, + .fini = _nvkm_gpuobj_fini, + .rd32 = _nvkm_gpuobj_rd32, + .wr32 = _nvkm_gpuobj_wr32, }; -static struct nouveau_oclass -nv04_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ - { 0x0017, &nv04_graph_ofuncs }, /* chroma */ - { 0x0018, &nv04_graph_ofuncs }, /* pattern (nv01) */ - { 0x0019, &nv04_graph_ofuncs }, /* clip */ - { 0x001c, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* line */ - { 0x001d, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* tri */ - { 0x001e, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* rect */ - { 0x001f, &nv04_graph_ofuncs, nv01_graph_blit_omthds }, - { 0x0021, &nv04_graph_ofuncs, nv01_graph_ifc_omthds }, - { 0x0030, &nv04_graph_ofuncs }, /* null */ - { 0x0036, &nv04_graph_ofuncs, nv03_graph_sifc_omthds }, - { 0x0037, &nv04_graph_ofuncs, nv03_graph_sifm_omthds }, - { 0x0038, &nv04_graph_ofuncs }, /* dvd subpicture */ - { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ - { 0x0042, &nv04_graph_ofuncs }, /* surf2d */ - { 0x0043, &nv04_graph_ofuncs }, /* rop */ - { 0x0044, &nv04_graph_ofuncs }, /* pattern */ - { 0x0048, &nv04_graph_ofuncs, nv03_graph_ttri_omthds }, - { 0x004a, &nv04_graph_ofuncs, nv04_graph_gdi_omthds }, - { 0x004b, &nv04_graph_ofuncs, nv03_graph_gdi_omthds }, - { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ - { 0x0053, &nv04_graph_ofuncs, nv04_graph_surf3d_omthds }, - { 0x0054, &nv04_graph_ofuncs }, /* ttri */ - { 0x0055, &nv04_graph_ofuncs }, /* mtri */ - { 0x0057, &nv04_graph_ofuncs }, /* chroma */ - { 0x0058, &nv04_graph_ofuncs }, /* surf_dst */ - { 0x0059, &nv04_graph_ofuncs }, /* surf_src */ - { 0x005a, &nv04_graph_ofuncs }, /* surf_color */ - { 0x005b, &nv04_graph_ofuncs }, /* surf_zeta */ - { 0x005c, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* line */ - { 0x005d, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* tri */ - { 0x005e, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* rect */ - { 0x005f, &nv04_graph_ofuncs, nv04_graph_blit_omthds }, - { 0x0060, &nv04_graph_ofuncs, nv04_graph_iifc_omthds }, - { 0x0061, &nv04_graph_ofuncs, nv04_graph_ifc_omthds }, - { 0x0064, &nv04_graph_ofuncs }, /* iifc (nv05) */ - { 0x0065, &nv04_graph_ofuncs }, /* ifc (nv05) */ - { 0x0066, &nv04_graph_ofuncs }, /* sifc (nv05) */ - { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ - { 0x0076, &nv04_graph_ofuncs, nv04_graph_sifc_omthds }, - { 0x0077, &nv04_graph_ofuncs, nv04_graph_sifm_omthds }, +static struct nvkm_oclass +nv04_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ + { 0x0017, &nv04_gr_ofuncs }, /* chroma */ + { 0x0018, &nv04_gr_ofuncs }, /* pattern (nv01) */ + { 0x0019, &nv04_gr_ofuncs }, /* clip */ + { 0x001c, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* line */ + { 0x001d, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* tri */ + { 0x001e, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* rect */ + { 0x001f, &nv04_gr_ofuncs, nv01_gr_blit_omthds }, + { 0x0021, &nv04_gr_ofuncs, nv01_gr_ifc_omthds }, + { 0x0030, &nv04_gr_ofuncs }, /* null */ + { 0x0036, &nv04_gr_ofuncs, nv03_gr_sifc_omthds }, + { 0x0037, &nv04_gr_ofuncs, nv03_gr_sifm_omthds }, + { 0x0038, &nv04_gr_ofuncs }, /* dvd subpicture */ + { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ + { 0x0042, &nv04_gr_ofuncs }, /* surf2d */ + { 0x0043, &nv04_gr_ofuncs }, /* rop */ + { 0x0044, &nv04_gr_ofuncs }, /* pattern */ + { 0x0048, &nv04_gr_ofuncs, nv03_gr_ttri_omthds }, + { 0x004a, &nv04_gr_ofuncs, nv04_gr_gdi_omthds }, + { 0x004b, &nv04_gr_ofuncs, nv03_gr_gdi_omthds }, + { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ + { 0x0053, &nv04_gr_ofuncs, nv04_gr_surf3d_omthds }, + { 0x0054, &nv04_gr_ofuncs }, /* ttri */ + { 0x0055, &nv04_gr_ofuncs }, /* mtri */ + { 0x0057, &nv04_gr_ofuncs }, /* chroma */ + { 0x0058, &nv04_gr_ofuncs }, /* surf_dst */ + { 0x0059, &nv04_gr_ofuncs }, /* surf_src */ + { 0x005a, &nv04_gr_ofuncs }, /* surf_color */ + { 0x005b, &nv04_gr_ofuncs }, /* surf_zeta */ + { 0x005c, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* line */ + { 0x005d, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* tri */ + { 0x005e, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* rect */ + { 0x005f, &nv04_gr_ofuncs, nv04_gr_blit_omthds }, + { 0x0060, &nv04_gr_ofuncs, nv04_gr_iifc_omthds }, + { 0x0061, &nv04_gr_ofuncs, nv04_gr_ifc_omthds }, + { 0x0064, &nv04_gr_ofuncs }, /* iifc (nv05) */ + { 0x0065, &nv04_gr_ofuncs }, /* ifc (nv05) */ + { 0x0066, &nv04_gr_ofuncs }, /* sifc (nv05) */ + { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ + { 0x0076, &nv04_gr_ofuncs, nv04_gr_sifc_omthds }, + { 0x0077, &nv04_gr_ofuncs, nv04_gr_sifm_omthds }, {}, }; @@ -1037,10 +1031,10 @@ nv04_graph_sclass[] = { * PGRAPH context ******************************************************************************/ -static struct nv04_graph_chan * -nv04_graph_channel(struct nv04_graph_priv *priv) +static struct nv04_gr_chan * +nv04_gr_channel(struct nv04_gr_priv *priv) { - struct nv04_graph_chan *chan = NULL; + struct nv04_gr_chan *chan = NULL; if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24; if (chid < ARRAY_SIZE(priv->chan)) @@ -1050,13 +1044,13 @@ nv04_graph_channel(struct nv04_graph_priv *priv) } static int -nv04_graph_load_context(struct nv04_graph_chan *chan, int chid) +nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) { - struct nv04_graph_priv *priv = nv04_graph_priv(chan); + struct nv04_gr_priv *priv = nv04_gr_priv(chan); int i; - for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) - nv_wr32(priv, nv04_graph_ctx_regs[i], chan->nv04[i]); + for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) + nv_wr32(priv, nv04_gr_ctx_regs[i], chan->nv04[i]); nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100); nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); @@ -1065,13 +1059,13 @@ nv04_graph_load_context(struct nv04_graph_chan *chan, int chid) } static int -nv04_graph_unload_context(struct nv04_graph_chan *chan) +nv04_gr_unload_context(struct nv04_gr_chan *chan) { - struct nv04_graph_priv *priv = nv04_graph_priv(chan); + struct nv04_gr_priv *priv = nv04_gr_priv(chan); int i; - for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) - chan->nv04[i] = nv_rd32(priv, nv04_graph_ctx_regs[i]); + for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) + chan->nv04[i] = nv_rd32(priv, nv04_gr_ctx_regs[i]); nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000); nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); @@ -1079,36 +1073,36 @@ nv04_graph_unload_context(struct nv04_graph_chan *chan) } static void -nv04_graph_context_switch(struct nv04_graph_priv *priv) +nv04_gr_context_switch(struct nv04_gr_priv *priv) { - struct nv04_graph_chan *prev = NULL; - struct nv04_graph_chan *next = NULL; + struct nv04_gr_chan *prev = NULL; + struct nv04_gr_chan *next = NULL; unsigned long flags; int chid; spin_lock_irqsave(&priv->lock, flags); - nv04_graph_idle(priv); + nv04_gr_idle(priv); /* If previous context is valid, we need to save it */ - prev = nv04_graph_channel(priv); + prev = nv04_gr_channel(priv); if (prev) - nv04_graph_unload_context(prev); + nv04_gr_unload_context(prev); /* load context for next channel */ chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; next = priv->chan[chid]; if (next) - nv04_graph_load_context(next, chid); + nv04_gr_load_context(next, chid); spin_unlock_irqrestore(&priv->lock, flags); } -static u32 *ctx_reg(struct nv04_graph_chan *chan, u32 reg) +static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg) { int i; - for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) { - if (nv04_graph_ctx_regs[i] == reg) + for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) { + if (nv04_gr_ctx_regs[i] == reg) return &chan->nv04[i]; } @@ -1116,18 +1110,18 @@ static u32 *ctx_reg(struct nv04_graph_chan *chan, u32 reg) } static int -nv04_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_gr_context_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fifo_chan *fifo = (void *)parent; - struct nv04_graph_priv *priv = (void *)engine; - struct nv04_graph_chan *chan; + struct nvkm_fifo_chan *fifo = (void *)parent; + struct nv04_gr_priv *priv = (void *)engine; + struct nv04_gr_chan *chan; unsigned long flags; int ret; - ret = nouveau_object_create(parent, engine, oclass, 0, &chan); + ret = nvkm_object_create(parent, engine, oclass, 0, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -1137,7 +1131,7 @@ nv04_graph_context_ctor(struct nouveau_object *parent, *pobject = nv_object(priv->chan[fifo->chid]); atomic_inc(&(*pobject)->refcount); spin_unlock_irqrestore(&priv->lock, flags); - nouveau_object_destroy(&chan->base); + nvkm_object_destroy(&chan->base); return 1; } @@ -1150,44 +1144,44 @@ nv04_graph_context_ctor(struct nouveau_object *parent, } static void -nv04_graph_context_dtor(struct nouveau_object *object) +nv04_gr_context_dtor(struct nvkm_object *object) { - struct nv04_graph_priv *priv = (void *)object->engine; - struct nv04_graph_chan *chan = (void *)object; + struct nv04_gr_priv *priv = (void *)object->engine; + struct nv04_gr_chan *chan = (void *)object; unsigned long flags; spin_lock_irqsave(&priv->lock, flags); priv->chan[chan->chid] = NULL; spin_unlock_irqrestore(&priv->lock, flags); - nouveau_object_destroy(&chan->base); + nvkm_object_destroy(&chan->base); } static int -nv04_graph_context_fini(struct nouveau_object *object, bool suspend) +nv04_gr_context_fini(struct nvkm_object *object, bool suspend) { - struct nv04_graph_priv *priv = (void *)object->engine; - struct nv04_graph_chan *chan = (void *)object; + struct nv04_gr_priv *priv = (void *)object->engine; + struct nv04_gr_chan *chan = (void *)object; unsigned long flags; spin_lock_irqsave(&priv->lock, flags); nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); - if (nv04_graph_channel(priv) == chan) - nv04_graph_unload_context(chan); + if (nv04_gr_channel(priv) == chan) + nv04_gr_unload_context(chan); nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); spin_unlock_irqrestore(&priv->lock, flags); - return nouveau_object_fini(&chan->base, suspend); + return nvkm_object_fini(&chan->base, suspend); } -static struct nouveau_oclass -nv04_graph_cclass = { +static struct nvkm_oclass +nv04_gr_cclass = { .handle = NV_ENGCTX(GR, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_graph_context_ctor, - .dtor = nv04_graph_context_dtor, - .init = nouveau_object_init, - .fini = nv04_graph_context_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv04_gr_context_ctor, + .dtor = nv04_gr_context_dtor, + .init = nvkm_object_init, + .fini = nv04_gr_context_fini, }, }; @@ -1196,31 +1190,31 @@ nv04_graph_cclass = { ******************************************************************************/ bool -nv04_graph_idle(void *obj) +nv04_gr_idle(void *obj) { - struct nouveau_graph *graph = nouveau_graph(obj); + struct nvkm_gr *gr = nvkm_gr(obj); u32 mask = 0xffffffff; if (nv_device(obj)->card_type == NV_40) mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; - if (!nv_wait(graph, NV04_PGRAPH_STATUS, mask, 0)) { - nv_error(graph, "idle timed out with status 0x%08x\n", - nv_rd32(graph, NV04_PGRAPH_STATUS)); + if (!nv_wait(gr, NV04_PGRAPH_STATUS, mask, 0)) { + nv_error(gr, "idle timed out with status 0x%08x\n", + nv_rd32(gr, NV04_PGRAPH_STATUS)); return false; } return true; } -static const struct nouveau_bitfield -nv04_graph_intr_name[] = { +static const struct nvkm_bitfield +nv04_gr_intr_name[] = { { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" }, {} }; -static const struct nouveau_bitfield -nv04_graph_nstatus[] = { +static const struct nvkm_bitfield +nv04_gr_nstatus[] = { { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, @@ -1228,8 +1222,8 @@ nv04_graph_nstatus[] = { {} }; -const struct nouveau_bitfield -nv04_graph_nsource[] = { +const struct nvkm_bitfield +nv04_gr_nsource[] = { { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" }, { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" }, { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" }, @@ -1253,12 +1247,12 @@ nv04_graph_nsource[] = { }; static void -nv04_graph_intr(struct nouveau_subdev *subdev) +nv04_gr_intr(struct nvkm_subdev *subdev) { - struct nv04_graph_priv *priv = (void *)subdev; - struct nv04_graph_chan *chan = NULL; - struct nouveau_namedb *namedb = NULL; - struct nouveau_handle *handle = NULL; + struct nv04_gr_priv *priv = (void *)subdev; + struct nv04_gr_chan *chan = NULL; + struct nvkm_namedb *namedb = NULL; + struct nvkm_handle *handle = NULL; u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); @@ -1280,7 +1274,7 @@ nv04_graph_intr(struct nouveau_subdev *subdev) if (stat & NV_PGRAPH_INTR_NOTIFY) { if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { - handle = nouveau_namedb_get_vinst(namedb, inst); + handle = nvkm_namedb_get_vinst(namedb, inst); if (handle && !nv_call(handle->object, mthd, data)) show &= ~NV_PGRAPH_INTR_NOTIFY; } @@ -1290,7 +1284,7 @@ nv04_graph_intr(struct nouveau_subdev *subdev) nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - nv04_graph_context_switch(priv); + nv04_gr_context_switch(priv); } nv_wr32(priv, NV03_PGRAPH_INTR, stat); @@ -1298,50 +1292,50 @@ nv04_graph_intr(struct nouveau_subdev *subdev) if (show) { nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv04_graph_intr_name, show); + nvkm_bitfield_print(nv04_gr_intr_name, show); pr_cont(" nsource:"); - nouveau_bitfield_print(nv04_graph_nsource, nsource); + nvkm_bitfield_print(nv04_gr_nsource, nsource); pr_cont(" nstatus:"); - nouveau_bitfield_print(nv04_graph_nstatus, nstatus); + nvkm_bitfield_print(nv04_gr_nstatus, nstatus); pr_cont("\n"); nv_error(priv, "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, nouveau_client_name(chan), subc, class, mthd, + chid, nvkm_client_name(chan), subc, class, mthd, data); } - nouveau_namedb_put(handle); + nvkm_namedb_put(handle); } static int -nv04_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv04_graph_priv *priv; + struct nv04_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv04_graph_intr; - nv_engine(priv)->cclass = &nv04_graph_cclass; - nv_engine(priv)->sclass = nv04_graph_sclass; + nv_subdev(priv)->intr = nv04_gr_intr; + nv_engine(priv)->cclass = &nv04_gr_cclass; + nv_engine(priv)->sclass = nv04_gr_sclass; spin_lock_init(&priv->lock); return 0; } static int -nv04_graph_init(struct nouveau_object *object) +nv04_gr_init(struct nvkm_object *object) { - struct nouveau_engine *engine = nv_engine(object); - struct nv04_graph_priv *priv = (void *)engine; + struct nvkm_engine *engine = nv_engine(object); + struct nv04_gr_priv *priv = (void *)engine; int ret; - ret = nouveau_graph_init(&priv->base); + ret = nvkm_gr_init(&priv->base); if (ret) return ret; @@ -1376,13 +1370,13 @@ nv04_graph_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass -nv04_graph_oclass = { +struct nvkm_oclass +nv04_gr_oclass = { .handle = NV_ENGINE(GR, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_graph_ctor, - .dtor = _nouveau_graph_dtor, - .init = nv04_graph_init, - .fini = _nouveau_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv04_gr_ctor, + .dtor = _nvkm_gr_dtor, + .init = nv04_gr_init, + .fini = _nvkm_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 2b12b09683c8..389904eb603f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -10,7 +10,7 @@ * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the + * paragr) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR @@ -21,17 +21,14 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#include <engine/gr.h> +#include "regs.h" #include <core/client.h> -#include <core/os.h> +#include <core/device.h> #include <core/handle.h> - -#include <subdev/fb.h> - #include <engine/fifo.h> -#include <engine/graph.h> - -#include "regs.h" +#include <subdev/fb.h> struct pipe_state { u32 pipe_0x0000[0x040/4]; @@ -46,7 +43,7 @@ struct pipe_state { u32 pipe_0x7800[0x0c0/4]; }; -static int nv10_graph_ctx_regs[] = { +static int nv10_gr_ctx_regs[] = { NV10_PGRAPH_CTX_SWITCH(0), NV10_PGRAPH_CTX_SWITCH(1), NV10_PGRAPH_CTX_SWITCH(2), @@ -368,7 +365,7 @@ static int nv10_graph_ctx_regs[] = { NV04_PGRAPH_VALID2, }; -static int nv17_graph_ctx_regs[] = { +static int nv17_gr_ctx_regs[] = { NV10_PGRAPH_DEBUG_4, 0x004006b0, 0x00400eac, @@ -389,24 +386,24 @@ static int nv17_graph_ctx_regs[] = { 0x00400a04, }; -struct nv10_graph_priv { - struct nouveau_graph base; - struct nv10_graph_chan *chan[32]; +struct nv10_gr_priv { + struct nvkm_gr base; + struct nv10_gr_chan *chan[32]; spinlock_t lock; }; -struct nv10_graph_chan { - struct nouveau_object base; +struct nv10_gr_chan { + struct nvkm_object base; int chid; - int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)]; - int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)]; + int nv10[ARRAY_SIZE(nv10_gr_ctx_regs)]; + int nv17[ARRAY_SIZE(nv17_gr_ctx_regs)]; struct pipe_state pipe_state; u32 lma_window[4]; }; -static inline struct nv10_graph_priv * -nv10_graph_priv(struct nv10_graph_chan *chan) +static inline struct nv10_gr_priv * +nv10_gr_priv(struct nv10_gr_chan *chan) { return (void *)nv_object(chan)->engine; } @@ -431,58 +428,58 @@ nv10_graph_priv(struct nv10_graph_chan *chan) nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \ } while (0) -static struct nouveau_oclass -nv10_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs }, /* clip */ - { 0x0030, &nv04_graph_ofuncs }, /* null */ - { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs }, /* rop */ - { 0x0044, &nv04_graph_ofuncs }, /* pattern */ - { 0x004a, &nv04_graph_ofuncs }, /* gdi */ - { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ - { 0x005f, &nv04_graph_ofuncs }, /* blit */ - { 0x0062, &nv04_graph_ofuncs }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs }, /* blit */ - { 0x0093, &nv04_graph_ofuncs }, /* surf3d */ - { 0x0094, &nv04_graph_ofuncs }, /* ttri */ - { 0x0095, &nv04_graph_ofuncs }, /* mtri */ - { 0x0056, &nv04_graph_ofuncs }, /* celcius */ +static struct nvkm_oclass +nv10_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs }, /* clip */ + { 0x0030, &nv04_gr_ofuncs }, /* null */ + { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs }, /* rop */ + { 0x0044, &nv04_gr_ofuncs }, /* pattern */ + { 0x004a, &nv04_gr_ofuncs }, /* gdi */ + { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ + { 0x005f, &nv04_gr_ofuncs }, /* blit */ + { 0x0062, &nv04_gr_ofuncs }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs }, /* blit */ + { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ + { 0x0094, &nv04_gr_ofuncs }, /* ttri */ + { 0x0095, &nv04_gr_ofuncs }, /* mtri */ + { 0x0056, &nv04_gr_ofuncs }, /* celcius */ {}, }; -static struct nouveau_oclass -nv15_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs }, /* clip */ - { 0x0030, &nv04_graph_ofuncs }, /* null */ - { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs }, /* rop */ - { 0x0044, &nv04_graph_ofuncs }, /* pattern */ - { 0x004a, &nv04_graph_ofuncs }, /* gdi */ - { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ - { 0x005f, &nv04_graph_ofuncs }, /* blit */ - { 0x0062, &nv04_graph_ofuncs }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs }, /* blit */ - { 0x0093, &nv04_graph_ofuncs }, /* surf3d */ - { 0x0094, &nv04_graph_ofuncs }, /* ttri */ - { 0x0095, &nv04_graph_ofuncs }, /* mtri */ - { 0x0096, &nv04_graph_ofuncs }, /* celcius */ +static struct nvkm_oclass +nv15_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs }, /* clip */ + { 0x0030, &nv04_gr_ofuncs }, /* null */ + { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs }, /* rop */ + { 0x0044, &nv04_gr_ofuncs }, /* pattern */ + { 0x004a, &nv04_gr_ofuncs }, /* gdi */ + { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ + { 0x005f, &nv04_gr_ofuncs }, /* blit */ + { 0x0062, &nv04_gr_ofuncs }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs }, /* blit */ + { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ + { 0x0094, &nv04_gr_ofuncs }, /* ttri */ + { 0x0095, &nv04_gr_ofuncs }, /* mtri */ + { 0x0096, &nv04_gr_ofuncs }, /* celcius */ {}, }; static int -nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv10_graph_chan *chan = (void *)object->parent; - struct nv10_graph_priv *priv = nv10_graph_priv(chan); + struct nv10_gr_chan *chan = (void *)object->parent; + struct nv10_gr_priv *priv = nv10_gr_priv(chan); struct pipe_state *pipe = &chan->pipe_state; u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3]; u32 xfmode0, xfmode1; @@ -494,14 +491,14 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd, if (mthd != 0x1644) return 0; - nv04_graph_idle(priv); + nv04_gr_idle(priv); PIPE_SAVE(priv, pipe_0x0040, 0x0040); PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200); PIPE_RESTORE(priv, chan->lma_window, 0x6790); - nv04_graph_idle(priv); + nv04_gr_idle(priv); xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); @@ -511,7 +508,7 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd, PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0); PIPE_SAVE(priv, pipe_0x6a80, 0x6a80); - nv04_graph_idle(priv); + nv04_gr_idle(priv); nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); @@ -534,7 +531,7 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd, PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); - nv04_graph_idle(priv); + nv04_gr_idle(priv); PIPE_RESTORE(priv, pipe_0x0040, 0x0040); @@ -549,55 +546,55 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd, nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv04_graph_idle(priv); + nv04_gr_idle(priv); return 0; } static int -nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv17_gr_mthd_lma_enable(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv10_graph_chan *chan = (void *)object->parent; - struct nv10_graph_priv *priv = nv10_graph_priv(chan); + struct nv10_gr_chan *chan = (void *)object->parent; + struct nv10_gr_priv *priv = nv10_gr_priv(chan); - nv04_graph_idle(priv); + nv04_gr_idle(priv); nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000); return 0; } -static struct nouveau_omthds +static struct nvkm_omthds nv17_celcius_omthds[] = { - { 0x1638, 0x1638, nv17_graph_mthd_lma_window }, - { 0x163c, 0x163c, nv17_graph_mthd_lma_window }, - { 0x1640, 0x1640, nv17_graph_mthd_lma_window }, - { 0x1644, 0x1644, nv17_graph_mthd_lma_window }, - { 0x1658, 0x1658, nv17_graph_mthd_lma_enable }, + { 0x1638, 0x1638, nv17_gr_mthd_lma_window }, + { 0x163c, 0x163c, nv17_gr_mthd_lma_window }, + { 0x1640, 0x1640, nv17_gr_mthd_lma_window }, + { 0x1644, 0x1644, nv17_gr_mthd_lma_window }, + { 0x1658, 0x1658, nv17_gr_mthd_lma_enable }, {} }; -static struct nouveau_oclass -nv17_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs }, /* clip */ - { 0x0030, &nv04_graph_ofuncs }, /* null */ - { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs }, /* rop */ - { 0x0044, &nv04_graph_ofuncs }, /* pattern */ - { 0x004a, &nv04_graph_ofuncs }, /* gdi */ - { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ - { 0x005f, &nv04_graph_ofuncs }, /* blit */ - { 0x0062, &nv04_graph_ofuncs }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs }, /* blit */ - { 0x0093, &nv04_graph_ofuncs }, /* surf3d */ - { 0x0094, &nv04_graph_ofuncs }, /* ttri */ - { 0x0095, &nv04_graph_ofuncs }, /* mtri */ - { 0x0099, &nv04_graph_ofuncs, nv17_celcius_omthds }, +static struct nvkm_oclass +nv17_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs }, /* clip */ + { 0x0030, &nv04_gr_ofuncs }, /* null */ + { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs }, /* rop */ + { 0x0044, &nv04_gr_ofuncs }, /* pattern */ + { 0x004a, &nv04_gr_ofuncs }, /* gdi */ + { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ + { 0x005f, &nv04_gr_ofuncs }, /* blit */ + { 0x0062, &nv04_gr_ofuncs }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs }, /* blit */ + { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ + { 0x0094, &nv04_gr_ofuncs }, /* ttri */ + { 0x0095, &nv04_gr_ofuncs }, /* mtri */ + { 0x0099, &nv04_gr_ofuncs, nv17_celcius_omthds }, {}, }; @@ -605,10 +602,10 @@ nv17_graph_sclass[] = { * PGRAPH context ******************************************************************************/ -static struct nv10_graph_chan * -nv10_graph_channel(struct nv10_graph_priv *priv) +static struct nv10_gr_chan * +nv10_gr_channel(struct nv10_gr_priv *priv) { - struct nv10_graph_chan *chan = NULL; + struct nv10_gr_chan *chan = NULL; if (nv_rd32(priv, 0x400144) & 0x00010000) { int chid = nv_rd32(priv, 0x400148) >> 24; if (chid < ARRAY_SIZE(priv->chan)) @@ -618,9 +615,9 @@ nv10_graph_channel(struct nv10_graph_priv *priv) } static void -nv10_graph_save_pipe(struct nv10_graph_chan *chan) +nv10_gr_save_pipe(struct nv10_gr_chan *chan) { - struct nv10_graph_priv *priv = nv10_graph_priv(chan); + struct nv10_gr_priv *priv = nv10_gr_priv(chan); struct pipe_state *pipe = &chan->pipe_state; PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400); @@ -636,14 +633,14 @@ nv10_graph_save_pipe(struct nv10_graph_chan *chan) } static void -nv10_graph_load_pipe(struct nv10_graph_chan *chan) +nv10_gr_load_pipe(struct nv10_gr_chan *chan) { - struct nv10_graph_priv *priv = nv10_graph_priv(chan); + struct nv10_gr_priv *priv = nv10_gr_priv(chan); struct pipe_state *pipe = &chan->pipe_state; u32 xfmode0, xfmode1; int i; - nv04_graph_idle(priv); + nv04_gr_idle(priv); /* XXX check haiku comments */ xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); @@ -668,7 +665,7 @@ nv10_graph_load_pipe(struct nv10_graph_chan *chan) PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); - nv04_graph_idle(priv); + nv04_gr_idle(priv); /* restore XFMODE */ nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0); @@ -682,13 +679,13 @@ nv10_graph_load_pipe(struct nv10_graph_chan *chan) PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400); PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000); PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040); - nv04_graph_idle(priv); + nv04_gr_idle(priv); } static void -nv10_graph_create_pipe(struct nv10_graph_chan *chan) +nv10_gr_create_pipe(struct nv10_gr_chan *chan) { - struct nv10_graph_priv *priv = nv10_graph_priv(chan); + struct nv10_gr_priv *priv = nv10_gr_priv(chan); struct pipe_state *pipe_state = &chan->pipe_state; u32 *pipe_state_addr; int i; @@ -841,11 +838,11 @@ nv10_graph_create_pipe(struct nv10_graph_chan *chan) } static int -nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg) +nv10_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg) { int i; - for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) { - if (nv10_graph_ctx_regs[i] == reg) + for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) { + if (nv10_gr_ctx_regs[i] == reg) return i; } nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg); @@ -853,11 +850,11 @@ nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg) } static int -nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg) +nv17_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg) { int i; - for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) { - if (nv17_graph_ctx_regs[i] == reg) + for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) { + if (nv17_gr_ctx_regs[i] == reg) return i; } nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg); @@ -865,9 +862,9 @@ nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg) } static void -nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst) +nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) { - struct nv10_graph_priv *priv = nv10_graph_priv(chan); + struct nv10_gr_priv *priv = nv10_gr_priv(chan); u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4]; u32 ctx_user, ctx_switch[5]; int i, subchan = -1; @@ -935,25 +932,25 @@ nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst) } static int -nv10_graph_load_context(struct nv10_graph_chan *chan, int chid) +nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) { - struct nv10_graph_priv *priv = nv10_graph_priv(chan); + struct nv10_gr_priv *priv = nv10_gr_priv(chan); u32 inst; int i; - for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) - nv_wr32(priv, nv10_graph_ctx_regs[i], chan->nv10[i]); + for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) + nv_wr32(priv, nv10_gr_ctx_regs[i], chan->nv10[i]); if (nv_device(priv)->card_type >= NV_11 && nv_device(priv)->chipset >= 0x17) { - for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) - nv_wr32(priv, nv17_graph_ctx_regs[i], chan->nv17[i]); + for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) + nv_wr32(priv, nv17_gr_ctx_regs[i], chan->nv17[i]); } - nv10_graph_load_pipe(chan); + nv10_gr_load_pipe(chan); inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; - nv10_graph_load_dma_vtxbuf(chan, chid, inst); + nv10_gr_load_dma_vtxbuf(chan, chid, inst); nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); @@ -962,21 +959,21 @@ nv10_graph_load_context(struct nv10_graph_chan *chan, int chid) } static int -nv10_graph_unload_context(struct nv10_graph_chan *chan) +nv10_gr_unload_context(struct nv10_gr_chan *chan) { - struct nv10_graph_priv *priv = nv10_graph_priv(chan); + struct nv10_gr_priv *priv = nv10_gr_priv(chan); int i; - for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) - chan->nv10[i] = nv_rd32(priv, nv10_graph_ctx_regs[i]); + for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) + chan->nv10[i] = nv_rd32(priv, nv10_gr_ctx_regs[i]); if (nv_device(priv)->card_type >= NV_11 && nv_device(priv)->chipset >= 0x17) { - for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) - chan->nv17[i] = nv_rd32(priv, nv17_graph_ctx_regs[i]); + for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) + chan->nv17[i] = nv_rd32(priv, nv17_gr_ctx_regs[i]); } - nv10_graph_save_pipe(chan); + nv10_gr_save_pipe(chan); nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000); nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); @@ -984,55 +981,54 @@ nv10_graph_unload_context(struct nv10_graph_chan *chan) } static void -nv10_graph_context_switch(struct nv10_graph_priv *priv) +nv10_gr_context_switch(struct nv10_gr_priv *priv) { - struct nv10_graph_chan *prev = NULL; - struct nv10_graph_chan *next = NULL; + struct nv10_gr_chan *prev = NULL; + struct nv10_gr_chan *next = NULL; unsigned long flags; int chid; spin_lock_irqsave(&priv->lock, flags); - nv04_graph_idle(priv); + nv04_gr_idle(priv); /* If previous context is valid, we need to save it */ - prev = nv10_graph_channel(priv); + prev = nv10_gr_channel(priv); if (prev) - nv10_graph_unload_context(prev); + nv10_gr_unload_context(prev); /* load context for next channel */ chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; next = priv->chan[chid]; if (next) - nv10_graph_load_context(next, chid); + nv10_gr_load_context(next, chid); spin_unlock_irqrestore(&priv->lock, flags); } #define NV_WRITE_CTX(reg, val) do { \ - int offset = nv10_graph_ctx_regs_find_offset(priv, reg); \ + int offset = nv10_gr_ctx_regs_find_offset(priv, reg); \ if (offset > 0) \ chan->nv10[offset] = val; \ } while (0) #define NV17_WRITE_CTX(reg, val) do { \ - int offset = nv17_graph_ctx_regs_find_offset(priv, reg); \ + int offset = nv17_gr_ctx_regs_find_offset(priv, reg); \ if (offset > 0) \ chan->nv17[offset] = val; \ } while (0) static int -nv10_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fifo_chan *fifo = (void *)parent; - struct nv10_graph_priv *priv = (void *)engine; - struct nv10_graph_chan *chan; + struct nvkm_fifo_chan *fifo = (void *)parent; + struct nv10_gr_priv *priv = (void *)engine; + struct nv10_gr_chan *chan; unsigned long flags; int ret; - ret = nouveau_object_create(parent, engine, oclass, 0, &chan); + ret = nvkm_object_create(parent, engine, oclass, 0, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -1042,7 +1038,7 @@ nv10_graph_context_ctor(struct nouveau_object *parent, *pobject = nv_object(priv->chan[fifo->chid]); atomic_inc(&(*pobject)->refcount); spin_unlock_irqrestore(&priv->lock, flags); - nouveau_object_destroy(&chan->base); + nvkm_object_destroy(&chan->base); return 1; } @@ -1066,7 +1062,7 @@ nv10_graph_context_ctor(struct nouveau_object *parent, } NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24); - nv10_graph_create_pipe(chan); + nv10_gr_create_pipe(chan); priv->chan[fifo->chid] = chan; chan->chid = fifo->chid; @@ -1075,44 +1071,44 @@ nv10_graph_context_ctor(struct nouveau_object *parent, } static void -nv10_graph_context_dtor(struct nouveau_object *object) +nv10_gr_context_dtor(struct nvkm_object *object) { - struct nv10_graph_priv *priv = (void *)object->engine; - struct nv10_graph_chan *chan = (void *)object; + struct nv10_gr_priv *priv = (void *)object->engine; + struct nv10_gr_chan *chan = (void *)object; unsigned long flags; spin_lock_irqsave(&priv->lock, flags); priv->chan[chan->chid] = NULL; spin_unlock_irqrestore(&priv->lock, flags); - nouveau_object_destroy(&chan->base); + nvkm_object_destroy(&chan->base); } static int -nv10_graph_context_fini(struct nouveau_object *object, bool suspend) +nv10_gr_context_fini(struct nvkm_object *object, bool suspend) { - struct nv10_graph_priv *priv = (void *)object->engine; - struct nv10_graph_chan *chan = (void *)object; + struct nv10_gr_priv *priv = (void *)object->engine; + struct nv10_gr_chan *chan = (void *)object; unsigned long flags; spin_lock_irqsave(&priv->lock, flags); nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); - if (nv10_graph_channel(priv) == chan) - nv10_graph_unload_context(chan); + if (nv10_gr_channel(priv) == chan) + nv10_gr_unload_context(chan); nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); spin_unlock_irqrestore(&priv->lock, flags); - return nouveau_object_fini(&chan->base, suspend); + return nvkm_object_fini(&chan->base, suspend); } -static struct nouveau_oclass -nv10_graph_cclass = { +static struct nvkm_oclass +nv10_gr_cclass = { .handle = NV_ENGCTX(GR, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv10_graph_context_ctor, - .dtor = nv10_graph_context_dtor, - .init = nouveau_object_init, - .fini = nv10_graph_context_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv10_gr_context_ctor, + .dtor = nv10_gr_context_dtor, + .init = nvkm_object_init, + .fini = nv10_gr_context_fini, }, }; @@ -1121,15 +1117,15 @@ nv10_graph_cclass = { ******************************************************************************/ static void -nv10_graph_tile_prog(struct nouveau_engine *engine, int i) +nv10_gr_tile_prog(struct nvkm_engine *engine, int i) { - struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; - struct nouveau_fifo *pfifo = nouveau_fifo(engine); - struct nv10_graph_priv *priv = (void *)engine; + struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; + struct nvkm_fifo *pfifo = nvkm_fifo(engine); + struct nv10_gr_priv *priv = (void *)engine; unsigned long flags; pfifo->pause(pfifo, &flags); - nv04_graph_idle(priv); + nv04_gr_idle(priv); nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit); nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch); @@ -1138,13 +1134,13 @@ nv10_graph_tile_prog(struct nouveau_engine *engine, int i) pfifo->start(pfifo, &flags); } -const struct nouveau_bitfield nv10_graph_intr_name[] = { +const struct nvkm_bitfield nv10_gr_intr_name[] = { { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" }, { NV_PGRAPH_INTR_ERROR, "ERROR" }, {} }; -const struct nouveau_bitfield nv10_graph_nstatus[] = { +const struct nvkm_bitfield nv10_gr_nstatus[] = { { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, @@ -1153,12 +1149,12 @@ const struct nouveau_bitfield nv10_graph_nstatus[] = { }; static void -nv10_graph_intr(struct nouveau_subdev *subdev) +nv10_gr_intr(struct nvkm_subdev *subdev) { - struct nv10_graph_priv *priv = (void *)subdev; - struct nv10_graph_chan *chan = NULL; - struct nouveau_namedb *namedb = NULL; - struct nouveau_handle *handle = NULL; + struct nv10_gr_priv *priv = (void *)subdev; + struct nv10_gr_chan *chan = NULL; + struct nvkm_namedb *namedb = NULL; + struct nvkm_handle *handle = NULL; u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); @@ -1179,7 +1175,7 @@ nv10_graph_intr(struct nouveau_subdev *subdev) if (stat & NV_PGRAPH_INTR_ERROR) { if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { - handle = nouveau_namedb_get_class(namedb, class); + handle = nvkm_namedb_get_class(namedb, class); if (handle && !nv_call(handle->object, mthd, data)) show &= ~NV_PGRAPH_INTR_ERROR; } @@ -1189,7 +1185,7 @@ nv10_graph_intr(struct nouveau_subdev *subdev) nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - nv10_graph_context_switch(priv); + nv10_gr_context_switch(priv); } nv_wr32(priv, NV03_PGRAPH_INTR, stat); @@ -1197,68 +1193,68 @@ nv10_graph_intr(struct nouveau_subdev *subdev) if (show) { nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv10_graph_intr_name, show); + nvkm_bitfield_print(nv10_gr_intr_name, show); pr_cont(" nsource:"); - nouveau_bitfield_print(nv04_graph_nsource, nsource); + nvkm_bitfield_print(nv04_gr_nsource, nsource); pr_cont(" nstatus:"); - nouveau_bitfield_print(nv10_graph_nstatus, nstatus); + nvkm_bitfield_print(nv10_gr_nstatus, nstatus); pr_cont("\n"); nv_error(priv, "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, nouveau_client_name(chan), subc, class, mthd, + chid, nvkm_client_name(chan), subc, class, mthd, data); } - nouveau_namedb_put(handle); + nvkm_namedb_put(handle); } static int -nv10_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv10_graph_priv *priv; + struct nv10_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv10_graph_intr; - nv_engine(priv)->cclass = &nv10_graph_cclass; + nv_subdev(priv)->intr = nv10_gr_intr; + nv_engine(priv)->cclass = &nv10_gr_cclass; if (nv_device(priv)->chipset <= 0x10) - nv_engine(priv)->sclass = nv10_graph_sclass; + nv_engine(priv)->sclass = nv10_gr_sclass; else if (nv_device(priv)->chipset < 0x17 || nv_device(priv)->card_type < NV_11) - nv_engine(priv)->sclass = nv15_graph_sclass; + nv_engine(priv)->sclass = nv15_gr_sclass; else - nv_engine(priv)->sclass = nv17_graph_sclass; + nv_engine(priv)->sclass = nv17_gr_sclass; - nv_engine(priv)->tile_prog = nv10_graph_tile_prog; + nv_engine(priv)->tile_prog = nv10_gr_tile_prog; spin_lock_init(&priv->lock); return 0; } static void -nv10_graph_dtor(struct nouveau_object *object) +nv10_gr_dtor(struct nvkm_object *object) { - struct nv10_graph_priv *priv = (void *)object; - nouveau_graph_destroy(&priv->base); + struct nv10_gr_priv *priv = (void *)object; + nvkm_gr_destroy(&priv->base); } static int -nv10_graph_init(struct nouveau_object *object) +nv10_gr_init(struct nvkm_object *object) { - struct nouveau_engine *engine = nv_engine(object); - struct nouveau_fb *pfb = nouveau_fb(object); - struct nv10_graph_priv *priv = (void *)engine; + struct nvkm_engine *engine = nv_engine(object); + struct nvkm_fb *pfb = nvkm_fb(object); + struct nv10_gr_priv *priv = (void *)engine; int ret, i; - ret = nouveau_graph_init(&priv->base); + ret = nvkm_gr_init(&priv->base); if (ret) return ret; @@ -1301,19 +1297,19 @@ nv10_graph_init(struct nouveau_object *object) } static int -nv10_graph_fini(struct nouveau_object *object, bool suspend) +nv10_gr_fini(struct nvkm_object *object, bool suspend) { - struct nv10_graph_priv *priv = (void *)object; - return nouveau_graph_fini(&priv->base, suspend); + struct nv10_gr_priv *priv = (void *)object; + return nvkm_gr_fini(&priv->base, suspend); } -struct nouveau_oclass -nv10_graph_oclass = { +struct nvkm_oclass +nv10_gr_oclass = { .handle = NV_ENGINE(GR, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv10_graph_ctor, - .dtor = nv10_graph_dtor, - .init = nv10_graph_init, - .fini = nv10_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv10_gr_ctor, + .dtor = nv10_gr_dtor, + .init = nv10_gr_init, + .fini = nv10_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index ceb9c746d94e..1713ffb669e8 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -1,39 +1,34 @@ +#include "nv20.h" +#include "regs.h" + #include <core/client.h> -#include <core/os.h> -#include <core/engctx.h> +#include <core/device.h> #include <core/handle.h> -#include <core/enum.h> - -#include <subdev/timer.h> -#include <subdev/fb.h> - -#include <engine/graph.h> #include <engine/fifo.h> - -#include "nv20.h" -#include "regs.h" +#include <subdev/fb.h> +#include <subdev/timer.h> /******************************************************************************* * Graphics object classes ******************************************************************************/ -static struct nouveau_oclass -nv20_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */ - { 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */ - { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ +static struct nvkm_oclass +nv20_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ + { 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */ + { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ {}, }; @@ -42,22 +37,20 @@ nv20_graph_sclass[] = { ******************************************************************************/ static int -nv20_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_chan *chan; + struct nv20_gr_chan *chan; int ret, i; - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, - 0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC, - &chan); + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; - chan->chid = nouveau_fifo_chan(parent)->chid; + chan->chid = nvkm_fifo_chan(parent)->chid; nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); nv_wo32(chan, 0x033c, 0xffff0000); @@ -107,13 +100,13 @@ nv20_graph_context_ctor(struct nouveau_object *parent, } int -nv20_graph_context_init(struct nouveau_object *object) +nv20_gr_context_init(struct nvkm_object *object) { - struct nv20_graph_priv *priv = (void *)object->engine; - struct nv20_graph_chan *chan = (void *)object; + struct nv20_gr_priv *priv = (void *)object->engine; + struct nv20_gr_chan *chan = (void *)object; int ret; - ret = nouveau_graph_context_init(&chan->base); + ret = nvkm_gr_context_init(&chan->base); if (ret) return ret; @@ -122,10 +115,10 @@ nv20_graph_context_init(struct nouveau_object *object) } int -nv20_graph_context_fini(struct nouveau_object *object, bool suspend) +nv20_gr_context_fini(struct nvkm_object *object, bool suspend) { - struct nv20_graph_priv *priv = (void *)object->engine; - struct nv20_graph_chan *chan = (void *)object; + struct nv20_gr_priv *priv = (void *)object->engine; + struct nv20_gr_chan *chan = (void *)object; int chid = -1; nv_mask(priv, 0x400720, 0x00000001, 0x00000000); @@ -141,19 +134,19 @@ nv20_graph_context_fini(struct nouveau_object *object, bool suspend) nv_mask(priv, 0x400720, 0x00000001, 0x00000001); nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000); - return nouveau_graph_context_fini(&chan->base, suspend); + return nvkm_gr_context_fini(&chan->base, suspend); } -static struct nouveau_oclass -nv20_graph_cclass = { +static struct nvkm_oclass +nv20_gr_cclass = { .handle = NV_ENGCTX(GR, 0x20), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv20_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv20_gr_context_ctor, + .dtor = _nvkm_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, }; @@ -162,15 +155,15 @@ nv20_graph_cclass = { ******************************************************************************/ void -nv20_graph_tile_prog(struct nouveau_engine *engine, int i) +nv20_gr_tile_prog(struct nvkm_engine *engine, int i) { - struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; - struct nouveau_fifo *pfifo = nouveau_fifo(engine); - struct nv20_graph_priv *priv = (void *)engine; + struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; + struct nvkm_fifo *pfifo = nvkm_fifo(engine); + struct nv20_gr_priv *priv = (void *)engine; unsigned long flags; pfifo->pause(pfifo, &flags); - nv04_graph_idle(priv); + nv04_gr_idle(priv); nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); @@ -193,12 +186,12 @@ nv20_graph_tile_prog(struct nouveau_engine *engine, int i) } void -nv20_graph_intr(struct nouveau_subdev *subdev) +nv20_gr_intr(struct nvkm_subdev *subdev) { - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle; - struct nv20_graph_priv *priv = (void *)subdev; + struct nvkm_engine *engine = nv_engine(subdev); + struct nvkm_object *engctx; + struct nvkm_handle *handle; + struct nv20_gr_priv *priv = (void *)subdev; u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); @@ -210,13 +203,13 @@ nv20_graph_intr(struct nouveau_subdev *subdev) u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; u32 show = stat; - engctx = nouveau_engctx_get(engine, chid); + engctx = nvkm_engctx_get(engine, chid); if (stat & NV_PGRAPH_INTR_ERROR) { if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { - handle = nouveau_handle_get_class(engctx, class); + handle = nvkm_handle_get_class(engctx, class); if (handle && !nv_call(handle->object, mthd, data)) show &= ~NV_PGRAPH_INTR_ERROR; - nouveau_handle_put(handle); + nvkm_handle_put(handle); } } @@ -225,65 +218,65 @@ nv20_graph_intr(struct nouveau_subdev *subdev) if (show) { nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv10_graph_intr_name, show); + nvkm_bitfield_print(nv10_gr_intr_name, show); pr_cont(" nsource:"); - nouveau_bitfield_print(nv04_graph_nsource, nsource); + nvkm_bitfield_print(nv04_gr_nsource, nsource); pr_cont(" nstatus:"); - nouveau_bitfield_print(nv10_graph_nstatus, nstatus); + nvkm_bitfield_print(nv10_gr_nstatus, nstatus); pr_cont("\n"); nv_error(priv, "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, nouveau_client_name(engctx), subc, class, mthd, + chid, nvkm_client_name(engctx), subc, class, mthd, data); } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } static int -nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_priv *priv; + struct nv20_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv20_graph_cclass; - nv_engine(priv)->sclass = nv20_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv20_gr_cclass; + nv_engine(priv)->sclass = nv20_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; return 0; } void -nv20_graph_dtor(struct nouveau_object *object) +nv20_gr_dtor(struct nvkm_object *object) { - struct nv20_graph_priv *priv = (void *)object; - nouveau_gpuobj_ref(NULL, &priv->ctxtab); - nouveau_graph_destroy(&priv->base); + struct nv20_gr_priv *priv = (void *)object; + nvkm_gpuobj_ref(NULL, &priv->ctxtab); + nvkm_gr_destroy(&priv->base); } int -nv20_graph_init(struct nouveau_object *object) +nv20_gr_init(struct nvkm_object *object) { - struct nouveau_engine *engine = nv_engine(object); - struct nv20_graph_priv *priv = (void *)engine; - struct nouveau_fb *pfb = nouveau_fb(object); + struct nvkm_engine *engine = nv_engine(object); + struct nv20_gr_priv *priv = (void *)engine; + struct nvkm_fb *pfb = nvkm_fb(object); u32 tmp, vramsz; int ret, i; - ret = nouveau_graph_init(&priv->base); + ret = nvkm_gr_init(&priv->base); if (ret) return ret; @@ -371,13 +364,13 @@ nv20_graph_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass -nv20_graph_oclass = { +struct nvkm_oclass +nv20_gr_oclass = { .handle = NV_ENGINE(GR, 0x20), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv20_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv20_graph_init, - .fini = _nouveau_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv20_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv20_gr_init, + .fini = _nvkm_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h new file mode 100644 index 000000000000..ac4dc048fed1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h @@ -0,0 +1,26 @@ +#ifndef __NV20_GR_H__ +#define __NV20_GR_H__ +#include <engine/gr.h> + +struct nv20_gr_priv { + struct nvkm_gr base; + struct nvkm_gpuobj *ctxtab; +}; + +struct nv20_gr_chan { + struct nvkm_gr_chan base; + int chid; +}; + +extern struct nvkm_oclass nv25_gr_sclass[]; +int nv20_gr_context_init(struct nvkm_object *); +int nv20_gr_context_fini(struct nvkm_object *, bool); + +void nv20_gr_tile_prog(struct nvkm_engine *, int); +void nv20_gr_intr(struct nvkm_subdev *); + +void nv20_gr_dtor(struct nvkm_object *); +int nv20_gr_init(struct nvkm_object *); + +int nv30_gr_init(struct nvkm_object *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index f8a6fdd7d5e8..bc362519cebb 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -1,36 +1,29 @@ -#include <core/os.h> -#include <core/engctx.h> -#include <core/enum.h> - -#include <subdev/timer.h> -#include <subdev/fb.h> - -#include <engine/graph.h> - #include "nv20.h" #include "regs.h" +#include <engine/fifo.h> + /******************************************************************************* * Graphics object classes ******************************************************************************/ -struct nouveau_oclass -nv25_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */ - { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ - { 0x0597, &nv04_graph_ofuncs, NULL }, /* kelvin */ +struct nvkm_oclass +nv25_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ + { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ + { 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */ {}, }; @@ -39,21 +32,20 @@ nv25_graph_sclass[] = { ******************************************************************************/ static int -nv25_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_chan *chan; + struct nv20_gr_chan *chan; int ret, i; - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x3724, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; - chan->chid = nouveau_fifo_chan(parent)->chid; + chan->chid = nvkm_fifo_chan(parent)->chid; nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); nv_wo32(chan, 0x035c, 0xffff0000); @@ -111,16 +103,16 @@ nv25_graph_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass -nv25_graph_cclass = { +static struct nvkm_oclass +nv25_gr_cclass = { .handle = NV_ENGCTX(GR, 0x25), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv25_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv25_gr_context_ctor, + .dtor = _nvkm_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, }; @@ -129,38 +121,38 @@ nv25_graph_cclass = { ******************************************************************************/ static int -nv25_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_priv *priv; + struct nv20_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv25_graph_cclass; - nv_engine(priv)->sclass = nv25_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv25_gr_cclass; + nv_engine(priv)->sclass = nv25_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; return 0; } -struct nouveau_oclass -nv25_graph_oclass = { +struct nvkm_oclass +nv25_gr_oclass = { .handle = NV_ENGINE(GR, 0x25), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv25_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv20_graph_init, - .fini = _nouveau_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv25_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv20_gr_init, + .fini = _nvkm_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index 5de9caa2ef67..22a5096e283d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -1,35 +1,27 @@ -#include <core/os.h> -#include <core/engctx.h> -#include <core/enum.h> - -#include <subdev/timer.h> -#include <subdev/fb.h> - -#include <engine/graph.h> - #include "nv20.h" #include "regs.h" +#include <engine/fifo.h> + /******************************************************************************* * PGRAPH context ******************************************************************************/ static int -nv2a_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_chan *chan; + struct nv20_gr_chan *chan; int ret, i; - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x36b0, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; - chan->chid = nouveau_fifo_chan(parent)->chid; + chan->chid = nvkm_fifo_chan(parent)->chid; nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); nv_wo32(chan, 0x033c, 0xffff0000); @@ -78,16 +70,16 @@ nv2a_graph_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass -nv2a_graph_cclass = { +static struct nvkm_oclass +nv2a_gr_cclass = { .handle = NV_ENGCTX(GR, 0x2a), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv2a_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv2a_gr_context_ctor, + .dtor = _nvkm_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, }; @@ -96,38 +88,38 @@ nv2a_graph_cclass = { ******************************************************************************/ static int -nv2a_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_priv *priv; + struct nv20_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv2a_graph_cclass; - nv_engine(priv)->sclass = nv25_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv2a_gr_cclass; + nv_engine(priv)->sclass = nv25_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; return 0; } -struct nouveau_oclass -nv2a_graph_oclass = { +struct nvkm_oclass +nv2a_gr_oclass = { .handle = NV_ENGINE(GR, 0x2a), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv2a_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv20_graph_init, - .fini = _nouveau_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv2a_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv20_gr_init, + .fini = _nvkm_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 2f9dbc709389..dcc84eb54fb6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -1,38 +1,33 @@ -#include <core/os.h> -#include <core/engctx.h> -#include <core/enum.h> - -#include <subdev/timer.h> -#include <subdev/fb.h> - -#include <engine/graph.h> - #include "nv20.h" #include "regs.h" +#include <core/device.h> +#include <engine/fifo.h> +#include <subdev/fb.h> + /******************************************************************************* * Graphics object classes ******************************************************************************/ -static struct nouveau_oclass -nv30_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ - { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */ - { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */ - { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */ - { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */ - { 0x0397, &nv04_graph_ofuncs, NULL }, /* rankine */ +static struct nvkm_oclass +nv30_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ + { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ + { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ + { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ + { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ + { 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */ {}, }; @@ -41,21 +36,20 @@ nv30_graph_sclass[] = { ******************************************************************************/ static int -nv30_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_chan *chan; + struct nv20_gr_chan *chan; int ret, i; - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x5f48, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; - chan->chid = nouveau_fifo_chan(parent)->chid; + chan->chid = nvkm_fifo_chan(parent)->chid; nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); nv_wo32(chan, 0x0410, 0x00000101); @@ -112,16 +106,16 @@ nv30_graph_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass -nv30_graph_cclass = { +static struct nvkm_oclass +nv30_gr_cclass = { .handle = NV_ENGCTX(GR, 0x30), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv30_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv30_gr_context_ctor, + .dtor = _nvkm_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, }; @@ -130,40 +124,40 @@ nv30_graph_cclass = { ******************************************************************************/ static int -nv30_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_priv *priv; + struct nv20_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv30_graph_cclass; - nv_engine(priv)->sclass = nv30_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv30_gr_cclass; + nv_engine(priv)->sclass = nv30_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; return 0; } int -nv30_graph_init(struct nouveau_object *object) +nv30_gr_init(struct nvkm_object *object) { - struct nouveau_engine *engine = nv_engine(object); - struct nv20_graph_priv *priv = (void *)engine; - struct nouveau_fb *pfb = nouveau_fb(object); + struct nvkm_engine *engine = nv_engine(object); + struct nv20_gr_priv *priv = (void *)engine; + struct nvkm_fb *pfb = nvkm_fb(object); int ret, i; - ret = nouveau_graph_init(&priv->base); + ret = nvkm_gr_init(&priv->base); if (ret) return ret; @@ -225,13 +219,13 @@ nv30_graph_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass -nv30_graph_oclass = { +struct nvkm_oclass +nv30_gr_oclass = { .handle = NV_ENGINE(GR, 0x30), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv30_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv30_graph_init, - .fini = _nouveau_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv30_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv30_gr_init, + .fini = _nvkm_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index 34dd26c70b64..985b7f3306ae 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -1,38 +1,31 @@ -#include <core/os.h> -#include <core/engctx.h> -#include <core/enum.h> - -#include <subdev/timer.h> -#include <subdev/fb.h> - -#include <engine/graph.h> - #include "nv20.h" #include "regs.h" +#include <engine/fifo.h> + /******************************************************************************* * Graphics object classes ******************************************************************************/ -static struct nouveau_oclass -nv34_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ - { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */ - { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */ - { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */ - { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */ - { 0x0697, &nv04_graph_ofuncs, NULL }, /* rankine */ +static struct nvkm_oclass +nv34_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ + { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ + { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ + { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ + { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ + { 0x0697, &nv04_gr_ofuncs, NULL }, /* rankine */ {}, }; @@ -41,21 +34,20 @@ nv34_graph_sclass[] = { ******************************************************************************/ static int -nv34_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_chan *chan; + struct nv20_gr_chan *chan; int ret, i; - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x46dc, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x46dc, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; - chan->chid = nouveau_fifo_chan(parent)->chid; + chan->chid = nvkm_fifo_chan(parent)->chid; nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); nv_wo32(chan, 0x040c, 0x01000101); @@ -112,16 +104,16 @@ nv34_graph_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass -nv34_graph_cclass = { +static struct nvkm_oclass +nv34_gr_cclass = { .handle = NV_ENGCTX(GR, 0x34), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv34_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv34_gr_context_ctor, + .dtor = _nvkm_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, }; @@ -130,38 +122,38 @@ nv34_graph_cclass = { ******************************************************************************/ static int -nv34_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_priv *priv; + struct nv20_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv34_graph_cclass; - nv_engine(priv)->sclass = nv34_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv34_gr_cclass; + nv_engine(priv)->sclass = nv34_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; return 0; } -struct nouveau_oclass -nv34_graph_oclass = { +struct nvkm_oclass +nv34_gr_oclass = { .handle = NV_ENGINE(GR, 0x34), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv34_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv30_graph_init, - .fini = _nouveau_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv34_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv30_gr_init, + .fini = _nvkm_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index 2fb5756d9f66..707625f19ff5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -1,36 +1,31 @@ -#include <core/os.h> -#include <core/engctx.h> -#include <core/enum.h> - -#include <subdev/timer.h> -#include <subdev/fb.h> - #include "nv20.h" #include "regs.h" +#include <engine/fifo.h> + /******************************************************************************* * Graphics object classes ******************************************************************************/ -static struct nouveau_oclass -nv35_graph_sclass[] = { - { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ - { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */ - { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */ - { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */ - { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */ - { 0x0497, &nv04_graph_ofuncs, NULL }, /* rankine */ +static struct nvkm_oclass +nv35_gr_sclass[] = { + { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ + { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ + { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ + { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ + { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ + { 0x0497, &nv04_gr_ofuncs, NULL }, /* rankine */ {}, }; @@ -39,21 +34,20 @@ nv35_graph_sclass[] = { ******************************************************************************/ static int -nv35_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_chan *chan; + struct nv20_gr_chan *chan; int ret, i; - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x577c, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; - chan->chid = nouveau_fifo_chan(parent)->chid; + chan->chid = nvkm_fifo_chan(parent)->chid; nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); nv_wo32(chan, 0x040c, 0x00000101); @@ -110,16 +104,16 @@ nv35_graph_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass -nv35_graph_cclass = { +static struct nvkm_oclass +nv35_gr_cclass = { .handle = NV_ENGCTX(GR, 0x35), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv35_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = nv20_graph_context_init, - .fini = nv20_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv35_gr_context_ctor, + .dtor = _nvkm_gr_context_dtor, + .init = nv20_gr_context_init, + .fini = nv20_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, }; @@ -128,38 +122,38 @@ nv35_graph_cclass = { ******************************************************************************/ static int -nv35_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv20_graph_priv *priv; + struct nv20_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_graph_intr; - nv_engine(priv)->cclass = &nv35_graph_cclass; - nv_engine(priv)->sclass = nv35_graph_sclass; - nv_engine(priv)->tile_prog = nv20_graph_tile_prog; + nv_subdev(priv)->intr = nv20_gr_intr; + nv_engine(priv)->cclass = &nv35_gr_cclass; + nv_engine(priv)->sclass = nv35_gr_sclass; + nv_engine(priv)->tile_prog = nv20_gr_tile_prog; return 0; } -struct nouveau_oclass -nv35_graph_oclass = { +struct nvkm_oclass +nv35_gr_oclass = { .handle = NV_ENGINE(GR, 0x35), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv35_graph_ctor, - .dtor = nv20_graph_dtor, - .init = nv30_graph_init, - .fini = _nouveau_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv35_gr_ctor, + .dtor = nv20_gr_dtor, + .init = nv30_gr_init, + .fini = _nvkm_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 4f401174868d..7e1937980e3f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -21,34 +21,28 @@ * * Authors: Ben Skeggs */ +#include "nv40.h" +#include "regs.h" #include <core/client.h> -#include <core/os.h> #include <core/handle.h> -#include <core/engctx.h> - #include <subdev/fb.h> #include <subdev/timer.h> - -#include <engine/graph.h> #include <engine/fifo.h> -#include "nv40.h" -#include "regs.h" - -struct nv40_graph_priv { - struct nouveau_graph base; +struct nv40_gr_priv { + struct nvkm_gr base; u32 size; }; -struct nv40_graph_chan { - struct nouveau_graph_chan base; +struct nv40_gr_chan { + struct nvkm_gr_chan base; }; static u64 -nv40_graph_units(struct nouveau_graph *graph) +nv40_gr_units(struct nvkm_gr *gr) { - struct nv40_graph_priv *priv = (void *)graph; + struct nv40_gr_priv *priv = (void *)gr; return nv_rd32(priv, 0x1540); } @@ -58,16 +52,15 @@ nv40_graph_units(struct nouveau_graph *graph) ******************************************************************************/ static int -nv40_graph_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_gpuobj *obj; + struct nvkm_gpuobj *obj; int ret; - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, - 20, 16, 0, &obj); + ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, + 20, 16, 0, &obj); *pobject = nv_object(obj); if (ret) return ret; @@ -83,55 +76,55 @@ nv40_graph_object_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs -nv40_graph_ofuncs = { - .ctor = nv40_graph_object_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, +static struct nvkm_ofuncs +nv40_gr_ofuncs = { + .ctor = nv40_gr_object_ctor, + .dtor = _nvkm_gpuobj_dtor, + .init = _nvkm_gpuobj_init, + .fini = _nvkm_gpuobj_fini, + .rd32 = _nvkm_gpuobj_rd32, + .wr32 = _nvkm_gpuobj_wr32, }; -static struct nouveau_oclass -nv40_graph_sclass[] = { - { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */ - { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */ - { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */ - { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */ - { 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */ +static struct nvkm_oclass +nv40_gr_sclass[] = { + { 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv40_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */ + { 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */ + { 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */ + { 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */ + { 0x4097, &nv40_gr_ofuncs, NULL }, /* curie */ {}, }; -static struct nouveau_oclass -nv44_graph_sclass[] = { - { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */ - { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */ - { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */ - { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */ - { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */ - { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */ - { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */ - { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */ - { 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */ +static struct nvkm_oclass +nv44_gr_sclass[] = { + { 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */ + { 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */ + { 0x0030, &nv40_gr_ofuncs, NULL }, /* null */ + { 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */ + { 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */ + { 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */ + { 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */ + { 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */ + { 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */ + { 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */ + { 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */ + { 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */ + { 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */ + { 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */ + { 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */ + { 0x4497, &nv40_gr_ofuncs, NULL }, /* curie */ {}, }; @@ -140,18 +133,16 @@ nv44_graph_sclass[] = { ******************************************************************************/ static int -nv40_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv40_graph_priv *priv = (void *)engine; - struct nv40_graph_chan *chan; + struct nv40_gr_priv *priv = (void *)engine; + struct nv40_gr_chan *chan; int ret; - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, - priv->size, 16, - NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -162,10 +153,10 @@ nv40_graph_context_ctor(struct nouveau_object *parent, } static int -nv40_graph_context_fini(struct nouveau_object *object, bool suspend) +nv40_gr_context_fini(struct nvkm_object *object, bool suspend) { - struct nv40_graph_priv *priv = (void *)object->engine; - struct nv40_graph_chan *chan = (void *)object; + struct nv40_gr_priv *priv = (void *)object->engine; + struct nv40_gr_chan *chan = (void *)object; u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; int ret = 0; @@ -194,16 +185,16 @@ nv40_graph_context_fini(struct nouveau_object *object, bool suspend) return ret; } -static struct nouveau_oclass -nv40_graph_cclass = { +static struct nvkm_oclass +nv40_gr_cclass = { .handle = NV_ENGCTX(GR, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = nv40_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv40_gr_context_ctor, + .dtor = _nvkm_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = nv40_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, }; @@ -212,15 +203,15 @@ nv40_graph_cclass = { ******************************************************************************/ static void -nv40_graph_tile_prog(struct nouveau_engine *engine, int i) +nv40_gr_tile_prog(struct nvkm_engine *engine, int i) { - struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; - struct nouveau_fifo *pfifo = nouveau_fifo(engine); - struct nv40_graph_priv *priv = (void *)engine; + struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; + struct nvkm_fifo *pfifo = nvkm_fifo(engine); + struct nv40_gr_priv *priv = (void *)engine; unsigned long flags; pfifo->pause(pfifo, &flags); - nv04_graph_idle(priv); + nv04_gr_idle(priv); switch (nv_device(priv)->chipset) { case 0x40: @@ -290,13 +281,13 @@ nv40_graph_tile_prog(struct nouveau_engine *engine, int i) } static void -nv40_graph_intr(struct nouveau_subdev *subdev) +nv40_gr_intr(struct nvkm_subdev *subdev) { - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle = NULL; - struct nv40_graph_priv *priv = (void *)subdev; + struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_engine *engine = nv_engine(subdev); + struct nvkm_object *engctx; + struct nvkm_handle *handle = NULL; + struct nv40_gr_priv *priv = (void *)subdev; u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); @@ -309,15 +300,15 @@ nv40_graph_intr(struct nouveau_subdev *subdev) u32 show = stat; int chid; - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); chid = pfifo->chid(pfifo, engctx); if (stat & NV_PGRAPH_INTR_ERROR) { if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { - handle = nouveau_handle_get_class(engctx, class); + handle = nvkm_handle_get_class(engctx, class); if (handle && !nv_call(handle->object, mthd, data)) show &= ~NV_PGRAPH_INTR_ERROR; - nouveau_handle_put(handle); + nvkm_handle_put(handle); } if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) { @@ -330,57 +321,57 @@ nv40_graph_intr(struct nouveau_subdev *subdev) if (show) { nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv10_graph_intr_name, show); + nvkm_bitfield_print(nv10_gr_intr_name, show); pr_cont(" nsource:"); - nouveau_bitfield_print(nv04_graph_nsource, nsource); + nvkm_bitfield_print(nv04_gr_nsource, nsource); pr_cont(" nstatus:"); - nouveau_bitfield_print(nv10_graph_nstatus, nstatus); + nvkm_bitfield_print(nv10_gr_nstatus, nstatus); pr_cont("\n"); nv_error(priv, "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 4, nouveau_client_name(engctx), subc, + chid, inst << 4, nvkm_client_name(engctx), subc, class, mthd, data); } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } static int -nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv40_graph_priv *priv; + struct nv40_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv40_graph_intr; - nv_engine(priv)->cclass = &nv40_graph_cclass; - if (nv44_graph_class(priv)) - nv_engine(priv)->sclass = nv44_graph_sclass; + nv_subdev(priv)->intr = nv40_gr_intr; + nv_engine(priv)->cclass = &nv40_gr_cclass; + if (nv44_gr_class(priv)) + nv_engine(priv)->sclass = nv44_gr_sclass; else - nv_engine(priv)->sclass = nv40_graph_sclass; - nv_engine(priv)->tile_prog = nv40_graph_tile_prog; + nv_engine(priv)->sclass = nv40_gr_sclass; + nv_engine(priv)->tile_prog = nv40_gr_tile_prog; - priv->base.units = nv40_graph_units; + priv->base.units = nv40_gr_units; return 0; } static int -nv40_graph_init(struct nouveau_object *object) +nv40_gr_init(struct nvkm_object *object) { - struct nouveau_engine *engine = nv_engine(object); - struct nouveau_fb *pfb = nouveau_fb(object); - struct nv40_graph_priv *priv = (void *)engine; + struct nvkm_engine *engine = nv_engine(object); + struct nvkm_fb *pfb = nvkm_fb(object); + struct nv40_gr_priv *priv = (void *)engine; int ret, i, j; u32 vramsz; - ret = nouveau_graph_init(&priv->base); + ret = nvkm_gr_init(&priv->base); if (ret) return ret; @@ -524,13 +515,13 @@ nv40_graph_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass -nv40_graph_oclass = { +struct nvkm_oclass +nv40_gr_oclass = { .handle = NV_ENGINE(GR, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_graph_ctor, - .dtor = _nouveau_graph_dtor, - .init = nv40_graph_init, - .fini = _nouveau_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv40_gr_ctor, + .dtor = _nvkm_gr_dtor, + .init = nv40_gr_init, + .fini = _nvkm_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h index ad8209377529..d852bd6de571 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -1,16 +1,17 @@ -#ifndef __NV40_GRAPH_H__ -#define __NV40_GRAPH_H__ +#ifndef __NV40_GR_H__ +#define __NV40_GR_H__ +#include <engine/gr.h> #include <core/device.h> -#include <core/gpuobj.h> +struct nvkm_gpuobj; /* returns 1 if device is one of the nv4x using the 0x4497 object class, * helpful to determine a number of other hardware features */ static inline int -nv44_graph_class(void *priv) +nv44_gr_class(void *priv) { - struct nouveau_device *device = nv_device(priv); + struct nvkm_device *device = nv_device(priv); if ((device->chipset & 0xf0) == 0x60) return 1; @@ -18,7 +19,6 @@ nv44_graph_class(void *priv) return !(0x0baf & (1 << (device->chipset & 0x0f))); } -int nv40_grctx_init(struct nouveau_device *, u32 *size); -void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); - +int nv40_grctx_init(struct nvkm_device *, u32 *size); +void nv40_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *); #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 38e0aa26f1cd..270d7cd63fc7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -21,36 +21,28 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" -#include <core/os.h> #include <core/client.h> +#include <core/device.h> #include <core/handle.h> -#include <core/engctx.h> -#include <core/enum.h> - -#include <subdev/fb.h> -#include <subdev/vm.h> -#include <subdev/timer.h> - #include <engine/fifo.h> -#include <engine/graph.h> - -#include "nv50.h" +#include <subdev/timer.h> -struct nv50_graph_priv { - struct nouveau_graph base; +struct nv50_gr_priv { + struct nvkm_gr base; spinlock_t lock; u32 size; }; -struct nv50_graph_chan { - struct nouveau_graph_chan base; +struct nv50_gr_chan { + struct nvkm_gr_chan base; }; static u64 -nv50_graph_units(struct nouveau_graph *graph) +nv50_gr_units(struct nvkm_gr *gr) { - struct nv50_graph_priv *priv = (void *)graph; + struct nv50_gr_priv *priv = (void *)gr; return nv_rd32(priv, 0x1540); } @@ -60,16 +52,15 @@ nv50_graph_units(struct nouveau_graph *graph) ******************************************************************************/ static int -nv50_graph_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_gpuobj *obj; + struct nvkm_gpuobj *obj; int ret; - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, - 16, 16, 0, &obj); + ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, + 16, 16, 0, &obj); *pobject = nv_object(obj); if (ret) return ret; @@ -81,65 +72,65 @@ nv50_graph_object_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs -nv50_graph_ofuncs = { - .ctor = nv50_graph_object_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, +static struct nvkm_ofuncs +nv50_gr_ofuncs = { + .ctor = nv50_gr_object_ctor, + .dtor = _nvkm_gpuobj_dtor, + .init = _nvkm_gpuobj_init, + .fini = _nvkm_gpuobj_fini, + .rd32 = _nvkm_gpuobj_rd32, + .wr32 = _nvkm_gpuobj_wr32, }; -static struct nouveau_oclass -nv50_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x5097, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, +static struct nvkm_oclass +nv50_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x5097, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, {} }; -static struct nouveau_oclass -nv84_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, - { 0x8297, &nv50_graph_ofuncs }, +static struct nvkm_oclass +g84_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, + { 0x8297, &nv50_gr_ofuncs }, {} }; -static struct nouveau_oclass -nva0_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, - { 0x8397, &nv50_graph_ofuncs }, +static struct nvkm_oclass +gt200_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, + { 0x8397, &nv50_gr_ofuncs }, {} }; -static struct nouveau_oclass -nva3_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, - { 0x8597, &nv50_graph_ofuncs }, - { 0x85c0, &nv50_graph_ofuncs }, +static struct nvkm_oclass +gt215_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, + { 0x8597, &nv50_gr_ofuncs }, + { 0x85c0, &nv50_gr_ofuncs }, {} }; -static struct nouveau_oclass -nvaf_graph_sclass[] = { - { 0x0030, &nv50_graph_ofuncs }, - { 0x502d, &nv50_graph_ofuncs }, - { 0x5039, &nv50_graph_ofuncs }, - { 0x50c0, &nv50_graph_ofuncs }, - { 0x85c0, &nv50_graph_ofuncs }, - { 0x8697, &nv50_graph_ofuncs }, +static struct nvkm_oclass +mcp89_gr_sclass[] = { + { 0x0030, &nv50_gr_ofuncs }, + { 0x502d, &nv50_gr_ofuncs }, + { 0x5039, &nv50_gr_ofuncs }, + { 0x50c0, &nv50_gr_ofuncs }, + { 0x85c0, &nv50_gr_ofuncs }, + { 0x8697, &nv50_gr_ofuncs }, {} }; @@ -148,18 +139,16 @@ nvaf_graph_sclass[] = { ******************************************************************************/ static int -nv50_graph_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv50_graph_priv *priv = (void *)engine; - struct nv50_graph_chan *chan; + struct nv50_gr_priv *priv = (void *)engine; + struct nv50_gr_chan *chan; int ret; - ret = nouveau_graph_context_create(parent, engine, oclass, NULL, - priv->size, 0, - NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, + 0, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -168,16 +157,16 @@ nv50_graph_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass -nv50_graph_cclass = { +static struct nvkm_oclass +nv50_gr_cclass = { .handle = NV_ENGCTX(GR, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_graph_context_ctor, - .dtor = _nouveau_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_gr_context_ctor, + .dtor = _nvkm_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, }, }; @@ -185,7 +174,7 @@ nv50_graph_cclass = { * PGRAPH engine/subdev functions ******************************************************************************/ -static const struct nouveau_bitfield nv50_pgraph_status[] = { +static const struct nvkm_bitfield nv50_pgr_status[] = { { 0x00000001, "BUSY" }, /* set when any bit is set */ { 0x00000002, "DISPATCH" }, { 0x00000004, "UNK2" }, @@ -214,22 +203,23 @@ static const struct nouveau_bitfield nv50_pgraph_status[] = { {} }; -static const char *const nv50_pgraph_vstatus_0[] = { +static const char *const nv50_pgr_vstatus_0[] = { "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP", NULL }; -static const char *const nv50_pgraph_vstatus_1[] = { +static const char *const nv50_pgr_vstatus_1[] = { "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL }; -static const char *const nv50_pgraph_vstatus_2[] = { +static const char *const nv50_pgr_vstatus_2[] = { "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK", "ROP", NULL }; -static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r, - const char *const units[], u32 status) +static void +nvkm_pgr_vstatus_print(struct nv50_gr_priv *priv, int r, + const char *const units[], u32 status) { int i; @@ -246,10 +236,10 @@ static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r, } static int -nv84_graph_tlb_flush(struct nouveau_engine *engine) +g84_gr_tlb_flush(struct nvkm_engine *engine) { - struct nouveau_timer *ptimer = nouveau_timer(engine); - struct nv50_graph_priv *priv = (void *)engine; + struct nvkm_timer *ptimer = nvkm_timer(engine); + struct nv50_gr_priv *priv = (void *)engine; bool idle, timeout = false; unsigned long flags; u64 start; @@ -284,15 +274,15 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine) tmp = nv_rd32(priv, 0x400700); nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp); - nouveau_bitfield_print(nv50_pgraph_status, tmp); + nvkm_bitfield_print(nv50_pgr_status, tmp); pr_cont("\n"); - nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0, - nv_rd32(priv, 0x400380)); - nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1, - nv_rd32(priv, 0x400384)); - nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2, - nv_rd32(priv, 0x400388)); + nvkm_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0, + nv_rd32(priv, 0x400380)); + nvkm_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1, + nv_rd32(priv, 0x400384)); + nvkm_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2, + nv_rd32(priv, 0x400388)); } @@ -304,7 +294,7 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine) return timeout ? -EBUSY : 0; } -static const struct nouveau_bitfield nv50_mp_exec_errors[] = { +static const struct nvkm_bitfield nv50_mp_exec_errors[] = { { 0x01, "STACK_UNDERFLOW" }, { 0x02, "STACK_MISMATCH" }, { 0x04, "QUADON_ACTIVE" }, @@ -315,7 +305,7 @@ static const struct nouveau_bitfield nv50_mp_exec_errors[] = { {} }; -static const struct nouveau_bitfield nv50_mpc_traps[] = { +static const struct nvkm_bitfield nv50_mpc_traps[] = { { 0x0000001, "LOCAL_LIMIT_READ" }, { 0x0000010, "LOCAL_LIMIT_WRITE" }, { 0x0000040, "STACK_LIMIT" }, @@ -329,7 +319,7 @@ static const struct nouveau_bitfield nv50_mpc_traps[] = { {} }; -static const struct nouveau_bitfield nv50_tex_traps[] = { +static const struct nvkm_bitfield nv50_tex_traps[] = { { 0x00000001, "" }, /* any bit set? */ { 0x00000002, "FAULT" }, { 0x00000004, "STORAGE_TYPE_MISMATCH" }, @@ -338,30 +328,30 @@ static const struct nouveau_bitfield nv50_tex_traps[] = { {} }; -static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = { +static const struct nvkm_bitfield nv50_gr_trap_m2mf[] = { { 0x00000001, "NOTIFY" }, { 0x00000002, "IN" }, { 0x00000004, "OUT" }, {} }; -static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = { +static const struct nvkm_bitfield nv50_gr_trap_vfetch[] = { { 0x00000001, "FAULT" }, {} }; -static const struct nouveau_bitfield nv50_graph_trap_strmout[] = { +static const struct nvkm_bitfield nv50_gr_trap_strmout[] = { { 0x00000001, "FAULT" }, {} }; -static const struct nouveau_bitfield nv50_graph_trap_ccache[] = { +static const struct nvkm_bitfield nv50_gr_trap_ccache[] = { { 0x00000001, "FAULT" }, {} }; /* There must be a *lot* of these. Will take some time to gather them up. */ -const struct nouveau_enum nv50_data_error_names[] = { +const struct nvkm_enum nv50_data_error_names[] = { { 0x00000003, "INVALID_OPERATION", NULL }, { 0x00000004, "INVALID_VALUE", NULL }, { 0x00000005, "INVALID_ENUM", NULL }, @@ -407,7 +397,7 @@ const struct nouveau_enum nv50_data_error_names[] = { {} }; -static const struct nouveau_bitfield nv50_graph_intr_name[] = { +static const struct nvkm_bitfield nv50_gr_intr_name[] = { { 0x00000001, "NOTIFY" }, { 0x00000002, "COMPUTE_QUERY" }, { 0x00000010, "ILLEGAL_MTHD" }, @@ -421,7 +411,7 @@ static const struct nouveau_bitfield nv50_graph_intr_name[] = { {} }; -static const struct nouveau_bitfield nv50_graph_trap_prop[] = { +static const struct nvkm_bitfield nv50_gr_trap_prop[] = { { 0x00000004, "SURF_WIDTH_OVERRUN" }, { 0x00000008, "SURF_HEIGHT_OVERRUN" }, { 0x00000010, "DST2D_FAULT" }, @@ -437,7 +427,7 @@ static const struct nouveau_bitfield nv50_graph_trap_prop[] = { }; static void -nv50_priv_prop_trap(struct nv50_graph_priv *priv, +nv50_priv_prop_trap(struct nv50_gr_priv *priv, u32 ustatus_addr, u32 ustatus, u32 tp) { u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); @@ -468,7 +458,7 @@ nv50_priv_prop_trap(struct nv50_graph_priv *priv, } if (ustatus) { nv_error(priv, "TRAP_PROP - TP %d -", tp); - nouveau_bitfield_print(nv50_graph_trap_prop, ustatus); + nvkm_bitfield_print(nv50_gr_trap_prop, ustatus); pr_cont(" - Address %02x%08x\n", e14, e10); } nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", @@ -476,7 +466,7 @@ nv50_priv_prop_trap(struct nv50_graph_priv *priv, } static void -nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) +nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display) { u32 units = nv_rd32(priv, 0x1540); u32 addr, mp10, status, pc, oplow, ophigh; @@ -500,7 +490,7 @@ nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) ophigh = nv_rd32(priv, addr + 0x74); nv_error(priv, "TRAP_MP_EXEC - " "TP %d MP %d:", tpid, i); - nouveau_bitfield_print(nv50_mp_exec_errors, status); + nvkm_bitfield_print(nv50_mp_exec_errors, status); pr_cont(" at %06x warp %d, opcode %08x %08x\n", pc&0xffffff, pc >> 24, oplow, ophigh); @@ -515,8 +505,8 @@ nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) } static void -nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, - u32 ustatus_new, int display, const char *name) +nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old, + u32 ustatus_new, int display, const char *name) { int tps = 0; u32 units = nv_rd32(priv, 0x1540); @@ -542,7 +532,7 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, nv_rd32(priv, r)); if (ustatus) { nv_error(priv, "%s - TP%d:", name, i); - nouveau_bitfield_print(nv50_tex_traps, + nvkm_bitfield_print(nv50_tex_traps, ustatus); pr_cont("\n"); ustatus = 0; @@ -556,7 +546,7 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, } if (ustatus && display) { nv_error(priv, "%s - TP%d:", name, i); - nouveau_bitfield_print(nv50_mpc_traps, ustatus); + nvkm_bitfield_print(nv50_mpc_traps, ustatus); pr_cont("\n"); ustatus = 0; } @@ -580,8 +570,8 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, } static int -nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, - int chid, u64 inst, struct nouveau_object *engctx) +nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display, + int chid, u64 inst, struct nvkm_object *engctx) { u32 status = nv_rd32(priv, 0x400108); u32 ustatus; @@ -617,7 +607,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, nv_error(priv, "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n", chid, inst, - nouveau_client_name(engctx), subc, + nvkm_client_name(engctx), subc, class, mthd, datah, datal, addr, r848); } else if (display) { @@ -642,7 +632,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, nv_error(priv, "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n", chid, inst, - nouveau_client_name(engctx), subc, + nvkm_client_name(engctx), subc, class, mthd, data, addr); } else if (display) { @@ -670,7 +660,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff; if (display) { nv_error(priv, "TRAP_M2MF"); - nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus); + nvkm_bitfield_print(nv50_gr_trap_m2mf, ustatus); pr_cont("\n"); nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n", nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808), @@ -691,7 +681,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff; if (display) { nv_error(priv, "TRAP_VFETCH"); - nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus); + nvkm_bitfield_print(nv50_gr_trap_vfetch, ustatus); pr_cont("\n"); nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n", nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08), @@ -708,7 +698,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff; if (display) { nv_error(priv, "TRAP_STRMOUT"); - nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus); + nvkm_bitfield_print(nv50_gr_trap_strmout, ustatus); pr_cont("\n"); nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n", nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808), @@ -729,7 +719,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff; if (display) { nv_error(priv, "TRAP_CCACHE"); - nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus); + nvkm_bitfield_print(nv50_gr_trap_ccache, ustatus); pr_cont("\n"); nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x" " %08x %08x %08x\n", @@ -791,13 +781,13 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, } static void -nv50_graph_intr(struct nouveau_subdev *subdev) +nv50_gr_intr(struct nvkm_subdev *subdev) { - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle = NULL; - struct nv50_graph_priv *priv = (void *)subdev; + struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_engine *engine = nv_engine(subdev); + struct nvkm_object *engctx; + struct nvkm_handle *handle = NULL; + struct nv50_gr_priv *priv = (void *)subdev; u32 stat = nv_rd32(priv, 0x400100); u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff; u32 addr = nv_rd32(priv, 0x400704); @@ -808,27 +798,27 @@ nv50_graph_intr(struct nouveau_subdev *subdev) u32 show = stat, show_bitfield = stat; int chid; - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); chid = pfifo->chid(pfifo, engctx); if (stat & 0x00000010) { - handle = nouveau_handle_get_class(engctx, class); + handle = nvkm_handle_get_class(engctx, class); if (handle && !nv_call(handle->object, mthd, data)) show &= ~0x00000010; - nouveau_handle_put(handle); + nvkm_handle_put(handle); } if (show & 0x00100000) { u32 ecode = nv_rd32(priv, 0x400110); nv_error(priv, "DATA_ERROR "); - nouveau_enum_print(nv50_data_error_names, ecode); + nvkm_enum_print(nv50_data_error_names, ecode); pr_cont("\n"); show_bitfield &= ~0x00100000; } if (stat & 0x00200000) { - if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, - engctx)) + if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12, + engctx)) show &= ~0x00200000; show_bitfield &= ~0x00200000; } @@ -840,43 +830,43 @@ nv50_graph_intr(struct nouveau_subdev *subdev) show &= show_bitfield; if (show) { nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv50_graph_intr_name, show); + nvkm_bitfield_print(nv50_gr_intr_name, show); pr_cont("\n"); } nv_error(priv, "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, (u64)inst << 12, nouveau_client_name(engctx), + chid, (u64)inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); } if (nv_rd32(priv, 0x400824) & (1 << 31)) nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31)); - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } static int -nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv50_graph_priv *priv; + struct nv50_gr_priv *priv; int ret; - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00201000; - nv_subdev(priv)->intr = nv50_graph_intr; - nv_engine(priv)->cclass = &nv50_graph_cclass; + nv_subdev(priv)->intr = nv50_gr_intr; + nv_engine(priv)->cclass = &nv50_gr_cclass; - priv->base.units = nv50_graph_units; + priv->base.units = nv50_gr_units; switch (nv_device(priv)->chipset) { case 0x50: - nv_engine(priv)->sclass = nv50_graph_sclass; + nv_engine(priv)->sclass = nv50_gr_sclass; break; case 0x84: case 0x86: @@ -884,20 +874,20 @@ nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, case 0x94: case 0x96: case 0x98: - nv_engine(priv)->sclass = nv84_graph_sclass; + nv_engine(priv)->sclass = g84_gr_sclass; break; case 0xa0: case 0xaa: case 0xac: - nv_engine(priv)->sclass = nva0_graph_sclass; + nv_engine(priv)->sclass = gt200_gr_sclass; break; case 0xa3: case 0xa5: case 0xa8: - nv_engine(priv)->sclass = nva3_graph_sclass; + nv_engine(priv)->sclass = gt215_gr_sclass; break; case 0xaf: - nv_engine(priv)->sclass = nvaf_graph_sclass; + nv_engine(priv)->sclass = mcp89_gr_sclass; break; } @@ -905,19 +895,19 @@ nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, /* unfortunate hw bug workaround... */ if (nv_device(priv)->chipset != 0x50 && nv_device(priv)->chipset != 0xac) - nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush; + nv_engine(priv)->tlb_flush = g84_gr_tlb_flush; spin_lock_init(&priv->lock); return 0; } static int -nv50_graph_init(struct nouveau_object *object) +nv50_gr_init(struct nvkm_object *object) { - struct nv50_graph_priv *priv = (void *)object; + struct nv50_gr_priv *priv = (void *)object; int ret, units, i; - ret = nouveau_graph_init(&priv->base); + ret = nvkm_gr_init(&priv->base); if (ret) return ret; @@ -997,13 +987,13 @@ nv50_graph_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass -nv50_graph_oclass = { +struct nvkm_oclass +nv50_gr_oclass = { .handle = NV_ENGINE(GR, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_graph_ctor, - .dtor = _nouveau_graph_dtor, - .init = nv50_graph_init, - .fini = _nouveau_graph_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_gr_ctor, + .dtor = _nvkm_gr_dtor, + .init = nv50_gr_init, + .fini = _nvkm_gr_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h new file mode 100644 index 000000000000..bcf786f6b731 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h @@ -0,0 +1,9 @@ +#ifndef __NV50_GR_H__ +#define __NV50_GR_H__ +#include <engine/gr.h> +struct nvkm_device; +struct nvkm_gpuobj; + +int nv50_grctx_init(struct nvkm_device *, u32 *size); +void nv50_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/regs.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h index fde8e24415e4..90a9873ce522 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/regs.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h @@ -1,5 +1,5 @@ -#ifndef __NOUVEAU_GRAPH_REGS_H__ -#define __NOUVEAU_GRAPH_REGS_H__ +#ifndef __NVKM_GR_REGS_H__ +#define __NVKM_GR_REGS_H__ #define NV04_PGRAPH_DEBUG_0 0x00400080 #define NV04_PGRAPH_DEBUG_1 0x00400084 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild new file mode 100644 index 000000000000..61b7b5f98f3c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild @@ -0,0 +1,5 @@ +nvkm-y += nvkm/engine/mpeg/nv31.o +nvkm-y += nvkm/engine/mpeg/nv40.o +nvkm-y += nvkm/engine/mpeg/nv44.o +nvkm-y += nvkm/engine/mpeg/nv50.o +nvkm-y += nvkm/engine/mpeg/g84.o diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c index e9cc8b116a24..0df889fa2611 100644 --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c @@ -21,30 +21,22 @@ * * Authors: Ben Skeggs */ - -#include <core/os.h> -#include <core/engctx.h> - -#include <subdev/vm.h> -#include <subdev/bar.h> -#include <subdev/timer.h> - #include <engine/mpeg.h> -struct nv84_mpeg_priv { - struct nouveau_mpeg base; +struct g84_mpeg_priv { + struct nvkm_mpeg base; }; -struct nv84_mpeg_chan { - struct nouveau_mpeg_chan base; +struct g84_mpeg_chan { + struct nvkm_mpeg_chan base; }; /******************************************************************************* * MPEG object classes ******************************************************************************/ -static struct nouveau_oclass -nv84_mpeg_sclass[] = { +static struct nvkm_oclass +g84_mpeg_sclass[] = { { 0x8274, &nv50_mpeg_ofuncs }, {} }; @@ -53,16 +45,16 @@ nv84_mpeg_sclass[] = { * PMPEG context ******************************************************************************/ -static struct nouveau_oclass -nv84_mpeg_cclass = { +static struct nvkm_oclass +g84_mpeg_cclass = { .handle = NV_ENGCTX(MPEG, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_mpeg_context_ctor, - .dtor = _nouveau_mpeg_context_dtor, - .init = _nouveau_mpeg_context_init, - .fini = _nouveau_mpeg_context_fini, - .rd32 = _nouveau_mpeg_context_rd32, - .wr32 = _nouveau_mpeg_context_wr32, + .dtor = _nvkm_mpeg_context_dtor, + .init = _nvkm_mpeg_context_init, + .fini = _nvkm_mpeg_context_fini, + .rd32 = _nvkm_mpeg_context_rd32, + .wr32 = _nvkm_mpeg_context_wr32, }, }; @@ -71,32 +63,32 @@ nv84_mpeg_cclass = { ******************************************************************************/ static int -nv84_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv84_mpeg_priv *priv; + struct g84_mpeg_priv *priv; int ret; - ret = nouveau_mpeg_create(parent, engine, oclass, &priv); + ret = nvkm_mpeg_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00000002; nv_subdev(priv)->intr = nv50_mpeg_intr; - nv_engine(priv)->cclass = &nv84_mpeg_cclass; - nv_engine(priv)->sclass = nv84_mpeg_sclass; + nv_engine(priv)->cclass = &g84_mpeg_cclass; + nv_engine(priv)->sclass = g84_mpeg_sclass; return 0; } -struct nouveau_oclass -nv84_mpeg_oclass = { +struct nvkm_oclass +g84_mpeg_oclass = { .handle = NV_ENGINE(MPEG, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_mpeg_ctor, - .dtor = _nouveau_mpeg_dtor, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_mpeg_ctor, + .dtor = _nvkm_mpeg_dtor, .init = nv50_mpeg_init, - .fini = _nouveau_mpeg_fini, + .fini = _nvkm_mpeg_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index d88c700b2f69..b5bef0718359 100644 --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -21,35 +21,30 @@ * * Authors: Ben Skeggs */ +#include "nv31.h" #include <core/client.h> -#include <core/os.h> -#include <core/engctx.h> #include <core/handle.h> - +#include <engine/fifo.h> +#include <subdev/instmem.h> #include <subdev/fb.h> #include <subdev/timer.h> -#include <subdev/instmem.h> - -#include <engine/fifo.h> -#include <engine/mpeg.h> -#include <engine/mpeg/nv31.h> /******************************************************************************* * MPEG object classes ******************************************************************************/ static int -nv31_mpeg_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv31_mpeg_object_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_gpuobj *obj; + struct nvkm_gpuobj *obj; int ret; - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, - 20, 16, 0, &obj); + ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, + 20, 16, 0, &obj); *pobject = nv_object(obj); if (ret) return ret; @@ -62,9 +57,9 @@ nv31_mpeg_object_ctor(struct nouveau_object *parent, } static int -nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len) +nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len) { - struct nouveau_instmem *imem = nouveau_instmem(object); + struct nvkm_instmem *imem = nvkm_instmem(object); struct nv31_mpeg_priv *priv = (void *)object->engine; u32 inst = *(u32 *)arg << 4; u32 dma0 = nv_ro32(imem, inst + 0); @@ -100,17 +95,17 @@ nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len) return 0; } -struct nouveau_ofuncs +struct nvkm_ofuncs nv31_mpeg_ofuncs = { .ctor = nv31_mpeg_object_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, + .dtor = _nvkm_gpuobj_dtor, + .init = _nvkm_gpuobj_init, + .fini = _nvkm_gpuobj_fini, + .rd32 = _nvkm_gpuobj_rd32, + .wr32 = _nvkm_gpuobj_wr32, }; -static struct nouveau_omthds +static struct nvkm_omthds nv31_mpeg_omthds[] = { { 0x0190, 0x0190, nv31_mpeg_mthd_dma }, { 0x01a0, 0x01a0, nv31_mpeg_mthd_dma }, @@ -118,7 +113,7 @@ nv31_mpeg_omthds[] = { {} }; -struct nouveau_oclass +struct nvkm_oclass nv31_mpeg_sclass[] = { { 0x3174, &nv31_mpeg_ofuncs, nv31_mpeg_omthds }, {} @@ -129,17 +124,17 @@ nv31_mpeg_sclass[] = { ******************************************************************************/ static int -nv31_mpeg_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv31_mpeg_context_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv31_mpeg_priv *priv = (void *)engine; struct nv31_mpeg_chan *chan; unsigned long flags; int ret; - ret = nouveau_object_create(parent, engine, oclass, 0, &chan); + ret = nvkm_object_create(parent, engine, oclass, 0, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -147,7 +142,7 @@ nv31_mpeg_context_ctor(struct nouveau_object *parent, spin_lock_irqsave(&nv_engine(priv)->lock, flags); if (priv->chan) { spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); - nouveau_object_destroy(&chan->base); + nvkm_object_destroy(&chan->base); *pobject = NULL; return -EBUSY; } @@ -157,7 +152,7 @@ nv31_mpeg_context_ctor(struct nouveau_object *parent, } static void -nv31_mpeg_context_dtor(struct nouveau_object *object) +nv31_mpeg_context_dtor(struct nvkm_object *object) { struct nv31_mpeg_priv *priv = (void *)object->engine; struct nv31_mpeg_chan *chan = (void *)object; @@ -166,17 +161,17 @@ nv31_mpeg_context_dtor(struct nouveau_object *object) spin_lock_irqsave(&nv_engine(priv)->lock, flags); priv->chan = NULL; spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); - nouveau_object_destroy(&chan->base); + nvkm_object_destroy(&chan->base); } -struct nouveau_oclass +struct nvkm_oclass nv31_mpeg_cclass = { .handle = NV_ENGCTX(MPEG, 0x31), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv31_mpeg_context_ctor, .dtor = nv31_mpeg_context_dtor, - .init = nouveau_object_init, - .fini = nouveau_object_fini, + .init = nvkm_object_init, + .fini = nvkm_object_fini, }, }; @@ -185,9 +180,9 @@ nv31_mpeg_cclass = { ******************************************************************************/ void -nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i) +nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i) { - struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; + struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; struct nv31_mpeg_priv *priv = (void *)engine; nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch); @@ -196,12 +191,12 @@ nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i) } void -nv31_mpeg_intr(struct nouveau_subdev *subdev) +nv31_mpeg_intr(struct nvkm_subdev *subdev) { struct nv31_mpeg_priv *priv = (void *)subdev; - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_handle *handle; - struct nouveau_object *engctx; + struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_handle *handle; + struct nvkm_object *engctx; u32 stat = nv_rd32(priv, 0x00b100); u32 type = nv_rd32(priv, 0x00b230); u32 mthd = nv_rd32(priv, 0x00b234); @@ -220,10 +215,10 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev) } if (type == 0x00000010 && engctx) { - handle = nouveau_handle_get_class(engctx, 0x3174); + handle = nvkm_handle_get_class(engctx, 0x3174); if (handle && !nv_call(handle->object, mthd, data)) show &= ~0x01000000; - nouveau_handle_put(handle); + nvkm_handle_put(handle); } } @@ -233,21 +228,21 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev) if (show) { nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n", pfifo->chid(pfifo, engctx), - nouveau_client_name(engctx), stat, type, mthd, data); + nvkm_client_name(engctx), stat, type, mthd, data); } spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); } static int -nv31_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv31_mpeg_priv *priv; int ret; - ret = nouveau_mpeg_create(parent, engine, oclass, &priv); + ret = nvkm_mpeg_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -261,14 +256,14 @@ nv31_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } int -nv31_mpeg_init(struct nouveau_object *object) +nv31_mpeg_init(struct nvkm_object *object) { - struct nouveau_engine *engine = nv_engine(object); + struct nvkm_engine *engine = nv_engine(object); struct nv31_mpeg_priv *priv = (void *)object; - struct nouveau_fb *pfb = nouveau_fb(object); + struct nvkm_fb *pfb = nvkm_fb(object); int ret, i; - ret = nouveau_mpeg_init(&priv->base); + ret = nvkm_mpeg_init(&priv->base); if (ret) return ret; @@ -297,13 +292,13 @@ nv31_mpeg_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass +struct nvkm_oclass nv31_mpeg_oclass = { .handle = NV_ENGINE(MPEG, 0x31), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv31_mpeg_ctor, - .dtor = _nouveau_mpeg_dtor, + .dtor = _nvkm_mpeg_dtor, .init = nv31_mpeg_init, - .fini = _nouveau_mpeg_fini, + .fini = _nvkm_mpeg_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h index d08629d0b6ad..782b796d7458 100644 --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h @@ -1,15 +1,13 @@ #ifndef __NV31_MPEG_H__ #define __NV31_MPEG_H__ - #include <engine/mpeg.h> struct nv31_mpeg_chan { - struct nouveau_object base; + struct nvkm_object base; }; struct nv31_mpeg_priv { - struct nouveau_mpeg base; + struct nvkm_mpeg base; struct nv31_mpeg_chan *chan; }; - #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c index bdb2f20ff7b1..9508bf9e140f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c @@ -21,25 +21,18 @@ * * Authors: Ben Skeggs */ +#include "nv31.h" -#include <core/os.h> -#include <core/engctx.h> - -#include <subdev/fb.h> -#include <subdev/timer.h> #include <subdev/instmem.h> -#include <engine/mpeg.h> -#include <engine/mpeg/nv31.h> - /******************************************************************************* * MPEG object classes ******************************************************************************/ static int -nv40_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len) +nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len) { - struct nouveau_instmem *imem = nouveau_instmem(object); + struct nvkm_instmem *imem = nvkm_instmem(object); struct nv31_mpeg_priv *priv = (void *)object->engine; u32 inst = *(u32 *)arg << 4; u32 dma0 = nv_ro32(imem, inst + 0); @@ -75,7 +68,7 @@ nv40_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len) return 0; } -static struct nouveau_omthds +static struct nvkm_omthds nv40_mpeg_omthds[] = { { 0x0190, 0x0190, nv40_mpeg_mthd_dma }, { 0x01a0, 0x01a0, nv40_mpeg_mthd_dma }, @@ -83,7 +76,7 @@ nv40_mpeg_omthds[] = { {} }; -struct nouveau_oclass +struct nvkm_oclass nv40_mpeg_sclass[] = { { 0x3174, &nv31_mpeg_ofuncs, nv40_mpeg_omthds }, {} @@ -94,7 +87,7 @@ nv40_mpeg_sclass[] = { ******************************************************************************/ static void -nv40_mpeg_intr(struct nouveau_subdev *subdev) +nv40_mpeg_intr(struct nvkm_subdev *subdev) { struct nv31_mpeg_priv *priv = (void *)subdev; u32 stat; @@ -109,14 +102,14 @@ nv40_mpeg_intr(struct nouveau_subdev *subdev) } static int -nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv31_mpeg_priv *priv; int ret; - ret = nouveau_mpeg_create(parent, engine, oclass, &priv); + ret = nvkm_mpeg_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -129,13 +122,13 @@ nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv40_mpeg_oclass = { .handle = NV_ENGINE(MPEG, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_mpeg_ctor, - .dtor = _nouveau_mpeg_dtor, + .dtor = _nvkm_mpeg_dtor, .init = nv31_mpeg_init, - .fini = _nouveau_mpeg_fini, + .fini = _nvkm_mpeg_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c index 72c7f33fd29b..4720ac884468 100644 --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c @@ -21,25 +21,18 @@ * * Authors: Ben Skeggs */ +#include <engine/mpeg.h> -#include <core/os.h> #include <core/client.h> -#include <core/engctx.h> #include <core/handle.h> - -#include <subdev/fb.h> -#include <subdev/timer.h> -#include <subdev/instmem.h> - #include <engine/fifo.h> -#include <engine/mpeg.h> struct nv44_mpeg_priv { - struct nouveau_mpeg base; + struct nvkm_mpeg base; }; struct nv44_mpeg_chan { - struct nouveau_mpeg_chan base; + struct nvkm_mpeg_chan base; }; /******************************************************************************* @@ -47,17 +40,16 @@ struct nv44_mpeg_chan { ******************************************************************************/ static int -nv44_mpeg_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv44_mpeg_context_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv44_mpeg_chan *chan; int ret; - ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL, - 264 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 264 * 4, + 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -67,7 +59,7 @@ nv44_mpeg_context_ctor(struct nouveau_object *parent, } static int -nv44_mpeg_context_fini(struct nouveau_object *object, bool suspend) +nv44_mpeg_context_fini(struct nvkm_object *object, bool suspend) { struct nv44_mpeg_priv *priv = (void *)object->engine; @@ -81,16 +73,16 @@ nv44_mpeg_context_fini(struct nouveau_object *object, bool suspend) return 0; } -static struct nouveau_oclass +static struct nvkm_oclass nv44_mpeg_cclass = { .handle = NV_ENGCTX(MPEG, 0x44), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv44_mpeg_context_ctor, - .dtor = _nouveau_mpeg_context_dtor, - .init = _nouveau_mpeg_context_init, + .dtor = _nvkm_mpeg_context_dtor, + .init = _nvkm_mpeg_context_init, .fini = nv44_mpeg_context_fini, - .rd32 = _nouveau_mpeg_context_rd32, - .wr32 = _nouveau_mpeg_context_wr32, + .rd32 = _nvkm_mpeg_context_rd32, + .wr32 = _nvkm_mpeg_context_wr32, }, }; @@ -99,12 +91,12 @@ nv44_mpeg_cclass = { ******************************************************************************/ static void -nv44_mpeg_intr(struct nouveau_subdev *subdev) +nv44_mpeg_intr(struct nvkm_subdev *subdev) { - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle; + struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_engine *engine = nv_engine(subdev); + struct nvkm_object *engctx; + struct nvkm_handle *handle; struct nv44_mpeg_priv *priv = (void *)subdev; u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff; u32 stat = nv_rd32(priv, 0x00b100); @@ -114,7 +106,7 @@ nv44_mpeg_intr(struct nouveau_subdev *subdev) u32 show = stat; int chid; - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); chid = pfifo->chid(pfifo, engctx); if (stat & 0x01000000) { @@ -125,10 +117,10 @@ nv44_mpeg_intr(struct nouveau_subdev *subdev) } if (type == 0x00000010) { - handle = nouveau_handle_get_class(engctx, 0x3174); + handle = nvkm_handle_get_class(engctx, 0x3174); if (handle && !nv_call(handle->object, mthd, data)) show &= ~0x01000000; - nouveau_handle_put(handle); + nvkm_handle_put(handle); } } @@ -138,15 +130,15 @@ nv44_mpeg_intr(struct nouveau_subdev *subdev) if (show) { nv_error(priv, "ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n", - chid, inst << 4, nouveau_client_name(engctx), stat, + chid, inst << 4, nvkm_client_name(engctx), stat, type, mthd, data); } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } static void -nv44_mpeg_me_intr(struct nouveau_subdev *subdev) +nv44_mpeg_me_intr(struct nvkm_subdev *subdev) { struct nv44_mpeg_priv *priv = (void *)subdev; u32 stat; @@ -161,14 +153,14 @@ nv44_mpeg_me_intr(struct nouveau_subdev *subdev) } static int -nv44_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv44_mpeg_priv *priv; int ret; - ret = nouveau_mpeg_create(parent, engine, oclass, &priv); + ret = nvkm_mpeg_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -181,13 +173,13 @@ nv44_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv44_mpeg_oclass = { .handle = NV_ENGINE(MPEG, 0x44), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv44_mpeg_ctor, - .dtor = _nouveau_mpeg_dtor, + .dtor = _nvkm_mpeg_dtor, .init = nv31_mpeg_init, - .fini = _nouveau_mpeg_fini, + .fini = _nvkm_mpeg_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c index cae33f86b11a..b3463f3739ce 100644 --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c @@ -21,22 +21,17 @@ * * Authors: Ben Skeggs */ +#include <engine/mpeg.h> -#include <core/os.h> -#include <core/engctx.h> - -#include <subdev/vm.h> #include <subdev/bar.h> #include <subdev/timer.h> -#include <engine/mpeg.h> - struct nv50_mpeg_priv { - struct nouveau_mpeg base; + struct nvkm_mpeg base; }; struct nv50_mpeg_chan { - struct nouveau_mpeg_chan base; + struct nvkm_mpeg_chan base; }; /******************************************************************************* @@ -44,16 +39,16 @@ struct nv50_mpeg_chan { ******************************************************************************/ static int -nv50_mpeg_object_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_mpeg_object_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_gpuobj *obj; + struct nvkm_gpuobj *obj; int ret; - ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, - 16, 16, 0, &obj); + ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, + 16, 16, 0, &obj); *pobject = nv_object(obj); if (ret) return ret; @@ -65,17 +60,17 @@ nv50_mpeg_object_ctor(struct nouveau_object *parent, return 0; } -struct nouveau_ofuncs +struct nvkm_ofuncs nv50_mpeg_ofuncs = { .ctor = nv50_mpeg_object_ctor, - .dtor = _nouveau_gpuobj_dtor, - .init = _nouveau_gpuobj_init, - .fini = _nouveau_gpuobj_fini, - .rd32 = _nouveau_gpuobj_rd32, - .wr32 = _nouveau_gpuobj_wr32, + .dtor = _nvkm_gpuobj_dtor, + .init = _nvkm_gpuobj_init, + .fini = _nvkm_gpuobj_fini, + .rd32 = _nvkm_gpuobj_rd32, + .wr32 = _nvkm_gpuobj_wr32, }; -static struct nouveau_oclass +static struct nvkm_oclass nv50_mpeg_sclass[] = { { 0x3174, &nv50_mpeg_ofuncs }, {} @@ -86,17 +81,17 @@ nv50_mpeg_sclass[] = { ******************************************************************************/ int -nv50_mpeg_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_mpeg_context_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_bar *bar = nouveau_bar(parent); + struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_mpeg_chan *chan; int ret; - ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4, - 0, NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4, + 0, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -107,16 +102,16 @@ nv50_mpeg_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass +static struct nvkm_oclass nv50_mpeg_cclass = { .handle = NV_ENGCTX(MPEG, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_mpeg_context_ctor, - .dtor = _nouveau_mpeg_context_dtor, - .init = _nouveau_mpeg_context_init, - .fini = _nouveau_mpeg_context_fini, - .rd32 = _nouveau_mpeg_context_rd32, - .wr32 = _nouveau_mpeg_context_wr32, + .dtor = _nvkm_mpeg_context_dtor, + .init = _nvkm_mpeg_context_init, + .fini = _nvkm_mpeg_context_fini, + .rd32 = _nvkm_mpeg_context_rd32, + .wr32 = _nvkm_mpeg_context_wr32, }, }; @@ -125,7 +120,7 @@ nv50_mpeg_cclass = { ******************************************************************************/ void -nv50_mpeg_intr(struct nouveau_subdev *subdev) +nv50_mpeg_intr(struct nvkm_subdev *subdev) { struct nv50_mpeg_priv *priv = (void *)subdev; u32 stat = nv_rd32(priv, 0x00b100); @@ -152,7 +147,7 @@ nv50_mpeg_intr(struct nouveau_subdev *subdev) } static void -nv50_vpe_intr(struct nouveau_subdev *subdev) +nv50_vpe_intr(struct nvkm_subdev *subdev) { struct nv50_mpeg_priv *priv = (void *)subdev; @@ -167,14 +162,14 @@ nv50_vpe_intr(struct nouveau_subdev *subdev) } static int -nv50_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_mpeg_priv *priv; int ret; - ret = nouveau_mpeg_create(parent, engine, oclass, &priv); + ret = nvkm_mpeg_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -187,12 +182,12 @@ nv50_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } int -nv50_mpeg_init(struct nouveau_object *object) +nv50_mpeg_init(struct nvkm_object *object) { struct nv50_mpeg_priv *priv = (void *)object; int ret; - ret = nouveau_mpeg_init(&priv->base); + ret = nvkm_mpeg_init(&priv->base); if (ret) return ret; @@ -218,13 +213,13 @@ nv50_mpeg_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass +struct nvkm_oclass nv50_mpeg_oclass = { .handle = NV_ENGINE(MPEG, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_mpeg_ctor, - .dtor = _nouveau_mpeg_dtor, + .dtor = _nvkm_mpeg_dtor, .init = nv50_mpeg_init, - .fini = _nouveau_mpeg_fini, + .fini = _nvkm_mpeg_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild new file mode 100644 index 000000000000..c59c83a67315 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild @@ -0,0 +1,3 @@ +nvkm-y += nvkm/engine/mspdec/g98.o +nvkm-y += nvkm/engine/mspdec/gf100.o +nvkm-y += nvkm/engine/mspdec/gk104.o diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c index fc9ae0ff1ef5..2174577793a4 100644 --- a/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c @@ -21,53 +21,52 @@ * * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin */ - +#include <engine/mspdec.h> #include <engine/falcon.h> -#include <engine/vp.h> -struct nv98_vp_priv { - struct nouveau_falcon base; +struct g98_mspdec_priv { + struct nvkm_falcon base; }; /******************************************************************************* - * VP object classes + * MSPDEC object classes ******************************************************************************/ -static struct nouveau_oclass -nv98_vp_sclass[] = { - { 0x88b2, &nouveau_object_ofuncs }, - { 0x85b2, &nouveau_object_ofuncs }, +static struct nvkm_oclass +g98_mspdec_sclass[] = { + { 0x88b2, &nvkm_object_ofuncs }, + { 0x85b2, &nvkm_object_ofuncs }, {}, }; /******************************************************************************* - * PVP context + * PMSPDEC context ******************************************************************************/ -static struct nouveau_oclass -nv98_vp_cclass = { - .handle = NV_ENGCTX(VP, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +g98_mspdec_cclass = { + .handle = NV_ENGCTX(MSPDEC, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PVP engine/subdev functions + * PMSPDEC engine/subdev functions ******************************************************************************/ static int -nv98_vp_init(struct nouveau_object *object) +g98_mspdec_init(struct nvkm_object *object) { - struct nv98_vp_priv *priv = (void *)object; + struct g98_mspdec_priv *priv = (void *)object; int ret; - ret = nouveau_falcon_init(&priv->base); + ret = nvkm_falcon_init(&priv->base); if (ret) return ret; @@ -77,34 +76,34 @@ nv98_vp_init(struct nouveau_object *object) } static int -nv98_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g98_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv98_vp_priv *priv; + struct g98_mspdec_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true, - "PVP", "vp", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, + "PMSPDEC", "mspdec", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x01020000; - nv_engine(priv)->cclass = &nv98_vp_cclass; - nv_engine(priv)->sclass = nv98_vp_sclass; + nv_engine(priv)->cclass = &g98_mspdec_cclass; + nv_engine(priv)->sclass = g98_mspdec_sclass; return 0; } -struct nouveau_oclass -nv98_vp_oclass = { - .handle = NV_ENGINE(VP, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv98_vp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nv98_vp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +g98_mspdec_oclass = { + .handle = NV_ENGINE(MSPDEC, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g98_mspdec_ctor, + .dtor = _nvkm_falcon_dtor, + .init = g98_mspdec_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c index ac1f62aace72..c814a5f65eb0 100644 --- a/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c @@ -21,52 +21,51 @@ * * Authors: Maarten Lankhorst */ - +#include <engine/mspdec.h> #include <engine/falcon.h> -#include <engine/vp.h> -struct nvc0_vp_priv { - struct nouveau_falcon base; +struct gf100_mspdec_priv { + struct nvkm_falcon base; }; /******************************************************************************* - * VP object classes + * MSPDEC object classes ******************************************************************************/ -static struct nouveau_oclass -nvc0_vp_sclass[] = { - { 0x90b2, &nouveau_object_ofuncs }, +static struct nvkm_oclass +gf100_mspdec_sclass[] = { + { 0x90b2, &nvkm_object_ofuncs }, {}, }; /******************************************************************************* - * PVP context + * PMSPDEC context ******************************************************************************/ -static struct nouveau_oclass -nvc0_vp_cclass = { - .handle = NV_ENGCTX(VP, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +gf100_mspdec_cclass = { + .handle = NV_ENGCTX(MSPDEC, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PVP engine/subdev functions + * PMSPDEC engine/subdev functions ******************************************************************************/ static int -nvc0_vp_init(struct nouveau_object *object) +gf100_mspdec_init(struct nvkm_object *object) { - struct nvc0_vp_priv *priv = (void *)object; + struct gf100_mspdec_priv *priv = (void *)object; int ret; - ret = nouveau_falcon_init(&priv->base); + ret = nvkm_falcon_init(&priv->base); if (ret) return ret; @@ -76,35 +75,35 @@ nvc0_vp_init(struct nouveau_object *object) } static int -nvc0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_vp_priv *priv; + struct gf100_mspdec_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true, - "PVP", "vp", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, + "PMSPDEC", "mspdec", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00020000; - nv_subdev(priv)->intr = nouveau_falcon_intr; - nv_engine(priv)->cclass = &nvc0_vp_cclass; - nv_engine(priv)->sclass = nvc0_vp_sclass; + nv_subdev(priv)->intr = nvkm_falcon_intr; + nv_engine(priv)->cclass = &gf100_mspdec_cclass; + nv_engine(priv)->sclass = gf100_mspdec_sclass; return 0; } -struct nouveau_oclass -nvc0_vp_oclass = { - .handle = NV_ENGINE(VP, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_vp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_vp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +gf100_mspdec_oclass = { + .handle = NV_ENGINE(MSPDEC, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_mspdec_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gf100_mspdec_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c index d4c3108479c9..979920650dbd 100644 --- a/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c @@ -21,52 +21,51 @@ * * Authors: Ben Skeggs */ - +#include <engine/mspdec.h> #include <engine/falcon.h> -#include <engine/vp.h> -struct nve0_vp_priv { - struct nouveau_falcon base; +struct gk104_mspdec_priv { + struct nvkm_falcon base; }; /******************************************************************************* - * VP object classes + * MSPDEC object classes ******************************************************************************/ -static struct nouveau_oclass -nve0_vp_sclass[] = { - { 0x95b2, &nouveau_object_ofuncs }, +static struct nvkm_oclass +gk104_mspdec_sclass[] = { + { 0x95b2, &nvkm_object_ofuncs }, {}, }; /******************************************************************************* - * PVP context + * PMSPDEC context ******************************************************************************/ -static struct nouveau_oclass -nve0_vp_cclass = { - .handle = NV_ENGCTX(VP, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +gk104_mspdec_cclass = { + .handle = NV_ENGCTX(MSPDEC, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PVP engine/subdev functions + * PMSPDEC engine/subdev functions ******************************************************************************/ static int -nve0_vp_init(struct nouveau_object *object) +gk104_mspdec_init(struct nvkm_object *object) { - struct nve0_vp_priv *priv = (void *)object; + struct gk104_mspdec_priv *priv = (void *)object; int ret; - ret = nouveau_falcon_init(&priv->base); + ret = nvkm_falcon_init(&priv->base); if (ret) return ret; @@ -76,35 +75,35 @@ nve0_vp_init(struct nouveau_object *object) } static int -nve0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_vp_priv *priv; + struct gk104_mspdec_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true, - "PVP", "vp", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, + "PMSPDEC", "mspdec", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00020000; - nv_subdev(priv)->intr = nouveau_falcon_intr; - nv_engine(priv)->cclass = &nve0_vp_cclass; - nv_engine(priv)->sclass = nve0_vp_sclass; + nv_subdev(priv)->intr = nvkm_falcon_intr; + nv_engine(priv)->cclass = &gk104_mspdec_cclass; + nv_engine(priv)->sclass = gk104_mspdec_sclass; return 0; } -struct nouveau_oclass -nve0_vp_oclass = { - .handle = NV_ENGINE(VP, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_vp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nve0_vp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +gk104_mspdec_oclass = { + .handle = NV_ENGINE(MSPDEC, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_mspdec_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gk104_mspdec_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild new file mode 100644 index 000000000000..4576a9eee39d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild @@ -0,0 +1,2 @@ +nvkm-y += nvkm/engine/msppp/g98.o +nvkm-y += nvkm/engine/msppp/gf100.o diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c index 13bf31c40aa1..7a602a2dec94 100644 --- a/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c @@ -21,53 +21,52 @@ * * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin */ - +#include <engine/msppp.h> #include <engine/falcon.h> -#include <engine/ppp.h> -struct nv98_ppp_priv { - struct nouveau_falcon base; +struct g98_msppp_priv { + struct nvkm_falcon base; }; /******************************************************************************* - * PPP object classes + * MSPPP object classes ******************************************************************************/ -static struct nouveau_oclass -nv98_ppp_sclass[] = { - { 0x88b3, &nouveau_object_ofuncs }, - { 0x85b3, &nouveau_object_ofuncs }, +static struct nvkm_oclass +g98_msppp_sclass[] = { + { 0x88b3, &nvkm_object_ofuncs }, + { 0x85b3, &nvkm_object_ofuncs }, {}, }; /******************************************************************************* - * PPPP context + * PMSPPP context ******************************************************************************/ -static struct nouveau_oclass -nv98_ppp_cclass = { - .handle = NV_ENGCTX(PPP, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +g98_msppp_cclass = { + .handle = NV_ENGCTX(MSPPP, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PPPP engine/subdev functions + * PMSPPP engine/subdev functions ******************************************************************************/ static int -nv98_ppp_init(struct nouveau_object *object) +g98_msppp_init(struct nvkm_object *object) { - struct nv98_ppp_priv *priv = (void *)object; + struct g98_msppp_priv *priv = (void *)object; int ret; - ret = nouveau_falcon_init(&priv->base); + ret = nvkm_falcon_init(&priv->base); if (ret) return ret; @@ -77,34 +76,34 @@ nv98_ppp_init(struct nouveau_object *object) } static int -nv98_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv98_ppp_priv *priv; + struct g98_msppp_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true, - "PPPP", "ppp", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, + "PMSPPP", "msppp", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00400002; - nv_engine(priv)->cclass = &nv98_ppp_cclass; - nv_engine(priv)->sclass = nv98_ppp_sclass; + nv_engine(priv)->cclass = &g98_msppp_cclass; + nv_engine(priv)->sclass = g98_msppp_sclass; return 0; } -struct nouveau_oclass -nv98_ppp_oclass = { - .handle = NV_ENGINE(PPP, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv98_ppp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nv98_ppp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +g98_msppp_oclass = { + .handle = NV_ENGINE(MSPPP, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g98_msppp_ctor, + .dtor = _nvkm_falcon_dtor, + .init = g98_msppp_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c index 73719aaa62d6..6047baee1f75 100644 --- a/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c @@ -21,52 +21,51 @@ * * Authors: Maarten Lankhorst */ - +#include <engine/msppp.h> #include <engine/falcon.h> -#include <engine/ppp.h> -struct nvc0_ppp_priv { - struct nouveau_falcon base; +struct gf100_msppp_priv { + struct nvkm_falcon base; }; /******************************************************************************* - * PPP object classes + * MSPPP object classes ******************************************************************************/ -static struct nouveau_oclass -nvc0_ppp_sclass[] = { - { 0x90b3, &nouveau_object_ofuncs }, +static struct nvkm_oclass +gf100_msppp_sclass[] = { + { 0x90b3, &nvkm_object_ofuncs }, {}, }; /******************************************************************************* - * PPPP context + * PMSPPP context ******************************************************************************/ -static struct nouveau_oclass -nvc0_ppp_cclass = { - .handle = NV_ENGCTX(PPP, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +gf100_msppp_cclass = { + .handle = NV_ENGCTX(MSPPP, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PPPP engine/subdev functions + * PMSPPP engine/subdev functions ******************************************************************************/ static int -nvc0_ppp_init(struct nouveau_object *object) +gf100_msppp_init(struct nvkm_object *object) { - struct nvc0_ppp_priv *priv = (void *)object; + struct gf100_msppp_priv *priv = (void *)object; int ret; - ret = nouveau_falcon_init(&priv->base); + ret = nvkm_falcon_init(&priv->base); if (ret) return ret; @@ -76,35 +75,35 @@ nvc0_ppp_init(struct nouveau_object *object) } static int -nvc0_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_ppp_priv *priv; + struct gf100_msppp_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true, - "PPPP", "ppp", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, + "PMSPPP", "msppp", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00000002; - nv_subdev(priv)->intr = nouveau_falcon_intr; - nv_engine(priv)->cclass = &nvc0_ppp_cclass; - nv_engine(priv)->sclass = nvc0_ppp_sclass; + nv_subdev(priv)->intr = nvkm_falcon_intr; + nv_engine(priv)->cclass = &gf100_msppp_cclass; + nv_engine(priv)->sclass = gf100_msppp_sclass; return 0; } -struct nouveau_oclass -nvc0_ppp_oclass = { - .handle = NV_ENGINE(PPP, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_ppp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_ppp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +gf100_msppp_oclass = { + .handle = NV_ENGINE(MSPPP, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_msppp_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gf100_msppp_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild new file mode 100644 index 000000000000..0c9811009e28 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild @@ -0,0 +1,3 @@ +nvkm-y += nvkm/engine/msvld/g98.o +nvkm-y += nvkm/engine/msvld/gf100.o +nvkm-y += nvkm/engine/msvld/gk104.o diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c index 6b089e022fd2..c8a6b4ef52a1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c @@ -21,54 +21,53 @@ * * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin */ - +#include <engine/msvld.h> #include <engine/falcon.h> -#include <engine/bsp.h> -struct nv98_bsp_priv { - struct nouveau_falcon base; +struct g98_msvld_priv { + struct nvkm_falcon base; }; /******************************************************************************* - * BSP object classes + * MSVLD object classes ******************************************************************************/ -static struct nouveau_oclass -nv98_bsp_sclass[] = { - { 0x88b1, &nouveau_object_ofuncs }, - { 0x85b1, &nouveau_object_ofuncs }, - { 0x86b1, &nouveau_object_ofuncs }, +static struct nvkm_oclass +g98_msvld_sclass[] = { + { 0x88b1, &nvkm_object_ofuncs }, + { 0x85b1, &nvkm_object_ofuncs }, + { 0x86b1, &nvkm_object_ofuncs }, {}, }; /******************************************************************************* - * PBSP context + * PMSVLD context ******************************************************************************/ -static struct nouveau_oclass -nv98_bsp_cclass = { - .handle = NV_ENGCTX(BSP, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +g98_msvld_cclass = { + .handle = NV_ENGCTX(MSVLD, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PBSP engine/subdev functions + * PMSVLD engine/subdev functions ******************************************************************************/ static int -nv98_bsp_init(struct nouveau_object *object) +g98_msvld_init(struct nvkm_object *object) { - struct nv98_bsp_priv *priv = (void *)object; + struct g98_msvld_priv *priv = (void *)object; int ret; - ret = nouveau_falcon_init(&priv->base); + ret = nvkm_falcon_init(&priv->base); if (ret) return ret; @@ -78,34 +77,34 @@ nv98_bsp_init(struct nouveau_object *object) } static int -nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g98_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv98_bsp_priv *priv; + struct g98_msvld_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, - "PBSP", "bsp", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, + "PMSVLD", "msvld", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x04008000; - nv_engine(priv)->cclass = &nv98_bsp_cclass; - nv_engine(priv)->sclass = nv98_bsp_sclass; + nv_engine(priv)->cclass = &g98_msvld_cclass; + nv_engine(priv)->sclass = g98_msvld_sclass; return 0; } -struct nouveau_oclass -nv98_bsp_oclass = { - .handle = NV_ENGINE(BSP, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv98_bsp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nv98_bsp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +g98_msvld_oclass = { + .handle = NV_ENGINE(MSVLD, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g98_msvld_ctor, + .dtor = _nvkm_falcon_dtor, + .init = g98_msvld_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c index ce860de43e61..b8d1e0f521ef 100644 --- a/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c @@ -21,52 +21,51 @@ * * Authors: Maarten Lankhorst */ - +#include <engine/msvld.h> #include <engine/falcon.h> -#include <engine/bsp.h> -struct nvc0_bsp_priv { - struct nouveau_falcon base; +struct gf100_msvld_priv { + struct nvkm_falcon base; }; /******************************************************************************* - * BSP object classes + * MSVLD object classes ******************************************************************************/ -static struct nouveau_oclass -nvc0_bsp_sclass[] = { - { 0x90b1, &nouveau_object_ofuncs }, +static struct nvkm_oclass +gf100_msvld_sclass[] = { + { 0x90b1, &nvkm_object_ofuncs }, {}, }; /******************************************************************************* - * PBSP context + * PMSVLD context ******************************************************************************/ -static struct nouveau_oclass -nvc0_bsp_cclass = { - .handle = NV_ENGCTX(BSP, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +gf100_msvld_cclass = { + .handle = NV_ENGCTX(MSVLD, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PBSP engine/subdev functions + * PMSVLD engine/subdev functions ******************************************************************************/ static int -nvc0_bsp_init(struct nouveau_object *object) +gf100_msvld_init(struct nvkm_object *object) { - struct nvc0_bsp_priv *priv = (void *)object; + struct gf100_msvld_priv *priv = (void *)object; int ret; - ret = nouveau_falcon_init(&priv->base); + ret = nvkm_falcon_init(&priv->base); if (ret) return ret; @@ -76,35 +75,35 @@ nvc0_bsp_init(struct nouveau_object *object) } static int -nvc0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_bsp_priv *priv; + struct gf100_msvld_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, - "PBSP", "bsp", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, + "PMSVLD", "msvld", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00008000; - nv_subdev(priv)->intr = nouveau_falcon_intr; - nv_engine(priv)->cclass = &nvc0_bsp_cclass; - nv_engine(priv)->sclass = nvc0_bsp_sclass; + nv_subdev(priv)->intr = nvkm_falcon_intr; + nv_engine(priv)->cclass = &gf100_msvld_cclass; + nv_engine(priv)->sclass = gf100_msvld_sclass; return 0; } -struct nouveau_oclass -nvc0_bsp_oclass = { - .handle = NV_ENGINE(BSP, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_bsp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_bsp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +gf100_msvld_oclass = { + .handle = NV_ENGINE(MSVLD, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_msvld_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gf100_msvld_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c index ba6aeca0285e..a0b0927834df 100644 --- a/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c @@ -21,52 +21,51 @@ * * Authors: Ben Skeggs */ - +#include <engine/msvld.h> #include <engine/falcon.h> -#include <engine/bsp.h> -struct nve0_bsp_priv { - struct nouveau_falcon base; +struct gk104_msvld_priv { + struct nvkm_falcon base; }; /******************************************************************************* - * BSP object classes + * MSVLD object classes ******************************************************************************/ -static struct nouveau_oclass -nve0_bsp_sclass[] = { - { 0x95b1, &nouveau_object_ofuncs }, +static struct nvkm_oclass +gk104_msvld_sclass[] = { + { 0x95b1, &nvkm_object_ofuncs }, {}, }; /******************************************************************************* - * PBSP context + * PMSVLD context ******************************************************************************/ -static struct nouveau_oclass -nve0_bsp_cclass = { - .handle = NV_ENGCTX(BSP, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +gk104_msvld_cclass = { + .handle = NV_ENGCTX(MSVLD, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PBSP engine/subdev functions + * PMSVLD engine/subdev functions ******************************************************************************/ static int -nve0_bsp_init(struct nouveau_object *object) +gk104_msvld_init(struct nvkm_object *object) { - struct nve0_bsp_priv *priv = (void *)object; + struct gk104_msvld_priv *priv = (void *)object; int ret; - ret = nouveau_falcon_init(&priv->base); + ret = nvkm_falcon_init(&priv->base); if (ret) return ret; @@ -76,35 +75,35 @@ nve0_bsp_init(struct nouveau_object *object) } static int -nve0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_bsp_priv *priv; + struct gk104_msvld_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, - "PBSP", "bsp", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, + "PMSVLD", "msvld", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00008000; - nv_subdev(priv)->intr = nouveau_falcon_intr; - nv_engine(priv)->cclass = &nve0_bsp_cclass; - nv_engine(priv)->sclass = nve0_bsp_sclass; + nv_subdev(priv)->intr = nvkm_falcon_intr; + nv_engine(priv)->cclass = &gk104_msvld_cclass; + nv_engine(priv)->sclass = gk104_msvld_sclass; return 0; } -struct nouveau_oclass -nve0_bsp_oclass = { - .handle = NV_ENGINE(BSP, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_bsp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nve0_bsp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +gk104_msvld_oclass = { + .handle = NV_ENGINE(MSVLD, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_msvld_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gk104_msvld_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild new file mode 100644 index 000000000000..413b6091e256 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild @@ -0,0 +1,9 @@ +nvkm-y += nvkm/engine/pm/base.o +nvkm-y += nvkm/engine/pm/daemon.o +nvkm-y += nvkm/engine/pm/nv40.o +nvkm-y += nvkm/engine/pm/nv50.o +nvkm-y += nvkm/engine/pm/g84.o +nvkm-y += nvkm/engine/pm/gt215.o +nvkm-y += nvkm/engine/pm/gf100.o +nvkm-y += nvkm/engine/pm/gk104.o +nvkm-y += nvkm/engine/pm/gk110.o diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c index 63013812f7c9..2006c445938d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -21,22 +21,21 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <core/client.h> +#include <core/device.h> #include <core/option.h> -#include <nvif/unpack.h> + #include <nvif/class.h> #include <nvif/ioctl.h> - -#include <subdev/clock.h> - -#include "priv.h" +#include <nvif/unpack.h> #define QUAD_MASK 0x0f #define QUAD_FREE 0x01 -static struct nouveau_perfsig * -nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size) +static struct nvkm_perfsig * +nvkm_perfsig_find_(struct nvkm_perfdom *dom, const char *name, u32 size) { char path[64]; int i; @@ -58,16 +57,16 @@ nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size) return NULL; } -struct nouveau_perfsig * -nouveau_perfsig_find(struct nouveau_perfmon *ppm, const char *name, u32 size, - struct nouveau_perfdom **pdom) +struct nvkm_perfsig * +nvkm_perfsig_find(struct nvkm_pm *ppm, const char *name, u32 size, + struct nvkm_perfdom **pdom) { - struct nouveau_perfdom *dom = *pdom; - struct nouveau_perfsig *sig; + struct nvkm_perfdom *dom = *pdom; + struct nvkm_perfsig *sig; if (dom == NULL) { list_for_each_entry(dom, &ppm->domains, head) { - sig = nouveau_perfsig_find_(dom, name, size); + sig = nvkm_perfsig_find_(dom, name, size); if (sig) { *pdom = dom; return sig; @@ -77,17 +76,17 @@ nouveau_perfsig_find(struct nouveau_perfmon *ppm, const char *name, u32 size, return NULL; } - return nouveau_perfsig_find_(dom, name, size); + return nvkm_perfsig_find_(dom, name, size); } -struct nouveau_perfctr * -nouveau_perfsig_wrap(struct nouveau_perfmon *ppm, const char *name, - struct nouveau_perfdom **pdom) +struct nvkm_perfctr * +nvkm_perfsig_wrap(struct nvkm_pm *ppm, const char *name, + struct nvkm_perfdom **pdom) { - struct nouveau_perfsig *sig; - struct nouveau_perfctr *ctr; + struct nvkm_perfsig *sig; + struct nvkm_perfctr *ctr; - sig = nouveau_perfsig_find(ppm, name, strlen(name), pdom); + sig = nvkm_perfsig_find(ppm, name, strlen(name), pdom); if (!sig) return NULL; @@ -104,16 +103,16 @@ nouveau_perfsig_wrap(struct nouveau_perfmon *ppm, const char *name, * Perfmon object classes ******************************************************************************/ static int -nouveau_perfctr_query(struct nouveau_object *object, void *data, u32 size) +nvkm_perfctr_query(struct nvkm_object *object, void *data, u32 size) { union { struct nvif_perfctr_query_v0 v0; } *args = data; - struct nouveau_device *device = nv_device(object); - struct nouveau_perfmon *ppm = (void *)object->engine; - struct nouveau_perfdom *dom = NULL, *chk; - const bool all = nouveau_boolopt(device->cfgopt, "NvPmShowAll", false); - const bool raw = nouveau_boolopt(device->cfgopt, "NvPmUnnamed", all); + struct nvkm_device *device = nv_device(object); + struct nvkm_pm *ppm = (void *)object->engine; + struct nvkm_perfdom *dom = NULL, *chk; + const bool all = nvkm_boolopt(device->cfgopt, "NvPmShowAll", false); + const bool raw = nvkm_boolopt(device->cfgopt, "NvPmUnnamed", all); const char *name; int tmp = 0, di, si; int ret; @@ -163,14 +162,14 @@ nouveau_perfctr_query(struct nouveau_object *object, void *data, u32 size) } static int -nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size) +nvkm_perfctr_sample(struct nvkm_object *object, void *data, u32 size) { union { struct nvif_perfctr_sample none; } *args = data; - struct nouveau_perfmon *ppm = (void *)object->engine; - struct nouveau_perfctr *ctr, *tmp; - struct nouveau_perfdom *dom; + struct nvkm_pm *ppm = (void *)object->engine; + struct nvkm_perfctr *ctr, *tmp; + struct nvkm_perfdom *dom; int ret; nv_ioctl(object, "perfctr sample size %d\n", size); @@ -187,7 +186,7 @@ nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size) tmp = NULL; while (!list_empty(&dom->list)) { ctr = list_first_entry(&dom->list, - typeof(*ctr), head); + typeof(*ctr), head); if (ctr->slot < 0) break; if ( tmp && tmp == ctr) break; if (!tmp) tmp = ctr; @@ -216,12 +215,12 @@ nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size) } static int -nouveau_perfctr_read(struct nouveau_object *object, void *data, u32 size) +nvkm_perfctr_read(struct nvkm_object *object, void *data, u32 size) { union { struct nvif_perfctr_read_v0 v0; } *args = data; - struct nouveau_perfctr *ctr = (void *)object; + struct nvkm_perfctr *ctr = (void *)object; int ret; nv_ioctl(object, "perfctr read size %d\n", size); @@ -239,16 +238,15 @@ nouveau_perfctr_read(struct nouveau_object *object, void *data, u32 size) } static int -nouveau_perfctr_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) +nvkm_perfctr_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { switch (mthd) { case NVIF_PERFCTR_V0_QUERY: - return nouveau_perfctr_query(object, data, size); + return nvkm_perfctr_query(object, data, size); case NVIF_PERFCTR_V0_SAMPLE: - return nouveau_perfctr_sample(object, data, size); + return nvkm_perfctr_sample(object, data, size); case NVIF_PERFCTR_V0_READ: - return nouveau_perfctr_read(object, data, size); + return nvkm_perfctr_read(object, data, size); default: break; } @@ -256,27 +254,26 @@ nouveau_perfctr_mthd(struct nouveau_object *object, u32 mthd, } static void -nouveau_perfctr_dtor(struct nouveau_object *object) +nvkm_perfctr_dtor(struct nvkm_object *object) { - struct nouveau_perfctr *ctr = (void *)object; + struct nvkm_perfctr *ctr = (void *)object; if (ctr->head.next) list_del(&ctr->head); - nouveau_object_destroy(&ctr->base); + nvkm_object_destroy(&ctr->base); } static int -nouveau_perfctr_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nvkm_perfctr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { union { struct nvif_perfctr_v0 v0; } *args = data; - struct nouveau_perfmon *ppm = (void *)engine; - struct nouveau_perfdom *dom = NULL; - struct nouveau_perfsig *sig[4] = {}; - struct nouveau_perfctr *ctr; + struct nvkm_pm *ppm = (void *)engine; + struct nvkm_perfdom *dom = NULL; + struct nvkm_perfsig *sig[4] = {}; + struct nvkm_perfctr *ctr; int ret, i; nv_ioctl(parent, "create perfctr size %d\n", size); @@ -287,15 +284,15 @@ nouveau_perfctr_ctor(struct nouveau_object *parent, return ret; for (i = 0; i < ARRAY_SIZE(args->v0.name) && args->v0.name[i][0]; i++) { - sig[i] = nouveau_perfsig_find(ppm, args->v0.name[i], - strnlen(args->v0.name[i], - sizeof(args->v0.name[i])), - &dom); + sig[i] = nvkm_perfsig_find(ppm, args->v0.name[i], + strnlen(args->v0.name[i], + sizeof(args->v0.name[i])), + &dom); if (!sig[i]) return -EINVAL; } - ret = nouveau_object_create(parent, engine, oclass, 0, &ctr); + ret = nvkm_object_create(parent, engine, oclass, 0, &ctr); *pobject = nv_object(ctr); if (ret) return ret; @@ -311,19 +308,19 @@ nouveau_perfctr_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_ofuncs -nouveau_perfctr_ofuncs = { - .ctor = nouveau_perfctr_ctor, - .dtor = nouveau_perfctr_dtor, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - .mthd = nouveau_perfctr_mthd, +static struct nvkm_ofuncs +nvkm_perfctr_ofuncs = { + .ctor = nvkm_perfctr_ctor, + .dtor = nvkm_perfctr_dtor, + .init = nvkm_object_init, + .fini = nvkm_object_fini, + .mthd = nvkm_perfctr_mthd, }; -struct nouveau_oclass -nouveau_perfmon_sclass[] = { +struct nvkm_oclass +nvkm_pm_sclass[] = { { .handle = NVIF_IOCTL_NEW_V0_PERFCTR, - .ofuncs = &nouveau_perfctr_ofuncs, + .ofuncs = &nvkm_perfctr_ofuncs, }, {}, }; @@ -332,27 +329,25 @@ nouveau_perfmon_sclass[] = { * PPM context ******************************************************************************/ static void -nouveau_perfctx_dtor(struct nouveau_object *object) +nvkm_perfctx_dtor(struct nvkm_object *object) { - struct nouveau_perfmon *ppm = (void *)object->engine; + struct nvkm_pm *ppm = (void *)object->engine; mutex_lock(&nv_subdev(ppm)->mutex); - nouveau_engctx_destroy(&ppm->context->base); + nvkm_engctx_destroy(&ppm->context->base); ppm->context = NULL; mutex_unlock(&nv_subdev(ppm)->mutex); } static int -nouveau_perfctx_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nvkm_perfctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_perfmon *ppm = (void *)engine; - struct nouveau_perfctx *ctx; + struct nvkm_pm *ppm = (void *)engine; + struct nvkm_perfctx *ctx; int ret; - ret = nouveau_engctx_create(parent, engine, oclass, NULL, - 0, 0, 0, &ctx); + ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0, 0, 0, &ctx); *pobject = nv_object(ctx); if (ret) return ret; @@ -368,14 +363,14 @@ nouveau_perfctx_ctor(struct nouveau_object *parent, return 0; } -struct nouveau_oclass -nouveau_perfmon_cclass = { - .handle = NV_ENGCTX(PERFMON, 0x00), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nouveau_perfctx_ctor, - .dtor = nouveau_perfctx_dtor, - .init = _nouveau_engctx_init, - .fini = _nouveau_engctx_fini, +struct nvkm_oclass +nvkm_pm_cclass = { + .handle = NV_ENGCTX(PM, 0x00), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nvkm_perfctx_ctor, + .dtor = nvkm_perfctx_dtor, + .init = _nvkm_engctx_init, + .fini = _nvkm_engctx_fini, }, }; @@ -383,13 +378,13 @@ nouveau_perfmon_cclass = { * PPM engine/subdev functions ******************************************************************************/ int -nouveau_perfdom_new(struct nouveau_perfmon *ppm, const char *name, u32 mask, - u32 base, u32 size_unit, u32 size_domain, - const struct nouveau_specdom *spec) +nvkm_perfdom_new(struct nvkm_pm *ppm, const char *name, u32 mask, + u32 base, u32 size_unit, u32 size_domain, + const struct nvkm_specdom *spec) { - const struct nouveau_specdom *sdom; - const struct nouveau_specsig *ssig; - struct nouveau_perfdom *dom; + const struct nvkm_specdom *sdom; + const struct nvkm_specsig *ssig; + struct nvkm_perfdom *dom; int i; for (i = 0; i == 0 || mask; i++) { @@ -436,44 +431,42 @@ nouveau_perfdom_new(struct nouveau_perfmon *ppm, const char *name, u32 mask, } int -_nouveau_perfmon_fini(struct nouveau_object *object, bool suspend) +_nvkm_pm_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_perfmon *ppm = (void *)object; - return nouveau_engine_fini(&ppm->base, suspend); + struct nvkm_pm *ppm = (void *)object; + return nvkm_engine_fini(&ppm->base, suspend); } int -_nouveau_perfmon_init(struct nouveau_object *object) +_nvkm_pm_init(struct nvkm_object *object) { - struct nouveau_perfmon *ppm = (void *)object; - return nouveau_engine_init(&ppm->base); + struct nvkm_pm *ppm = (void *)object; + return nvkm_engine_init(&ppm->base); } void -_nouveau_perfmon_dtor(struct nouveau_object *object) +_nvkm_pm_dtor(struct nvkm_object *object) { - struct nouveau_perfmon *ppm = (void *)object; - struct nouveau_perfdom *dom, *tmp; + struct nvkm_pm *ppm = (void *)object; + struct nvkm_perfdom *dom, *tmp; list_for_each_entry_safe(dom, tmp, &ppm->domains, head) { list_del(&dom->head); kfree(dom); } - nouveau_engine_destroy(&ppm->base); + nvkm_engine_destroy(&ppm->base); } int -nouveau_perfmon_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int length, void **pobject) +nvkm_pm_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_perfmon *ppm; + struct nvkm_pm *ppm; int ret; - ret = nouveau_engine_create_(parent, engine, oclass, true, "PPM", - "perfmon", length, pobject); + ret = nvkm_engine_create_(parent, engine, oclass, true, "PPM", + "pm", length, pobject); ppm = *pobject; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c index 50696cc7b7d7..a7a5f3a3c91b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c @@ -21,12 +21,11 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static void -pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) +pwr_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom, + struct nvkm_perfctr *ctr) { u32 mask = 0x00000000; u32 ctrl = 0x00000001; @@ -41,15 +40,15 @@ pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, } static void -pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) +pwr_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom, + struct nvkm_perfctr *ctr) { ctr->ctr = ppm->pwr[ctr->slot]; ctr->clk = ppm->pwr[ppm->last]; } static void -pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) +pwr_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom) { int i; @@ -59,16 +58,16 @@ pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) } } -static const struct nouveau_funcdom +static const struct nvkm_funcdom pwr_perfctr_func = { .init = pwr_perfctr_init, .read = pwr_perfctr_read, .next = pwr_perfctr_next, }; -const struct nouveau_specdom -nva3_perfmon_pwr[] = { - { 0x20, (const struct nouveau_specsig[]) { +const struct nvkm_specdom +gt215_pm_pwr[] = { + { 0x20, (const struct nvkm_specsig[]) { { 0x00, "pwr_gr_idle" }, { 0x04, "pwr_bsp_idle" }, { 0x05, "pwr_vp_idle" }, @@ -79,9 +78,9 @@ nva3_perfmon_pwr[] = { {} }; -const struct nouveau_specdom -nvc0_perfmon_pwr[] = { - { 0x20, (const struct nouveau_specsig[]) { +const struct nvkm_specdom +gf100_pm_pwr[] = { + { 0x20, (const struct nvkm_specsig[]) { { 0x00, "pwr_gr_idle" }, { 0x04, "pwr_bsp_idle" }, { 0x05, "pwr_vp_idle" }, @@ -93,9 +92,9 @@ nvc0_perfmon_pwr[] = { {} }; -const struct nouveau_specdom -nve0_perfmon_pwr[] = { - { 0x20, (const struct nouveau_specsig[]) { +const struct nvkm_specdom +gk104_pm_pwr[] = { + { 0x20, (const struct nvkm_specsig[]) { { 0x00, "pwr_gr_idle" }, { 0x04, "pwr_bsp_idle" }, { 0x05, "pwr_vp_idle" }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c new file mode 100644 index 000000000000..d54c6705ba17 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c @@ -0,0 +1,65 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "nv40.h" + +static const struct nvkm_specdom +g84_pm[] = { + { 0x20, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + {} +}; + +struct nvkm_oclass * +g84_pm_oclass = &(struct nv40_pm_oclass) { + .base.handle = NV_ENGINE(PM, 0x84), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv40_pm_ctor, + .dtor = _nvkm_pm_dtor, + .init = _nvkm_pm_init, + .fini = _nvkm_pm_fini, + }, + .doms = g84_pm, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c index 74b241042502..008fed73dd82 100644 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c @@ -21,42 +21,29 @@ * * Authors: Ben Skeggs */ +#include "gf100.h" -#include "nvc0.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nvc0_perfmon_hub[] = { +static const struct nvkm_specdom +gf100_pm_hub[] = { {} }; -static const struct nouveau_specdom -nvc0_perfmon_gpc[] = { +static const struct nvkm_specdom +gf100_pm_gpc[] = { {} }; -static const struct nouveau_specdom -nvc0_perfmon_part[] = { +static const struct nvkm_specdom +gf100_pm_part[] = { {} }; static void -nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) +gf100_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom, + struct nvkm_perfctr *ctr) { - struct nvc0_perfmon_priv *priv = (void *)ppm; - struct nvc0_perfmon_cntr *cntr = (void *)ctr; + struct gf100_pm_priv *priv = (void *)ppm; + struct gf100_pm_cntr *cntr = (void *)ctr; u32 log = ctr->logic_op; u32 src = 0x00000000; int i; @@ -71,11 +58,11 @@ nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, } static void -nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) +gf100_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom, + struct nvkm_perfctr *ctr) { - struct nvc0_perfmon_priv *priv = (void *)ppm; - struct nvc0_perfmon_cntr *cntr = (void *)ctr; + struct gf100_pm_priv *priv = (void *)ppm; + struct gf100_pm_cntr *cntr = (void *)ctr; switch (cntr->base.slot) { case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break; @@ -87,51 +74,50 @@ nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, } static void -nvc0_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) +gf100_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom) { - struct nvc0_perfmon_priv *priv = (void *)ppm; + struct gf100_pm_priv *priv = (void *)ppm; nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27); nv_wr32(priv, dom->addr + 0x0ec, 0x00000011); } -const struct nouveau_funcdom -nvc0_perfctr_func = { - .init = nvc0_perfctr_init, - .read = nvc0_perfctr_read, - .next = nvc0_perfctr_next, +const struct nvkm_funcdom +gf100_perfctr_func = { + .init = gf100_perfctr_init, + .read = gf100_perfctr_read, + .next = gf100_perfctr_next, }; int -nvc0_perfmon_fini(struct nouveau_object *object, bool suspend) +gf100_pm_fini(struct nvkm_object *object, bool suspend) { - struct nvc0_perfmon_priv *priv = (void *)object; + struct gf100_pm_priv *priv = (void *)object; nv_mask(priv, 0x000200, 0x10000000, 0x00000000); nv_mask(priv, 0x000200, 0x10000000, 0x10000000); - return nouveau_perfmon_fini(&priv->base, suspend); + return nvkm_pm_fini(&priv->base, suspend); } static int -nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_perfmon_priv *priv; + struct gf100_pm_priv *priv; u32 mask; int ret; - ret = nouveau_perfmon_create(parent, engine, oclass, &priv); + ret = nvkm_pm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, - nvc0_perfmon_pwr); + ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gf100_pm_pwr); if (ret) return ret; /* HUB */ - ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, - nvc0_perfmon_hub); + ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, + gf100_pm_hub); if (ret) return ret; @@ -140,8 +126,8 @@ nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, mask &= ~nv_rd32(priv, 0x022504); mask &= ~nv_rd32(priv, 0x022584); - ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000, - 0x1000, 0x200, nvc0_perfmon_gpc); + ret = nvkm_perfdom_new(&priv->base, "gpc", mask, 0x180000, + 0x1000, 0x200, gf100_pm_gpc); if (ret) return ret; @@ -150,24 +136,24 @@ nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, mask &= ~nv_rd32(priv, 0x022548); mask &= ~nv_rd32(priv, 0x0225c8); - ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000, - 0x1000, 0x200, nvc0_perfmon_part); + ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000, + 0x1000, 0x200, gf100_pm_part); if (ret) return ret; - nv_engine(priv)->cclass = &nouveau_perfmon_cclass; - nv_engine(priv)->sclass = nouveau_perfmon_sclass; + nv_engine(priv)->cclass = &nvkm_pm_cclass; + nv_engine(priv)->sclass = nvkm_pm_sclass; priv->base.last = 7; return 0; } -struct nouveau_oclass -nvc0_perfmon_oclass = { - .handle = NV_ENGINE(PERFMON, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = nvc0_perfmon_fini, +struct nvkm_oclass +gf100_pm_oclass = { + .handle = NV_ENGINE(PM, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_pm_ctor, + .dtor = _nvkm_pm_dtor, + .init = _nvkm_pm_init, + .fini = gf100_pm_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h new file mode 100644 index 000000000000..6a01fc7fec6f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h @@ -0,0 +1,15 @@ +#ifndef __NVKM_PM_NVC0_H__ +#define __NVKM_PM_NVC0_H__ +#include "priv.h" + +struct gf100_pm_priv { + struct nvkm_pm base; +}; + +struct gf100_pm_cntr { + struct nvkm_perfctr base; +}; + +extern const struct nvkm_funcdom gf100_perfctr_func; +int gf100_pm_fini(struct nvkm_object *, bool); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c new file mode 100644 index 000000000000..75b9ff3d1a2c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c @@ -0,0 +1,148 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "gf100.h" + +static const struct nvkm_specdom +gk104_pm_hub[] = { + { 0x60, (const struct nvkm_specsig[]) { + { 0x47, "hub00_user_0" }, + {} + }, &gf100_perfctr_func }, + { 0x40, (const struct nvkm_specsig[]) { + { 0x27, "hub01_user_0" }, + {} + }, &gf100_perfctr_func }, + { 0x60, (const struct nvkm_specsig[]) { + { 0x47, "hub02_user_0" }, + {} + }, &gf100_perfctr_func }, + { 0x60, (const struct nvkm_specsig[]) { + { 0x47, "hub03_user_0" }, + {} + }, &gf100_perfctr_func }, + { 0x40, (const struct nvkm_specsig[]) { + { 0x03, "host_mmio_rd" }, + { 0x27, "hub04_user_0" }, + {} + }, &gf100_perfctr_func }, + { 0x60, (const struct nvkm_specsig[]) { + { 0x47, "hub05_user_0" }, + {} + }, &gf100_perfctr_func }, + { 0xc0, (const struct nvkm_specsig[]) { + { 0x74, "host_fb_rd3x" }, + { 0x75, "host_fb_rd3x_2" }, + { 0xa7, "hub06_user_0" }, + {} + }, &gf100_perfctr_func }, + { 0x60, (const struct nvkm_specsig[]) { + { 0x47, "hub07_user_0" }, + {} + }, &gf100_perfctr_func }, + {} +}; + +static const struct nvkm_specdom +gk104_pm_gpc[] = { + { 0xe0, (const struct nvkm_specsig[]) { + { 0xc7, "gpc00_user_0" }, + {} + }, &gf100_perfctr_func }, + {} +}; + +static const struct nvkm_specdom +gk104_pm_part[] = { + { 0x60, (const struct nvkm_specsig[]) { + { 0x47, "part00_user_0" }, + {} + }, &gf100_perfctr_func }, + { 0x60, (const struct nvkm_specsig[]) { + { 0x47, "part01_user_0" }, + {} + }, &gf100_perfctr_func }, + {} +}; + +static int +gk104_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gf100_pm_priv *priv; + u32 mask; + int ret; + + ret = nvkm_pm_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + /* PDAEMON */ + ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gk104_pm_pwr); + if (ret) + return ret; + + /* HUB */ + ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, + gk104_pm_hub); + if (ret) + return ret; + + /* GPC */ + mask = (1 << nv_rd32(priv, 0x022430)) - 1; + mask &= ~nv_rd32(priv, 0x022504); + mask &= ~nv_rd32(priv, 0x022584); + + ret = nvkm_perfdom_new(&priv->base, "gpc", mask, 0x180000, + 0x1000, 0x200, gk104_pm_gpc); + if (ret) + return ret; + + /* PART */ + mask = (1 << nv_rd32(priv, 0x022438)) - 1; + mask &= ~nv_rd32(priv, 0x022548); + mask &= ~nv_rd32(priv, 0x0225c8); + + ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000, + 0x1000, 0x200, gk104_pm_part); + if (ret) + return ret; + + nv_engine(priv)->cclass = &nvkm_pm_cclass; + nv_engine(priv)->sclass = nvkm_pm_sclass; + priv->base.last = 7; + return 0; +} + +struct nvkm_oclass +gk104_pm_oclass = { + .handle = NV_ENGINE(PM, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_pm_ctor, + .dtor = _nvkm_pm_dtor, + .init = _nvkm_pm_init, + .fini = gf100_pm_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c new file mode 100644 index 000000000000..6820176e5f78 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c @@ -0,0 +1,57 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "gf100.h" + +static int +gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gf100_pm_priv *priv; + int ret; + + ret = nvkm_pm_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gk104_pm_pwr); + if (ret) + return ret; + + nv_engine(priv)->cclass = &nvkm_pm_cclass; + nv_engine(priv)->sclass = nvkm_pm_sclass; + return 0; +} + +struct nvkm_oclass +gk110_pm_oclass = { + .handle = NV_ENGINE(PM, 0xf0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk110_pm_ctor, + .dtor = _nvkm_pm_dtor, + .init = _nvkm_pm_init, + .fini = gf100_pm_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c index 9232c7fc6253..d065bfc59bbf 100644 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c @@ -21,58 +21,63 @@ * * Authors: Ben Skeggs */ - #include "nv40.h" -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nv84_perfmon[] = { - { 0x20, (const struct nouveau_specsig[]) { +static const struct nvkm_specdom +gt215_pm[] = { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, {} }; -struct nouveau_oclass * -nv84_perfmon_oclass = &(struct nv40_perfmon_oclass) { - .base.handle = NV_ENGINE(PERFMON, 0x84), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = _nouveau_perfmon_fini, +static int +gt215_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **object) +{ + int ret = nv40_pm_ctor(parent, engine, oclass, data, size, object); + if (ret == 0) { + struct nv40_pm_priv *priv = (void *)*object; + ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, + gt215_pm_pwr); + if (ret) + return ret; + + priv->base.last = 3; + } + return ret; +} + +struct nvkm_oclass * +gt215_pm_oclass = &(struct nv40_pm_oclass) { + .base.handle = NV_ENGINE(PM, 0xa3), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gt215_pm_ctor, + .dtor = _nvkm_pm_dtor, + .init = _nvkm_pm_init, + .fini = _nvkm_pm_fini, }, - .doms = nv84_perfmon, + .doms = gt215_pm, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c index b2a10785adb1..ff22f06b22b8 100644 --- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c @@ -21,27 +21,14 @@ * * Authors: Ben Skeggs */ - #include "nv40.h" -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - static void -nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) +nv40_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom, + struct nvkm_perfctr *ctr) { - struct nv40_perfmon_priv *priv = (void *)ppm; - struct nv40_perfmon_cntr *cntr = (void *)ctr; + struct nv40_pm_priv *priv = (void *)ppm; + struct nv40_pm_cntr *cntr = (void *)ctr; u32 log = ctr->logic_op; u32 src = 0x00000000; int i; @@ -55,11 +42,11 @@ nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, } static void -nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) +nv40_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom, + struct nvkm_perfctr *ctr) { - struct nv40_perfmon_priv *priv = (void *)ppm; - struct nv40_perfmon_cntr *cntr = (void *)ctr; + struct nv40_pm_priv *priv = (void *)ppm; + struct nv40_pm_cntr *cntr = (void *)ctr; switch (cntr->base.slot) { case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break; @@ -71,73 +58,73 @@ nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, } static void -nv40_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) +nv40_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom) { - struct nv40_perfmon_priv *priv = (void *)ppm; + struct nv40_pm_priv *priv = (void *)ppm; if (priv->sequence != ppm->sequence) { nv_wr32(priv, 0x400084, 0x00000020); priv->sequence = ppm->sequence; } } -const struct nouveau_funcdom +const struct nvkm_funcdom nv40_perfctr_func = { .init = nv40_perfctr_init, .read = nv40_perfctr_read, .next = nv40_perfctr_next, }; -static const struct nouveau_specdom -nv40_perfmon[] = { - { 0x20, (const struct nouveau_specsig[]) { +static const struct nvkm_specdom +nv40_pm[] = { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { + { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, {} }; int -nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv40_perfmon_oclass *mclass = (void *)oclass; - struct nv40_perfmon_priv *priv; + struct nv40_pm_oclass *mclass = (void *)oclass; + struct nv40_pm_priv *priv; int ret; - ret = nouveau_perfmon_create(parent, engine, oclass, &priv); + ret = nvkm_pm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms); + ret = nvkm_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms); if (ret) return ret; - nv_engine(priv)->cclass = &nouveau_perfmon_cclass; - nv_engine(priv)->sclass = nouveau_perfmon_sclass; + nv_engine(priv)->cclass = &nvkm_pm_cclass; + nv_engine(priv)->sclass = nvkm_pm_sclass; return 0; } -struct nouveau_oclass * -nv40_perfmon_oclass = &(struct nv40_perfmon_oclass) { - .base.handle = NV_ENGINE(PERFMON, 0x40), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = _nouveau_perfmon_fini, +struct nvkm_oclass * +nv40_pm_oclass = &(struct nv40_pm_oclass) { + .base.handle = NV_ENGINE(PM, 0x40), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv40_pm_ctor, + .dtor = _nvkm_pm_dtor, + .init = _nvkm_pm_init, + .fini = _nvkm_pm_fini, }, - .doms = nv40_perfmon, + .doms = nv40_pm, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h new file mode 100644 index 000000000000..2338e150420e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h @@ -0,0 +1,24 @@ +#ifndef __NVKM_PM_NV40_H__ +#define __NVKM_PM_NV40_H__ +#include "priv.h" + +struct nv40_pm_oclass { + struct nvkm_oclass base; + const struct nvkm_specdom *doms; +}; + +struct nv40_pm_priv { + struct nvkm_pm base; + u32 sequence; +}; + +int nv40_pm_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *data, u32 size, + struct nvkm_object **pobject); + +struct nv40_pm_cntr { + struct nvkm_perfctr base; +}; + +extern const struct nvkm_funcdom nv40_perfctr_func; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c new file mode 100644 index 000000000000..6af83b5d1b11 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c @@ -0,0 +1,57 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "nv40.h" + +static const struct nvkm_specdom +nv50_pm[] = { + { 0x040, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x100, (const struct nvkm_specsig[]) { + { 0xc8, "gr_idle" }, + {} + }, &nv40_perfctr_func }, + { 0x100, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x020, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x040, (const struct nvkm_specsig[]) { + {} + }, &nv40_perfctr_func }, + {} +}; + +struct nvkm_oclass * +nv50_pm_oclass = &(struct nv40_pm_oclass) { + .base.handle = NV_ENGINE(PM, 0x50), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv40_pm_ctor, + .dtor = _nvkm_pm_dtor, + .init = _nvkm_pm_init, + .fini = _nvkm_pm_fini, + }, + .doms = nv50_pm, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h new file mode 100644 index 000000000000..1e6eff2a6d79 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h @@ -0,0 +1,90 @@ +#ifndef __NVKM_PM_PRIV_H__ +#define __NVKM_PM_PRIV_H__ +#include <engine/pm.h> + +struct nvkm_perfctr { + struct nvkm_object base; + struct list_head head; + struct nvkm_perfsig *signal[4]; + int slot; + u32 logic_op; + u32 clk; + u32 ctr; +}; + +extern struct nvkm_oclass nvkm_pm_sclass[]; + +#include <core/engctx.h> + +struct nvkm_perfctx { + struct nvkm_engctx base; +}; + +extern struct nvkm_oclass nvkm_pm_cclass; + +struct nvkm_specsig { + u8 signal; + const char *name; +}; + +struct nvkm_perfsig { + const char *name; +}; + +struct nvkm_perfdom; +struct nvkm_perfctr * +nvkm_perfsig_wrap(struct nvkm_pm *, const char *, struct nvkm_perfdom **); + +struct nvkm_specdom { + u16 signal_nr; + const struct nvkm_specsig *signal; + const struct nvkm_funcdom *func; +}; + +extern const struct nvkm_specdom gt215_pm_pwr[]; +extern const struct nvkm_specdom gf100_pm_pwr[]; +extern const struct nvkm_specdom gk104_pm_pwr[]; + +struct nvkm_perfdom { + struct list_head head; + struct list_head list; + const struct nvkm_funcdom *func; + char name[32]; + u32 addr; + u8 quad; + u32 signal_nr; + struct nvkm_perfsig signal[]; +}; + +struct nvkm_funcdom { + void (*init)(struct nvkm_pm *, struct nvkm_perfdom *, + struct nvkm_perfctr *); + void (*read)(struct nvkm_pm *, struct nvkm_perfdom *, + struct nvkm_perfctr *); + void (*next)(struct nvkm_pm *, struct nvkm_perfdom *); +}; + +int nvkm_perfdom_new(struct nvkm_pm *, const char *, u32, u32, u32, u32, + const struct nvkm_specdom *); + +#define nvkm_pm_create(p,e,o,d) \ + nvkm_pm_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_pm_dtor(p) ({ \ + struct nvkm_pm *c = (p); \ + _nvkm_pm_dtor(nv_object(c)); \ +}) +#define nvkm_pm_init(p) ({ \ + struct nvkm_pm *c = (p); \ + _nvkm_pm_init(nv_object(c)); \ +}) +#define nvkm_pm_fini(p,s) ({ \ + struct nvkm_pm *c = (p); \ + _nvkm_pm_fini(nv_object(c), (s)); \ +}) + +int nvkm_pm_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_pm_dtor(struct nvkm_object *); +int _nvkm_pm_init(struct nvkm_object *); +int _nvkm_pm_fini(struct nvkm_object *, bool); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild new file mode 100644 index 000000000000..552d40a4641f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild @@ -0,0 +1 @@ +nvkm-y += nvkm/engine/sec/g98.o diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s index 629da02dc352..06ee06071104 100644 --- a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s @@ -1,5 +1,5 @@ /* - * fuc microcode for nv98 pcrypt engine + * fuc microcode for g98 psec engine * Copyright (C) 2010 Marcin Kościelnicki * * This program is free software; you can redistribute it and/or modify @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -.section #nv98_pcrypt_data +.section #g98_psec_data ctx_dma: ctx_dma_query: .b32 0 @@ -70,31 +70,31 @@ engine_cmd_dtable: .b32 #ctx_src_address_low + 0x20000 ~0xfffffff0 .b32 #ctx_dst_address_high + 0x20000 ~0xff .b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0 -.b32 #crypt_cmd_mode + 0x00000 ~0xf -.b32 #crypt_cmd_length + 0x10000 ~0x0ffffff0 +.b32 #sec_cmd_mode + 0x00000 ~0xf +.b32 #sec_cmd_length + 0x10000 ~0x0ffffff0 .equ #engine_cmd_max 0xce .align 4 -crypt_dtable: -.b16 #crypt_copy_prep #crypt_do_inout -.b16 #crypt_store_prep #crypt_do_out -.b16 #crypt_ecb_e_prep #crypt_do_inout -.b16 #crypt_ecb_d_prep #crypt_do_inout -.b16 #crypt_cbc_e_prep #crypt_do_inout -.b16 #crypt_cbc_d_prep #crypt_do_inout -.b16 #crypt_pcbc_e_prep #crypt_do_inout -.b16 #crypt_pcbc_d_prep #crypt_do_inout -.b16 #crypt_cfb_e_prep #crypt_do_inout -.b16 #crypt_cfb_d_prep #crypt_do_inout -.b16 #crypt_ofb_prep #crypt_do_inout -.b16 #crypt_ctr_prep #crypt_do_inout -.b16 #crypt_cbc_mac_prep #crypt_do_in -.b16 #crypt_cmac_finish_complete_prep #crypt_do_in -.b16 #crypt_cmac_finish_partial_prep #crypt_do_in +sec_dtable: +.b16 #sec_copy_prep #sec_do_inout +.b16 #sec_store_prep #sec_do_out +.b16 #sec_ecb_e_prep #sec_do_inout +.b16 #sec_ecb_d_prep #sec_do_inout +.b16 #sec_cbc_e_prep #sec_do_inout +.b16 #sec_cbc_d_prep #sec_do_inout +.b16 #sec_pcbc_e_prep #sec_do_inout +.b16 #sec_pcbc_d_prep #sec_do_inout +.b16 #sec_cfb_e_prep #sec_do_inout +.b16 #sec_cfb_d_prep #sec_do_inout +.b16 #sec_ofb_prep #sec_do_inout +.b16 #sec_ctr_prep #sec_do_inout +.b16 #sec_cbc_mac_prep #sec_do_in +.b16 #sec_cmac_finish_complete_prep #sec_do_in +.b16 #sec_cmac_finish_partial_prep #sec_do_in .align 0x100 -.section #nv98_pcrypt_code +.section #g98_psec_code // $r0 is always set to 0 in our code - this allows some space savings. clear b32 $r0 @@ -417,23 +417,23 @@ cmd_wrcache_flush: iowr I[$r2] $r3 ret -crypt_cmd_mode: +sec_cmd_mode: // if >= 0xf, INVALID_ENUM bset $flags $p1 or $r2 2 cmpu b32 $r3 0xf - bra nc #crypt_cmd_mode_return + bra nc #sec_cmd_mode_return bclr $flags $p1 st b32 D[$r0 + #ctx_mode] $r3 - crypt_cmd_mode_return: + sec_cmd_mode_return: ret -crypt_cmd_length: +sec_cmd_length: // nop if length == 0 cmpu b32 $r3 0 - bra e #crypt_cmd_mode_return + bra e #sec_cmd_mode_return // init key, IV cxset 3 @@ -471,11 +471,11 @@ crypt_cmd_length: shl b32 $r8 2 // run prep - ld b16 $r9 D[$r8 + #crypt_dtable] + ld b16 $r9 D[$r8 + #sec_dtable] call $r9 // do it - ld b16 $r9 D[$r8 + #crypt_dtable + 2] + ld b16 $r9 D[$r8 + #sec_dtable + 2] call $r9 cxset 1 xdwait @@ -509,25 +509,25 @@ crypt_cmd_length: ret -crypt_copy_prep: +sec_copy_prep: cs0begin 2 cxsin $c0 cxsout $c0 ret -crypt_store_prep: +sec_store_prep: cs0begin 1 cxsout $c6 ret -crypt_ecb_e_prep: +sec_ecb_e_prep: cs0begin 3 cxsin $c0 cenc $c0 $c0 cxsout $c0 ret -crypt_ecb_d_prep: +sec_ecb_d_prep: ckexp $c7 $c7 cs0begin 3 cxsin $c0 @@ -535,7 +535,7 @@ crypt_ecb_d_prep: cxsout $c0 ret -crypt_cbc_e_prep: +sec_cbc_e_prep: cs0begin 4 cxsin $c0 cxor $c6 $c0 @@ -543,7 +543,7 @@ crypt_cbc_e_prep: cxsout $c6 ret -crypt_cbc_d_prep: +sec_cbc_d_prep: ckexp $c7 $c7 cs0begin 5 cmov $c2 $c6 @@ -553,7 +553,7 @@ crypt_cbc_d_prep: cxsout $c0 ret -crypt_pcbc_e_prep: +sec_pcbc_e_prep: cs0begin 5 cxsin $c0 cxor $c6 $c0 @@ -562,7 +562,7 @@ crypt_pcbc_e_prep: cxor $c6 $c0 ret -crypt_pcbc_d_prep: +sec_pcbc_d_prep: ckexp $c7 $c7 cs0begin 5 cxsin $c0 @@ -572,7 +572,7 @@ crypt_pcbc_d_prep: cxor $c6 $c0 ret -crypt_cfb_e_prep: +sec_cfb_e_prep: cs0begin 4 cenc $c6 $c6 cxsin $c0 @@ -580,7 +580,7 @@ crypt_cfb_e_prep: cxsout $c6 ret -crypt_cfb_d_prep: +sec_cfb_d_prep: cs0begin 4 cenc $c0 $c6 cxsin $c6 @@ -588,7 +588,7 @@ crypt_cfb_d_prep: cxsout $c0 ret -crypt_ofb_prep: +sec_ofb_prep: cs0begin 4 cenc $c6 $c6 cxsin $c0 @@ -596,7 +596,7 @@ crypt_ofb_prep: cxsout $c0 ret -crypt_ctr_prep: +sec_ctr_prep: cs0begin 5 cenc $c1 $c6 cadd $c6 1 @@ -605,14 +605,14 @@ crypt_ctr_prep: cxsout $c0 ret -crypt_cbc_mac_prep: +sec_cbc_mac_prep: cs0begin 3 cxsin $c0 cxor $c6 $c0 cenc $c6 $c6 ret -crypt_cmac_finish_complete_prep: +sec_cmac_finish_complete_prep: cs0begin 7 cxsin $c0 cxor $c6 $c0 @@ -623,7 +623,7 @@ crypt_cmac_finish_complete_prep: cenc $c6 $c6 ret -crypt_cmac_finish_partial_prep: +sec_cmac_finish_partial_prep: cs0begin 8 cxsin $c0 cxor $c6 $c0 @@ -636,12 +636,12 @@ crypt_cmac_finish_partial_prep: ret // TODO -crypt_do_in: +sec_do_in: add b32 $r3 $r5 mov $xdbase $r4 mov $r9 #swap sethi $r9 0x20000 - crypt_do_in_loop: + sec_do_in_loop: xdld $r5 $r9 xdwait cxset 0x22 @@ -650,17 +650,17 @@ crypt_do_in: xdwait add b32 $r5 0x10 cmpu b32 $r5 $r3 - bra ne #crypt_do_in_loop + bra ne #sec_do_in_loop cxset 1 xdwait ret -crypt_do_out: +sec_do_out: add b32 $r3 $r7 mov $xdbase $r6 mov $r9 #swap sethi $r9 0x20000 - crypt_do_out_loop: + sec_do_out_loop: cs0exec 1 cxset 0x61 xdld $r7 $r9 @@ -669,14 +669,14 @@ crypt_do_out: xdwait add b32 $r7 0x10 cmpu b32 $r7 $r3 - bra ne #crypt_do_out_loop + bra ne #sec_do_out_loop ret -crypt_do_inout: +sec_do_inout: add b32 $r3 $r5 mov $r9 #swap sethi $r9 0x20000 - crypt_do_inout_loop: + sec_do_inout_loop: mov $xdbase $r4 xdld $r5 $r9 xdwait @@ -692,7 +692,7 @@ crypt_do_inout: add b32 $r5 0x10 add b32 $r7 0x10 cmpu b32 $r5 $r3 - bra ne #crypt_do_inout_loop + bra ne #sec_do_inout_loop ret .align 0x100 diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h index 38676c74e6e0..5d65c4fbb087 100644 --- a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h @@ -1,4 +1,4 @@ -uint32_t nv98_pcrypt_data[] = { +uint32_t g98_psec_data[] = { /* 0x0000: ctx_dma */ /* 0x0000: ctx_dma_query */ 0x00000000, @@ -103,7 +103,7 @@ uint32_t nv98_pcrypt_data[] = { 0xfffffff0, 0x00010285, 0xf000000f, -/* 0x0150: crypt_dtable */ +/* 0x0150: sec_dtable */ 0x04db0321, 0x04b1032f, 0x04db0339, @@ -150,7 +150,7 @@ uint32_t nv98_pcrypt_data[] = { 0x00000000, }; -uint32_t nv98_pcrypt_code[] = { +uint32_t g98_psec_code[] = { 0x17f004bd, 0x0010fe35, 0xf10004fe, @@ -329,14 +329,14 @@ uint32_t nv98_pcrypt_code[] = { 0xbd220027, 0x0133f034, 0xf80023d0, -/* 0x0271: crypt_cmd_mode */ +/* 0x0271: sec_cmd_mode */ 0x0131f400, 0xb00225f0, 0x18f40f34, 0x0132f409, -/* 0x0283: crypt_cmd_mode_return */ +/* 0x0283: sec_cmd_mode_return */ 0xf80d0380, -/* 0x0285: crypt_cmd_length */ +/* 0x0285: sec_cmd_length */ 0x0034b000, 0xf4fb0bf4, 0x47f0033c, @@ -376,33 +376,33 @@ uint32_t nv98_pcrypt_code[] = { 0xf05047f0, 0x04fa0643, 0xf803f805, -/* 0x0321: crypt_copy_prep */ +/* 0x0321: sec_copy_prep */ 0x203cf500, 0x003cf594, 0x003cf588, -/* 0x032f: crypt_store_prep */ +/* 0x032f: sec_store_prep */ 0xf500f88c, 0xf594103c, 0xf88c063c, -/* 0x0339: crypt_ecb_e_prep */ +/* 0x0339: sec_ecb_e_prep */ 0x303cf500, 0x003cf594, 0x003cf588, 0x003cf5d0, -/* 0x034b: crypt_ecb_d_prep */ +/* 0x034b: sec_ecb_d_prep */ 0xf500f88c, 0xf5c8773c, 0xf594303c, 0xf588003c, 0xf5d4003c, 0xf88c003c, -/* 0x0361: crypt_cbc_e_prep */ +/* 0x0361: sec_cbc_e_prep */ 0x403cf500, 0x003cf594, 0x063cf588, 0x663cf5ac, 0x063cf5d0, -/* 0x0377: crypt_cbc_d_prep */ +/* 0x0377: sec_cbc_d_prep */ 0xf500f88c, 0xf5c8773c, 0xf594503c, @@ -411,14 +411,14 @@ uint32_t nv98_pcrypt_code[] = { 0xf5d4603c, 0xf5ac203c, 0xf88c003c, -/* 0x0395: crypt_pcbc_e_prep */ +/* 0x0395: sec_pcbc_e_prep */ 0x503cf500, 0x003cf594, 0x063cf588, 0x663cf5ac, 0x063cf5d0, 0x063cf58c, -/* 0x03af: crypt_pcbc_d_prep */ +/* 0x03af: sec_pcbc_d_prep */ 0xf500f8ac, 0xf5c8773c, 0xf594503c, @@ -427,26 +427,26 @@ uint32_t nv98_pcrypt_code[] = { 0xf5ac163c, 0xf58c063c, 0xf8ac063c, -/* 0x03cd: crypt_cfb_e_prep */ +/* 0x03cd: sec_cfb_e_prep */ 0x403cf500, 0x663cf594, 0x003cf5d0, 0x063cf588, 0x063cf5ac, -/* 0x03e3: crypt_cfb_d_prep */ +/* 0x03e3: sec_cfb_d_prep */ 0xf500f88c, 0xf594403c, 0xf5d0603c, 0xf588063c, 0xf5ac603c, 0xf88c003c, -/* 0x03f9: crypt_ofb_prep */ +/* 0x03f9: sec_ofb_prep */ 0x403cf500, 0x663cf594, 0x003cf5d0, 0x603cf588, 0x003cf5ac, -/* 0x040f: crypt_ctr_prep */ +/* 0x040f: sec_ctr_prep */ 0xf500f88c, 0xf594503c, 0xf5d0613c, @@ -454,12 +454,12 @@ uint32_t nv98_pcrypt_code[] = { 0xf588003c, 0xf5ac103c, 0xf88c003c, -/* 0x0429: crypt_cbc_mac_prep */ +/* 0x0429: sec_cbc_mac_prep */ 0x303cf500, 0x003cf594, 0x063cf588, 0x663cf5ac, -/* 0x043b: crypt_cmac_finish_complete_prep */ +/* 0x043b: sec_cmac_finish_complete_prep */ 0xf500f8d0, 0xf594703c, 0xf588003c, @@ -469,7 +469,7 @@ uint32_t nv98_pcrypt_code[] = { 0xf5bc003c, 0xf5ac063c, 0xf8d0663c, -/* 0x045d: crypt_cmac_finish_partial_prep */ +/* 0x045d: sec_cmac_finish_partial_prep */ 0x803cf500, 0x003cf594, 0x063cf588, @@ -479,12 +479,12 @@ uint32_t nv98_pcrypt_code[] = { 0x003cf5bc, 0x063cf5bc, 0x663cf5ac, -/* 0x0483: crypt_do_in */ +/* 0x0483: sec_do_in */ 0xbb00f8d0, 0x47fe0035, 0x8097f100, 0x0293f000, -/* 0x0490: crypt_do_in_loop */ +/* 0x0490: sec_do_in_loop */ 0xf80559fa, 0x223cf403, 0xf50609fa, @@ -493,11 +493,11 @@ uint32_t nv98_pcrypt_code[] = { 0xf40453b8, 0x3cf4e91b, 0xf803f801, -/* 0x04b1: crypt_do_out */ +/* 0x04b1: sec_do_out */ 0x0037bb00, 0xf10067fe, 0xf0008097, -/* 0x04be: crypt_do_out_loop */ +/* 0x04be: sec_do_out_loop */ 0x3cf50293, 0x3cf49810, 0x0579fa61, @@ -505,11 +505,11 @@ uint32_t nv98_pcrypt_code[] = { 0x03f8013c, 0xb81070b6, 0x1bf40473, -/* 0x04db: crypt_do_inout */ +/* 0x04db: sec_do_inout */ 0xbb00f8e8, 0x97f10035, 0x93f00080, -/* 0x04e5: crypt_do_inout_loop */ +/* 0x04e5: sec_do_inout_loop */ 0x0047fe02, 0xf80559fa, 0x213cf403, diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c index 5571c09534cb..9d5c1b8b1f8c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c @@ -21,57 +21,50 @@ * * Authors: Ben Skeggs */ +#include <engine/sec.h> +#include <engine/falcon.h> +#include "fuc/g98.fuc0s.h" #include <core/client.h> -#include <core/os.h> #include <core/enum.h> -#include <core/engctx.h> - -#include <subdev/timer.h> -#include <subdev/fb.h> - -#include <engine/falcon.h> #include <engine/fifo.h> -#include <engine/crypt.h> - -#include "fuc/nv98.fuc.h" -struct nv98_crypt_priv { - struct nouveau_falcon base; +struct g98_sec_priv { + struct nvkm_falcon base; }; /******************************************************************************* * Crypt object classes ******************************************************************************/ -static struct nouveau_oclass -nv98_crypt_sclass[] = { - { 0x88b4, &nouveau_object_ofuncs }, +static struct nvkm_oclass +g98_sec_sclass[] = { + { 0x88b4, &nvkm_object_ofuncs }, {}, }; /******************************************************************************* - * PCRYPT context + * PSEC context ******************************************************************************/ -static struct nouveau_oclass -nv98_crypt_cclass = { - .handle = NV_ENGCTX(CRYPT, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, +static struct nvkm_oclass +g98_sec_cclass = { + .handle = NV_ENGCTX(SEC, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; /******************************************************************************* - * PCRYPT engine/subdev functions + * PSEC engine/subdev functions ******************************************************************************/ -static const struct nouveau_enum nv98_crypt_isr_error_name[] = { +static const struct nvkm_enum g98_sec_isr_error_name[] = { { 0x0000, "ILLEGAL_MTHD" }, { 0x0001, "INVALID_BITFIELD" }, { 0x0002, "INVALID_ENUM" }, @@ -80,12 +73,12 @@ static const struct nouveau_enum nv98_crypt_isr_error_name[] = { }; static void -nv98_crypt_intr(struct nouveau_subdev *subdev) +g98_sec_intr(struct nvkm_subdev *subdev) { - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nv98_crypt_priv *priv = (void *)subdev; + struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_engine *engine = nv_engine(subdev); + struct nvkm_object *engctx; + struct g98_sec_priv *priv = (void *)subdev; u32 disp = nv_rd32(priv, 0x08701c); u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16); u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff; @@ -96,14 +89,14 @@ nv98_crypt_intr(struct nouveau_subdev *subdev) u32 data = nv_rd32(priv, 0x087044); int chid; - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); chid = pfifo->chid(pfifo, engctx); if (stat & 0x00000040) { nv_error(priv, "DISPATCH_ERROR ["); - nouveau_enum_print(nv98_crypt_isr_error_name, ssta); + nvkm_enum_print(g98_sec_isr_error_name, ssta); pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", - chid, (u64)inst << 12, nouveau_client_name(engctx), + chid, (u64)inst << 12, nvkm_client_name(engctx), subc, mthd, data); nv_wr32(priv, 0x087004, 0x00000040); stat &= ~0x00000040; @@ -114,43 +107,43 @@ nv98_crypt_intr(struct nouveau_subdev *subdev) nv_wr32(priv, 0x087004, stat); } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } static int -nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv98_crypt_priv *priv; + struct g98_sec_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true, - "PCRYPT", "crypt", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x087000, true, + "PSEC", "sec", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00004000; - nv_subdev(priv)->intr = nv98_crypt_intr; - nv_engine(priv)->cclass = &nv98_crypt_cclass; - nv_engine(priv)->sclass = nv98_crypt_sclass; - nv_falcon(priv)->code.data = nv98_pcrypt_code; - nv_falcon(priv)->code.size = sizeof(nv98_pcrypt_code); - nv_falcon(priv)->data.data = nv98_pcrypt_data; - nv_falcon(priv)->data.size = sizeof(nv98_pcrypt_data); + nv_subdev(priv)->intr = g98_sec_intr; + nv_engine(priv)->cclass = &g98_sec_cclass; + nv_engine(priv)->sclass = g98_sec_sclass; + nv_falcon(priv)->code.data = g98_psec_code; + nv_falcon(priv)->code.size = sizeof(g98_psec_code); + nv_falcon(priv)->data.data = g98_psec_data; + nv_falcon(priv)->data.size = sizeof(g98_psec_data); return 0; } -struct nouveau_oclass -nv98_crypt_oclass = { - .handle = NV_ENGINE(CRYPT, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv98_crypt_ctor, - .dtor = _nouveau_falcon_dtor, - .init = _nouveau_falcon_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, +struct nvkm_oclass +g98_sec_oclass = { + .handle = NV_ENGINE(SEC, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g98_sec_ctor, + .dtor = _nvkm_falcon_dtor, + .init = _nvkm_falcon_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild new file mode 100644 index 000000000000..bdc3a05907d5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild @@ -0,0 +1,4 @@ +nvkm-y += nvkm/engine/sw/nv04.o +nvkm-y += nvkm/engine/sw/nv10.o +nvkm-y += nvkm/engine/sw/nv50.o +nvkm-y += nvkm/engine/sw/gf100.o diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c index 6af370d3a06d..533d5d8ed363 100644 --- a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c @@ -21,27 +21,19 @@ * * Authors: Ben Skeggs */ - -#include <core/os.h> -#include <core/engctx.h> -#include <core/event.h> +#include "nv50.h" #include <subdev/bar.h> -#include <engine/software.h> -#include <engine/disp.h> - -#include "nv50.h" - /******************************************************************************* * software object classes ******************************************************************************/ static int -nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +gf100_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); u64 data = *(u32 *)args; if (mthd == 0x0400) { chan->vblank.offset &= 0x00ffffffffULL; @@ -54,11 +46,11 @@ nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, } static int -nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); - struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); + struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; u32 data = *(u32 *)args; switch (mthd) { @@ -79,22 +71,22 @@ nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd, return 0; } -static struct nouveau_omthds -nvc0_software_omthds[] = { - { 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset }, - { 0x0404, 0x0404, nvc0_software_mthd_vblsem_offset }, - { 0x0408, 0x0408, nv50_software_mthd_vblsem_value }, - { 0x040c, 0x040c, nv50_software_mthd_vblsem_release }, - { 0x0500, 0x0500, nv50_software_mthd_flip }, - { 0x0600, 0x0600, nvc0_software_mthd_mp_control }, - { 0x0644, 0x0644, nvc0_software_mthd_mp_control }, - { 0x06ac, 0x06ac, nvc0_software_mthd_mp_control }, +static struct nvkm_omthds +gf100_sw_omthds[] = { + { 0x0400, 0x0400, gf100_sw_mthd_vblsem_offset }, + { 0x0404, 0x0404, gf100_sw_mthd_vblsem_offset }, + { 0x0408, 0x0408, nv50_sw_mthd_vblsem_value }, + { 0x040c, 0x040c, nv50_sw_mthd_vblsem_release }, + { 0x0500, 0x0500, nv50_sw_mthd_flip }, + { 0x0600, 0x0600, gf100_sw_mthd_mp_control }, + { 0x0644, 0x0644, gf100_sw_mthd_mp_control }, + { 0x06ac, 0x06ac, gf100_sw_mthd_mp_control }, {} }; -static struct nouveau_oclass -nvc0_software_sclass[] = { - { 0x906e, &nouveau_object_ofuncs, nvc0_software_omthds }, +static struct nvkm_oclass +gf100_sw_sclass[] = { + { 0x906e, &nvkm_object_ofuncs, gf100_sw_omthds }, {} }; @@ -103,12 +95,12 @@ nvc0_software_sclass[] = { ******************************************************************************/ static int -nvc0_software_vblsem_release(struct nvkm_notify *notify) +gf100_sw_vblsem_release(struct nvkm_notify *notify) { - struct nv50_software_chan *chan = + struct nv50_sw_chan *chan = container_of(notify, typeof(*chan), vblank.notify[notify->index]); - struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; - struct nouveau_bar *bar = nouveau_bar(priv); + struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; + struct nvkm_bar *bar = nvkm_bar(priv); nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); bar->flush(bar); @@ -119,31 +111,31 @@ nvc0_software_vblsem_release(struct nvkm_notify *notify) return NVKM_NOTIFY_DROP; } -static struct nv50_software_cclass -nvc0_software_cclass = { +static struct nv50_sw_cclass +gf100_sw_cclass = { .base.handle = NV_ENGCTX(SW, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_software_context_ctor, - .dtor = nv50_software_context_dtor, - .init = _nouveau_software_context_init, - .fini = _nouveau_software_context_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_sw_context_ctor, + .dtor = nv50_sw_context_dtor, + .init = _nvkm_sw_context_init, + .fini = _nvkm_sw_context_fini, }, - .vblank = nvc0_software_vblsem_release, + .vblank = gf100_sw_vblsem_release, }; /******************************************************************************* * software engine/subdev functions ******************************************************************************/ -struct nouveau_oclass * -nvc0_software_oclass = &(struct nv50_software_oclass) { +struct nvkm_oclass * +gf100_sw_oclass = &(struct nv50_sw_oclass) { .base.handle = NV_ENGINE(SW, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_software_ctor, - .dtor = _nouveau_software_dtor, - .init = _nouveau_software_init, - .fini = _nouveau_software_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_sw_ctor, + .dtor = _nvkm_sw_dtor, + .init = _nvkm_sw_init, + .fini = _nvkm_sw_fini, }, - .cclass = &nvc0_software_cclass.base, - .sclass = nvc0_software_sclass, + .cclass = &gf100_sw_cclass.base, + .sclass = gf100_sw_sclass, }.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c index 64df15c7f051..897024421d36 100644 --- a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c @@ -21,19 +21,15 @@ * * Authors: Ben Skeggs */ - -#include <core/os.h> -#include <core/engctx.h> - -#include <engine/software.h> +#include <engine/sw.h> #include <engine/fifo.h> -struct nv04_software_priv { - struct nouveau_software base; +struct nv04_sw_priv { + struct nvkm_sw base; }; -struct nv04_software_chan { - struct nouveau_software_chan base; +struct nv04_sw_chan { + struct nvkm_sw_chan base; }; /******************************************************************************* @@ -41,35 +37,33 @@ struct nv04_software_chan { ******************************************************************************/ static int -nv04_software_set_ref(struct nouveau_object *object, u32 mthd, - void *data, u32 size) +nv04_sw_set_ref(struct nvkm_object *object, u32 mthd, void *data, u32 size) { - struct nouveau_object *channel = (void *)nv_engctx(object->parent); - struct nouveau_fifo_chan *fifo = (void *)channel->parent; + struct nvkm_object *channel = (void *)nv_engctx(object->parent); + struct nvkm_fifo_chan *fifo = (void *)channel->parent; atomic_set(&fifo->refcnt, *(u32*)data); return 0; } static int -nv04_software_flip(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv04_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size) { - struct nv04_software_chan *chan = (void *)nv_engctx(object->parent); + struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent); if (chan->base.flip) return chan->base.flip(chan->base.flip_data); return -EINVAL; } -static struct nouveau_omthds -nv04_software_omthds[] = { - { 0x0150, 0x0150, nv04_software_set_ref }, - { 0x0500, 0x0500, nv04_software_flip }, +static struct nvkm_omthds +nv04_sw_omthds[] = { + { 0x0150, 0x0150, nv04_sw_set_ref }, + { 0x0500, 0x0500, nv04_sw_flip }, {} }; -static struct nouveau_oclass -nv04_software_sclass[] = { - { 0x006e, &nouveau_object_ofuncs, nv04_software_omthds }, +static struct nvkm_oclass +nv04_sw_sclass[] = { + { 0x006e, &nvkm_object_ofuncs, nv04_sw_omthds }, {} }; @@ -78,15 +72,14 @@ nv04_software_sclass[] = { ******************************************************************************/ static int -nv04_software_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv04_software_chan *chan; + struct nv04_sw_chan *chan; int ret; - ret = nouveau_software_context_create(parent, engine, oclass, &chan); + ret = nvkm_sw_context_create(parent, engine, oclass, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -94,14 +87,14 @@ nv04_software_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass -nv04_software_cclass = { +static struct nvkm_oclass +nv04_sw_cclass = { .handle = NV_ENGCTX(SW, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_software_context_ctor, - .dtor = _nouveau_software_context_dtor, - .init = _nouveau_software_context_init, - .fini = _nouveau_software_context_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv04_sw_context_ctor, + .dtor = _nvkm_sw_context_dtor, + .init = _nvkm_sw_context_init, + .fini = _nvkm_sw_context_fini, }, }; @@ -110,37 +103,37 @@ nv04_software_cclass = { ******************************************************************************/ void -nv04_software_intr(struct nouveau_subdev *subdev) +nv04_sw_intr(struct nvkm_subdev *subdev) { nv_mask(subdev, 0x000100, 0x80000000, 0x00000000); } static int -nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv04_software_priv *priv; + struct nv04_sw_priv *priv; int ret; - ret = nouveau_software_create(parent, engine, oclass, &priv); + ret = nvkm_sw_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; - nv_engine(priv)->cclass = &nv04_software_cclass; - nv_engine(priv)->sclass = nv04_software_sclass; - nv_subdev(priv)->intr = nv04_software_intr; + nv_engine(priv)->cclass = &nv04_sw_cclass; + nv_engine(priv)->sclass = nv04_sw_sclass; + nv_subdev(priv)->intr = nv04_sw_intr; return 0; } -struct nouveau_oclass * -nv04_software_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv04_sw_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(SW, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_software_ctor, - .dtor = _nouveau_software_dtor, - .init = _nouveau_software_init, - .fini = _nouveau_software_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv04_sw_ctor, + .dtor = _nvkm_sw_dtor, + .init = _nvkm_sw_init, + .fini = _nvkm_sw_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c index f54a2253deca..c61153a3fb8b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c @@ -21,18 +21,14 @@ * * Authors: Ben Skeggs */ +#include <engine/sw.h> -#include <core/os.h> -#include <core/engctx.h> - -#include <engine/software.h> - -struct nv10_software_priv { - struct nouveau_software base; +struct nv10_sw_priv { + struct nvkm_sw base; }; -struct nv10_software_chan { - struct nouveau_software_chan base; +struct nv10_sw_chan { + struct nvkm_sw_chan base; }; /******************************************************************************* @@ -40,24 +36,23 @@ struct nv10_software_chan { ******************************************************************************/ static int -nv10_software_flip(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv10_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size) { - struct nv10_software_chan *chan = (void *)nv_engctx(object->parent); + struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent); if (chan->base.flip) return chan->base.flip(chan->base.flip_data); return -EINVAL; } -static struct nouveau_omthds -nv10_software_omthds[] = { - { 0x0500, 0x0500, nv10_software_flip }, +static struct nvkm_omthds +nv10_sw_omthds[] = { + { 0x0500, 0x0500, nv10_sw_flip }, {} }; -static struct nouveau_oclass -nv10_software_sclass[] = { - { 0x016e, &nouveau_object_ofuncs, nv10_software_omthds }, +static struct nvkm_oclass +nv10_sw_sclass[] = { + { 0x016e, &nvkm_object_ofuncs, nv10_sw_omthds }, {} }; @@ -66,15 +61,14 @@ nv10_software_sclass[] = { ******************************************************************************/ static int -nv10_software_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv10_software_chan *chan; + struct nv10_sw_chan *chan; int ret; - ret = nouveau_software_context_create(parent, engine, oclass, &chan); + ret = nvkm_sw_context_create(parent, engine, oclass, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -82,14 +76,14 @@ nv10_software_context_ctor(struct nouveau_object *parent, return 0; } -static struct nouveau_oclass -nv10_software_cclass = { +static struct nvkm_oclass +nv10_sw_cclass = { .handle = NV_ENGCTX(SW, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv10_software_context_ctor, - .dtor = _nouveau_software_context_dtor, - .init = _nouveau_software_context_init, - .fini = _nouveau_software_context_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv10_sw_context_ctor, + .dtor = _nvkm_sw_context_dtor, + .init = _nvkm_sw_context_init, + .fini = _nvkm_sw_context_fini, }, }; @@ -98,31 +92,31 @@ nv10_software_cclass = { ******************************************************************************/ static int -nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv10_software_priv *priv; + struct nv10_sw_priv *priv; int ret; - ret = nouveau_software_create(parent, engine, oclass, &priv); + ret = nvkm_sw_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; - nv_engine(priv)->cclass = &nv10_software_cclass; - nv_engine(priv)->sclass = nv10_software_sclass; - nv_subdev(priv)->intr = nv04_software_intr; + nv_engine(priv)->cclass = &nv10_sw_cclass; + nv_engine(priv)->sclass = nv10_sw_sclass; + nv_subdev(priv)->intr = nv04_sw_intr; return 0; } -struct nouveau_oclass * -nv10_software_oclass = &(struct nouveau_oclass) { +struct nvkm_oclass * +nv10_sw_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(SW, 0x10), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv10_software_ctor, - .dtor = _nouveau_software_dtor, - .init = _nouveau_software_init, - .fini = _nouveau_software_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv10_sw_ctor, + .dtor = _nvkm_sw_dtor, + .init = _nvkm_sw_init, + .fini = _nvkm_sw_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index a0fec205f9db..401fcd73086b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -21,72 +21,67 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" -#include <core/os.h> -#include <core/engctx.h> -#include <core/namedb.h> +#include <core/device.h> #include <core/handle.h> -#include <core/gpuobj.h> -#include <core/event.h> -#include <nvif/event.h> - -#include <subdev/bar.h> - +#include <core/namedb.h> #include <engine/disp.h> +#include <subdev/bar.h> -#include "nv50.h" +#include <nvif/event.h> /******************************************************************************* * software object classes ******************************************************************************/ static int -nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); - struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent; - struct nouveau_handle *handle; + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); + struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)->parent; + struct nvkm_handle *handle; int ret = -EINVAL; - handle = nouveau_namedb_get(nv_namedb(fifo), *(u32 *)args); + handle = nvkm_namedb_get(nv_namedb(fifo), *(u32 *)args); if (!handle) return -ENOENT; if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { - struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object); + struct nvkm_gpuobj *gpuobj = nv_gpuobj(handle->object); chan->vblank.ctxdma = gpuobj->node->offset >> 4; ret = 0; } - nouveau_namedb_put(handle); + nvkm_namedb_put(handle); return ret; } static int -nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv50_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); chan->vblank.offset = *(u32 *)args; return 0; } int -nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv50_sw_mthd_vblsem_value(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); chan->vblank.value = *(u32 *)args; return 0; } int -nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv50_sw_mthd_vblsem_release(struct nvkm_object *object, u32 mthd, + void *args, u32 size) { - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); u32 head = *(u32 *)args; - if (head >= nouveau_disp(chan)->vblank.index_nr) + if (head >= nvkm_disp(chan)->vblank.index_nr) return -EINVAL; nvkm_notify_get(&chan->vblank.notify[head]); @@ -94,28 +89,27 @@ nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd, } int -nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd, - void *args, u32 size) +nv50_sw_mthd_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size) { - struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); + struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); if (chan->base.flip) return chan->base.flip(chan->base.flip_data); return -EINVAL; } -static struct nouveau_omthds -nv50_software_omthds[] = { - { 0x018c, 0x018c, nv50_software_mthd_dma_vblsem }, - { 0x0400, 0x0400, nv50_software_mthd_vblsem_offset }, - { 0x0404, 0x0404, nv50_software_mthd_vblsem_value }, - { 0x0408, 0x0408, nv50_software_mthd_vblsem_release }, - { 0x0500, 0x0500, nv50_software_mthd_flip }, +static struct nvkm_omthds +nv50_sw_omthds[] = { + { 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem }, + { 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset }, + { 0x0404, 0x0404, nv50_sw_mthd_vblsem_value }, + { 0x0408, 0x0408, nv50_sw_mthd_vblsem_release }, + { 0x0500, 0x0500, nv50_sw_mthd_flip }, {} }; -static struct nouveau_oclass -nv50_software_sclass[] = { - { 0x506e, &nouveau_object_ofuncs, nv50_software_omthds }, +static struct nvkm_oclass +nv50_sw_sclass[] = { + { 0x506e, &nvkm_object_ofuncs, nv50_sw_omthds }, {} }; @@ -124,12 +118,12 @@ nv50_software_sclass[] = { ******************************************************************************/ static int -nv50_software_vblsem_release(struct nvkm_notify *notify) +nv50_sw_vblsem_release(struct nvkm_notify *notify) { - struct nv50_software_chan *chan = + struct nv50_sw_chan *chan = container_of(notify, typeof(*chan), vblank.notify[notify->index]); - struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; - struct nouveau_bar *bar = nouveau_bar(priv); + struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; + struct nvkm_bar *bar = nvkm_bar(priv); nv_wr32(priv, 0x001704, chan->vblank.channel); nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); @@ -147,29 +141,28 @@ nv50_software_vblsem_release(struct nvkm_notify *notify) } void -nv50_software_context_dtor(struct nouveau_object *object) +nv50_sw_context_dtor(struct nvkm_object *object) { - struct nv50_software_chan *chan = (void *)object; + struct nv50_sw_chan *chan = (void *)object; int i; for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++) nvkm_notify_fini(&chan->vblank.notify[i]); - nouveau_software_context_destroy(&chan->base); + nvkm_sw_context_destroy(&chan->base); } int -nv50_software_context_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_disp *pdisp = nouveau_disp(parent); - struct nv50_software_cclass *pclass = (void *)oclass; - struct nv50_software_chan *chan; + struct nvkm_disp *pdisp = nvkm_disp(parent); + struct nv50_sw_cclass *pclass = (void *)oclass; + struct nv50_sw_chan *chan; int ret, i; - ret = nouveau_software_context_create(parent, engine, oclass, &chan); + ret = nvkm_sw_context_create(parent, engine, oclass, &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -191,16 +184,16 @@ nv50_software_context_ctor(struct nouveau_object *parent, return 0; } -static struct nv50_software_cclass -nv50_software_cclass = { +static struct nv50_sw_cclass +nv50_sw_cclass = { .base.handle = NV_ENGCTX(SW, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_software_context_ctor, - .dtor = nv50_software_context_dtor, - .init = _nouveau_software_context_init, - .fini = _nouveau_software_context_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_sw_context_ctor, + .dtor = nv50_sw_context_dtor, + .init = _nvkm_sw_context_init, + .fini = _nvkm_sw_context_fini, }, - .vblank = nv50_software_vblsem_release, + .vblank = nv50_sw_vblsem_release, }; /******************************************************************************* @@ -208,34 +201,34 @@ nv50_software_cclass = { ******************************************************************************/ int -nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv50_software_oclass *pclass = (void *)oclass; - struct nv50_software_priv *priv; + struct nv50_sw_oclass *pclass = (void *)oclass; + struct nv50_sw_priv *priv; int ret; - ret = nouveau_software_create(parent, engine, oclass, &priv); + ret = nvkm_sw_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_engine(priv)->cclass = pclass->cclass; nv_engine(priv)->sclass = pclass->sclass; - nv_subdev(priv)->intr = nv04_software_intr; + nv_subdev(priv)->intr = nv04_sw_intr; return 0; } -struct nouveau_oclass * -nv50_software_oclass = &(struct nv50_software_oclass) { +struct nvkm_oclass * +nv50_sw_oclass = &(struct nv50_sw_oclass) { .base.handle = NV_ENGINE(SW, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_software_ctor, - .dtor = _nouveau_software_dtor, - .init = _nouveau_software_init, - .fini = _nouveau_software_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_sw_ctor, + .dtor = _nvkm_sw_dtor, + .init = _nvkm_sw_init, + .fini = _nvkm_sw_fini, }, - .cclass = &nv50_software_cclass.base, - .sclass = nv50_software_sclass, + .cclass = &nv50_sw_cclass.base, + .sclass = nv50_sw_sclass, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h new file mode 100644 index 000000000000..d8adc1108467 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h @@ -0,0 +1,45 @@ +#ifndef __NVKM_SW_NV50_H__ +#define __NVKM_SW_NV50_H__ +#include <engine/sw.h> +#include <core/notify.h> + +struct nv50_sw_oclass { + struct nvkm_oclass base; + struct nvkm_oclass *cclass; + struct nvkm_oclass *sclass; +}; + +struct nv50_sw_priv { + struct nvkm_sw base; +}; + +int nv50_sw_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); + +struct nv50_sw_cclass { + struct nvkm_oclass base; + int (*vblank)(struct nvkm_notify *); +}; + +struct nv50_sw_chan { + struct nvkm_sw_chan base; + struct { + struct nvkm_notify notify[4]; + u32 channel; + u32 ctxdma; + u64 offset; + u32 value; + } vblank; +}; + +int nv50_sw_context_ctor(struct nvkm_object *, + struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nv50_sw_context_dtor(struct nvkm_object *); + +int nv50_sw_mthd_vblsem_value(struct nvkm_object *, u32, void *, u32); +int nv50_sw_mthd_vblsem_release(struct nvkm_object *, u32, void *, u32); +int nv50_sw_mthd_flip(struct nvkm_object *, u32, void *, u32); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild new file mode 100644 index 000000000000..6b390eb92b0e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild @@ -0,0 +1 @@ +nvkm-y += nvkm/engine/vp/g84.o diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c index fd6272b8cdb2..45f4e186befc 100644 --- a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c @@ -21,17 +21,18 @@ * * Authors: Ben Skeggs, Ilia Mirkin */ - -#include <engine/xtensa.h> #include <engine/vp.h> +#include <engine/xtensa.h> + +#include <core/engctx.h> /******************************************************************************* * VP object classes ******************************************************************************/ -static struct nouveau_oclass -nv84_vp_sclass[] = { - { 0x7476, &nouveau_object_ofuncs }, +static struct nvkm_oclass +g84_vp_sclass[] = { + { 0x7476, &nvkm_object_ofuncs }, {}, }; @@ -39,16 +40,16 @@ nv84_vp_sclass[] = { * PVP context ******************************************************************************/ -static struct nouveau_oclass -nv84_vp_cclass = { +static struct nvkm_oclass +g84_vp_cclass = { .handle = NV_ENGCTX(VP, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_xtensa_engctx_ctor, - .dtor = _nouveau_engctx_dtor, - .init = _nouveau_engctx_init, - .fini = _nouveau_engctx_fini, - .rd32 = _nouveau_engctx_rd32, - .wr32 = _nouveau_engctx_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_xtensa_engctx_ctor, + .dtor = _nvkm_engctx_dtor, + .init = _nvkm_engctx_init, + .fini = _nvkm_engctx_fini, + .rd32 = _nvkm_engctx_rd32, + .wr32 = _nvkm_engctx_wr32, }, }; @@ -57,36 +58,36 @@ nv84_vp_cclass = { ******************************************************************************/ static int -nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_vp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_xtensa *priv; + struct nvkm_xtensa *priv; int ret; - ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true, - "PVP", "vp", &priv); + ret = nvkm_xtensa_create(parent, engine, oclass, 0xf000, true, + "PVP", "vp", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x01020000; - nv_engine(priv)->cclass = &nv84_vp_cclass; - nv_engine(priv)->sclass = nv84_vp_sclass; + nv_engine(priv)->cclass = &g84_vp_cclass; + nv_engine(priv)->sclass = g84_vp_sclass; priv->fifo_val = 0x111; priv->unkd28 = 0x9c544; return 0; } -struct nouveau_oclass -nv84_vp_oclass = { +struct nvkm_oclass +g84_vp_oclass = { .handle = NV_ENGINE(VP, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_vp_ctor, - .dtor = _nouveau_xtensa_dtor, - .init = _nouveau_xtensa_init, - .fini = _nouveau_xtensa_fini, - .rd32 = _nouveau_xtensa_rd32, - .wr32 = _nouveau_xtensa_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_vp_ctor, + .dtor = _nvkm_xtensa_dtor, + .init = _nvkm_xtensa_init, + .fini = _nvkm_xtensa_fini, + .rd32 = _nvkm_xtensa_rd32, + .wr32 = _nvkm_xtensa_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c index 92384759d2f5..cea90df533d9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c @@ -19,43 +19,43 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ - #include <engine/xtensa.h> +#include <core/device.h> + +#include <core/engctx.h> u32 -_nouveau_xtensa_rd32(struct nouveau_object *object, u64 addr) +_nvkm_xtensa_rd32(struct nvkm_object *object, u64 addr) { - struct nouveau_xtensa *xtensa = (void *)object; + struct nvkm_xtensa *xtensa = (void *)object; return nv_rd32(xtensa, xtensa->addr + addr); } void -_nouveau_xtensa_wr32(struct nouveau_object *object, u64 addr, u32 data) +_nvkm_xtensa_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nouveau_xtensa *xtensa = (void *)object; + struct nvkm_xtensa *xtensa = (void *)object; nv_wr32(xtensa, xtensa->addr + addr, data); } int -_nouveau_xtensa_engctx_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +_nvkm_xtensa_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_engctx *engctx; + struct nvkm_engctx *engctx; int ret; - ret = nouveau_engctx_create(parent, engine, oclass, NULL, - 0x10000, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &engctx); + ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, &engctx); *pobject = nv_object(engctx); return ret; } void -_nouveau_xtensa_intr(struct nouveau_subdev *subdev) +_nvkm_xtensa_intr(struct nvkm_subdev *subdev) { - struct nouveau_xtensa *xtensa = (void *)subdev; + struct nvkm_xtensa *xtensa = (void *)subdev; u32 unk104 = nv_ro32(xtensa, 0xd04); u32 intr = nv_ro32(xtensa, 0xc20); u32 chan = nv_ro32(xtensa, 0xc28); @@ -72,39 +72,36 @@ _nouveau_xtensa_intr(struct nouveau_subdev *subdev) } int -nouveau_xtensa_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 addr, bool enable, - const char *iname, const char *fname, - int length, void **pobject) +nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 addr, bool enable, + const char *iname, const char *fname, + int length, void **pobject) { - struct nouveau_xtensa *xtensa; + struct nvkm_xtensa *xtensa; int ret; - ret = nouveau_engine_create_(parent, engine, oclass, enable, iname, - fname, length, pobject); + ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, + fname, length, pobject); xtensa = *pobject; if (ret) return ret; - nv_subdev(xtensa)->intr = _nouveau_xtensa_intr; - + nv_subdev(xtensa)->intr = _nvkm_xtensa_intr; xtensa->addr = addr; - return 0; } int -_nouveau_xtensa_init(struct nouveau_object *object) +_nvkm_xtensa_init(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); - struct nouveau_xtensa *xtensa = (void *)object; + struct nvkm_device *device = nv_device(object); + struct nvkm_xtensa *xtensa = (void *)object; const struct firmware *fw; char name[32]; int i, ret; u32 tmp; - ret = nouveau_engine_init(&xtensa->base); + ret = nvkm_engine_init(&xtensa->base); if (ret) return ret; @@ -124,8 +121,8 @@ _nouveau_xtensa_init(struct nouveau_object *object) return -EINVAL; } - ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0, - &xtensa->gpu_fw); + ret = nvkm_gpuobj_new(object, NULL, 0x40000, 0x1000, 0, + &xtensa->gpu_fw); if (ret) { release_firmware(fw); return ret; @@ -157,20 +154,19 @@ _nouveau_xtensa_init(struct nouveau_object *object) nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ - return 0; } int -_nouveau_xtensa_fini(struct nouveau_object *object, bool suspend) +_nvkm_xtensa_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_xtensa *xtensa = (void *)object; + struct nvkm_xtensa *xtensa = (void *)object; nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */ nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */ if (!suspend) - nouveau_gpuobj_ref(NULL, &xtensa->gpu_fw); + nvkm_gpuobj_ref(NULL, &xtensa->gpu_fw); - return nouveau_engine_fini(&xtensa->base, suspend); + return nvkm_engine_fini(&xtensa->base, suspend); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild new file mode 100644 index 000000000000..a1bb3e48739c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild @@ -0,0 +1,19 @@ +include $(src)/nvkm/subdev/bar/Kbuild +include $(src)/nvkm/subdev/bios/Kbuild +include $(src)/nvkm/subdev/bus/Kbuild +include $(src)/nvkm/subdev/clk/Kbuild +include $(src)/nvkm/subdev/devinit/Kbuild +include $(src)/nvkm/subdev/fb/Kbuild +include $(src)/nvkm/subdev/fuse/Kbuild +include $(src)/nvkm/subdev/gpio/Kbuild +include $(src)/nvkm/subdev/i2c/Kbuild +include $(src)/nvkm/subdev/ibus/Kbuild +include $(src)/nvkm/subdev/instmem/Kbuild +include $(src)/nvkm/subdev/ltc/Kbuild +include $(src)/nvkm/subdev/mc/Kbuild +include $(src)/nvkm/subdev/mmu/Kbuild +include $(src)/nvkm/subdev/mxm/Kbuild +include $(src)/nvkm/subdev/pmu/Kbuild +include $(src)/nvkm/subdev/therm/Kbuild +include $(src)/nvkm/subdev/timer/Kbuild +include $(src)/nvkm/subdev/volt/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild new file mode 100644 index 000000000000..1ab554a0b5e0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild @@ -0,0 +1,4 @@ +nvkm-y += nvkm/subdev/bar/base.o +nvkm-y += nvkm/subdev/bar/nv50.o +nvkm-y += nvkm/subdev/bar/gf100.o +nvkm-y += nvkm/subdev/bar/gk20a.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c new file mode 100644 index 000000000000..3502d00122ef --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -0,0 +1,144 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include <core/device.h> +#include <subdev/fb.h> +#include <subdev/mmu.h> + +struct nvkm_barobj { + struct nvkm_object base; + struct nvkm_vma vma; + void __iomem *iomem; +}; + +static int +nvkm_barobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_device(parent); + struct nvkm_bar *bar = nvkm_bar(device); + struct nvkm_mem *mem = data; + struct nvkm_barobj *barobj; + int ret; + + ret = nvkm_object_create(parent, engine, oclass, 0, &barobj); + *pobject = nv_object(barobj); + if (ret) + return ret; + + ret = bar->kmap(bar, mem, NV_MEM_ACCESS_RW, &barobj->vma); + if (ret) + return ret; + + barobj->iomem = ioremap(nv_device_resource_start(device, 3) + + (u32)barobj->vma.offset, mem->size << 12); + if (!barobj->iomem) { + nv_warn(bar, "PRAMIN ioremap failed\n"); + return -ENOMEM; + } + + return 0; +} + +static void +nvkm_barobj_dtor(struct nvkm_object *object) +{ + struct nvkm_bar *bar = nvkm_bar(object); + struct nvkm_barobj *barobj = (void *)object; + if (barobj->vma.node) { + if (barobj->iomem) + iounmap(barobj->iomem); + bar->unmap(bar, &barobj->vma); + } + nvkm_object_destroy(&barobj->base); +} + +static u32 +nvkm_barobj_rd32(struct nvkm_object *object, u64 addr) +{ + struct nvkm_barobj *barobj = (void *)object; + return ioread32_native(barobj->iomem + addr); +} + +static void +nvkm_barobj_wr32(struct nvkm_object *object, u64 addr, u32 data) +{ + struct nvkm_barobj *barobj = (void *)object; + iowrite32_native(data, barobj->iomem + addr); +} + +static struct nvkm_oclass +nvkm_barobj_oclass = { + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nvkm_barobj_ctor, + .dtor = nvkm_barobj_dtor, + .init = nvkm_object_init, + .fini = nvkm_object_fini, + .rd32 = nvkm_barobj_rd32, + .wr32 = nvkm_barobj_wr32, + }, +}; + +int +nvkm_bar_alloc(struct nvkm_bar *bar, struct nvkm_object *parent, + struct nvkm_mem *mem, struct nvkm_object **pobject) +{ + struct nvkm_object *gpuobj; + int ret = nvkm_object_ctor(parent, &parent->engine->subdev.object, + &nvkm_barobj_oclass, mem, 0, &gpuobj); + if (ret == 0) + *pobject = gpuobj; + return ret; +} + +int +nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) +{ + struct nvkm_bar *bar; + int ret; + + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL", + "bar", length, pobject); + bar = *pobject; + if (ret) + return ret; + + return 0; +} + +void +nvkm_bar_destroy(struct nvkm_bar *bar) +{ + nvkm_subdev_destroy(&bar->base); +} + +void +_nvkm_bar_dtor(struct nvkm_object *object) +{ + struct nvkm_bar *bar = (void *)object; + nvkm_bar_destroy(bar); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c new file mode 100644 index 000000000000..12a1aebd9a96 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -0,0 +1,219 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include <core/device.h> +#include <core/gpuobj.h> +#include <subdev/fb.h> +#include <subdev/mmu.h> + +struct gf100_bar_priv_vm { + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +struct gf100_bar_priv { + struct nvkm_bar base; + spinlock_t lock; + struct gf100_bar_priv_vm bar[2]; +}; + +static int +gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) +{ + struct gf100_bar_priv *priv = (void *)bar; + int ret; + + ret = nvkm_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma); + if (ret) + return ret; + + nvkm_vm_map(vma, mem); + return 0; +} + +static int +gf100_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) +{ + struct gf100_bar_priv *priv = (void *)bar; + int ret; + + ret = nvkm_vm_get(priv->bar[1].vm, mem->size << 12, + mem->page_shift, flags, vma); + if (ret) + return ret; + + nvkm_vm_map(vma, mem); + return 0; +} + +static void +gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) +{ + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); +} + +static int +gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm, + int bar_nr) +{ + struct nvkm_device *device = nv_device(&priv->base); + struct nvkm_vm *vm; + resource_size_t bar_len; + int ret; + + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, + &bar_vm->mem); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, + &bar_vm->pgd); + if (ret) + return ret; + + bar_len = nv_device_resource_len(device, bar_nr); + + ret = nvkm_vm_new(device, 0, bar_len, 0, &vm); + if (ret) + return ret; + + atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); + + /* + * Bootstrap page table lookup. + */ + if (bar_nr == 3) { + ret = nvkm_gpuobj_new(nv_object(priv), NULL, + (bar_len >> 12) * 8, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, + &vm->pgt[0].obj[0]); + vm->pgt[0].refcount[0] = 1; + if (ret) + return ret; + } + + ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd); + nvkm_vm_ref(NULL, &vm, NULL); + if (ret) + return ret; + + nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); + nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); + nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); + nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); + return 0; +} + +int +gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_device(parent); + struct gf100_bar_priv *priv; + bool has_bar3 = nv_device_resource_len(device, 3) != 0; + int ret; + + ret = nvkm_bar_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + /* BAR3 */ + if (has_bar3) { + ret = gf100_bar_ctor_vm(priv, &priv->bar[0], 3); + if (ret) + return ret; + } + + /* BAR1 */ + ret = gf100_bar_ctor_vm(priv, &priv->bar[1], 1); + if (ret) + return ret; + + if (has_bar3) { + priv->base.alloc = nvkm_bar_alloc; + priv->base.kmap = gf100_bar_kmap; + } + priv->base.umap = gf100_bar_umap; + priv->base.unmap = gf100_bar_unmap; + priv->base.flush = g84_bar_flush; + spin_lock_init(&priv->lock); + return 0; +} + +void +gf100_bar_dtor(struct nvkm_object *object) +{ + struct gf100_bar_priv *priv = (void *)object; + + nvkm_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd); + nvkm_gpuobj_ref(NULL, &priv->bar[1].pgd); + nvkm_gpuobj_ref(NULL, &priv->bar[1].mem); + + if (priv->bar[0].vm) { + nvkm_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]); + nvkm_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd); + } + nvkm_gpuobj_ref(NULL, &priv->bar[0].pgd); + nvkm_gpuobj_ref(NULL, &priv->bar[0].mem); + + nvkm_bar_destroy(&priv->base); +} + +int +gf100_bar_init(struct nvkm_object *object) +{ + struct gf100_bar_priv *priv = (void *)object; + int ret; + + ret = nvkm_bar_init(&priv->base); + if (ret) + return ret; + + nv_mask(priv, 0x000200, 0x00000100, 0x00000000); + nv_mask(priv, 0x000200, 0x00000100, 0x00000100); + + nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12); + if (priv->bar[0].mem) + nv_wr32(priv, 0x001714, + 0xc0000000 | priv->bar[0].mem->addr >> 12); + return 0; +} + +struct nvkm_oclass +gf100_bar_oclass = { + .handle = NV_SUBDEV(BAR, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_bar_ctor, + .dtor = gf100_bar_dtor, + .init = gf100_bar_init, + .fini = _nvkm_bar_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c index bf877af9d3bd..148f739a276e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c @@ -19,36 +19,32 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - -#include <subdev/bar.h> - #include "priv.h" int -gk20a_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk20a_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_bar *bar; + struct nvkm_bar *bar; int ret; - ret = nvc0_bar_ctor(parent, engine, oclass, data, size, pobject); + ret = gf100_bar_ctor(parent, engine, oclass, data, size, pobject); if (ret) return ret; - bar = (struct nouveau_bar *)*pobject; + bar = (struct nvkm_bar *)*pobject; bar->iomap_uncached = true; - return 0; } -struct nouveau_oclass +struct nvkm_oclass gk20a_bar_oclass = { .handle = NV_SUBDEV(BAR, 0xea), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk20a_bar_ctor, - .dtor = nvc0_bar_dtor, - .init = nvc0_bar_init, - .fini = _nouveau_bar_fini, + .dtor = gf100_bar_dtor, + .init = gf100_bar_init, + .fini = _nvkm_bar_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c index f748ba49dfc8..8548adb91dcc 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -21,66 +21,65 @@ * * Authors: Ben Skeggs */ +#include "priv.h" +#include <core/device.h> #include <core/gpuobj.h> - -#include <subdev/timer.h> #include <subdev/fb.h> -#include <subdev/vm.h> - -#include "priv.h" +#include <subdev/mmu.h> +#include <subdev/timer.h> struct nv50_bar_priv { - struct nouveau_bar base; + struct nvkm_bar base; spinlock_t lock; - struct nouveau_gpuobj *mem; - struct nouveau_gpuobj *pad; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *bar1_vm; - struct nouveau_gpuobj *bar1; - struct nouveau_vm *bar3_vm; - struct nouveau_gpuobj *bar3; + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pad; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *bar1_vm; + struct nvkm_gpuobj *bar1; + struct nvkm_vm *bar3_vm; + struct nvkm_gpuobj *bar3; }; static int -nv50_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem, - u32 flags, struct nouveau_vma *vma) +nv50_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) { struct nv50_bar_priv *priv = (void *)bar; int ret; - ret = nouveau_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma); + ret = nvkm_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma); if (ret) return ret; - nouveau_vm_map(vma, mem); + nvkm_vm_map(vma, mem); return 0; } static int -nv50_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem, - u32 flags, struct nouveau_vma *vma) +nv50_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) { struct nv50_bar_priv *priv = (void *)bar; int ret; - ret = nouveau_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma); + ret = nvkm_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma); if (ret) return ret; - nouveau_vm_map(vma, mem); + nvkm_vm_map(vma, mem); return 0; } static void -nv50_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma) +nv50_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) { - nouveau_vm_unmap(vma); - nouveau_vm_put(vma); + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); } static void -nv50_bar_flush(struct nouveau_bar *bar) +nv50_bar_flush(struct nvkm_bar *bar) { struct nv50_bar_priv *priv = (void *)bar; unsigned long flags; @@ -92,7 +91,7 @@ nv50_bar_flush(struct nouveau_bar *bar) } void -nv84_bar_flush(struct nouveau_bar *bar) +g84_bar_flush(struct nvkm_bar *bar) { struct nv50_bar_priv *priv = (void *)bar; unsigned long flags; @@ -104,36 +103,35 @@ nv84_bar_flush(struct nouveau_bar *bar) } static int -nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); - struct nouveau_object *heap; - struct nouveau_vm *vm; + struct nvkm_device *device = nv_device(parent); + struct nvkm_object *heap; + struct nvkm_vm *vm; struct nv50_bar_priv *priv; u64 start, limit; int ret; - ret = nouveau_bar_create(parent, engine, oclass, &priv); + ret = nvkm_bar_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, - NVOBJ_FLAG_HEAP, &priv->mem); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, + NVOBJ_FLAG_HEAP, &priv->mem); heap = nv_object(priv->mem); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), heap, - (device->chipset == 0x50) ? 0x1400 : 0x0200, - 0, 0, &priv->pad); + ret = nvkm_gpuobj_new(nv_object(priv), heap, + (device->chipset == 0x50) ? 0x1400 : 0x0200, + 0, 0, &priv->pad); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), heap, 0x4000, 0, - 0, &priv->pgd); + ret = nvkm_gpuobj_new(nv_object(priv), heap, 0x4000, 0, 0, &priv->pgd); if (ret) return ret; @@ -141,25 +139,25 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, start = 0x0100000000ULL; limit = start + nv_device_resource_len(device, 3); - ret = nouveau_vm_new(device, start, limit, start, &vm); + ret = nvkm_vm_new(device, start, limit, start, &vm); if (ret) return ret; atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); - ret = nouveau_gpuobj_new(nv_object(priv), heap, - ((limit-- - start) >> 12) * 8, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]); + ret = nvkm_gpuobj_new(nv_object(priv), heap, + ((limit-- - start) >> 12) * 8, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]); vm->pgt[0].refcount[0] = 1; if (ret) return ret; - ret = nouveau_vm_ref(vm, &priv->bar3_vm, priv->pgd); - nouveau_vm_ref(NULL, &vm, NULL); + ret = nvkm_vm_ref(vm, &priv->bar3_vm, priv->pgd); + nvkm_vm_ref(NULL, &vm, NULL); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3); + ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3); if (ret) return ret; @@ -175,18 +173,18 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, start = 0x0000000000ULL; limit = start + nv_device_resource_len(device, 1); - ret = nouveau_vm_new(device, start, limit--, start, &vm); + ret = nvkm_vm_new(device, start, limit--, start, &vm); if (ret) return ret; atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); - ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd); - nouveau_vm_ref(NULL, &vm, NULL); + ret = nvkm_vm_ref(vm, &priv->bar1_vm, priv->pgd); + nvkm_vm_ref(NULL, &vm, NULL); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1); + ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1); if (ret) return ret; @@ -198,42 +196,42 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_wo32(priv->bar1, 0x10, 0x00000000); nv_wo32(priv->bar1, 0x14, 0x00000000); - priv->base.alloc = nouveau_bar_alloc; + priv->base.alloc = nvkm_bar_alloc; priv->base.kmap = nv50_bar_kmap; priv->base.umap = nv50_bar_umap; priv->base.unmap = nv50_bar_unmap; if (device->chipset == 0x50) priv->base.flush = nv50_bar_flush; else - priv->base.flush = nv84_bar_flush; + priv->base.flush = g84_bar_flush; spin_lock_init(&priv->lock); return 0; } static void -nv50_bar_dtor(struct nouveau_object *object) +nv50_bar_dtor(struct nvkm_object *object) { struct nv50_bar_priv *priv = (void *)object; - nouveau_gpuobj_ref(NULL, &priv->bar1); - nouveau_vm_ref(NULL, &priv->bar1_vm, priv->pgd); - nouveau_gpuobj_ref(NULL, &priv->bar3); + nvkm_gpuobj_ref(NULL, &priv->bar1); + nvkm_vm_ref(NULL, &priv->bar1_vm, priv->pgd); + nvkm_gpuobj_ref(NULL, &priv->bar3); if (priv->bar3_vm) { - nouveau_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]); - nouveau_vm_ref(NULL, &priv->bar3_vm, priv->pgd); + nvkm_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]); + nvkm_vm_ref(NULL, &priv->bar3_vm, priv->pgd); } - nouveau_gpuobj_ref(NULL, &priv->pgd); - nouveau_gpuobj_ref(NULL, &priv->pad); - nouveau_gpuobj_ref(NULL, &priv->mem); - nouveau_bar_destroy(&priv->base); + nvkm_gpuobj_ref(NULL, &priv->pgd); + nvkm_gpuobj_ref(NULL, &priv->pad); + nvkm_gpuobj_ref(NULL, &priv->mem); + nvkm_bar_destroy(&priv->base); } static int -nv50_bar_init(struct nouveau_object *object) +nv50_bar_init(struct nvkm_object *object) { struct nv50_bar_priv *priv = (void *)object; int ret, i; - ret = nouveau_bar_init(&priv->base); + ret = nvkm_bar_init(&priv->base); if (ret) return ret; @@ -255,16 +253,16 @@ nv50_bar_init(struct nouveau_object *object) } static int -nv50_bar_fini(struct nouveau_object *object, bool suspend) +nv50_bar_fini(struct nvkm_object *object, bool suspend) { struct nv50_bar_priv *priv = (void *)object; - return nouveau_bar_fini(&priv->base, suspend); + return nvkm_bar_fini(&priv->base, suspend); } -struct nouveau_oclass +struct nvkm_oclass nv50_bar_oclass = { .handle = NV_SUBDEV(BAR, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_bar_ctor, .dtor = nv50_bar_dtor, .init = nv50_bar_init, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h new file mode 100644 index 000000000000..aa85f61b48c2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h @@ -0,0 +1,30 @@ +#ifndef __NVKM_BAR_PRIV_H__ +#define __NVKM_BAR_PRIV_H__ +#include <subdev/bar.h> + +#define nvkm_bar_create(p,e,o,d) \ + nvkm_bar_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_bar_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_bar_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +int nvkm_bar_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void nvkm_bar_destroy(struct nvkm_bar *); + +void _nvkm_bar_dtor(struct nvkm_object *); +#define _nvkm_bar_init _nvkm_subdev_init +#define _nvkm_bar_fini _nvkm_subdev_fini + +int nvkm_bar_alloc(struct nvkm_bar *, struct nvkm_object *, + struct nvkm_mem *, struct nvkm_object **); + +void g84_bar_flush(struct nvkm_bar *); + +int gf100_bar_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gf100_bar_dtor(struct nvkm_object *); +int gf100_bar_init(struct nvkm_object *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild new file mode 100644 index 000000000000..64730d5e9351 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild @@ -0,0 +1,37 @@ +nvkm-y += nvkm/subdev/bios/base.o +nvkm-y += nvkm/subdev/bios/bit.o +nvkm-y += nvkm/subdev/bios/boost.o +nvkm-y += nvkm/subdev/bios/conn.o +nvkm-y += nvkm/subdev/bios/cstep.o +nvkm-y += nvkm/subdev/bios/dcb.o +nvkm-y += nvkm/subdev/bios/disp.o +nvkm-y += nvkm/subdev/bios/dp.o +nvkm-y += nvkm/subdev/bios/extdev.o +nvkm-y += nvkm/subdev/bios/fan.o +nvkm-y += nvkm/subdev/bios/gpio.o +nvkm-y += nvkm/subdev/bios/i2c.o +nvkm-y += nvkm/subdev/bios/image.o +nvkm-y += nvkm/subdev/bios/init.o +nvkm-y += nvkm/subdev/bios/mxm.o +nvkm-y += nvkm/subdev/bios/npde.o +nvkm-y += nvkm/subdev/bios/pcir.o +nvkm-y += nvkm/subdev/bios/perf.o +nvkm-y += nvkm/subdev/bios/pll.o +nvkm-y += nvkm/subdev/bios/pmu.o +nvkm-y += nvkm/subdev/bios/ramcfg.o +nvkm-y += nvkm/subdev/bios/rammap.o +nvkm-y += nvkm/subdev/bios/shadow.o +nvkm-y += nvkm/subdev/bios/shadowacpi.o +nvkm-y += nvkm/subdev/bios/shadowof.o +nvkm-y += nvkm/subdev/bios/shadowpci.o +nvkm-y += nvkm/subdev/bios/shadowramin.o +nvkm-y += nvkm/subdev/bios/shadowrom.o +nvkm-y += nvkm/subdev/bios/timing.o +nvkm-y += nvkm/subdev/bios/therm.o +nvkm-y += nvkm/subdev/bios/vmap.o +nvkm-y += nvkm/subdev/bios/volt.o +nvkm-y += nvkm/subdev/bios/xpio.o +nvkm-y += nvkm/subdev/bios/M0203.o +nvkm-y += nvkm/subdev/bios/M0205.o +nvkm-y += nvkm/subdev/bios/M0209.o +nvkm-y += nvkm/subdev/bios/P0260.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0203.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.c index 28906b16d4e5..08eb03fbc203 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/M0203.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/M0203.h> u32 -nvbios_M0203Te(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +nvbios_M0203Te(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_M; u32 data = 0x00000000; @@ -53,7 +52,7 @@ nvbios_M0203Te(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u32 -nvbios_M0203Tp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +nvbios_M0203Tp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0203T *info) { u32 data = nvbios_M0203Te(bios, ver, hdr, cnt, len); @@ -70,7 +69,7 @@ nvbios_M0203Tp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, } u32 -nvbios_M0203Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) +nvbios_M0203Ee(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr) { u8 cnt, len; u32 data = nvbios_M0203Te(bios, ver, hdr, &cnt, &len); @@ -83,7 +82,7 @@ nvbios_M0203Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) } u32 -nvbios_M0203Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +nvbios_M0203Ep(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, struct nvbios_M0203E *info) { u32 data = nvbios_M0203Ee(bios, idx, ver, hdr); @@ -101,7 +100,7 @@ nvbios_M0203Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, } u32 -nvbios_M0203Em(struct nouveau_bios *bios, u8 ramcfg, u8 *ver, u8 *hdr, +nvbios_M0203Em(struct nvkm_bios *bios, u8 ramcfg, u8 *ver, u8 *hdr, struct nvbios_M0203E *info) { struct nvbios_M0203T M0203T; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.c index ac9617c5fc2a..e1a8ad5f3066 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/M0205.h> u32 -nvbios_M0205Te(struct nouveau_bios *bios, +nvbios_M0205Te(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_M; @@ -56,7 +55,7 @@ nvbios_M0205Te(struct nouveau_bios *bios, } u32 -nvbios_M0205Tp(struct nouveau_bios *bios, +nvbios_M0205Tp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz, struct nvbios_M0205T *info) { @@ -73,7 +72,7 @@ nvbios_M0205Tp(struct nouveau_bios *bios, } u32 -nvbios_M0205Ee(struct nouveau_bios *bios, int idx, +nvbios_M0205Ee(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; @@ -89,7 +88,7 @@ nvbios_M0205Ee(struct nouveau_bios *bios, int idx, } u32 -nvbios_M0205Ep(struct nouveau_bios *bios, int idx, +nvbios_M0205Ep(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0205E *info) { @@ -106,7 +105,7 @@ nvbios_M0205Ep(struct nouveau_bios *bios, int idx, } u32 -nvbios_M0205Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) +nvbios_M0205Se(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) { u8 cnt, len; @@ -120,7 +119,7 @@ nvbios_M0205Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) } u32 -nvbios_M0205Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr, +nvbios_M0205Sp(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr, struct nvbios_M0205S *info) { u32 data = nvbios_M0205Se(bios, ent, idx, ver, hdr); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c index b142a510e89f..3026920c3358 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/M0209.h> u32 -nvbios_M0209Te(struct nouveau_bios *bios, +nvbios_M0209Te(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_M; @@ -56,7 +55,7 @@ nvbios_M0209Te(struct nouveau_bios *bios, } u32 -nvbios_M0209Ee(struct nouveau_bios *bios, int idx, +nvbios_M0209Ee(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; @@ -72,9 +71,8 @@ nvbios_M0209Ee(struct nouveau_bios *bios, int idx, } u32 -nvbios_M0209Ep(struct nouveau_bios *bios, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_M0209E *info) +nvbios_M0209Ep(struct nvkm_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0209E *info) { u32 data = nvbios_M0209Ee(bios, idx, ver, hdr, cnt, len); memset(info, 0x00, sizeof(*info)); @@ -94,7 +92,7 @@ nvbios_M0209Ep(struct nouveau_bios *bios, int idx, } u32 -nvbios_M0209Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) +nvbios_M0209Se(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) { u8 cnt, len; @@ -108,7 +106,7 @@ nvbios_M0209Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) } u32 -nvbios_M0209Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr, +nvbios_M0209Sp(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr, struct nvbios_M0209S *info) { struct nvbios_M0209E M0209E; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.c index 199f4e5f7488..b72edcf849b6 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> -#include <subdev/bios/ramcfg.h> #include <subdev/bios/P0260.h> u32 -nvbios_P0260Te(struct nouveau_bios *bios, +nvbios_P0260Te(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz) { struct bit_entry bit_P; @@ -57,7 +55,7 @@ nvbios_P0260Te(struct nouveau_bios *bios, } u32 -nvbios_P0260Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +nvbios_P0260Ee(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { u8 hdr, cnt, xnr, xsz; u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, len, &xnr, &xsz); @@ -67,7 +65,7 @@ nvbios_P0260Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) } u32 -nvbios_P0260Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len, +nvbios_P0260Ep(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len, struct nvbios_P0260E *info) { u32 data = nvbios_P0260Ee(bios, idx, ver, len); @@ -83,7 +81,7 @@ nvbios_P0260Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len, } u32 -nvbios_P0260Xe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *xsz) +nvbios_P0260Xe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *xsz) { u8 hdr, cnt, len, xnr; u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, &len, &xnr, xsz); @@ -93,7 +91,7 @@ nvbios_P0260Xe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *xsz) } u32 -nvbios_P0260Xp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +nvbios_P0260Xp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, struct nvbios_P0260X *info) { u32 data = nvbios_P0260Xe(bios, idx, ver, hdr); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c index 7df3a273553d..8db204f92ed3 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c @@ -21,18 +21,12 @@ * * Authors: Ben Skeggs */ - -#include <core/object.h> -#include <core/device.h> -#include <core/subdev.h> -#include <core/option.h> +#include "priv.h" #include <subdev/bios.h> #include <subdev/bios/bmp.h> #include <subdev/bios/bit.h> -#include "priv.h" - u8 nvbios_checksum(const u8 *data, int size) { @@ -59,7 +53,7 @@ nvbios_findstr(const u8 *data, int size, const char *str, int len) } int -nvbios_extend(struct nouveau_bios *bios, u32 length) +nvbios_extend(struct nvkm_bios *bios, u32 length) { if (bios->size < length) { u8 *prev = bios->data; @@ -76,59 +70,58 @@ nvbios_extend(struct nouveau_bios *bios, u32 length) } static u8 -nouveau_bios_rd08(struct nouveau_object *object, u64 addr) +nvkm_bios_rd08(struct nvkm_object *object, u64 addr) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; return bios->data[addr]; } static u16 -nouveau_bios_rd16(struct nouveau_object *object, u64 addr) +nvkm_bios_rd16(struct nvkm_object *object, u64 addr) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; return get_unaligned_le16(&bios->data[addr]); } static u32 -nouveau_bios_rd32(struct nouveau_object *object, u64 addr) +nvkm_bios_rd32(struct nvkm_object *object, u64 addr) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; return get_unaligned_le32(&bios->data[addr]); } static void -nouveau_bios_wr08(struct nouveau_object *object, u64 addr, u8 data) +nvkm_bios_wr08(struct nvkm_object *object, u64 addr, u8 data) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; bios->data[addr] = data; } static void -nouveau_bios_wr16(struct nouveau_object *object, u64 addr, u16 data) +nvkm_bios_wr16(struct nvkm_object *object, u64 addr, u16 data) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; put_unaligned_le16(data, &bios->data[addr]); } static void -nouveau_bios_wr32(struct nouveau_object *object, u64 addr, u32 data) +nvkm_bios_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; put_unaligned_le32(data, &bios->data[addr]); } static int -nouveau_bios_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nvkm_bios_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_bios *bios; + struct nvkm_bios *bios; struct bit_entry bit_i; int ret; - ret = nouveau_subdev_create(parent, engine, oclass, 0, - "VBIOS", "bios", &bios); + ret = nvkm_subdev_create(parent, engine, oclass, 0, + "VBIOS", "bios", &bios); *pobject = nv_object(bios); if (ret) return ret; @@ -174,40 +167,40 @@ nouveau_bios_ctor(struct nouveau_object *parent, } static void -nouveau_bios_dtor(struct nouveau_object *object) +nvkm_bios_dtor(struct nvkm_object *object) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; kfree(bios->data); - nouveau_subdev_destroy(&bios->base); + nvkm_subdev_destroy(&bios->base); } static int -nouveau_bios_init(struct nouveau_object *object) +nvkm_bios_init(struct nvkm_object *object) { - struct nouveau_bios *bios = (void *)object; - return nouveau_subdev_init(&bios->base); + struct nvkm_bios *bios = (void *)object; + return nvkm_subdev_init(&bios->base); } static int -nouveau_bios_fini(struct nouveau_object *object, bool suspend) +nvkm_bios_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_bios *bios = (void *)object; - return nouveau_subdev_fini(&bios->base, suspend); + struct nvkm_bios *bios = (void *)object; + return nvkm_subdev_fini(&bios->base, suspend); } -struct nouveau_oclass -nouveau_bios_oclass = { +struct nvkm_oclass +nvkm_bios_oclass = { .handle = NV_SUBDEV(VBIOS, 0x00), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nouveau_bios_ctor, - .dtor = nouveau_bios_dtor, - .init = nouveau_bios_init, - .fini = nouveau_bios_fini, - .rd08 = nouveau_bios_rd08, - .rd16 = nouveau_bios_rd16, - .rd32 = nouveau_bios_rd32, - .wr08 = nouveau_bios_wr08, - .wr16 = nouveau_bios_wr16, - .wr32 = nouveau_bios_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nvkm_bios_ctor, + .dtor = nvkm_bios_dtor, + .init = nvkm_bios_init, + .fini = nvkm_bios_fini, + .rd08 = nvkm_bios_rd08, + .rd16 = nvkm_bios_rd16, + .rd32 = nvkm_bios_rd32, + .wr08 = nvkm_bios_wr08, + .wr16 = nvkm_bios_wr16, + .wr32 = nvkm_bios_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/bit.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.c index 1d03a3f2b2d2..eab540496cdf 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/bit.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.c @@ -21,14 +21,11 @@ * * Authors: Ben Skeggs */ - -#include "core/object.h" - -#include "subdev/bios.h" -#include "subdev/bios/bit.h" +#include <subdev/bios.h> +#include <subdev/bios/bit.h> int -bit_entry(struct nouveau_bios *bios, u8 id, struct bit_entry *bit) +bit_entry(struct nvkm_bios *bios, u8 id, struct bit_entry *bit) { if (likely(bios->bit_offset)) { u8 entries = nv_ro08(bios, bios->bit_offset + 10); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/boost.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c index c1835e591c44..12e958533f46 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/boost.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/boost.h> u16 -nvbios_boostTe(struct nouveau_bios *bios, +nvbios_boostTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_P; @@ -57,7 +56,7 @@ nvbios_boostTe(struct nouveau_bios *bios, } u16 -nvbios_boostEe(struct nouveau_bios *bios, int idx, +nvbios_boostEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; @@ -73,7 +72,7 @@ nvbios_boostEe(struct nouveau_bios *bios, int idx, } u16 -nvbios_boostEp(struct nouveau_bios *bios, int idx, +nvbios_boostEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info) { u16 data = nvbios_boostEe(bios, idx, ver, hdr, cnt, len); @@ -87,7 +86,7 @@ nvbios_boostEp(struct nouveau_bios *bios, int idx, } u16 -nvbios_boostEm(struct nouveau_bios *bios, u8 pstate, +nvbios_boostEm(struct nvkm_bios *bios, u8 pstate, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info) { u32 data, idx = 0; @@ -99,7 +98,7 @@ nvbios_boostEm(struct nouveau_bios *bios, u8 pstate, } u16 -nvbios_boostSe(struct nouveau_bios *bios, int idx, +nvbios_boostSe(struct nvkm_bios *bios, int idx, u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len) { if (data && idx < cnt) { @@ -111,7 +110,7 @@ nvbios_boostSe(struct nouveau_bios *bios, int idx, } u16 -nvbios_boostSp(struct nouveau_bios *bios, int idx, +nvbios_boostSp(struct nvkm_bios *bios, int idx, u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_boostS *info) { diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.c index 2ede3bcd96a1..706a1650a4f2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.c @@ -21,15 +21,12 @@ * * Authors: Ben Skeggs */ - -#include <core/device.h> - #include <subdev/bios.h> #include <subdev/bios/dcb.h> #include <subdev/bios/conn.h> u32 -nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +nvbios_connTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u32 dcb = dcb_table(bios, ver, hdr, cnt, len); if (dcb && *ver >= 0x30 && *hdr >= 0x16) { @@ -46,7 +43,7 @@ nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u32 -nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +nvbios_connTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_connT *info) { u32 data = nvbios_connTe(bios, ver, hdr, cnt, len); @@ -62,7 +59,7 @@ nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, } u32 -nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len) +nvbios_connEe(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len) { u8 hdr, cnt; u32 data = nvbios_connTe(bios, ver, &hdr, &cnt, len); @@ -72,7 +69,7 @@ nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len) } u32 -nvbios_connEp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len, +nvbios_connEp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, struct nvbios_connE *info) { u32 data = nvbios_connEe(bios, idx, ver, len); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c index d3b15327fbfd..16f7ad8a4f80 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/cstep.h> u16 -nvbios_cstepTe(struct nouveau_bios *bios, +nvbios_cstepTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz) { struct bit_entry bit_P; @@ -57,7 +56,7 @@ nvbios_cstepTe(struct nouveau_bios *bios, } u16 -nvbios_cstepEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) +nvbios_cstepEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr) { u8 cnt, len, xnr, xsz; u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz); @@ -70,7 +69,7 @@ nvbios_cstepEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) } u16 -nvbios_cstepEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +nvbios_cstepEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, struct nvbios_cstepE *info) { u16 data = nvbios_cstepEe(bios, idx, ver, hdr); @@ -83,7 +82,7 @@ nvbios_cstepEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, } u16 -nvbios_cstepEm(struct nouveau_bios *bios, u8 pstate, u8 *ver, u8 *hdr, +nvbios_cstepEm(struct nvkm_bios *bios, u8 pstate, u8 *ver, u8 *hdr, struct nvbios_cstepE *info) { u32 data, idx = 0; @@ -95,7 +94,7 @@ nvbios_cstepEm(struct nouveau_bios *bios, u8 pstate, u8 *ver, u8 *hdr, } u16 -nvbios_cstepXe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) +nvbios_cstepXe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr) { u8 cnt, len, xnr, xsz; u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz); @@ -108,7 +107,7 @@ nvbios_cstepXe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) } u16 -nvbios_cstepXp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +nvbios_cstepXp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, struct nvbios_cstepX *info) { u16 data = nvbios_cstepXe(bios, idx, ver, hdr); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c index 96099aff8b41..8d78140f9401 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c @@ -21,16 +21,15 @@ * * Authors: Ben Skeggs */ +#include <subdev/bios.h> +#include <subdev/bios/dcb.h> -#include "core/device.h" - -#include "subdev/bios.h" -#include "subdev/bios/dcb.h" +#include <core/device.h> u16 -dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +dcb_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { - struct nouveau_device *device = nv_device(bios); + struct nvkm_device *device = nv_device(bios); u16 dcb = 0x0000; if (device->card_type > NV_04) @@ -98,7 +97,7 @@ dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u16 -dcb_outp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len) +dcb_outp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len) { u8 hdr, cnt; u16 dcb = dcb_table(bios, ver, &hdr, &cnt, len); @@ -120,7 +119,7 @@ dcb_outp_hashm(struct dcb_output *outp) } u16 -dcb_outp_parse(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len, +dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, struct dcb_output *outp) { u16 dcb = dcb_outp(bios, idx, ver, len); @@ -194,7 +193,7 @@ dcb_outp_parse(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len, } u16 -dcb_outp_match(struct nouveau_bios *bios, u16 type, u16 mask, +dcb_outp_match(struct nvkm_bios *bios, u16 type, u16 mask, u8 *ver, u8 *len, struct dcb_output *outp) { u16 dcb, idx = 0; @@ -208,8 +207,8 @@ dcb_outp_match(struct nouveau_bios *bios, u16 type, u16 mask, } int -dcb_outp_foreach(struct nouveau_bios *bios, void *data, - int (*exec)(struct nouveau_bios *, void *, int, u16)) +dcb_outp_foreach(struct nvkm_bios *bios, void *data, + int (*exec)(struct nvkm_bios *, void *, int, u16)) { int ret, idx = -1; u8 ver, len; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/disp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c index 51f355599694..262c410b7ee2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/disp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/disp.h> u16 -nvbios_disp_table(struct nouveau_bios *bios, +nvbios_disp_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub) { struct bit_entry U; @@ -57,8 +56,7 @@ nvbios_disp_table(struct nouveau_bios *bios, } u16 -nvbios_disp_entry(struct nouveau_bios *bios, u8 idx, - u8 *ver, u8 *len, u8 *sub) +nvbios_disp_entry(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, u8 *sub) { u8 hdr, cnt; u16 data = nvbios_disp_table(bios, ver, &hdr, &cnt, len, sub); @@ -69,8 +67,7 @@ nvbios_disp_entry(struct nouveau_bios *bios, u8 idx, } u16 -nvbios_disp_parse(struct nouveau_bios *bios, u8 idx, - u8 *ver, u8 *len, u8 *sub, +nvbios_disp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, u8 *sub, struct nvbios_disp *info) { u16 data = nvbios_disp_entry(bios, idx, ver, len, sub); @@ -82,7 +79,7 @@ nvbios_disp_parse(struct nouveau_bios *bios, u8 idx, } u16 -nvbios_outp_entry(struct nouveau_bios *bios, u8 idx, +nvbios_outp_entry(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct nvbios_disp info; @@ -96,9 +93,8 @@ nvbios_outp_entry(struct nouveau_bios *bios, u8 idx, } u16 -nvbios_outp_parse(struct nouveau_bios *bios, u8 idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_outp *info) +nvbios_outp_parse(struct nvkm_bios *bios, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *info) { u16 data = nvbios_outp_entry(bios, idx, ver, hdr, cnt, len); if (data && *hdr >= 0x0a) { @@ -117,9 +113,8 @@ nvbios_outp_parse(struct nouveau_bios *bios, u8 idx, } u16 -nvbios_outp_match(struct nouveau_bios *bios, u16 type, u16 mask, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_outp *info) +nvbios_outp_match(struct nvkm_bios *bios, u16 type, u16 mask, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *info) { u16 data, idx = 0; while ((data = nvbios_outp_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) { @@ -132,7 +127,7 @@ nvbios_outp_match(struct nouveau_bios *bios, u16 type, u16 mask, } u16 -nvbios_ocfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx, +nvbios_ocfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { if (idx < *cnt) @@ -141,9 +136,8 @@ nvbios_ocfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx, } u16 -nvbios_ocfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ocfg *info) +nvbios_ocfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *info) { u16 data = nvbios_ocfg_entry(bios, outp, idx, ver, hdr, cnt, len); if (data) { @@ -155,9 +149,8 @@ nvbios_ocfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx, } u16 -nvbios_ocfg_match(struct nouveau_bios *bios, u16 outp, u16 type, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ocfg *info) +nvbios_ocfg_match(struct nvkm_bios *bios, u16 outp, u16 type, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *info) { u16 data, idx = 0; while ((data = nvbios_ocfg_parse(bios, outp, idx++, ver, hdr, cnt, len, info))) { @@ -168,7 +161,7 @@ nvbios_ocfg_match(struct nouveau_bios *bios, u16 outp, u16 type, } u16 -nvbios_oclk_match(struct nouveau_bios *bios, u16 cmp, u32 khz) +nvbios_oclk_match(struct nvkm_bios *bios, u16 cmp, u32 khz) { while (cmp) { if (khz / 10 >= nv_ro16(bios, cmp + 0x00)) diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c index cef53f81f12b..95970faae6c8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ - - -#include "subdev/bios.h" -#include "subdev/bios/bit.h" -#include "subdev/bios/dp.h" +#include <subdev/bios.h> +#include <subdev/bios/bit.h> +#include <subdev/bios/dp.h> static u16 -nvbios_dp_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +nvbios_dp_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry d; @@ -57,7 +55,7 @@ nvbios_dp_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } static u16 -nvbios_dpout_entry(struct nouveau_bios *bios, u8 idx, +nvbios_dpout_entry(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u16 data = nvbios_dp_table(bios, ver, hdr, cnt, len); @@ -86,7 +84,7 @@ nvbios_dpout_entry(struct nouveau_bios *bios, u8 idx, } u16 -nvbios_dpout_parse(struct nouveau_bios *bios, u8 idx, +nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpout *info) { @@ -128,7 +126,7 @@ nvbios_dpout_parse(struct nouveau_bios *bios, u8 idx, } u16 -nvbios_dpout_match(struct nouveau_bios *bios, u16 type, u16 mask, +nvbios_dpout_match(struct nvkm_bios *bios, u16 type, u16 mask, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpout *info) { @@ -143,7 +141,7 @@ nvbios_dpout_match(struct nouveau_bios *bios, u16 type, u16 mask, } static u16 -nvbios_dpcfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx, +nvbios_dpcfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { if (*ver >= 0x40) { @@ -160,7 +158,7 @@ nvbios_dpcfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx, } u16 -nvbios_dpcfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx, +nvbios_dpcfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *info) { @@ -190,7 +188,7 @@ nvbios_dpcfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx, } u16 -nvbios_dpcfg_match(struct nouveau_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe, +nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *info) { diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c index 49285d4f7ca5..a8503a1854c4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c @@ -21,13 +21,12 @@ * * Authors: Martin Peres */ - #include <subdev/bios.h> #include <subdev/bios/dcb.h> #include <subdev/bios/extdev.h> static u16 -extdev_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) +extdev_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) { u8 dcb_ver, dcb_hdr, dcb_cnt, dcb_len; u16 dcb, extdev = 0; @@ -44,12 +43,11 @@ extdev_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) *hdr = nv_ro08(bios, extdev + 1); *cnt = nv_ro08(bios, extdev + 2); *len = nv_ro08(bios, extdev + 3); - return extdev + *hdr; } static u16 -nvbios_extdev_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +nvbios_extdev_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { u8 hdr, cnt; u16 extdev = extdev_table(bios, ver, &hdr, len, &cnt); @@ -59,8 +57,8 @@ nvbios_extdev_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) } static void -extdev_parse_entry(struct nouveau_bios *bios, u16 offset, - struct nvbios_extdev_func *entry) +extdev_parse_entry(struct nvkm_bios *bios, u16 offset, + struct nvbios_extdev_func *entry) { entry->type = nv_ro08(bios, offset + 0); entry->addr = nv_ro08(bios, offset + 1); @@ -68,7 +66,7 @@ extdev_parse_entry(struct nouveau_bios *bios, u16 offset, } int -nvbios_extdev_parse(struct nouveau_bios *bios, int idx, +nvbios_extdev_parse(struct nvkm_bios *bios, int idx, struct nvbios_extdev_func *func) { u8 ver, len; @@ -78,12 +76,11 @@ nvbios_extdev_parse(struct nouveau_bios *bios, int idx, return -EINVAL; extdev_parse_entry(bios, entry, func); - return 0; } int -nvbios_extdev_find(struct nouveau_bios *bios, enum nvbios_extdev_type type, +nvbios_extdev_find(struct nvkm_bios *bios, enum nvbios_extdev_type type, struct nvbios_extdev_func *func) { u8 ver, len, i; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c index e419892240f5..8dba70d9d9a9 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c @@ -21,13 +21,12 @@ * * Authors: Martin Peres */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/fan.h> u16 -nvbios_fan_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +nvbios_fan_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_P; u16 fan = 0x0000; @@ -54,7 +53,7 @@ nvbios_fan_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u16 -nvbios_fan_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +nvbios_fan_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u16 data = nvbios_fan_table(bios, ver, hdr, cnt, len); @@ -64,7 +63,7 @@ nvbios_fan_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, } u16 -nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan) +nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan) { u8 ver, hdr, cnt, len; @@ -89,5 +88,6 @@ nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan) fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff; } + return data; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.c index 172a4f999990..8ce154d88f51 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.c @@ -21,14 +21,13 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/dcb.h> #include <subdev/bios/gpio.h> #include <subdev/bios/xpio.h> u16 -dcb_gpio_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +dcb_gpio_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u16 data = 0x0000; u16 dcb = dcb_table(bios, ver, hdr, cnt, len); @@ -59,7 +58,7 @@ dcb_gpio_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u16 -dcb_gpio_entry(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len) +dcb_gpio_entry(struct nvkm_bios *bios, int idx, int ent, u8 *ver, u8 *len) { u8 hdr, cnt, xver; /* use gpio version for xpio entry parsing */ u16 gpio; @@ -71,11 +70,12 @@ dcb_gpio_entry(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len) if (gpio && ent < cnt) return gpio + hdr + (ent * *len); + return 0x0000; } u16 -dcb_gpio_parse(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len, +dcb_gpio_parse(struct nvkm_bios *bios, int idx, int ent, u8 *ver, u8 *len, struct dcb_gpio_func *gpio) { u16 data = dcb_gpio_entry(bios, idx, ent, ver, len); @@ -116,7 +116,7 @@ dcb_gpio_parse(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len, } u16 -dcb_gpio_match(struct nouveau_bios *bios, int idx, u8 func, u8 line, +dcb_gpio_match(struct nvkm_bios *bios, int idx, u8 func, u8 line, u8 *ver, u8 *len, struct dcb_gpio_func *gpio) { u8 hdr, cnt, i = 0; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c index 282320ba9264..d1a89b2bd5c1 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ - - -#include "subdev/bios.h" -#include "subdev/bios/dcb.h" -#include "subdev/bios/i2c.h" +#include <subdev/bios.h> +#include <subdev/bios/dcb.h> +#include <subdev/bios/i2c.h> u16 -dcb_i2c_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +dcb_i2c_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u16 i2c = 0x0000; u16 dcb = dcb_table(bios, ver, hdr, cnt, len); @@ -60,7 +58,7 @@ dcb_i2c_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u16 -dcb_i2c_entry(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len) +dcb_i2c_entry(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len) { u8 hdr, cnt; u16 i2c = dcb_i2c_table(bios, ver, &hdr, &cnt, len); @@ -70,7 +68,7 @@ dcb_i2c_entry(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len) } int -dcb_i2c_parse(struct nouveau_bios *bios, u8 idx, struct dcb_i2c_entry *info) +dcb_i2c_parse(struct nvkm_bios *bios, u8 idx, struct dcb_i2c_entry *info) { u8 ver, len; u16 ent = dcb_i2c_entry(bios, idx, &ver, &len); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/image.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c index 373f9a564ac9..1815540a0e8b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/image.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c @@ -21,14 +21,13 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - #include <subdev/bios.h> #include <subdev/bios/image.h> #include <subdev/bios/pcir.h> #include <subdev/bios/npde.h> static bool -nvbios_imagen(struct nouveau_bios *bios, struct nvbios_image *image) +nvbios_imagen(struct nvkm_bios *bios, struct nvbios_image *image) { struct nvbios_pcirT pcir; struct nvbios_npdeT npde; @@ -66,7 +65,7 @@ nvbios_imagen(struct nouveau_bios *bios, struct nvbios_image *image) } bool -nvbios_image(struct nouveau_bios *bios, int idx, struct nvbios_image *image) +nvbios_image(struct nvkm_bios *bios, int idx, struct nvbios_image *image) { memset(image, 0x00, sizeof(*image)); do { diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index c6579ef32cd1..f67cdae1e90a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c @@ -1,19 +1,41 @@ -#include <core/engine.h> -#include <core/device.h> - +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ #include <subdev/bios.h> -#include <subdev/bios/bmp.h> #include <subdev/bios/bit.h> +#include <subdev/bios/bmp.h> #include <subdev/bios/conn.h> #include <subdev/bios/dcb.h> #include <subdev/bios/dp.h> #include <subdev/bios/gpio.h> #include <subdev/bios/init.h> #include <subdev/bios/ramcfg.h> + +#include <core/device.h> #include <subdev/devinit.h> +#include <subdev/gpio.h> #include <subdev/i2c.h> #include <subdev/vga.h> -#include <subdev/gpio.h> #define bioslog(lvl, fmt, args...) do { \ nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \ @@ -97,7 +119,7 @@ init_crtc(struct nvbios_init *init) static u8 init_conn(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; struct nvbios_connE connE; u8 ver, hdr; u32 conn; @@ -119,7 +141,7 @@ init_conn(struct nvbios_init *init) static inline u32 init_nvreg(struct nvbios_init *init, u32 reg) { - struct nouveau_devinit *devinit = nouveau_devinit(init->bios); + struct nvkm_devinit *devinit = nvkm_devinit(init->bios); /* C51 (at least) sometimes has the lower bits set which the VBIOS * interprets to mean that access needs to go through certain IO @@ -203,7 +225,7 @@ init_wrport(struct nvbios_init *init, u16 port, u8 value) static u8 init_rdvgai(struct nvbios_init *init, u16 port, u8 index) { - struct nouveau_subdev *subdev = init->subdev; + struct nvkm_subdev *subdev = init->subdev; if (init_exec(init)) { int head = init->crtc < 0 ? 0 : init->crtc; return nv_rdvgai(subdev, head, port, index); @@ -232,10 +254,10 @@ init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) } } -static struct nouveau_i2c_port * +static struct nvkm_i2c_port * init_i2c(struct nvbios_init *init, int index) { - struct nouveau_i2c *i2c = nouveau_i2c(init->bios); + struct nvkm_i2c *i2c = nvkm_i2c(init->bios); if (index == 0xff) { index = NV_I2C_DEFAULT(0); @@ -265,7 +287,7 @@ init_i2c(struct nvbios_init *init, int index) static int init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) { - struct nouveau_i2c_port *port = init_i2c(init, index); + struct nvkm_i2c_port *port = init_i2c(init, index); if (port && init_exec(init)) return nv_rdi2cr(port, addr, reg); return -ENODEV; @@ -274,7 +296,7 @@ init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) static int init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) { - struct nouveau_i2c_port *port = init_i2c(init, index); + struct nvkm_i2c_port *port = init_i2c(init, index); if (port && init_exec(init)) return nv_wri2cr(port, addr, reg, val); return -ENODEV; @@ -283,7 +305,7 @@ init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) static u8 init_rdauxr(struct nvbios_init *init, u32 addr) { - struct nouveau_i2c_port *port = init_i2c(init, -2); + struct nvkm_i2c_port *port = init_i2c(init, -2); u8 data; if (port && init_exec(init)) { @@ -299,7 +321,7 @@ init_rdauxr(struct nvbios_init *init, u32 addr) static int init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) { - struct nouveau_i2c_port *port = init_i2c(init, -2); + struct nvkm_i2c_port *port = init_i2c(init, -2); if (port && init_exec(init)) { int ret = nv_wraux(port, addr, &data, 1); if (ret) @@ -312,7 +334,7 @@ init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) static void init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) { - struct nouveau_devinit *devinit = nouveau_devinit(init->bios); + struct nvkm_devinit *devinit = nvkm_devinit(init->bios); if (devinit->pll_set && init_exec(init)) { int ret = devinit->pll_set(devinit, id, freq); if (ret) @@ -325,7 +347,7 @@ init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) *****************************************************************************/ static u16 -init_table(struct nouveau_bios *bios, u16 *len) +init_table(struct nvkm_bios *bios, u16 *len) { struct bit_entry bit_I; @@ -345,7 +367,7 @@ init_table(struct nouveau_bios *bios, u16 *len) static u16 init_table_(struct nvbios_init *init, u16 offset, const char *name) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 len, data = init_table(bios, &len); if (data) { if (len >= offset + 2) { @@ -375,7 +397,7 @@ init_table_(struct nvbios_init *init, u16 offset, const char *name) #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); static u16 -init_script(struct nouveau_bios *bios, int index) +init_script(struct nvkm_bios *bios, int index) { struct nvbios_init init = { .bios = bios }; u16 bmp_ver = bmp_version(bios), data; @@ -396,7 +418,7 @@ init_script(struct nouveau_bios *bios, int index) } static u16 -init_unknown_script(struct nouveau_bios *bios) +init_unknown_script(struct nvkm_bios *bios) { u16 len, data = init_table(bios, &len); if (data && len >= 16) @@ -429,7 +451,7 @@ init_ram_restrict(struct nvbios_init *init) static u8 init_xlat_(struct nvbios_init *init, u8 index, u8 offset) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 table = init_xlat_table(init); if (table) { u16 data = nv_ro16(bios, table + (index * 2)); @@ -447,7 +469,7 @@ init_xlat_(struct nvbios_init *init, u8 index, u8 offset) static bool init_condition_met(struct nvbios_init *init, u8 cond) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 table = init_condition_table(init); if (table) { u32 reg = nv_ro32(bios, table + (cond * 12) + 0); @@ -463,7 +485,7 @@ init_condition_met(struct nvbios_init *init, u8 cond) static bool init_io_condition_met(struct nvbios_init *init, u8 cond) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 table = init_io_condition_table(init); if (table) { u16 port = nv_ro16(bios, table + (cond * 5) + 0); @@ -480,7 +502,7 @@ init_io_condition_met(struct nvbios_init *init, u8 cond) static bool init_io_flag_condition_met(struct nvbios_init *init, u8 cond) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 table = init_io_flag_condition_table(init); if (table) { u16 port = nv_ro16(bios, table + (cond * 9) + 0); @@ -515,7 +537,6 @@ init_tmds_reg(struct nvbios_init *init, u8 tmds) * CR58 for CR57 = 0 to index a table of offsets to the basic * 0x6808b0 address, and then flip the offset by 8. */ - const int pramdac_offset[13] = { 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; const u32 pramdac_table[4] = { @@ -589,7 +610,7 @@ init_done(struct nvbios_init *init) static void init_io_restrict_prog(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 port = nv_ro16(bios, init->offset + 1); u8 index = nv_ro08(bios, init->offset + 3); u8 mask = nv_ro08(bios, init->offset + 4); @@ -626,7 +647,7 @@ init_io_restrict_prog(struct nvbios_init *init) static void init_repeat(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 count = nv_ro08(bios, init->offset + 1); u16 repeat = init->repeat; @@ -652,7 +673,7 @@ init_repeat(struct nvbios_init *init) static void init_io_restrict_pll(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 port = nv_ro16(bios, init->offset + 1); u8 index = nv_ro08(bios, init->offset + 3); u8 mask = nv_ro08(bios, init->offset + 4); @@ -708,7 +729,7 @@ init_end_repeat(struct nvbios_init *init) static void init_copy(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 reg = nv_ro32(bios, init->offset + 1); u8 shift = nv_ro08(bios, init->offset + 5); u8 smask = nv_ro08(bios, init->offset + 6); @@ -747,7 +768,7 @@ init_not(struct nvbios_init *init) static void init_io_flag_condition(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 cond = nv_ro08(bios, init->offset + 1); trace("IO_FLAG_CONDITION\t0x%02x\n", cond); @@ -764,7 +785,7 @@ init_io_flag_condition(struct nvbios_init *init) static void init_dp_condition(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; struct nvbios_dpout info; u8 cond = nv_ro08(bios, init->offset + 1); u8 unkn = nv_ro08(bios, init->offset + 2); @@ -812,7 +833,7 @@ init_dp_condition(struct nvbios_init *init) static void init_io_mask_or(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 index = nv_ro08(bios, init->offset + 1); u8 or = init_or(init); u8 data; @@ -831,7 +852,7 @@ init_io_mask_or(struct nvbios_init *init) static void init_io_or(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 index = nv_ro08(bios, init->offset + 1); u8 or = init_or(init); u8 data; @@ -850,7 +871,7 @@ init_io_or(struct nvbios_init *init) static void init_andn_reg(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 reg = nv_ro32(bios, init->offset + 1); u32 mask = nv_ro32(bios, init->offset + 5); @@ -867,7 +888,7 @@ init_andn_reg(struct nvbios_init *init) static void init_or_reg(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 reg = nv_ro32(bios, init->offset + 1); u32 mask = nv_ro32(bios, init->offset + 5); @@ -884,7 +905,7 @@ init_or_reg(struct nvbios_init *init) static void init_idx_addr_latched(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 creg = nv_ro32(bios, init->offset + 1); u32 dreg = nv_ro32(bios, init->offset + 5); u32 mask = nv_ro32(bios, init->offset + 9); @@ -914,7 +935,7 @@ init_idx_addr_latched(struct nvbios_init *init) static void init_io_restrict_pll2(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 port = nv_ro16(bios, init->offset + 1); u8 index = nv_ro08(bios, init->offset + 3); u8 mask = nv_ro08(bios, init->offset + 4); @@ -949,7 +970,7 @@ init_io_restrict_pll2(struct nvbios_init *init) static void init_pll2(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 reg = nv_ro32(bios, init->offset + 1); u32 freq = nv_ro32(bios, init->offset + 5); @@ -966,7 +987,7 @@ init_pll2(struct nvbios_init *init) static void init_i2c_byte(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 index = nv_ro08(bios, init->offset + 1); u8 addr = nv_ro08(bios, init->offset + 2) >> 1; u8 count = nv_ro08(bios, init->offset + 3); @@ -997,7 +1018,7 @@ init_i2c_byte(struct nvbios_init *init) static void init_zm_i2c_byte(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 index = nv_ro08(bios, init->offset + 1); u8 addr = nv_ro08(bios, init->offset + 2) >> 1; u8 count = nv_ro08(bios, init->offset + 3); @@ -1014,7 +1035,6 @@ init_zm_i2c_byte(struct nvbios_init *init) init_wri2cr(init, index, addr, reg, data); } - } /** @@ -1024,7 +1044,7 @@ init_zm_i2c_byte(struct nvbios_init *init) static void init_zm_i2c(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 index = nv_ro08(bios, init->offset + 1); u8 addr = nv_ro08(bios, init->offset + 2) >> 1; u8 count = nv_ro08(bios, init->offset + 3); @@ -1040,7 +1060,7 @@ init_zm_i2c(struct nvbios_init *init) } if (init_exec(init)) { - struct nouveau_i2c_port *port = init_i2c(init, index); + struct nvkm_i2c_port *port = init_i2c(init, index); struct i2c_msg msg = { .addr = addr, .flags = 0, .len = count, .buf = data, }; @@ -1058,7 +1078,7 @@ init_zm_i2c(struct nvbios_init *init) static void init_tmds(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 tmds = nv_ro08(bios, init->offset + 1); u8 addr = nv_ro08(bios, init->offset + 2); u8 mask = nv_ro08(bios, init->offset + 3); @@ -1084,7 +1104,7 @@ init_tmds(struct nvbios_init *init) static void init_zm_tmds_group(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 tmds = nv_ro08(bios, init->offset + 1); u8 count = nv_ro08(bios, init->offset + 2); u32 reg = init_tmds_reg(init, tmds); @@ -1111,7 +1131,7 @@ init_zm_tmds_group(struct nvbios_init *init) static void init_cr_idx_adr_latch(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 addr0 = nv_ro08(bios, init->offset + 1); u8 addr1 = nv_ro08(bios, init->offset + 2); u8 base = nv_ro08(bios, init->offset + 3); @@ -1141,7 +1161,7 @@ init_cr_idx_adr_latch(struct nvbios_init *init) static void init_cr(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 addr = nv_ro08(bios, init->offset + 1); u8 mask = nv_ro08(bios, init->offset + 2); u8 data = nv_ro08(bios, init->offset + 3); @@ -1161,7 +1181,7 @@ init_cr(struct nvbios_init *init) static void init_zm_cr(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 addr = nv_ro08(bios, init->offset + 1); u8 data = nv_ro08(bios, init->offset + 2); @@ -1178,7 +1198,7 @@ init_zm_cr(struct nvbios_init *init) static void init_zm_cr_group(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 count = nv_ro08(bios, init->offset + 1); trace("ZM_CR_GROUP\n"); @@ -1202,7 +1222,7 @@ init_zm_cr_group(struct nvbios_init *init) static void init_condition_time(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 cond = nv_ro08(bios, init->offset + 1); u8 retry = nv_ro08(bios, init->offset + 2); u8 wait = min((u16)retry * 50, 100); @@ -1229,7 +1249,7 @@ init_condition_time(struct nvbios_init *init) static void init_ltime(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 msec = nv_ro16(bios, init->offset + 1); trace("LTIME\t0x%04x\n", msec); @@ -1246,7 +1266,7 @@ init_ltime(struct nvbios_init *init) static void init_zm_reg_sequence(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 base = nv_ro32(bios, init->offset + 1); u8 count = nv_ro08(bios, init->offset + 5); @@ -1271,7 +1291,7 @@ init_zm_reg_sequence(struct nvbios_init *init) static void init_sub_direct(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 addr = nv_ro16(bios, init->offset + 1); u16 save; @@ -1297,7 +1317,7 @@ init_sub_direct(struct nvbios_init *init) static void init_jump(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 offset = nv_ro16(bios, init->offset + 1); trace("JUMP\t0x%04x\n", offset); @@ -1315,7 +1335,7 @@ init_jump(struct nvbios_init *init) static void init_i2c_if(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 index = nv_ro08(bios, init->offset + 1); u8 addr = nv_ro08(bios, init->offset + 2); u8 reg = nv_ro08(bios, init->offset + 3); @@ -1342,7 +1362,7 @@ init_i2c_if(struct nvbios_init *init) static void init_copy_nv_reg(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 sreg = nv_ro32(bios, init->offset + 1); u8 shift = nv_ro08(bios, init->offset + 5); u32 smask = nv_ro32(bios, init->offset + 6); @@ -1368,7 +1388,7 @@ init_copy_nv_reg(struct nvbios_init *init) static void init_zm_index_io(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 port = nv_ro16(bios, init->offset + 1); u8 index = nv_ro08(bios, init->offset + 3); u8 data = nv_ro08(bios, init->offset + 4); @@ -1386,7 +1406,7 @@ init_zm_index_io(struct nvbios_init *init) static void init_compute_mem(struct nvbios_init *init) { - struct nouveau_devinit *devinit = nouveau_devinit(init->bios); + struct nvkm_devinit *devinit = nvkm_devinit(init->bios); trace("COMPUTE_MEM\n"); init->offset += 1; @@ -1404,7 +1424,7 @@ init_compute_mem(struct nvbios_init *init) static void init_reset(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 reg = nv_ro32(bios, init->offset + 1); u32 data1 = nv_ro32(bios, init->offset + 5); u32 data2 = nv_ro32(bios, init->offset + 9); @@ -1440,7 +1460,7 @@ init_configure_mem_clk(struct nvbios_init *init) static void init_configure_mem(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 mdata, sdata; u32 addr, data; @@ -1490,7 +1510,7 @@ init_configure_mem(struct nvbios_init *init) static void init_configure_clk(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 mdata, clock; trace("CONFIGURE_CLK\n"); @@ -1524,7 +1544,7 @@ init_configure_clk(struct nvbios_init *init) static void init_configure_preinit(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 strap; trace("CONFIGURE_PREINIT\n"); @@ -1550,7 +1570,7 @@ init_configure_preinit(struct nvbios_init *init) static void init_io(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 port = nv_ro16(bios, init->offset + 1); u8 mask = nv_ro16(bios, init->offset + 3); u8 data = nv_ro16(bios, init->offset + 4); @@ -1590,7 +1610,7 @@ init_io(struct nvbios_init *init) static void init_sub(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 index = nv_ro08(bios, init->offset + 1); u16 addr, save; @@ -1617,7 +1637,7 @@ init_sub(struct nvbios_init *init) static void init_ram_condition(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 mask = nv_ro08(bios, init->offset + 1); u8 value = nv_ro08(bios, init->offset + 2); @@ -1636,7 +1656,7 @@ init_ram_condition(struct nvbios_init *init) static void init_nv_reg(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 reg = nv_ro32(bios, init->offset + 1); u32 mask = nv_ro32(bios, init->offset + 5); u32 data = nv_ro32(bios, init->offset + 9); @@ -1654,7 +1674,7 @@ init_nv_reg(struct nvbios_init *init) static void init_macro(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 macro = nv_ro08(bios, init->offset + 1); u16 table; @@ -1690,7 +1710,7 @@ init_resume(struct nvbios_init *init) static void init_time(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 usec = nv_ro16(bios, init->offset + 1); trace("TIME\t0x%04x\n", usec); @@ -1711,7 +1731,7 @@ init_time(struct nvbios_init *init) static void init_condition(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 cond = nv_ro08(bios, init->offset + 1); trace("CONDITION\t0x%02x\n", cond); @@ -1728,7 +1748,7 @@ init_condition(struct nvbios_init *init) static void init_io_condition(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 cond = nv_ro08(bios, init->offset + 1); trace("IO_CONDITION\t0x%02x\n", cond); @@ -1745,7 +1765,7 @@ init_io_condition(struct nvbios_init *init) static void init_index_io(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u16 port = nv_ro16(bios, init->offset + 1); u8 index = nv_ro16(bios, init->offset + 3); u8 mask = nv_ro08(bios, init->offset + 4); @@ -1767,7 +1787,7 @@ init_index_io(struct nvbios_init *init) static void init_pll(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 reg = nv_ro32(bios, init->offset + 1); u32 freq = nv_ro16(bios, init->offset + 5) * 10; @@ -1784,7 +1804,7 @@ init_pll(struct nvbios_init *init) static void init_zm_reg(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 addr = nv_ro32(bios, init->offset + 1); u32 data = nv_ro32(bios, init->offset + 5); @@ -1804,7 +1824,7 @@ init_zm_reg(struct nvbios_init *init) static void init_ram_restrict_pll(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 type = nv_ro08(bios, init->offset + 1); u8 count = init_ram_restrict_group_count(init); u8 strap = init_ram_restrict(init); @@ -1834,7 +1854,7 @@ init_ram_restrict_pll(struct nvbios_init *init) static void init_gpio(struct nvbios_init *init) { - struct nouveau_gpio *gpio = nouveau_gpio(init->bios); + struct nvkm_gpio *gpio = nvkm_gpio(init->bios); trace("GPIO\n"); init->offset += 1; @@ -1850,7 +1870,7 @@ init_gpio(struct nvbios_init *init) static void init_ram_restrict_zm_reg_group(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 addr = nv_ro32(bios, init->offset + 1); u8 incr = nv_ro08(bios, init->offset + 5); u8 num = nv_ro08(bios, init->offset + 6); @@ -1888,7 +1908,7 @@ init_ram_restrict_zm_reg_group(struct nvbios_init *init) static void init_copy_zm_reg(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 sreg = nv_ro32(bios, init->offset + 1); u32 dreg = nv_ro32(bios, init->offset + 5); @@ -1905,7 +1925,7 @@ init_copy_zm_reg(struct nvbios_init *init) static void init_zm_reg_group(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 addr = nv_ro32(bios, init->offset + 1); u8 count = nv_ro08(bios, init->offset + 5); @@ -1927,7 +1947,7 @@ init_zm_reg_group(struct nvbios_init *init) static void init_xlat(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 saddr = nv_ro32(bios, init->offset + 1); u8 sshift = nv_ro08(bios, init->offset + 5); u8 smask = nv_ro08(bios, init->offset + 6); @@ -1955,7 +1975,7 @@ init_xlat(struct nvbios_init *init) static void init_zm_mask_add(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 addr = nv_ro32(bios, init->offset + 1); u32 mask = nv_ro32(bios, init->offset + 5); u32 add = nv_ro32(bios, init->offset + 9); @@ -1976,7 +1996,7 @@ init_zm_mask_add(struct nvbios_init *init) static void init_auxch(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 addr = nv_ro32(bios, init->offset + 1); u8 count = nv_ro08(bios, init->offset + 5); @@ -2000,7 +2020,7 @@ init_auxch(struct nvbios_init *init) static void init_zm_auxch(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u32 addr = nv_ro32(bios, init->offset + 1); u8 count = nv_ro08(bios, init->offset + 5); @@ -2022,14 +2042,14 @@ init_zm_auxch(struct nvbios_init *init) static void init_i2c_long_if(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; + struct nvkm_bios *bios = init->bios; u8 index = nv_ro08(bios, init->offset + 1); u8 addr = nv_ro08(bios, init->offset + 2) >> 1; u8 reglo = nv_ro08(bios, init->offset + 3); u8 reghi = nv_ro08(bios, init->offset + 4); u8 mask = nv_ro08(bios, init->offset + 5); u8 data = nv_ro08(bios, init->offset + 6); - struct nouveau_i2c_port *port; + struct nvkm_i2c_port *port; trace("I2C_LONG_IF\t" "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", @@ -2061,8 +2081,8 @@ init_i2c_long_if(struct nvbios_init *init) static void init_gpio_ne(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; - struct nouveau_gpio *gpio = nouveau_gpio(bios); + struct nvkm_bios *bios = init->bios; + struct nvkm_gpio *gpio = nvkm_gpio(bios); struct dcb_gpio_func func; u8 count = nv_ro08(bios, init->offset + 1); u8 idx = 0, ver, len; @@ -2185,9 +2205,9 @@ nvbios_exec(struct nvbios_init *init) } int -nvbios_init(struct nouveau_subdev *subdev, bool execute) +nvbios_init(struct nvkm_subdev *subdev, bool execute) { - struct nouveau_bios *bios = nouveau_bios(subdev); + struct nvkm_bios *bios = nvkm_bios(subdev); int ret = 0; int i = -1; u16 data; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c index 2610b11a99b3..c4087df4f85e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/mxm.h> u16 -mxm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr) +mxm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr) { struct bit_entry x; @@ -51,28 +50,28 @@ mxm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr) * * MXM v3.x VBIOS are nicer and provide pointers to these tables. */ -static u8 nv84_sor_map[16] = { +static u8 g84_sor_map[16] = { 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static u8 nv92_sor_map[16] = { +static u8 g92_sor_map[16] = { 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31, 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static u8 nv94_sor_map[16] = { +static u8 g94_sor_map[16] = { 0x00, 0x14, 0x24, 0x11, 0x34, 0x31, 0x11, 0x31, 0x11, 0x31, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static u8 nv98_sor_map[16] = { +static u8 g98_sor_map[16] = { 0x00, 0x14, 0x12, 0x11, 0x00, 0x31, 0x11, 0x31, 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; u8 -mxm_sor_map(struct nouveau_bios *bios, u8 conn) +mxm_sor_map(struct nvkm_bios *bios, u8 conn) { u8 ver, hdr; u16 mxm = mxm_table(bios, &ver, &hdr); @@ -95,20 +94,20 @@ mxm_sor_map(struct nouveau_bios *bios, u8 conn) } if (bios->version.chip == 0x84 || bios->version.chip == 0x86) - return nv84_sor_map[conn]; + return g84_sor_map[conn]; if (bios->version.chip == 0x92) - return nv92_sor_map[conn]; + return g92_sor_map[conn]; if (bios->version.chip == 0x94 || bios->version.chip == 0x96) - return nv94_sor_map[conn]; + return g94_sor_map[conn]; if (bios->version.chip == 0x98) - return nv98_sor_map[conn]; + return g98_sor_map[conn]; nv_warn(bios, "missing sor map\n"); return 0x00; } u8 -mxm_ddc_map(struct nouveau_bios *bios, u8 port) +mxm_ddc_map(struct nvkm_bios *bios, u8 port) { u8 ver, hdr; u16 mxm = mxm_table(bios, &ver, &hdr); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/npde.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c index d694716a166c..fd7dd718b2bf 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/npde.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - #include <subdev/bios.h> #include <subdev/bios/npde.h> #include <subdev/bios/pcir.h> u32 -nvbios_npdeTe(struct nouveau_bios *bios, u32 base) +nvbios_npdeTe(struct nvkm_bios *bios, u32 base) { struct nvbios_pcirT pcir; u8 ver; u16 hdr; @@ -47,7 +46,7 @@ nvbios_npdeTe(struct nouveau_bios *bios, u32 base) } u32 -nvbios_npdeTp(struct nouveau_bios *bios, u32 base, struct nvbios_npdeT *info) +nvbios_npdeTp(struct nvkm_bios *bios, u32 base, struct nvbios_npdeT *info) { u32 data = nvbios_npdeTe(bios, base); memset(info, 0x00, sizeof(*info)); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pcir.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c index 91dae26bc50f..df5978753ae8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/pcir.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c @@ -21,12 +21,11 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - #include <subdev/bios.h> #include <subdev/bios/pcir.h> u32 -nvbios_pcirTe(struct nouveau_bios *bios, u32 base, u8 *ver, u16 *hdr) +nvbios_pcirTe(struct nvkm_bios *bios, u32 base, u8 *ver, u16 *hdr) { u32 data = nv_ro16(bios, base + 0x18); if (data) { @@ -49,7 +48,7 @@ nvbios_pcirTe(struct nouveau_bios *bios, u32 base, u8 *ver, u16 *hdr) } u32 -nvbios_pcirTp(struct nouveau_bios *bios, u32 base, u8 *ver, u16 *hdr, +nvbios_pcirTp(struct nvkm_bios *bios, u32 base, u8 *ver, u16 *hdr, struct nvbios_pcirT *info) { u32 data = nvbios_pcirTe(bios, base, ver, hdr); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index 675e221680aa..382ae9cdbf58 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/perf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c @@ -21,13 +21,14 @@ * * Authors: Martin Peres */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/perf.h> +#include <core/device.h> + u16 -nvbios_perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, +nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_P; @@ -76,7 +77,7 @@ nvbios_perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, } u16 -nvbios_perf_entry(struct nouveau_bios *bios, int idx, +nvbios_perf_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; @@ -92,9 +93,8 @@ nvbios_perf_entry(struct nouveau_bios *bios, int idx, } u16 -nvbios_perfEp(struct nouveau_bios *bios, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_perfE *info) +nvbios_perfEp(struct nvkm_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *info) { u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len); memset(info, 0x00, sizeof(*info)); @@ -155,7 +155,7 @@ nvbios_perfEp(struct nouveau_bios *bios, int idx, } u32 -nvbios_perfSe(struct nouveau_bios *bios, u32 perfE, int idx, +nvbios_perfSe(struct nvkm_bios *bios, u32 perfE, int idx, u8 *ver, u8 *hdr, u8 cnt, u8 len) { u32 data = 0x00000000; @@ -167,7 +167,7 @@ nvbios_perfSe(struct nouveau_bios *bios, u32 perfE, int idx, } u32 -nvbios_perfSp(struct nouveau_bios *bios, u32 perfE, int idx, +nvbios_perfSp(struct nvkm_bios *bios, u32 perfE, int idx, u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_perfS *info) { @@ -184,7 +184,7 @@ nvbios_perfSp(struct nouveau_bios *bios, u32 perfE, int idx, } int -nvbios_perf_fan_parse(struct nouveau_bios *bios, +nvbios_perf_fan_parse(struct nvkm_bios *bios, struct nvbios_perf_fan *fan) { u8 ver, hdr, cnt, len, snr, ssz; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c index 1f76de597d4b..ebd402e19dbf 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/pll.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c @@ -21,12 +21,13 @@ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ - -#include <subdev/vga.h> #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/bmp.h> #include <subdev/bios/pll.h> +#include <subdev/vga.h> + +#include <core/device.h> struct pll_mapping { u8 type; @@ -66,7 +67,7 @@ nv50_pll_mapping[] = { }; static struct pll_mapping -nv84_pll_mapping[] = { +g84_pll_mapping[] = { { PLL_CORE , 0x004028 }, { PLL_SHADER, 0x004020 }, { PLL_MEMORY, 0x004008 }, @@ -78,7 +79,7 @@ nv84_pll_mapping[] = { }; static u16 -pll_limits_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_C; @@ -109,7 +110,7 @@ pll_limits_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } static struct pll_mapping * -pll_map(struct nouveau_bios *bios) +pll_map(struct nvkm_bios *bios) { switch (nv_device(bios)->card_type) { case NV_04: @@ -128,14 +129,14 @@ pll_map(struct nouveau_bios *bios) if (nv_device(bios)->chipset < 0xa3 || nv_device(bios)->chipset == 0xaa || nv_device(bios)->chipset == 0xac) - return nv84_pll_mapping; + return g84_pll_mapping; default: return NULL; } } static u16 -pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) +pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) { struct pll_mapping *map; u8 hdr, cnt; @@ -177,7 +178,7 @@ pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) } static u16 -pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) +pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) { struct pll_mapping *map; u8 hdr, cnt; @@ -219,7 +220,7 @@ pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) } int -nvbios_pll_parse(struct nouveau_bios *bios, u32 type, struct nvbios_pll *info) +nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info) { u8 ver, len; u32 reg = type; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pmu.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c index 66c56ba07d1b..20c5ce0cd573 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/pmu.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c @@ -21,14 +21,13 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/image.h> #include <subdev/bios/pmu.h> static u32 -weirdo_pointer(struct nouveau_bios *bios, u32 data) +weirdo_pointer(struct nvkm_bios *bios, u32 data) { struct nvbios_image image; int idx = 0; @@ -43,7 +42,7 @@ weirdo_pointer(struct nouveau_bios *bios, u32 data) } u32 -nvbios_pmuTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +nvbios_pmuTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_p; u32 data = 0; @@ -63,7 +62,7 @@ nvbios_pmuTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u32 -nvbios_pmuTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +nvbios_pmuTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_pmuT *info) { u32 data = nvbios_pmuTe(bios, ver, hdr, cnt, len); @@ -76,7 +75,7 @@ nvbios_pmuTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, } u32 -nvbios_pmuEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) +nvbios_pmuEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr) { u8 cnt, len; u32 data = nvbios_pmuTe(bios, ver, hdr, &cnt, &len); @@ -89,7 +88,7 @@ nvbios_pmuEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) } u32 -nvbios_pmuEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +nvbios_pmuEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, struct nvbios_pmuE *info) { u32 data = nvbios_pmuEe(bios, idx, ver, hdr); @@ -104,7 +103,7 @@ nvbios_pmuEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, } bool -nvbios_pmuRm(struct nouveau_bios *bios, u8 type, struct nvbios_pmuR *info) +nvbios_pmuRm(struct nvkm_bios *bios, u8 type, struct nvbios_pmuR *info) { struct nvbios_pmuE pmuE; u8 ver, hdr, idx = 0; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h index 187d225bd1e9..95e4fa1531d6 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h @@ -1,18 +1,17 @@ #ifndef __NVKM_BIOS_PRIV_H__ #define __NVKM_BIOS_PRIV_H__ - #include <subdev/bios.h> struct nvbios_source { const char *name; - void *(*init)(struct nouveau_bios *, const char *); + void *(*init)(struct nvkm_bios *, const char *); void (*fini)(void *); - u32 (*read)(void *, u32 offset, u32 length, struct nouveau_bios *); + u32 (*read)(void *, u32 offset, u32 length, struct nvkm_bios *); bool rw; }; -int nvbios_extend(struct nouveau_bios *, u32 length); -int nvbios_shadow(struct nouveau_bios *); +int nvbios_extend(struct nvkm_bios *, u32 length); +int nvbios_shadow(struct nvkm_bios *); extern const struct nvbios_source nvbios_rom; extern const struct nvbios_source nvbios_ramin; @@ -21,5 +20,4 @@ extern const struct nvbios_source nvbios_acpi_slow; extern const struct nvbios_source nvbios_pcirom; extern const struct nvbios_source nvbios_platform; extern const struct nvbios_source nvbios_of; - #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c index 1623c8dfe797..a17b221119b2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/ramcfg.h> #include <subdev/bios/M0203.h> static u8 -nvbios_ramcfg_strap(struct nouveau_subdev *subdev) +nvbios_ramcfg_strap(struct nvkm_subdev *subdev) { return (nv_rd32(subdev, 0x101000) & 0x0000003c) >> 2; } u8 -nvbios_ramcfg_count(struct nouveau_bios *bios) +nvbios_ramcfg_count(struct nvkm_bios *bios) { struct bit_entry bit_M; @@ -49,9 +48,9 @@ nvbios_ramcfg_count(struct nouveau_bios *bios) } u8 -nvbios_ramcfg_index(struct nouveau_subdev *subdev) +nvbios_ramcfg_index(struct nvkm_subdev *subdev) { - struct nouveau_bios *bios = nouveau_bios(subdev); + struct nvkm_bios *bios = nvkm_bios(subdev); u8 strap = nvbios_ramcfg_strap(subdev); u32 xlat = 0x00000000; struct bit_entry bit_M; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c index c5685228c322..8b17bb4b220c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> -#include <subdev/bios/ramcfg.h> #include <subdev/bios/rammap.h> u32 -nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, +nvbios_rammapTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_P; @@ -59,7 +57,7 @@ nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, } u32 -nvbios_rammapEe(struct nouveau_bios *bios, int idx, +nvbios_rammapEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; @@ -75,9 +73,8 @@ nvbios_rammapEe(struct nouveau_bios *bios, int idx, } u32 -nvbios_rammapEp(struct nouveau_bios *bios, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ramcfg *p) +nvbios_rammapEp(struct nvkm_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p) { u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp; memset(p, 0x00, sizeof(*p)); @@ -118,9 +115,8 @@ nvbios_rammapEp(struct nouveau_bios *bios, int idx, } u32 -nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ramcfg *info) +nvbios_rammapEm(struct nvkm_bios *bios, u16 mhz, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *info) { int idx = 0; u32 data; @@ -132,9 +128,8 @@ nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz, } u32 -nvbios_rammapSe(struct nouveau_bios *bios, u32 data, - u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, - u8 *ver, u8 *hdr) +nvbios_rammapSe(struct nvkm_bios *bios, u32 data, + u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, u8 *ver, u8 *hdr) { if (idx < ecnt) { data = data + ehdr + (idx * elen); @@ -146,7 +141,7 @@ nvbios_rammapSe(struct nouveau_bios *bios, u32 data, } u32 -nvbios_rammapSp(struct nouveau_bios *bios, u32 data, +nvbios_rammapSp(struct nvkm_bios *bios, u32 data, u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, u8 *ver, u8 *hdr, struct nvbios_ramcfg *p) { diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadow.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c index bb9e0018d936..8c2b7cba5cff 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadow.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c @@ -21,13 +21,15 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - #include "priv.h" + +#include <core/device.h> #include <core/option.h> +#include <subdev/bios.h> #include <subdev/bios/image.h> struct shadow { - struct nouveau_oclass base; + struct nvkm_oclass base; u32 skip; const struct nvbios_source *func; void *data; @@ -36,7 +38,7 @@ struct shadow { }; static bool -shadow_fetch(struct nouveau_bios *bios, u32 upto) +shadow_fetch(struct nvkm_bios *bios, u32 upto) { struct shadow *mthd = (void *)nv_object(bios)->oclass; const u32 limit = (upto + 3) & ~3; @@ -50,36 +52,36 @@ shadow_fetch(struct nouveau_bios *bios, u32 upto) } static u8 -shadow_rd08(struct nouveau_object *object, u64 addr) +shadow_rd08(struct nvkm_object *object, u64 addr) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; if (shadow_fetch(bios, addr + 1)) return bios->data[addr]; return 0x00; } static u16 -shadow_rd16(struct nouveau_object *object, u64 addr) +shadow_rd16(struct nvkm_object *object, u64 addr) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; if (shadow_fetch(bios, addr + 2)) return get_unaligned_le16(&bios->data[addr]); return 0x0000; } static u32 -shadow_rd32(struct nouveau_object *object, u64 addr) +shadow_rd32(struct nvkm_object *object, u64 addr) { - struct nouveau_bios *bios = (void *)object; + struct nvkm_bios *bios = (void *)object; if (shadow_fetch(bios, addr + 4)) return get_unaligned_le32(&bios->data[addr]); return 0x00000000; } -static struct nouveau_oclass +static struct nvkm_oclass shadow_class = { .handle = NV_SUBDEV(VBIOS, 0x00), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .rd08 = shadow_rd08, .rd16 = shadow_rd16, .rd32 = shadow_rd32, @@ -87,7 +89,7 @@ shadow_class = { }; static int -shadow_image(struct nouveau_bios *bios, int idx, struct shadow *mthd) +shadow_image(struct nvkm_bios *bios, int idx, struct shadow *mthd) { struct nvbios_image image; int score = 1; @@ -126,9 +128,9 @@ shadow_image(struct nouveau_bios *bios, int idx, struct shadow *mthd) } static int -shadow_score(struct nouveau_bios *bios, struct shadow *mthd) +shadow_score(struct nvkm_bios *bios, struct shadow *mthd) { - struct nouveau_oclass *oclass = nv_object(bios)->oclass; + struct nvkm_oclass *oclass = nv_object(bios)->oclass; int score; nv_object(bios)->oclass = &mthd->base; score = shadow_image(bios, 0, mthd); @@ -138,7 +140,7 @@ shadow_score(struct nouveau_bios *bios, struct shadow *mthd) } static int -shadow_method(struct nouveau_bios *bios, struct shadow *mthd, const char *name) +shadow_method(struct nvkm_bios *bios, struct shadow *mthd, const char *name) { const struct nvbios_source *func = mthd->func; if (func->name) { @@ -163,7 +165,7 @@ shadow_method(struct nouveau_bios *bios, struct shadow *mthd, const char *name) } static u32 -shadow_fw_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios) +shadow_fw_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios) { const struct firmware *fw = data; if (offset + length <= fw->size) { @@ -174,7 +176,7 @@ shadow_fw_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios) } static void * -shadow_fw_init(struct nouveau_bios *bios, const char *name) +shadow_fw_init(struct nvkm_bios *bios, const char *name) { struct device *dev = &nv_device(bios)->pdev->dev; const struct firmware *fw; @@ -194,7 +196,7 @@ shadow_fw = { }; int -nvbios_shadow(struct nouveau_bios *bios) +nvbios_shadow(struct nvkm_bios *bios) { struct shadow mthds[] = { { shadow_class, 0, &nvbios_of }, @@ -211,7 +213,7 @@ nvbios_shadow(struct nouveau_bios *bios) int optlen; /* handle user-specified bios source */ - optarg = nouveau_stropt(nv_device(bios)->cfgopt, "NvBios", &optlen); + optarg = nvkm_stropt(nv_device(bios)->cfgopt, "NvBios", &optlen); source = optarg ? kstrndup(optarg, optlen, GFP_KERNEL) : NULL; if (source) { /* try to match one of the built-in methods */ diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowacpi.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c index bc130c12ec06..1fbd93bbb561 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowacpi.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c @@ -20,9 +20,10 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ - #include "priv.h" +#include <core/device.h> + #if defined(CONFIG_ACPI) && defined(CONFIG_X86) int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); bool nouveau_acpi_rom_supported(struct pci_dev *pdev); @@ -45,7 +46,7 @@ nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) * on some systems, such as Lenovo W530. */ static u32 -acpi_read_fast(void *data, u32 offset, u32 length, struct nouveau_bios *bios) +acpi_read_fast(void *data, u32 offset, u32 length, struct nvkm_bios *bios) { u32 limit = (offset + length + 0xfff) & ~0xfff; u32 start = offset & ~0x00000fff; @@ -66,7 +67,7 @@ acpi_read_fast(void *data, u32 offset, u32 length, struct nouveau_bios *bios) * function. */ static u32 -acpi_read_slow(void *data, u32 offset, u32 length, struct nouveau_bios *bios) +acpi_read_slow(void *data, u32 offset, u32 length, struct nvkm_bios *bios) { u32 limit = (offset + length + 0xfff) & ~0xfff; u32 start = offset & ~0xfff; @@ -87,7 +88,7 @@ acpi_read_slow(void *data, u32 offset, u32 length, struct nouveau_bios *bios) } static void * -acpi_init(struct nouveau_bios *bios, const char *name) +acpi_init(struct nvkm_bios *bios, const char *name) { if (!nouveau_acpi_rom_supported(nv_device(bios)->pdev)) return ERR_PTR(-ENODEV); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowof.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c index 3abe487a6025..4c19a7dba803 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowof.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c @@ -20,9 +20,10 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ - #include "priv.h" +#include <core/device.h> + #if defined(__powerpc__) struct priv { const void __iomem *data; @@ -30,7 +31,7 @@ struct priv { }; static u32 -of_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios) +of_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios) { struct priv *priv = data; if (offset + length <= priv->size) { @@ -41,7 +42,7 @@ of_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios) } static void * -of_init(struct nouveau_bios *bios, const char *name) +of_init(struct nvkm_bios *bios, const char *name) { struct pci_dev *pdev = nv_device(bios)->pdev; struct device_node *dn; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowpci.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c index 1d0389c0abef..1b045483dc87 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowpci.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c @@ -20,9 +20,10 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ - #include "priv.h" +#include <core/device.h> + struct priv { struct pci_dev *pdev; void __iomem *rom; @@ -30,7 +31,7 @@ struct priv { }; static u32 -pcirom_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios) +pcirom_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios) { struct priv *priv = data; if (offset + length <= priv->size) { @@ -50,7 +51,7 @@ pcirom_fini(void *data) } static void * -pcirom_init(struct nouveau_bios *bios, const char *name) +pcirom_init(struct nvkm_bios *bios, const char *name) { struct pci_dev *pdev = nv_device(bios)->pdev; struct priv *priv = NULL; @@ -82,7 +83,7 @@ nvbios_pcirom = { }; static void * -platform_init(struct nouveau_bios *bios, const char *name) +platform_init(struct nvkm_bios *bios, const char *name) { struct pci_dev *pdev = nv_device(bios)->pdev; struct priv *priv; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowramin.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c index 5e58bba0dd5c..abe8ae4d3a9f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowramin.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c @@ -20,16 +20,17 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ - #include "priv.h" +#include <core/device.h> + struct priv { - struct nouveau_bios *bios; + struct nvkm_bios *bios; u32 bar0; }; static u32 -pramin_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios) +pramin_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios) { u32 i; if (offset + length <= 0x00100000) { @@ -44,12 +45,14 @@ static void pramin_fini(void *data) { struct priv *priv = data; - nv_wr32(priv->bios, 0x001700, priv->bar0); - kfree(priv); + if (priv) { + nv_wr32(priv->bios, 0x001700, priv->bar0); + kfree(priv); + } } static void * -pramin_init(struct nouveau_bios *bios, const char *name) +pramin_init(struct nvkm_bios *bios, const char *name) { struct priv *priv = NULL; u64 addr = 0; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowrom.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c index b7992bc3ffa5..6ec3b237925e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowrom.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c @@ -20,11 +20,12 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ - #include "priv.h" +#include <core/device.h> + static u32 -prom_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios) +prom_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios) { u32 i; if (offset + length <= 0x00100000) { @@ -38,7 +39,7 @@ prom_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios) static void prom_fini(void *data) { - struct nouveau_bios *bios = data; + struct nvkm_bios *bios = data; if (nv_device(bios)->card_type < NV_50) nv_mask(bios, 0x001850, 0x00000001, 0x00000001); else @@ -46,7 +47,7 @@ prom_fini(void *data) } static void * -prom_init(struct nouveau_bios *bios, const char *name) +prom_init(struct nvkm_bios *bios, const char *name) { if (nv_device(bios)->card_type < NV_50) { if (nv_device(bios)->card_type == NV_40 && diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/therm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c index d15854094078..249ff6d583df 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/therm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c @@ -21,13 +21,14 @@ * * Authors: Martin Peres */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/therm.h> +#include <core/device.h> + static u16 -therm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) +therm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) { struct bit_entry bit_P; u16 therm = 0; @@ -51,12 +52,11 @@ therm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) *hdr = nv_ro08(bios, therm + 1); *len = nv_ro08(bios, therm + 2); *cnt = nv_ro08(bios, therm + 3); - return therm + nv_ro08(bios, therm + 1); } static u16 -nvbios_therm_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +nvbios_therm_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { u8 hdr, cnt; u16 therm = therm_table(bios, ver, &hdr, len, &cnt); @@ -66,7 +66,7 @@ nvbios_therm_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) } int -nvbios_therm_sensor_parse(struct nouveau_bios *bios, +nvbios_therm_sensor_parse(struct nvkm_bios *bios, enum nvbios_therm_domain domain, struct nvbios_therm_sensor *sensor) { @@ -152,10 +152,9 @@ nvbios_therm_sensor_parse(struct nouveau_bios *bios, } int -nvbios_therm_fan_parse(struct nouveau_bios *bios, - struct nvbios_therm_fan *fan) +nvbios_therm_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan) { - struct nouveau_therm_trip_point *cur_trip = NULL; + struct nvbios_therm_trip_point *cur_trip = NULL; u8 ver, len, i; u16 entry; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c index 8521eca1ed9c..763fd29a58f2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> -#include <subdev/bios/ramcfg.h> #include <subdev/bios/timing.h> u16 -nvbios_timingTe(struct nouveau_bios *bios, +nvbios_timingTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_P; @@ -68,7 +66,7 @@ nvbios_timingTe(struct nouveau_bios *bios, } u16 -nvbios_timingEe(struct nouveau_bios *bios, int idx, +nvbios_timingEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; @@ -84,9 +82,8 @@ nvbios_timingEe(struct nouveau_bios *bios, int idx, } u16 -nvbios_timingEp(struct nouveau_bios *bios, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_ramcfg *p) +nvbios_timingEp(struct nvkm_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p) { u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; p->timing_ver = *ver; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c index f343a1b060e8..e95b69faa82e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c @@ -21,13 +21,12 @@ * * Authors: Martin Peres */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/vmap.h> u16 -nvbios_vmap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +nvbios_vmap_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_P; u16 vmap = 0x0000; @@ -55,7 +54,7 @@ nvbios_vmap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u16 -nvbios_vmap_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +nvbios_vmap_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_vmap *info) { u16 vmap = nvbios_vmap_table(bios, ver, hdr, cnt, len); @@ -69,7 +68,7 @@ nvbios_vmap_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, } u16 -nvbios_vmap_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +nvbios_vmap_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { u8 hdr, cnt; u16 vmap = nvbios_vmap_table(bios, ver, &hdr, &cnt, len); @@ -81,7 +80,7 @@ nvbios_vmap_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) } u16 -nvbios_vmap_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len, +nvbios_vmap_entry_parse(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len, struct nvbios_vmap_entry *info) { u16 vmap = nvbios_vmap_entry(bios, idx, ver, len); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/volt.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c index bb590de4ecb2..8454ab7c4a3d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/volt.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c @@ -21,13 +21,12 @@ * * Authors: Martin Peres */ - #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/volt.h> u16 -nvbios_volt_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +nvbios_volt_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_P; u16 volt = 0x0000; @@ -67,7 +66,7 @@ nvbios_volt_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u16 -nvbios_volt_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_volt *info) { u16 volt = nvbios_volt_table(bios, ver, hdr, cnt, len); @@ -102,7 +101,7 @@ nvbios_volt_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, } u16 -nvbios_volt_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +nvbios_volt_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { u8 hdr, cnt; u16 volt = nvbios_volt_table(bios, ver, &hdr, &cnt, len); @@ -114,7 +113,7 @@ nvbios_volt_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) } u16 -nvbios_volt_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len, +nvbios_volt_entry_parse(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len, struct nvbios_volt_entry *info) { u16 volt = nvbios_volt_entry(bios, idx, ver, len); diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.c index e9b8e5d30a7a..63a5e1b5cb3c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include <subdev/bios.h> #include <subdev/bios/gpio.h> #include <subdev/bios/xpio.h> static u16 -dcb_xpiod_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +dcb_xpiod_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u16 data = dcb_gpio_table(bios, ver, hdr, cnt, len); if (data && *ver >= 0x40 && *hdr >= 0x06) { @@ -44,7 +43,7 @@ dcb_xpiod_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u16 -dcb_xpio_table(struct nouveau_bios *bios, u8 idx, +dcb_xpio_table(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u16 data = dcb_xpiod_table(bios, ver, hdr, cnt, len); @@ -62,9 +61,8 @@ dcb_xpio_table(struct nouveau_bios *bios, u8 idx, } u16 -dcb_xpio_parse(struct nouveau_bios *bios, u8 idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_xpio *info) +dcb_xpio_parse(struct nvkm_bios *bios, u8 idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_xpio *info) { u16 data = dcb_xpio_table(bios, idx, ver, hdr, cnt, len); if (data && *len >= 6) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild new file mode 100644 index 000000000000..83d80b13f149 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild @@ -0,0 +1,6 @@ +nvkm-y += nvkm/subdev/bus/hwsq.o +nvkm-y += nvkm/subdev/bus/nv04.o +nvkm-y += nvkm/subdev/bus/nv31.o +nvkm-y += nvkm/subdev/bus/nv50.o +nvkm-y += nvkm/subdev/bus/g94.o +nvkm-y += nvkm/subdev/bus/gf100.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c index d3659055fa4b..cbe699e82593 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c @@ -22,13 +22,12 @@ * Authors: Martin Peres <martin.peres@labri.fr> * Ben Skeggs */ +#include "nv04.h" #include <subdev/timer.h> -#include "nv04.h" - static int -nv94_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size) +g94_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size) { struct nv50_bus_priv *priv = (void *)pbus; int i; @@ -44,16 +43,16 @@ nv94_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size) return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT; } -struct nouveau_oclass * -nv94_bus_oclass = &(struct nv04_bus_impl) { +struct nvkm_oclass * +g94_bus_oclass = &(struct nv04_bus_impl) { .base.handle = NV_SUBDEV(BUS, 0x94), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_bus_ctor, - .dtor = _nouveau_bus_dtor, + .dtor = _nvkm_bus_dtor, .init = nv50_bus_init, - .fini = _nouveau_bus_fini, + .fini = _nvkm_bus_fini, }, .intr = nv50_bus_intr, - .hwsq_exec = nv94_bus_hwsq_exec, + .hwsq_exec = g94_bus_hwsq_exec, .hwsq_size = 128, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c index 73839d7151a7..ebc63ba968d4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c @@ -22,13 +22,12 @@ * Authors: Martin Peres <martin.peres@labri.fr> * Ben Skeggs */ - #include "nv04.h" static void -nvc0_bus_intr(struct nouveau_subdev *subdev) +gf100_bus_intr(struct nvkm_subdev *subdev) { - struct nouveau_bus *pbus = nouveau_bus(subdev); + struct nvkm_bus *pbus = nvkm_bus(subdev); u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); if (stat & 0x0000000e) { @@ -54,12 +53,12 @@ nvc0_bus_intr(struct nouveau_subdev *subdev) } static int -nvc0_bus_init(struct nouveau_object *object) +gf100_bus_init(struct nvkm_object *object) { struct nv04_bus_priv *priv = (void *)object; int ret; - ret = nouveau_bus_init(&priv->base); + ret = nvkm_bus_init(&priv->base); if (ret) return ret; @@ -68,14 +67,14 @@ nvc0_bus_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * -nvc0_bus_oclass = &(struct nv04_bus_impl) { +struct nvkm_oclass * +gf100_bus_oclass = &(struct nv04_bus_impl) { .base.handle = NV_SUBDEV(BUS, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_bus_ctor, - .dtor = _nouveau_bus_dtor, - .init = nvc0_bus_init, - .fini = _nouveau_bus_fini, + .dtor = _nvkm_bus_dtor, + .init = gf100_bus_init, + .fini = _nvkm_bus_fini, }, - .intr = nvc0_bus_intr, + .intr = gf100_bus_intr, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c index f757470e2284..b8853bf16b23 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c @@ -21,12 +21,10 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include <subdev/timer.h> #include <subdev/bus.h> -struct nouveau_hwsq { - struct nouveau_bus *pbus; +struct nvkm_hwsq { + struct nvkm_bus *pbus; u32 addr; u32 data; struct { @@ -36,16 +34,16 @@ struct nouveau_hwsq { }; static void -hwsq_cmd(struct nouveau_hwsq *hwsq, int size, u8 data[]) +hwsq_cmd(struct nvkm_hwsq *hwsq, int size, u8 data[]) { memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0])); hwsq->c.size += size; } int -nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq) +nvkm_hwsq_init(struct nvkm_bus *pbus, struct nvkm_hwsq **phwsq) { - struct nouveau_hwsq *hwsq; + struct nvkm_hwsq *hwsq; hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL); if (hwsq) { @@ -60,12 +58,12 @@ nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq) } int -nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec) +nvkm_hwsq_fini(struct nvkm_hwsq **phwsq, bool exec) { - struct nouveau_hwsq *hwsq = *phwsq; + struct nvkm_hwsq *hwsq = *phwsq; int ret = 0, i; if (hwsq) { - struct nouveau_bus *pbus = hwsq->pbus; + struct nvkm_bus *pbus = hwsq->pbus; hwsq->c.size = (hwsq->c.size + 4) / 4; if (hwsq->c.size <= pbus->hwsq_size) { if (exec) @@ -88,7 +86,7 @@ nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec) } void -nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data) +nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data) { nv_debug(hwsq->pbus, "R[%06x] = 0x%08x\n", addr, data); @@ -113,7 +111,7 @@ nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data) } void -nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data) +nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data) { nv_debug(hwsq->pbus, " FLAG[%02x] = %d\n", flag, data); flag += 0x80; @@ -125,14 +123,14 @@ nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data) } void -nouveau_hwsq_wait(struct nouveau_hwsq *hwsq, u8 flag, u8 data) +nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data) { nv_debug(hwsq->pbus, " WAIT[%02x] = %d\n", flag, data); hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data }); } void -nouveau_hwsq_nsec(struct nouveau_hwsq *hwsq, u32 nsec) +nvkm_hwsq_nsec(struct nvkm_hwsq *hwsq, u32 nsec) { u8 shift = 0, usec = nsec / 1000; while (usec & ~3) { diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h index 12176f9c1bc6..3394a5ea8a9f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h @@ -1,11 +1,10 @@ #ifndef __NVKM_BUS_HWSQ_H__ #define __NVKM_BUS_HWSQ_H__ - #include <subdev/bus.h> struct hwsq { - struct nouveau_subdev *subdev; - struct nouveau_hwsq *hwsq; + struct nvkm_subdev *subdev; + struct nvkm_hwsq *hwsq; int sequence; }; @@ -34,12 +33,12 @@ hwsq_reg(u32 addr) } static inline int -hwsq_init(struct hwsq *ram, struct nouveau_subdev *subdev) +hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev) { - struct nouveau_bus *pbus = nouveau_bus(subdev); + struct nvkm_bus *pbus = nvkm_bus(subdev); int ret; - ret = nouveau_hwsq_init(pbus, &ram->hwsq); + ret = nvkm_hwsq_init(pbus, &ram->hwsq); if (ret) return ret; @@ -53,7 +52,7 @@ hwsq_exec(struct hwsq *ram, bool exec) { int ret = 0; if (ram->subdev) { - ret = nouveau_hwsq_fini(&ram->hwsq, exec); + ret = nvkm_hwsq_fini(&ram->hwsq, exec); ram->subdev = NULL; } return ret; @@ -73,8 +72,8 @@ hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data) reg->sequence = ram->sequence; reg->data = data; if (reg->addr[0] != reg->addr[1]) - nouveau_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data); - nouveau_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data); + nvkm_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data); + nvkm_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data); } static inline void @@ -95,19 +94,18 @@ hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data) static inline void hwsq_setf(struct hwsq *ram, u8 flag, int data) { - nouveau_hwsq_setf(ram->hwsq, flag, data); + nvkm_hwsq_setf(ram->hwsq, flag, data); } static inline void hwsq_wait(struct hwsq *ram, u8 flag, u8 data) { - nouveau_hwsq_wait(ram->hwsq, flag, data); + nvkm_hwsq_wait(ram->hwsq, flag, data); } static inline void hwsq_nsec(struct hwsq *ram, u32 nsec) { - nouveau_hwsq_nsec(ram->hwsq, nsec); + nvkm_hwsq_nsec(ram->hwsq, nsec); } - #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c index 23921b5351db..19c8e50eeff7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c @@ -22,13 +22,12 @@ * Authors: Martin Peres <martin.peres@labri.fr> * Ben Skeggs */ - #include "nv04.h" static void -nv04_bus_intr(struct nouveau_subdev *subdev) +nv04_bus_intr(struct nvkm_subdev *subdev) { - struct nouveau_bus *pbus = nouveau_bus(subdev); + struct nvkm_bus *pbus = nvkm_bus(subdev); u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); if (stat & 0x00000001) { @@ -38,7 +37,7 @@ nv04_bus_intr(struct nouveau_subdev *subdev) } if (stat & 0x00000110) { - subdev = nouveau_subdev(subdev, NVDEV_SUBDEV_GPIO); + subdev = nvkm_subdev(subdev, NVDEV_SUBDEV_GPIO); if (subdev && subdev->intr) subdev->intr(subdev); stat &= ~0x00000110; @@ -52,26 +51,26 @@ nv04_bus_intr(struct nouveau_subdev *subdev) } static int -nv04_bus_init(struct nouveau_object *object) +nv04_bus_init(struct nvkm_object *object) { struct nv04_bus_priv *priv = (void *)object; nv_wr32(priv, 0x001100, 0xffffffff); nv_wr32(priv, 0x001140, 0x00000111); - return nouveau_bus_init(&priv->base); + return nvkm_bus_init(&priv->base); } int -nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_bus_impl *impl = (void *)oclass; struct nv04_bus_priv *priv; int ret; - ret = nouveau_bus_create(parent, engine, oclass, &priv); + ret = nvkm_bus_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -82,14 +81,14 @@ nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv04_bus_oclass = &(struct nv04_bus_impl) { .base.handle = NV_SUBDEV(BUS, 0x04), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_bus_ctor, - .dtor = _nouveau_bus_dtor, + .dtor = _nvkm_bus_dtor, .init = nv04_bus_init, - .fini = _nouveau_bus_fini, + .fini = _nvkm_bus_fini, }, .intr = nv04_bus_intr, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h new file mode 100644 index 000000000000..3ddc8f91b1e3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h @@ -0,0 +1,21 @@ +#ifndef __NVKM_BUS_NV04_H__ +#define __NVKM_BUS_NV04_H__ +#include <subdev/bus.h> + +struct nv04_bus_priv { + struct nvkm_bus base; +}; + +int nv04_bus_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +int nv50_bus_init(struct nvkm_object *); +void nv50_bus_intr(struct nvkm_subdev *); + +struct nv04_bus_impl { + struct nvkm_oclass base; + void (*intr)(struct nvkm_subdev *); + int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32); + u32 hwsq_size; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c index 94da46f61627..c5739bce8052 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c @@ -22,18 +22,17 @@ * Authors: Martin Peres <martin.peres@labri.fr> * Ben Skeggs */ - #include "nv04.h" static void -nv31_bus_intr(struct nouveau_subdev *subdev) +nv31_bus_intr(struct nvkm_subdev *subdev) { - struct nouveau_bus *pbus = nouveau_bus(subdev); + struct nvkm_bus *pbus = nvkm_bus(subdev); u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144); if (gpio) { - subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_GPIO); + subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_GPIO); if (subdev && subdev->intr) subdev->intr(subdev); } @@ -51,7 +50,7 @@ nv31_bus_intr(struct nouveau_subdev *subdev) } if (stat & 0x00070000) { - subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM); + subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM); if (subdev && subdev->intr) subdev->intr(subdev); stat &= ~0x00070000; @@ -65,12 +64,12 @@ nv31_bus_intr(struct nouveau_subdev *subdev) } static int -nv31_bus_init(struct nouveau_object *object) +nv31_bus_init(struct nvkm_object *object) { struct nv04_bus_priv *priv = (void *)object; int ret; - ret = nouveau_bus_init(&priv->base); + ret = nvkm_bus_init(&priv->base); if (ret) return ret; @@ -79,14 +78,14 @@ nv31_bus_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv31_bus_oclass = &(struct nv04_bus_impl) { .base.handle = NV_SUBDEV(BUS, 0x31), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_bus_ctor, - .dtor = _nouveau_bus_dtor, + .dtor = _nvkm_bus_dtor, .init = nv31_bus_init, - .fini = _nouveau_bus_fini, + .fini = _nvkm_bus_fini, }, .intr = nv31_bus_intr, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c index 11918f7e2aca..1987863d71ee 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c @@ -22,13 +22,12 @@ * Authors: Martin Peres <martin.peres@labri.fr> * Ben Skeggs */ +#include "nv04.h" #include <subdev/timer.h> -#include "nv04.h" - static int -nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size) +nv50_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size) { struct nv50_bus_priv *priv = (void *)pbus; int i; @@ -44,9 +43,9 @@ nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size) } void -nv50_bus_intr(struct nouveau_subdev *subdev) +nv50_bus_intr(struct nvkm_subdev *subdev) { - struct nouveau_bus *pbus = nouveau_bus(subdev); + struct nvkm_bus *pbus = nvkm_bus(subdev); u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); if (stat & 0x00000008) { @@ -62,7 +61,7 @@ nv50_bus_intr(struct nouveau_subdev *subdev) } if (stat & 0x00010000) { - subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM); + subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM); if (subdev && subdev->intr) subdev->intr(subdev); stat &= ~0x00010000; @@ -76,12 +75,12 @@ nv50_bus_intr(struct nouveau_subdev *subdev) } int -nv50_bus_init(struct nouveau_object *object) +nv50_bus_init(struct nvkm_object *object) { struct nv04_bus_priv *priv = (void *)object; int ret; - ret = nouveau_bus_init(&priv->base); + ret = nvkm_bus_init(&priv->base); if (ret) return ret; @@ -90,14 +89,14 @@ nv50_bus_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv50_bus_oclass = &(struct nv04_bus_impl) { .base.handle = NV_SUBDEV(BUS, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_bus_ctor, - .dtor = _nouveau_bus_dtor, + .dtor = _nvkm_bus_dtor, .init = nv50_bus_init, - .fini = _nouveau_bus_fini, + .fini = _nvkm_bus_fini, }, .intr = nv50_bus_intr, .hwsq_exec = nv50_bus_hwsq_exec, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild new file mode 100644 index 000000000000..9c2f688c9602 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild @@ -0,0 +1,12 @@ +nvkm-y += nvkm/subdev/clk/base.o +nvkm-y += nvkm/subdev/clk/nv04.o +nvkm-y += nvkm/subdev/clk/nv40.o +nvkm-y += nvkm/subdev/clk/nv50.o +nvkm-y += nvkm/subdev/clk/g84.o +nvkm-y += nvkm/subdev/clk/gt215.o +nvkm-y += nvkm/subdev/clk/mcp77.o +nvkm-y += nvkm/subdev/clk/gf100.o +nvkm-y += nvkm/subdev/clk/gk104.o +nvkm-y += nvkm/subdev/clk/gk20a.o +nvkm-y += nvkm/subdev/clk/pllnv04.o +nvkm-y += nvkm/subdev/clk/pllgt215.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index e51b72d47129..b24a9cc04b73 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -21,27 +21,26 @@ * * Authors: Ben Skeggs */ - -#include <core/option.h> - -#include <subdev/clock.h> -#include <subdev/therm.h> -#include <subdev/volt.h> -#include <subdev/fb.h> - +#include <subdev/clk.h> #include <subdev/bios.h> #include <subdev/bios/boost.h> #include <subdev/bios/cstep.h> #include <subdev/bios/perf.h> +#include <subdev/fb.h> +#include <subdev/therm.h> +#include <subdev/volt.h> + +#include <core/device.h> +#include <core/option.h> /****************************************************************************** * misc *****************************************************************************/ static u32 -nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust, - u8 pstate, u8 domain, u32 input) +nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, + u8 pstate, u8 domain, u32 input) { - struct nouveau_bios *bios = nouveau_bios(clk); + struct nvkm_bios *bios = nvkm_bios(clk); struct nvbios_boostE boostE; u8 ver, hdr, cnt, len; u16 data; @@ -76,12 +75,11 @@ nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust, * C-States *****************************************************************************/ static int -nouveau_cstate_prog(struct nouveau_clock *clk, - struct nouveau_pstate *pstate, int cstatei) +nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) { - struct nouveau_therm *ptherm = nouveau_therm(clk); - struct nouveau_volt *volt = nouveau_volt(clk); - struct nouveau_cstate *cstate; + struct nvkm_therm *ptherm = nvkm_therm(clk); + struct nvkm_volt *volt = nvkm_volt(clk); + struct nvkm_cstate *cstate; int ret; if (!list_empty(&pstate->list)) { @@ -91,7 +89,7 @@ nouveau_cstate_prog(struct nouveau_clock *clk, } if (ptherm) { - ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1); + ret = nvkm_therm_cstate(ptherm, pstate->fanspeed, +1); if (ret && ret != -ENODEV) { nv_error(clk, "failed to raise fan speed: %d\n", ret); return ret; @@ -119,7 +117,7 @@ nouveau_cstate_prog(struct nouveau_clock *clk, } if (ptherm) { - ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1); + ret = nvkm_therm_cstate(ptherm, pstate->fanspeed, -1); if (ret && ret != -ENODEV) nv_error(clk, "failed to lower fan speed: %d\n", ret); } @@ -128,19 +126,18 @@ nouveau_cstate_prog(struct nouveau_clock *clk, } static void -nouveau_cstate_del(struct nouveau_cstate *cstate) +nvkm_cstate_del(struct nvkm_cstate *cstate) { list_del(&cstate->head); kfree(cstate); } static int -nouveau_cstate_new(struct nouveau_clock *clk, int idx, - struct nouveau_pstate *pstate) +nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) { - struct nouveau_bios *bios = nouveau_bios(clk); - struct nouveau_clocks *domain = clk->domains; - struct nouveau_cstate *cstate = NULL; + struct nvkm_bios *bios = nvkm_bios(clk); + struct nvkm_domain *domain = clk->domains; + struct nvkm_cstate *cstate = NULL; struct nvbios_cstepX cstepX; u8 ver, hdr; u16 data; @@ -158,10 +155,8 @@ nouveau_cstate_new(struct nouveau_clock *clk, int idx, while (domain && domain->name != nv_clk_src_max) { if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { - u32 freq = nouveau_clock_adjust(clk, true, - pstate->pstate, - domain->bios, - cstepX.freq); + u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate, + domain->bios, cstepX.freq); cstate->domain[domain->name] = freq; } domain++; @@ -175,10 +170,10 @@ nouveau_cstate_new(struct nouveau_clock *clk, int idx, * P-States *****************************************************************************/ static int -nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei) +nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) { - struct nouveau_fb *pfb = nouveau_fb(clk); - struct nouveau_pstate *pstate; + struct nvkm_fb *pfb = nvkm_fb(clk); + struct nvkm_pstate *pstate; int ret, idx = 0; list_for_each_entry(pstate, &clk->states, head) { @@ -199,13 +194,13 @@ nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei) pfb->ram->tidy(pfb); } - return nouveau_cstate_prog(clk, pstate, 0); + return nvkm_cstate_prog(clk, pstate, 0); } static void -nouveau_pstate_work(struct work_struct *work) +nvkm_pstate_work(struct work_struct *work) { - struct nouveau_clock *clk = container_of(work, typeof(*clk), work); + struct nvkm_clk *clk = container_of(work, typeof(*clk), work); int pstate; if (!atomic_xchg(&clk->waiting, 0)) @@ -227,7 +222,7 @@ nouveau_pstate_work(struct work_struct *work) nv_trace(clk, "-> %d\n", pstate); if (pstate != clk->pstate) { - int ret = nouveau_pstate_prog(clk, pstate); + int ret = nvkm_pstate_prog(clk, pstate); if (ret) { nv_error(clk, "error setting pstate %d: %d\n", pstate, ret); @@ -239,7 +234,7 @@ nouveau_pstate_work(struct work_struct *work) } static int -nouveau_pstate_calc(struct nouveau_clock *clk, bool wait) +nvkm_pstate_calc(struct nvkm_clk *clk, bool wait) { atomic_set(&clk->waiting, 1); schedule_work(&clk->work); @@ -249,10 +244,10 @@ nouveau_pstate_calc(struct nouveau_clock *clk, bool wait) } static void -nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate) +nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) { - struct nouveau_clocks *clock = clk->domains - 1; - struct nouveau_cstate *cstate; + struct nvkm_domain *clock = clk->domains - 1; + struct nvkm_cstate *cstate; char info[3][32] = { "", "", "" }; char name[4] = "--"; int i = -1; @@ -291,12 +286,12 @@ nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate) } static void -nouveau_pstate_del(struct nouveau_pstate *pstate) +nvkm_pstate_del(struct nvkm_pstate *pstate) { - struct nouveau_cstate *cstate, *temp; + struct nvkm_cstate *cstate, *temp; list_for_each_entry_safe(cstate, temp, &pstate->list, head) { - nouveau_cstate_del(cstate); + nvkm_cstate_del(cstate); } list_del(&pstate->head); @@ -304,12 +299,12 @@ nouveau_pstate_del(struct nouveau_pstate *pstate) } static int -nouveau_pstate_new(struct nouveau_clock *clk, int idx) +nvkm_pstate_new(struct nvkm_clk *clk, int idx) { - struct nouveau_bios *bios = nouveau_bios(clk); - struct nouveau_clocks *domain = clk->domains - 1; - struct nouveau_pstate *pstate; - struct nouveau_cstate *cstate; + struct nvkm_bios *bios = nvkm_bios(clk); + struct nvkm_domain *domain = clk->domains - 1; + struct nvkm_pstate *pstate; + struct nvkm_cstate *cstate; struct nvbios_cstepE cstepE; struct nvbios_perfE perfE; u8 ver, hdr, cnt, len; @@ -346,10 +341,10 @@ nouveau_pstate_new(struct nouveau_clock *clk, int idx) continue; if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { - perfS.v40.freq = nouveau_clock_adjust(clk, false, - pstate->pstate, - domain->bios, - perfS.v40.freq); + perfS.v40.freq = nvkm_clk_adjust(clk, false, + pstate->pstate, + domain->bios, + perfS.v40.freq); } cstate->domain[domain->name] = perfS.v40.freq; @@ -359,11 +354,11 @@ nouveau_pstate_new(struct nouveau_clock *clk, int idx) if (data) { int idx = cstepE.index; do { - nouveau_cstate_new(clk, idx, pstate); + nvkm_cstate_new(clk, idx, pstate); } while(idx--); } - nouveau_pstate_info(clk, pstate); + nvkm_pstate_info(clk, pstate); list_add_tail(&pstate->head, &clk->states); clk->state_nr++; return 0; @@ -373,9 +368,9 @@ nouveau_pstate_new(struct nouveau_clock *clk, int idx) * Adjustment triggers *****************************************************************************/ static int -nouveau_clock_ustate_update(struct nouveau_clock *clk, int req) +nvkm_clk_ustate_update(struct nvkm_clk *clk, int req) { - struct nouveau_pstate *pstate; + struct nvkm_pstate *pstate; int i = 0; if (!clk->allow_reclock) @@ -397,17 +392,20 @@ nouveau_clock_ustate_update(struct nouveau_clock *clk, int req) } static int -nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen) +nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) { int ret = 1; + if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen)) + return -2; + if (strncasecmpz(mode, "disabled", arglen)) { char save = mode[arglen]; long v; ((char *)mode)[arglen] = '\0'; if (!kstrtol(mode, 0, &v)) { - ret = nouveau_clock_ustate_update(clk, v); + ret = nvkm_clk_ustate_update(clk, v); if (ret < 0) ret = 1; } @@ -418,53 +416,53 @@ nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen) } int -nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr) +nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr) { - int ret = nouveau_clock_ustate_update(clk, req); + int ret = nvkm_clk_ustate_update(clk, req); if (ret >= 0) { if (ret -= 2, pwr) clk->ustate_ac = ret; else clk->ustate_dc = ret; - return nouveau_pstate_calc(clk, true); + return nvkm_pstate_calc(clk, true); } return ret; } int -nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel) +nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait) { if (!rel) clk->astate = req; if ( rel) clk->astate += rel; clk->astate = min(clk->astate, clk->state_nr - 1); clk->astate = max(clk->astate, 0); - return nouveau_pstate_calc(clk, true); + return nvkm_pstate_calc(clk, wait); } int -nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel) +nvkm_clk_tstate(struct nvkm_clk *clk, int req, int rel) { if (!rel) clk->tstate = req; if ( rel) clk->tstate += rel; clk->tstate = min(clk->tstate, 0); clk->tstate = max(clk->tstate, -(clk->state_nr - 1)); - return nouveau_pstate_calc(clk, true); + return nvkm_pstate_calc(clk, true); } int -nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel) +nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel) { if (!rel) clk->dstate = req; if ( rel) clk->dstate += rel; clk->dstate = min(clk->dstate, clk->state_nr - 1); clk->dstate = max(clk->dstate, 0); - return nouveau_pstate_calc(clk, true); + return nvkm_pstate_calc(clk, true); } static int -nouveau_clock_pwrsrc(struct nvkm_notify *notify) +nvkm_clk_pwrsrc(struct nvkm_notify *notify) { - struct nouveau_clock *clk = + struct nvkm_clk *clk = container_of(notify, typeof(*clk), pwrsrc_ntfy); - nouveau_pstate_calc(clk, false); + nvkm_pstate_calc(clk, false); return NVKM_NOTIFY_DROP; } @@ -473,21 +471,21 @@ nouveau_clock_pwrsrc(struct nvkm_notify *notify) *****************************************************************************/ int -_nouveau_clock_fini(struct nouveau_object *object, bool suspend) +_nvkm_clk_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_clock *clk = (void *)object; + struct nvkm_clk *clk = (void *)object; nvkm_notify_put(&clk->pwrsrc_ntfy); - return nouveau_subdev_fini(&clk->base, suspend); + return nvkm_subdev_fini(&clk->base, suspend); } int -_nouveau_clock_init(struct nouveau_object *object) +_nvkm_clk_init(struct nvkm_object *object) { - struct nouveau_clock *clk = (void *)object; - struct nouveau_clocks *clock = clk->domains; + struct nvkm_clk *clk = (void *)object; + struct nvkm_domain *clock = clk->domains; int ret; - ret = nouveau_subdev_init(&clk->base); + ret = nvkm_subdev_init(&clk->base); if (ret) return ret; @@ -505,47 +503,44 @@ _nouveau_clock_init(struct nouveau_object *object) clock++; } - nouveau_pstate_info(clk, &clk->bstate); + nvkm_pstate_info(clk, &clk->bstate); clk->astate = clk->state_nr - 1; clk->tstate = 0; clk->dstate = 0; clk->pstate = -1; - nouveau_pstate_calc(clk, true); + nvkm_pstate_calc(clk, true); return 0; } void -_nouveau_clock_dtor(struct nouveau_object *object) +_nvkm_clk_dtor(struct nvkm_object *object) { - struct nouveau_clock *clk = (void *)object; - struct nouveau_pstate *pstate, *temp; + struct nvkm_clk *clk = (void *)object; + struct nvkm_pstate *pstate, *temp; nvkm_notify_fini(&clk->pwrsrc_ntfy); list_for_each_entry_safe(pstate, temp, &clk->states, head) { - nouveau_pstate_del(pstate); + nvkm_pstate_del(pstate); } - nouveau_subdev_destroy(&clk->base); + nvkm_subdev_destroy(&clk->base); } int -nouveau_clock_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - struct nouveau_clocks *clocks, - struct nouveau_pstate *pstates, int nb_pstates, - bool allow_reclock, - int length, void **object) +nvkm_clk_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, struct nvkm_domain *clocks, + struct nvkm_pstate *pstates, int nb_pstates, + bool allow_reclock, int length, void **object) { - struct nouveau_device *device = nv_device(parent); - struct nouveau_clock *clk; + struct nvkm_device *device = nv_device(parent); + struct nvkm_clk *clk; int ret, idx, arglen; const char *mode; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK", - "clock", length, object); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "CLK", + "clock", length, object); clk = *object; if (ret) return ret; @@ -555,7 +550,7 @@ nouveau_clock_create_(struct nouveau_object *parent, clk->ustate_ac = -1; clk->ustate_dc = -1; - INIT_WORK(&clk->work, nouveau_pstate_work); + INIT_WORK(&clk->work, nvkm_pstate_work); init_waitqueue_head(&clk->wait); atomic_set(&clk->waiting, 0); @@ -563,7 +558,7 @@ nouveau_clock_create_(struct nouveau_object *parent, if (!pstates) { idx = 0; do { - ret = nouveau_pstate_new(clk, idx++); + ret = nvkm_pstate_new(clk, idx++); } while (ret == 0); } else { for (idx = 0; idx < nb_pstates; idx++) @@ -573,25 +568,24 @@ nouveau_clock_create_(struct nouveau_object *parent, clk->allow_reclock = allow_reclock; - ret = nvkm_notify_init(NULL, &device->event, nouveau_clock_pwrsrc, true, + ret = nvkm_notify_init(NULL, &device->event, nvkm_clk_pwrsrc, true, NULL, 0, 0, &clk->pwrsrc_ntfy); if (ret) return ret; - mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen); + mode = nvkm_stropt(device->cfgopt, "NvClkMode", &arglen); if (mode) { - clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); - clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); + clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen); + clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen); } - mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen); + mode = nvkm_stropt(device->cfgopt, "NvClkModeAC", &arglen); if (mode) - clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); + clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen); - mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen); + mode = nvkm_stropt(device->cfgopt, "NvClkModeDC", &arglen); if (mode) - clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); - + clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen); return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c index b0b7c1437f10..4c90b9769d64 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c @@ -21,11 +21,10 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - #include "nv50.h" -static struct nouveau_clocks -nv84_domains[] = { +static struct nvkm_domain +g84_domains[] = { { nv_clk_src_crystal, 0xff }, { nv_clk_src_href , 0xff }, { nv_clk_src_core , 0xff, 0, "core", 1000 }, @@ -35,14 +34,14 @@ nv84_domains[] = { { nv_clk_src_max } }; -struct nouveau_oclass * -nv84_clock_oclass = &(struct nv50_clock_oclass) { - .base.handle = NV_SUBDEV(CLOCK, 0x84), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, +struct nvkm_oclass * +g84_clk_oclass = &(struct nv50_clk_oclass) { + .base.handle = NV_SUBDEV(CLK, 0x84), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_clk_ctor, + .dtor = _nvkm_clk_dtor, + .init = _nvkm_clk_init, + .fini = _nvkm_clk_fini, }, - .domains = nv84_domains, + .domains = g84_domains, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c index 1234abaab2db..3d7330d54b02 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -21,15 +21,15 @@ * * Authors: Ben Skeggs */ +#include <subdev/clk.h> +#include "pll.h" -#include <subdev/clock.h> +#include <core/device.h> #include <subdev/bios.h> #include <subdev/bios/pll.h> #include <subdev/timer.h> -#include "pll.h" - -struct nvc0_clock_info { +struct gf100_clk_info { u32 freq; u32 ssel; u32 mdiv; @@ -38,17 +38,17 @@ struct nvc0_clock_info { u32 coef; }; -struct nvc0_clock_priv { - struct nouveau_clock base; - struct nvc0_clock_info eng[16]; +struct gf100_clk_priv { + struct nvkm_clk base; + struct gf100_clk_info eng[16]; }; -static u32 read_div(struct nvc0_clock_priv *, int, u32, u32); +static u32 read_div(struct gf100_clk_priv *, int, u32, u32); static u32 -read_vco(struct nvc0_clock_priv *priv, u32 dsrc) +read_vco(struct gf100_clk_priv *priv, u32 dsrc) { - struct nouveau_clock *clk = &priv->base; + struct nvkm_clk *clk = &priv->base; u32 ssrc = nv_rd32(priv, dsrc); if (!(ssrc & 0x00000100)) return clk->read(clk, nv_clk_src_sppll0); @@ -56,9 +56,9 @@ read_vco(struct nvc0_clock_priv *priv, u32 dsrc) } static u32 -read_pll(struct nvc0_clock_priv *priv, u32 pll) +read_pll(struct gf100_clk_priv *priv, u32 pll) { - struct nouveau_clock *clk = &priv->base; + struct nvkm_clk *clk = &priv->base; u32 ctrl = nv_rd32(priv, pll + 0x00); u32 coef = nv_rd32(priv, pll + 0x04); u32 P = (coef & 0x003f0000) >> 16; @@ -95,7 +95,7 @@ read_pll(struct nvc0_clock_priv *priv, u32 pll) } static u32 -read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) +read_div(struct gf100_clk_priv *priv, int doff, u32 dsrc, u32 dctl) { u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); u32 sctl = nv_rd32(priv, dctl + (doff * 4)); @@ -121,7 +121,7 @@ read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) } static u32 -read_clk(struct nvc0_clock_priv *priv, int clk) +read_clk(struct gf100_clk_priv *priv, int clk) { u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); u32 ssel = nv_rd32(priv, 0x137100); @@ -145,10 +145,10 @@ read_clk(struct nvc0_clock_priv *priv, int clk) } static int -nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +gf100_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) { - struct nouveau_device *device = nv_device(clk); - struct nvc0_clock_priv *priv = (void *)clk; + struct nvkm_device *device = nv_device(clk); + struct gf100_clk_priv *priv = (void *)clk; switch (src) { case nv_clk_src_crystal: @@ -196,7 +196,7 @@ nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) } static u32 -calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) +calc_div(struct gf100_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) { u32 div = min((ref * 2) / freq, (u32)65); if (div < 2) @@ -207,7 +207,7 @@ calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) } static u32 -calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) +calc_src(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) { u32 sclk; @@ -236,9 +236,9 @@ calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) } static u32 -calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef) +calc_pll(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *coef) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_pll limits; int N, M, P, ret; @@ -250,7 +250,7 @@ calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef) if (!limits.refclk) return 0; - ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); + ret = gt215_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); if (ret <= 0) return 0; @@ -259,10 +259,10 @@ calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef) } static int -calc_clk(struct nvc0_clock_priv *priv, - struct nouveau_cstate *cstate, int clk, int dom) +calc_clk(struct gf100_clk_priv *priv, + struct nvkm_cstate *cstate, int clk, int dom) { - struct nvc0_clock_info *info = &priv->eng[clk]; + struct gf100_clk_info *info = &priv->eng[clk]; u32 freq = cstate->domain[dom]; u32 src0, div0, div1D, div1P = 0; u32 clk0, clk1 = 0; @@ -311,9 +311,9 @@ calc_clk(struct nvc0_clock_priv *priv, } static int -nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +gf100_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) { - struct nvc0_clock_priv *priv = (void *)clk; + struct gf100_clk_priv *priv = (void *)clk; int ret; if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || @@ -330,9 +330,9 @@ nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) } static void -nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk) +gf100_clk_prog_0(struct gf100_clk_priv *priv, int clk) { - struct nvc0_clock_info *info = &priv->eng[clk]; + struct gf100_clk_info *info = &priv->eng[clk]; if (clk < 7 && !info->ssel) { nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); @@ -340,16 +340,16 @@ nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk) } static void -nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk) +gf100_clk_prog_1(struct gf100_clk_priv *priv, int clk) { nv_mask(priv, 0x137100, (1 << clk), 0x00000000); nv_wait(priv, 0x137100, (1 << clk), 0x00000000); } static void -nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk) +gf100_clk_prog_2(struct gf100_clk_priv *priv, int clk) { - struct nvc0_clock_info *info = &priv->eng[clk]; + struct gf100_clk_info *info = &priv->eng[clk]; const u32 addr = 0x137000 + (clk * 0x20); if (clk <= 7) { nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); @@ -364,9 +364,9 @@ nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk) } static void -nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk) +gf100_clk_prog_3(struct gf100_clk_priv *priv, int clk) { - struct nvc0_clock_info *info = &priv->eng[clk]; + struct gf100_clk_info *info = &priv->eng[clk]; if (info->ssel) { nv_mask(priv, 0x137100, (1 << clk), info->ssel); nv_wait(priv, 0x137100, (1 << clk), info->ssel); @@ -374,24 +374,24 @@ nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk) } static void -nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk) +gf100_clk_prog_4(struct gf100_clk_priv *priv, int clk) { - struct nvc0_clock_info *info = &priv->eng[clk]; + struct gf100_clk_info *info = &priv->eng[clk]; nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); } static int -nvc0_clock_prog(struct nouveau_clock *clk) +gf100_clk_prog(struct nvkm_clk *clk) { - struct nvc0_clock_priv *priv = (void *)clk; + struct gf100_clk_priv *priv = (void *)clk; struct { - void (*exec)(struct nvc0_clock_priv *, int); + void (*exec)(struct gf100_clk_priv *, int); } stage[] = { - { nvc0_clock_prog_0 }, /* div programming */ - { nvc0_clock_prog_1 }, /* select div mode */ - { nvc0_clock_prog_2 }, /* (maybe) program pll */ - { nvc0_clock_prog_3 }, /* (maybe) select pll mode */ - { nvc0_clock_prog_4 }, /* final divider */ + { gf100_clk_prog_0 }, /* div programming */ + { gf100_clk_prog_1 }, /* select div mode */ + { gf100_clk_prog_2 }, /* (maybe) program pll */ + { gf100_clk_prog_3 }, /* (maybe) select pll mode */ + { gf100_clk_prog_4 }, /* final divider */ }; int i, j; @@ -407,14 +407,14 @@ nvc0_clock_prog(struct nouveau_clock *clk) } static void -nvc0_clock_tidy(struct nouveau_clock *clk) +gf100_clk_tidy(struct nvkm_clk *clk) { - struct nvc0_clock_priv *priv = (void *)clk; + struct gf100_clk_priv *priv = (void *)clk; memset(priv->eng, 0x00, sizeof(priv->eng)); } -static struct nouveau_clocks -nvc0_domain[] = { +static struct nvkm_domain +gf100_domain[] = { { nv_clk_src_crystal, 0xff }, { nv_clk_src_href , 0xff }, { nv_clk_src_hubk06 , 0x00 }, @@ -430,33 +430,33 @@ nvc0_domain[] = { }; static int -nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_clock_priv *priv; + struct gf100_clk_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, NULL, 0, - false, &priv); + ret = nvkm_clk_create(parent, engine, oclass, gf100_domain, + NULL, 0, false, &priv); *pobject = nv_object(priv); if (ret) return ret; - priv->base.read = nvc0_clock_read; - priv->base.calc = nvc0_clock_calc; - priv->base.prog = nvc0_clock_prog; - priv->base.tidy = nvc0_clock_tidy; + priv->base.read = gf100_clk_read; + priv->base.calc = gf100_clk_calc; + priv->base.prog = gf100_clk_prog; + priv->base.tidy = gf100_clk_tidy; return 0; } -struct nouveau_oclass -nvc0_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, +struct nvkm_oclass +gf100_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_clk_ctor, + .dtor = _nvkm_clk_dtor, + .init = _nvkm_clk_init, + .fini = _nvkm_clk_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c index 7eccad57512e..e9b2310bdfbb 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c @@ -21,15 +21,15 @@ * * Authors: Ben Skeggs */ +#include <subdev/clk.h> +#include "pll.h" -#include <subdev/clock.h> +#include <core/device.h> #include <subdev/timer.h> #include <subdev/bios.h> #include <subdev/bios/pll.h> -#include "pll.h" - -struct nve0_clock_info { +struct gk104_clk_info { u32 freq; u32 ssel; u32 mdiv; @@ -38,16 +38,16 @@ struct nve0_clock_info { u32 coef; }; -struct nve0_clock_priv { - struct nouveau_clock base; - struct nve0_clock_info eng[16]; +struct gk104_clk_priv { + struct nvkm_clk base; + struct gk104_clk_info eng[16]; }; -static u32 read_div(struct nve0_clock_priv *, int, u32, u32); -static u32 read_pll(struct nve0_clock_priv *, u32); +static u32 read_div(struct gk104_clk_priv *, int, u32, u32); +static u32 read_pll(struct gk104_clk_priv *, u32); static u32 -read_vco(struct nve0_clock_priv *priv, u32 dsrc) +read_vco(struct gk104_clk_priv *priv, u32 dsrc) { u32 ssrc = nv_rd32(priv, dsrc); if (!(ssrc & 0x00000100)) @@ -56,7 +56,7 @@ read_vco(struct nve0_clock_priv *priv, u32 dsrc) } static u32 -read_pll(struct nve0_clock_priv *priv, u32 pll) +read_pll(struct gk104_clk_priv *priv, u32 pll) { u32 ctrl = nv_rd32(priv, pll + 0x00); u32 coef = nv_rd32(priv, pll + 0x04); @@ -101,7 +101,7 @@ read_pll(struct nve0_clock_priv *priv, u32 pll) } static u32 -read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) +read_div(struct gk104_clk_priv *priv, int doff, u32 dsrc, u32 dctl) { u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); u32 sctl = nv_rd32(priv, dctl + (doff * 4)); @@ -127,7 +127,7 @@ read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) } static u32 -read_mem(struct nve0_clock_priv *priv) +read_mem(struct gk104_clk_priv *priv) { switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) { case 1: return read_pll(priv, 0x132020); @@ -138,7 +138,7 @@ read_mem(struct nve0_clock_priv *priv) } static u32 -read_clk(struct nve0_clock_priv *priv, int clk) +read_clk(struct gk104_clk_priv *priv, int clk) { u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); u32 sclk, sdiv; @@ -181,10 +181,10 @@ read_clk(struct nve0_clock_priv *priv, int clk) } static int -nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +gk104_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) { - struct nouveau_device *device = nv_device(clk); - struct nve0_clock_priv *priv = (void *)clk; + struct nvkm_device *device = nv_device(clk); + struct gk104_clk_priv *priv = (void *)clk; switch (src) { case nv_clk_src_crystal: @@ -214,7 +214,7 @@ nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) } static u32 -calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) +calc_div(struct gk104_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) { u32 div = min((ref * 2) / freq, (u32)65); if (div < 2) @@ -225,7 +225,7 @@ calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) } static u32 -calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) +calc_src(struct gk104_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) { u32 sclk; @@ -254,9 +254,9 @@ calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) } static u32 -calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef) +calc_pll(struct gk104_clk_priv *priv, int clk, u32 freq, u32 *coef) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_pll limits; int N, M, P, ret; @@ -268,7 +268,7 @@ calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef) if (!limits.refclk) return 0; - ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); + ret = gt215_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); if (ret <= 0) return 0; @@ -277,10 +277,10 @@ calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef) } static int -calc_clk(struct nve0_clock_priv *priv, - struct nouveau_cstate *cstate, int clk, int dom) +calc_clk(struct gk104_clk_priv *priv, + struct nvkm_cstate *cstate, int clk, int dom) { - struct nve0_clock_info *info = &priv->eng[clk]; + struct gk104_clk_info *info = &priv->eng[clk]; u32 freq = cstate->domain[dom]; u32 src0, div0, div1D, div1P = 0; u32 clk0, clk1 = 0; @@ -329,9 +329,9 @@ calc_clk(struct nve0_clock_priv *priv, } static int -nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +gk104_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) { - struct nve0_clock_priv *priv = (void *)clk; + struct gk104_clk_priv *priv = (void *)clk; int ret; if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || @@ -347,9 +347,9 @@ nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) } static void -nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk) +gk104_clk_prog_0(struct gk104_clk_priv *priv, int clk) { - struct nve0_clock_info *info = &priv->eng[clk]; + struct gk104_clk_info *info = &priv->eng[clk]; if (!info->ssel) { nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv); nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); @@ -357,22 +357,22 @@ nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk) } static void -nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk) +gk104_clk_prog_1_0(struct gk104_clk_priv *priv, int clk) { nv_mask(priv, 0x137100, (1 << clk), 0x00000000); nv_wait(priv, 0x137100, (1 << clk), 0x00000000); } static void -nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk) +gk104_clk_prog_1_1(struct gk104_clk_priv *priv, int clk) { nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000); } static void -nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk) +gk104_clk_prog_2(struct gk104_clk_priv *priv, int clk) { - struct nve0_clock_info *info = &priv->eng[clk]; + struct gk104_clk_info *info = &priv->eng[clk]; const u32 addr = 0x137000 + (clk * 0x20); nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); @@ -385,9 +385,9 @@ nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk) } static void -nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) +gk104_clk_prog_3(struct gk104_clk_priv *priv, int clk) { - struct nve0_clock_info *info = &priv->eng[clk]; + struct gk104_clk_info *info = &priv->eng[clk]; if (info->ssel) nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); else @@ -395,9 +395,9 @@ nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) } static void -nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk) +gk104_clk_prog_4_0(struct gk104_clk_priv *priv, int clk) { - struct nve0_clock_info *info = &priv->eng[clk]; + struct gk104_clk_info *info = &priv->eng[clk]; if (info->ssel) { nv_mask(priv, 0x137100, (1 << clk), info->ssel); nv_wait(priv, 0x137100, (1 << clk), info->ssel); @@ -405,9 +405,9 @@ nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk) } static void -nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk) +gk104_clk_prog_4_1(struct gk104_clk_priv *priv, int clk) { - struct nve0_clock_info *info = &priv->eng[clk]; + struct gk104_clk_info *info = &priv->eng[clk]; if (info->ssel) { nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000); nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100); @@ -415,20 +415,20 @@ nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk) } static int -nve0_clock_prog(struct nouveau_clock *clk) +gk104_clk_prog(struct nvkm_clk *clk) { - struct nve0_clock_priv *priv = (void *)clk; + struct gk104_clk_priv *priv = (void *)clk; struct { u32 mask; - void (*exec)(struct nve0_clock_priv *, int); + void (*exec)(struct gk104_clk_priv *, int); } stage[] = { - { 0x007f, nve0_clock_prog_0 }, /* div programming */ - { 0x007f, nve0_clock_prog_1_0 }, /* select div mode */ - { 0xff80, nve0_clock_prog_1_1 }, - { 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */ - { 0xff80, nve0_clock_prog_3 }, /* final divider */ - { 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */ - { 0xff80, nve0_clock_prog_4_1 }, + { 0x007f, gk104_clk_prog_0 }, /* div programming */ + { 0x007f, gk104_clk_prog_1_0 }, /* select div mode */ + { 0xff80, gk104_clk_prog_1_1 }, + { 0x00ff, gk104_clk_prog_2 }, /* (maybe) program pll */ + { 0xff80, gk104_clk_prog_3 }, /* final divider */ + { 0x007f, gk104_clk_prog_4_0 }, /* (maybe) select pll mode */ + { 0xff80, gk104_clk_prog_4_1 }, }; int i, j; @@ -446,14 +446,14 @@ nve0_clock_prog(struct nouveau_clock *clk) } static void -nve0_clock_tidy(struct nouveau_clock *clk) +gk104_clk_tidy(struct nvkm_clk *clk) { - struct nve0_clock_priv *priv = (void *)clk; + struct gk104_clk_priv *priv = (void *)clk; memset(priv->eng, 0x00, sizeof(priv->eng)); } -static struct nouveau_clocks -nve0_domain[] = { +static struct nvkm_domain +gk104_domain[] = { { nv_clk_src_crystal, 0xff }, { nv_clk_src_href , 0xff }, { nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 }, @@ -468,33 +468,33 @@ nve0_domain[] = { }; static int -nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_clock_priv *priv; + struct gk104_clk_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, NULL, 0, - true, &priv); + ret = nvkm_clk_create(parent, engine, oclass, gk104_domain, + NULL, 0, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - priv->base.read = nve0_clock_read; - priv->base.calc = nve0_clock_calc; - priv->base.prog = nve0_clock_prog; - priv->base.tidy = nve0_clock_tidy; + priv->base.read = gk104_clk_read; + priv->base.calc = gk104_clk_calc; + priv->base.prog = gk104_clk_prog; + priv->base.tidy = gk104_clk_tidy; return 0; } -struct nouveau_oclass -nve0_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, +struct nvkm_oclass +gk104_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_clk_ctor, + .dtor = _nvkm_clk_dtor, + .init = _nvkm_clk_init, + .fini = _nvkm_clk_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c index fb4fad374bdd..65c532742b08 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -22,6 +22,14 @@ * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c * */ +#include <subdev/clk.h> +#include <subdev/timer.h> + +#include <core/device.h> + +#ifdef __KERNEL__ +#include <nouveau_platform.h> +#endif #define MHZ (1000 * 1000) @@ -87,13 +95,6 @@ #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) -#include <subdev/clock.h> -#include <subdev/timer.h> - -#ifdef __KERNEL__ -#include <nouveau_platform.h> -#endif - static const u8 pl_to_div[] = { /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, @@ -116,16 +117,16 @@ static const struct gk20a_clk_pllg_params gk20a_pllg_params = { .min_pl = 1, .max_pl = 32, }; -struct gk20a_clock_priv { - struct nouveau_clock base; +struct gk20a_clk_priv { + struct nvkm_clk base; const struct gk20a_clk_pllg_params *params; u32 m, n, pl; u32 parent_rate; }; -#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base) +#define to_gk20a_clk(base) container_of(base, struct gk20a_clk_priv, base) static void -gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv) +gk20a_pllg_read_mnp(struct gk20a_clk_priv *priv) { u32 val; @@ -136,7 +137,7 @@ gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv) } static u32 -gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv) +gk20a_pllg_calc_rate(struct gk20a_clk_priv *priv) { u32 rate; u32 divider; @@ -149,7 +150,7 @@ gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv) } static int -gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate) +gk20a_pllg_calc_mnp(struct gk20a_clk_priv *priv, unsigned long rate) { u32 target_clk_f, ref_clk_f, target_freq; u32 min_vco_f, max_vco_f; @@ -260,12 +261,11 @@ found_match: nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]); - return 0; } static int -gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n) +gk20a_pllg_slide(struct gk20a_clk_priv *priv, u32 n) { u32 val; int ramp_timeout; @@ -322,21 +322,21 @@ gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n) } static void -_gk20a_pllg_enable(struct gk20a_clock_priv *priv) +_gk20a_pllg_enable(struct gk20a_clk_priv *priv) { nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); nv_rd32(priv, GPCPLL_CFG); } static void -_gk20a_pllg_disable(struct gk20a_clock_priv *priv) +_gk20a_pllg_disable(struct gk20a_clk_priv *priv) { nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); nv_rd32(priv, GPCPLL_CFG); } static int -_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) +_gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv, bool allow_slide) { u32 val, cfg; u32 m_old, pl_old, n_lo; @@ -402,8 +402,8 @@ _gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) nv_wr32(priv, GPCPLL_CFG, val); } - if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, - GPCPLL_CFG_LOCK)) { + if (!nvkm_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, + GPCPLL_CFG_LOCK)) { nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__); return -ETIMEDOUT; } @@ -422,7 +422,7 @@ _gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) } static int -gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv) +gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv) { int err; @@ -434,7 +434,7 @@ gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv) } static void -gk20a_pllg_disable(struct gk20a_clock_priv *priv) +gk20a_pllg_disable(struct gk20a_clk_priv *priv) { u32 val; @@ -458,14 +458,14 @@ gk20a_pllg_disable(struct gk20a_clock_priv *priv) #define GK20A_CLK_GPC_MDIV 1000 -static struct nouveau_clocks +static struct nvkm_domain gk20a_domains[] = { { nv_clk_src_crystal, 0xff }, { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, { nv_clk_src_max } }; -static struct nouveau_pstate +static struct nvkm_pstate gk20a_pstates[] = { { .base = { @@ -560,9 +560,9 @@ gk20a_pstates[] = { }; static int -gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +gk20a_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) { - struct gk20a_clock_priv *priv = (void *)clk; + struct gk20a_clk_priv *priv = (void *)clk; switch (src) { case nv_clk_src_crystal: @@ -577,34 +577,34 @@ gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) } static int -gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +gk20a_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) { - struct gk20a_clock_priv *priv = (void *)clk; + struct gk20a_clk_priv *priv = (void *)clk; return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV); } static int -gk20a_clock_prog(struct nouveau_clock *clk) +gk20a_clk_prog(struct nvkm_clk *clk) { - struct gk20a_clock_priv *priv = (void *)clk; + struct gk20a_clk_priv *priv = (void *)clk; return gk20a_pllg_program_mnp(priv); } static void -gk20a_clock_tidy(struct nouveau_clock *clk) +gk20a_clk_tidy(struct nvkm_clk *clk) { } static int -gk20a_clock_fini(struct nouveau_object *object, bool suspend) +gk20a_clk_fini(struct nvkm_object *object, bool suspend) { - struct gk20a_clock_priv *priv = (void *)object; + struct gk20a_clk_priv *priv = (void *)object; int ret; - ret = nouveau_clock_fini(&priv->base, false); + ret = nvkm_clk_fini(&priv->base, false); gk20a_pllg_disable(priv); @@ -612,18 +612,18 @@ gk20a_clock_fini(struct nouveau_object *object, bool suspend) } static int -gk20a_clock_init(struct nouveau_object *object) +gk20a_clk_init(struct nvkm_object *object) { - struct gk20a_clock_priv *priv = (void *)object; + struct gk20a_clk_priv *priv = (void *)object; int ret; nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); - ret = nouveau_clock_init(&priv->base); + ret = nvkm_clk_init(&priv->base); if (ret) return ret; - ret = gk20a_clock_prog(&priv->base); + ret = gk20a_clk_prog(&priv->base); if (ret) { nv_error(priv, "cannot initialize clock\n"); return ret; @@ -633,11 +633,11 @@ gk20a_clock_init(struct nouveau_object *object) } static int -gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct gk20a_clock_priv *priv; + struct gk20a_clk_priv *priv; struct nouveau_platform_device *plat; int ret; int i; @@ -648,8 +648,9 @@ gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, gk20a_pstates[i].pstate = i + 1; } - ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains, - gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv); + ret = nvkm_clk_create(parent, engine, oclass, gk20a_domains, + gk20a_pstates, ARRAY_SIZE(gk20a_pstates), + true, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -660,21 +661,20 @@ gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->parent_rate = clk_get_rate(plat->gpu->clk); nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ); - priv->base.read = gk20a_clock_read; - priv->base.calc = gk20a_clock_calc; - priv->base.prog = gk20a_clock_prog; - priv->base.tidy = gk20a_clock_tidy; - + priv->base.read = gk20a_clk_read; + priv->base.calc = gk20a_clk_calc; + priv->base.prog = gk20a_clk_prog; + priv->base.tidy = gk20a_clk_tidy; return 0; } -struct nouveau_oclass -gk20a_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0xea), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = gk20a_clock_ctor, - .dtor = _nouveau_subdev_dtor, - .init = gk20a_clock_init, - .fini = gk20a_clock_fini, +struct nvkm_oclass +gk20a_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0xea), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk20a_clk_ctor, + .dtor = _nvkm_subdev_dtor, + .init = gk20a_clk_init, + .fini = gk20a_clk_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c index 07ad01247675..822d32a28d6e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c @@ -22,26 +22,25 @@ * Authors: Ben Skeggs * Roy Spliet */ +#include "gt215.h" +#include "pll.h" +#include <core/device.h> #include <engine/fifo.h> #include <subdev/bios.h> #include <subdev/bios/pll.h> #include <subdev/timer.h> -#include "pll.h" - -#include "nva3.h" - -struct nva3_clock_priv { - struct nouveau_clock base; - struct nva3_clock_info eng[nv_clk_src_max]; +struct gt215_clk_priv { + struct nvkm_clk base; + struct gt215_clk_info eng[nv_clk_src_max]; }; -static u32 read_clk(struct nva3_clock_priv *, int, bool); -static u32 read_pll(struct nva3_clock_priv *, int, u32); +static u32 read_clk(struct gt215_clk_priv *, int, bool); +static u32 read_pll(struct gt215_clk_priv *, int, u32); static u32 -read_vco(struct nva3_clock_priv *priv, int clk) +read_vco(struct gt215_clk_priv *priv, int clk) { u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); @@ -58,7 +57,7 @@ read_vco(struct nva3_clock_priv *priv, int clk) } static u32 -read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en) +read_clk(struct gt215_clk_priv *priv, int clk, bool ignore_en) { u32 sctl, sdiv, sclk; @@ -104,7 +103,7 @@ read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en) } static u32 -read_pll(struct nva3_clock_priv *priv, int clk, u32 pll) +read_pll(struct gt215_clk_priv *priv, int clk, u32 pll) { u32 ctrl = nv_rd32(priv, pll + 0); u32 sclk = 0, P = 1, N = 1, M = 1; @@ -130,13 +129,14 @@ read_pll(struct nva3_clock_priv *priv, int clk, u32 pll) if (M * P) return sclk * N / (M * P); + return 0; } static int -nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +gt215_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) { - struct nva3_clock_priv *priv = (void *)clk; + struct gt215_clk_priv *priv = (void *)clk; u32 hsrc; switch (src) { @@ -176,10 +176,10 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) } int -nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz, - struct nva3_clock_info *info) +gt215_clk_info(struct nvkm_clk *clock, int clk, u32 khz, + struct gt215_clk_info *info) { - struct nva3_clock_priv *priv = (void *)clock; + struct gt215_clk_priv *priv = (void *)clock; u32 oclk, sclk, sdiv, diff; info->clk = 0; @@ -223,11 +223,11 @@ nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz, } int -nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, - struct nva3_clock_info *info) +gt215_pll_info(struct nvkm_clk *clock, int clk, u32 pll, u32 khz, + struct gt215_clk_info *info) { - struct nouveau_bios *bios = nouveau_bios(clock); - struct nva3_clock_priv *priv = (void *)clock; + struct nvkm_bios *bios = nvkm_bios(clock); + struct gt215_clk_priv *priv = (void *)clock; struct nvbios_pll limits; int P, N, M, diff; int ret; @@ -236,7 +236,7 @@ nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, /* If we can get a within [-2, 3) MHz of a divider, we'll disable the * PLL and use the divider instead. */ - ret = nva3_clk_info(clock, clk, khz, info); + ret = gt215_clk_info(clock, clk, khz, info); diff = khz - ret; if (!pll || (diff >= -2000 && diff < 3000)) { goto out; @@ -247,38 +247,37 @@ nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, if (ret) return ret; - ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info); + ret = gt215_clk_info(clock, clk - 0x10, limits.refclk, info); if (ret != limits.refclk) return -EINVAL; - ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); + ret = gt215_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); if (ret >= 0) { info->pll = (P << 16) | (N << 8) | M; } out: info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); - return ret ? ret : -ERANGE; } static int -calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate, +calc_clk(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate, int clk, u32 pll, int idx) { - int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx], - &priv->eng[idx]); + int ret = gt215_pll_info(&priv->base, clk, pll, cstate->domain[idx], + &priv->eng[idx]); if (ret >= 0) return 0; return ret; } static int -calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate) +calc_host(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate) { int ret = 0; u32 kHz = cstate->domain[nv_clk_src_host]; - struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; + struct gt215_clk_info *info = &priv->eng[nv_clk_src_host]; if (kHz == 277000) { info->clk = 0; @@ -288,16 +287,17 @@ calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate) info->host_out = NVA3_HOST_CLK; - ret = nva3_clk_info(&priv->base, 0x1d, kHz, info); + ret = gt215_clk_info(&priv->base, 0x1d, kHz, info); if (ret >= 0) return 0; + return ret; } int -nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags) +gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) { - struct nouveau_fifo *pfifo = nouveau_fifo(clk); + struct nvkm_fifo *pfifo = nvkm_fifo(clk); /* halt and idle execution engines */ nv_mask(clk, 0x020060, 0x00070000, 0x00000000); @@ -318,9 +318,9 @@ nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags) } void -nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags) +gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) { - struct nouveau_fifo *pfifo = nouveau_fifo(clk); + struct nvkm_fifo *pfifo = nvkm_fifo(clk); if (pfifo && flags) pfifo->start(pfifo, flags); @@ -330,16 +330,16 @@ nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags) } static void -disable_clk_src(struct nva3_clock_priv *priv, u32 src) +disable_clk_src(struct gt215_clk_priv *priv, u32 src) { nv_mask(priv, src, 0x00000100, 0x00000000); nv_mask(priv, src, 0x00000001, 0x00000000); } static void -prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx) +prog_pll(struct gt215_clk_priv *priv, int clk, u32 pll, int idx) { - struct nva3_clock_info *info = &priv->eng[idx]; + struct gt215_clk_info *info = &priv->eng[idx]; const u32 src0 = 0x004120 + (clk * 4); const u32 src1 = 0x004160 + (clk * 4); const u32 ctrl = pll + 0; @@ -377,16 +377,16 @@ prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx) } static void -prog_clk(struct nva3_clock_priv *priv, int clk, int idx) +prog_clk(struct gt215_clk_priv *priv, int clk, int idx) { - struct nva3_clock_info *info = &priv->eng[idx]; + struct gt215_clk_info *info = &priv->eng[idx]; nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); } static void -prog_host(struct nva3_clock_priv *priv) +prog_host(struct gt215_clk_priv *priv) { - struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; + struct gt215_clk_info *info = &priv->eng[nv_clk_src_host]; u32 hsrc = (nv_rd32(priv, 0xc040)); switch (info->host_out) { @@ -411,9 +411,9 @@ prog_host(struct nva3_clock_priv *priv) } static void -prog_core(struct nva3_clock_priv *priv, int idx) +prog_core(struct gt215_clk_priv *priv, int idx) { - struct nva3_clock_info *info = &priv->eng[idx]; + struct gt215_clk_info *info = &priv->eng[idx]; u32 fb_delay = nv_rd32(priv, 0x10002c); if (fb_delay < info->fb_delay) @@ -426,10 +426,10 @@ prog_core(struct nva3_clock_priv *priv, int idx) } static int -nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +gt215_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) { - struct nva3_clock_priv *priv = (void *)clk; - struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; + struct gt215_clk_priv *priv = (void *)clk; + struct gt215_clk_info *core = &priv->eng[nv_clk_src_core]; int ret; if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || @@ -442,9 +442,9 @@ nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) /* XXX: Should be reading the highest bit in the VBIOS clock to decide * whether to use a PLL or not... but using a PLL defeats the purpose */ if (core->pll) { - ret = nva3_clk_info(clk, 0x10, - cstate->domain[nv_clk_src_core_intm], - &priv->eng[nv_clk_src_core_intm]); + ret = gt215_clk_info(clk, 0x10, + cstate->domain[nv_clk_src_core_intm], + &priv->eng[nv_clk_src_core_intm]); if (ret < 0) return ret; } @@ -453,15 +453,15 @@ nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) } static int -nva3_clock_prog(struct nouveau_clock *clk) +gt215_clk_prog(struct nvkm_clk *clk) { - struct nva3_clock_priv *priv = (void *)clk; - struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; + struct gt215_clk_priv *priv = (void *)clk; + struct gt215_clk_info *core = &priv->eng[nv_clk_src_core]; int ret = 0; unsigned long flags; unsigned long *f = &flags; - ret = nva3_clock_pre(clk, f); + ret = gt215_clk_pre(clk, f); if (ret) goto out; @@ -478,18 +478,17 @@ out: if (ret == -EBUSY) f = NULL; - nva3_clock_post(clk, f); - + gt215_clk_post(clk, f); return ret; } static void -nva3_clock_tidy(struct nouveau_clock *clk) +gt215_clk_tidy(struct nvkm_clk *clk) { } -static struct nouveau_clocks -nva3_domain[] = { +static struct nvkm_domain +gt215_domain[] = { { nv_clk_src_crystal , 0xff }, { nv_clk_src_core , 0x00, 0, "core", 1000 }, { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, @@ -502,33 +501,33 @@ nva3_domain[] = { }; static int -nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gt215_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nva3_clock_priv *priv; + struct gt215_clk_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0, - true, &priv); + ret = nvkm_clk_create(parent, engine, oclass, gt215_domain, + NULL, 0, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - priv->base.read = nva3_clock_read; - priv->base.calc = nva3_clock_calc; - priv->base.prog = nva3_clock_prog; - priv->base.tidy = nva3_clock_tidy; + priv->base.read = gt215_clk_read; + priv->base.calc = gt215_clk_calc; + priv->base.prog = gt215_clk_prog; + priv->base.tidy = gt215_clk_tidy; return 0; } -struct nouveau_oclass -nva3_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, +struct nvkm_oclass +gt215_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0xa3), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gt215_clk_ctor, + .dtor = _nvkm_clk_dtor, + .init = _nvkm_clk_init, + .fini = _nvkm_clk_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h new file mode 100644 index 000000000000..b447d9cd4d37 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h @@ -0,0 +1,18 @@ +#ifndef __NVKM_CLK_NVA3_H__ +#define __NVKM_CLK_NVA3_H__ +#include <subdev/clk.h> + +struct gt215_clk_info { + u32 clk; + u32 pll; + enum { + NVA3_HOST_277, + NVA3_HOST_CLK, + } host_out; + u32 fb_delay; +}; + +int gt215_pll_info(struct nvkm_clk *, int, u32, u32, struct gt215_clk_info *); +int gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags); +void gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c index 54aeab8005a0..c54417b146c7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c @@ -21,18 +21,16 @@ * * Authors: Ben Skeggs */ +#include "gt215.h" +#include "pll.h" -#include <engine/fifo.h> +#include <core/device.h> #include <subdev/bios.h> #include <subdev/bios/pll.h> #include <subdev/timer.h> -#include <subdev/clock.h> - -#include "nva3.h" -#include "pll.h" -struct nvaa_clock_priv { - struct nouveau_clock base; +struct mcp77_clk_priv { + struct nvkm_clk base; enum nv_clk_src csrc, ssrc, vsrc; u32 cctrl, sctrl; u32 ccoef, scoef; @@ -41,13 +39,13 @@ struct nvaa_clock_priv { }; static u32 -read_div(struct nouveau_clock *clk) +read_div(struct nvkm_clk *clk) { return nv_rd32(clk, 0x004600); } static u32 -read_pll(struct nouveau_clock *clk, u32 base) +read_pll(struct nvkm_clk *clk, u32 base) { u32 ctrl = nv_rd32(clk, base + 0); u32 coef = nv_rd32(clk, base + 4); @@ -78,9 +76,9 @@ read_pll(struct nouveau_clock *clk, u32 base) } static int -nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +mcp77_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) { - struct nvaa_clock_priv *priv = (void *)clk; + struct mcp77_clk_priv *priv = (void *)clk; u32 mast = nv_rd32(clk, 0x00c054); u32 P = 0; @@ -160,12 +158,12 @@ nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) } static u32 -calc_pll(struct nvaa_clock_priv *priv, u32 reg, +calc_pll(struct mcp77_clk_priv *priv, u32 reg, u32 clock, int *N, int *M, int *P) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_pll pll; - struct nouveau_clock *clk = &priv->base; + struct nvkm_clk *clk = &priv->base; int ret; ret = nvbios_pll_parse(bios, reg, &pll); @@ -199,9 +197,9 @@ calc_P(u32 src, u32 target, int *div) } static int -nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +mcp77_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) { - struct nvaa_clock_priv *priv = (void *)clk; + struct mcp77_clk_priv *priv = (void *)clk; const int shader = cstate->domain[nv_clk_src_shader]; const int core = cstate->domain[nv_clk_src_core]; const int vdec = cstate->domain[nv_clk_src_vdec]; @@ -216,8 +214,7 @@ nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) /* Calculate clock * 2, so shader clock can use it too */ clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1); - if (abs(core - out) <= - abs(core - (clock >> 1))) { + if (abs(core - out) <= abs(core - (clock >> 1))) { priv->csrc = nv_clk_src_hclkm4; priv->cctrl = divs << 16; } else { @@ -242,9 +239,8 @@ nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) priv->ssrc = nv_clk_src_href; } else { clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1); - if (priv->csrc == nv_clk_src_core) { + if (priv->csrc == nv_clk_src_core) out = calc_P((core << 1), shader, &divs); - } if (abs(shader - out) <= abs(shader - clock) && @@ -261,8 +257,7 @@ nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) /* vclk */ out = calc_P(core, vdec, &divs); clock = calc_P(500000, vdec, &P1); - if(abs(vdec - out) <= - abs(vdec - clock)) { + if(abs(vdec - out) <= abs(vdec - clock)) { priv->vsrc = nv_clk_src_cclk; priv->vdiv = divs << 16; } else { @@ -297,15 +292,15 @@ nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) } static int -nvaa_clock_prog(struct nouveau_clock *clk) +mcp77_clk_prog(struct nvkm_clk *clk) { - struct nvaa_clock_priv *priv = (void *)clk; + struct mcp77_clk_priv *priv = (void *)clk; u32 pllmask = 0, mast; unsigned long flags; unsigned long *f = &flags; int ret = 0; - ret = nva3_clock_pre(clk, f); + ret = gt215_clk_pre(clk, f); if (ret) goto out; @@ -382,18 +377,17 @@ out: if (ret == -EBUSY) f = NULL; - nva3_clock_post(clk, f); - + gt215_clk_post(clk, f); return ret; } static void -nvaa_clock_tidy(struct nouveau_clock *clk) +mcp77_clk_tidy(struct nvkm_clk *clk) { } -static struct nouveau_clocks -nvaa_domains[] = { +static struct nvkm_domain +mcp77_domains[] = { { nv_clk_src_crystal, 0xff }, { nv_clk_src_href , 0xff }, { nv_clk_src_core , 0xff, 0, "core", 1000 }, @@ -403,33 +397,33 @@ nvaa_domains[] = { }; static int -nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +mcp77_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvaa_clock_priv *priv; + struct mcp77_clk_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, NULL, - 0, true, &priv); + ret = nvkm_clk_create(parent, engine, oclass, mcp77_domains, + NULL, 0, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - priv->base.read = nvaa_clock_read; - priv->base.calc = nvaa_clock_calc; - priv->base.prog = nvaa_clock_prog; - priv->base.tidy = nvaa_clock_tidy; + priv->base.read = mcp77_clk_read; + priv->base.calc = mcp77_clk_calc; + priv->base.prog = mcp77_clk_prog; + priv->base.tidy = mcp77_clk_tidy; return 0; } -struct nouveau_oclass * -nvaa_clock_oclass = &(struct nouveau_oclass) { - .handle = NV_SUBDEV(CLOCK, 0xaa), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvaa_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, +struct nvkm_oclass * +mcp77_clk_oclass = &(struct nvkm_oclass) { + .handle = NV_SUBDEV(CLK, 0xaa), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = mcp77_clk_ctor, + .dtor = _nvkm_clk_dtor, + .init = _nvkm_clk_init, + .fini = _nvkm_clk_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c index 4c48232686be..63dbbb575228 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c @@ -21,21 +21,20 @@ * * Authors: Ben Skeggs */ +#include <subdev/clk.h> +#include "pll.h" #include <subdev/bios.h> #include <subdev/bios/pll.h> -#include <subdev/clock.h> #include <subdev/devinit/nv04.h> -#include "pll.h" - -struct nv04_clock_priv { - struct nouveau_clock base; +struct nv04_clk_priv { + struct nvkm_clk base; }; int -nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, - int clk, struct nouveau_pll_vals *pv) +nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info, + int clk, struct nvkm_pll_vals *pv) { int N1, M1, N2, M2, P; int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P); @@ -51,11 +50,10 @@ nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, } int -nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1, - struct nouveau_pll_vals *pv) +nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) { - struct nouveau_devinit *devinit = nouveau_devinit(clk); - int cv = nouveau_bios(clk)->version.chip; + struct nvkm_devinit *devinit = nvkm_devinit(clk); + int cv = nvkm_bios(clk)->version.chip; if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || cv >= 0x40) { @@ -69,37 +67,37 @@ nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1, return 0; } -static struct nouveau_clocks +static struct nvkm_domain nv04_domain[] = { { nv_clk_src_max } }; static int -nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv04_clock_priv *priv; + struct nv04_clk_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0, - false, &priv); + ret = nvkm_clk_create(parent, engine, oclass, nv04_domain, + NULL, 0, false, &priv); *pobject = nv_object(priv); if (ret) return ret; - priv->base.pll_calc = nv04_clock_pll_calc; - priv->base.pll_prog = nv04_clock_pll_prog; + priv->base.pll_calc = nv04_clk_pll_calc; + priv->base.pll_prog = nv04_clk_pll_prog; return 0; } -struct nouveau_oclass -nv04_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, +struct nvkm_oclass +nv04_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0x04), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv04_clk_ctor, + .dtor = _nvkm_clk_dtor, + .init = _nvkm_clk_init, + .fini = _nvkm_clk_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c index 08368fe97029..ed838130c89d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c @@ -21,22 +21,22 @@ * * Authors: Ben Skeggs */ +#include <subdev/clk.h> +#include "pll.h" -#include <subdev/clock.h> +#include <core/device.h> #include <subdev/bios.h> #include <subdev/bios/pll.h> -#include "pll.h" - -struct nv40_clock_priv { - struct nouveau_clock base; +struct nv40_clk_priv { + struct nvkm_clk base; u32 ctrl; u32 npll_ctrl; u32 npll_coef; u32 spll; }; -static struct nouveau_clocks +static struct nvkm_domain nv40_domain[] = { { nv_clk_src_crystal, 0xff }, { nv_clk_src_href , 0xff }, @@ -47,7 +47,7 @@ nv40_domain[] = { }; static u32 -read_pll_1(struct nv40_clock_priv *priv, u32 reg) +read_pll_1(struct nv40_clk_priv *priv, u32 reg) { u32 ctrl = nv_rd32(priv, reg + 0x00); int P = (ctrl & 0x00070000) >> 16; @@ -62,7 +62,7 @@ read_pll_1(struct nv40_clock_priv *priv, u32 reg) } static u32 -read_pll_2(struct nv40_clock_priv *priv, u32 reg) +read_pll_2(struct nv40_clk_priv *priv, u32 reg) { u32 ctrl = nv_rd32(priv, reg + 0x00); u32 coef = nv_rd32(priv, reg + 0x04); @@ -87,7 +87,7 @@ read_pll_2(struct nv40_clock_priv *priv, u32 reg) } static u32 -read_clk(struct nv40_clock_priv *priv, u32 src) +read_clk(struct nv40_clk_priv *priv, u32 src) { switch (src) { case 3: @@ -102,9 +102,9 @@ read_clk(struct nv40_clock_priv *priv, u32 src) } static int -nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +nv40_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) { - struct nv40_clock_priv *priv = (void *)clk; + struct nv40_clk_priv *priv = (void *)clk; u32 mast = nv_rd32(priv, 0x00c040); switch (src) { @@ -127,10 +127,10 @@ nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) } static int -nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk, - int *N1, int *M1, int *N2, int *M2, int *log2P) +nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk, + int *N1, int *M1, int *N2, int *M2, int *log2P) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_pll pll; int ret; @@ -144,21 +144,22 @@ nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk, ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P); if (ret == 0) return -ERANGE; + return ret; } static int -nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +nv40_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) { - struct nv40_clock_priv *priv = (void *)clk; + struct nv40_clk_priv *priv = (void *)clk; int gclk = cstate->domain[nv_clk_src_core]; int sclk = cstate->domain[nv_clk_src_shader]; int N1, M1, N2, M2, log2P; int ret; /* core/geometric clock */ - ret = nv40_clock_calc_pll(priv, 0x004000, gclk, - &N1, &M1, &N2, &M2, &log2P); + ret = nv40_clk_calc_pll(priv, 0x004000, gclk, + &N1, &M1, &N2, &M2, &log2P); if (ret < 0) return ret; @@ -172,8 +173,8 @@ nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) /* use the second pll for shader/rop clock, if it differs from core */ if (sclk && sclk != gclk) { - ret = nv40_clock_calc_pll(priv, 0x004008, sclk, - &N1, &M1, NULL, NULL, &log2P); + ret = nv40_clk_calc_pll(priv, 0x004008, sclk, + &N1, &M1, NULL, NULL, &log2P); if (ret < 0) return ret; @@ -188,9 +189,9 @@ nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) } static int -nv40_clock_prog(struct nouveau_clock *clk) +nv40_clk_prog(struct nvkm_clk *clk) { - struct nv40_clock_priv *priv = (void *)clk; + struct nv40_clk_priv *priv = (void *)clk; nv_mask(priv, 0x00c040, 0x00000333, 0x00000000); nv_wr32(priv, 0x004004, priv->npll_coef); nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl); @@ -201,40 +202,40 @@ nv40_clock_prog(struct nouveau_clock *clk) } static void -nv40_clock_tidy(struct nouveau_clock *clk) +nv40_clk_tidy(struct nvkm_clk *clk) { } static int -nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv40_clock_priv *priv; + struct nv40_clk_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, NULL, 0, - true, &priv); + ret = nvkm_clk_create(parent, engine, oclass, nv40_domain, + NULL, 0, true, &priv); *pobject = nv_object(priv); if (ret) return ret; - priv->base.pll_calc = nv04_clock_pll_calc; - priv->base.pll_prog = nv04_clock_pll_prog; - priv->base.read = nv40_clock_read; - priv->base.calc = nv40_clock_calc; - priv->base.prog = nv40_clock_prog; - priv->base.tidy = nv40_clock_tidy; + priv->base.pll_calc = nv04_clk_pll_calc; + priv->base.pll_prog = nv04_clk_pll_prog; + priv->base.read = nv40_clk_read; + priv->base.calc = nv40_clk_calc; + priv->base.prog = nv40_clk_prog; + priv->base.tidy = nv40_clk_tidy; return 0; } -struct nouveau_oclass -nv40_clock_oclass = { - .handle = NV_SUBDEV(CLOCK, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, +struct nvkm_oclass +nv40_clk_oclass = { + .handle = NV_SUBDEV(CLK, 0x40), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv40_clk_ctor, + .dtor = _nvkm_clk_dtor, + .init = _nvkm_clk_init, + .fini = _nvkm_clk_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c index 5070ebc260f8..9b4ffd6347ce 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c @@ -21,16 +21,16 @@ * * Authors: Ben Skeggs */ - -#include <subdev/bios.h> -#include <subdev/bios/pll.h> - #include "nv50.h" #include "pll.h" #include "seq.h" +#include <core/device.h> +#include <subdev/bios.h> +#include <subdev/bios/pll.h> + static u32 -read_div(struct nv50_clock_priv *priv) +read_div(struct nv50_clk_priv *priv) { switch (nv_device(priv)->chipset) { case 0x50: /* it exists, but only has bit 31, not the dividers.. */ @@ -49,9 +49,9 @@ read_div(struct nv50_clock_priv *priv) } static u32 -read_pll_src(struct nv50_clock_priv *priv, u32 base) +read_pll_src(struct nv50_clk_priv *priv, u32 base) { - struct nouveau_clock *clk = &priv->base; + struct nvkm_clk *clk = &priv->base; u32 coef, ref = clk->read(clk, nv_clk_src_crystal); u32 rsel = nv_rd32(priv, 0x00e18c); int P, N, M, id; @@ -116,13 +116,14 @@ read_pll_src(struct nv50_clock_priv *priv, u32 base) if (M) return (ref * N / M) >> P; + return 0; } static u32 -read_pll_ref(struct nv50_clock_priv *priv, u32 base) +read_pll_ref(struct nv50_clk_priv *priv, u32 base) { - struct nouveau_clock *clk = &priv->base; + struct nvkm_clk *clk = &priv->base; u32 src, mast = nv_rd32(priv, 0x00c040); switch (base) { @@ -147,13 +148,14 @@ read_pll_ref(struct nv50_clock_priv *priv, u32 base) if (src) return clk->read(clk, nv_clk_src_href); + return read_pll_src(priv, base); } static u32 -read_pll(struct nv50_clock_priv *priv, u32 base) +read_pll(struct nv50_clk_priv *priv, u32 base) { - struct nouveau_clock *clk = &priv->base; + struct nvkm_clk *clk = &priv->base; u32 mast = nv_rd32(priv, 0x00c040); u32 ctrl = nv_rd32(priv, base + 0); u32 coef = nv_rd32(priv, base + 4); @@ -162,7 +164,7 @@ read_pll(struct nv50_clock_priv *priv, u32 base) int N1, N2, M1, M2; if (base == 0x004028 && (mast & 0x00100000)) { - /* wtf, appears to only disable post-divider on nva0 */ + /* wtf, appears to only disable post-divider on gt200 */ if (nv_device(priv)->chipset != 0xa0) return clk->read(clk, nv_clk_src_dom6); } @@ -185,9 +187,9 @@ read_pll(struct nv50_clock_priv *priv, u32 base) } static int -nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +nv50_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) { - struct nv50_clock_priv *priv = (void *)clk; + struct nv50_clk_priv *priv = (void *)clk; u32 mast = nv_rd32(priv, 0x00c040); u32 P = 0; @@ -316,9 +318,9 @@ nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) } static u32 -calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) +calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_pll pll; int ret; @@ -359,10 +361,10 @@ clk_same(u32 a, u32 b) } static int -nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +nv50_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) { - struct nv50_clock_priv *priv = (void *)clk; - struct nv50_clock_hwsq *hwsq = &priv->hwsq; + struct nv50_clk_priv *priv = (void *)clk; + struct nv50_clk_hwsq *hwsq = &priv->hwsq; const int shader = cstate->domain[nv_clk_src_shader]; const int core = cstate->domain[nv_clk_src_core]; const int vdec = cstate->domain[nv_clk_src_vdec]; @@ -484,30 +486,30 @@ nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) } static int -nv50_clock_prog(struct nouveau_clock *clk) +nv50_clk_prog(struct nvkm_clk *clk) { - struct nv50_clock_priv *priv = (void *)clk; + struct nv50_clk_priv *priv = (void *)clk; return clk_exec(&priv->hwsq, true); } static void -nv50_clock_tidy(struct nouveau_clock *clk) +nv50_clk_tidy(struct nvkm_clk *clk) { - struct nv50_clock_priv *priv = (void *)clk; + struct nv50_clk_priv *priv = (void *)clk; clk_exec(&priv->hwsq, false); } int -nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv50_clock_oclass *pclass = (void *)oclass; - struct nv50_clock_priv *priv; + struct nv50_clk_oclass *pclass = (void *)oclass; + struct nv50_clk_priv *priv; int ret; - ret = nouveau_clock_create(parent, engine, oclass, pclass->domains, - NULL, 0, false, &priv); + ret = nvkm_clk_create(parent, engine, oclass, pclass->domains, + NULL, 0, false, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -529,14 +531,14 @@ nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } priv->hwsq.r_mast = hwsq_reg(0x00c040); - priv->base.read = nv50_clock_read; - priv->base.calc = nv50_clock_calc; - priv->base.prog = nv50_clock_prog; - priv->base.tidy = nv50_clock_tidy; + priv->base.read = nv50_clk_read; + priv->base.calc = nv50_clk_calc; + priv->base.prog = nv50_clk_prog; + priv->base.tidy = nv50_clk_tidy; return 0; } -static struct nouveau_clocks +static struct nvkm_domain nv50_domains[] = { { nv_clk_src_crystal, 0xff }, { nv_clk_src_href , 0xff }, @@ -546,14 +548,14 @@ nv50_domains[] = { { nv_clk_src_max } }; -struct nouveau_oclass * -nv50_clock_oclass = &(struct nv50_clock_oclass) { - .base.handle = NV_SUBDEV(CLOCK, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_clock_ctor, - .dtor = _nouveau_clock_dtor, - .init = _nouveau_clock_init, - .fini = _nouveau_clock_fini, +struct nvkm_oclass * +nv50_clk_oclass = &(struct nv50_clk_oclass) { + .base.handle = NV_SUBDEV(CLK, 0x50), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_clk_ctor, + .dtor = _nvkm_clk_dtor, + .init = _nvkm_clk_init, + .fini = _nvkm_clk_fini, }, .domains = nv50_domains, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h new file mode 100644 index 000000000000..0ead76a32f10 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h @@ -0,0 +1,28 @@ +#ifndef __NVKM_CLK_NV50_H__ +#define __NVKM_CLK_NV50_H__ +#include <subdev/bus/hwsq.h> +#include <subdev/clk.h> + +struct nv50_clk_hwsq { + struct hwsq base; + struct hwsq_reg r_fifo; + struct hwsq_reg r_spll[2]; + struct hwsq_reg r_nvpll[2]; + struct hwsq_reg r_divs; + struct hwsq_reg r_mast; +}; + +struct nv50_clk_priv { + struct nvkm_clk base; + struct nv50_clk_hwsq hwsq; +}; + +int nv50_clk_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); + +struct nv50_clk_oclass { + struct nvkm_oclass base; + struct nvkm_domain *domains; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h new file mode 100644 index 000000000000..44020a30dee8 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h @@ -0,0 +1,11 @@ +#ifndef __NVKM_PLL_H__ +#define __NVKM_PLL_H__ +#include <core/os.h> +struct nvkm_subdev; +struct nvbios_pll; + +int nv04_pll_calc(struct nvkm_subdev *, struct nvbios_pll *, u32 freq, + int *N1, int *M1, int *N2, int *M2, int *P); +int gt215_pll_calc(struct nvkm_subdev *, struct nvbios_pll *, u32 freq, + int *N, int *fN, int *M, int *P); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c index 8eca457c2814..783a3e78d632 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c @@ -21,16 +21,14 @@ * * Authors: Ben Skeggs */ +#include "pll.h" -#include <subdev/clock.h> #include <subdev/bios.h> #include <subdev/bios/pll.h> -#include "pll.h" - int -nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, - u32 freq, int *pN, int *pfN, int *pM, int *P) +gt215_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info, + u32 freq, int *pN, int *pfN, int *pM, int *P) { u32 best_err = ~0, err; int M, lM, hM, N, fN; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c index b47d543ab2e3..f2292895a1a8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c @@ -20,14 +20,13 @@ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ +#include "pll.h" #include <subdev/bios.h> #include <subdev/bios/pll.h> -#include "pll.h" - static int -getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, +getMNP_single(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk, int *pN, int *pM, int *pP) { /* Find M, N and P for a single stage PLL @@ -38,7 +37,7 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, * "clk" parameter in kHz * returns calculated clock */ - struct nouveau_bios *bios = nouveau_bios(subdev); + struct nvkm_bios *bios = nvkm_bios(subdev); int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq; int minM = info->vco1.min_m, maxM = info->vco1.max_m; int minN = info->vco1.min_n, maxN = info->vco1.max_n; @@ -126,7 +125,7 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, } static int -getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, +getMNP_double(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk, int *pN1, int *pM1, int *pN2, int *pM2, int *pP) { /* Find M, N and P for a two stage PLL @@ -137,7 +136,7 @@ getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, * "clk" parameter in kHz * returns calculated clock */ - int chip_version = nouveau_bios(subdev)->version.chip; + int chip_version = nvkm_bios(subdev)->version.chip; int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq; int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq; int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq; @@ -225,7 +224,7 @@ getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, } int -nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq, +nv04_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info, u32 freq, int *N1, int *M1, int *N2, int *M2, int *P) { int ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h index fb33f06ebd59..d717e8b8f679 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h @@ -1,7 +1,5 @@ #ifndef __NVKM_CLK_SEQ_H__ #define __NVKM_CLK_SEQ_H__ - -#include <subdev/bus.h> #include <subdev/bus/hwsq.h> #define clk_init(s,p) hwsq_init(&(s)->base, (p)) @@ -13,5 +11,4 @@ #define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) #define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) #define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n)) - #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild new file mode 100644 index 000000000000..793e73d16dac --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild @@ -0,0 +1,14 @@ +nvkm-y += nvkm/subdev/devinit/base.o +nvkm-y += nvkm/subdev/devinit/nv04.o +nvkm-y += nvkm/subdev/devinit/nv05.o +nvkm-y += nvkm/subdev/devinit/nv10.o +nvkm-y += nvkm/subdev/devinit/nv1a.o +nvkm-y += nvkm/subdev/devinit/nv20.o +nvkm-y += nvkm/subdev/devinit/nv50.o +nvkm-y += nvkm/subdev/devinit/g84.o +nvkm-y += nvkm/subdev/devinit/g98.o +nvkm-y += nvkm/subdev/devinit/gt215.o +nvkm-y += nvkm/subdev/devinit/mcp89.o +nvkm-y += nvkm/subdev/devinit/gf100.o +nvkm-y += nvkm/subdev/devinit/gm107.o +nvkm-y += nvkm/subdev/devinit/gm204.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c index 0e45cee82463..b0d7c5f40db1 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c @@ -21,17 +21,16 @@ * * Authors: Ben Skeggs */ +#include "priv.h" +#include <core/device.h> #include <core/option.h> - #include <subdev/vga.h> -#include "priv.h" - int -_nouveau_devinit_fini(struct nouveau_object *object, bool suspend) +_nvkm_devinit_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_devinit *devinit = (void *)object; + struct nvkm_devinit *devinit = (void *)object; /* force full reinit on resume */ if (suspend) @@ -40,17 +39,17 @@ _nouveau_devinit_fini(struct nouveau_object *object, bool suspend) /* unlock the extended vga crtc regs */ nv_lockvgac(devinit, false); - return nouveau_subdev_fini(&devinit->base, suspend); + return nvkm_subdev_fini(&devinit->base, suspend); } int -_nouveau_devinit_init(struct nouveau_object *object) +_nvkm_devinit_init(struct nvkm_object *object) { - struct nouveau_devinit_impl *impl = (void *)object->oclass; - struct nouveau_devinit *devinit = (void *)object; + struct nvkm_devinit_impl *impl = (void *)object->oclass; + struct nvkm_devinit *devinit = (void *)object; int ret; - ret = nouveau_subdev_init(&devinit->base); + ret = nvkm_subdev_init(&devinit->base); if (ret) return ret; @@ -64,34 +63,32 @@ _nouveau_devinit_init(struct nouveau_object *object) } void -_nouveau_devinit_dtor(struct nouveau_object *object) +_nvkm_devinit_dtor(struct nvkm_object *object) { - struct nouveau_devinit *devinit = (void *)object; + struct nvkm_devinit *devinit = (void *)object; /* lock crtc regs */ nv_lockvgac(devinit, true); - nouveau_subdev_destroy(&devinit->base); + nvkm_subdev_destroy(&devinit->base); } int -nouveau_devinit_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int size, void **pobject) +nvkm_devinit_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int size, void **pobject) { - struct nouveau_devinit_impl *impl = (void *)oclass; - struct nouveau_device *device = nv_device(parent); - struct nouveau_devinit *devinit; + struct nvkm_devinit_impl *impl = (void *)oclass; + struct nvkm_device *device = nv_device(parent); + struct nvkm_devinit *devinit; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "DEVINIT", - "init", size, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "DEVINIT", + "init", size, pobject); devinit = *pobject; if (ret) return ret; - devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false); + devinit->post = nvkm_boolopt(device->cfgopt, "NvForcePost", false); devinit->meminit = impl->meminit; devinit->pll_set = impl->pll_set; devinit->mmio = impl->mmio; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h index 6103484fea72..36684c3f9e9c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h @@ -23,9 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include <core/device.h> - #include <subdev/fb/regsnv04.h> #define NV04_PFB_DEBUG_0 0x00100080 @@ -48,7 +46,7 @@ # define NV10_PFB_REFCTRL_VALID_1 (1 << 31) static inline struct io_mapping * -fbmem_init(struct nouveau_device *dev) +fbmem_init(struct nvkm_device *dev) { return io_mapping_create_wc(nv_device_resource_start(dev, 1), nv_device_resource_len(dev, 1)); diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c index a7c80ded77cd..ca776ce75f4f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c @@ -21,11 +21,13 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" +#include <subdev/bios.h> +#include <subdev/bios/init.h> + static u64 -nv84_devinit_disable(struct nouveau_devinit *devinit) +g84_devinit_disable(struct nvkm_devinit *devinit) { struct nv50_devinit_priv *priv = (void *)devinit; u32 r001540 = nv_rd32(priv, 0x001540); @@ -36,7 +38,7 @@ nv84_devinit_disable(struct nouveau_devinit *devinit) disable |= (1ULL << NVDEV_ENGINE_MPEG); disable |= (1ULL << NVDEV_ENGINE_VP); disable |= (1ULL << NVDEV_ENGINE_BSP); - disable |= (1ULL << NVDEV_ENGINE_CRYPT); + disable |= (1ULL << NVDEV_ENGINE_CIPHER); } if (!(r00154c & 0x00000004)) @@ -44,21 +46,21 @@ nv84_devinit_disable(struct nouveau_devinit *devinit) if (!(r00154c & 0x00000020)) disable |= (1ULL << NVDEV_ENGINE_BSP); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVDEV_ENGINE_CRYPT); + disable |= (1ULL << NVDEV_ENGINE_CIPHER); return disable; } -struct nouveau_oclass * -nv84_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +g84_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x84), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_devinit_ctor, - .dtor = _nouveau_devinit_dtor, + .dtor = _nvkm_devinit_dtor, .init = nv50_devinit_init, - .fini = _nouveau_devinit_fini, + .fini = _nvkm_devinit_fini, }, .pll_set = nv50_devinit_pll_set, - .disable = nv84_devinit_disable, + .disable = g84_devinit_disable, .post = nvbios_init, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c index a773253a17f6..d29bacee65ee 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c @@ -21,11 +21,13 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" +#include <subdev/bios.h> +#include <subdev/bios/init.h> + static u64 -nv98_devinit_disable(struct nouveau_devinit *devinit) +g98_devinit_disable(struct nvkm_devinit *devinit) { struct nv50_devinit_priv *priv = (void *)devinit; u32 r001540 = nv_rd32(priv, 0x001540); @@ -33,31 +35,31 @@ nv98_devinit_disable(struct nouveau_devinit *devinit) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVDEV_ENGINE_VP); - disable |= (1ULL << NVDEV_ENGINE_BSP); - disable |= (1ULL << NVDEV_ENGINE_PPP); + disable |= (1ULL << NVDEV_ENGINE_MSPDEC); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); + disable |= (1ULL << NVDEV_ENGINE_MSPPP); } if (!(r00154c & 0x00000004)) disable |= (1ULL << NVDEV_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVDEV_ENGINE_CRYPT); + disable |= (1ULL << NVDEV_ENGINE_SEC); return disable; } -struct nouveau_oclass * -nv98_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +g98_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x98), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_devinit_ctor, - .dtor = _nouveau_devinit_dtor, + .dtor = _nvkm_devinit_dtor, .init = nv50_devinit_init, - .fini = _nouveau_devinit_fini, + .fini = _nvkm_devinit_fini, }, .pll_set = nv50_devinit_pll_set, - .disable = nv98_devinit_disable, + .disable = g98_devinit_disable, .post = nvbios_init, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c index 80bd7f5eda3d..e8778c67578e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c @@ -21,14 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" +#include <subdev/bios.h> +#include <subdev/bios/init.h> +#include <subdev/bios/pll.h> +#include <subdev/clk/pll.h> + int -nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) +gf100_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq) { struct nv50_devinit_priv *priv = (void *)devinit; - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_pll info; int N, fN, M, P; int ret; @@ -37,7 +41,7 @@ nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) if (ret) return ret; - ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P); + ret = gt215_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P); if (ret < 0) return ret; @@ -60,7 +64,7 @@ nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) } static u64 -nvc0_devinit_disable(struct nouveau_devinit *devinit) +gf100_devinit_disable(struct nvkm_devinit *devinit) { struct nv50_devinit_priv *priv = (void *)devinit; u32 r022500 = nv_rd32(priv, 0x022500); @@ -70,50 +74,51 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit) disable |= (1ULL << NVDEV_ENGINE_DISP); if (r022500 & 0x00000002) { - disable |= (1ULL << NVDEV_ENGINE_VP); - disable |= (1ULL << NVDEV_ENGINE_PPP); + disable |= (1ULL << NVDEV_ENGINE_MSPDEC); + disable |= (1ULL << NVDEV_ENGINE_MSPPP); } if (r022500 & 0x00000004) - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (r022500 & 0x00000008) - disable |= (1ULL << NVDEV_ENGINE_VENC); + disable |= (1ULL << NVDEV_ENGINE_MSENC); if (r022500 & 0x00000100) - disable |= (1ULL << NVDEV_ENGINE_COPY0); + disable |= (1ULL << NVDEV_ENGINE_CE0); if (r022500 & 0x00000200) - disable |= (1ULL << NVDEV_ENGINE_COPY1); + disable |= (1ULL << NVDEV_ENGINE_CE1); return disable; } static int -nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_devinit_priv *priv; int ret; - ret = nouveau_devinit_create(parent, engine, oclass, &priv); + ret = nvkm_devinit_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; if (nv_rd32(priv, 0x022500) & 0x00000001) priv->base.post = true; + return 0; } -struct nouveau_oclass * -nvc0_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +gf100_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_devinit_ctor, - .dtor = _nouveau_devinit_dtor, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_devinit_ctor, + .dtor = _nvkm_devinit_dtor, .init = nv50_devinit_init, - .fini = _nouveau_devinit_fini, + .fini = _nvkm_devinit_fini, }, - .pll_set = nvc0_devinit_pll_set, - .disable = nvc0_devinit_disable, + .pll_set = gf100_devinit_pll_set, + .disable = gf100_devinit_disable, .post = nvbios_init, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c index 4ba43d6a1ec8..b345a53e881d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c @@ -21,11 +21,13 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" +#include <subdev/bios.h> +#include <subdev/bios/init.h> + u64 -gm107_devinit_disable(struct nouveau_devinit *devinit) +gm107_devinit_disable(struct nvkm_devinit *devinit) { struct nv50_devinit_priv *priv = (void *)devinit; u32 r021c00 = nv_rd32(priv, 0x021c00); @@ -33,25 +35,25 @@ gm107_devinit_disable(struct nouveau_devinit *devinit) u64 disable = 0ULL; if (r021c00 & 0x00000001) - disable |= (1ULL << NVDEV_ENGINE_COPY0); + disable |= (1ULL << NVDEV_ENGINE_CE0); if (r021c00 & 0x00000004) - disable |= (1ULL << NVDEV_ENGINE_COPY2); + disable |= (1ULL << NVDEV_ENGINE_CE2); if (r021c04 & 0x00000001) disable |= (1ULL << NVDEV_ENGINE_DISP); return disable; } -struct nouveau_oclass * -gm107_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +gm107_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x07), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_devinit_ctor, - .dtor = _nouveau_devinit_dtor, + .dtor = _nvkm_devinit_dtor, .init = nv50_devinit_init, - .fini = _nouveau_devinit_fini, + .fini = _nvkm_devinit_fini, }, - .pll_set = nvc0_devinit_pll_set, + .pll_set = gf100_devinit_pll_set, .disable = gm107_devinit_disable, .post = nvbios_init, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c index e44a86662a2a..535172c5f1ad 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c @@ -21,17 +21,16 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/pmu.h> -#include "nv50.h" - static void pmu_code(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len, bool sec) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); int i; nv_wr32(priv, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu); @@ -50,7 +49,7 @@ pmu_code(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len, bool sec) static void pmu_data(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); int i; nv_wr32(priv, 0x10a1c0, 0x01000000 | pmu); @@ -78,7 +77,7 @@ static int pmu_load(struct nv50_devinit_priv *priv, u8 type, bool post, u32 *init_addr_pmu, u32 *args_addr_pmu) { - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_pmuR pmu; if (!nvbios_pmuRm(bios, type, &pmu)) { @@ -103,10 +102,10 @@ pmu_load(struct nv50_devinit_priv *priv, u8 type, bool post, } static int -gm204_devinit_post(struct nouveau_subdev *subdev, bool post) +gm204_devinit_post(struct nvkm_subdev *subdev, bool post) { - struct nv50_devinit_priv *priv = (void *)nouveau_devinit(subdev); - struct nouveau_bios *bios = nouveau_bios(priv); + struct nv50_devinit_priv *priv = (void *)nvkm_devinit(subdev); + struct nvkm_bios *bios = nvkm_bios(priv); struct bit_entry bit_I; u32 init, args; int ret; @@ -158,16 +157,16 @@ gm204_devinit_post(struct nouveau_subdev *subdev, bool post) return pmu_load(priv, 0x01, post, NULL, NULL); } -struct nouveau_oclass * -gm204_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +gm204_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x07), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_devinit_ctor, - .dtor = _nouveau_devinit_dtor, + .dtor = _nvkm_devinit_dtor, .init = nv50_devinit_init, - .fini = _nouveau_devinit_fini, + .fini = _nvkm_devinit_fini, }, - .pll_set = nvc0_devinit_pll_set, + .pll_set = gf100_devinit_pll_set, .disable = gm107_devinit_disable, .post = gm204_devinit_post, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c index b9cd9e53f760..6a3e8d4efed7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c @@ -21,14 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" +#include <subdev/bios.h> +#include <subdev/bios/init.h> +#include <subdev/bios/pll.h> +#include <subdev/clk/pll.h> + int -nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) +gt215_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq) { struct nv50_devinit_priv *priv = (void *)devinit; - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_pll info; int N, fN, M, P; int ret; @@ -37,7 +41,7 @@ nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) if (ret) return ret; - ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P); + ret = gt215_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P); if (ret < 0) return ret; @@ -59,7 +63,7 @@ nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) } static u64 -nva3_devinit_disable(struct nouveau_devinit *devinit) +gt215_devinit_disable(struct nvkm_devinit *devinit) { struct nv50_devinit_priv *priv = (void *)devinit; u32 r001540 = nv_rd32(priv, 0x001540); @@ -67,22 +71,22 @@ nva3_devinit_disable(struct nouveau_devinit *devinit) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVDEV_ENGINE_VP); - disable |= (1ULL << NVDEV_ENGINE_PPP); + disable |= (1ULL << NVDEV_ENGINE_MSPDEC); + disable |= (1ULL << NVDEV_ENGINE_MSPPP); } if (!(r00154c & 0x00000004)) disable |= (1ULL << NVDEV_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVDEV_ENGINE_COPY0); + disable |= (1ULL << NVDEV_ENGINE_CE0); return disable; } static u32 -nva3_devinit_mmio_part[] = { +gt215_devinit_mmio_part[] = { 0x100720, 0x1008bc, 4, 0x100a20, 0x100adc, 4, 0x100d80, 0x100ddc, 4, @@ -95,10 +99,10 @@ nva3_devinit_mmio_part[] = { }; static u32 -nva3_devinit_mmio(struct nouveau_devinit *devinit, u32 addr) +gt215_devinit_mmio(struct nvkm_devinit *devinit, u32 addr) { struct nv50_devinit_priv *priv = (void *)devinit; - u32 *mmio = nva3_devinit_mmio_part; + u32 *mmio = gt215_devinit_mmio_part; /* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP * instructions which touch registers that may not even exist on @@ -130,17 +134,17 @@ nva3_devinit_mmio(struct nouveau_devinit *devinit, u32 addr) return addr; } -struct nouveau_oclass * -nva3_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +gt215_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0xa3), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_devinit_ctor, - .dtor = _nouveau_devinit_dtor, + .dtor = _nvkm_devinit_dtor, .init = nv50_devinit_init, - .fini = _nouveau_devinit_fini, + .fini = _nvkm_devinit_fini, }, - .pll_set = nva3_devinit_pll_set, - .disable = nva3_devinit_disable, - .mmio = nva3_devinit_mmio, + .pll_set = gt215_devinit_pll_set, + .disable = gt215_devinit_disable, + .mmio = gt215_devinit_mmio, .post = nvbios_init, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c index 3729846a8e5c..55cf48bbca1c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c @@ -21,11 +21,13 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" +#include <subdev/bios.h> +#include <subdev/bios/init.h> + static u64 -nvaf_devinit_disable(struct nouveau_devinit *devinit) +mcp89_devinit_disable(struct nvkm_devinit *devinit) { struct nv50_devinit_priv *priv = (void *)devinit; u32 r001540 = nv_rd32(priv, 0x001540); @@ -33,32 +35,32 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit) u64 disable = 0; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVDEV_ENGINE_VP); - disable |= (1ULL << NVDEV_ENGINE_PPP); + disable |= (1ULL << NVDEV_ENGINE_MSPDEC); + disable |= (1ULL << NVDEV_ENGINE_MSPPP); } if (!(r00154c & 0x00000004)) disable |= (1ULL << NVDEV_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (!(r00154c & 0x00000040)) disable |= (1ULL << NVDEV_ENGINE_VIC); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVDEV_ENGINE_COPY0); + disable |= (1ULL << NVDEV_ENGINE_CE0); return disable; } -struct nouveau_oclass * -nvaf_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +mcp89_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0xaf), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_devinit_ctor, - .dtor = _nouveau_devinit_dtor, + .dtor = _nvkm_devinit_dtor, .init = nv50_devinit_init, - .fini = _nouveau_devinit_fini, + .fini = _nvkm_devinit_fini, }, - .pll_set = nva3_devinit_pll_set, - .disable = nvaf_devinit_disable, + .pll_set = gt215_devinit_pll_set, + .disable = mcp89_devinit_disable, .post = nvbios_init, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c index 65651c50f6ea..03a0da834244 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c @@ -23,14 +23,17 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ +#include "nv04.h" +#include "fbmem.h" +#include <subdev/bios.h> +#include <subdev/bios/init.h> +#include <subdev/bios/pll.h> +#include <subdev/clk/pll.h> #include <subdev/vga.h> -#include "fbmem.h" -#include "nv04.h" - static void -nv04_devinit_meminit(struct nouveau_devinit *devinit) +nv04_devinit_meminit(struct nvkm_devinit *devinit) { struct nv04_devinit_priv *priv = (void *)devinit; u32 patt = 0xdeadbeef; @@ -136,10 +139,10 @@ powerctrl_1_shift(int chip_version, int reg) } void -setPLL_single(struct nouveau_devinit *devinit, u32 reg, - struct nouveau_pll_vals *pv) +setPLL_single(struct nvkm_devinit *devinit, u32 reg, + struct nvkm_pll_vals *pv) { - int chip_version = nouveau_bios(devinit)->version.chip; + int chip_version = nvkm_bios(devinit)->version.chip; uint32_t oldpll = nv_rd32(devinit, reg); int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; @@ -190,10 +193,10 @@ new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) } void -setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1, - struct nouveau_pll_vals *pv) +setPLL_double_highregs(struct nvkm_devinit *devinit, u32 reg1, + struct nvkm_pll_vals *pv) { - int chip_version = nouveau_bios(devinit)->version.chip; + int chip_version = nvkm_bios(devinit)->version.chip; bool nv3035 = chip_version == 0x30 || chip_version == 0x35; uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); uint32_t oldpll1 = nv_rd32(devinit, reg1); @@ -267,8 +270,8 @@ setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1, } void -setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg, - struct nouveau_pll_vals *pv) +setPLL_double_lowregs(struct nvkm_devinit *devinit, u32 NMNMreg, + struct nvkm_pll_vals *pv) { /* When setting PLLs, there is a merry game of disabling and enabling * various bits of hardware during the process. This function is a @@ -301,7 +304,7 @@ setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg, struct nvbios_pll info; uint8_t Pval2; - if (nvbios_pll_parse(nouveau_bios(devinit), Preg, &info)) + if (nvbios_pll_parse(nvkm_bios(devinit), Preg, &info)) return; Pval2 = pv->log2P + info.bias_p; @@ -347,10 +350,10 @@ setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg, } int -nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) +nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq) { - struct nouveau_bios *bios = nouveau_bios(devinit); - struct nouveau_pll_vals pv; + struct nvkm_bios *bios = nvkm_bios(devinit); + struct nvkm_pll_vals pv; struct nvbios_pll info; int cv = bios->version.chip; int N1, M1, N2, M2, P; @@ -361,7 +364,7 @@ nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) return ret; ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, - &N1, &M1, &N2, &M2, &P); + &N1, &M1, &N2, &M2, &P); if (!ret) return -EINVAL; @@ -385,7 +388,7 @@ nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) } int -nv04_devinit_fini(struct nouveau_object *object, bool suspend) +nv04_devinit_fini(struct nvkm_object *object, bool suspend) { struct nv04_devinit_priv *priv = (void *)object; int ret; @@ -393,7 +396,7 @@ nv04_devinit_fini(struct nouveau_object *object, bool suspend) /* make i2c busses accessible */ nv_mask(priv, 0x000200, 0x00000001, 0x00000001); - ret = nouveau_devinit_fini(&priv->base, suspend); + ret = nvkm_devinit_fini(&priv->base, suspend); if (ret) return ret; @@ -401,12 +404,11 @@ nv04_devinit_fini(struct nouveau_object *object, bool suspend) if (priv->owner < 0) priv->owner = nv_rdvgaowner(priv); nv_wrvgaowner(priv, 0); - return 0; } int -nv04_devinit_init(struct nouveau_object *object) +nv04_devinit_init(struct nvkm_object *object) { struct nv04_devinit_priv *priv = (void *)object; @@ -422,29 +424,29 @@ nv04_devinit_init(struct nouveau_object *object) } } - return nouveau_devinit_init(&priv->base); + return nvkm_devinit_init(&priv->base); } void -nv04_devinit_dtor(struct nouveau_object *object) +nv04_devinit_dtor(struct nvkm_object *object) { struct nv04_devinit_priv *priv = (void *)object; /* restore vga owner saved at first init */ nv_wrvgaowner(priv, priv->owner); - nouveau_devinit_destroy(&priv->base); + nvkm_devinit_destroy(&priv->base); } int -nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_devinit_priv *priv; int ret; - ret = nouveau_devinit_create(parent, engine, oclass, &priv); + ret = nvkm_devinit_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -453,10 +455,10 @@ nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * -nv04_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +nv04_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x04), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_devinit_ctor, .dtor = nv04_devinit_dtor, .init = nv04_devinit_init, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h new file mode 100644 index 000000000000..14a51a9ff7d0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h @@ -0,0 +1,22 @@ +#ifndef __NVKM_DEVINIT_NV04_H__ +#define __NVKM_DEVINIT_NV04_H__ +#include "priv.h" +struct nvkm_pll_vals; + +struct nv04_devinit_priv { + struct nvkm_devinit base; + u8 owner; +}; + +int nv04_devinit_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nv04_devinit_dtor(struct nvkm_object *); +int nv04_devinit_init(struct nvkm_object *); +int nv04_devinit_fini(struct nvkm_object *, bool); +int nv04_devinit_pll_set(struct nvkm_devinit *, u32, u32); + +void setPLL_single(struct nvkm_devinit *, u32, struct nvkm_pll_vals *); +void setPLL_double_highregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *); +void setPLL_double_lowregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c index a2007a3efc4d..def8649216c2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c @@ -23,16 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ +#include "nv04.h" +#include "fbmem.h" #include <subdev/bios.h> #include <subdev/bios/bmp.h> +#include <subdev/bios/init.h> #include <subdev/vga.h> -#include "fbmem.h" -#include "nv04.h" - static void -nv05_devinit_meminit(struct nouveau_devinit *devinit) +nv05_devinit_meminit(struct nvkm_devinit *devinit) { static const u8 default_config_tab[][2] = { { 0x24, 0x00 }, @@ -45,7 +45,7 @@ nv05_devinit_meminit(struct nouveau_devinit *devinit) { 0x00, 0x00 } }; struct nv04_devinit_priv *priv = (void *)devinit; - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct io_mapping *fb; u32 patt = 0xdeadbeef; u16 data; @@ -125,10 +125,10 @@ out: fbmem_fini(fb); } -struct nouveau_oclass * -nv05_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +nv05_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x05), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_devinit_ctor, .dtor = nv04_devinit_dtor, .init = nv04_devinit_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c index 178b46f79b50..7aabc1bf0640 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c @@ -23,14 +23,14 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - -#include <subdev/vga.h> - -#include "fbmem.h" #include "nv04.h" +#include "fbmem.h" + +#include <subdev/bios.h> +#include <subdev/bios/init.h> static void -nv10_devinit_meminit(struct nouveau_devinit *devinit) +nv10_devinit_meminit(struct nvkm_devinit *devinit) { struct nv04_devinit_priv *priv = (void *)devinit; static const int mem_width[] = { 0x10, 0x00, 0x20 }; @@ -96,10 +96,10 @@ amount_found: fbmem_fini(fb); } -struct nouveau_oclass * -nv10_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +nv10_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x10), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_devinit_ctor, .dtor = nv04_devinit_dtor, .init = nv04_devinit_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c index 995dd97af3e9..9f36fff5a1c3 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c @@ -21,13 +21,15 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" -struct nouveau_oclass * -nv1a_devinit_oclass = &(struct nouveau_devinit_impl) { +#include <subdev/bios.h> +#include <subdev/bios/init.h> + +struct nvkm_oclass * +nv1a_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x1a), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_devinit_ctor, .dtor = nv04_devinit_dtor, .init = nv04_devinit_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c index 915089fb46f7..02fcfd921c42 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c @@ -23,15 +23,17 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" #include "fbmem.h" +#include <subdev/bios.h> +#include <subdev/bios/init.h> + static void -nv20_devinit_meminit(struct nouveau_devinit *devinit) +nv20_devinit_meminit(struct nvkm_devinit *devinit) { struct nv04_devinit_priv *priv = (void *)devinit; - struct nouveau_device *device = nv_device(priv); + struct nvkm_device *device = nv_device(priv); uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900); uint32_t amount, off; struct io_mapping *fb; @@ -60,10 +62,10 @@ nv20_devinit_meminit(struct nouveau_devinit *devinit) fbmem_fini(fb); } -struct nouveau_oclass * -nv20_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +nv20_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x20), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_devinit_ctor, .dtor = nv04_devinit_dtor, .init = nv04_devinit_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c index 968334d1dca4..26b7cb13e167 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c @@ -21,21 +21,22 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" #include <subdev/bios.h> #include <subdev/bios/dcb.h> #include <subdev/bios/disp.h> #include <subdev/bios/init.h> +#include <subdev/bios/pll.h> +#include <subdev/clk/pll.h> #include <subdev/ibus.h> #include <subdev/vga.h> -#include "nv50.h" - int -nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) +nv50_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq) { struct nv50_devinit_priv *priv = (void *)devinit; - struct nouveau_bios *bios = nouveau_bios(priv); + struct nvkm_bios *bios = nvkm_bios(priv); struct nvbios_pll info; int N1, M1, N2, M2, P; int ret; @@ -76,7 +77,7 @@ nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) } static u64 -nv50_devinit_disable(struct nouveau_devinit *devinit) +nv50_devinit_disable(struct nvkm_devinit *devinit) { struct nv50_devinit_priv *priv = (void *)devinit; u32 r001540 = nv_rd32(priv, 0x001540); @@ -89,10 +90,10 @@ nv50_devinit_disable(struct nouveau_devinit *devinit) } int -nv50_devinit_init(struct nouveau_object *object) +nv50_devinit_init(struct nvkm_object *object) { - struct nouveau_bios *bios = nouveau_bios(object); - struct nouveau_ibus *ibus = nouveau_ibus(object); + struct nvkm_bios *bios = nvkm_bios(object); + struct nvkm_ibus *ibus = nvkm_ibus(object); struct nv50_devinit_priv *priv = (void *)object; struct nvbios_outp info; struct dcb_output outp; @@ -114,7 +115,7 @@ nv50_devinit_init(struct nouveau_object *object) if (priv->base.post && ibus) nv_ofuncs(ibus)->init(nv_object(ibus)); - ret = nouveau_devinit_init(&priv->base); + ret = nvkm_devinit_init(&priv->base); if (ret) return ret; @@ -124,7 +125,7 @@ nv50_devinit_init(struct nouveau_object *object) */ while (priv->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) { if (nvbios_outp_match(bios, outp.hasht, outp.hashm, - &ver, &hdr, &cnt, &len, &info)) { + &ver, &hdr, &cnt, &len, &info)) { struct nvbios_init init = { .subdev = nv_subdev(priv), .bios = bios, @@ -143,14 +144,14 @@ nv50_devinit_init(struct nouveau_object *object) } int -nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_devinit_priv *priv; int ret; - ret = nouveau_devinit_create(parent, engine, oclass, &priv); + ret = nvkm_devinit_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -158,14 +159,14 @@ nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * -nv50_devinit_oclass = &(struct nouveau_devinit_impl) { +struct nvkm_oclass * +nv50_devinit_oclass = &(struct nvkm_devinit_impl) { .base.handle = NV_SUBDEV(DEVINIT, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_devinit_ctor, - .dtor = _nouveau_devinit_dtor, + .dtor = _nvkm_devinit_dtor, .init = nv50_devinit_init, - .fini = _nouveau_devinit_fini, + .fini = _nvkm_devinit_fini, }, .pll_set = nv50_devinit_pll_set, .disable = nv50_devinit_disable, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h new file mode 100644 index 000000000000..b882b65ff3cd --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h @@ -0,0 +1,21 @@ +#ifndef __NVKM_DEVINIT_NV50_H__ +#define __NVKM_DEVINIT_NV50_H__ +#include "priv.h" + +struct nv50_devinit_priv { + struct nvkm_devinit base; + u32 r001540; +}; + +int nv50_devinit_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +int nv50_devinit_init(struct nvkm_object *); +int nv50_devinit_pll_set(struct nvkm_devinit *, u32, u32); + +int gt215_devinit_pll_set(struct nvkm_devinit *, u32, u32); + +int gf100_devinit_pll_set(struct nvkm_devinit *, u32, u32); + +u64 gm107_devinit_disable(struct nvkm_devinit *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h new file mode 100644 index 000000000000..bb51a95d8012 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h @@ -0,0 +1,34 @@ +#ifndef __NVKM_DEVINIT_PRIV_H__ +#define __NVKM_DEVINIT_PRIV_H__ +#include <subdev/devinit.h> + +struct nvkm_devinit_impl { + struct nvkm_oclass base; + void (*meminit)(struct nvkm_devinit *); + int (*pll_set)(struct nvkm_devinit *, u32 type, u32 freq); + u64 (*disable)(struct nvkm_devinit *); + u32 (*mmio)(struct nvkm_devinit *, u32); + int (*post)(struct nvkm_subdev *, bool); +}; + +#define nvkm_devinit_create(p,e,o,d) \ + nvkm_devinit_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_devinit_destroy(p) ({ \ + struct nvkm_devinit *d = (p); \ + _nvkm_devinit_dtor(nv_object(d)); \ +}) +#define nvkm_devinit_init(p) ({ \ + struct nvkm_devinit *d = (p); \ + _nvkm_devinit_init(nv_object(d)); \ +}) +#define nvkm_devinit_fini(p,s) ({ \ + struct nvkm_devinit *d = (p); \ + _nvkm_devinit_fini(nv_object(d), (s)); \ +}) + +int nvkm_devinit_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_devinit_dtor(struct nvkm_object *); +int _nvkm_devinit_init(struct nvkm_object *); +int _nvkm_devinit_fini(struct nvkm_object *, bool suspend); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild new file mode 100644 index 000000000000..904d601e8a50 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild @@ -0,0 +1,45 @@ +nvkm-y += nvkm/subdev/fb/base.o +nvkm-y += nvkm/subdev/fb/nv04.o +nvkm-y += nvkm/subdev/fb/nv10.o +nvkm-y += nvkm/subdev/fb/nv1a.o +nvkm-y += nvkm/subdev/fb/nv20.o +nvkm-y += nvkm/subdev/fb/nv25.o +nvkm-y += nvkm/subdev/fb/nv30.o +nvkm-y += nvkm/subdev/fb/nv35.o +nvkm-y += nvkm/subdev/fb/nv36.o +nvkm-y += nvkm/subdev/fb/nv40.o +nvkm-y += nvkm/subdev/fb/nv41.o +nvkm-y += nvkm/subdev/fb/nv44.o +nvkm-y += nvkm/subdev/fb/nv46.o +nvkm-y += nvkm/subdev/fb/nv47.o +nvkm-y += nvkm/subdev/fb/nv49.o +nvkm-y += nvkm/subdev/fb/nv4e.o +nvkm-y += nvkm/subdev/fb/nv50.o +nvkm-y += nvkm/subdev/fb/g84.o +nvkm-y += nvkm/subdev/fb/gt215.o +nvkm-y += nvkm/subdev/fb/mcp77.o +nvkm-y += nvkm/subdev/fb/mcp89.o +nvkm-y += nvkm/subdev/fb/gf100.o +nvkm-y += nvkm/subdev/fb/gk104.o +nvkm-y += nvkm/subdev/fb/gk20a.o +nvkm-y += nvkm/subdev/fb/gm107.o +nvkm-y += nvkm/subdev/fb/ramnv04.o +nvkm-y += nvkm/subdev/fb/ramnv10.o +nvkm-y += nvkm/subdev/fb/ramnv1a.o +nvkm-y += nvkm/subdev/fb/ramnv20.o +nvkm-y += nvkm/subdev/fb/ramnv40.o +nvkm-y += nvkm/subdev/fb/ramnv41.o +nvkm-y += nvkm/subdev/fb/ramnv44.o +nvkm-y += nvkm/subdev/fb/ramnv49.o +nvkm-y += nvkm/subdev/fb/ramnv4e.o +nvkm-y += nvkm/subdev/fb/ramnv50.o +nvkm-y += nvkm/subdev/fb/ramgt215.o +nvkm-y += nvkm/subdev/fb/rammcp77.o +nvkm-y += nvkm/subdev/fb/ramgf100.o +nvkm-y += nvkm/subdev/fb/ramgk104.o +nvkm-y += nvkm/subdev/fb/ramgk20a.o +nvkm-y += nvkm/subdev/fb/ramgm107.o +nvkm-y += nvkm/subdev/fb/sddr2.o +nvkm-y += nvkm/subdev/fb/sddr3.o +nvkm-y += nvkm/subdev/fb/gddr3.o +nvkm-y += nvkm/subdev/fb/gddr5.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c index c866148c440f..16589fa613cd 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c @@ -21,14 +21,13 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/bios.h> #include <subdev/bios/M0203.h> -#include "priv.h" - int -nouveau_fb_bios_memtype(struct nouveau_bios *bios) +nvkm_fb_bios_memtype(struct nvkm_bios *bios) { const u8 ramcfg = (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2; struct nvbios_M0203E M0203E; @@ -51,25 +50,25 @@ nouveau_fb_bios_memtype(struct nouveau_bios *bios) } int -_nouveau_fb_fini(struct nouveau_object *object, bool suspend) +_nvkm_fb_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_fb *pfb = (void *)object; + struct nvkm_fb *pfb = (void *)object; int ret; ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); if (ret && suspend) return ret; - return nouveau_subdev_fini(&pfb->base, suspend); + return nvkm_subdev_fini(&pfb->base, suspend); } int -_nouveau_fb_init(struct nouveau_object *object) +_nvkm_fb_init(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object; + struct nvkm_fb *pfb = (void *)object; int ret, i; - ret = nouveau_subdev_init(&pfb->base); + ret = nvkm_subdev_init(&pfb->base); if (ret) return ret; @@ -84,25 +83,25 @@ _nouveau_fb_init(struct nouveau_object *object) } void -_nouveau_fb_dtor(struct nouveau_object *object) +_nvkm_fb_dtor(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object; + struct nvkm_fb *pfb = (void *)object; int i; for (i = 0; i < pfb->tile.regions; i++) pfb->tile.fini(pfb, i, &pfb->tile.region[i]); - nouveau_mm_fini(&pfb->tags); - nouveau_mm_fini(&pfb->vram); + nvkm_mm_fini(&pfb->tags); + nvkm_mm_fini(&pfb->vram); - nouveau_object_ref(NULL, (struct nouveau_object **)&pfb->ram); - nouveau_subdev_destroy(&pfb->base); + nvkm_object_ref(NULL, (struct nvkm_object **)&pfb->ram); + nvkm_subdev_destroy(&pfb->base); } int -nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) +nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_fb_impl *impl = (void *)oclass; + struct nvkm_fb_impl *impl = (void *)oclass; static const char *name[] = { [NV_MEM_TYPE_UNKNOWN] = "unknown", [NV_MEM_TYPE_STOLEN ] = "stolen system memory", @@ -116,38 +115,35 @@ nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine, [NV_MEM_TYPE_GDDR4 ] = "GDDR4", [NV_MEM_TYPE_GDDR5 ] = "GDDR5", }; - struct nouveau_object *ram; - struct nouveau_fb *pfb; + struct nvkm_object *ram; + struct nvkm_fb *pfb; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PFB", "fb", - length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PFB", "fb", + length, pobject); pfb = *pobject; if (ret) return ret; pfb->memtype_valid = impl->memtype; - ret = nouveau_object_ctor(nv_object(pfb), nv_object(pfb), - impl->ram, NULL, 0, &ram); + ret = nvkm_object_ctor(nv_object(pfb), NULL, impl->ram, NULL, 0, &ram); if (ret) { nv_fatal(pfb, "error detecting memory configuration!!\n"); return ret; } - atomic_dec(&ram->parent->refcount); - atomic_dec(&ram->engine->refcount); pfb->ram = (void *)ram; - if (!nouveau_mm_initialised(&pfb->vram)) { - ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1); + if (!nvkm_mm_initialised(&pfb->vram)) { + ret = nvkm_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1); if (ret) return ret; } - if (!nouveau_mm_initialised(&pfb->tags)) { - ret = nouveau_mm_init(&pfb->tags, 0, pfb->ram->tags ? - ++pfb->ram->tags : 0, 1); + if (!nvkm_mm_initialised(&pfb->tags)) { + ret = nvkm_mm_init(&pfb->tags, 0, pfb->ram->tags ? + ++pfb->ram->tags : 0, 1); if (ret) return ret; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c index cf0e767d3833..6c968d1e98b3 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c @@ -21,17 +21,16 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nouveau_oclass * -nv84_fb_oclass = &(struct nv50_fb_impl) { +struct nvkm_oclass * +g84_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x84), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c index d85a25d027ee..15b462ae33cb 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c @@ -22,8 +22,6 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> * Roy Spliet <rspliet@eclipso.eu> */ - -#include <subdev/bios.h> #include "priv.h" struct ramxlat { @@ -70,7 +68,7 @@ ramgddr3_wr_lo[] = { }; int -nouveau_gddr3_calc(struct nouveau_ram *ram) +nvkm_gddr3_calc(struct nvkm_ram *ram) { int CL, WR, CWL, DLL = 0, ODT = 0, hi; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c index 7fbbe05d5c60..f6f9eee1dcd0 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c @@ -21,8 +21,6 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include <subdev/bios.h> #include "priv.h" /* binary driver only executes this path if the condition (a) is true @@ -34,7 +32,7 @@ #define NOTE00(a) 1 int -nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts) +nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts) { int pd, lf, xd, vh, vr, vo, l3; int WL, CL, WR, at[2], dt, ds; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index 32f28dc73ef2..d51aa0237baf 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -21,22 +21,23 @@ * * Authors: Ben Skeggs */ +#include "gf100.h" -#include "nvc0.h" +#include <core/device.h> -extern const u8 nvc0_pte_storage_type_map[256]; +extern const u8 gf100_pte_storage_type_map[256]; bool -nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) +gf100_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags) { u8 memtype = (tile_flags & 0x0000ff00) >> 8; - return likely((nvc0_pte_storage_type_map[memtype] != 0xff)); + return likely((gf100_pte_storage_type_map[memtype] != 0xff)); } static void -nvc0_fb_intr(struct nouveau_subdev *subdev) +gf100_fb_intr(struct nvkm_subdev *subdev) { - struct nvc0_fb_priv *priv = (void *)subdev; + struct gf100_fb_priv *priv = (void *)subdev; u32 intr = nv_rd32(priv, 0x000100); if (intr & 0x08000000) { nv_debug(priv, "PFFB intr\n"); @@ -49,26 +50,27 @@ nvc0_fb_intr(struct nouveau_subdev *subdev) } int -nvc0_fb_init(struct nouveau_object *object) +gf100_fb_init(struct nvkm_object *object) { - struct nvc0_fb_priv *priv = (void *)object; + struct gf100_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; if (priv->r100c10_page) nv_wr32(priv, 0x100c10, priv->r100c10 >> 8); + nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ return 0; } void -nvc0_fb_dtor(struct nouveau_object *object) +gf100_fb_dtor(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); - struct nvc0_fb_priv *priv = (void *)object; + struct nvkm_device *device = nv_device(object); + struct gf100_fb_priv *priv = (void *)object; if (priv->r100c10_page) { dma_unmap_page(nv_device_base(device), priv->r100c10, PAGE_SIZE, @@ -76,19 +78,19 @@ nvc0_fb_dtor(struct nouveau_object *object) __free_page(priv->r100c10_page); } - nouveau_fb_destroy(&priv->base); + nvkm_fb_destroy(&priv->base); } int -nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); - struct nvc0_fb_priv *priv; + struct nvkm_device *device = nv_device(parent); + struct gf100_fb_priv *priv; int ret; - ret = nouveau_fb_create(parent, engine, oclass, &priv); + ret = nvkm_fb_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -102,19 +104,19 @@ nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return -EFAULT; } - nv_subdev(priv)->intr = nvc0_fb_intr; + nv_subdev(priv)->intr = gf100_fb_intr; return 0; } -struct nouveau_oclass * -nvc0_fb_oclass = &(struct nouveau_fb_impl) { +struct nvkm_oclass * +gf100_fb_oclass = &(struct nvkm_fb_impl) { .base.handle = NV_SUBDEV(FB, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fb_ctor, - .dtor = nvc0_fb_dtor, - .init = nvc0_fb_init, - .fini = _nouveau_fb_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fb_ctor, + .dtor = gf100_fb_dtor, + .init = gf100_fb_init, + .fini = _nvkm_fb_fini, }, - .memtype = nvc0_fb_memtype_valid, - .ram = &nvc0_ram_oclass, + .memtype = gf100_fb_memtype_valid, + .ram = &gf100_ram_oclass, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h new file mode 100644 index 000000000000..0af4da259471 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h @@ -0,0 +1,28 @@ +#ifndef __NVKM_RAM_NVC0_H__ +#define __NVKM_RAM_NVC0_H__ +#include "priv.h" +#include "nv50.h" + +struct gf100_fb_priv { + struct nvkm_fb base; + struct page *r100c10_page; + dma_addr_t r100c10; +}; + +int gf100_fb_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gf100_fb_dtor(struct nvkm_object *); +int gf100_fb_init(struct nvkm_object *); +bool gf100_fb_memtype_valid(struct nvkm_fb *, u32); + +#define gf100_ram_create(p,e,o,m,d) \ + gf100_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d) +int gf100_ram_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, u32, int, void **); +int gf100_ram_get(struct nvkm_fb *, u64, u32, u32, u32, + struct nvkm_mem **); +void gf100_ram_put(struct nvkm_fb *, struct nvkm_mem **); + +int gk104_ram_init(struct nvkm_object*); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c index 595db50cfef3..1c08317665bb 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c @@ -21,18 +21,17 @@ * * Authors: Ben Skeggs */ +#include "gf100.h" -#include "nvc0.h" - -struct nouveau_oclass * -nve0_fb_oclass = &(struct nouveau_fb_impl) { +struct nvkm_oclass * +gk104_fb_oclass = &(struct nvkm_fb_impl) { .base.handle = NV_SUBDEV(FB, 0xe0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fb_ctor, - .dtor = nvc0_fb_dtor, - .init = nvc0_fb_init, - .fini = _nouveau_fb_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fb_ctor, + .dtor = gf100_fb_dtor, + .init = gf100_fb_init, + .fini = _nvkm_fb_fini, }, - .memtype = nvc0_fb_memtype_valid, - .ram = &nve0_ram_oclass, + .memtype = gf100_fb_memtype_valid, + .ram = &gk104_ram_oclass, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c index fde42e4d1b56..6762847c05e8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c @@ -19,20 +19,19 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - -#include "nvc0.h" +#include "gf100.h" struct gk20a_fb_priv { - struct nouveau_fb base; + struct nvkm_fb base; }; static int -gk20a_fb_init(struct nouveau_object *object) +gk20a_fb_init(struct nvkm_object *object) { struct gk20a_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -41,14 +40,14 @@ gk20a_fb_init(struct nouveau_object *object) } static int -gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct gk20a_fb_priv *priv; int ret; - ret = nouveau_fb_create(parent, engine, oclass, &priv); + ret = nvkm_fb_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -56,15 +55,15 @@ gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * -gk20a_fb_oclass = &(struct nouveau_fb_impl) { +struct nvkm_oclass * +gk20a_fb_oclass = &(struct nvkm_fb_impl) { .base.handle = NV_SUBDEV(FB, 0xea), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gk20a_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = gk20a_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, - .memtype = nvc0_fb_memtype_valid, + .memtype = gf100_fb_memtype_valid, .ram = &gk20a_ram_oclass, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c index c4840aedc2dc..843f9356b360 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c @@ -21,18 +21,17 @@ * * Authors: Ben Skeggs */ +#include "gf100.h" -#include "nvc0.h" - -struct nouveau_oclass * -gm107_fb_oclass = &(struct nouveau_fb_impl) { +struct nvkm_oclass * +gm107_fb_oclass = &(struct nvkm_fb_impl) { .base.handle = NV_SUBDEV(FB, 0x07), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fb_ctor, - .dtor = nvc0_fb_dtor, - .init = nvc0_fb_init, - .fini = _nouveau_fb_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fb_ctor, + .dtor = gf100_fb_dtor, + .init = gf100_fb_init, + .fini = _nvkm_fb_fini, }, - .memtype = nvc0_fb_memtype_valid, + .memtype = gf100_fb_memtype_valid, .ram = &gm107_ram_oclass, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c index dab6e1c63d48..dd9b8a0a3c8e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nouveau_oclass * -nva3_fb_oclass = &(struct nv50_fb_impl) { +struct nvkm_oclass * +gt215_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0xa3), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &nva3_ram_oclass, + .base.ram = >215_ram_oclass, .trap = 0x000d0fff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c index cba8e6818035..7be4a47ef4ad 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nouveau_oclass * -nvaa_fb_oclass = &(struct nv50_fb_impl) { +struct nvkm_oclass * +mcp77_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0xaa), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &nvaa_ram_oclass, + .base.ram = &mcp77_ram_oclass, .trap = 0x001d07ff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c index 5423faa2c09b..2d00656faef5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nouveau_oclass * -nvaf_fb_oclass = &(struct nv50_fb_impl) { +struct nvkm_oclass * +mcp89_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0xaf), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &nvaa_ram_oclass, + .base.ram = &mcp77_ram_oclass, .trap = 0x089d1fff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c index 8309fe33fe84..c063dec7d03a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c @@ -21,13 +21,11 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" - -#define NV04_PFB_CFG0 0x00100200 +#include "regsnv04.h" bool -nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) +nv04_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags) { if (!(tile_flags & 0xff00)) return true; @@ -36,12 +34,12 @@ nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) } static int -nv04_fb_init(struct nouveau_object *object) +nv04_fb_init(struct nvkm_object *object) { struct nv04_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -54,15 +52,15 @@ nv04_fb_init(struct nouveau_object *object) } int -nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_fb_impl *impl = (void *)oclass; struct nv04_fb_priv *priv; int ret; - ret = nouveau_fb_create(parent, engine, oclass, &priv); + ret = nvkm_fb_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -75,14 +73,14 @@ nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv04_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x04), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv04_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv04_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h new file mode 100644 index 000000000000..caa0d03aaacc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h @@ -0,0 +1,53 @@ +#ifndef __NVKM_FB_NV04_H__ +#define __NVKM_FB_NV04_H__ +#include "priv.h" + +struct nv04_fb_priv { + struct nvkm_fb base; +}; + +int nv04_fb_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); + +struct nv04_fb_impl { + struct nvkm_fb_impl base; + struct { + int regions; + void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); + void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags, + struct nvkm_fb_tile *); + void (*fini)(struct nvkm_fb *, int i, + struct nvkm_fb_tile *); + void (*prog)(struct nvkm_fb *, int i, + struct nvkm_fb_tile *); + } tile; +}; + +void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); +void nv10_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *); +void nv10_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); + +void nv20_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); +void nv20_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *); +void nv20_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); + +int nv30_fb_init(struct nvkm_object *); +void nv30_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); + +void nv40_fb_tile_comp(struct nvkm_fb *, int i, u32 size, u32 flags, + struct nvkm_fb_tile *); + +int nv41_fb_init(struct nvkm_object *); +void nv41_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); + +int nv44_fb_init(struct nvkm_object *); +void nv44_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); + +void nv46_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c index ffb7ec6d97aa..f3530e4a6760 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c @@ -23,12 +23,11 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv10_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { tile->addr = 0x80000000 | addr; tile->limit = max(1u, addr + size) - 1; @@ -36,7 +35,7 @@ nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } void -nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv10_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { tile->addr = 0; tile->limit = 0; @@ -45,7 +44,7 @@ nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) } void -nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv10_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); @@ -53,14 +52,14 @@ nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) nv_rd32(pfb, 0x100240 + (i * 0x10)); } -struct nouveau_oclass * +struct nvkm_oclass * nv10_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x10), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, - .init = _nouveau_fb_init, - .fini = _nouveau_fb_fini, + .dtor = _nvkm_fb_dtor, + .init = _nvkm_fb_init, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv10_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c index 265d1253624a..83bcb73caf0a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" -struct nouveau_oclass * +struct nvkm_oclass * nv1a_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x1a), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, - .init = _nouveau_fb_init, - .fini = _nouveau_fb_fini, + .dtor = _nvkm_fb_dtor, + .init = _nvkm_fb_init, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv1a_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c index 2209ade63339..e37084b8d05e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c @@ -23,12 +23,11 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv20_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { tile->addr = 0x00000001 | addr; tile->limit = max(1u, addr + size) - 1; @@ -40,12 +39,12 @@ nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } static void -nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv20_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ else tile->zcomp = 0x04000000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -57,17 +56,17 @@ nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } void -nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv20_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { tile->addr = 0; tile->limit = 0; tile->pitch = 0; tile->zcomp = 0; - nouveau_mm_free(&pfb->tags, &tile->tag); + nvkm_mm_free(&pfb->tags, &tile->tag); } void -nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv20_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); @@ -76,14 +75,14 @@ nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp); } -struct nouveau_oclass * +struct nvkm_oclass * nv20_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x20), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, - .init = _nouveau_fb_init, - .fini = _nouveau_fb_fini, + .dtor = _nvkm_fb_dtor, + .init = _nvkm_fb_init, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c index e2a66c355c50..bc9f54f38fba 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c @@ -23,16 +23,15 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" static void -nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv25_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ else tile->zcomp = 0x00200000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -42,14 +41,14 @@ nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } } -struct nouveau_oclass * +struct nvkm_oclass * nv25_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x25), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, - .init = _nouveau_fb_init, - .fini = _nouveau_fb_fini, + .dtor = _nvkm_fb_dtor, + .init = _nvkm_fb_init, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c index cbec402ba5b9..09ebb9477e00 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c @@ -23,12 +23,13 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" +#include <core/device.h> + void -nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { /* for performance, select alternate bank offset for zeta */ if (!(flags & 4)) { @@ -46,12 +47,12 @@ nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } static void -nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv30_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ else tile->zcomp |= 0x02000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -65,7 +66,7 @@ nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, static int calc_bias(struct nv04_fb_priv *priv, int k, int i, int j) { - struct nouveau_device *device = nv_device(priv); + struct nvkm_device *device = nv_device(priv); int b = (device->chipset > 0x30 ? nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) : 0) & 0xf; @@ -88,13 +89,13 @@ calc_ref(struct nv04_fb_priv *priv, int l, int k, int i) } int -nv30_fb_init(struct nouveau_object *object) +nv30_fb_init(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); + struct nvkm_device *device = nv_device(object); struct nv04_fb_priv *priv = (void *)object; int ret, i, j; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -120,14 +121,14 @@ nv30_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv30_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x30), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv30_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c index b2cf8c69fb2e..c01dc1839ea4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c @@ -23,16 +23,15 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" static void -nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv35_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ else tile->zcomp |= 0x08000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -43,14 +42,14 @@ nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } } -struct nouveau_oclass * +struct nvkm_oclass * nv35_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x35), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv30_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c index b4cdae2a3b2f..cad75a1cef22 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c @@ -23,16 +23,15 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" static void -nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv36_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ else tile->zcomp |= 0x20000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -43,14 +42,14 @@ nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } } -struct nouveau_oclass * +struct nvkm_oclass * nv36_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x36), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv30_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c index 52814258c212..dbe5c1910c2c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv40_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x80); u32 tags = round_up(tiles / pfb->ram->parts, 0x100); if ( (flags & 2) && - !nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + !nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ tile->zcomp |= ((tile->tag->offset ) >> 8); tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; @@ -44,12 +43,12 @@ nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } static int -nv40_fb_init(struct nouveau_object *object) +nv40_fb_init(struct nvkm_object *object) { struct nv04_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -57,14 +56,14 @@ nv40_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv40_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x40), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv40_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv40_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h new file mode 100644 index 000000000000..602182661820 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h @@ -0,0 +1,14 @@ +#ifndef __NVKM_FB_NV40_H__ +#define __NVKM_FB_NV40_H__ +#include "priv.h" + +struct nv40_ram { + struct nvkm_ram base; + u32 ctrl; + u32 coef; +}; + +int nv40_ram_calc(struct nvkm_fb *, u32); +int nv40_ram_prog(struct nvkm_fb *); +void nv40_ram_tidy(struct nvkm_fb *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c index b239a8615599..d9e1a40a2955 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c @@ -23,11 +23,10 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv41_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); @@ -37,12 +36,12 @@ nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) } int -nv41_fb_init(struct nouveau_object *object) +nv41_fb_init(struct nvkm_object *object) { struct nv04_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -50,14 +49,14 @@ nv41_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv41_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x41), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv41_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv41_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c index d8478208a681..20b97c83c4af 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c @@ -23,12 +23,11 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" static void -nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv44_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { tile->addr = 0x00000001; /* mode = vram */ tile->addr |= addr; @@ -37,7 +36,7 @@ nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } void -nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv44_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); @@ -46,12 +45,12 @@ nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) } int -nv44_fb_init(struct nouveau_object *object) +nv44_fb_init(struct nvkm_object *object) { struct nv04_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -60,14 +59,14 @@ nv44_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv44_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x44), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv44_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv44_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c index a5b77514d35b..5bfac38cdf24 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c @@ -23,12 +23,11 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv46_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv46_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { /* for performance, select alternate bank offset for zeta */ if (!(flags & 4)) tile->addr = (0 << 3); @@ -40,14 +39,14 @@ nv46_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, tile->pitch = pitch; } -struct nouveau_oclass * +struct nvkm_oclass * nv46_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x46), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv44_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv44_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c index 3bea142376bc..d3b3988d1d49 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" -struct nouveau_oclass * +struct nvkm_oclass * nv47_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x47), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv41_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv41_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c index 666cbd5d47f5..236e36c5054e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" -struct nouveau_oclass * +struct nvkm_oclass * nv49_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x49), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv41_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv49_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c index 42e64f364ec1..1352b6a73fb0 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" -struct nouveau_oclass * +struct nvkm_oclass * nv4e_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x4e), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv44_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv4e_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 4150b0d10af8..0480ce52aa06 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -21,15 +21,12 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" #include <core/client.h> -#include <core/enum.h> +#include <core/device.h> #include <core/engctx.h> -#include <core/object.h> - -#include <subdev/bios.h> - -#include "nv50.h" +#include <core/enum.h> int nv50_fb_memtype[0x80] = { @@ -44,12 +41,12 @@ nv50_fb_memtype[0x80] = { }; bool -nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype) +nv50_fb_memtype_valid(struct nvkm_fb *pfb, u32 memtype) { return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0; } -static const struct nouveau_enum vm_dispatch_subclients[] = { +static const struct nvkm_enum vm_dispatch_subclients[] = { { 0x00000000, "GRCTX", NULL }, { 0x00000001, "NOTIFY", NULL }, { 0x00000002, "QUERY", NULL }, @@ -60,14 +57,14 @@ static const struct nouveau_enum vm_dispatch_subclients[] = { {} }; -static const struct nouveau_enum vm_ccache_subclients[] = { +static const struct nvkm_enum vm_ccache_subclients[] = { { 0x00000000, "CB", NULL }, { 0x00000001, "TIC", NULL }, { 0x00000002, "TSC", NULL }, {} }; -static const struct nouveau_enum vm_prop_subclients[] = { +static const struct nvkm_enum vm_prop_subclients[] = { { 0x00000000, "RT0", NULL }, { 0x00000001, "RT1", NULL }, { 0x00000002, "RT2", NULL }, @@ -84,24 +81,24 @@ static const struct nouveau_enum vm_prop_subclients[] = { {} }; -static const struct nouveau_enum vm_pfifo_subclients[] = { +static const struct nvkm_enum vm_pfifo_subclients[] = { { 0x00000000, "PUSHBUF", NULL }, { 0x00000001, "SEMAPHORE", NULL }, {} }; -static const struct nouveau_enum vm_bar_subclients[] = { +static const struct nvkm_enum vm_bar_subclients[] = { { 0x00000000, "FB", NULL }, { 0x00000001, "IN", NULL }, {} }; -static const struct nouveau_enum vm_client[] = { +static const struct nvkm_enum vm_client[] = { { 0x00000000, "STRMOUT", NULL }, { 0x00000003, "DISPATCH", vm_dispatch_subclients }, { 0x00000004, "PFIFO_WRITE", NULL }, { 0x00000005, "CCACHE", vm_ccache_subclients }, - { 0x00000006, "PPPP", NULL }, + { 0x00000006, "PMSPPP", NULL }, { 0x00000007, "CLIPID", NULL }, { 0x00000008, "PFIFO_READ", NULL }, { 0x00000009, "VFETCH", NULL }, @@ -115,24 +112,24 @@ static const struct nouveau_enum vm_client[] = { {} }; -static const struct nouveau_enum vm_engine[] = { +static const struct nvkm_enum vm_engine[] = { { 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR }, { 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP }, { 0x00000004, "PEEPHOLE", NULL }, { 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO }, { 0x00000006, "BAR", vm_bar_subclients }, - { 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP }, + { 0x00000008, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP }, { 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG }, { 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP }, - { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT }, + { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER }, { 0x0000000b, "PCOUNTER", NULL }, { 0x0000000c, "SEMAPHORE_BG", NULL }, - { 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 }, + { 0x0000000d, "PCE0", NULL, NVDEV_ENGINE_CE0 }, { 0x0000000e, "PDAEMON", NULL }, {} }; -static const struct nouveau_enum vm_fault[] = { +static const struct nvkm_enum vm_fault[] = { { 0x00000000, "PT_NOT_PRESENT", NULL }, { 0x00000001, "PT_TOO_SHORT", NULL }, { 0x00000002, "PAGE_NOT_PRESENT", NULL }, @@ -146,13 +143,13 @@ static const struct nouveau_enum vm_fault[] = { }; static void -nv50_fb_intr(struct nouveau_subdev *subdev) +nv50_fb_intr(struct nvkm_subdev *subdev) { - struct nouveau_device *device = nv_device(subdev); - struct nouveau_engine *engine; + struct nvkm_device *device = nv_device(subdev); + struct nvkm_engine *engine; struct nv50_fb_priv *priv = (void *)subdev; - const struct nouveau_enum *en, *cl; - struct nouveau_object *engctx = NULL; + const struct nvkm_enum *en, *cl; + struct nvkm_object *engctx = NULL; u32 trap[6], idx, chan; u8 st0, st1, st2, st3; int i; @@ -183,14 +180,21 @@ nv50_fb_intr(struct nouveau_subdev *subdev) } chan = (trap[2] << 16) | trap[1]; - en = nouveau_enum_find(vm_engine, st0); + en = nvkm_enum_find(vm_engine, st0); if (en && en->data2) { - const struct nouveau_enum *orig_en = en; + const struct nvkm_enum *orig_en = en; while (en->name && en->value == st0 && en->data2) { - engine = nouveau_engine(subdev, en->data2); + engine = nvkm_engine(subdev, en->data2); + /*XXX: clean this up */ + if (!engine && en->data2 == NVDEV_ENGINE_BSP) + engine = nvkm_engine(subdev, NVDEV_ENGINE_MSVLD); + if (!engine && en->data2 == NVDEV_ENGINE_CIPHER) + engine = nvkm_engine(subdev, NVDEV_ENGINE_SEC); + if (!engine && en->data2 == NVDEV_ENGINE_VP) + engine = nvkm_engine(subdev, NVDEV_ENGINE_MSPDEC); if (engine) { - engctx = nouveau_engctx_get(engine, chan); + engctx = nvkm_engctx_get(engine, chan); if (engctx) break; } @@ -203,23 +207,23 @@ nv50_fb_intr(struct nouveau_subdev *subdev) nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ", (trap[5] & 0x00000100) ? "read" : "write", trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan, - nouveau_client_name(engctx)); + nvkm_client_name(engctx)); - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); if (en) pr_cont("%s/", en->name); else pr_cont("%02x/", st0); - cl = nouveau_enum_find(vm_client, st2); + cl = nvkm_enum_find(vm_client, st2); if (cl) pr_cont("%s/", cl->name); else pr_cont("%02x/", st2); - if (cl && cl->data) cl = nouveau_enum_find(cl->data, st3); - else if (en && en->data) cl = nouveau_enum_find(en->data, st3); + if (cl && cl->data) cl = nvkm_enum_find(cl->data, st3); + else if (en && en->data) cl = nvkm_enum_find(en->data, st3); else cl = NULL; if (cl) pr_cont("%s", cl->name); @@ -227,7 +231,7 @@ nv50_fb_intr(struct nouveau_subdev *subdev) pr_cont("%02x", st3); pr_cont(" reason: "); - en = nouveau_enum_find(vm_fault, st1); + en = nvkm_enum_find(vm_fault, st1); if (en) pr_cont("%s\n", en->name); else @@ -235,15 +239,15 @@ nv50_fb_intr(struct nouveau_subdev *subdev) } int -nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); + struct nvkm_device *device = nv_device(parent); struct nv50_fb_priv *priv; int ret; - ret = nouveau_fb_create(parent, engine, oclass, &priv); + ret = nvkm_fb_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -264,9 +268,9 @@ nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } void -nv50_fb_dtor(struct nouveau_object *object) +nv50_fb_dtor(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); + struct nvkm_device *device = nv_device(object); struct nv50_fb_priv *priv = (void *)object; if (priv->r100c08_page) { @@ -275,17 +279,17 @@ nv50_fb_dtor(struct nouveau_object *object) __free_page(priv->r100c08_page); } - nouveau_fb_destroy(&priv->base); + nvkm_fb_destroy(&priv->base); } int -nv50_fb_init(struct nouveau_object *object) +nv50_fb_init(struct nvkm_object *object) { struct nv50_fb_impl *impl = (void *)object->oclass; struct nv50_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -301,14 +305,14 @@ nv50_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv50_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x50), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h new file mode 100644 index 000000000000..f3cde3f1f511 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h @@ -0,0 +1,31 @@ +#ifndef __NVKM_FB_NV50_H__ +#define __NVKM_FB_NV50_H__ +#include "priv.h" + +struct nv50_fb_priv { + struct nvkm_fb base; + struct page *r100c08_page; + dma_addr_t r100c08; +}; + +int nv50_fb_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nv50_fb_dtor(struct nvkm_object *); +int nv50_fb_init(struct nvkm_object *); + +struct nv50_fb_impl { + struct nvkm_fb_impl base; + u32 trap; +}; + +#define nv50_ram_create(p,e,o,d) \ + nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d) +int nv50_ram_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +int nv50_ram_get(struct nvkm_fb *, u64 size, u32 align, u32 ncmin, + u32 memtype, struct nvkm_mem **); +void nv50_ram_put(struct nvkm_fb *, struct nvkm_mem **); +void __nv50_ram_put(struct nvkm_fb *, struct nvkm_mem *); +extern int nv50_fb_memtype[0x80]; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h new file mode 100644 index 000000000000..d82da02daa1f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h @@ -0,0 +1,74 @@ +#ifndef __NVKM_FB_PRIV_H__ +#define __NVKM_FB_PRIV_H__ +#include <subdev/fb.h> +struct nvkm_bios; + +#define nvkm_ram_create(p,e,o,d) \ + nvkm_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d) +#define nvkm_ram_destroy(p) \ + nvkm_object_destroy(&(p)->base) +#define nvkm_ram_init(p) \ + nvkm_object_init(&(p)->base) +#define nvkm_ram_fini(p,s) \ + nvkm_object_fini(&(p)->base, (s)) + +#define nvkm_ram_create_(p,e,o,s,d) \ + nvkm_object_create_((p), (e), (o), 0, (s), (void **)d) +#define _nvkm_ram_dtor nvkm_object_destroy +#define _nvkm_ram_init nvkm_object_init +#define _nvkm_ram_fini nvkm_object_fini + +extern struct nvkm_oclass nv04_ram_oclass; +extern struct nvkm_oclass nv10_ram_oclass; +extern struct nvkm_oclass nv1a_ram_oclass; +extern struct nvkm_oclass nv20_ram_oclass; +extern struct nvkm_oclass nv40_ram_oclass; +extern struct nvkm_oclass nv41_ram_oclass; +extern struct nvkm_oclass nv44_ram_oclass; +extern struct nvkm_oclass nv49_ram_oclass; +extern struct nvkm_oclass nv4e_ram_oclass; +extern struct nvkm_oclass nv50_ram_oclass; +extern struct nvkm_oclass gt215_ram_oclass; +extern struct nvkm_oclass mcp77_ram_oclass; +extern struct nvkm_oclass gf100_ram_oclass; +extern struct nvkm_oclass gk104_ram_oclass; +extern struct nvkm_oclass gk20a_ram_oclass; +extern struct nvkm_oclass gm107_ram_oclass; + +int nvkm_sddr2_calc(struct nvkm_ram *ram); +int nvkm_sddr3_calc(struct nvkm_ram *ram); +int nvkm_gddr3_calc(struct nvkm_ram *ram); +int nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts); + +#define nvkm_fb_create(p,e,c,d) \ + nvkm_fb_create_((p), (e), (c), sizeof(**d), (void **)d) +#define nvkm_fb_destroy(p) ({ \ + struct nvkm_fb *pfb = (p); \ + _nvkm_fb_dtor(nv_object(pfb)); \ +}) +#define nvkm_fb_init(p) ({ \ + struct nvkm_fb *pfb = (p); \ + _nvkm_fb_init(nv_object(pfb)); \ +}) +#define nvkm_fb_fini(p,s) ({ \ + struct nvkm_fb *pfb = (p); \ + _nvkm_fb_fini(nv_object(pfb), (s)); \ +}) + +int nvkm_fb_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_fb_dtor(struct nvkm_object *); +int _nvkm_fb_init(struct nvkm_object *); +int _nvkm_fb_fini(struct nvkm_object *, bool); + +struct nvkm_fb_impl { + struct nvkm_oclass base; + struct nvkm_oclass *ram; + bool (*memtype)(struct nvkm_fb *, u32); +}; + +bool nv04_fb_memtype_valid(struct nvkm_fb *, u32 memtype); +bool nv50_fb_memtype_valid(struct nvkm_fb *, u32 memtype); + +int nvkm_fb_bios_memtype(struct nvkm_bios *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h index 0ac7256443bb..f343682b1387 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h @@ -1,11 +1,10 @@ #ifndef __NVKM_FBRAM_FUC_H__ #define __NVKM_FBRAM_FUC_H__ - -#include <subdev/pwr.h> +#include <subdev/pmu.h> struct ramfuc { - struct nouveau_memx *memx; - struct nouveau_fb *pfb; + struct nvkm_memx *memx; + struct nvkm_fb *pfb; int sequence; }; @@ -55,12 +54,12 @@ ramfuc_reg(u32 addr) } static inline int -ramfuc_init(struct ramfuc *ram, struct nouveau_fb *pfb) +ramfuc_init(struct ramfuc *ram, struct nvkm_fb *pfb) { - struct nouveau_pwr *ppwr = nouveau_pwr(pfb); + struct nvkm_pmu *pmu = nvkm_pmu(pfb); int ret; - ret = nouveau_memx_init(ppwr, &ram->memx); + ret = nvkm_memx_init(pmu, &ram->memx); if (ret) return ret; @@ -74,7 +73,7 @@ ramfuc_exec(struct ramfuc *ram, bool exec) { int ret = 0; if (ram->pfb) { - ret = nouveau_memx_fini(&ram->memx, exec); + ret = nvkm_memx_fini(&ram->memx, exec); ram->pfb = NULL; } return ret; @@ -97,10 +96,8 @@ ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data) reg->data = data; for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { - if (mask & 1) { - nouveau_memx_wr32(ram->memx, reg->addr+off, reg->data); - } - + if (mask & 1) + nvkm_memx_wr32(ram->memx, reg->addr+off, reg->data); off += reg->stride; } } @@ -125,45 +122,45 @@ ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) static inline void ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec) { - nouveau_memx_wait(ram->memx, addr, mask, data, nsec); + nvkm_memx_wait(ram->memx, addr, mask, data, nsec); } static inline void ramfuc_nsec(struct ramfuc *ram, u32 nsec) { - nouveau_memx_nsec(ram->memx, nsec); + nvkm_memx_nsec(ram->memx, nsec); } static inline void ramfuc_wait_vblank(struct ramfuc *ram) { - nouveau_memx_wait_vblank(ram->memx); + nvkm_memx_wait_vblank(ram->memx); } static inline void ramfuc_train(struct ramfuc *ram) { - nouveau_memx_train(ram->memx); + nvkm_memx_train(ram->memx); } static inline int -ramfuc_train_result(struct nouveau_fb *pfb, u32 *result, u32 rsize) +ramfuc_train_result(struct nvkm_fb *pfb, u32 *result, u32 rsize) { - struct nouveau_pwr *ppwr = nouveau_pwr(pfb); + struct nvkm_pmu *pmu = nvkm_pmu(pfb); - return nouveau_memx_train_result(ppwr, result, rsize); + return nvkm_memx_train_result(pmu, result, rsize); } static inline void ramfuc_block(struct ramfuc *ram) { - nouveau_memx_block(ram->memx); + nvkm_memx_block(ram->memx); } static inline void ramfuc_unblock(struct ramfuc *ram) { - nouveau_memx_unblock(ram->memx); + nvkm_memx_unblock(ram->memx); } #define ram_init(s,p) ramfuc_init(&(s)->base, (p)) @@ -180,5 +177,4 @@ ramfuc_unblock(struct ramfuc *ram) #define ram_train_result(s,r,l) ramfuc_train_result((s), (r), (l)) #define ram_block(s) ramfuc_block(&(s)->base) #define ram_unblock(s) ramfuc_unblock(&(s)->base) - #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index 735cb9580abe..de9f39569943 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -21,23 +21,20 @@ * * Authors: Ben Skeggs */ +#include "gf100.h" +#include "ramfuc.h" +#include <core/device.h> +#include <core/option.h> #include <subdev/bios.h> #include <subdev/bios/pll.h> #include <subdev/bios/rammap.h> #include <subdev/bios/timing.h> +#include <subdev/clk.h> +#include <subdev/clk/pll.h> #include <subdev/ltc.h> -#include <subdev/clock.h> -#include <subdev/clock/pll.h> - -#include <core/option.h> - -#include "ramfuc.h" - -#include "nvc0.h" - -struct nvc0_ramfuc { +struct gf100_ramfuc { struct ramfuc base; struct ramfuc_reg r_0x10fe20; @@ -100,18 +97,18 @@ struct nvc0_ramfuc { struct ramfuc_reg r_0x13d8f4; }; -struct nvc0_ram { - struct nouveau_ram base; - struct nvc0_ramfuc fuc; +struct gf100_ram { + struct nvkm_ram base; + struct gf100_ramfuc fuc; struct nvbios_pll refpll; struct nvbios_pll mempll; }; static void -nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic) +gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic) { - struct nvc0_ram *ram = container_of(fuc, typeof(*ram), fuc); - struct nouveau_fb *pfb = nouveau_fb(ram); + struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc); + struct nvkm_fb *pfb = nvkm_fb(ram); u32 part = nv_rd32(pfb, 0x022438), i; u32 mask = nv_rd32(pfb, 0x022554); u32 addr = 0x110974; @@ -127,12 +124,12 @@ nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic) } static int -nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) +gf100_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_clock *clk = nouveau_clock(pfb); - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nvc0_ram *ram = (void *)pfb->ram; - struct nvc0_ramfuc *fuc = &ram->fuc; + struct nvkm_clk *clk = nvkm_clk(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); + struct gf100_ram *ram = (void *)pfb->ram; + struct gf100_ramfuc *fuc = &ram->fuc; struct nvbios_ramcfg cfg; u8 ver, cnt, len, strap; struct { @@ -146,7 +143,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) /* lookup memory config data relevant to the target frequency */ rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, - &cnt, &ramcfg.size, &cfg); + &cnt, &ramcfg.size, &cfg); if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { nv_error(pfb, "invalid/missing rammap entry\n"); return -EINVAL; @@ -169,7 +166,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) strap = nv_ro08(bios, ramcfg.data + 0x01); if (strap != 0xff) { timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, - &cnt, &len); + &cnt, &len); if (!timing.data || ver != 0x10 || timing.size < 0x19) { nv_error(pfb, "invalid/missing timing entry\n"); return -EINVAL; @@ -213,8 +210,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) if (mode == 1 && from == 0) { /* calculate refpll */ - ret = nva3_pll_calc(nv_subdev(pfb), &ram->refpll, - ram->mempll.refclk, &N1, NULL, &M1, &P); + ret = gt215_pll_calc(nv_subdev(pfb), &ram->refpll, + ram->mempll.refclk, &N1, NULL, &M1, &P); if (ret <= 0) { nv_error(pfb, "unable to calc refpll\n"); return ret ? ret : -ERANGE; @@ -228,8 +225,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); /* calculate mempll */ - ret = nva3_pll_calc(nv_subdev(pfb), &ram->mempll, freq, - &N1, NULL, &M1, &P); + ret = gt215_pll_calc(nv_subdev(pfb), &ram->mempll, freq, + &N1, NULL, &M1, &P); if (ret <= 0) { nv_error(pfb, "unable to calc refpll\n"); return ret ? ret : -ERANGE; @@ -277,7 +274,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x10f210, 0x00000000); ram_nsec(fuc, 1000); if (mode == 0) - nvc0_ram_train(fuc, 0x000c1001); + gf100_ram_train(fuc, 0x000c1001); ram_wr32(fuc, 0x10f310, 0x00000001); ram_nsec(fuc, 1000); ram_wr32(fuc, 0x10f090, 0x00000061); @@ -325,8 +322,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x10f348, 0x00700008); ram_wr32(fuc, 0x61c140, 0x19240000); ram_wr32(fuc, 0x10f830, 0x00300017); - nvc0_ram_train(fuc, 0x80021001); - nvc0_ram_train(fuc, 0x80081001); + gf100_ram_train(fuc, 0x80021001); + gf100_ram_train(fuc, 0x80081001); ram_wr32(fuc, 0x10f340, 0x00500004); ram_nsec(fuc, 1000); ram_wr32(fuc, 0x10f830, 0x01300017); @@ -379,7 +376,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x13d8f4, 0x00000000); ram_wr32(fuc, 0x61c140, 0x09a40000); - nvc0_ram_train(fuc, 0x800e1008); + gf100_ram_train(fuc, 0x800e1008); ram_nsec(fuc, 1000); ram_wr32(fuc, 0x10f800, 0x00001804); @@ -392,7 +389,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x10f9b0, 0x05313f41); ram_wr32(fuc, 0x10f9b4, 0x00002f50); - nvc0_ram_train(fuc, 0x010c1001); + gf100_ram_train(fuc, 0x010c1001); } ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800); @@ -400,34 +397,35 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) if (mode == 0) ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); + return 0; } static int -nvc0_ram_prog(struct nouveau_fb *pfb) +gf100_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_device *device = nv_device(pfb); - struct nvc0_ram *ram = (void *)pfb->ram; - struct nvc0_ramfuc *fuc = &ram->fuc; - ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true)); + struct nvkm_device *device = nv_device(pfb); + struct gf100_ram *ram = (void *)pfb->ram; + struct gf100_ramfuc *fuc = &ram->fuc; + ram_exec(fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); return 0; } static void -nvc0_ram_tidy(struct nouveau_fb *pfb) +gf100_ram_tidy(struct nvkm_fb *pfb) { - struct nvc0_ram *ram = (void *)pfb->ram; - struct nvc0_ramfuc *fuc = &ram->fuc; + struct gf100_ram *ram = (void *)pfb->ram; + struct gf100_ramfuc *fuc = &ram->fuc; ram_exec(fuc, false); } -extern const u8 nvc0_pte_storage_type_map[256]; +extern const u8 gf100_pte_storage_type_map[256]; void -nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +gf100_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) { - struct nouveau_ltc *ltc = nouveau_ltc(pfb); - struct nouveau_mem *mem = *pmem; + struct nvkm_ltc *ltc = nvkm_ltc(pfb); + struct nvkm_mem *mem = *pmem; *pmem = NULL; if (unlikely(mem == NULL)) @@ -443,15 +441,15 @@ nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) } int -nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, - u32 memtype, struct nouveau_mem **pmem) +gf100_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, + u32 memtype, struct nvkm_mem **pmem) { - struct nouveau_mm *mm = &pfb->vram; - struct nouveau_mm_node *r; - struct nouveau_mem *mem; + struct nvkm_mm *mm = &pfb->vram; + struct nvkm_mm_node *r; + struct nvkm_mem *mem; int type = (memtype & 0x0ff); int back = (memtype & 0x800); - const bool comp = nvc0_pte_storage_type_map[type] != type; + const bool comp = gf100_pte_storage_type_map[type] != type; int ret; size >>= 12; @@ -469,7 +467,7 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, mutex_lock(&pfb->base.mutex); if (comp) { - struct nouveau_ltc *ltc = nouveau_ltc(pfb); + struct nvkm_ltc *ltc = nvkm_ltc(pfb); /* compression only works with lpages */ if (align == (1 << (17 - 12))) { @@ -478,15 +476,15 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, } if (unlikely(!mem->tag)) - type = nvc0_pte_storage_type_map[type]; + type = gf100_pte_storage_type_map[type]; } mem->memtype = type; do { if (back) - ret = nouveau_mm_tail(mm, 0, 1, size, ncmin, align, &r); + ret = nvkm_mm_tail(mm, 0, 1, size, ncmin, align, &r); else - ret = nouveau_mm_head(mm, 0, 1, size, ncmin, align, &r); + ret = nvkm_mm_head(mm, 0, 1, size, ncmin, align, &r); if (ret) { mutex_unlock(&pfb->base.mutex); pfb->ram->put(pfb, &mem); @@ -498,20 +496,20 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, } while (size); mutex_unlock(&pfb->base.mutex); - r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry); + r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); mem->offset = (u64)r->offset << 12; *pmem = mem; return 0; } int -nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 maskaddr, int size, - void **pobject) +gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 maskaddr, int size, + void **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_ram *ram; const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ u32 parts = nv_rd32(pfb, 0x022438); @@ -521,7 +519,7 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, bool uniform = true; int ret, part; - ret = nouveau_ram_create_(parent, engine, oclass, size, pobject); + ret = nvkm_ram_create_(parent, engine, oclass, size, pobject); ram = *pobject; if (ret) return ret; @@ -529,7 +527,7 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800)); nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask); - ram->type = nouveau_fb_bios_memtype(bios); + ram->type = nvkm_fb_bios_memtype(bios); ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1; /* read amount of vram attached to each memory controller */ @@ -551,11 +549,11 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, if (uniform) { offset = rsvd_head; length = (ram->size >> 12) - rsvd_head - rsvd_tail; - ret = nouveau_mm_init(&pfb->vram, offset, length, 1); + ret = nvkm_mm_init(&pfb->vram, offset, length, 1); } else { /* otherwise, address lowest common amount from 0GiB */ - ret = nouveau_mm_init(&pfb->vram, rsvd_head, - (bsize << 8) * parts - rsvd_head, 1); + ret = nvkm_mm_init(&pfb->vram, rsvd_head, + (bsize << 8) * parts - rsvd_head, 1); if (ret) return ret; @@ -563,27 +561,27 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, offset = (0x0200000000ULL >> 12) + (bsize << 8); length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail; - ret = nouveau_mm_init(&pfb->vram, offset, length, 1); + ret = nvkm_mm_init(&pfb->vram, offset, length, 1); if (ret) - nouveau_mm_fini(&pfb->vram); + nvkm_mm_fini(&pfb->vram); } if (ret) return ret; - ram->get = nvc0_ram_get; - ram->put = nvc0_ram_put; + ram->get = gf100_ram_get; + ram->put = gf100_ram_put; return 0; } static int -nvc0_ram_init(struct nouveau_object *object) +gf100_ram_init(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object->parent; - struct nvc0_ram *ram = (void *)object; + struct nvkm_fb *pfb = (void *)object->parent; + struct gf100_ram *ram = (void *)object; int ret, i; - ret = nouveau_ram_init(&ram->base); + ret = nvkm_ram_init(&ram->base); if (ret) return ret; @@ -624,15 +622,15 @@ nvc0_ram_init(struct nouveau_object *object) } static int -nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_bios *bios = nouveau_bios(parent); - struct nvc0_ram *ram; + struct nvkm_bios *bios = nvkm_bios(parent); + struct gf100_ram *ram; int ret; - ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram); + ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -651,9 +649,9 @@ nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, switch (ram->base.type) { case NV_MEM_TYPE_GDDR5: - ram->base.calc = nvc0_ram_calc; - ram->base.prog = nvc0_ram_prog; - ram->base.tidy = nvc0_ram_tidy; + ram->base.calc = gf100_ram_calc; + ram->base.prog = gf100_ram_prog; + ram->base.tidy = gf100_ram_tidy; break; default: nv_warn(ram, "reclocking of this ram type unsupported\n"); @@ -721,13 +719,13 @@ nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass -nvc0_ram_oclass = { +struct nvkm_oclass +gf100_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = nvc0_ram_init, - .fini = _nouveau_ram_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_ram_ctor, + .dtor = _nvkm_ram_dtor, + .init = gf100_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 6bae474abb44..1ef15c3e6a81 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -21,29 +21,23 @@ * * Authors: Ben Skeggs */ +#include "ramfuc.h" +#include "gf100.h" -#include <subdev/gpio.h> - +#include <core/device.h> +#include <core/option.h> #include <subdev/bios.h> -#include <subdev/bios/pll.h> #include <subdev/bios/init.h> -#include <subdev/bios/rammap.h> -#include <subdev/bios/timing.h> #include <subdev/bios/M0205.h> #include <subdev/bios/M0209.h> +#include <subdev/bios/pll.h> +#include <subdev/bios/rammap.h> +#include <subdev/bios/timing.h> +#include <subdev/clk.h> +#include <subdev/clk/pll.h> +#include <subdev/gpio.h> -#include <subdev/clock.h> -#include <subdev/clock/pll.h> - -#include <subdev/timer.h> - -#include <core/option.h> - -#include "nvc0.h" - -#include "ramfuc.h" - -struct nve0_ramfuc { +struct gk104_ramfuc { struct ramfuc base; struct nvbios_pll refpll; @@ -124,9 +118,9 @@ struct nve0_ramfuc { struct ramfuc_reg r_0x100750; }; -struct nve0_ram { - struct nouveau_ram base; - struct nve0_ramfuc fuc; +struct gk104_ram { + struct nvkm_ram base; + struct gk104_ramfuc fuc; struct list_head cfg; u32 parts; @@ -144,9 +138,9 @@ struct nve0_ram { * GDDR5 ******************************************************************************/ static void -nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data) +gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data) { - struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); + struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); u32 addr = 0x110974, i; ram_mask(fuc, 0x10f910, mask, data); @@ -160,9 +154,9 @@ nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data) } static void -r1373f4_init(struct nve0_ramfuc *fuc) +r1373f4_init(struct gk104_ramfuc *fuc) { - struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); + struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); const u32 runk0 = ram->fN1 << 16; @@ -210,10 +204,10 @@ r1373f4_init(struct nve0_ramfuc *fuc) } static void -r1373f4_fini(struct nve0_ramfuc *fuc) +r1373f4_fini(struct gk104_ramfuc *fuc) { - struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); - struct nouveau_ram_data *next = ram->base.next; + struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); + struct nvkm_ram_data *next = ram->base.next; u8 v0 = next->bios.ramcfg_11_03_c0; u8 v1 = next->bios.ramcfg_11_03_30; u32 tmp; @@ -232,10 +226,10 @@ r1373f4_fini(struct nve0_ramfuc *fuc) } static void -nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg, - u32 _mask, u32 _data, u32 _copy) +gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, + u32 _mask, u32 _data, u32 _copy) { - struct nve0_fb_priv *priv = (void *)nouveau_fb(ram); + struct gk104_fb_priv *priv = (void *)nvkm_fb(ram); struct ramfuc *fuc = &ram->fuc.base; u32 addr = 0x110000 + (reg->addr & 0xfff); u32 mask = _mask | _copy; @@ -246,19 +240,19 @@ nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg, if (ram->pnuts & (1 << i)) { u32 prev = nv_rd32(priv, addr); u32 next = (prev & ~mask) | data; - nouveau_memx_wr32(fuc->memx, addr, next); + nvkm_memx_wr32(fuc->memx, addr, next); } } } #define ram_nuts(s,r,m,d,c) \ - nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) + gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) static int -nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) +gk104_ram_calc_gddr5(struct nvkm_fb *pfb, u32 freq) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; - struct nouveau_ram_data *next = ram->base.next; + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; + struct nvkm_ram_data *next = ram->base.next; int vc = !next->bios.ramcfg_11_02_08; int mv = !next->bios.ramcfg_11_02_04; u32 mask, data; @@ -283,7 +277,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); - nve0_ram_train(fuc, 0x01020000, 0x000c0000); + gk104_ram_train(fuc, 0x01020000, 0x000c0000); ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ ram_nsec(fuc, 1000); @@ -588,7 +582,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) { u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); - nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ + gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ ram_nsec(fuc, 1000); ram_wr32(fuc, 0x10f294, temp); } @@ -643,7 +637,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) } else { data = 0xa40e0000; } - nve0_ram_train(fuc, 0xbc0f0000, data); + gk104_ram_train(fuc, 0xbc0f0000, data); if (1) /* XXX: not always? */ ram_nsec(fuc, 1000); @@ -661,7 +655,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) } if (next->bios.ramcfg_11_07_02) - nve0_ram_train(fuc, 0x80020000, 0x01000000); + gk104_ram_train(fuc, 0x80020000, 0x01000000); ram_unblock(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0f00); @@ -680,14 +674,14 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ******************************************************************************/ static int -nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) +gk104_ram_calc_sddr3(struct nvkm_fb *pfb, u32 freq) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); const u32 runk0 = ram->fN1 << 16; const u32 runk1 = ram->fN1; - struct nouveau_ram_data *next = ram->base.next; + struct nvkm_ram_data *next = ram->base.next; int vc = !next->bios.ramcfg_11_02_08; int mv = !next->bios.ramcfg_11_02_04; u32 mask, data; @@ -932,11 +926,10 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) ******************************************************************************/ static int -nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz, - struct nouveau_ram_data *data) +gk104_ram_calc_data(struct nvkm_fb *pfb, u32 khz, struct nvkm_ram_data *data) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nouveau_ram_data *cfg; + struct gk104_ram *ram = (void *)pfb->ram; + struct nvkm_ram_data *cfg; u32 mhz = khz / 1000; list_for_each_entry(cfg, &ram->cfg, head) { @@ -953,10 +946,10 @@ nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz, } static int -nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) +gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; int refclk, i; int ret; @@ -980,8 +973,8 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) refclk = fuc->mempll.refclk; /* calculate refpll coefficients */ - ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1, - &ram->fN1, &ram->M1, &ram->P1); + ret = gt215_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1, + &ram->fN1, &ram->M1, &ram->P1); fuc->mempll.refclk = ret; if (ret <= 0) { nv_error(pfb, "unable to calc refpll\n"); @@ -997,8 +990,8 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) fuc->mempll.min_p = 1; fuc->mempll.max_p = 2; - ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, - &ram->N2, NULL, &ram->M2, &ram->P2); + ret = gt215_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, + &ram->N2, NULL, &ram->M2, &ram->P2); if (ret <= 0) { nv_error(pfb, "unable to calc mempll\n"); return -EINVAL; @@ -1013,14 +1006,14 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) switch (ram->base.type) { case NV_MEM_TYPE_DDR3: - ret = nouveau_sddr3_calc(&ram->base); + ret = nvkm_sddr3_calc(&ram->base); if (ret == 0) - ret = nve0_ram_calc_sddr3(pfb, next->freq); + ret = gk104_ram_calc_sddr3(pfb, next->freq); break; case NV_MEM_TYPE_GDDR5: - ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0); + ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0); if (ret == 0) - ret = nve0_ram_calc_gddr5(pfb, next->freq); + ret = gk104_ram_calc_gddr5(pfb, next->freq); break; default: ret = -ENOSYS; @@ -1031,21 +1024,21 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) } static int -nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) +gk104_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_clock *clk = nouveau_clock(pfb); - struct nve0_ram *ram = (void *)pfb->ram; - struct nouveau_ram_data *xits = &ram->base.xition; - struct nouveau_ram_data *copy; + struct nvkm_clk *clk = nvkm_clk(pfb); + struct gk104_ram *ram = (void *)pfb->ram; + struct nvkm_ram_data *xits = &ram->base.xition; + struct nvkm_ram_data *copy; int ret; if (ram->base.next == NULL) { - ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), - &ram->base.former); + ret = gk104_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), + &ram->base.former); if (ret) return ret; - ret = nve0_ram_calc_data(pfb, freq, &ram->base.target); + ret = gk104_ram_calc_data(pfb, freq, &ram->base.target); if (ret) return ret; @@ -1069,14 +1062,14 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram->base.next = &ram->base.target; } - return nve0_ram_calc_xits(pfb, ram->base.next); + return gk104_ram_calc_xits(pfb, ram->base.next); } static void -nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq) +gk104_ram_prog_0(struct nvkm_fb *pfb, u32 freq) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nouveau_ram_data *cfg; + struct gk104_ram *ram = (void *)pfb->ram; + struct nvkm_ram_data *cfg; u32 mhz = freq / 1000; u32 mask, data; @@ -1149,35 +1142,35 @@ nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq) } static int -nve0_ram_prog(struct nouveau_fb *pfb) +gk104_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_device *device = nv_device(pfb); - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; - struct nouveau_ram_data *next = ram->base.next; + struct nvkm_device *device = nv_device(pfb); + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; + struct nvkm_ram_data *next = ram->base.next; - if (!nouveau_boolopt(device->cfgopt, "NvMemExec", true)) { + if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) { ram_exec(fuc, false); return (ram->base.next == &ram->base.xition); } - nve0_ram_prog_0(pfb, 1000); + gk104_ram_prog_0(pfb, 1000); ram_exec(fuc, true); - nve0_ram_prog_0(pfb, next->freq); + gk104_ram_prog_0(pfb, next->freq); return (ram->base.next == &ram->base.xition); } static void -nve0_ram_tidy(struct nouveau_fb *pfb) +gk104_ram_tidy(struct nvkm_fb *pfb) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; ram->base.next = NULL; ram_exec(fuc, false); } -struct nve0_ram_train { +struct gk104_ram_train { u16 mask; struct nvbios_M0209S remap; struct nvbios_M0209S type00; @@ -1190,10 +1183,10 @@ struct nve0_ram_train { }; static int -nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg, - struct nve0_ram_train *train) +gk104_ram_train_type(struct nvkm_fb *pfb, int i, u8 ramcfg, + struct gk104_ram_train *train) { - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); struct nvbios_M0205E M0205E; struct nvbios_M0205S M0205S; struct nvbios_M0209E M0209E; @@ -1251,7 +1244,7 @@ nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg, } static int -nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train) +gk104_ram_train_init_0(struct nvkm_fb *pfb, struct gk104_ram_train *train) { int i, j; @@ -1285,15 +1278,15 @@ nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train) } static int -nve0_ram_train_init(struct nouveau_fb *pfb) +gk104_ram_train_init(struct nvkm_fb *pfb) { u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); - struct nve0_ram_train *train; + struct gk104_ram_train *train; int ret = -ENOMEM, i; if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) { for (i = 0; i < 0x100; i++) { - ret = nve0_ram_train_type(pfb, i, ramcfg, train); + ret = gk104_ram_train_type(pfb, i, ramcfg, train); if (ret && ret != -ENOENT) break; } @@ -1301,7 +1294,7 @@ nve0_ram_train_init(struct nouveau_fb *pfb) switch (pfb->ram->type) { case NV_MEM_TYPE_GDDR5: - ret = nve0_ram_train_init_0(pfb, train); + ret = gk104_ram_train_init_0(pfb, train); break; default: ret = 0; @@ -1313,16 +1306,16 @@ nve0_ram_train_init(struct nouveau_fb *pfb) } int -nve0_ram_init(struct nouveau_object *object) +gk104_ram_init(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object->parent; - struct nve0_ram *ram = (void *)object; - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_fb *pfb = (void *)object->parent; + struct gk104_ram *ram = (void *)object; + struct nvkm_bios *bios = nvkm_bios(pfb); u8 ver, hdr, cnt, len, snr, ssz; u32 data, save; int ret, i; - ret = nouveau_ram_init(&ram->base); + ret = nvkm_ram_init(&ram->base); if (ret) return ret; @@ -1360,15 +1353,15 @@ nve0_ram_init(struct nouveau_object *object) nv_wr32(pfb, 0x10ecc0, 0xffffffff); nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010); - return nve0_ram_train_init(pfb); + return gk104_ram_train_init(pfb); } static int -nve0_ram_ctor_data(struct nve0_ram *ram, u8 ramcfg, int i) +gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i) { - struct nouveau_fb *pfb = (void *)nv_object(ram)->parent; - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nouveau_ram_data *cfg; + struct nvkm_fb *pfb = (void *)nv_object(ram)->parent; + struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_ram_data *cfg; struct nvbios_ramcfg *d = &ram->diff; struct nvbios_ramcfg *p, *n; u8 ver, hdr, cnt, len; @@ -1434,33 +1427,33 @@ done: } static void -nve0_ram_dtor(struct nouveau_object *object) +gk104_ram_dtor(struct nvkm_object *object) { - struct nve0_ram *ram = (void *)object; - struct nouveau_ram_data *cfg, *tmp; + struct gk104_ram *ram = (void *)object; + struct nvkm_ram_data *cfg, *tmp; list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) { kfree(cfg); } - nouveau_ram_destroy(&ram->base); + nvkm_ram_destroy(&ram->base); } static int -nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nouveau_gpio *gpio = nouveau_gpio(pfb); + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_gpio *gpio = nvkm_gpio(pfb); struct dcb_gpio_func func; - struct nve0_ram *ram; + struct gk104_ram *ram; int ret, i; u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); u32 tmp; - ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram); + ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -1470,9 +1463,9 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, switch (ram->base.type) { case NV_MEM_TYPE_DDR3: case NV_MEM_TYPE_GDDR5: - ram->base.calc = nve0_ram_calc; - ram->base.prog = nve0_ram_prog; - ram->base.tidy = nve0_ram_tidy; + ram->base.calc = gk104_ram_calc; + ram->base.prog = gk104_ram_prog; + ram->base.tidy = gk104_ram_tidy; break; default: nv_warn(pfb, "reclocking of this RAM type is unsupported\n"); @@ -1510,7 +1503,7 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, * need to treat this condition as a "don't touch" indicator. */ for (i = 0; !ret; i++) { - ret = nve0_ram_ctor_data(ram, ramcfg, i); + ret = gk104_ram_ctor_data(ram, ramcfg, i); if (ret && ret != -ENOENT) { nv_error(pfb, "failed to parse ramcfg data\n"); return ret; @@ -1634,13 +1627,13 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass -nve0_ram_oclass = { +struct nvkm_oclass +gk104_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_ram_ctor, - .dtor = nve0_ram_dtor, - .init = nve0_ram_init, - .fini = _nouveau_ram_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_ram_ctor, + .dtor = gk104_ram_dtor, + .init = gk104_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c index 4d77d75e4673..5f30db140b47 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c @@ -19,20 +19,19 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - #include "priv.h" -#include <subdev/fb.h> +#include <core/device.h> struct gk20a_mem { - struct nouveau_mem base; + struct nvkm_mem base; void *cpuaddr; dma_addr_t handle; }; #define to_gk20a_mem(m) container_of(m, struct gk20a_mem, base) static void -gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +gk20a_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) { struct device *dev = nv_device_base(nv_device(pfb)); struct gk20a_mem *mem = to_gk20a_mem(*pmem); @@ -50,8 +49,8 @@ gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) } static int -gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, - u32 memtype, struct nouveau_mem **pmem) +gk20a_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, + u32 memtype, struct nvkm_mem **pmem) { struct device *dev = nv_device_base(nv_device(pfb)); struct gk20a_mem *mem; @@ -116,19 +115,18 @@ gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, mem->base.pages[i] = mem->handle + (PAGE_SIZE * i); mem->base.offset = (u64)mem->base.pages[0]; - return 0; } static int -gk20a_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 datasize, - struct nouveau_object **pobject) +gk20a_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 datasize, + struct nvkm_object **pobject) { - struct nouveau_ram *ram; + struct nvkm_ram *ram; int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -137,16 +135,15 @@ gk20a_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ram->get = gk20a_ram_get; ram->put = gk20a_ram_put; - return 0; } -struct nouveau_oclass +struct nvkm_oclass gk20a_ram_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk20a_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c index 4c6363595c79..a298b39f55c5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c @@ -21,22 +21,21 @@ * * Authors: Ben Skeggs */ - -#include "nvc0.h" +#include "gf100.h" struct gm107_ram { - struct nouveau_ram base; + struct nvkm_ram base; }; static int -gm107_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gm107_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct gm107_ram *ram; int ret; - ret = nvc0_ram_create(parent, engine, oclass, 0x021c14, &ram); + ret = gf100_ram_create(parent, engine, oclass, 0x021c14, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -44,13 +43,13 @@ gm107_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass gm107_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm107_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = nve0_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = gk104_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c index 3b38a538845d..24176401b49b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c @@ -23,32 +23,22 @@ * Roy Spliet <rspliet@eclipso.eu> */ +#include "ramfuc.h" +#include "nv50.h" + +#include <core/device.h> +#include <core/option.h> #include <subdev/bios.h> -#include <subdev/bios/bit.h> -#include <subdev/bios/pll.h> -#include <subdev/bios/rammap.h> #include <subdev/bios/M0205.h> +#include <subdev/bios/rammap.h> #include <subdev/bios/timing.h> - -#include <subdev/clock/nva3.h> -#include <subdev/clock/pll.h> - +#include <subdev/clk/gt215.h> #include <subdev/gpio.h> -#include <subdev/timer.h> - -#include <engine/fifo.h> - -#include <core/option.h> - -#include "ramfuc.h" - -#include "nv50.h" - /* XXX: Remove when memx gains GPIO support */ extern int nv50_gpio_location(int line, u32 *reg, u32 *shift); -struct nva3_ramfuc { +struct gt215_ramfuc { struct ramfuc base; struct ramfuc_reg r_0x001610; struct ramfuc_reg r_0x001700; @@ -89,7 +79,7 @@ struct nva3_ramfuc { struct ramfuc_reg r_gpioFBVREF; }; -struct nva3_ltrain { +struct gt215_ltrain { enum { NVA3_TRAIN_UNKNOWN, NVA3_TRAIN_UNSUPPORTED, @@ -100,17 +90,17 @@ struct nva3_ltrain { u32 r_100720; u32 r_1111e0; u32 r_111400; - struct nouveau_mem *mem; + struct nvkm_mem *mem; }; -struct nva3_ram { - struct nouveau_ram base; - struct nva3_ramfuc fuc; - struct nva3_ltrain ltrain; +struct gt215_ram { + struct nvkm_ram base; + struct gt215_ramfuc fuc; + struct gt215_ltrain ltrain; }; void -nva3_link_train_calc(u32 *vals, struct nva3_ltrain *train) +gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train) { int i, lo, hi; u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0; @@ -164,14 +154,14 @@ nva3_link_train_calc(u32 *vals, struct nva3_ltrain *train) * Link training for (at least) DDR3 */ int -nva3_link_train(struct nouveau_fb *pfb) +gt215_link_train(struct nvkm_fb *pfb) { - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nva3_ram *ram = (void *)pfb->ram; - struct nouveau_clock *clk = nouveau_clock(pfb); - struct nva3_ltrain *train = &ram->ltrain; - struct nouveau_device *device = nv_device(pfb); - struct nva3_ramfuc *fuc = &ram->fuc; + struct nvkm_bios *bios = nvkm_bios(pfb); + struct gt215_ram *ram = (void *)pfb->ram; + struct nvkm_clk *clk = nvkm_clk(pfb); + struct gt215_ltrain *train = &ram->ltrain; + struct nvkm_device *device = nv_device(pfb); + struct gt215_ramfuc *fuc = &ram->fuc; u32 *result, r1700; int ret, i; struct nvbios_M0205T M0205T = { 0 }; @@ -180,7 +170,7 @@ nva3_link_train(struct nouveau_fb *pfb) unsigned long flags; unsigned long *f = &flags; - if (nouveau_boolopt(device->cfgopt, "NvMemExec", true) != true) + if (nvkm_boolopt(device->cfgopt, "NvMemExec", true) != true) return -ENOSYS; /* XXX: Multiple partitions? */ @@ -197,7 +187,7 @@ nva3_link_train(struct nouveau_fb *pfb) clk_current = clk->read(clk, nv_clk_src_mem); - ret = nva3_clock_pre(clk, f); + ret = gt215_clk_pre(clk, f); if (ret) goto out; @@ -252,12 +242,12 @@ nva3_link_train(struct nouveau_fb *pfb) nv_mask(pfb, 0x616308, 0x10, 0x10); nv_mask(pfb, 0x616b08, 0x10, 0x10); - nva3_clock_post(clk, f); + gt215_clk_post(clk, f); ram_train_result(pfb, result, 64); for (i = 0; i < 64; i++) nv_debug(pfb, "Train: %08x", result[i]); - nva3_link_train_calc(result, train); + gt215_link_train_calc(result, train); nv_debug(pfb, "Train: %08x %08x %08x", train->r_100720, train->r_1111e0, train->r_111400); @@ -274,12 +264,12 @@ out: train->state = NVA3_TRAIN_UNSUPPORTED; - nva3_clock_post(clk, f); + gt215_clk_post(clk, f); return ret; } int -nva3_link_train_init(struct nouveau_fb *pfb) +gt215_link_train_init(struct nvkm_fb *pfb) { static const u32 pattern[16] = { 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee, @@ -287,10 +277,10 @@ nva3_link_train_init(struct nouveau_fb *pfb) 0x33333333, 0x55555555, 0x77777777, 0x66666666, 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb, }; - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nva3_ram *ram = (void *)pfb->ram; - struct nva3_ltrain *train = &ram->ltrain; - struct nouveau_mem *mem; + struct nvkm_bios *bios = nvkm_bios(pfb); + struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ltrain *train = &ram->ltrain; + struct nvkm_mem *mem; struct nvbios_M0205E M0205E; u8 ver, hdr, cnt, len; u32 r001700; @@ -340,14 +330,13 @@ nva3_link_train_init(struct nouveau_fb *pfb) train->r_100720 = nv_rd32(pfb, 0x100720); train->r_1111e0 = nv_rd32(pfb, 0x1111e0); train->r_111400 = nv_rd32(pfb, 0x111400); - return 0; } void -nva3_link_train_fini(struct nouveau_fb *pfb) +gt215_link_train_fini(struct nvkm_fb *pfb) { - struct nva3_ram *ram = (void *)pfb->ram; + struct gt215_ram *ram = (void *)pfb->ram; if (ram->ltrain.mem) pfb->ram->put(pfb, &ram->ltrain.mem); @@ -358,9 +347,9 @@ nva3_link_train_fini(struct nouveau_fb *pfb) */ #define T(t) cfg->timing_10_##t static int -nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing) +gt215_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing) { - struct nva3_ram *ram = (void *)pfb->ram; + struct gt215_ram *ram = (void *)pfb->ram; struct nvbios_ramcfg *cfg = &ram->base.target.bios; int tUNK_base, tUNK_40_0, prevCL; u32 cur2, cur3, cur7, cur8; @@ -433,7 +422,7 @@ nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing) #undef T static void -nouveau_sddr2_dll_reset(struct nva3_ramfuc *fuc) +nvkm_sddr2_dll_reset(struct gt215_ramfuc *fuc) { ram_mask(fuc, mr[0], 0x100, 0x100); ram_nsec(fuc, 1000); @@ -442,7 +431,7 @@ nouveau_sddr2_dll_reset(struct nva3_ramfuc *fuc) } static void -nouveau_sddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr) +nvkm_sddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr) { u32 mr1_old = ram_rd32(fuc, mr[1]); @@ -454,7 +443,7 @@ nouveau_sddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr) } static void -nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr) +nvkm_gddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr) { u32 mr1_old = ram_rd32(fuc, mr[1]); @@ -465,7 +454,7 @@ nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr) } static void -nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clock_info *mclk) +gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk) { ram_wr32(fuc, 0x004004, mclk->pll); ram_mask(fuc, 0x004000, 0x00000001, 0x00000001); @@ -475,9 +464,9 @@ nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clock_info *mclk) } static void -nva3_ram_fbvref(struct nva3_ramfuc *fuc, u32 val) +gt215_ram_fbvref(struct gt215_ramfuc *fuc, u32 val) { - struct nouveau_gpio *gpio = nouveau_gpio(fuc->base.pfb); + struct nvkm_gpio *gpio = nvkm_gpio(fuc->base.pfb); struct dcb_gpio_func func; u32 reg, sh, gpio_val; int ret; @@ -498,14 +487,14 @@ nva3_ram_fbvref(struct nva3_ramfuc *fuc, u32 val) } static int -nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) +gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nva3_ram *ram = (void *)pfb->ram; - struct nva3_ramfuc *fuc = &ram->fuc; - struct nva3_ltrain *train = &ram->ltrain; - struct nva3_clock_info mclk; - struct nouveau_ram_data *next; + struct nvkm_bios *bios = nvkm_bios(pfb); + struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ramfuc *fuc = &ram->fuc; + struct gt215_ltrain *train = &ram->ltrain; + struct gt215_clk_info mclk; + struct nvkm_ram_data *next; u8 ver, hdr, cnt, len, strap; u32 data; u32 r004018, r100760, r100da0, r111100, ctrl; @@ -519,12 +508,12 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram->base.next = next; if (ram->ltrain.state == NVA3_TRAIN_ONCE) - nva3_link_train(pfb); + gt215_link_train(pfb); /* lookup memory config data relevant to the target frequency */ i = 0; data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len, - &next->bios); + &next->bios); if (!data || ver != 0x10 || hdr < 0x05) { nv_error(pfb, "invalid/missing rammap entry\n"); return -EINVAL; @@ -555,13 +544,13 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) } } - ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); + ret = gt215_pll_info(nvkm_clk(pfb), 0x12, 0x4000, freq, &mclk); if (ret < 0) { nv_error(pfb, "failed mclk calculation\n"); return ret; } - nva3_ram_timing_calc(pfb, timing); + gt215_ram_timing_calc(pfb, timing); ret = ram_init(fuc, pfb); if (ret) @@ -574,13 +563,13 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) switch (ram->base.type) { case NV_MEM_TYPE_DDR2: - ret = nouveau_sddr2_calc(&ram->base); + ret = nvkm_sddr2_calc(&ram->base); break; case NV_MEM_TYPE_DDR3: - ret = nouveau_sddr3_calc(&ram->base); + ret = nvkm_sddr3_calc(&ram->base); break; case NV_MEM_TYPE_GDDR3: - ret = nouveau_gddr3_calc(&ram->base); + ret = nvkm_gddr3_calc(&ram->base); break; default: ret = -ENOSYS; @@ -621,7 +610,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) /* If switching from non-pll to pll, lock before disabling FB */ if (mclk.pll && !pll2pll) { ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101); - nva3_ram_lock_pll(fuc, &mclk); + gt215_ram_lock_pll(fuc, &mclk); } /* Start with disabling some CRTCs and PFIFO? */ @@ -643,15 +632,15 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) /* If we're disabling the DLL, do it now */ switch (next->bios.ramcfg_10_DLLoff * ram->base.type) { case NV_MEM_TYPE_DDR3: - nouveau_sddr3_dll_disable(fuc, ram->base.mr); + nvkm_sddr3_dll_disable(fuc, ram->base.mr); break; case NV_MEM_TYPE_GDDR3: - nouveau_gddr3_dll_disable(fuc, ram->base.mr); + nvkm_gddr3_dll_disable(fuc, ram->base.mr); break; } if (fuc->r_gpioFBVREF.addr && next->bios.timing_10_ODT) - nva3_ram_fbvref(fuc, 0); + gt215_ram_fbvref(fuc, 0); /* Brace RAM for impact */ ram_wr32(fuc, 0x1002d4, 0x00000001); @@ -678,7 +667,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x004000, 0x00000008, 0x00000008); ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000); ram_wr32(fuc, 0x004018, 0x00001000); - nva3_ram_lock_pll(fuc, &mclk); + gt215_ram_lock_pll(fuc, &mclk); } if (mclk.pll) { @@ -818,11 +807,11 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x111100, 0xffffffff, r111100); if (fuc->r_gpioFBVREF.addr && !next->bios.timing_10_ODT) - nva3_ram_fbvref(fuc, 1); + gt215_ram_fbvref(fuc, 1); /* Reset DLL */ if (!next->bios.ramcfg_10_DLLoff) - nouveau_sddr2_dll_reset(fuc); + nvkm_sddr2_dll_reset(fuc); if (ram->base.type == NV_MEM_TYPE_GDDR3) { ram_nsec(fuc, 31000); @@ -866,12 +855,12 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) } static int -nva3_ram_prog(struct nouveau_fb *pfb) +gt215_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_device *device = nv_device(pfb); - struct nva3_ram *ram = (void *)pfb->ram; - struct nva3_ramfuc *fuc = &ram->fuc; - bool exec = nouveau_boolopt(device->cfgopt, "NvMemExec", true); + struct nvkm_device *device = nv_device(pfb); + struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ramfuc *fuc = &ram->fuc; + bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true); if (exec) { nv_mask(pfb, 0x001534, 0x2, 0x2); @@ -891,49 +880,48 @@ nva3_ram_prog(struct nouveau_fb *pfb) } static void -nva3_ram_tidy(struct nouveau_fb *pfb) +gt215_ram_tidy(struct nvkm_fb *pfb) { - struct nva3_ram *ram = (void *)pfb->ram; - struct nva3_ramfuc *fuc = &ram->fuc; + struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ramfuc *fuc = &ram->fuc; ram_exec(fuc, false); } static int -nva3_ram_init(struct nouveau_object *object) +gt215_ram_init(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object->parent; - struct nva3_ram *ram = (void *)object; + struct nvkm_fb *pfb = (void *)object->parent; + struct gt215_ram *ram = (void *)object; int ret; - ret = nouveau_ram_init(&ram->base); + ret = nvkm_ram_init(&ram->base); if (ret) return ret; - nva3_link_train_init(pfb); - + gt215_link_train_init(pfb); return 0; } static int -nva3_ram_fini(struct nouveau_object *object, bool suspend) +gt215_ram_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_fb *pfb = (void *)object->parent; + struct nvkm_fb *pfb = (void *)object->parent; if (!suspend) - nva3_link_train_fini(pfb); + gt215_link_train_fini(pfb); return 0; } static int -nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 datasize, - struct nouveau_object **pobject) +gt215_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 datasize, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_gpio *gpio = nouveau_gpio(pfb); + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_gpio *gpio = nvkm_gpio(pfb); struct dcb_gpio_func func; - struct nva3_ram *ram; + struct gt215_ram *ram; int ret, i; u32 reg, shift; @@ -946,9 +934,9 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, case NV_MEM_TYPE_DDR2: case NV_MEM_TYPE_DDR3: case NV_MEM_TYPE_GDDR3: - ram->base.calc = nva3_ram_calc; - ram->base.prog = nva3_ram_prog; - ram->base.tidy = nva3_ram_tidy; + ram->base.calc = gt215_ram_calc; + ram->base.prog = gt215_ram_prog; + ram->base.tidy = gt215_ram_tidy; break; default: nv_warn(ram, "reclocking of this ram type unsupported\n"); @@ -1013,12 +1001,12 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass -nva3_ram_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = nva3_ram_init, - .fini = nva3_ram_fini, +struct nvkm_oclass +gt215_ram_oclass = { + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gt215_ram_ctor, + .dtor = _nvkm_ram_dtor, + .init = gt215_ram_init, + .fini = gt215_ram_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c new file mode 100644 index 000000000000..abc18e89a97c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c @@ -0,0 +1,101 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "nv50.h" + +struct mcp77_ram_priv { + struct nvkm_ram base; + u64 poller_base; +}; + +static int +mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 datasize, + struct nvkm_object **pobject) +{ + u32 rsvd_head = ( 256 * 1024); /* vga memory */ + u32 rsvd_tail = (1024 * 1024); /* vbios etc */ + struct nvkm_fb *pfb = nvkm_fb(parent); + struct mcp77_ram_priv *priv; + int ret; + + ret = nvkm_ram_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->base.type = NV_MEM_TYPE_STOLEN; + priv->base.stolen = (u64)nv_rd32(pfb, 0x100e10) << 12; + priv->base.size = (u64)nv_rd32(pfb, 0x100e14) << 12; + + rsvd_tail += 0x1000; + priv->poller_base = priv->base.size - rsvd_tail; + + ret = nvkm_mm_init(&pfb->vram, rsvd_head >> 12, + (priv->base.size - (rsvd_head + rsvd_tail)) >> 12, + 1); + if (ret) + return ret; + + priv->base.get = nv50_ram_get; + priv->base.put = nv50_ram_put; + return 0; +} + +static int +mcp77_ram_init(struct nvkm_object *object) +{ + struct nvkm_fb *pfb = nvkm_fb(object); + struct mcp77_ram_priv *priv = (void *)object; + int ret; + u64 dniso, hostnb, flush; + + ret = nvkm_ram_init(&priv->base); + if (ret) + return ret; + + dniso = ((priv->base.size - (priv->poller_base + 0x00)) >> 5) - 1; + hostnb = ((priv->base.size - (priv->poller_base + 0x20)) >> 5) - 1; + flush = ((priv->base.size - (priv->poller_base + 0x40)) >> 5) - 1; + + /* Enable NISO poller for various clients and set their associated + * read address, only for MCP77/78 and MCP79/7A. (fd#25701) + */ + nv_wr32(pfb, 0x100c18, dniso); + nv_mask(pfb, 0x100c14, 0x00000000, 0x00000001); + nv_wr32(pfb, 0x100c1c, hostnb); + nv_mask(pfb, 0x100c14, 0x00000000, 0x00000002); + nv_wr32(pfb, 0x100c24, flush); + nv_mask(pfb, 0x100c14, 0x00000000, 0x00010000); + return 0; +} + +struct nvkm_oclass +mcp77_ram_oclass = { + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = mcp77_ram_ctor, + .dtor = _nvkm_ram_dtor, + .init = mcp77_ram_init, + .fini = _nvkm_ram_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c index 1972268d1410..855de1617229 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c @@ -21,22 +21,20 @@ * * Authors: Ben Skeggs */ - -#include <subdev/fb/regsnv04.h> - #include "priv.h" +#include "regsnv04.h" static int -nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -65,16 +63,17 @@ nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, ram->type = NV_MEM_TYPE_SGRAM; else ram->type = NV_MEM_TYPE_SDRAM; + return 0; } -struct nouveau_oclass +struct nvkm_oclass nv04_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c index 8311f3774edf..3b8a1eda5b64 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static int -nv10_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; u32 cfg0 = nv_rd32(pfb, 0x100200); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -48,14 +47,13 @@ nv10_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } - -struct nouveau_oclass +struct nvkm_oclass nv10_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv10_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c index d0caddfb9db0..fbae05db4ffd 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c @@ -21,16 +21,17 @@ * * Authors: Ben Skeggs */ - #include "priv.h" +#include <core/device.h> + static int -nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; struct pci_dev *bridge; u32 mem, mib; int ret; @@ -41,7 +42,7 @@ nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return -ENODEV; } - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -59,13 +60,13 @@ nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv1a_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv1a_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c index fdc11bba226d..d9e7187bd235 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static int -nv20_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; u32 pbus1218 = nv_rd32(pfb, 0x001218); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -51,13 +50,13 @@ nv20_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv20_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv20_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c index 7648beb11199..3d31fa45c1a6 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c @@ -21,23 +21,20 @@ * * Authors: Ben Skeggs */ +#include "nv40.h" +#include <core/device.h> #include <subdev/bios.h> #include <subdev/bios/bit.h> -#include <subdev/bios/pll.h> #include <subdev/bios/init.h> -#include <subdev/clock.h> -#include <subdev/clock/pll.h> +#include <subdev/bios/pll.h> +#include <subdev/clk/pll.h> #include <subdev/timer.h> -#include <engine/fifo.h> - -#include "nv40.h" - int -nv40_ram_calc(struct nouveau_fb *pfb, u32 freq) +nv40_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); struct nv40_ram *ram = (void *)pfb->ram; struct nvbios_pll pll; int N1, M1, N2, M2; @@ -68,9 +65,9 @@ nv40_ram_calc(struct nouveau_fb *pfb, u32 freq) } int -nv40_ram_prog(struct nouveau_fb *pfb) +nv40_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); struct nv40_ram *ram = (void *)pfb->ram; struct bit_entry M; u32 crtc_mask = 0; @@ -167,21 +164,21 @@ nv40_ram_prog(struct nouveau_fb *pfb) } void -nv40_ram_tidy(struct nouveau_fb *pfb) +nv40_ram_tidy(struct nvkm_fb *pfb) { } static int -nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nv40_ram *ram; u32 pbus1218 = nv_rd32(pfb, 0x001218); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -203,13 +200,13 @@ nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, } -struct nouveau_oclass +struct nvkm_oclass nv40_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c index d64498a4d9ee..33c612b1355f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "nv40.h" static int -nv41_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nv40_ram *ram; u32 pfb474 = nv_rd32(pfb, 0x100474); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -55,13 +54,13 @@ nv41_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv41_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv41_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c index 089acac810c5..f575a7246403 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "nv40.h" static int -nv44_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nv40_ram *ram; u32 pfb474 = nv_rd32(pfb, 0x100474); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -53,13 +52,13 @@ nv44_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv44_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv44_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c index baa013afa57b..51b44cdb2732 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "nv40.h" static int -nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nv40_ram *ram; u32 pfb914 = nv_rd32(pfb, 0x100914); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -55,13 +54,13 @@ nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv49_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv49_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c index 63a6aab86028..f3ed1c60d730 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static int -nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -43,13 +42,13 @@ nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv4e_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv4e_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index 64a983c96625..d2c81dd635dc 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -21,21 +21,16 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "ramseq.h" +#include <core/device.h> +#include <core/option.h> #include <subdev/bios.h> -#include <subdev/bios/bit.h> -#include <subdev/bios/pll.h> #include <subdev/bios/perf.h> +#include <subdev/bios/pll.h> #include <subdev/bios/timing.h> -#include <subdev/clock/pll.h> -#include <subdev/fb.h> - -#include <core/option.h> -#include <core/mm.h> - -#include "ramseq.h" - -#include "nv50.h" +#include <subdev/clk/pll.h> struct nv50_ramseq { struct hwsq base; @@ -56,16 +51,16 @@ struct nv50_ramseq { }; struct nv50_ram { - struct nouveau_ram base; + struct nvkm_ram base; struct nv50_ramseq hwsq; }; #define QFX5800NVA0 1 static int -nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) +nv50_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); struct nv50_ram *ram = (void *)pfb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; struct nvbios_perfE perfE; @@ -82,7 +77,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) i = 0; do { ramcfg.data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt, - &ramcfg.size, &perfE); + &ramcfg.size, &perfE); if (!ramcfg.data || (ver < 0x25 || ver >= 0x40) || (ramcfg.size < 2)) { nv_error(pfb, "invalid/missing perftab entry\n"); @@ -103,7 +98,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) strap = nv_ro08(bios, ramcfg.data + 0x01); if (strap != 0xff) { timing.data = nvbios_timingEe(bios, strap, &ver, &hdr, - &cnt, &len); + &cnt, &len); if (!timing.data || ver != 0x10 || hdr < 0x12) { nv_error(pfb, "invalid/missing timing entry " "%02x %04x %02x %02x\n", @@ -136,7 +131,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) mpll.vco2.max_freq = 0; if (ret == 0) { ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq, - &N1, &M1, &N2, &M2, &P); + &N1, &M1, &N2, &M2, &P); if (ret == 0) ret = -EINVAL; } @@ -205,18 +200,18 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) } static int -nv50_ram_prog(struct nouveau_fb *pfb) +nv50_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_device *device = nv_device(pfb); + struct nvkm_device *device = nv_device(pfb); struct nv50_ram *ram = (void *)pfb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; - ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", true)); + ram_exec(hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); return 0; } static void -nv50_ram_tidy(struct nouveau_fb *pfb) +nv50_ram_tidy(struct nvkm_fb *pfb) { struct nv50_ram *ram = (void *)pfb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; @@ -224,24 +219,24 @@ nv50_ram_tidy(struct nouveau_fb *pfb) } void -__nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem) +__nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem *mem) { - struct nouveau_mm_node *this; + struct nvkm_mm_node *this; while (!list_empty(&mem->regions)) { this = list_first_entry(&mem->regions, typeof(*this), rl_entry); list_del(&this->rl_entry); - nouveau_mm_free(&pfb->vram, &this); + nvkm_mm_free(&pfb->vram, &this); } - nouveau_mm_free(&pfb->tags, &mem->tag); + nvkm_mm_free(&pfb->tags, &mem->tag); } void -nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) { - struct nouveau_mem *mem = *pmem; + struct nvkm_mem *mem = *pmem; *pmem = NULL; if (unlikely(mem == NULL)) @@ -255,13 +250,13 @@ nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) } int -nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, - u32 memtype, struct nouveau_mem **pmem) +nv50_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, + u32 memtype, struct nvkm_mem **pmem) { - struct nouveau_mm *heap = &pfb->vram; - struct nouveau_mm *tags = &pfb->tags; - struct nouveau_mm_node *r; - struct nouveau_mem *mem; + struct nvkm_mm *heap = &pfb->vram; + struct nvkm_mm *tags = &pfb->tags; + struct nvkm_mm_node *r; + struct nvkm_mem *mem; int comp = (memtype & 0x300) >> 8; int type = (memtype & 0x07f); int back = (memtype & 0x800); @@ -280,7 +275,7 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, if (align == 16) { int n = (max >> 4) * comp; - ret = nouveau_mm_head(tags, 0, 1, n, n, 1, &mem->tag); + ret = nvkm_mm_head(tags, 0, 1, n, n, 1, &mem->tag); if (ret) mem->tag = NULL; } @@ -296,9 +291,9 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, type = nv50_fb_memtype[type]; do { if (back) - ret = nouveau_mm_tail(heap, 0, type, max, min, align, &r); + ret = nvkm_mm_tail(heap, 0, type, max, min, align, &r); else - ret = nouveau_mm_head(heap, 0, type, max, min, align, &r); + ret = nvkm_mm_head(heap, 0, type, max, min, align, &r); if (ret) { mutex_unlock(&pfb->base.mutex); pfb->ram->put(pfb, &mem); @@ -310,14 +305,14 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, } while (max); mutex_unlock(&pfb->base.mutex); - r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry); + r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); mem->offset = (u64)r->offset << 12; *pmem = mem; return 0; } static u32 -nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram) +nv50_fb_vram_rblock(struct nvkm_fb *pfb, struct nvkm_ram *ram) { int colbits, rowbitsa, rowbitsb, banks; u64 rowsize, predicted; @@ -326,8 +321,8 @@ nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram) r0 = nv_rd32(pfb, 0x100200); r4 = nv_rd32(pfb, 0x100204); rt = nv_rd32(pfb, 0x100250); - nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, - nv_rd32(pfb, 0x001540)); + nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", + r0, r4, rt, nv_rd32(pfb, 0x001540)); colbits = (r4 & 0x0000f000) >> 12; rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; @@ -353,17 +348,17 @@ nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram) } int -nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) +nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ - struct nouveau_bios *bios = nouveau_bios(parent); - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_bios *bios = nvkm_bios(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; int ret; - ret = nouveau_ram_create_(parent, engine, oclass, length, pobject); + ret = nvkm_ram_create_(parent, engine, oclass, length, pobject); ram = *pobject; if (ret) return ret; @@ -377,7 +372,7 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, switch (nv_rd32(pfb, 0x100714) & 0x00000007) { case 0: ram->type = NV_MEM_TYPE_DDR1; break; case 1: - if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3) + if (nvkm_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3) ram->type = NV_MEM_TYPE_DDR3; else ram->type = NV_MEM_TYPE_DDR2; @@ -389,9 +384,9 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, break; } - ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) - - (rsvd_head + rsvd_tail), - nv50_fb_vram_rblock(pfb, ram) >> 12); + ret = nvkm_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) - + (rsvd_head + rsvd_tail), + nv50_fb_vram_rblock(pfb, ram) >> 12); if (ret) return ret; @@ -403,9 +398,9 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 datasize, - struct nouveau_object **pobject) +nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 datasize, + struct nvkm_object **pobject) { struct nv50_ram *ram; int ret, i; @@ -459,12 +454,12 @@ nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv50_ram_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h index 571077e39071..0f1f97ccd5f6 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h @@ -1,7 +1,5 @@ #ifndef __NVKM_FBRAM_SEQ_H__ #define __NVKM_FBRAM_SEQ_H__ - -#include <subdev/bus.h> #include <subdev/bus/hwsq.h> #define ram_init(s,p) hwsq_init(&(s)->base, (p)) @@ -14,5 +12,4 @@ #define ram_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) #define ram_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) #define ram_nsec(s,n) hwsq_nsec(&(s)->base, (n)) - #endif diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h index 0f7fc0c52ab2..1f865f61504e 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h @@ -1,5 +1,5 @@ -#ifndef __NOUVEAU_FB_REGS_04_H__ -#define __NOUVEAU_FB_REGS_04_H__ +#ifndef __NVKM_FB_REGS_04_H__ +#define __NVKM_FB_REGS_04_H__ #define NV04_PFB_BOOT_0 0x00100000 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003 @@ -17,5 +17,6 @@ # define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 # define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100 # define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000 +#define NV04_PFB_CFG0 0x00100200 #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c index 252575f3aa29..afab42df28d4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c @@ -22,7 +22,6 @@ * Authors: Roy Spliet <rspliet@eclipso.eu> * Ben Skeggs */ - #include "priv.h" struct ramxlat { @@ -58,7 +57,7 @@ ramddr2_wr[] = { }; int -nouveau_sddr2_calc(struct nouveau_ram *ram) +nvkm_sddr2_calc(struct nvkm_ram *ram) { int CL, WR, DLL = 0, ODT = 0; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c index a2dca4869e52..10844355c3f3 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c @@ -22,7 +22,6 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> * Roy Spliet <rspliet@eclipso.eu> */ - #include "priv.h" struct ramxlat { @@ -67,7 +66,7 @@ ramddr3_cwl[] = { }; int -nouveau_sddr3_calc(struct nouveau_ram *ram) +nvkm_sddr3_calc(struct nvkm_ram *ram) { int CWL, CL, WR, DLL = 0, ODT = 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild new file mode 100644 index 000000000000..f3d4e6e131b6 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild @@ -0,0 +1,4 @@ +nvkm-y += nvkm/subdev/fuse/base.o +nvkm-y += nvkm/subdev/fuse/nv50.o +nvkm-y += nvkm/subdev/fuse/gf100.o +nvkm-y += nvkm/subdev/fuse/gm107.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c index 9e8e92127715..b7b7193bbce7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c @@ -21,34 +21,31 @@ * * Authors: Martin Peres */ - #include <subdev/fuse.h> int -_nouveau_fuse_init(struct nouveau_object *object) +_nvkm_fuse_init(struct nvkm_object *object) { - struct nouveau_fuse *fuse = (void *)object; - return nouveau_subdev_init(&fuse->base); + struct nvkm_fuse *fuse = (void *)object; + return nvkm_subdev_init(&fuse->base); } void -_nouveau_fuse_dtor(struct nouveau_object *object) +_nvkm_fuse_dtor(struct nvkm_object *object) { - struct nouveau_fuse *fuse = (void *)object; - nouveau_subdev_destroy(&fuse->base); + struct nvkm_fuse *fuse = (void *)object; + nvkm_subdev_destroy(&fuse->base); } int -nouveau_fuse_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) +nvkm_fuse_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_fuse *fuse; + struct nvkm_fuse *fuse; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "FUSE", - "fuse", length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "FUSE", + "fuse", length, pobject); fuse = *pobject; - return ret; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c index 5ed03f54b3d4..393ef3a0faaf 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c @@ -21,63 +21,58 @@ * * Authors: Martin Peres */ - #include "priv.h" struct gf100_fuse_priv { - struct nouveau_fuse base; + struct nvkm_fuse base; spinlock_t fuse_enable_lock; }; static u32 -gf100_fuse_rd32(struct nouveau_object *object, u64 addr) +gf100_fuse_rd32(struct nvkm_object *object, u64 addr) { struct gf100_fuse_priv *priv = (void *)object; unsigned long flags; u32 fuse_enable, unk, val; + /* racy if another part of nvkm start writing to these regs */ spin_lock_irqsave(&priv->fuse_enable_lock, flags); - - /* racy if another part of nouveau start writing to these regs */ fuse_enable = nv_mask(priv, 0x22400, 0x800, 0x800); unk = nv_mask(priv, 0x21000, 0x1, 0x1); val = nv_rd32(priv, 0x21100 + addr); nv_wr32(priv, 0x21000, unk); nv_wr32(priv, 0x22400, fuse_enable); - spin_unlock_irqrestore(&priv->fuse_enable_lock, flags); - return val; } static int -gf100_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct gf100_fuse_priv *priv; int ret; - ret = nouveau_fuse_create(parent, engine, oclass, &priv); + ret = nvkm_fuse_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; spin_lock_init(&priv->fuse_enable_lock); - return 0; } -struct nouveau_oclass +struct nvkm_oclass gf100_fuse_oclass = { .handle = NV_SUBDEV(FUSE, 0xC0), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gf100_fuse_ctor, - .dtor = _nouveau_fuse_dtor, - .init = _nouveau_fuse_init, - .fini = _nouveau_fuse_fini, + .dtor = _nvkm_fuse_dtor, + .init = _nvkm_fuse_init, + .fini = _nvkm_fuse_fini, .rd32 = gf100_fuse_rd32, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c index 4f1a636c6538..ba19158a5912 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c @@ -21,31 +21,29 @@ * * Authors: Martin Peres */ - #include "priv.h" struct gm107_fuse_priv { - struct nouveau_fuse base; + struct nvkm_fuse base; }; static u32 -gm107_fuse_rd32(struct nouveau_object *object, u64 addr) +gm107_fuse_rd32(struct nvkm_object *object, u64 addr) { struct gf100_fuse_priv *priv = (void *)object; - return nv_rd32(priv, 0x21100 + addr); } static int -gm107_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gm107_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct gm107_fuse_priv *priv; int ret; - ret = nouveau_fuse_create(parent, engine, oclass, &priv); + ret = nvkm_fuse_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -53,14 +51,14 @@ gm107_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass gm107_fuse_oclass = { .handle = NV_SUBDEV(FUSE, 0x117), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm107_fuse_ctor, - .dtor = _nouveau_fuse_dtor, - .init = _nouveau_fuse_init, - .fini = _nouveau_fuse_fini, + .dtor = _nvkm_fuse_dtor, + .init = _nvkm_fuse_init, + .fini = _nvkm_fuse_fini, .rd32 = gm107_fuse_rd32, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c index a374ade485be..0d2afc426100 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c @@ -21,61 +21,56 @@ * * Authors: Martin Peres */ - #include "priv.h" -struct g80_fuse_priv { - struct nouveau_fuse base; +struct nv50_fuse_priv { + struct nvkm_fuse base; spinlock_t fuse_enable_lock; }; static u32 -g80_fuse_rd32(struct nouveau_object *object, u64 addr) +nv50_fuse_rd32(struct nvkm_object *object, u64 addr) { - struct g80_fuse_priv *priv = (void *)object; + struct nv50_fuse_priv *priv = (void *)object; unsigned long flags; u32 fuse_enable, val; + /* racy if another part of nvkm start writing to this reg */ spin_lock_irqsave(&priv->fuse_enable_lock, flags); - - /* racy if another part of nouveau start writing to this reg */ fuse_enable = nv_mask(priv, 0x1084, 0x800, 0x800); val = nv_rd32(priv, 0x21000 + addr); nv_wr32(priv, 0x1084, fuse_enable); - spin_unlock_irqrestore(&priv->fuse_enable_lock, flags); - return val; } static int -g80_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct g80_fuse_priv *priv; + struct nv50_fuse_priv *priv; int ret; - ret = nouveau_fuse_create(parent, engine, oclass, &priv); + ret = nvkm_fuse_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; spin_lock_init(&priv->fuse_enable_lock); - return 0; } -struct nouveau_oclass -g80_fuse_oclass = { +struct nvkm_oclass +nv50_fuse_oclass = { .handle = NV_SUBDEV(FUSE, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = g80_fuse_ctor, - .dtor = _nouveau_fuse_dtor, - .init = _nouveau_fuse_init, - .fini = _nouveau_fuse_fini, - .rd32 = g80_fuse_rd32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_fuse_ctor, + .dtor = _nvkm_fuse_dtor, + .init = _nvkm_fuse_init, + .fini = _nvkm_fuse_fini, + .rd32 = nv50_fuse_rd32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h new file mode 100644 index 000000000000..7e050f789384 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h @@ -0,0 +1,7 @@ +#ifndef __NVKM_FUSE_PRIV_H__ +#define __NVKM_FUSE_PRIV_H__ +#include <subdev/fuse.h> + +int _nvkm_fuse_init(struct nvkm_object *object); +void _nvkm_fuse_dtor(struct nvkm_object *object); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild new file mode 100644 index 000000000000..ea42a9ed1821 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild @@ -0,0 +1,6 @@ +nvkm-y += nvkm/subdev/gpio/base.o +nvkm-y += nvkm/subdev/gpio/nv10.o +nvkm-y += nvkm/subdev/gpio/nv50.o +nvkm-y += nvkm/subdev/gpio/g94.o +nvkm-y += nvkm/subdev/gpio/gf110.o +nvkm-y += nvkm/subdev/gpio/gk104.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c index 7ad99b763f4c..dea58161ba46 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c @@ -21,32 +21,30 @@ * * Authors: Ben Skeggs */ - -#include <subdev/bios.h> -#include <subdev/bios/gpio.h> - #include "priv.h" +#include <core/device.h> +#include <core/notify.h> + static int -nouveau_gpio_drive(struct nouveau_gpio *gpio, - int idx, int line, int dir, int out) +nvkm_gpio_drive(struct nvkm_gpio *gpio, int idx, int line, int dir, int out) { - const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; + const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; return impl->drive ? impl->drive(gpio, line, dir, out) : -ENODEV; } static int -nouveau_gpio_sense(struct nouveau_gpio *gpio, int idx, int line) +nvkm_gpio_sense(struct nvkm_gpio *gpio, int idx, int line) { - const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; + const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; return impl->sense ? impl->sense(gpio, line) : -ENODEV; } static int -nouveau_gpio_find(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line, - struct dcb_gpio_func *func) +nvkm_gpio_find(struct nvkm_gpio *gpio, int idx, u8 tag, u8 line, + struct dcb_gpio_func *func) { - struct nouveau_bios *bios = nouveau_bios(gpio); + struct nvkm_bios *bios = nvkm_bios(gpio); u8 ver, len; u16 data; @@ -74,30 +72,30 @@ nouveau_gpio_find(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line, } static int -nouveau_gpio_set(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line, int state) +nvkm_gpio_set(struct nvkm_gpio *gpio, int idx, u8 tag, u8 line, int state) { struct dcb_gpio_func func; int ret; - ret = nouveau_gpio_find(gpio, idx, tag, line, &func); + ret = nvkm_gpio_find(gpio, idx, tag, line, &func); if (ret == 0) { int dir = !!(func.log[state] & 0x02); int out = !!(func.log[state] & 0x01); - ret = nouveau_gpio_drive(gpio, idx, func.line, dir, out); + ret = nvkm_gpio_drive(gpio, idx, func.line, dir, out); } return ret; } static int -nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line) +nvkm_gpio_get(struct nvkm_gpio *gpio, int idx, u8 tag, u8 line) { struct dcb_gpio_func func; int ret; - ret = nouveau_gpio_find(gpio, idx, tag, line, &func); + ret = nvkm_gpio_find(gpio, idx, tag, line, &func); if (ret == 0) { - ret = nouveau_gpio_sense(gpio, idx, func.line); + ret = nvkm_gpio_sense(gpio, idx, func.line); if (ret >= 0) ret = (ret == (func.log[1] & 1)); } @@ -106,24 +104,24 @@ nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line) } static void -nouveau_gpio_intr_fini(struct nvkm_event *event, int type, int index) +nvkm_gpio_intr_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event); - const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; + struct nvkm_gpio *gpio = container_of(event, typeof(*gpio), event); + const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; impl->intr_mask(gpio, type, 1 << index, 0); } static void -nouveau_gpio_intr_init(struct nvkm_event *event, int type, int index) +nvkm_gpio_intr_init(struct nvkm_event *event, int type, int index) { - struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event); - const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; + struct nvkm_gpio *gpio = container_of(event, typeof(*gpio), event); + const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; impl->intr_mask(gpio, type, 1 << index, 1 << index); } static int -nouveau_gpio_intr_ctor(struct nouveau_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_gpio_intr_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { struct nvkm_gpio_ntfy_req *req = data; if (!WARN_ON(size != sizeof(*req))) { @@ -136,10 +134,10 @@ nouveau_gpio_intr_ctor(struct nouveau_object *object, void *data, u32 size, } static void -nouveau_gpio_intr(struct nouveau_subdev *subdev) +nvkm_gpio_intr(struct nvkm_subdev *subdev) { - struct nouveau_gpio *gpio = nouveau_gpio(subdev); - const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; + struct nvkm_gpio *gpio = nvkm_gpio(subdev); + const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; u32 hi, lo, i; impl->intr_stat(gpio, &hi, &lo); @@ -154,23 +152,23 @@ nouveau_gpio_intr(struct nouveau_subdev *subdev) } static const struct nvkm_event_func -nouveau_gpio_intr_func = { - .ctor = nouveau_gpio_intr_ctor, - .init = nouveau_gpio_intr_init, - .fini = nouveau_gpio_intr_fini, +nvkm_gpio_intr_func = { + .ctor = nvkm_gpio_intr_ctor, + .init = nvkm_gpio_intr_init, + .fini = nvkm_gpio_intr_fini, }; int -_nouveau_gpio_fini(struct nouveau_object *object, bool suspend) +_nvkm_gpio_fini(struct nvkm_object *object, bool suspend) { - const struct nouveau_gpio_impl *impl = (void *)object->oclass; - struct nouveau_gpio *gpio = nouveau_gpio(object); + const struct nvkm_gpio_impl *impl = (void *)object->oclass; + struct nvkm_gpio *gpio = nvkm_gpio(object); u32 mask = (1 << impl->lines) - 1; impl->intr_mask(gpio, NVKM_GPIO_TOGGLED, mask, 0); impl->intr_stat(gpio, &mask, &mask); - return nouveau_subdev_fini(&gpio->base, suspend); + return nvkm_subdev_fini(&gpio->base, suspend); } static struct dmi_system_id gpio_reset_ids[] = { @@ -185,12 +183,12 @@ static struct dmi_system_id gpio_reset_ids[] = { }; int -_nouveau_gpio_init(struct nouveau_object *object) +_nvkm_gpio_init(struct nvkm_object *object) { - struct nouveau_gpio *gpio = nouveau_gpio(object); + struct nvkm_gpio *gpio = nvkm_gpio(object); int ret; - ret = nouveau_subdev_init(&gpio->base); + ret = nvkm_subdev_init(&gpio->base); if (ret) return ret; @@ -201,52 +199,50 @@ _nouveau_gpio_init(struct nouveau_object *object) } void -_nouveau_gpio_dtor(struct nouveau_object *object) +_nvkm_gpio_dtor(struct nvkm_object *object) { - struct nouveau_gpio *gpio = (void *)object; + struct nvkm_gpio *gpio = (void *)object; nvkm_event_fini(&gpio->event); - nouveau_subdev_destroy(&gpio->base); + nvkm_subdev_destroy(&gpio->base); } int -nouveau_gpio_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int length, void **pobject) +nvkm_gpio_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - const struct nouveau_gpio_impl *impl = (void *)oclass; - struct nouveau_gpio *gpio; + const struct nvkm_gpio_impl *impl = (void *)oclass; + struct nvkm_gpio *gpio; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "GPIO", "gpio", - length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "GPIO", + "gpio", length, pobject); gpio = *pobject; if (ret) return ret; - gpio->find = nouveau_gpio_find; - gpio->set = nouveau_gpio_set; - gpio->get = nouveau_gpio_get; + gpio->find = nvkm_gpio_find; + gpio->set = nvkm_gpio_set; + gpio->get = nvkm_gpio_get; gpio->reset = impl->reset; - ret = nvkm_event_init(&nouveau_gpio_intr_func, 2, impl->lines, + ret = nvkm_event_init(&nvkm_gpio_intr_func, 2, impl->lines, &gpio->event); if (ret) return ret; - nv_subdev(gpio)->intr = nouveau_gpio_intr; + nv_subdev(gpio)->intr = nvkm_gpio_intr; return 0; } int -_nouveau_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +_nvkm_gpio_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_gpio *gpio; + struct nvkm_gpio *gpio; int ret; - ret = nouveau_gpio_create(parent, engine, oclass, &gpio); + ret = nvkm_gpio_create(parent, engine, oclass, &gpio); *pobject = nv_object(gpio); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c index cae404ccadac..12b3e01fca8e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c @@ -21,11 +21,10 @@ * * Authors: Ben Skeggs */ - #include "priv.h" void -nv94_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) +g94_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) { u32 intr0 = nv_rd32(gpio, 0x00e054); u32 intr1 = nv_rd32(gpio, 0x00e074); @@ -38,7 +37,7 @@ nv94_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) } void -nv94_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) +g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) { u32 inte0 = nv_rd32(gpio, 0x00e050); u32 inte1 = nv_rd32(gpio, 0x00e070); @@ -56,18 +55,18 @@ nv94_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) nv_wr32(gpio, 0x00e070, inte1); } -struct nouveau_oclass * -nv94_gpio_oclass = &(struct nouveau_gpio_impl) { +struct nvkm_oclass * +g94_gpio_oclass = &(struct nvkm_gpio_impl) { .base.handle = NV_SUBDEV(GPIO, 0x94), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_gpio_ctor, - .dtor = _nouveau_gpio_dtor, - .init = _nouveau_gpio_init, - .fini = _nouveau_gpio_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_gpio_ctor, + .dtor = _nvkm_gpio_dtor, + .init = _nvkm_gpio_init, + .fini = _nvkm_gpio_fini, }, .lines = 32, - .intr_stat = nv94_gpio_intr_stat, - .intr_mask = nv94_gpio_intr_mask, + .intr_stat = g94_gpio_intr_stat, + .intr_mask = g94_gpio_intr_mask, .drive = nv50_gpio_drive, .sense = nv50_gpio_sense, .reset = nv50_gpio_reset, diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf110.c index 480d6d2af770..2c3bb255d1f8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf110.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include "priv.h" void -nvd0_gpio_reset(struct nouveau_gpio *gpio, u8 match) +gf110_gpio_reset(struct nvkm_gpio *gpio, u8 match) { - struct nouveau_bios *bios = nouveau_bios(gpio); + struct nvkm_bios *bios = nvkm_bios(gpio); u8 ver, len; u16 entry; int ent = -1; @@ -53,7 +52,7 @@ nvd0_gpio_reset(struct nouveau_gpio *gpio, u8 match) } int -nvd0_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) +gf110_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out) { u32 data = ((dir ^ 1) << 13) | (out << 12); nv_mask(gpio, 0x00d610 + (line * 4), 0x00003000, data); @@ -62,24 +61,24 @@ nvd0_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) } int -nvd0_gpio_sense(struct nouveau_gpio *gpio, int line) +gf110_gpio_sense(struct nvkm_gpio *gpio, int line) { return !!(nv_rd32(gpio, 0x00d610 + (line * 4)) & 0x00004000); } -struct nouveau_oclass * -nvd0_gpio_oclass = &(struct nouveau_gpio_impl) { +struct nvkm_oclass * +gf110_gpio_oclass = &(struct nvkm_gpio_impl) { .base.handle = NV_SUBDEV(GPIO, 0xd0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_gpio_ctor, - .dtor = _nouveau_gpio_dtor, - .init = _nouveau_gpio_init, - .fini = _nouveau_gpio_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_gpio_ctor, + .dtor = _nvkm_gpio_dtor, + .init = _nvkm_gpio_init, + .fini = _nvkm_gpio_fini, }, .lines = 32, - .intr_stat = nv94_gpio_intr_stat, - .intr_mask = nv94_gpio_intr_mask, - .drive = nvd0_gpio_drive, - .sense = nvd0_gpio_sense, - .reset = nvd0_gpio_reset, + .intr_stat = g94_gpio_intr_stat, + .intr_mask = g94_gpio_intr_mask, + .drive = gf110_gpio_drive, + .sense = gf110_gpio_sense, + .reset = gf110_gpio_reset, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c index e1145b48c76c..42fd2faaaa4f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c @@ -21,11 +21,10 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static void -nve0_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) +gk104_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) { u32 intr0 = nv_rd32(gpio, 0x00dc00); u32 intr1 = nv_rd32(gpio, 0x00dc80); @@ -38,7 +37,7 @@ nve0_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) } void -nve0_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) +gk104_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) { u32 inte0 = nv_rd32(gpio, 0x00dc08); u32 inte1 = nv_rd32(gpio, 0x00dc88); @@ -56,19 +55,19 @@ nve0_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) nv_wr32(gpio, 0x00dc88, inte1); } -struct nouveau_oclass * -nve0_gpio_oclass = &(struct nouveau_gpio_impl) { +struct nvkm_oclass * +gk104_gpio_oclass = &(struct nvkm_gpio_impl) { .base.handle = NV_SUBDEV(GPIO, 0xe0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_gpio_ctor, - .dtor = _nouveau_gpio_dtor, - .init = _nouveau_gpio_init, - .fini = _nouveau_gpio_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_gpio_ctor, + .dtor = _nvkm_gpio_dtor, + .init = _nvkm_gpio_init, + .fini = _nvkm_gpio_fini, }, .lines = 32, - .intr_stat = nve0_gpio_intr_stat, - .intr_mask = nve0_gpio_intr_mask, - .drive = nvd0_gpio_drive, - .sense = nvd0_gpio_sense, - .reset = nvd0_gpio_reset, + .intr_stat = gk104_gpio_intr_stat, + .intr_mask = gk104_gpio_intr_mask, + .drive = gf110_gpio_drive, + .sense = gf110_gpio_sense, + .reset = gf110_gpio_reset, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c index 27ad23eaf185..2b295154247e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c @@ -23,11 +23,10 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "priv.h" static int -nv10_gpio_sense(struct nouveau_gpio *gpio, int line) +nv10_gpio_sense(struct nvkm_gpio *gpio, int line) { if (line < 2) { line = line * 16; @@ -49,7 +48,7 @@ nv10_gpio_sense(struct nouveau_gpio *gpio, int line) } static int -nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) +nv10_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out) { u32 reg, mask, data; @@ -79,7 +78,7 @@ nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) } static void -nv10_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) +nv10_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) { u32 intr = nv_rd32(gpio, 0x001104); u32 stat = nv_rd32(gpio, 0x001144) & intr; @@ -89,7 +88,7 @@ nv10_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) } static void -nv10_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) +nv10_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) { u32 inte = nv_rd32(gpio, 0x001144); if (type & NVKM_GPIO_LO) @@ -99,14 +98,14 @@ nv10_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) nv_wr32(gpio, 0x001144, inte); } -struct nouveau_oclass * -nv10_gpio_oclass = &(struct nouveau_gpio_impl) { +struct nvkm_oclass * +nv10_gpio_oclass = &(struct nvkm_gpio_impl) { .base.handle = NV_SUBDEV(GPIO, 0x10), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_gpio_ctor, - .dtor = _nouveau_gpio_dtor, - .init = _nouveau_gpio_init, - .fini = _nouveau_gpio_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_gpio_ctor, + .dtor = _nvkm_gpio_dtor, + .init = _nvkm_gpio_init, + .fini = _nvkm_gpio_fini, }, .lines = 16, .intr_stat = nv10_gpio_intr_stat, diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c index 2e30d5a62d6e..6a031035bd27 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include "priv.h" void -nv50_gpio_reset(struct nouveau_gpio *gpio, u8 match) +nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match) { - struct nouveau_bios *bios = nouveau_bios(gpio); + struct nvkm_bios *bios = nvkm_bios(gpio); u8 ver, len; u16 entry; int ent = -1; @@ -68,7 +67,7 @@ nv50_gpio_location(int line, u32 *reg, u32 *shift) } int -nv50_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) +nv50_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out) { u32 reg, shift; @@ -80,7 +79,7 @@ nv50_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) } int -nv50_gpio_sense(struct nouveau_gpio *gpio, int line) +nv50_gpio_sense(struct nvkm_gpio *gpio, int line) { u32 reg, shift; @@ -91,7 +90,7 @@ nv50_gpio_sense(struct nouveau_gpio *gpio, int line) } static void -nv50_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) +nv50_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) { u32 intr = nv_rd32(gpio, 0x00e054); u32 stat = nv_rd32(gpio, 0x00e050) & intr; @@ -101,7 +100,7 @@ nv50_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) } static void -nv50_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) +nv50_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) { u32 inte = nv_rd32(gpio, 0x00e050); if (type & NVKM_GPIO_LO) @@ -111,14 +110,14 @@ nv50_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) nv_wr32(gpio, 0x00e050, inte); } -struct nouveau_oclass * -nv50_gpio_oclass = &(struct nouveau_gpio_impl) { +struct nvkm_oclass * +nv50_gpio_oclass = &(struct nvkm_gpio_impl) { .base.handle = NV_SUBDEV(GPIO, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_gpio_ctor, - .dtor = _nouveau_gpio_dtor, - .init = _nouveau_gpio_init, - .fini = _nouveau_gpio_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_gpio_ctor, + .dtor = _nvkm_gpio_dtor, + .init = _nvkm_gpio_init, + .fini = _nvkm_gpio_fini, }, .lines = 16, .intr_stat = nv50_gpio_intr_stat, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h new file mode 100644 index 000000000000..382f8d44e140 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h @@ -0,0 +1,64 @@ +#ifndef __NVKM_GPIO_PRIV_H__ +#define __NVKM_GPIO_PRIV_H__ +#include <subdev/gpio.h> + +#define nvkm_gpio_create(p,e,o,d) \ + nvkm_gpio_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_gpio_destroy(p) ({ \ + struct nvkm_gpio *gpio = (p); \ + _nvkm_gpio_dtor(nv_object(gpio)); \ +}) +#define nvkm_gpio_init(p) ({ \ + struct nvkm_gpio *gpio = (p); \ + _nvkm_gpio_init(nv_object(gpio)); \ +}) +#define nvkm_gpio_fini(p,s) ({ \ + struct nvkm_gpio *gpio = (p); \ + _nvkm_gpio_fini(nv_object(gpio), (s)); \ +}) + +int nvkm_gpio_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +int _nvkm_gpio_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void _nvkm_gpio_dtor(struct nvkm_object *); +int _nvkm_gpio_init(struct nvkm_object *); +int _nvkm_gpio_fini(struct nvkm_object *, bool); + +struct nvkm_gpio_impl { + struct nvkm_oclass base; + int lines; + + /* read and ack pending interrupts, returning only data + * for lines that have not been masked off, while still + * performing the ack for anything that was pending. + */ + void (*intr_stat)(struct nvkm_gpio *, u32 *, u32 *); + + /* mask on/off interrupts for hi/lo transitions on a + * given set of gpio lines + */ + void (*intr_mask)(struct nvkm_gpio *, u32, u32, u32); + + /* configure gpio direction and output value */ + int (*drive)(struct nvkm_gpio *, int line, int dir, int out); + + /* sense current state of given gpio line */ + int (*sense)(struct nvkm_gpio *, int line); + + /*XXX*/ + void (*reset)(struct nvkm_gpio *, u8); +}; + +void nv50_gpio_reset(struct nvkm_gpio *, u8); +int nv50_gpio_drive(struct nvkm_gpio *, int, int, int); +int nv50_gpio_sense(struct nvkm_gpio *, int); + +void g94_gpio_intr_stat(struct nvkm_gpio *, u32 *, u32 *); +void g94_gpio_intr_mask(struct nvkm_gpio *, u32, u32, u32); + +void gf110_gpio_reset(struct nvkm_gpio *, u8); +int gf110_gpio_drive(struct nvkm_gpio *, int, int, int); +int gf110_gpio_sense(struct nvkm_gpio *, int); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild new file mode 100644 index 000000000000..d68307409980 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild @@ -0,0 +1,16 @@ +nvkm-y += nvkm/subdev/i2c/base.o +nvkm-y += nvkm/subdev/i2c/anx9805.o +nvkm-y += nvkm/subdev/i2c/aux.o +nvkm-y += nvkm/subdev/i2c/bit.o +nvkm-y += nvkm/subdev/i2c/pad.o +nvkm-y += nvkm/subdev/i2c/padnv04.o +nvkm-y += nvkm/subdev/i2c/padg94.o +nvkm-y += nvkm/subdev/i2c/padgm204.o +nvkm-y += nvkm/subdev/i2c/nv04.o +nvkm-y += nvkm/subdev/i2c/nv4e.o +nvkm-y += nvkm/subdev/i2c/nv50.o +nvkm-y += nvkm/subdev/i2c/g94.o +nvkm-y += nvkm/subdev/i2c/gf110.o +nvkm-y += nvkm/subdev/i2c/gf117.o +nvkm-y += nvkm/subdev/i2c/gk104.o +nvkm-y += nvkm/subdev/i2c/gm204.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c index 2c2731a6cf91..d17dd1cf3c34 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - #include "port.h" struct anx9805_i2c_port { - struct nouveau_i2c_port base; + struct nvkm_i2c_port base; u32 addr; u32 ctrl; }; static int -anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh) +anx9805_train(struct nvkm_i2c_port *port, int link_nr, int link_bw, bool enh) { struct anx9805_i2c_port *chan = (void *)port; - struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent; + struct nvkm_i2c_port *mast = (void *)nv_object(chan)->parent; u8 tmp, i; DBG("ANX9805 train %d 0x%02x %d\n", link_nr, link_bw, enh); @@ -62,11 +61,11 @@ anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh) } static int -anx9805_aux(struct nouveau_i2c_port *port, bool retry, +anx9805_aux(struct nvkm_i2c_port *port, bool retry, u8 type, u32 addr, u8 *data, u8 size) { struct anx9805_i2c_port *chan = (void *)port; - struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent; + struct nvkm_i2c_port *mast = (void *)nv_object(chan)->parent; int i, ret = -ETIMEDOUT; u8 buf[16] = {}; u8 tmp; @@ -116,25 +115,25 @@ done: return ret; } -static const struct nouveau_i2c_func +static const struct nvkm_i2c_func anx9805_aux_func = { .aux = anx9805_aux, .lnk_ctl = anx9805_train, }; static int -anx9805_aux_chan_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +anx9805_aux_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { - struct nouveau_i2c_port *mast = (void *)parent; + struct nvkm_i2c_port *mast = (void *)parent; struct anx9805_i2c_port *chan; int ret; - ret = nouveau_i2c_port_create(parent, engine, oclass, index, - &nouveau_i2c_aux_algo, &anx9805_aux_func, - &chan); + ret = nvkm_i2c_port_create(parent, engine, oclass, index, + &nvkm_i2c_aux_algo, &anx9805_aux_func, + &chan); *pobject = nv_object(chan); if (ret) return ret; @@ -156,22 +155,23 @@ anx9805_aux_chan_ctor(struct nouveau_object *parent, struct i2c_algo_bit_data *algo = mast->adapter.algo_data; algo->udelay = max(algo->udelay, 40); } + return 0; } -static struct nouveau_ofuncs +static struct nvkm_ofuncs anx9805_aux_ofuncs = { .ctor = anx9805_aux_chan_ctor, - .dtor = _nouveau_i2c_port_dtor, - .init = _nouveau_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .dtor = _nvkm_i2c_port_dtor, + .init = _nvkm_i2c_port_init, + .fini = _nvkm_i2c_port_fini, }; static int anx9805_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { struct anx9805_i2c_port *port = adap->algo_data; - struct nouveau_i2c_port *mast = (void *)nv_object(port)->parent; + struct nvkm_i2c_port *mast = (void *)nv_object(port)->parent; struct i2c_msg *msg = msgs; int ret = -ETIMEDOUT; int i, j, cnt = num; @@ -233,23 +233,22 @@ anx9805_i2c_algo = { .functionality = anx9805_func }; -static const struct nouveau_i2c_func +static const struct nvkm_i2c_func anx9805_i2c_func = { }; static int -anx9805_ddc_port_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +anx9805_ddc_port_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { - struct nouveau_i2c_port *mast = (void *)parent; + struct nvkm_i2c_port *mast = (void *)parent; struct anx9805_i2c_port *port; int ret; - ret = nouveau_i2c_port_create(parent, engine, oclass, index, - &anx9805_i2c_algo, &anx9805_i2c_func, - &port); + ret = nvkm_i2c_port_create(parent, engine, oclass, index, + &anx9805_i2c_algo, &anx9805_i2c_func, &port); *pobject = nv_object(port); if (ret) return ret; @@ -271,19 +270,20 @@ anx9805_ddc_port_ctor(struct nouveau_object *parent, struct i2c_algo_bit_data *algo = mast->adapter.algo_data; algo->udelay = max(algo->udelay, 40); } + return 0; } -static struct nouveau_ofuncs +static struct nvkm_ofuncs anx9805_ddc_ofuncs = { .ctor = anx9805_ddc_port_ctor, - .dtor = _nouveau_i2c_port_dtor, - .init = _nouveau_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .dtor = _nvkm_i2c_port_dtor, + .init = _nvkm_i2c_port_init, + .fini = _nvkm_i2c_port_fini, }; -struct nouveau_oclass -nouveau_anx9805_sclass[] = { +struct nvkm_oclass +nvkm_anx9805_sclass[] = { { .handle = NV_I2C_TYPE_EXTDDC(0x0d), .ofuncs = &anx9805_ddc_ofuncs }, { .handle = NV_I2C_TYPE_EXTAUX(0x0d), .ofuncs = &anx9805_aux_ofuncs }, { .handle = NV_I2C_TYPE_EXTDDC(0x0e), .ofuncs = &anx9805_ddc_ofuncs }, diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c index 02eb42be2e9e..1c18860f80d1 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include "priv.h" int -nv_rdaux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size) +nv_rdaux(struct nvkm_i2c_port *port, u32 addr, u8 *data, u8 size) { - struct nouveau_i2c *i2c = nouveau_i2c(port); + struct nvkm_i2c *i2c = nvkm_i2c(port); if (port->func->aux) { int ret = i2c->acquire(port, 0); if (ret == 0) { @@ -40,9 +39,9 @@ nv_rdaux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size) } int -nv_wraux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size) +nv_wraux(struct nvkm_i2c_port *port, u32 addr, u8 *data, u8 size) { - struct nouveau_i2c *i2c = nouveau_i2c(port); + struct nvkm_i2c *i2c = nvkm_i2c(port); if (port->func->aux) { int ret = i2c->acquire(port, 0); if (ret == 0) { @@ -57,8 +56,8 @@ nv_wraux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size) static int aux_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { - struct nouveau_i2c_port *port = adap->algo_data; - struct nouveau_i2c *i2c = nouveau_i2c(port); + struct nvkm_i2c_port *port = adap->algo_data; + struct nvkm_i2c *i2c = nvkm_i2c(port); struct i2c_msg *msg = msgs; int ret, mcnt = num; @@ -108,7 +107,7 @@ aux_func(struct i2c_adapter *adap) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; } -const struct i2c_algorithm nouveau_i2c_aux_algo = { +const struct i2c_algorithm nvkm_i2c_aux_algo = { .master_xfer = aux_xfer, .functionality = aux_func }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c index 0dc605db7ec8..9200f122c02c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c @@ -21,18 +21,14 @@ * * Authors: Ben Skeggs */ +#include "priv.h" +#include "pad.h" +#include <core/device.h> +#include <core/notify.h> #include <core/option.h> -#include <core/object.h> -#include <core/event.h> - #include <subdev/bios.h> #include <subdev/bios/dcb.h> -#include <subdev/bios/i2c.h> -#include <subdev/vga.h> - -#include "priv.h" -#include "pad.h" /****************************************************************************** * interface to linux i2c bit-banging algorithm @@ -45,46 +41,46 @@ #endif static int -nouveau_i2c_pre_xfer(struct i2c_adapter *adap) +nvkm_i2c_pre_xfer(struct i2c_adapter *adap) { struct i2c_algo_bit_data *bit = adap->algo_data; - struct nouveau_i2c_port *port = bit->data; - return nouveau_i2c(port)->acquire(port, bit->timeout); + struct nvkm_i2c_port *port = bit->data; + return nvkm_i2c(port)->acquire(port, bit->timeout); } static void -nouveau_i2c_post_xfer(struct i2c_adapter *adap) +nvkm_i2c_post_xfer(struct i2c_adapter *adap) { struct i2c_algo_bit_data *bit = adap->algo_data; - struct nouveau_i2c_port *port = bit->data; - return nouveau_i2c(port)->release(port); + struct nvkm_i2c_port *port = bit->data; + return nvkm_i2c(port)->release(port); } static void -nouveau_i2c_setscl(void *data, int state) +nvkm_i2c_setscl(void *data, int state) { - struct nouveau_i2c_port *port = data; + struct nvkm_i2c_port *port = data; port->func->drive_scl(port, state); } static void -nouveau_i2c_setsda(void *data, int state) +nvkm_i2c_setsda(void *data, int state) { - struct nouveau_i2c_port *port = data; + struct nvkm_i2c_port *port = data; port->func->drive_sda(port, state); } static int -nouveau_i2c_getscl(void *data) +nvkm_i2c_getscl(void *data) { - struct nouveau_i2c_port *port = data; + struct nvkm_i2c_port *port = data; return port->func->sense_scl(port); } static int -nouveau_i2c_getsda(void *data) +nvkm_i2c_getsda(void *data) { - struct nouveau_i2c_port *port = data; + struct nvkm_i2c_port *port = data; return port->func->sense_sda(port); } @@ -93,42 +89,41 @@ nouveau_i2c_getsda(void *data) *****************************************************************************/ int -_nouveau_i2c_port_fini(struct nouveau_object *object, bool suspend) +_nvkm_i2c_port_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_i2c_port *port = (void *)object; + struct nvkm_i2c_port *port = (void *)object; struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port); nv_ofuncs(pad)->fini(nv_object(pad), suspend); - return nouveau_object_fini(&port->base, suspend); + return nvkm_object_fini(&port->base, suspend); } void -_nouveau_i2c_port_dtor(struct nouveau_object *object) +_nvkm_i2c_port_dtor(struct nvkm_object *object) { - struct nouveau_i2c_port *port = (void *)object; + struct nvkm_i2c_port *port = (void *)object; i2c_del_adapter(&port->adapter); - nouveau_object_destroy(&port->base); + nvkm_object_destroy(&port->base); } int -nouveau_i2c_port_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, u8 index, - const struct i2c_algorithm *algo, - const struct nouveau_i2c_func *func, - int size, void **pobject) +nvkm_i2c_port_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u8 index, + const struct i2c_algorithm *algo, + const struct nvkm_i2c_func *func, + int size, void **pobject) { - struct nouveau_device *device = nv_device(engine); - struct nouveau_i2c *i2c = (void *)engine; - struct nouveau_i2c_port *port; + struct nvkm_device *device = nv_device(parent); + struct nvkm_i2c *i2c = nvkm_i2c(parent); + struct nvkm_i2c_port *port; int ret; - ret = nouveau_object_create_(parent, engine, oclass, 0, size, pobject); + ret = nvkm_object_create_(parent, engine, oclass, 0, size, pobject); port = *pobject; if (ret) return ret; snprintf(port->adapter.name, sizeof(port->adapter.name), - "nouveau-%s-%d", device->name, index); + "nvkm-%s-%d", device->name, index); port->adapter.owner = THIS_MODULE; port->adapter.dev.parent = nv_device_base(device); port->index = index; @@ -136,8 +131,8 @@ nouveau_i2c_port_create_(struct nouveau_object *parent, port->func = func; mutex_init(&port->mutex); - if ( algo == &nouveau_i2c_bit_algo && - !nouveau_boolopt(device->cfgopt, "NvI2C", CSTMSEL)) { + if ( algo == &nvkm_i2c_bit_algo && + !nvkm_boolopt(device->cfgopt, "NvI2C", CSTMSEL)) { struct i2c_algo_bit_data *bit; bit = kzalloc(sizeof(*bit), GFP_KERNEL); @@ -147,12 +142,12 @@ nouveau_i2c_port_create_(struct nouveau_object *parent, bit->udelay = 10; bit->timeout = usecs_to_jiffies(2200); bit->data = port; - bit->pre_xfer = nouveau_i2c_pre_xfer; - bit->post_xfer = nouveau_i2c_post_xfer; - bit->setsda = nouveau_i2c_setsda; - bit->setscl = nouveau_i2c_setscl; - bit->getsda = nouveau_i2c_getsda; - bit->getscl = nouveau_i2c_getscl; + bit->pre_xfer = nvkm_i2c_pre_xfer; + bit->post_xfer = nvkm_i2c_post_xfer; + bit->setsda = nvkm_i2c_setsda; + bit->setscl = nvkm_i2c_setscl; + bit->getsda = nvkm_i2c_getsda; + bit->getscl = nvkm_i2c_getscl; port->adapter.algo_data = bit; ret = i2c_bit_add_bus(&port->adapter); @@ -171,11 +166,11 @@ nouveau_i2c_port_create_(struct nouveau_object *parent, * base i2c subdev class implementation *****************************************************************************/ -static struct nouveau_i2c_port * -nouveau_i2c_find(struct nouveau_i2c *i2c, u8 index) +static struct nvkm_i2c_port * +nvkm_i2c_find(struct nvkm_i2c *i2c, u8 index) { - struct nouveau_bios *bios = nouveau_bios(i2c); - struct nouveau_i2c_port *port; + struct nvkm_bios *bios = nvkm_bios(i2c); + struct nvkm_i2c_port *port; if (index == NV_I2C_DEFAULT(0) || index == NV_I2C_DEFAULT(1)) { @@ -200,10 +195,10 @@ nouveau_i2c_find(struct nouveau_i2c *i2c, u8 index) return NULL; } -static struct nouveau_i2c_port * -nouveau_i2c_find_type(struct nouveau_i2c *i2c, u16 type) +static struct nvkm_i2c_port * +nvkm_i2c_find_type(struct nvkm_i2c *i2c, u16 type) { - struct nouveau_i2c_port *port; + struct nvkm_i2c_port *port; list_for_each_entry(port, &i2c->ports, head) { if (nv_hclass(port) == type) @@ -214,10 +209,10 @@ nouveau_i2c_find_type(struct nouveau_i2c *i2c, u16 type) } static void -nouveau_i2c_release_pad(struct nouveau_i2c_port *port) +nvkm_i2c_release_pad(struct nvkm_i2c_port *port) { struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port); - struct nouveau_i2c *i2c = nouveau_i2c(port); + struct nvkm_i2c *i2c = nvkm_i2c(port); if (atomic_dec_and_test(&nv_object(pad)->usecount)) { nv_ofuncs(pad)->fini(nv_object(pad), false); @@ -226,18 +221,18 @@ nouveau_i2c_release_pad(struct nouveau_i2c_port *port) } static int -nouveau_i2c_try_acquire_pad(struct nouveau_i2c_port *port) +nvkm_i2c_try_acquire_pad(struct nvkm_i2c_port *port) { struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port); if (atomic_add_return(1, &nv_object(pad)->usecount) != 1) { - struct nouveau_object *owner = (void *)pad->port; + struct nvkm_object *owner = (void *)pad->port; do { if (owner == (void *)port) return 0; owner = owner->parent; } while(owner); - nouveau_i2c_release_pad(port); + nvkm_i2c_release_pad(port); return -EBUSY; } @@ -247,48 +242,48 @@ nouveau_i2c_try_acquire_pad(struct nouveau_i2c_port *port) } static int -nouveau_i2c_acquire_pad(struct nouveau_i2c_port *port, unsigned long timeout) +nvkm_i2c_acquire_pad(struct nvkm_i2c_port *port, unsigned long timeout) { - struct nouveau_i2c *i2c = nouveau_i2c(port); + struct nvkm_i2c *i2c = nvkm_i2c(port); if (timeout) { if (wait_event_timeout(i2c->wait, - nouveau_i2c_try_acquire_pad(port) == 0, + nvkm_i2c_try_acquire_pad(port) == 0, timeout) == 0) return -EBUSY; } else { - wait_event(i2c->wait, nouveau_i2c_try_acquire_pad(port) == 0); + wait_event(i2c->wait, nvkm_i2c_try_acquire_pad(port) == 0); } return 0; } static void -nouveau_i2c_release(struct nouveau_i2c_port *port) +nvkm_i2c_release(struct nvkm_i2c_port *port) __releases(pad->mutex) { - nouveau_i2c(port)->release_pad(port); + nvkm_i2c(port)->release_pad(port); mutex_unlock(&port->mutex); } static int -nouveau_i2c_acquire(struct nouveau_i2c_port *port, unsigned long timeout) +nvkm_i2c_acquire(struct nvkm_i2c_port *port, unsigned long timeout) __acquires(pad->mutex) { int ret; mutex_lock(&port->mutex); - if ((ret = nouveau_i2c(port)->acquire_pad(port, timeout))) + if ((ret = nvkm_i2c(port)->acquire_pad(port, timeout))) mutex_unlock(&port->mutex); return ret; } static int -nouveau_i2c_identify(struct nouveau_i2c *i2c, int index, const char *what, - struct nouveau_i2c_board_info *info, - bool (*match)(struct nouveau_i2c_port *, - struct i2c_board_info *, void *), void *data) +nvkm_i2c_identify(struct nvkm_i2c *i2c, int index, const char *what, + struct nvkm_i2c_board_info *info, + bool (*match)(struct nvkm_i2c_port *, + struct i2c_board_info *, void *), void *data) { - struct nouveau_i2c_port *port = nouveau_i2c_find(i2c, index); + struct nvkm_i2c_port *port = nvkm_i2c_find(i2c, index); int i; if (!port) { @@ -327,27 +322,27 @@ nouveau_i2c_identify(struct nouveau_i2c *i2c, int index, const char *what, } static void -nouveau_i2c_intr_fini(struct nvkm_event *event, int type, int index) +nvkm_i2c_intr_fini(struct nvkm_event *event, int type, int index) { - struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event); - struct nouveau_i2c_port *port = i2c->find(i2c, index); - const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass; + struct nvkm_i2c *i2c = container_of(event, typeof(*i2c), event); + struct nvkm_i2c_port *port = i2c->find(i2c, index); + const struct nvkm_i2c_impl *impl = (void *)nv_object(i2c)->oclass; if (port && port->aux >= 0) impl->aux_mask(i2c, type, 1 << port->aux, 0); } static void -nouveau_i2c_intr_init(struct nvkm_event *event, int type, int index) +nvkm_i2c_intr_init(struct nvkm_event *event, int type, int index) { - struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event); - struct nouveau_i2c_port *port = i2c->find(i2c, index); - const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass; + struct nvkm_i2c *i2c = container_of(event, typeof(*i2c), event); + struct nvkm_i2c_port *port = i2c->find(i2c, index); + const struct nvkm_i2c_impl *impl = (void *)nv_object(i2c)->oclass; if (port && port->aux >= 0) impl->aux_mask(i2c, type, 1 << port->aux, 1 << port->aux); } static int -nouveau_i2c_intr_ctor(struct nouveau_object *object, void *data, u32 size, +nvkm_i2c_intr_ctor(struct nvkm_object *object, void *data, u32 size, struct nvkm_notify *notify) { struct nvkm_i2c_ntfy_req *req = data; @@ -361,11 +356,11 @@ nouveau_i2c_intr_ctor(struct nouveau_object *object, void *data, u32 size, } static void -nouveau_i2c_intr(struct nouveau_subdev *subdev) +nvkm_i2c_intr(struct nvkm_subdev *subdev) { - struct nouveau_i2c_impl *impl = (void *)nv_oclass(subdev); - struct nouveau_i2c *i2c = nouveau_i2c(subdev); - struct nouveau_i2c_port *port; + struct nvkm_i2c_impl *impl = (void *)nv_oclass(subdev); + struct nvkm_i2c *i2c = nvkm_i2c(subdev); + struct nvkm_i2c_port *port; u32 hi, lo, rq, tx, e; if (impl->aux_stat) { @@ -393,18 +388,18 @@ nouveau_i2c_intr(struct nouveau_subdev *subdev) } static const struct nvkm_event_func -nouveau_i2c_intr_func = { - .ctor = nouveau_i2c_intr_ctor, - .init = nouveau_i2c_intr_init, - .fini = nouveau_i2c_intr_fini, +nvkm_i2c_intr_func = { + .ctor = nvkm_i2c_intr_ctor, + .init = nvkm_i2c_intr_init, + .fini = nvkm_i2c_intr_fini, }; int -_nouveau_i2c_fini(struct nouveau_object *object, bool suspend) +_nvkm_i2c_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_i2c_impl *impl = (void *)nv_oclass(object); - struct nouveau_i2c *i2c = (void *)object; - struct nouveau_i2c_port *port; + struct nvkm_i2c_impl *impl = (void *)nv_oclass(object); + struct nvkm_i2c *i2c = (void *)object; + struct nvkm_i2c_port *port; u32 mask; int ret; @@ -419,7 +414,7 @@ _nouveau_i2c_fini(struct nouveau_object *object, bool suspend) impl->aux_stat(i2c, &mask, &mask, &mask, &mask); } - return nouveau_subdev_fini(&i2c->base, suspend); + return nvkm_subdev_fini(&i2c->base, suspend); fail: list_for_each_entry_continue_reverse(port, &i2c->ports, head) { nv_ofuncs(port)->init(nv_object(port)); @@ -429,13 +424,13 @@ fail: } int -_nouveau_i2c_init(struct nouveau_object *object) +_nvkm_i2c_init(struct nvkm_object *object) { - struct nouveau_i2c *i2c = (void *)object; - struct nouveau_i2c_port *port; + struct nvkm_i2c *i2c = (void *)object; + struct nvkm_i2c_port *port; int ret; - ret = nouveau_subdev_init(&i2c->base); + ret = nvkm_subdev_init(&i2c->base); if (ret == 0) { list_for_each_entry(port, &i2c->ports, head) { ret = nv_ofuncs(port)->init(nv_object(port)); @@ -454,33 +449,33 @@ fail: } void -_nouveau_i2c_dtor(struct nouveau_object *object) +_nvkm_i2c_dtor(struct nvkm_object *object) { - struct nouveau_i2c *i2c = (void *)object; - struct nouveau_i2c_port *port, *temp; + struct nvkm_i2c *i2c = (void *)object; + struct nvkm_i2c_port *port, *temp; nvkm_event_fini(&i2c->event); list_for_each_entry_safe(port, temp, &i2c->ports, head) { - nouveau_object_ref(NULL, (struct nouveau_object **)&port); + nvkm_object_ref(NULL, (struct nvkm_object **)&port); } - nouveau_subdev_destroy(&i2c->base); + nvkm_subdev_destroy(&i2c->base); } -static struct nouveau_oclass * -nouveau_i2c_extdev_sclass[] = { - nouveau_anx9805_sclass, +static struct nvkm_oclass * +nvkm_i2c_extdev_sclass[] = { + nvkm_anx9805_sclass, }; static void -nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type, - struct dcb_i2c_entry *info) +nvkm_i2c_create_port(struct nvkm_i2c *i2c, int index, u8 type, + struct dcb_i2c_entry *info) { - const struct nouveau_i2c_impl *impl = (void *)nv_oclass(i2c); - struct nouveau_oclass *oclass; - struct nouveau_object *parent; - struct nouveau_object *object; + const struct nvkm_i2c_impl *impl = (void *)nv_oclass(i2c); + struct nvkm_oclass *oclass; + struct nvkm_object *parent; + struct nvkm_object *object; int ret, pad; if (info->share != DCB_I2C_UNUSED) { @@ -494,8 +489,8 @@ nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type, oclass = impl->pad_x; } - ret = nouveau_object_ctor(NULL, nv_object(i2c), oclass, NULL, pad, - &parent); + ret = nvkm_object_ctor(nv_object(i2c), NULL, oclass, + NULL, pad, &parent); if (ret < 0) return; @@ -503,44 +498,40 @@ nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type, do { ret = -EINVAL; if (oclass->handle == type) { - ret = nouveau_object_ctor(parent, nv_object(i2c), - oclass, info, index, - &object); + ret = nvkm_object_ctor(parent, NULL, oclass, + info, index, &object); } } while (ret && (++oclass)->handle); - nouveau_object_ref(NULL, &parent); + nvkm_object_ref(NULL, &parent); } int -nouveau_i2c_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int length, void **pobject) +nvkm_i2c_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_bios *bios = nouveau_bios(parent); - struct nouveau_i2c *i2c; - struct nouveau_object *object; + struct nvkm_bios *bios = nvkm_bios(parent); + struct nvkm_i2c *i2c; + struct nvkm_object *object; struct dcb_i2c_entry info; int ret, i, j, index = -1; struct dcb_output outp; u8 ver, hdr; u32 data; - ret = nouveau_subdev_create(parent, engine, oclass, 0, - "I2C", "i2c", &i2c); + ret = nvkm_subdev_create(parent, engine, oclass, 0, "I2C", "i2c", &i2c); *pobject = nv_object(i2c); if (ret) return ret; - nv_subdev(i2c)->intr = nouveau_i2c_intr; - i2c->find = nouveau_i2c_find; - i2c->find_type = nouveau_i2c_find_type; - i2c->acquire_pad = nouveau_i2c_acquire_pad; - i2c->release_pad = nouveau_i2c_release_pad; - i2c->acquire = nouveau_i2c_acquire; - i2c->release = nouveau_i2c_release; - i2c->identify = nouveau_i2c_identify; + nv_subdev(i2c)->intr = nvkm_i2c_intr; + i2c->find = nvkm_i2c_find; + i2c->find_type = nvkm_i2c_find_type; + i2c->acquire_pad = nvkm_i2c_acquire_pad; + i2c->release_pad = nvkm_i2c_release_pad; + i2c->acquire = nvkm_i2c_acquire; + i2c->release = nvkm_i2c_release; + i2c->identify = nvkm_i2c_identify; init_waitqueue_head(&i2c->wait); INIT_LIST_HEAD(&i2c->ports); @@ -549,23 +540,21 @@ nouveau_i2c_create_(struct nouveau_object *parent, case DCB_I2C_NV04_BIT: case DCB_I2C_NV4E_BIT: case DCB_I2C_NVIO_BIT: - nouveau_i2c_create_port(i2c, NV_I2C_PORT(index), - info.type, &info); + nvkm_i2c_create_port(i2c, NV_I2C_PORT(index), + info.type, &info); break; case DCB_I2C_NVIO_AUX: - nouveau_i2c_create_port(i2c, NV_I2C_AUX(index), - info.type, &info); + nvkm_i2c_create_port(i2c, NV_I2C_AUX(index), + info.type, &info); break; case DCB_I2C_PMGR: if (info.drive != DCB_I2C_UNUSED) { - nouveau_i2c_create_port(i2c, NV_I2C_PORT(index), - DCB_I2C_NVIO_BIT, - &info); + nvkm_i2c_create_port(i2c, NV_I2C_PORT(index), + DCB_I2C_NVIO_BIT, &info); } if (info.auxch != DCB_I2C_UNUSED) { - nouveau_i2c_create_port(i2c, NV_I2C_AUX(index), - DCB_I2C_NVIO_AUX, - &info); + nvkm_i2c_create_port(i2c, NV_I2C_AUX(index), + DCB_I2C_NVIO_AUX, &info); } break; case DCB_I2C_UNUSED: @@ -597,20 +586,19 @@ nouveau_i2c_create_(struct nouveau_object *parent, ret = -ENODEV; j = -1; - while (ret && ++j < ARRAY_SIZE(nouveau_i2c_extdev_sclass)) { + while (ret && ++j < ARRAY_SIZE(nvkm_i2c_extdev_sclass)) { parent = nv_object(i2c->find(i2c, outp.i2c_index)); - oclass = nouveau_i2c_extdev_sclass[j]; + oclass = nvkm_i2c_extdev_sclass[j]; do { if (oclass->handle != info.type) continue; - ret = nouveau_object_ctor(parent, *pobject, - oclass, NULL, - index++, &object); + ret = nvkm_object_ctor(parent, NULL, oclass, + NULL, index++, &object); } while (ret && (++oclass)->handle); } } - ret = nvkm_event_init(&nouveau_i2c_intr_func, 4, index, &i2c->event); + ret = nvkm_event_init(&nvkm_i2c_intr_func, 4, index, &i2c->event); if (ret) return ret; @@ -618,14 +606,14 @@ nouveau_i2c_create_(struct nouveau_object *parent, } int -_nouveau_i2c_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +_nvkm_i2c_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_i2c *i2c; + struct nvkm_i2c *i2c; int ret; - ret = nouveau_i2c_create(parent, engine, oclass, &i2c); + ret = nvkm_i2c_create(parent, engine, oclass, &i2c); *pobject = nv_object(i2c); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c index 813ffc96e864..861a453d2a67 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c @@ -21,7 +21,6 @@ * * Authors: Ben Skeggs */ - #include "priv.h" #ifdef CONFIG_NOUVEAU_I2C_INTERNAL @@ -30,37 +29,37 @@ #define T_HOLD 5000 static inline void -i2c_drive_scl(struct nouveau_i2c_port *port, int state) +i2c_drive_scl(struct nvkm_i2c_port *port, int state) { port->func->drive_scl(port, state); } static inline void -i2c_drive_sda(struct nouveau_i2c_port *port, int state) +i2c_drive_sda(struct nvkm_i2c_port *port, int state) { port->func->drive_sda(port, state); } static inline int -i2c_sense_scl(struct nouveau_i2c_port *port) +i2c_sense_scl(struct nvkm_i2c_port *port) { return port->func->sense_scl(port); } static inline int -i2c_sense_sda(struct nouveau_i2c_port *port) +i2c_sense_sda(struct nvkm_i2c_port *port) { return port->func->sense_sda(port); } static void -i2c_delay(struct nouveau_i2c_port *port, u32 nsec) +i2c_delay(struct nvkm_i2c_port *port, u32 nsec) { udelay((nsec + 500) / 1000); } static bool -i2c_raise_scl(struct nouveau_i2c_port *port) +i2c_raise_scl(struct nvkm_i2c_port *port) { u32 timeout = T_TIMEOUT / T_RISEFALL; @@ -73,7 +72,7 @@ i2c_raise_scl(struct nouveau_i2c_port *port) } static int -i2c_start(struct nouveau_i2c_port *port) +i2c_start(struct nvkm_i2c_port *port) { int ret = 0; @@ -93,7 +92,7 @@ i2c_start(struct nouveau_i2c_port *port) } static void -i2c_stop(struct nouveau_i2c_port *port) +i2c_stop(struct nvkm_i2c_port *port) { i2c_drive_scl(port, 0); i2c_drive_sda(port, 0); @@ -106,7 +105,7 @@ i2c_stop(struct nouveau_i2c_port *port) } static int -i2c_bitw(struct nouveau_i2c_port *port, int sda) +i2c_bitw(struct nvkm_i2c_port *port, int sda) { i2c_drive_sda(port, sda); i2c_delay(port, T_RISEFALL); @@ -121,7 +120,7 @@ i2c_bitw(struct nouveau_i2c_port *port, int sda) } static int -i2c_bitr(struct nouveau_i2c_port *port) +i2c_bitr(struct nvkm_i2c_port *port) { int sda; @@ -140,7 +139,7 @@ i2c_bitr(struct nouveau_i2c_port *port) } static int -i2c_get_byte(struct nouveau_i2c_port *port, u8 *byte, bool last) +i2c_get_byte(struct nvkm_i2c_port *port, u8 *byte, bool last) { int i, bit; @@ -156,7 +155,7 @@ i2c_get_byte(struct nouveau_i2c_port *port, u8 *byte, bool last) } static int -i2c_put_byte(struct nouveau_i2c_port *port, u8 byte) +i2c_put_byte(struct nvkm_i2c_port *port, u8 byte) { int i, ret; for (i = 7; i >= 0; i--) { @@ -172,7 +171,7 @@ i2c_put_byte(struct nouveau_i2c_port *port, u8 byte) } static int -i2c_addr(struct nouveau_i2c_port *port, struct i2c_msg *msg) +i2c_addr(struct nvkm_i2c_port *port, struct i2c_msg *msg) { u32 addr = msg->addr << 1; if (msg->flags & I2C_M_RD) @@ -183,11 +182,11 @@ i2c_addr(struct nouveau_i2c_port *port, struct i2c_msg *msg) static int i2c_bit_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { - struct nouveau_i2c_port *port = adap->algo_data; + struct nvkm_i2c_port *port = adap->algo_data; struct i2c_msg *msg = msgs; int ret = 0, mcnt = num; - ret = nouveau_i2c(port)->acquire(port, nsecs_to_jiffies(T_TIMEOUT)); + ret = nvkm_i2c(port)->acquire(port, nsecs_to_jiffies(T_TIMEOUT)); if (ret) return ret; @@ -211,7 +210,7 @@ i2c_bit_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) } i2c_stop(port); - nouveau_i2c(port)->release(port); + nvkm_i2c(port)->release(port); return (ret < 0) ? ret : num; } #else @@ -228,7 +227,7 @@ i2c_bit_func(struct i2c_adapter *adap) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; } -const struct i2c_algorithm nouveau_i2c_bit_algo = { +const struct i2c_algorithm nvkm_i2c_bit_algo = { .master_xfer = i2c_bit_xfer, .functionality = i2c_bit_func }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c index e383ee81f4d2..2a2dd47b9835 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c @@ -21,11 +21,10 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" void -nv94_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) +g94_aux_stat(struct nvkm_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) { u32 intr = nv_rd32(i2c, 0x00e06c); u32 stat = nv_rd32(i2c, 0x00e068) & intr, i; @@ -39,7 +38,7 @@ nv94_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) } void -nv94_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data) +g94_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data) { u32 temp = nv_rd32(i2c, 0x00e068), i; for (i = 0; i < 8; i++) { @@ -58,13 +57,13 @@ nv94_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data) #define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args) static void -auxch_fini(struct nouveau_i2c *aux, int ch) +auxch_fini(struct nvkm_i2c *aux, int ch) { nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000); } static int -auxch_init(struct nouveau_i2c *aux, int ch) +auxch_init(struct nvkm_i2c *aux, int ch) { const u32 unksel = 1; /* nfi which to use, or if it matters.. */ const u32 ureq = unksel ? 0x00100000 : 0x00200000; @@ -99,10 +98,10 @@ auxch_init(struct nouveau_i2c *aux, int ch) } int -nv94_aux(struct nouveau_i2c_port *base, bool retry, +g94_aux(struct nvkm_i2c_port *base, bool retry, u8 type, u32 addr, u8 *data, u8 size) { - struct nouveau_i2c *aux = nouveau_i2c(base); + struct nvkm_i2c *aux = nvkm_i2c(base); struct nv50_i2c_port *port = (void *)base; u32 ctrl, stat, timeout, retries; u32 xbuf[4] = {}; @@ -185,8 +184,8 @@ out: return ret < 0 ? ret : (stat & 0x000f0000) >> 16; } -static const struct nouveau_i2c_func -nv94_i2c_func = { +static const struct nvkm_i2c_func +g94_i2c_func = { .drive_scl = nv50_i2c_drive_scl, .drive_sda = nv50_i2c_drive_sda, .sense_scl = nv50_i2c_sense_scl, @@ -194,17 +193,16 @@ nv94_i2c_func = { }; static int -nv94_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +g94_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { struct dcb_i2c_entry *info = data; struct nv50_i2c_port *port; int ret; - ret = nouveau_i2c_port_create(parent, engine, oclass, index, - &nouveau_i2c_bit_algo, &nv94_i2c_func, - &port); + ret = nvkm_i2c_port_create(parent, engine, oclass, index, + &nvkm_i2c_bit_algo, &g94_i2c_func, &port); *pobject = nv_object(port); if (ret) return ret; @@ -217,23 +215,22 @@ nv94_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -static const struct nouveau_i2c_func -nv94_aux_func = { - .aux = nv94_aux, +static const struct nvkm_i2c_func +g94_aux_func = { + .aux = g94_aux, }; int -nv94_aux_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +g94_aux_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { struct dcb_i2c_entry *info = data; struct nv50_i2c_port *port; int ret; - ret = nouveau_i2c_port_create(parent, engine, oclass, index, - &nouveau_i2c_aux_algo, &nv94_aux_func, - &port); + ret = nvkm_i2c_port_create(parent, engine, oclass, index, + &nvkm_i2c_aux_algo, &g94_aux_func, &port); *pobject = nv_object(port); if (ret) return ret; @@ -243,40 +240,40 @@ nv94_aux_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -static struct nouveau_oclass -nv94_i2c_sclass[] = { +static struct nvkm_oclass +g94_i2c_sclass[] = { { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv94_i2c_port_ctor, - .dtor = _nouveau_i2c_port_dtor, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g94_i2c_port_ctor, + .dtor = _nvkm_i2c_port_dtor, .init = nv50_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .fini = _nvkm_i2c_port_fini, }, }, { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv94_aux_port_ctor, - .dtor = _nouveau_i2c_port_dtor, - .init = _nouveau_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g94_aux_port_ctor, + .dtor = _nvkm_i2c_port_dtor, + .init = _nvkm_i2c_port_init, + .fini = _nvkm_i2c_port_fini, }, }, {} }; -struct nouveau_oclass * -nv94_i2c_oclass = &(struct nouveau_i2c_impl) { +struct nvkm_oclass * +g94_i2c_oclass = &(struct nvkm_i2c_impl) { .base.handle = NV_SUBDEV(I2C, 0x94), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_i2c_ctor, - .dtor = _nouveau_i2c_dtor, - .init = _nouveau_i2c_init, - .fini = _nouveau_i2c_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_i2c_ctor, + .dtor = _nvkm_i2c_dtor, + .init = _nvkm_i2c_init, + .fini = _nvkm_i2c_fini, }, - .sclass = nv94_i2c_sclass, + .sclass = g94_i2c_sclass, .pad_x = &nv04_i2c_pad_oclass, - .pad_s = &nv94_i2c_pad_oclass, + .pad_s = &g94_i2c_pad_oclass, .aux = 4, - .aux_stat = nv94_aux_stat, - .aux_mask = nv94_aux_mask, + .aux_stat = g94_aux_stat, + .aux_mask = g94_aux_mask, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf110.c index fd99380502ec..4d4ac6638140 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf110.c @@ -21,45 +21,43 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" static int -nvd0_i2c_sense_scl(struct nouveau_i2c_port *base) +gf110_i2c_sense_scl(struct nvkm_i2c_port *base) { - struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv50_i2c_port *port = (void *)base; return !!(nv_rd32(priv, port->addr) & 0x00000010); } static int -nvd0_i2c_sense_sda(struct nouveau_i2c_port *base) +gf110_i2c_sense_sda(struct nvkm_i2c_port *base) { - struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv50_i2c_port *port = (void *)base; return !!(nv_rd32(priv, port->addr) & 0x00000020); } -static const struct nouveau_i2c_func -nvd0_i2c_func = { +static const struct nvkm_i2c_func +gf110_i2c_func = { .drive_scl = nv50_i2c_drive_scl, .drive_sda = nv50_i2c_drive_sda, - .sense_scl = nvd0_i2c_sense_scl, - .sense_sda = nvd0_i2c_sense_sda, + .sense_scl = gf110_i2c_sense_scl, + .sense_sda = gf110_i2c_sense_sda, }; int -nvd0_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +gf110_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { struct dcb_i2c_entry *info = data; struct nv50_i2c_port *port; int ret; - ret = nouveau_i2c_port_create(parent, engine, oclass, index, - &nouveau_i2c_bit_algo, &nvd0_i2c_func, - &port); + ret = nvkm_i2c_port_create(parent, engine, oclass, index, + &nvkm_i2c_bit_algo, &gf110_i2c_func, &port); *pobject = nv_object(port); if (ret) return ret; @@ -69,40 +67,40 @@ nvd0_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass -nvd0_i2c_sclass[] = { +struct nvkm_oclass +gf110_i2c_sclass[] = { { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvd0_i2c_port_ctor, - .dtor = _nouveau_i2c_port_dtor, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf110_i2c_port_ctor, + .dtor = _nvkm_i2c_port_dtor, .init = nv50_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .fini = _nvkm_i2c_port_fini, }, }, { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv94_aux_port_ctor, - .dtor = _nouveau_i2c_port_dtor, - .init = _nouveau_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g94_aux_port_ctor, + .dtor = _nvkm_i2c_port_dtor, + .init = _nvkm_i2c_port_init, + .fini = _nvkm_i2c_port_fini, }, }, {} }; -struct nouveau_oclass * -nvd0_i2c_oclass = &(struct nouveau_i2c_impl) { +struct nvkm_oclass * +gf110_i2c_oclass = &(struct nvkm_i2c_impl) { .base.handle = NV_SUBDEV(I2C, 0xd0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_i2c_ctor, - .dtor = _nouveau_i2c_dtor, - .init = _nouveau_i2c_init, - .fini = _nouveau_i2c_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_i2c_ctor, + .dtor = _nvkm_i2c_dtor, + .init = _nvkm_i2c_init, + .fini = _nvkm_i2c_fini, }, - .sclass = nvd0_i2c_sclass, + .sclass = gf110_i2c_sclass, .pad_x = &nv04_i2c_pad_oclass, - .pad_s = &nv94_i2c_pad_oclass, + .pad_s = &g94_i2c_pad_oclass, .aux = 4, - .aux_stat = nv94_aux_stat, - .aux_mask = nv94_aux_mask, + .aux_stat = g94_aux_stat, + .aux_mask = g94_aux_mask, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c index fa891c39866b..e290b40f2d13 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nouveau_oclass * -gf117_i2c_oclass = &(struct nouveau_i2c_impl) { +struct nvkm_oclass * +gf117_i2c_oclass = &(struct nvkm_i2c_impl) { .base.handle = NV_SUBDEV(I2C, 0xd7), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_i2c_ctor, - .dtor = _nouveau_i2c_dtor, - .init = _nouveau_i2c_init, - .fini = _nouveau_i2c_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_i2c_ctor, + .dtor = _nvkm_i2c_dtor, + .init = _nvkm_i2c_init, + .fini = _nvkm_i2c_fini, }, - .sclass = nvd0_i2c_sclass, + .sclass = gf110_i2c_sclass, .pad_x = &nv04_i2c_pad_oclass, .pad_s = &nv04_i2c_pad_oclass, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c index 25fe5c2d110e..1a464903a992 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c @@ -21,11 +21,10 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" void -nve0_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) +gk104_aux_stat(struct nvkm_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) { u32 intr = nv_rd32(i2c, 0x00dc60); u32 stat = nv_rd32(i2c, 0x00dc68) & intr, i; @@ -39,7 +38,7 @@ nve0_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) } void -nve0_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data) +gk104_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data) { u32 temp = nv_rd32(i2c, 0x00dc68), i; for (i = 0; i < 8; i++) { @@ -54,19 +53,19 @@ nve0_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data) nv_wr32(i2c, 0x00dc68, temp); } -struct nouveau_oclass * -nve0_i2c_oclass = &(struct nouveau_i2c_impl) { +struct nvkm_oclass * +gk104_i2c_oclass = &(struct nvkm_i2c_impl) { .base.handle = NV_SUBDEV(I2C, 0xe0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_i2c_ctor, - .dtor = _nouveau_i2c_dtor, - .init = _nouveau_i2c_init, - .fini = _nouveau_i2c_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_i2c_ctor, + .dtor = _nvkm_i2c_dtor, + .init = _nvkm_i2c_init, + .fini = _nvkm_i2c_fini, }, - .sclass = nvd0_i2c_sclass, + .sclass = gf110_i2c_sclass, .pad_x = &nv04_i2c_pad_oclass, - .pad_s = &nv94_i2c_pad_oclass, + .pad_s = &g94_i2c_pad_oclass, .aux = 4, - .aux_stat = nve0_aux_stat, - .aux_mask = nve0_aux_mask, + .aux_stat = gk104_aux_stat, + .aux_mask = gk104_aux_mask, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c index 06a2b87ccbf1..ab64237b3842 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" #define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args) #define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args) static void -auxch_fini(struct nouveau_i2c *aux, int ch) +auxch_fini(struct nvkm_i2c *aux, int ch) { nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00310000, 0x00000000); } static int -auxch_init(struct nouveau_i2c *aux, int ch) +auxch_init(struct nvkm_i2c *aux, int ch) { const u32 unksel = 1; /* nfi which to use, or if it matters.. */ const u32 ureq = unksel ? 0x00100000 : 0x00200000; @@ -69,10 +68,10 @@ auxch_init(struct nouveau_i2c *aux, int ch) } int -gm204_aux(struct nouveau_i2c_port *base, bool retry, +gm204_aux(struct nvkm_i2c_port *base, bool retry, u8 type, u32 addr, u8 *data, u8 size) { - struct nouveau_i2c *aux = nouveau_i2c(base); + struct nvkm_i2c *aux = nvkm_i2c(base); struct nv50_i2c_port *port = (void *)base; u32 ctrl, stat, timeout, retries; u32 xbuf[4] = {}; @@ -155,24 +154,23 @@ out: return ret < 0 ? ret : (stat & 0x000f0000) >> 16; } -static const struct nouveau_i2c_func +static const struct nvkm_i2c_func gm204_aux_func = { .aux = gm204_aux, }; int -gm204_aux_port_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +gm204_aux_port_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { struct dcb_i2c_entry *info = data; struct nv50_i2c_port *port; int ret; - ret = nouveau_i2c_port_create(parent, engine, oclass, index, - &nouveau_i2c_aux_algo, &gm204_aux_func, - &port); + ret = nvkm_i2c_port_create(parent, engine, oclass, index, + &nvkm_i2c_aux_algo, &gm204_aux_func, &port); *pobject = nv_object(port); if (ret) return ret; @@ -182,40 +180,40 @@ gm204_aux_port_ctor(struct nouveau_object *parent, return 0; } -struct nouveau_oclass +struct nvkm_oclass gm204_i2c_sclass[] = { { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvd0_i2c_port_ctor, - .dtor = _nouveau_i2c_port_dtor, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf110_i2c_port_ctor, + .dtor = _nvkm_i2c_port_dtor, .init = nv50_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .fini = _nvkm_i2c_port_fini, }, }, { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm204_aux_port_ctor, - .dtor = _nouveau_i2c_port_dtor, - .init = _nouveau_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .dtor = _nvkm_i2c_port_dtor, + .init = _nvkm_i2c_port_init, + .fini = _nvkm_i2c_port_fini, }, }, {} }; -struct nouveau_oclass * -gm204_i2c_oclass = &(struct nouveau_i2c_impl) { +struct nvkm_oclass * +gm204_i2c_oclass = &(struct nvkm_i2c_impl) { .base.handle = NV_SUBDEV(I2C, 0x24), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_i2c_ctor, - .dtor = _nouveau_i2c_dtor, - .init = _nouveau_i2c_init, - .fini = _nouveau_i2c_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_i2c_ctor, + .dtor = _nvkm_i2c_dtor, + .init = _nvkm_i2c_init, + .fini = _nvkm_i2c_fini, }, .sclass = gm204_i2c_sclass, .pad_x = &nv04_i2c_pad_oclass, .pad_s = &gm204_i2c_pad_oclass, .aux = 8, - .aux_stat = nve0_aux_stat, - .aux_mask = nve0_aux_mask, + .aux_stat = gk104_aux_stat, + .aux_mask = gk104_aux_mask, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c index b1725bdea967..4cdf1c489353 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c @@ -21,25 +21,24 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/vga.h> -#include "priv.h" - struct nv04_i2c_priv { - struct nouveau_i2c base; + struct nvkm_i2c base; }; struct nv04_i2c_port { - struct nouveau_i2c_port base; + struct nvkm_i2c_port base; u8 drive; u8 sense; }; static void -nv04_i2c_drive_scl(struct nouveau_i2c_port *base, int state) +nv04_i2c_drive_scl(struct nvkm_i2c_port *base, int state) { - struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv04_i2c_port *port = (void *)base; u8 val = nv_rdvgac(priv, 0, port->drive); if (state) val |= 0x20; @@ -48,9 +47,9 @@ nv04_i2c_drive_scl(struct nouveau_i2c_port *base, int state) } static void -nv04_i2c_drive_sda(struct nouveau_i2c_port *base, int state) +nv04_i2c_drive_sda(struct nvkm_i2c_port *base, int state) { - struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv04_i2c_port *port = (void *)base; u8 val = nv_rdvgac(priv, 0, port->drive); if (state) val |= 0x10; @@ -59,22 +58,22 @@ nv04_i2c_drive_sda(struct nouveau_i2c_port *base, int state) } static int -nv04_i2c_sense_scl(struct nouveau_i2c_port *base) +nv04_i2c_sense_scl(struct nvkm_i2c_port *base) { - struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv04_i2c_port *port = (void *)base; return !!(nv_rdvgac(priv, 0, port->sense) & 0x04); } static int -nv04_i2c_sense_sda(struct nouveau_i2c_port *base) +nv04_i2c_sense_sda(struct nvkm_i2c_port *base) { - struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv04_i2c_port *port = (void *)base; return !!(nv_rdvgac(priv, 0, port->sense) & 0x08); } -static const struct nouveau_i2c_func +static const struct nvkm_i2c_func nv04_i2c_func = { .drive_scl = nv04_i2c_drive_scl, .drive_sda = nv04_i2c_drive_sda, @@ -83,17 +82,16 @@ nv04_i2c_func = { }; static int -nv04_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +nv04_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { struct dcb_i2c_entry *info = data; struct nv04_i2c_port *port; int ret; - ret = nouveau_i2c_port_create(parent, engine, oclass, index, - &nouveau_i2c_bit_algo, &nv04_i2c_func, - &port); + ret = nvkm_i2c_port_create(parent, engine, oclass, index, + &nvkm_i2c_bit_algo, &nv04_i2c_func, &port); *pobject = nv_object(port); if (ret) return ret; @@ -103,27 +101,27 @@ nv04_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -static struct nouveau_oclass +static struct nvkm_oclass nv04_i2c_sclass[] = { { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NV04_BIT), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_i2c_port_ctor, - .dtor = _nouveau_i2c_port_dtor, - .init = _nouveau_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .dtor = _nvkm_i2c_port_dtor, + .init = _nvkm_i2c_port_init, + .fini = _nvkm_i2c_port_fini, }, }, {} }; -struct nouveau_oclass * -nv04_i2c_oclass = &(struct nouveau_i2c_impl) { +struct nvkm_oclass * +nv04_i2c_oclass = &(struct nvkm_i2c_impl) { .base.handle = NV_SUBDEV(I2C, 0x04), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_i2c_ctor, - .dtor = _nouveau_i2c_dtor, - .init = _nouveau_i2c_init, - .fini = _nouveau_i2c_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_i2c_ctor, + .dtor = _nvkm_i2c_dtor, + .init = _nvkm_i2c_init, + .fini = _nvkm_i2c_fini, }, .sclass = nv04_i2c_sclass, .pad_x = &nv04_i2c_pad_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c index f16c87ce5ba1..046fe5e2ea19 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c @@ -21,53 +21,52 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/vga.h> -#include "priv.h" - struct nv4e_i2c_priv { - struct nouveau_i2c base; + struct nvkm_i2c base; }; struct nv4e_i2c_port { - struct nouveau_i2c_port base; + struct nvkm_i2c_port base; u32 addr; }; static void -nv4e_i2c_drive_scl(struct nouveau_i2c_port *base, int state) +nv4e_i2c_drive_scl(struct nvkm_i2c_port *base, int state) { - struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv4e_i2c_port *port = (void *)base; nv_mask(priv, port->addr, 0x2f, state ? 0x21 : 0x01); } static void -nv4e_i2c_drive_sda(struct nouveau_i2c_port *base, int state) +nv4e_i2c_drive_sda(struct nvkm_i2c_port *base, int state) { - struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv4e_i2c_port *port = (void *)base; nv_mask(priv, port->addr, 0x1f, state ? 0x11 : 0x01); } static int -nv4e_i2c_sense_scl(struct nouveau_i2c_port *base) +nv4e_i2c_sense_scl(struct nvkm_i2c_port *base) { - struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv4e_i2c_port *port = (void *)base; return !!(nv_rd32(priv, port->addr) & 0x00040000); } static int -nv4e_i2c_sense_sda(struct nouveau_i2c_port *base) +nv4e_i2c_sense_sda(struct nvkm_i2c_port *base) { - struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv4e_i2c_port *port = (void *)base; return !!(nv_rd32(priv, port->addr) & 0x00080000); } -static const struct nouveau_i2c_func +static const struct nvkm_i2c_func nv4e_i2c_func = { .drive_scl = nv4e_i2c_drive_scl, .drive_sda = nv4e_i2c_drive_sda, @@ -76,17 +75,16 @@ nv4e_i2c_func = { }; static int -nv4e_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +nv4e_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { struct dcb_i2c_entry *info = data; struct nv4e_i2c_port *port; int ret; - ret = nouveau_i2c_port_create(parent, engine, oclass, index, - &nouveau_i2c_bit_algo, &nv4e_i2c_func, - &port); + ret = nvkm_i2c_port_create(parent, engine, oclass, index, + &nvkm_i2c_bit_algo, &nv4e_i2c_func, &port); *pobject = nv_object(port); if (ret) return ret; @@ -95,27 +93,27 @@ nv4e_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -static struct nouveau_oclass +static struct nvkm_oclass nv4e_i2c_sclass[] = { { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NV4E_BIT), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv4e_i2c_port_ctor, - .dtor = _nouveau_i2c_port_dtor, - .init = _nouveau_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .dtor = _nvkm_i2c_port_dtor, + .init = _nvkm_i2c_port_init, + .fini = _nvkm_i2c_port_fini, }, }, {} }; -struct nouveau_oclass * -nv4e_i2c_oclass = &(struct nouveau_i2c_impl) { +struct nvkm_oclass * +nv4e_i2c_oclass = &(struct nvkm_i2c_impl) { .base.handle = NV_SUBDEV(I2C, 0x4e), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_i2c_ctor, - .dtor = _nouveau_i2c_dtor, - .init = _nouveau_i2c_init, - .fini = _nouveau_i2c_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_i2c_ctor, + .dtor = _nvkm_i2c_dtor, + .init = _nvkm_i2c_init, + .fini = _nvkm_i2c_fini, }, .sclass = nv4e_i2c_sclass, .pad_x = &nv04_i2c_pad_oclass, diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c index 7b8756d4df08..fba5b26a5682 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" void -nv50_i2c_drive_scl(struct nouveau_i2c_port *base, int state) +nv50_i2c_drive_scl(struct nvkm_i2c_port *base, int state) { - struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv50_i2c_port *port = (void *)base; if (state) port->state |= 0x01; else port->state &= 0xfe; @@ -35,9 +34,9 @@ nv50_i2c_drive_scl(struct nouveau_i2c_port *base, int state) } void -nv50_i2c_drive_sda(struct nouveau_i2c_port *base, int state) +nv50_i2c_drive_sda(struct nvkm_i2c_port *base, int state) { - struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv50_i2c_port *port = (void *)base; if (state) port->state |= 0x02; else port->state &= 0xfd; @@ -45,22 +44,22 @@ nv50_i2c_drive_sda(struct nouveau_i2c_port *base, int state) } int -nv50_i2c_sense_scl(struct nouveau_i2c_port *base) +nv50_i2c_sense_scl(struct nvkm_i2c_port *base) { - struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv50_i2c_port *port = (void *)base; return !!(nv_rd32(priv, port->addr) & 0x00000001); } int -nv50_i2c_sense_sda(struct nouveau_i2c_port *base) +nv50_i2c_sense_sda(struct nvkm_i2c_port *base) { - struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; + struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base); struct nv50_i2c_port *port = (void *)base; return !!(nv_rd32(priv, port->addr) & 0x00000002); } -static const struct nouveau_i2c_func +static const struct nvkm_i2c_func nv50_i2c_func = { .drive_scl = nv50_i2c_drive_scl, .drive_sda = nv50_i2c_drive_sda, @@ -76,17 +75,16 @@ const u32 nv50_i2c_addr[] = { const int nv50_i2c_addr_nr = ARRAY_SIZE(nv50_i2c_addr); static int -nv50_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +nv50_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { struct dcb_i2c_entry *info = data; struct nv50_i2c_port *port; int ret; - ret = nouveau_i2c_port_create(parent, engine, oclass, index, - &nouveau_i2c_bit_algo, &nv50_i2c_func, - &port); + ret = nvkm_i2c_port_create(parent, engine, oclass, index, + &nvkm_i2c_bit_algo, &nv50_i2c_func, &port); *pobject = nv_object(port); if (ret) return ret; @@ -100,35 +98,35 @@ nv50_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } int -nv50_i2c_port_init(struct nouveau_object *object) +nv50_i2c_port_init(struct nvkm_object *object) { - struct nv50_i2c_priv *priv = (void *)object->engine; + struct nv50_i2c_priv *priv = (void *)nvkm_i2c(object); struct nv50_i2c_port *port = (void *)object; nv_wr32(priv, port->addr, port->state); - return nouveau_i2c_port_init(&port->base); + return nvkm_i2c_port_init(&port->base); } -static struct nouveau_oclass +static struct nvkm_oclass nv50_i2c_sclass[] = { { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_i2c_port_ctor, - .dtor = _nouveau_i2c_port_dtor, + .dtor = _nvkm_i2c_port_dtor, .init = nv50_i2c_port_init, - .fini = _nouveau_i2c_port_fini, + .fini = _nvkm_i2c_port_fini, }, }, {} }; -struct nouveau_oclass * -nv50_i2c_oclass = &(struct nouveau_i2c_impl) { +struct nvkm_oclass * +nv50_i2c_oclass = &(struct nvkm_i2c_impl) { .base.handle = NV_SUBDEV(I2C, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_i2c_ctor, - .dtor = _nouveau_i2c_dtor, - .init = _nouveau_i2c_init, - .fini = _nouveau_i2c_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_i2c_ctor, + .dtor = _nvkm_i2c_dtor, + .init = _nvkm_i2c_init, + .fini = _nvkm_i2c_fini, }, .sclass = nv50_i2c_sclass, .pad_x = &nv04_i2c_pad_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h new file mode 100644 index 000000000000..b3139e721b02 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h @@ -0,0 +1,32 @@ +#ifndef __NV50_I2C_H__ +#define __NV50_I2C_H__ +#include "priv.h" + +struct nv50_i2c_priv { + struct nvkm_i2c base; +}; + +struct nv50_i2c_port { + struct nvkm_i2c_port base; + u32 addr; + u32 state; +}; + +extern const u32 nv50_i2c_addr[]; +extern const int nv50_i2c_addr_nr; +int nv50_i2c_port_init(struct nvkm_object *); +int nv50_i2c_sense_scl(struct nvkm_i2c_port *); +int nv50_i2c_sense_sda(struct nvkm_i2c_port *); +void nv50_i2c_drive_scl(struct nvkm_i2c_port *, int state); +void nv50_i2c_drive_sda(struct nvkm_i2c_port *, int state); + +int g94_aux_port_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void g94_i2c_acquire(struct nvkm_i2c_port *); +void g94_i2c_release(struct nvkm_i2c_port *); + +int gf110_i2c_port_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c index e9e412477c12..a242eeb67829 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c @@ -21,35 +21,34 @@ * * Authors: Ben Skeggs */ - #include "pad.h" int -_nvkm_i2c_pad_fini(struct nouveau_object *object, bool suspend) +_nvkm_i2c_pad_fini(struct nvkm_object *object, bool suspend) { struct nvkm_i2c_pad *pad = (void *)object; DBG("-> NULL\n"); pad->port = NULL; - return nouveau_object_fini(&pad->base, suspend); + return nvkm_object_fini(&pad->base, suspend); } int -_nvkm_i2c_pad_init(struct nouveau_object *object) +_nvkm_i2c_pad_init(struct nvkm_object *object) { struct nvkm_i2c_pad *pad = (void *)object; DBG("-> PORT:%02x\n", pad->next->index); pad->port = pad->next; - return nouveau_object_init(&pad->base); + return nvkm_object_init(&pad->base); } int -nvkm_i2c_pad_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int index, +nvkm_i2c_pad_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, int index, int size, void **pobject) { - struct nouveau_i2c *i2c = (void *)engine; - struct nouveau_i2c_port *port; + struct nvkm_i2c *i2c = nvkm_i2c(parent); + struct nvkm_i2c_port *port; struct nvkm_i2c_pad *pad; int ret; @@ -62,7 +61,7 @@ nvkm_i2c_pad_create_(struct nouveau_object *parent, } } - ret = nouveau_object_create_(parent, engine, oclass, 0, size, pobject); + ret = nvkm_object_create_(parent, engine, oclass, 0, size, pobject); pad = *pobject; if (ret) return ret; @@ -72,9 +71,9 @@ nvkm_i2c_pad_create_(struct nouveau_object *parent, } int -_nvkm_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +_nvkm_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { struct nvkm_i2c_pad *pad; int ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h index 452ac10c3004..f3422cc6f8db 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h @@ -1,20 +1,19 @@ #ifndef __NVKM_I2C_PAD_H__ #define __NVKM_I2C_PAD_H__ - #include "priv.h" struct nvkm_i2c_pad { - struct nouveau_object base; + struct nvkm_object base; int index; - struct nouveau_i2c_port *port; - struct nouveau_i2c_port *next; + struct nvkm_i2c_port *port; + struct nvkm_i2c_port *next; }; static inline struct nvkm_i2c_pad * -nvkm_i2c_pad(struct nouveau_i2c_port *port) +nvkm_i2c_pad(struct nvkm_i2c_port *port) { - struct nouveau_object *pad = nv_object(port); - while (pad->parent) + struct nvkm_object *pad = nv_object(port); + while (!nv_iclass(pad->parent, NV_SUBDEV_CLASS)) pad = pad->parent; return (void *)pad; } @@ -34,25 +33,24 @@ nvkm_i2c_pad(struct nouveau_i2c_port *port) _nvkm_i2c_pad_fini(nv_object(_p), (s)); \ }) -int nvkm_i2c_pad_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int index, int, void **); +int nvkm_i2c_pad_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int index, int, void **); -int _nvkm_i2c_pad_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -#define _nvkm_i2c_pad_dtor nouveau_object_destroy -int _nvkm_i2c_pad_init(struct nouveau_object *); -int _nvkm_i2c_pad_fini(struct nouveau_object *, bool); +int _nvkm_i2c_pad_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +#define _nvkm_i2c_pad_dtor nvkm_object_destroy +int _nvkm_i2c_pad_init(struct nvkm_object *); +int _nvkm_i2c_pad_fini(struct nvkm_object *, bool); #ifndef MSG #define MSG(l,f,a...) do { \ struct nvkm_i2c_pad *_pad = (void *)pad; \ - nv_##l(nv_object(_pad)->engine, "PAD:%c:%02x: "f, \ + nv_##l(_pad, "PAD:%c:%02x: "f, \ _pad->index >= 0x100 ? 'X' : 'S', \ _pad->index >= 0x100 ? _pad->index - 0x100 : _pad->index, ##a); \ } while(0) #define DBG(f,a...) MSG(debug, f, ##a) #define ERR(f,a...) MSG(error, f, ##a) #endif - #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c index 0dc6753014f0..e9832f7a7e38 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c @@ -21,28 +21,27 @@ * * Authors: Ben Skeggs */ - #include "pad.h" -struct nv94_i2c_pad { +struct g94_i2c_pad { struct nvkm_i2c_pad base; int addr; }; static int -nv94_i2c_pad_fini(struct nouveau_object *object, bool suspend) +g94_i2c_pad_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_i2c *i2c = (void *)object->engine; - struct nv94_i2c_pad *pad = (void *)object; + struct nvkm_i2c *i2c = (void *)nvkm_i2c(object); + struct g94_i2c_pad *pad = (void *)object; nv_mask(i2c, 0x00e50c + pad->addr, 0x00000001, 0x00000001); return nvkm_i2c_pad_fini(&pad->base, suspend); } static int -nv94_i2c_pad_init(struct nouveau_object *object) +g94_i2c_pad_init(struct nvkm_object *object) { - struct nouveau_i2c *i2c = (void *)object->engine; - struct nv94_i2c_pad *pad = (void *)object; + struct nvkm_i2c *i2c = (void *)nvkm_i2c(object); + struct g94_i2c_pad *pad = (void *)object; switch (nv_oclass(pad->base.next)->handle) { case NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX): @@ -59,11 +58,11 @@ nv94_i2c_pad_init(struct nouveau_object *object) } static int -nv94_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +g94_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { - struct nv94_i2c_pad *pad; + struct g94_i2c_pad *pad; int ret; ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); @@ -75,12 +74,12 @@ nv94_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass -nv94_i2c_pad_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv94_i2c_pad_ctor, +struct nvkm_oclass +g94_i2c_pad_oclass = { + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g94_i2c_pad_ctor, .dtor = _nvkm_i2c_pad_dtor, - .init = nv94_i2c_pad_init, - .fini = nv94_i2c_pad_fini, + .init = g94_i2c_pad_init, + .fini = g94_i2c_pad_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm204.c index f0e6fbbaa8cd..be590405444d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm204.c @@ -21,7 +21,6 @@ * * Authors: Ben Skeggs */ - #include "pad.h" struct gm204_i2c_pad { @@ -30,18 +29,18 @@ struct gm204_i2c_pad { }; static int -gm204_i2c_pad_fini(struct nouveau_object *object, bool suspend) +gm204_i2c_pad_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_i2c *i2c = (void *)object->engine; + struct nvkm_i2c *i2c = (void *)nvkm_i2c(object); struct gm204_i2c_pad *pad = (void *)object; nv_mask(i2c, 0x00d97c + pad->addr, 0x00000001, 0x00000001); return nvkm_i2c_pad_fini(&pad->base, suspend); } static int -gm204_i2c_pad_init(struct nouveau_object *object) +gm204_i2c_pad_init(struct nvkm_object *object) { - struct nouveau_i2c *i2c = (void *)object->engine; + struct nvkm_i2c *i2c = (void *)nvkm_i2c(object); struct gm204_i2c_pad *pad = (void *)object; switch (nv_oclass(pad->base.next)->handle) { @@ -59,9 +58,9 @@ gm204_i2c_pad_init(struct nouveau_object *object) } static int -gm204_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 index, - struct nouveau_object **pobject) +gm204_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 index, + struct nvkm_object **pobject) { struct gm204_i2c_pad *pad; int ret; @@ -75,9 +74,9 @@ gm204_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass gm204_i2c_pad_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm204_i2c_pad_ctor, .dtor = _nvkm_i2c_pad_dtor, .init = gm204_i2c_pad_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c index 2c4b61296dd1..22c7daaad3a0 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c @@ -21,12 +21,11 @@ * * Authors: Ben Skeggs */ - #include "pad.h" -struct nouveau_oclass +struct nvkm_oclass nv04_i2c_pad_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = _nvkm_i2c_pad_ctor, .dtor = _nvkm_i2c_pad_dtor, .init = _nvkm_i2c_pad_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/port.h index a8ff6e077af5..586f53dad813 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/port.h @@ -1,15 +1,13 @@ #ifndef __NVKM_I2C_PORT_H__ #define __NVKM_I2C_PORT_H__ - #include "priv.h" #ifndef MSG #define MSG(l,f,a...) do { \ - struct nouveau_i2c_port *_port = (void *)port; \ - nv_##l(nv_object(_port)->engine, "PORT:%02x: "f, _port->index, ##a); \ + struct nvkm_i2c_port *_port = (void *)port; \ + nv_##l(_port, "PORT:%02x: "f, _port->index, ##a); \ } while(0) #define DBG(f,a...) MSG(debug, f, ##a) #define ERR(f,a...) MSG(error, f, ##a) #endif - #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h new file mode 100644 index 000000000000..6586e1567fcf --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h @@ -0,0 +1,87 @@ +#ifndef __NVKM_I2C_PRIV_H__ +#define __NVKM_I2C_PRIV_H__ +#include <subdev/i2c.h> + +extern struct nvkm_oclass nv04_i2c_pad_oclass; +extern struct nvkm_oclass g94_i2c_pad_oclass; +extern struct nvkm_oclass gm204_i2c_pad_oclass; + +#define nvkm_i2c_port_create(p,e,o,i,a,f,d) \ + nvkm_i2c_port_create_((p), (e), (o), (i), (a), (f), \ + sizeof(**d), (void **)d) +#define nvkm_i2c_port_destroy(p) ({ \ + struct nvkm_i2c_port *port = (p); \ + _nvkm_i2c_port_dtor(nv_object(i2c)); \ +}) +#define nvkm_i2c_port_init(p) \ + nvkm_object_init(&(p)->base) +#define nvkm_i2c_port_fini(p,s) \ + nvkm_object_fini(&(p)->base, (s)) + +int nvkm_i2c_port_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, u8, + const struct i2c_algorithm *, + const struct nvkm_i2c_func *, + int, void **); +void _nvkm_i2c_port_dtor(struct nvkm_object *); +#define _nvkm_i2c_port_init nvkm_object_init +int _nvkm_i2c_port_fini(struct nvkm_object *, bool); + +#define nvkm_i2c_create(p,e,o,d) \ + nvkm_i2c_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_i2c_destroy(p) ({ \ + struct nvkm_i2c *i2c = (p); \ + _nvkm_i2c_dtor(nv_object(i2c)); \ +}) +#define nvkm_i2c_init(p) ({ \ + struct nvkm_i2c *i2c = (p); \ + _nvkm_i2c_init(nv_object(i2c)); \ +}) +#define nvkm_i2c_fini(p,s) ({ \ + struct nvkm_i2c *i2c = (p); \ + _nvkm_i2c_fini(nv_object(i2c), (s)); \ +}) + +int nvkm_i2c_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +int _nvkm_i2c_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void _nvkm_i2c_dtor(struct nvkm_object *); +int _nvkm_i2c_init(struct nvkm_object *); +int _nvkm_i2c_fini(struct nvkm_object *, bool); + +extern struct nvkm_oclass nvkm_anx9805_sclass[]; +extern struct nvkm_oclass gf110_i2c_sclass[]; + +extern const struct i2c_algorithm nvkm_i2c_bit_algo; +extern const struct i2c_algorithm nvkm_i2c_aux_algo; + +struct nvkm_i2c_impl { + struct nvkm_oclass base; + + /* supported i2c port classes */ + struct nvkm_oclass *sclass; + struct nvkm_oclass *pad_x; + struct nvkm_oclass *pad_s; + + /* number of native dp aux channels present */ + int aux; + + /* read and ack pending interrupts, returning only data + * for ports that have not been masked off, while still + * performing the ack for anything that was pending. + */ + void (*aux_stat)(struct nvkm_i2c *, u32 *, u32 *, u32 *, u32 *); + + /* mask on/off interrupt types for a given set of auxch + */ + void (*aux_mask)(struct nvkm_i2c *, u32, u32, u32); +}; + +void g94_aux_stat(struct nvkm_i2c *, u32 *, u32 *, u32 *, u32 *); +void g94_aux_mask(struct nvkm_i2c *, u32, u32, u32); + +void gk104_aux_stat(struct nvkm_i2c *, u32 *, u32 *, u32 *, u32 *); +void gk104_aux_mask(struct nvkm_i2c *, u32, u32, u32); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild new file mode 100644 index 000000000000..a0b12d27284a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild @@ -0,0 +1,3 @@ +nvkm-y += nvkm/subdev/ibus/gf100.o +nvkm-y += nvkm/subdev/ibus/gk104.o +nvkm-y += nvkm/subdev/ibus/gk20a.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c index 4e977ff27e44..8e578f802f66 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c @@ -21,15 +21,14 @@ * * Authors: Ben Skeggs */ - #include <subdev/ibus.h> -struct nvc0_ibus_priv { - struct nouveau_ibus base; +struct gf100_ibus_priv { + struct nvkm_ibus base; }; static void -nvc0_ibus_intr_hub(struct nvc0_ibus_priv *priv, int i) +gf100_ibus_intr_hub(struct gf100_ibus_priv *priv, int i) { u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0400)); u32 data = nv_rd32(priv, 0x122124 + (i * 0x0400)); @@ -39,7 +38,7 @@ nvc0_ibus_intr_hub(struct nvc0_ibus_priv *priv, int i) } static void -nvc0_ibus_intr_rop(struct nvc0_ibus_priv *priv, int i) +gf100_ibus_intr_rop(struct gf100_ibus_priv *priv, int i) { u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0400)); u32 data = nv_rd32(priv, 0x124124 + (i * 0x0400)); @@ -49,7 +48,7 @@ nvc0_ibus_intr_rop(struct nvc0_ibus_priv *priv, int i) } static void -nvc0_ibus_intr_gpc(struct nvc0_ibus_priv *priv, int i) +gf100_ibus_intr_gpc(struct gf100_ibus_priv *priv, int i) { u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0400)); u32 data = nv_rd32(priv, 0x128124 + (i * 0x0400)); @@ -59,9 +58,9 @@ nvc0_ibus_intr_gpc(struct nvc0_ibus_priv *priv, int i) } static void -nvc0_ibus_intr(struct nouveau_subdev *subdev) +gf100_ibus_intr(struct nvkm_subdev *subdev) { - struct nvc0_ibus_priv *priv = (void *)subdev; + struct gf100_ibus_priv *priv = (void *)subdev; u32 intr0 = nv_rd32(priv, 0x121c58); u32 intr1 = nv_rd32(priv, 0x121c5c); u32 hubnr = nv_rd32(priv, 0x121c70); @@ -72,7 +71,7 @@ nvc0_ibus_intr(struct nouveau_subdev *subdev) for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { u32 stat = 0x00000100 << i; if (intr0 & stat) { - nvc0_ibus_intr_hub(priv, i); + gf100_ibus_intr_hub(priv, i); intr0 &= ~stat; } } @@ -80,7 +79,7 @@ nvc0_ibus_intr(struct nouveau_subdev *subdev) for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { u32 stat = 0x00010000 << i; if (intr0 & stat) { - nvc0_ibus_intr_rop(priv, i); + gf100_ibus_intr_rop(priv, i); intr0 &= ~stat; } } @@ -88,36 +87,36 @@ nvc0_ibus_intr(struct nouveau_subdev *subdev) for (i = 0; intr1 && i < gpcnr; i++) { u32 stat = 0x00000001 << i; if (intr1 & stat) { - nvc0_ibus_intr_gpc(priv, i); + gf100_ibus_intr_gpc(priv, i); intr1 &= ~stat; } } } static int -nvc0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_ibus_priv *priv; + struct gf100_ibus_priv *priv; int ret; - ret = nouveau_ibus_create(parent, engine, oclass, &priv); + ret = nvkm_ibus_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; - nv_subdev(priv)->intr = nvc0_ibus_intr; + nv_subdev(priv)->intr = gf100_ibus_intr; return 0; } -struct nouveau_oclass -nvc0_ibus_oclass = { +struct nvkm_oclass +gf100_ibus_oclass = { .handle = NV_SUBDEV(IBUS, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_ibus_ctor, - .dtor = _nouveau_ibus_dtor, - .init = _nouveau_ibus_init, - .fini = _nouveau_ibus_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_ibus_ctor, + .dtor = _nvkm_ibus_dtor, + .init = _nvkm_ibus_init, + .fini = _nvkm_ibus_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c index ebef970a0645..7b6e9a6cd7b2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c @@ -21,15 +21,14 @@ * * Authors: Ben Skeggs */ - #include <subdev/ibus.h> -struct nve0_ibus_priv { - struct nouveau_ibus base; +struct gk104_ibus_priv { + struct nvkm_ibus base; }; static void -nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i) +gk104_ibus_intr_hub(struct gk104_ibus_priv *priv, int i) { u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0800)); u32 data = nv_rd32(priv, 0x122124 + (i * 0x0800)); @@ -39,7 +38,7 @@ nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i) } static void -nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i) +gk104_ibus_intr_rop(struct gk104_ibus_priv *priv, int i) { u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0800)); u32 data = nv_rd32(priv, 0x124124 + (i * 0x0800)); @@ -49,7 +48,7 @@ nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i) } static void -nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i) +gk104_ibus_intr_gpc(struct gk104_ibus_priv *priv, int i) { u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0800)); u32 data = nv_rd32(priv, 0x128124 + (i * 0x0800)); @@ -59,9 +58,9 @@ nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i) } static void -nve0_ibus_intr(struct nouveau_subdev *subdev) +gk104_ibus_intr(struct nvkm_subdev *subdev) { - struct nve0_ibus_priv *priv = (void *)subdev; + struct gk104_ibus_priv *priv = (void *)subdev; u32 intr0 = nv_rd32(priv, 0x120058); u32 intr1 = nv_rd32(priv, 0x12005c); u32 hubnr = nv_rd32(priv, 0x120070); @@ -72,7 +71,7 @@ nve0_ibus_intr(struct nouveau_subdev *subdev) for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { u32 stat = 0x00000100 << i; if (intr0 & stat) { - nve0_ibus_intr_hub(priv, i); + gk104_ibus_intr_hub(priv, i); intr0 &= ~stat; } } @@ -80,7 +79,7 @@ nve0_ibus_intr(struct nouveau_subdev *subdev) for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { u32 stat = 0x00010000 << i; if (intr0 & stat) { - nve0_ibus_intr_rop(priv, i); + gk104_ibus_intr_rop(priv, i); intr0 &= ~stat; } } @@ -88,17 +87,17 @@ nve0_ibus_intr(struct nouveau_subdev *subdev) for (i = 0; intr1 && i < gpcnr; i++) { u32 stat = 0x00000001 << i; if (intr1 & stat) { - nve0_ibus_intr_gpc(priv, i); + gk104_ibus_intr_gpc(priv, i); intr1 &= ~stat; } } } static int -nve0_ibus_init(struct nouveau_object *object) +gk104_ibus_init(struct nvkm_object *object) { - struct nve0_ibus_priv *priv = (void *)object; - int ret = nouveau_ibus_init(&priv->base); + struct gk104_ibus_priv *priv = (void *)object; + int ret = nvkm_ibus_init(&priv->base); if (ret == 0) { nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000); nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200); @@ -112,29 +111,29 @@ nve0_ibus_init(struct nouveau_object *object) } static int -nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_ibus_priv *priv; + struct gk104_ibus_priv *priv; int ret; - ret = nouveau_ibus_create(parent, engine, oclass, &priv); + ret = nvkm_ibus_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; - nv_subdev(priv)->intr = nve0_ibus_intr; + nv_subdev(priv)->intr = gk104_ibus_intr; return 0; } -struct nouveau_oclass -nve0_ibus_oclass = { +struct nvkm_oclass +gk104_ibus_oclass = { .handle = NV_SUBDEV(IBUS, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_ibus_ctor, - .dtor = _nouveau_ibus_dtor, - .init = nve0_ibus_init, - .fini = _nouveau_ibus_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_ibus_ctor, + .dtor = _nvkm_ibus_dtor, + .init = gk104_ibus_init, + .fini = _nvkm_ibus_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c index 245f0ebaa6af..c0fdb89e74ac 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c @@ -19,12 +19,11 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - #include <subdev/ibus.h> #include <subdev/timer.h> struct gk20a_ibus_priv { - struct nouveau_ibus base; + struct nvkm_ibus base; }; static void @@ -42,7 +41,7 @@ gk20a_ibus_init_priv_ring(struct gk20a_ibus_priv *priv) } static void -gk20a_ibus_intr(struct nouveau_subdev *subdev) +gk20a_ibus_intr(struct nvkm_subdev *subdev) { struct gk20a_ibus_priv *priv = (void *)subdev; u32 status0 = nv_rd32(priv, 0x120058); @@ -60,12 +59,12 @@ gk20a_ibus_intr(struct nouveau_subdev *subdev) } static int -gk20a_ibus_init(struct nouveau_object *object) +gk20a_ibus_init(struct nvkm_object *object) { struct gk20a_ibus_priv *priv = (void *)object; int ret; - ret = _nouveau_ibus_init(object); + ret = _nvkm_ibus_init(object); if (ret) return ret; @@ -75,14 +74,14 @@ gk20a_ibus_init(struct nouveau_object *object) } static int -gk20a_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk20a_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct gk20a_ibus_priv *priv; int ret; - ret = nouveau_ibus_create(parent, engine, oclass, &priv); + ret = nvkm_ibus_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -91,13 +90,13 @@ gk20a_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass gk20a_ibus_oclass = { .handle = NV_SUBDEV(IBUS, 0xea), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk20a_ibus_ctor, - .dtor = _nouveau_ibus_dtor, + .dtor = _nvkm_ibus_dtor, .init = gk20a_ibus_init, - .fini = _nouveau_ibus_fini, + .fini = _nvkm_ibus_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild new file mode 100644 index 000000000000..e6f35abe7879 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild @@ -0,0 +1,4 @@ +nvkm-y += nvkm/subdev/instmem/base.o +nvkm-y += nvkm/subdev/instmem/nv04.o +nvkm-y += nvkm/subdev/instmem/nv40.o +nvkm-y += nvkm/subdev/instmem/nv50.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c index 14706d9842ca..d16358cc6cbb 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c @@ -21,38 +21,37 @@ * * Authors: Ben Skeggs */ - #include "priv.h" +#include <core/engine.h> + /****************************************************************************** * instmem object base implementation *****************************************************************************/ void -_nouveau_instobj_dtor(struct nouveau_object *object) +_nvkm_instobj_dtor(struct nvkm_object *object) { - struct nouveau_instmem *imem = (void *)object->engine; - struct nouveau_instobj *iobj = (void *)object; + struct nvkm_instmem *imem = nvkm_instmem(object); + struct nvkm_instobj *iobj = (void *)object; mutex_lock(&nv_subdev(imem)->mutex); list_del(&iobj->head); mutex_unlock(&nv_subdev(imem)->mutex); - return nouveau_object_destroy(&iobj->base); + return nvkm_object_destroy(&iobj->base); } int -nouveau_instobj_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int length, void **pobject) +nvkm_instobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_instmem *imem = (void *)engine; - struct nouveau_instobj *iobj; + struct nvkm_instmem *imem = nvkm_instmem(parent); + struct nvkm_instobj *iobj; int ret; - ret = nouveau_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS, - length, pobject); + ret = nvkm_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS, + length, pobject); iobj = *pobject; if (ret) return ret; @@ -68,27 +67,24 @@ nouveau_instobj_create_(struct nouveau_object *parent, *****************************************************************************/ static int -nouveau_instmem_alloc(struct nouveau_instmem *imem, - struct nouveau_object *parent, u32 size, u32 align, - struct nouveau_object **pobject) +nvkm_instmem_alloc(struct nvkm_instmem *imem, struct nvkm_object *parent, + u32 size, u32 align, struct nvkm_object **pobject) { - struct nouveau_object *engine = nv_object(imem); - struct nouveau_instmem_impl *impl = (void *)engine->oclass; - struct nouveau_instobj_args args = { .size = size, .align = align }; - return nouveau_object_ctor(parent, engine, impl->instobj, &args, - sizeof(args), pobject); + struct nvkm_instmem_impl *impl = (void *)imem->base.object.oclass; + struct nvkm_instobj_args args = { .size = size, .align = align }; + return nvkm_object_ctor(parent, &parent->engine->subdev.object, + impl->instobj, &args, sizeof(args), pobject); } int -_nouveau_instmem_fini(struct nouveau_object *object, bool suspend) +_nvkm_instmem_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_instmem *imem = (void *)object; - struct nouveau_instobj *iobj; + struct nvkm_instmem *imem = (void *)object; + struct nvkm_instobj *iobj; int i, ret = 0; if (suspend) { mutex_lock(&imem->base.mutex); - list_for_each_entry(iobj, &imem->list, head) { iobj->suspend = vmalloc(iobj->size); if (!iobj->suspend) { @@ -99,29 +95,26 @@ _nouveau_instmem_fini(struct nouveau_object *object, bool suspend) for (i = 0; i < iobj->size; i += 4) iobj->suspend[i / 4] = nv_ro32(iobj, i); } - mutex_unlock(&imem->base.mutex); - if (ret) return ret; } - return nouveau_subdev_fini(&imem->base, suspend); + return nvkm_subdev_fini(&imem->base, suspend); } int -_nouveau_instmem_init(struct nouveau_object *object) +_nvkm_instmem_init(struct nvkm_object *object) { - struct nouveau_instmem *imem = (void *)object; - struct nouveau_instobj *iobj; + struct nvkm_instmem *imem = (void *)object; + struct nvkm_instobj *iobj; int ret, i; - ret = nouveau_subdev_init(&imem->base); + ret = nvkm_subdev_init(&imem->base); if (ret) return ret; mutex_lock(&imem->base.mutex); - list_for_each_entry(iobj, &imem->list, head) { if (iobj->suspend) { for (i = 0; i < iobj->size; i += 4) @@ -130,28 +123,24 @@ _nouveau_instmem_init(struct nouveau_object *object) iobj->suspend = NULL; } } - mutex_unlock(&imem->base.mutex); - return 0; } int -nouveau_instmem_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int length, void **pobject) +nvkm_instmem_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_instmem *imem; + struct nvkm_instmem *imem; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, - "INSTMEM", "instmem", length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "INSTMEM", + "instmem", length, pobject); imem = *pobject; if (ret) return ret; INIT_LIST_HEAD(&imem->list); - imem->alloc = nouveau_instmem_alloc; + imem->alloc = nvkm_instmem_alloc; return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c index e8b1401c59c0..80614f1b2074 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c @@ -21,56 +21,59 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" +#include <core/ramht.h> + /****************************************************************************** * instmem object implementation *****************************************************************************/ static u32 -nv04_instobj_rd32(struct nouveau_object *object, u64 addr) +nv04_instobj_rd32(struct nvkm_object *object, u64 addr) { + struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object); struct nv04_instobj_priv *node = (void *)object; - return nv_ro32(object->engine, node->mem->offset + addr); + return nv_ro32(priv, node->mem->offset + addr); } static void -nv04_instobj_wr32(struct nouveau_object *object, u64 addr, u32 data) +nv04_instobj_wr32(struct nvkm_object *object, u64 addr, u32 data) { + struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object); struct nv04_instobj_priv *node = (void *)object; - nv_wo32(object->engine, node->mem->offset + addr, data); + nv_wo32(priv, node->mem->offset + addr, data); } static void -nv04_instobj_dtor(struct nouveau_object *object) +nv04_instobj_dtor(struct nvkm_object *object) { - struct nv04_instmem_priv *priv = (void *)object->engine; + struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object); struct nv04_instobj_priv *node = (void *)object; - nouveau_mm_free(&priv->heap, &node->mem); - nouveau_instobj_destroy(&node->base); + nvkm_mm_free(&priv->heap, &node->mem); + nvkm_instobj_destroy(&node->base); } static int -nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv04_instmem_priv *priv = (void *)engine; + struct nv04_instmem_priv *priv = (void *)nvkm_instmem(parent); struct nv04_instobj_priv *node; - struct nouveau_instobj_args *args = data; + struct nvkm_instobj_args *args = data; int ret; if (!args->align) args->align = 1; - ret = nouveau_instobj_create(parent, engine, oclass, &node); + ret = nvkm_instobj_create(parent, engine, oclass, &node); *pobject = nv_object(node); if (ret) return ret; - ret = nouveau_mm_head(&priv->heap, 0, 1, args->size, args->size, - args->align, &node->mem); + ret = nvkm_mm_head(&priv->heap, 0, 1, args->size, args->size, + args->align, &node->mem); if (ret) return ret; @@ -79,13 +82,13 @@ nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_instobj_impl +struct nvkm_instobj_impl nv04_instobj_oclass = { - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_instobj_ctor, .dtor = nv04_instobj_dtor, - .init = _nouveau_instobj_init, - .fini = _nouveau_instobj_fini, + .init = _nvkm_instobj_init, + .fini = _nvkm_instobj_fini, .rd32 = nv04_instobj_rd32, .wr32 = nv04_instobj_wr32, }, @@ -96,40 +99,40 @@ nv04_instobj_oclass = { *****************************************************************************/ static u32 -nv04_instmem_rd32(struct nouveau_object *object, u64 addr) +nv04_instmem_rd32(struct nvkm_object *object, u64 addr) { return nv_rd32(object, 0x700000 + addr); } static void -nv04_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) +nv04_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data) { return nv_wr32(object, 0x700000 + addr, data); } void -nv04_instmem_dtor(struct nouveau_object *object) +nv04_instmem_dtor(struct nvkm_object *object) { struct nv04_instmem_priv *priv = (void *)object; - nouveau_gpuobj_ref(NULL, &priv->ramfc); - nouveau_gpuobj_ref(NULL, &priv->ramro); - nouveau_ramht_ref(NULL, &priv->ramht); - nouveau_gpuobj_ref(NULL, &priv->vbios); - nouveau_mm_fini(&priv->heap); + nvkm_gpuobj_ref(NULL, &priv->ramfc); + nvkm_gpuobj_ref(NULL, &priv->ramro); + nvkm_ramht_ref(NULL, &priv->ramht); + nvkm_gpuobj_ref(NULL, &priv->vbios); + nvkm_mm_fini(&priv->heap); if (priv->iomem) iounmap(priv->iomem); - nouveau_instmem_destroy(&priv->base); + nvkm_instmem_destroy(&priv->base); } static int -nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_instmem_priv *priv; int ret; - ret = nouveau_instmem_create(parent, engine, oclass, &priv); + ret = nvkm_instmem_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -137,44 +140,44 @@ nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, /* PRAMIN aperture maps over the end of VRAM, reserve it */ priv->base.reserved = 512 * 1024; - ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); + ret = nvkm_mm_init(&priv->heap, 0, priv->base.reserved, 1); if (ret) return ret; /* 0x00000-0x10000: reserve for probable vbios image */ - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0, - &priv->vbios); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0, + &priv->vbios); if (ret) return ret; /* 0x10000-0x18000: reserve for RAMHT */ - ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht); + ret = nvkm_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht); if (ret) return ret; /* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */ - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00800, 0, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00800, 0, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); if (ret) return ret; /* 0x18800-0x18a00: reserve for RAMRO */ - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0, - &priv->ramro); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0, + &priv->ramro); if (ret) return ret; return 0; } -struct nouveau_oclass * -nv04_instmem_oclass = &(struct nouveau_instmem_impl) { +struct nvkm_oclass * +nv04_instmem_oclass = &(struct nvkm_instmem_impl) { .base.handle = NV_SUBDEV(INSTMEM, 0x04), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_instmem_ctor, .dtor = nv04_instmem_dtor, - .init = _nouveau_instmem_init, - .fini = _nouveau_instmem_fini, + .init = _nvkm_instmem_init, + .fini = _nvkm_instmem_fini, .rd32 = nv04_instmem_rd32, .wr32 = nv04_instmem_wr32, }, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h new file mode 100644 index 000000000000..42b6c928047c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h @@ -0,0 +1,36 @@ +#ifndef __NV04_INSTMEM_H__ +#define __NV04_INSTMEM_H__ +#include "priv.h" + +#include <core/mm.h> + +extern struct nvkm_instobj_impl nv04_instobj_oclass; + +struct nv04_instmem_priv { + struct nvkm_instmem base; + + void __iomem *iomem; + struct nvkm_mm heap; + + struct nvkm_gpuobj *vbios; + struct nvkm_ramht *ramht; + struct nvkm_gpuobj *ramro; + struct nvkm_gpuobj *ramfc; +}; + +static inline struct nv04_instmem_priv * +nv04_instmem(void *obj) +{ + return (void *)nvkm_instmem(obj); +} + +struct nv04_instobj_priv { + struct nvkm_instobj base; + struct nvkm_mm_node *mem; +}; + +void nv04_instmem_dtor(struct nvkm_object *); + +int nv04_instmem_alloc(struct nvkm_instmem *, struct nvkm_object *, + u32 size, u32 align, struct nvkm_object **pobject); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c index 8803809f9fc5..b42b8588fc0e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c @@ -21,39 +21,39 @@ * * Authors: Ben Skeggs */ - -#include <engine/graph/nv40.h> - #include "nv04.h" +#include <core/ramht.h> +#include <engine/gr/nv40.h> + /****************************************************************************** * instmem subdev implementation *****************************************************************************/ static u32 -nv40_instmem_rd32(struct nouveau_object *object, u64 addr) +nv40_instmem_rd32(struct nvkm_object *object, u64 addr) { struct nv04_instmem_priv *priv = (void *)object; return ioread32_native(priv->iomem + addr); } static void -nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) +nv40_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data) { struct nv04_instmem_priv *priv = (void *)object; iowrite32_native(data, priv->iomem + addr); } static int -nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); + struct nvkm_device *device = nv_device(parent); struct nv04_instmem_priv *priv; int ret, bar, vs; - ret = nouveau_instmem_create(parent, engine, oclass, &priv); + ret = nvkm_instmem_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -73,12 +73,12 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, /* PRAMIN aperture maps over the end of vram, reserve enough space * to fit graphics contexts for every channel, the magics come - * from engine/graph/nv40.c + * from engine/gr/nv40.c */ vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8); if (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs; else if (device->chipset < 0x43) priv->base.reserved = 0x4f00 * vs; - else if (nv44_graph_class(priv)) priv->base.reserved = 0x4980 * vs; + else if (nv44_gr_class(priv)) priv->base.reserved = 0x4980 * vs; else priv->base.reserved = 0x4a40 * vs; priv->base.reserved += 16 * 1024; priv->base.reserved *= 32; /* per-channel */ @@ -87,49 +87,48 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.reserved = round_up(priv->base.reserved, 4096); - ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); + ret = nvkm_mm_init(&priv->heap, 0, priv->base.reserved, 1); if (ret) return ret; /* 0x00000-0x10000: reserve for probable vbios image */ - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0, - &priv->vbios); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0, + &priv->vbios); if (ret) return ret; /* 0x10000-0x18000: reserve for RAMHT */ - ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0, - &priv->ramht); + ret = nvkm_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht); if (ret) return ret; /* 0x18000-0x18200: reserve for RAMRO * 0x18200-0x20000: padding */ - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x08000, 0, 0, - &priv->ramro); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x08000, 0, 0, + &priv->ramro); if (ret) return ret; /* 0x20000-0x21000: reserve for RAMFC * 0x21000-0x40000: padding and some unknown crap */ - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, + NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); if (ret) return ret; return 0; } -struct nouveau_oclass * -nv40_instmem_oclass = &(struct nouveau_instmem_impl) { +struct nvkm_oclass * +nv40_instmem_oclass = &(struct nvkm_instmem_impl) { .base.handle = NV_SUBDEV(INSTMEM, 0x40), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_instmem_ctor, .dtor = nv04_instmem_dtor, - .init = _nouveau_instmem_init, - .fini = _nouveau_instmem_fini, + .init = _nvkm_instmem_init, + .fini = _nvkm_instmem_fini, .rd32 = nv40_instmem_rd32, .wr32 = nv40_instmem_wr32, }, diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index 7cb3b098a08d..8404143f93ee 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -21,21 +21,19 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/fb.h> -#include <core/mm.h> - -#include "priv.h" struct nv50_instmem_priv { - struct nouveau_instmem base; + struct nvkm_instmem base; spinlock_t lock; u64 addr; }; struct nv50_instobj_priv { - struct nouveau_instobj base; - struct nouveau_mem *mem; + struct nvkm_instobj base; + struct nvkm_mem *mem; }; /****************************************************************************** @@ -43,9 +41,9 @@ struct nv50_instobj_priv { *****************************************************************************/ static u32 -nv50_instobj_rd32(struct nouveau_object *object, u64 offset) +nv50_instobj_rd32(struct nvkm_object *object, u64 offset) { - struct nv50_instmem_priv *priv = (void *)object->engine; + struct nv50_instmem_priv *priv = (void *)nvkm_instmem(object); struct nv50_instobj_priv *node = (void *)object; unsigned long flags; u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; @@ -63,9 +61,9 @@ nv50_instobj_rd32(struct nouveau_object *object, u64 offset) } static void -nv50_instobj_wr32(struct nouveau_object *object, u64 offset, u32 data) +nv50_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data) { - struct nv50_instmem_priv *priv = (void *)object->engine; + struct nv50_instmem_priv *priv = (void *)nvkm_instmem(object); struct nv50_instobj_priv *node = (void *)object; unsigned long flags; u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; @@ -81,28 +79,28 @@ nv50_instobj_wr32(struct nouveau_object *object, u64 offset, u32 data) } static void -nv50_instobj_dtor(struct nouveau_object *object) +nv50_instobj_dtor(struct nvkm_object *object) { struct nv50_instobj_priv *node = (void *)object; - struct nouveau_fb *pfb = nouveau_fb(object); + struct nvkm_fb *pfb = nvkm_fb(object); pfb->ram->put(pfb, &node->mem); - nouveau_instobj_destroy(&node->base); + nvkm_instobj_destroy(&node->base); } static int -nv50_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_instobj_args *args = data; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_instobj_args *args = data; struct nv50_instobj_priv *node; int ret; args->size = max((args->size + 4095) & ~4095, (u32)4096); args->align = max((args->align + 4095) & ~4095, (u32)4096); - ret = nouveau_instobj_create(parent, engine, oclass, &node); + ret = nvkm_instobj_create(parent, engine, oclass, &node); *pobject = nv_object(node); if (ret) return ret; @@ -117,13 +115,13 @@ nv50_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -static struct nouveau_instobj_impl +static struct nvkm_instobj_impl nv50_instobj_oclass = { - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_instobj_ctor, .dtor = nv50_instobj_dtor, - .init = _nouveau_instobj_init, - .fini = _nouveau_instobj_fini, + .init = _nvkm_instobj_init, + .fini = _nvkm_instobj_fini, .rd32 = nv50_instobj_rd32, .wr32 = nv50_instobj_wr32, }, @@ -134,22 +132,22 @@ nv50_instobj_oclass = { *****************************************************************************/ static int -nv50_instmem_fini(struct nouveau_object *object, bool suspend) +nv50_instmem_fini(struct nvkm_object *object, bool suspend) { struct nv50_instmem_priv *priv = (void *)object; priv->addr = ~0ULL; - return nouveau_instmem_fini(&priv->base, suspend); + return nvkm_instmem_fini(&priv->base, suspend); } static int -nv50_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_instmem_priv *priv; int ret; - ret = nouveau_instmem_create(parent, engine, oclass, &priv); + ret = nvkm_instmem_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -158,13 +156,13 @@ nv50_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * -nv50_instmem_oclass = &(struct nouveau_instmem_impl) { +struct nvkm_oclass * +nv50_instmem_oclass = &(struct nvkm_instmem_impl) { .base.handle = NV_SUBDEV(INSTMEM, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_instmem_ctor, - .dtor = _nouveau_instmem_dtor, - .init = _nouveau_instmem_init, + .dtor = _nvkm_instmem_dtor, + .init = _nvkm_instmem_init, .fini = nv50_instmem_fini, }, .instobj = &nv50_instobj_oclass.base, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h new file mode 100644 index 000000000000..b10e292e5607 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h @@ -0,0 +1,54 @@ +#ifndef __NVKM_INSTMEM_PRIV_H__ +#define __NVKM_INSTMEM_PRIV_H__ +#include <subdev/instmem.h> + +struct nvkm_instobj_impl { + struct nvkm_oclass base; +}; + +struct nvkm_instobj_args { + u32 size; + u32 align; +}; + +#define nvkm_instobj_create(p,e,o,d) \ + nvkm_instobj_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_instobj_destroy(p) ({ \ + struct nvkm_instobj *iobj = (p); \ + _nvkm_instobj_dtor(nv_object(iobj)); \ +}) +#define nvkm_instobj_init(p) \ + nvkm_object_init(&(p)->base) +#define nvkm_instobj_fini(p,s) \ + nvkm_object_fini(&(p)->base, (s)) + +int nvkm_instobj_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_instobj_dtor(struct nvkm_object *); +#define _nvkm_instobj_init nvkm_object_init +#define _nvkm_instobj_fini nvkm_object_fini + +struct nvkm_instmem_impl { + struct nvkm_oclass base; + struct nvkm_oclass *instobj; +}; + +#define nvkm_instmem_create(p,e,o,d) \ + nvkm_instmem_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_instmem_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_instmem_init(p) ({ \ + struct nvkm_instmem *imem = (p); \ + _nvkm_instmem_init(nv_object(imem)); \ +}) +#define nvkm_instmem_fini(p,s) ({ \ + struct nvkm_instmem *imem = (p); \ + _nvkm_instmem_fini(nv_object(imem), (s)); \ +}) + +int nvkm_instmem_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +#define _nvkm_instmem_dtor _nvkm_subdev_dtor +int _nvkm_instmem_init(struct nvkm_object *); +int _nvkm_instmem_fini(struct nvkm_object *, bool); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild new file mode 100644 index 000000000000..e5df3d865f0c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild @@ -0,0 +1,4 @@ +nvkm-y += nvkm/subdev/ltc/base.o +nvkm-y += nvkm/subdev/ltc/gf100.o +nvkm-y += nvkm/subdev/ltc/gk104.o +nvkm-y += nvkm/subdev/ltc/gm107.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c index 7fa331516f84..2fb87fbfd11c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c @@ -21,17 +21,15 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - #include "priv.h" static int -nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n, - struct nouveau_mm_node **pnode) +nvkm_ltc_tags_alloc(struct nvkm_ltc *ltc, u32 n, struct nvkm_mm_node **pnode) { struct nvkm_ltc_priv *priv = (void *)ltc; int ret; - ret = nouveau_mm_head(&priv->tags, 0, 1, n, n, 1, pnode); + ret = nvkm_mm_head(&priv->tags, 0, 1, n, n, 1, pnode); if (ret) *pnode = NULL; @@ -39,14 +37,14 @@ nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n, } static void -nvkm_ltc_tags_free(struct nouveau_ltc *ltc, struct nouveau_mm_node **pnode) +nvkm_ltc_tags_free(struct nvkm_ltc *ltc, struct nvkm_mm_node **pnode) { struct nvkm_ltc_priv *priv = (void *)ltc; - nouveau_mm_free(&priv->tags, pnode); + nvkm_mm_free(&priv->tags, pnode); } static void -nvkm_ltc_tags_clear(struct nouveau_ltc *ltc, u32 first, u32 count) +nvkm_ltc_tags_clear(struct nvkm_ltc *ltc, u32 first, u32 count) { const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); struct nvkm_ltc_priv *priv = (void *)ltc; @@ -59,7 +57,7 @@ nvkm_ltc_tags_clear(struct nouveau_ltc *ltc, u32 first, u32 count) } static int -nvkm_ltc_zbc_color_get(struct nouveau_ltc *ltc, int index, const u32 color[4]) +nvkm_ltc_zbc_color_get(struct nvkm_ltc *ltc, int index, const u32 color[4]) { const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); struct nvkm_ltc_priv *priv = (void *)ltc; @@ -69,7 +67,7 @@ nvkm_ltc_zbc_color_get(struct nouveau_ltc *ltc, int index, const u32 color[4]) } static int -nvkm_ltc_zbc_depth_get(struct nouveau_ltc *ltc, int index, const u32 depth) +nvkm_ltc_zbc_depth_get(struct nvkm_ltc *ltc, int index, const u32 depth) { const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); struct nvkm_ltc_priv *priv = (void *)ltc; @@ -79,13 +77,13 @@ nvkm_ltc_zbc_depth_get(struct nouveau_ltc *ltc, int index, const u32 depth) } int -_nvkm_ltc_init(struct nouveau_object *object) +_nvkm_ltc_init(struct nvkm_object *object) { const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object); struct nvkm_ltc_priv *priv = (void *)object; int ret, i; - ret = nouveau_subdev_init(&priv->base.base); + ret = nvkm_subdev_init(&priv->base.base); if (ret) return ret; @@ -98,15 +96,15 @@ _nvkm_ltc_init(struct nouveau_object *object) } int -nvkm_ltc_create_(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) +nvkm_ltc_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { const struct nvkm_ltc_impl *impl = (void *)oclass; struct nvkm_ltc_priv *priv; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PLTCG", - "l2c", length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PLTCG", + "l2c", length, pobject); priv = *pobject; if (ret) return ret; @@ -119,7 +117,7 @@ nvkm_ltc_create_(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.tags_free = nvkm_ltc_tags_free; priv->base.tags_clear = nvkm_ltc_tags_clear; priv->base.zbc_min = 1; /* reserve 0 for disabled */ - priv->base.zbc_max = min(impl->zbc, NOUVEAU_LTC_MAX_ZBC_CNT) - 1; + priv->base.zbc_max = min(impl->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1; priv->base.zbc_color_get = nvkm_ltc_zbc_color_get; priv->base.zbc_depth_get = nvkm_ltc_zbc_depth_get; return 0; diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c index 2db0977284f8..8e7cc6200d60 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c @@ -21,12 +21,12 @@ * * Authors: Ben Skeggs */ +#include "priv.h" +#include <core/enum.h> #include <subdev/fb.h> #include <subdev/timer.h> -#include "priv.h" - void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit) { @@ -62,7 +62,7 @@ gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth) nv_wr32(priv, 0x17ea58, depth); } -static const struct nouveau_bitfield +static const struct nvkm_bitfield gf100_ltc_lts_intr_name[] = { { 0x00000001, "IDLE_ERROR_IQ" }, { 0x00000002, "IDLE_ERROR_CBC" }, @@ -89,7 +89,7 @@ gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts) if (stat) { nv_info(priv, "LTC%d_LTS%d:", ltc, lts); - nouveau_bitfield_print(gf100_ltc_lts_intr_name, stat); + nvkm_bitfield_print(gf100_ltc_lts_intr_name, stat); pr_cont("\n"); } @@ -97,7 +97,7 @@ gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts) } void -gf100_ltc_intr(struct nouveau_subdev *subdev) +gf100_ltc_intr(struct nvkm_subdev *subdev) { struct nvkm_ltc_priv *priv = (void *)subdev; u32 mask; @@ -112,7 +112,7 @@ gf100_ltc_intr(struct nouveau_subdev *subdev) } static int -gf100_ltc_init(struct nouveau_object *object) +gf100_ltc_init(struct nvkm_object *object) { struct nvkm_ltc_priv *priv = (void *)object; u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); @@ -130,13 +130,13 @@ gf100_ltc_init(struct nouveau_object *object) } void -gf100_ltc_dtor(struct nouveau_object *object) +gf100_ltc_dtor(struct nvkm_object *object) { - struct nouveau_fb *pfb = nouveau_fb(object); + struct nvkm_fb *pfb = nvkm_fb(object); struct nvkm_ltc_priv *priv = (void *)object; - nouveau_mm_fini(&priv->tags); - nouveau_mm_free(&pfb->vram, &priv->tag_ram); + nvkm_mm_fini(&priv->tags); + nvkm_mm_free(&pfb->vram, &priv->tag_ram); nvkm_ltc_destroy(priv); } @@ -144,7 +144,7 @@ gf100_ltc_dtor(struct nouveau_object *object) /* TODO: Figure out tag memory details and drop the over-cautious allocation. */ int -gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv) +gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv) { u32 tag_size, tag_margin, tag_align; int ret; @@ -170,8 +170,8 @@ gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv) tag_size += tag_align; tag_size = (tag_size + 0xfff) >> 12; /* round up */ - ret = nouveau_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1, - &priv->tag_ram); + ret = nvkm_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1, + &priv->tag_ram); if (ret) { priv->num_tags = 0; } else { @@ -183,16 +183,16 @@ gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv) priv->tag_base = tag_base; } - ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1); + ret = nvkm_mm_init(&priv->tags, 0, priv->num_tags, 1); return ret; } int -gf100_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nvkm_ltc_priv *priv; u32 parts, mask; int ret, i; @@ -218,10 +218,10 @@ gf100_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * +struct nvkm_oclass * gf100_ltc_oclass = &(struct nvkm_ltc_impl) { .base.handle = NV_SUBDEV(LTC, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gf100_ltc_ctor, .dtor = gf100_ltc_dtor, .init = gf100_ltc_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c index b39b5d0eb8f9..d53959b5ec67 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c @@ -21,11 +21,10 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static int -gk104_ltc_init(struct nouveau_object *object) +gk104_ltc_init(struct nvkm_object *object) { struct nvkm_ltc_priv *priv = (void *)object; u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); @@ -42,10 +41,10 @@ gk104_ltc_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * gk104_ltc_oclass = &(struct nvkm_ltc_impl) { .base.handle = NV_SUBDEV(LTC, 0xe4), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gf100_ltc_ctor, .dtor = gf100_ltc_dtor, .init = gk104_ltc_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c index 89fc4238f50c..6b3f6f4ce107 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -21,12 +21,11 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/fb.h> #include <subdev/timer.h> -#include "priv.h" - static void gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit) { @@ -75,7 +74,7 @@ gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts) } static void -gm107_ltc_intr(struct nouveau_subdev *subdev) +gm107_ltc_intr(struct nvkm_subdev *subdev) { struct nvkm_ltc_priv *priv = (void *)subdev; u32 mask; @@ -90,7 +89,7 @@ gm107_ltc_intr(struct nouveau_subdev *subdev) } static int -gm107_ltc_init(struct nouveau_object *object) +gm107_ltc_init(struct nvkm_object *object) { struct nvkm_ltc_priv *priv = (void *)object; u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); @@ -107,11 +106,11 @@ gm107_ltc_init(struct nouveau_object *object) } static int -gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nvkm_ltc_priv *priv; u32 parts, mask; int ret, i; @@ -136,10 +135,10 @@ gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * +struct nvkm_oclass * gm107_ltc_oclass = &(struct nvkm_ltc_impl) { .base.handle = NV_SUBDEV(LTC, 0xff), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gm107_ltc_ctor, .dtor = gf100_ltc_dtor, .init = gm107_ltc_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h index 41f179d93da6..09537d7b6783 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -1,23 +1,22 @@ #ifndef __NVKM_LTC_PRIV_H__ #define __NVKM_LTC_PRIV_H__ - #include <subdev/ltc.h> -#include <subdev/fb.h> -#include <core/enum.h> +#include <core/mm.h> +struct nvkm_fb; struct nvkm_ltc_priv { - struct nouveau_ltc base; + struct nvkm_ltc base; u32 ltc_nr; u32 lts_nr; u32 num_tags; u32 tag_base; - struct nouveau_mm tags; - struct nouveau_mm_node *tag_ram; + struct nvkm_mm tags; + struct nvkm_mm_node *tag_ram; - u32 zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT][4]; - u32 zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT]; + u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4]; + u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT]; }; #define nvkm_ltc_create(p,e,o,d) \ @@ -35,24 +34,24 @@ struct nvkm_ltc_priv { _nvkm_ltc_fini(nv_object(_priv), (s)); \ }) -int nvkm_ltc_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); +int nvkm_ltc_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); -#define _nvkm_ltc_dtor _nouveau_subdev_dtor -int _nvkm_ltc_init(struct nouveau_object *); -#define _nvkm_ltc_fini _nouveau_subdev_fini +#define _nvkm_ltc_dtor _nvkm_subdev_dtor +int _nvkm_ltc_init(struct nvkm_object *); +#define _nvkm_ltc_fini _nvkm_subdev_fini -int gf100_ltc_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void gf100_ltc_dtor(struct nouveau_object *); -int gf100_ltc_init_tag_ram(struct nouveau_fb *, struct nvkm_ltc_priv *); -int gf100_ltc_tags_alloc(struct nouveau_ltc *, u32, struct nouveau_mm_node **); -void gf100_ltc_tags_free(struct nouveau_ltc *, struct nouveau_mm_node **); +int gf100_ltc_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gf100_ltc_dtor(struct nvkm_object *); +int gf100_ltc_init_tag_ram(struct nvkm_fb *, struct nvkm_ltc_priv *); +int gf100_ltc_tags_alloc(struct nvkm_ltc *, u32, struct nvkm_mm_node **); +void gf100_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **); struct nvkm_ltc_impl { - struct nouveau_oclass base; - void (*intr)(struct nouveau_subdev *); + struct nvkm_oclass base; + void (*intr)(struct nvkm_subdev *); void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit); void (*cbc_wait)(struct nvkm_ltc_priv *); @@ -62,10 +61,9 @@ struct nvkm_ltc_impl { void (*zbc_clear_depth)(struct nvkm_ltc_priv *, int, const u32); }; -void gf100_ltc_intr(struct nouveau_subdev *); +void gf100_ltc_intr(struct nvkm_subdev *); void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32); void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *); void gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *, int, const u32[4]); void gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *, int, const u32); - #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild new file mode 100644 index 000000000000..721643f04bb5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild @@ -0,0 +1,11 @@ +nvkm-y += nvkm/subdev/mc/base.o +nvkm-y += nvkm/subdev/mc/nv04.o +nvkm-y += nvkm/subdev/mc/nv40.o +nvkm-y += nvkm/subdev/mc/nv44.o +nvkm-y += nvkm/subdev/mc/nv4c.o +nvkm-y += nvkm/subdev/mc/nv50.o +nvkm-y += nvkm/subdev/mc/g94.o +nvkm-y += nvkm/subdev/mc/g98.o +nvkm-y += nvkm/subdev/mc/gf100.o +nvkm-y += nvkm/subdev/mc/gf106.o +nvkm-y += nvkm/subdev/mc/gk20a.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c index ca7cee3a314a..5b051a26653e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c @@ -21,20 +21,21 @@ * * Authors: Ben Skeggs */ - #include "priv.h" + +#include <core/device.h> #include <core/option.h> static inline void -nouveau_mc_unk260(struct nouveau_mc *pmc, u32 data) +nvkm_mc_unk260(struct nvkm_mc *pmc, u32 data) { - const struct nouveau_mc_oclass *impl = (void *)nv_oclass(pmc); + const struct nvkm_mc_oclass *impl = (void *)nv_oclass(pmc); if (impl->unk260) impl->unk260(pmc, data); } static inline u32 -nouveau_mc_intr_mask(struct nouveau_mc *pmc) +nvkm_mc_intr_mask(struct nvkm_mc *pmc) { u32 intr = nv_rd32(pmc, 0x000100); if (intr == 0xffffffff) /* likely fallen off the bus */ @@ -43,25 +44,25 @@ nouveau_mc_intr_mask(struct nouveau_mc *pmc) } static irqreturn_t -nouveau_mc_intr(int irq, void *arg) +nvkm_mc_intr(int irq, void *arg) { - struct nouveau_mc *pmc = arg; - const struct nouveau_mc_oclass *oclass = (void *)nv_object(pmc)->oclass; - const struct nouveau_mc_intr *map = oclass->intr; - struct nouveau_subdev *unit; + struct nvkm_mc *pmc = arg; + const struct nvkm_mc_oclass *oclass = (void *)nv_object(pmc)->oclass; + const struct nvkm_mc_intr *map = oclass->intr; + struct nvkm_subdev *unit; u32 intr; nv_wr32(pmc, 0x000140, 0x00000000); nv_rd32(pmc, 0x000140); - intr = nouveau_mc_intr_mask(pmc); + intr = nvkm_mc_intr_mask(pmc); if (pmc->use_msi) oclass->msi_rearm(pmc); if (intr) { - u32 stat = intr = nouveau_mc_intr_mask(pmc); + u32 stat = intr = nvkm_mc_intr_mask(pmc); while (map->stat) { if (intr & map->stat) { - unit = nouveau_subdev(pmc, map->unit); + unit = nvkm_subdev(pmc, map->unit); if (unit && unit->intr) unit->intr(unit); stat &= ~map->stat; @@ -78,18 +79,18 @@ nouveau_mc_intr(int irq, void *arg) } int -_nouveau_mc_fini(struct nouveau_object *object, bool suspend) +_nvkm_mc_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_mc *pmc = (void *)object; + struct nvkm_mc *pmc = (void *)object; nv_wr32(pmc, 0x000140, 0x00000000); - return nouveau_subdev_fini(&pmc->base, suspend); + return nvkm_subdev_fini(&pmc->base, suspend); } int -_nouveau_mc_init(struct nouveau_object *object) +_nvkm_mc_init(struct nvkm_object *object) { - struct nouveau_mc *pmc = (void *)object; - int ret = nouveau_subdev_init(&pmc->base); + struct nvkm_mc *pmc = (void *)object; + int ret = nvkm_subdev_init(&pmc->base); if (ret) return ret; nv_wr32(pmc, 0x000140, 0x00000001); @@ -97,34 +98,34 @@ _nouveau_mc_init(struct nouveau_object *object) } void -_nouveau_mc_dtor(struct nouveau_object *object) +_nvkm_mc_dtor(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); - struct nouveau_mc *pmc = (void *)object; + struct nvkm_device *device = nv_device(object); + struct nvkm_mc *pmc = (void *)object; free_irq(pmc->irq, pmc); if (pmc->use_msi) pci_disable_msi(device->pdev); - nouveau_subdev_destroy(&pmc->base); + nvkm_subdev_destroy(&pmc->base); } int -nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *bclass, int length, void **pobject) +nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *bclass, int length, void **pobject) { - const struct nouveau_mc_oclass *oclass = (void *)bclass; - struct nouveau_device *device = nv_device(parent); - struct nouveau_mc *pmc; + const struct nvkm_mc_oclass *oclass = (void *)bclass; + struct nvkm_device *device = nv_device(parent); + struct nvkm_mc *pmc; int ret; - ret = nouveau_subdev_create_(parent, engine, bclass, 0, "PMC", - "master", length, pobject); + ret = nvkm_subdev_create_(parent, engine, bclass, 0, "PMC", + "master", length, pobject); pmc = *pobject; if (ret) return ret; - pmc->unk260 = nouveau_mc_unk260; + pmc->unk260 = nvkm_mc_unk260; - if (nv_device_is_pci(device)) + if (nv_device_is_pci(device)) { switch (device->pdev->device & 0x0ff0) { case 0x00f0: case 0x02e0: @@ -138,10 +139,11 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, default: pmc->use_msi = true; break; + } } - pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", - pmc->use_msi); + pmc->use_msi = nvkm_boolopt(device->cfgopt, "NvMSI", + pmc->use_msi); if (pmc->use_msi && oclass->msi_rearm) { pmc->use_msi = pci_enable_msi(device->pdev) == 0; @@ -159,9 +161,7 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, return ret; pmc->irq = ret; - ret = request_irq(pmc->irq, nouveau_mc_intr, IRQF_SHARED, "nouveau", - pmc); - + ret = request_irq(pmc->irq, nvkm_mc_intr, IRQF_SHARED, "nvkm", pmc); if (ret < 0) return ret; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c index 5f4541105e73..f042e7d8321d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c @@ -21,17 +21,16 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" -struct nouveau_oclass * -nv94_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +g94_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0x94), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv50_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, .intr = nv50_mc_intr, .msi_rearm = nv40_mc_msi_rearm, diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c index 3c76d9038f38..8ab7f1272a14 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c @@ -21,39 +21,38 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" -static const struct nouveau_mc_intr -nv98_mc_intr[] = { +static const struct nvkm_mc_intr +g98_mc_intr[] = { { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */ - { 0x00000001, NVDEV_ENGINE_PPP }, + { 0x00000001, NVDEV_ENGINE_MSPPP }, { 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00001000, NVDEV_ENGINE_GR }, - { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */ - { 0x00008000, NVDEV_ENGINE_BSP }, - { 0x00020000, NVDEV_ENGINE_VP }, - { 0x00040000, NVDEV_SUBDEV_PWR }, /* NVA3:NVC0 */ + { 0x00004000, NVDEV_ENGINE_SEC }, /* NV84:NVA3 */ + { 0x00008000, NVDEV_ENGINE_MSVLD }, + { 0x00020000, NVDEV_ENGINE_MSPDEC }, + { 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */ { 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */ { 0x00100000, NVDEV_SUBDEV_TIMER }, { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ - { 0x00400000, NVDEV_ENGINE_COPY0 }, /* NVA3- */ + { 0x00400000, NVDEV_ENGINE_CE0 }, /* NVA3- */ { 0x10000000, NVDEV_SUBDEV_BUS }, { 0x80000000, NVDEV_ENGINE_SW }, { 0x0042d101, NVDEV_SUBDEV_FB }, {}, }; -struct nouveau_oclass * -nv98_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +g98_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0x98), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv50_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, - .intr = nv98_mc_intr, + .intr = g98_mc_intr, .msi_rearm = nv40_mc_msi_rearm, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c index 15d41dc176ff..2425984b045e 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c @@ -21,26 +21,25 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" -const struct nouveau_mc_intr -nvc0_mc_intr[] = { +const struct nvkm_mc_intr +gf100_mc_intr[] = { { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */ - { 0x00000001, NVDEV_ENGINE_PPP }, - { 0x00000020, NVDEV_ENGINE_COPY0 }, - { 0x00000040, NVDEV_ENGINE_COPY1 }, - { 0x00000080, NVDEV_ENGINE_COPY2 }, + { 0x00000001, NVDEV_ENGINE_MSPPP }, + { 0x00000020, NVDEV_ENGINE_CE0 }, + { 0x00000040, NVDEV_ENGINE_CE1 }, + { 0x00000080, NVDEV_ENGINE_CE2 }, { 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00001000, NVDEV_ENGINE_GR }, { 0x00002000, NVDEV_SUBDEV_FB }, - { 0x00008000, NVDEV_ENGINE_BSP }, + { 0x00008000, NVDEV_ENGINE_MSVLD }, { 0x00040000, NVDEV_SUBDEV_THERM }, - { 0x00020000, NVDEV_ENGINE_VP }, + { 0x00020000, NVDEV_ENGINE_MSPDEC }, { 0x00100000, NVDEV_SUBDEV_TIMER }, { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ - { 0x01000000, NVDEV_SUBDEV_PWR }, + { 0x01000000, NVDEV_SUBDEV_PMU }, { 0x02000000, NVDEV_SUBDEV_LTC }, { 0x08000000, NVDEV_SUBDEV_FB }, { 0x10000000, NVDEV_SUBDEV_BUS }, @@ -50,28 +49,28 @@ nvc0_mc_intr[] = { }; static void -nvc0_mc_msi_rearm(struct nouveau_mc *pmc) +gf100_mc_msi_rearm(struct nvkm_mc *pmc) { struct nv04_mc_priv *priv = (void *)pmc; nv_wr32(priv, 0x088704, 0x00000000); } void -nvc0_mc_unk260(struct nouveau_mc *pmc, u32 data) +gf100_mc_unk260(struct nvkm_mc *pmc, u32 data) { nv_wr32(pmc, 0x000260, data); } -struct nouveau_oclass * -nvc0_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +gf100_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv50_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, - .intr = nvc0_mc_intr, - .msi_rearm = nvc0_mc_msi_rearm, - .unk260 = nvc0_mc_unk260, + .intr = gf100_mc_intr, + .msi_rearm = gf100_mc_msi_rearm, + .unk260 = gf100_mc_unk260, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c index 68b5f61aadb5..8d2a8f457778 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" -struct nouveau_oclass * -nvc3_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +gf106_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0xc3), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv50_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, - .intr = nvc0_mc_intr, + .intr = gf100_mc_intr, .msi_rearm = nv40_mc_msi_rearm, - .unk260 = nvc0_mc_unk260, + .unk260 = gf100_mc_unk260, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c index b8d6cb435d0a..43b27742956d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c @@ -21,18 +21,17 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" -struct nouveau_oclass * -gk20a_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +gk20a_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0xea), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv50_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, - .intr = nvc0_mc_intr, + .intr = gf100_mc_intr, .msi_rearm = nv40_mc_msi_rearm, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c index 2d787e4dfefa..32713827b4dc 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c @@ -21,10 +21,9 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" -const struct nouveau_mc_intr +const struct nvkm_mc_intr nv04_mc_intr[] = { { 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */ { 0x00000100, NVDEV_ENGINE_FIFO }, @@ -40,25 +39,25 @@ nv04_mc_intr[] = { }; int -nv04_mc_init(struct nouveau_object *object) +nv04_mc_init(struct nvkm_object *object) { struct nv04_mc_priv *priv = (void *)object; nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */ nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */ - return nouveau_mc_init(&priv->base); + return nvkm_mc_init(&priv->base); } int -nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_mc_priv *priv; int ret; - ret = nouveau_mc_create(parent, engine, oclass, &priv); + ret = nvkm_mc_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -66,14 +65,14 @@ nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * -nv04_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +nv04_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0x04), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv04_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, .intr = nv04_mc_intr, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h new file mode 100644 index 000000000000..411de3d08ab6 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h @@ -0,0 +1,20 @@ +#ifndef __NVKM_MC_NV04_H__ +#define __NVKM_MC_NV04_H__ +#include "priv.h" + +struct nv04_mc_priv { + struct nvkm_mc base; +}; + +int nv04_mc_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); + +extern const struct nvkm_mc_intr nv04_mc_intr[]; +int nv04_mc_init(struct nvkm_object *); +void nv40_mc_msi_rearm(struct nvkm_mc *); +int nv44_mc_init(struct nvkm_object *object); +int nv50_mc_init(struct nvkm_object *); +extern const struct nvkm_mc_intr nv50_mc_intr[]; +extern const struct nvkm_mc_intr gf100_mc_intr[]; +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c index 5b1faecfed2d..b7613059da08 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c @@ -21,24 +21,23 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" void -nv40_mc_msi_rearm(struct nouveau_mc *pmc) +nv40_mc_msi_rearm(struct nvkm_mc *pmc) { struct nv04_mc_priv *priv = (void *)pmc; nv_wr08(priv, 0x088068, 0xff); } -struct nouveau_oclass * -nv40_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +nv40_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0x40), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv04_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, .intr = nv04_mc_intr, .msi_rearm = nv40_mc_msi_rearm, diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c index cc4d0d2d886e..2c7f7c701a2b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c @@ -21,11 +21,10 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" int -nv44_mc_init(struct nouveau_object *object) +nv44_mc_init(struct nvkm_object *object) { struct nv04_mc_priv *priv = (void *)object; u32 tmp = nv_rd32(priv, 0x10020c); @@ -37,17 +36,17 @@ nv44_mc_init(struct nouveau_object *object) nv_wr32(priv, 0x001708, 0); nv_wr32(priv, 0x00170c, tmp); - return nouveau_mc_init(&priv->base); + return nvkm_mc_init(&priv->base); } -struct nouveau_oclass * -nv44_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +nv44_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0x44), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv44_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, .intr = nv04_mc_intr, .msi_rearm = nv40_mc_msi_rearm, diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c index a75c35ccf25c..c0aac7e20d45 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c @@ -21,25 +21,16 @@ * * Authors: Ilia Mirkin */ - #include "nv04.h" -static void -nv4c_mc_msi_rearm(struct nouveau_mc *pmc) -{ - struct nv04_mc_priv *priv = (void *)pmc; - nv_wr08(priv, 0x088050, 0xff); -} - -struct nouveau_oclass * -nv4c_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +nv4c_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0x4c), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv44_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, .intr = nv04_mc_intr, - .msi_rearm = nv4c_mc_msi_rearm, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c index 9ca93e2718f7..40e3019e1fde 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c @@ -21,16 +21,17 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" -const struct nouveau_mc_intr +#include <core/device.h> + +const struct nvkm_mc_intr nv50_mc_intr[] = { { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */ { 0x00000001, NVDEV_ENGINE_MPEG }, { 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00001000, NVDEV_ENGINE_GR }, - { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84- */ + { 0x00004000, NVDEV_ENGINE_CIPHER }, /* NV84- */ { 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */ { 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */ { 0x00100000, NVDEV_SUBDEV_TIMER }, @@ -43,28 +44,28 @@ nv50_mc_intr[] = { }; static void -nv50_mc_msi_rearm(struct nouveau_mc *pmc) +nv50_mc_msi_rearm(struct nvkm_mc *pmc) { - struct nouveau_device *device = nv_device(pmc); + struct nvkm_device *device = nv_device(pmc); pci_write_config_byte(device->pdev, 0x68, 0xff); } int -nv50_mc_init(struct nouveau_object *object) +nv50_mc_init(struct nvkm_object *object) { struct nv04_mc_priv *priv = (void *)object; nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */ - return nouveau_mc_init(&priv->base); + return nvkm_mc_init(&priv->base); } -struct nouveau_oclass * -nv50_mc_oclass = &(struct nouveau_mc_oclass) { +struct nvkm_oclass * +nv50_mc_oclass = &(struct nvkm_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mc_ctor, - .dtor = _nouveau_mc_dtor, + .dtor = _nvkm_mc_dtor, .init = nv50_mc_init, - .fini = _nouveau_mc_fini, + .fini = _nvkm_mc_fini, }, .intr = nv50_mc_intr, .msi_rearm = nv50_mc_msi_rearm, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h new file mode 100644 index 000000000000..d2cad07afd1a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h @@ -0,0 +1,36 @@ +#ifndef __NVKM_MC_PRIV_H__ +#define __NVKM_MC_PRIV_H__ +#include <subdev/mc.h> + +#define nvkm_mc_create(p,e,o,d) \ + nvkm_mc_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_mc_destroy(p) ({ \ + struct nvkm_mc *pmc = (p); _nvkm_mc_dtor(nv_object(pmc)); \ +}) +#define nvkm_mc_init(p) ({ \ + struct nvkm_mc *pmc = (p); _nvkm_mc_init(nv_object(pmc)); \ +}) +#define nvkm_mc_fini(p,s) ({ \ + struct nvkm_mc *pmc = (p); _nvkm_mc_fini(nv_object(pmc), (s)); \ +}) + +int nvkm_mc_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_mc_dtor(struct nvkm_object *); +int _nvkm_mc_init(struct nvkm_object *); +int _nvkm_mc_fini(struct nvkm_object *, bool); + +struct nvkm_mc_intr { + u32 stat; + u32 unit; +}; + +struct nvkm_mc_oclass { + struct nvkm_oclass base; + const struct nvkm_mc_intr *intr; + void (*msi_rearm)(struct nvkm_mc *); + void (*unk260)(struct nvkm_mc *, u32); +}; + +void gf100_mc_unk260(struct nvkm_mc *, u32); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild new file mode 100644 index 000000000000..012c9db687b2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild @@ -0,0 +1,6 @@ +nvkm-y += nvkm/subdev/mmu/base.o +nvkm-y += nvkm/subdev/mmu/nv04.o +nvkm-y += nvkm/subdev/mmu/nv41.o +nvkm-y += nvkm/subdev/mmu/nv44.o +nvkm-y += nvkm/subdev/mmu/nv50.o +nvkm-y += nvkm/subdev/mmu/gf100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c new file mode 100644 index 000000000000..277b6ec04e24 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c @@ -0,0 +1,480 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include <subdev/mmu.h> +#include <subdev/fb.h> + +#include <core/gpuobj.h> + +void +nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node) +{ + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_mm_node *r; + int big = vma->node->type != mmu->spg_shift; + u32 offset = vma->node->offset + (delta >> 12); + u32 bits = vma->node->type - 12; + u32 pde = (offset >> mmu->pgt_bits) - vm->fpde; + u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits; + u32 max = 1 << (mmu->pgt_bits - bits); + u32 end, len; + + delta = 0; + list_for_each_entry(r, &node->regions, rl_entry) { + u64 phys = (u64)r->offset << 12; + u32 num = r->length >> bits; + + while (num) { + struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big]; + + end = (pte + num); + if (unlikely(end >= max)) + end = max; + len = end - pte; + + mmu->map(vma, pgt, node, pte, len, phys, delta); + + num -= len; + pte += len; + if (unlikely(end >= max)) { + phys += len << (bits + 12); + pde++; + pte = 0; + } + + delta += (u64)len << vma->node->type; + } + } + + mmu->flush(vm); +} + +static void +nvkm_vm_map_sg_table(struct nvkm_vma *vma, u64 delta, u64 length, + struct nvkm_mem *mem) +{ + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; + int big = vma->node->type != mmu->spg_shift; + u32 offset = vma->node->offset + (delta >> 12); + u32 bits = vma->node->type - 12; + u32 num = length >> vma->node->type; + u32 pde = (offset >> mmu->pgt_bits) - vm->fpde; + u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits; + u32 max = 1 << (mmu->pgt_bits - bits); + unsigned m, sglen; + u32 end, len; + int i; + struct scatterlist *sg; + + for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) { + struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big]; + sglen = sg_dma_len(sg) >> PAGE_SHIFT; + + end = pte + sglen; + if (unlikely(end >= max)) + end = max; + len = end - pte; + + for (m = 0; m < len; m++) { + dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); + + mmu->map_sg(vma, pgt, mem, pte, 1, &addr); + num--; + pte++; + + if (num == 0) + goto finish; + } + if (unlikely(end >= max)) { + pde++; + pte = 0; + } + if (m < sglen) { + for (; m < sglen; m++) { + dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); + + mmu->map_sg(vma, pgt, mem, pte, 1, &addr); + num--; + pte++; + if (num == 0) + goto finish; + } + } + + } +finish: + mmu->flush(vm); +} + +static void +nvkm_vm_map_sg(struct nvkm_vma *vma, u64 delta, u64 length, + struct nvkm_mem *mem) +{ + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; + dma_addr_t *list = mem->pages; + int big = vma->node->type != mmu->spg_shift; + u32 offset = vma->node->offset + (delta >> 12); + u32 bits = vma->node->type - 12; + u32 num = length >> vma->node->type; + u32 pde = (offset >> mmu->pgt_bits) - vm->fpde; + u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits; + u32 max = 1 << (mmu->pgt_bits - bits); + u32 end, len; + + while (num) { + struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big]; + + end = (pte + num); + if (unlikely(end >= max)) + end = max; + len = end - pte; + + mmu->map_sg(vma, pgt, mem, pte, len, list); + + num -= len; + pte += len; + list += len; + if (unlikely(end >= max)) { + pde++; + pte = 0; + } + } + + mmu->flush(vm); +} + +void +nvkm_vm_map(struct nvkm_vma *vma, struct nvkm_mem *node) +{ + if (node->sg) + nvkm_vm_map_sg_table(vma, 0, node->size << 12, node); + else + if (node->pages) + nvkm_vm_map_sg(vma, 0, node->size << 12, node); + else + nvkm_vm_map_at(vma, 0, node); +} + +void +nvkm_vm_unmap_at(struct nvkm_vma *vma, u64 delta, u64 length) +{ + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; + int big = vma->node->type != mmu->spg_shift; + u32 offset = vma->node->offset + (delta >> 12); + u32 bits = vma->node->type - 12; + u32 num = length >> vma->node->type; + u32 pde = (offset >> mmu->pgt_bits) - vm->fpde; + u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits; + u32 max = 1 << (mmu->pgt_bits - bits); + u32 end, len; + + while (num) { + struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big]; + + end = (pte + num); + if (unlikely(end >= max)) + end = max; + len = end - pte; + + mmu->unmap(pgt, pte, len); + + num -= len; + pte += len; + if (unlikely(end >= max)) { + pde++; + pte = 0; + } + } + + mmu->flush(vm); +} + +void +nvkm_vm_unmap(struct nvkm_vma *vma) +{ + nvkm_vm_unmap_at(vma, 0, (u64)vma->node->length << 12); +} + +static void +nvkm_vm_unmap_pgt(struct nvkm_vm *vm, int big, u32 fpde, u32 lpde) +{ + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_vm_pgd *vpgd; + struct nvkm_vm_pgt *vpgt; + struct nvkm_gpuobj *pgt; + u32 pde; + + for (pde = fpde; pde <= lpde; pde++) { + vpgt = &vm->pgt[pde - vm->fpde]; + if (--vpgt->refcount[big]) + continue; + + pgt = vpgt->obj[big]; + vpgt->obj[big] = NULL; + + list_for_each_entry(vpgd, &vm->pgd_list, head) { + mmu->map_pgt(vpgd->obj, pde, vpgt->obj); + } + + mutex_unlock(&nv_subdev(mmu)->mutex); + nvkm_gpuobj_ref(NULL, &pgt); + mutex_lock(&nv_subdev(mmu)->mutex); + } +} + +static int +nvkm_vm_map_pgt(struct nvkm_vm *vm, u32 pde, u32 type) +{ + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; + struct nvkm_vm_pgd *vpgd; + struct nvkm_gpuobj *pgt; + int big = (type != mmu->spg_shift); + u32 pgt_size; + int ret; + + pgt_size = (1 << (mmu->pgt_bits + 12)) >> type; + pgt_size *= 8; + + mutex_unlock(&nv_subdev(mmu)->mutex); + ret = nvkm_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, &pgt); + mutex_lock(&nv_subdev(mmu)->mutex); + if (unlikely(ret)) + return ret; + + /* someone beat us to filling the PDE while we didn't have the lock */ + if (unlikely(vpgt->refcount[big]++)) { + mutex_unlock(&nv_subdev(mmu)->mutex); + nvkm_gpuobj_ref(NULL, &pgt); + mutex_lock(&nv_subdev(mmu)->mutex); + return 0; + } + + vpgt->obj[big] = pgt; + list_for_each_entry(vpgd, &vm->pgd_list, head) { + mmu->map_pgt(vpgd->obj, pde, vpgt->obj); + } + + return 0; +} + +int +nvkm_vm_get(struct nvkm_vm *vm, u64 size, u32 page_shift, u32 access, + struct nvkm_vma *vma) +{ + struct nvkm_mmu *mmu = vm->mmu; + u32 align = (1 << page_shift) >> 12; + u32 msize = size >> 12; + u32 fpde, lpde, pde; + int ret; + + mutex_lock(&nv_subdev(mmu)->mutex); + ret = nvkm_mm_head(&vm->mm, 0, page_shift, msize, msize, align, + &vma->node); + if (unlikely(ret != 0)) { + mutex_unlock(&nv_subdev(mmu)->mutex); + return ret; + } + + fpde = (vma->node->offset >> mmu->pgt_bits); + lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits; + + for (pde = fpde; pde <= lpde; pde++) { + struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; + int big = (vma->node->type != mmu->spg_shift); + + if (likely(vpgt->refcount[big])) { + vpgt->refcount[big]++; + continue; + } + + ret = nvkm_vm_map_pgt(vm, pde, vma->node->type); + if (ret) { + if (pde != fpde) + nvkm_vm_unmap_pgt(vm, big, fpde, pde - 1); + nvkm_mm_free(&vm->mm, &vma->node); + mutex_unlock(&nv_subdev(mmu)->mutex); + return ret; + } + } + mutex_unlock(&nv_subdev(mmu)->mutex); + + vma->vm = NULL; + nvkm_vm_ref(vm, &vma->vm, NULL); + vma->offset = (u64)vma->node->offset << 12; + vma->access = access; + return 0; +} + +void +nvkm_vm_put(struct nvkm_vma *vma) +{ + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; + u32 fpde, lpde; + + if (unlikely(vma->node == NULL)) + return; + fpde = (vma->node->offset >> mmu->pgt_bits); + lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits; + + mutex_lock(&nv_subdev(mmu)->mutex); + nvkm_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde); + nvkm_mm_free(&vm->mm, &vma->node); + mutex_unlock(&nv_subdev(mmu)->mutex); + + nvkm_vm_ref(NULL, &vma->vm, NULL); +} + +int +nvkm_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset, + u32 block, struct nvkm_vm **pvm) +{ + struct nvkm_vm *vm; + u64 mm_length = (offset + length) - mm_offset; + int ret; + + vm = kzalloc(sizeof(*vm), GFP_KERNEL); + if (!vm) + return -ENOMEM; + + INIT_LIST_HEAD(&vm->pgd_list); + vm->mmu = mmu; + kref_init(&vm->refcount); + vm->fpde = offset >> (mmu->pgt_bits + 12); + vm->lpde = (offset + length - 1) >> (mmu->pgt_bits + 12); + + vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); + if (!vm->pgt) { + kfree(vm); + return -ENOMEM; + } + + ret = nvkm_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, + block >> 12); + if (ret) { + vfree(vm->pgt); + kfree(vm); + return ret; + } + + *pvm = vm; + + return 0; +} + +int +nvkm_vm_new(struct nvkm_device *device, u64 offset, u64 length, u64 mm_offset, + struct nvkm_vm **pvm) +{ + struct nvkm_mmu *mmu = nvkm_mmu(device); + return mmu->create(mmu, offset, length, mm_offset, pvm); +} + +static int +nvkm_vm_link(struct nvkm_vm *vm, struct nvkm_gpuobj *pgd) +{ + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_vm_pgd *vpgd; + int i; + + if (!pgd) + return 0; + + vpgd = kzalloc(sizeof(*vpgd), GFP_KERNEL); + if (!vpgd) + return -ENOMEM; + + nvkm_gpuobj_ref(pgd, &vpgd->obj); + + mutex_lock(&nv_subdev(mmu)->mutex); + for (i = vm->fpde; i <= vm->lpde; i++) + mmu->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj); + list_add(&vpgd->head, &vm->pgd_list); + mutex_unlock(&nv_subdev(mmu)->mutex); + return 0; +} + +static void +nvkm_vm_unlink(struct nvkm_vm *vm, struct nvkm_gpuobj *mpgd) +{ + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_vm_pgd *vpgd, *tmp; + struct nvkm_gpuobj *pgd = NULL; + + if (!mpgd) + return; + + mutex_lock(&nv_subdev(mmu)->mutex); + list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { + if (vpgd->obj == mpgd) { + pgd = vpgd->obj; + list_del(&vpgd->head); + kfree(vpgd); + break; + } + } + mutex_unlock(&nv_subdev(mmu)->mutex); + + nvkm_gpuobj_ref(NULL, &pgd); +} + +static void +nvkm_vm_del(struct kref *kref) +{ + struct nvkm_vm *vm = container_of(kref, typeof(*vm), refcount); + struct nvkm_vm_pgd *vpgd, *tmp; + + list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { + nvkm_vm_unlink(vm, vpgd->obj); + } + + nvkm_mm_fini(&vm->mm); + vfree(vm->pgt); + kfree(vm); +} + +int +nvkm_vm_ref(struct nvkm_vm *ref, struct nvkm_vm **ptr, struct nvkm_gpuobj *pgd) +{ + if (ref) { + int ret = nvkm_vm_link(ref, pgd); + if (ret) + return ret; + + kref_get(&ref->refcount); + } + + if (*ptr) { + nvkm_vm_unlink(*ptr, pgd); + kref_put(&(*ptr)->refcount, nvkm_vm_del); + } + + *ptr = ref; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c index 2d0988755530..294cda37f068 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c @@ -21,25 +21,23 @@ * * Authors: Ben Skeggs */ - -#include <core/device.h> -#include <core/gpuobj.h> - -#include <subdev/timer.h> +#include <subdev/mmu.h> +#include <subdev/bar.h> #include <subdev/fb.h> -#include <subdev/vm.h> #include <subdev/ltc.h> -#include <subdev/bar.h> +#include <subdev/timer.h> -struct nvc0_vmmgr_priv { - struct nouveau_vmmgr base; +#include <core/gpuobj.h> + +struct gf100_mmu_priv { + struct nvkm_mmu base; }; /* Map from compressed to corresponding uncompressed storage type. * The value 0xff represents an invalid storage type. */ -const u8 nvc0_pte_storage_type_map[256] = +const u8 gf100_pte_storage_type_map[256] = { 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */ 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -77,8 +75,7 @@ const u8 nvc0_pte_storage_type_map[256] = static void -nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, - struct nouveau_gpuobj *pgt[2]) +gf100_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 index, struct nvkm_gpuobj *pgt[2]) { u32 pde[2] = { 0, 0 }; @@ -92,7 +89,7 @@ nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, } static inline u64 -nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) +gf100_vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target) { phys >>= 8; @@ -102,22 +99,20 @@ nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) phys |= ((u64)target << 32); phys |= ((u64)memtype << 36); - return phys; } static void -nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) +gf100_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) { u64 next = 1 << (vma->node->type - 8); - phys = nvc0_vm_addr(vma, phys, mem->memtype, 0); + phys = gf100_vm_addr(vma, phys, mem->memtype, 0); pte <<= 3; if (mem->tag) { - struct nouveau_ltc *ltc = - nouveau_ltc(vma->vm->vmm->base.base.parent); + struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu); u32 tag = mem->tag->offset + (delta >> 17); phys |= (u64)tag << (32 + 12); next |= (u64)1 << (32 + 12); @@ -133,16 +128,16 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +gf100_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; /* compressed storage types are invalid for system memory */ - u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff]; + u32 memtype = gf100_pte_storage_type_map[mem->memtype & 0xff]; pte <<= 3; while (cnt--) { - u64 phys = nvc0_vm_addr(vma, *list++, memtype, target); + u64 phys = gf100_vm_addr(vma, *list++, memtype, target); nv_wo32(pgt, pte + 0, lower_32_bits(phys)); nv_wo32(pgt, pte + 4, upper_32_bits(phys)); pte += 8; @@ -150,7 +145,7 @@ nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +gf100_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { pte <<= 3; while (cnt--) { @@ -161,11 +156,11 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nvc0_vm_flush(struct nouveau_vm *vm) +gf100_vm_flush(struct nvkm_vm *vm) { - struct nvc0_vmmgr_priv *priv = (void *)vm->vmm; - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_vm_pgd *vpgd; + struct gf100_mmu_priv *priv = (void *)vm->mmu; + struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_vm_pgd *vpgd; u32 type; bar->flush(bar); @@ -197,21 +192,21 @@ nvc0_vm_flush(struct nouveau_vm *vm) } static int -nvc0_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **pvm) +gf100_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset, + struct nvkm_vm **pvm) { - return nouveau_vm_create(vmm, offset, length, mm_offset, 4096, pvm); + return nvkm_vm_create(mmu, offset, length, mm_offset, 4096, pvm); } static int -nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_vmmgr_priv *priv; + struct gf100_mmu_priv *priv; int ret; - ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -221,22 +216,22 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.pgt_bits = 27 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 17; - priv->base.create = nvc0_vm_create; - priv->base.map_pgt = nvc0_vm_map_pgt; - priv->base.map = nvc0_vm_map; - priv->base.map_sg = nvc0_vm_map_sg; - priv->base.unmap = nvc0_vm_unmap; - priv->base.flush = nvc0_vm_flush; + priv->base.create = gf100_vm_create; + priv->base.map_pgt = gf100_vm_map_pgt; + priv->base.map = gf100_vm_map; + priv->base.map_sg = gf100_vm_map_sg; + priv->base.unmap = gf100_vm_unmap; + priv->base.flush = gf100_vm_flush; return 0; } -struct nouveau_oclass -nvc0_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_vmmgr_ctor, - .dtor = _nouveau_vmmgr_dtor, - .init = _nouveau_vmmgr_init, - .fini = _nouveau_vmmgr_fini, +struct nvkm_oclass +gf100_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_mmu_ctor, + .dtor = _nvkm_mmu_dtor, + .init = _nvkm_mmu_init, + .fini = _nvkm_mmu_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c index ed45437167f2..fe93ea2711c9 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c @@ -21,11 +21,11 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" +#include <core/device.h> #include <core/gpuobj.h> -#include "nv04.h" - #define NV04_PDMA_SIZE (128 * 1024 * 1024) #define NV04_PDMA_PAGE ( 4 * 1024) @@ -34,8 +34,8 @@ ******************************************************************************/ static void -nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { pte = 0x00008 + (pte * 4); while (cnt) { @@ -51,7 +51,7 @@ nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { pte = 0x00008 + (pte * 4); while (cnt--) { @@ -61,7 +61,7 @@ nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nv04_vm_flush(struct nouveau_vm *vm) +nv04_vm_flush(struct nvkm_vm *vm) { } @@ -70,27 +70,27 @@ nv04_vm_flush(struct nouveau_vm *vm) ******************************************************************************/ int -nv04_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, u64 mmstart, - struct nouveau_vm **pvm) +nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart, + struct nvkm_vm **pvm) { return -EINVAL; } /******************************************************************************* - * VMMGR subdev + * MMU subdev ******************************************************************************/ static int -nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv04_vmmgr_priv *priv; - struct nouveau_gpuobj *dma; + struct nv04_mmu_priv *priv; + struct nvkm_gpuobj *dma; int ret; - ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIGART", - "pcigart", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART", + "pcigart", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -105,15 +105,15 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.unmap = nv04_vm_unmap; priv->base.flush = nv04_vm_flush; - ret = nouveau_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, - &priv->vm); + ret = nvkm_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, + &priv->vm); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + - 8, 16, NVOBJ_FLAG_ZERO_ALLOC, - &priv->vm->pgt[0].obj[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, + (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8, + 16, NVOBJ_FLAG_ZERO_ALLOC, + &priv->vm->pgt[0].obj[0]); dma = priv->vm->pgt[0].obj[0]; priv->vm->pgt[0].refcount[0] = 1; if (ret) @@ -125,27 +125,27 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } void -nv04_vmmgr_dtor(struct nouveau_object *object) +nv04_mmu_dtor(struct nvkm_object *object) { - struct nv04_vmmgr_priv *priv = (void *)object; + struct nv04_mmu_priv *priv = (void *)object; if (priv->vm) { - nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); - nouveau_vm_ref(NULL, &priv->vm, NULL); + nvkm_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); + nvkm_vm_ref(NULL, &priv->vm, NULL); } if (priv->nullp) { pci_free_consistent(nv_device(priv)->pdev, 16 * 1024, priv->nullp, priv->null); } - nouveau_vmmgr_destroy(&priv->base); + nvkm_mmu_destroy(&priv->base); } -struct nouveau_oclass -nv04_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv04_vmmgr_ctor, - .dtor = nv04_vmmgr_dtor, - .init = _nouveau_vmmgr_init, - .fini = _nouveau_vmmgr_fini, +struct nvkm_oclass +nv04_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0x04), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv04_mmu_ctor, + .dtor = nv04_mmu_dtor, + .init = _nvkm_mmu_init, + .fini = _nvkm_mmu_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h new file mode 100644 index 000000000000..7bf6f4b38f1d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h @@ -0,0 +1,19 @@ +#ifndef __NV04_MMU_PRIV__ +#define __NV04_MMU_PRIV__ + +#include <subdev/mmu.h> + +struct nv04_mmu_priv { + struct nvkm_mmu base; + struct nvkm_vm *vm; + dma_addr_t null; + void *nullp; +}; + +static inline struct nv04_mmu_priv * +nv04_mmu(void *obj) +{ + return (void *)nvkm_mmu(obj); +} + +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c index 064c76262876..61ee3ab11660 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" +#include <core/device.h> #include <core/gpuobj.h> #include <core/option.h> - #include <subdev/timer.h> -#include <subdev/vm.h> - -#include "nv04.h" #define NV41_GART_SIZE (512 * 1024 * 1024) #define NV41_GART_PAGE ( 4 * 1024) @@ -38,8 +36,8 @@ ******************************************************************************/ static void -nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +nv41_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { pte = pte * 4; while (cnt) { @@ -55,7 +53,7 @@ nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +nv41_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { pte = pte * 4; while (cnt--) { @@ -65,9 +63,9 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nv41_vm_flush(struct nouveau_vm *vm) +nv41_vm_flush(struct nvkm_vm *vm) { - struct nv04_vmmgr_priv *priv = (void *)vm->vmm; + struct nv04_mmu_priv *priv = (void *)vm->mmu; mutex_lock(&nv_subdev(priv)->mutex); nv_wr32(priv, 0x100810, 0x00000022); @@ -80,26 +78,26 @@ nv41_vm_flush(struct nouveau_vm *vm) } /******************************************************************************* - * VMMGR subdev + * MMU subdev ******************************************************************************/ static int -nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); - struct nv04_vmmgr_priv *priv; + struct nvkm_device *device = nv_device(parent); + struct nv04_mmu_priv *priv; int ret; if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || - !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { - return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass, - data, size, pobject); + !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) { + return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass, + data, size, pobject); } - ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART", - "pciegart", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART", + "pciegart", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -114,15 +112,15 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.unmap = nv41_vm_unmap; priv->base.flush = nv41_vm_flush; - ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096, - &priv->vm); + ret = nvkm_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096, + &priv->vm); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (NV41_GART_SIZE / NV41_GART_PAGE) * 4, - 16, NVOBJ_FLAG_ZERO_ALLOC, - &priv->vm->pgt[0].obj[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, + (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &priv->vm->pgt[0].obj[0]); priv->vm->pgt[0].refcount[0] = 1; if (ret) return ret; @@ -131,13 +129,13 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv41_vmmgr_init(struct nouveau_object *object) +nv41_mmu_init(struct nvkm_object *object) { - struct nv04_vmmgr_priv *priv = (void *)object; - struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0]; + struct nv04_mmu_priv *priv = (void *)object; + struct nvkm_gpuobj *dma = priv->vm->pgt[0].obj[0]; int ret; - ret = nouveau_vmmgr_init(&priv->base); + ret = nvkm_mmu_init(&priv->base); if (ret) return ret; @@ -147,13 +145,13 @@ nv41_vmmgr_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass -nv41_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0x41), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv41_vmmgr_ctor, - .dtor = nv04_vmmgr_dtor, - .init = nv41_vmmgr_init, - .fini = _nouveau_vmmgr_fini, +struct nvkm_oclass +nv41_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0x41), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv41_mmu_ctor, + .dtor = nv04_mmu_dtor, + .init = nv41_mmu_init, + .fini = _nvkm_mmu_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c index fae1f67d5948..b90ded1887aa 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" +#include <core/device.h> #include <core/gpuobj.h> #include <core/option.h> - #include <subdev/timer.h> -#include <subdev/vm.h> - -#include "nv04.h" #define NV44_GART_SIZE (512 * 1024 * 1024) #define NV44_GART_PAGE ( 4 * 1024) @@ -38,7 +36,7 @@ ******************************************************************************/ static void -nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, +nv44_vm_fill(struct nvkm_gpuobj *pgt, dma_addr_t null, dma_addr_t *list, u32 pte, u32 cnt) { u32 base = (pte << 2) & ~0x0000000f; @@ -84,10 +82,10 @@ nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, } static void -nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { - struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm; + struct nv04_mmu_priv *priv = (void *)vma->vm->mmu; u32 tmp[4]; int i; @@ -115,9 +113,9 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +nv44_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { - struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt); + struct nv04_mmu_priv *priv = (void *)nvkm_mmu(pgt); if (pte & 3) { u32 max = 4 - (pte & 3); @@ -140,9 +138,9 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nv44_vm_flush(struct nouveau_vm *vm) +nv44_vm_flush(struct nvkm_vm *vm) { - struct nv04_vmmgr_priv *priv = (void *)vm->vmm; + struct nv04_mmu_priv *priv = (void *)vm->mmu; nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE); nv_wr32(priv, 0x100808, 0x00000020); if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001)) @@ -151,26 +149,26 @@ nv44_vm_flush(struct nouveau_vm *vm) } /******************************************************************************* - * VMMGR subdev + * MMU subdev ******************************************************************************/ static int -nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); - struct nv04_vmmgr_priv *priv; + struct nvkm_device *device = nv_device(parent); + struct nv04_mmu_priv *priv; int ret; if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || - !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { - return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass, - data, size, pobject); + !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) { + return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass, + data, size, pobject); } - ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART", - "pciegart", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART", + "pciegart", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -191,15 +189,15 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return -ENOMEM; } - ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096, - &priv->vm); + ret = nvkm_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096, + &priv->vm); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (NV44_GART_SIZE / NV44_GART_PAGE) * 4, - 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC, - &priv->vm->pgt[0].obj[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, + (NV44_GART_SIZE / NV44_GART_PAGE) * 4, + 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC, + &priv->vm->pgt[0].obj[0]); priv->vm->pgt[0].refcount[0] = 1; if (ret) return ret; @@ -208,14 +206,14 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv44_vmmgr_init(struct nouveau_object *object) +nv44_mmu_init(struct nvkm_object *object) { - struct nv04_vmmgr_priv *priv = (void *)object; - struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0]; + struct nv04_mmu_priv *priv = (void *)object; + struct nvkm_gpuobj *gart = priv->vm->pgt[0].obj[0]; u32 addr; int ret; - ret = nouveau_vmmgr_init(&priv->base); + ret = nvkm_mmu_init(&priv->base); if (ret) return ret; @@ -237,13 +235,13 @@ nv44_vmmgr_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass -nv44_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0x44), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv44_vmmgr_ctor, - .dtor = nv04_vmmgr_dtor, - .init = nv44_vmmgr_init, - .fini = _nouveau_vmmgr_fini, +struct nvkm_oclass +nv44_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0x44), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv44_mmu_ctor, + .dtor = nv04_mmu_dtor, + .init = nv44_mmu_init, + .fini = _nvkm_mmu_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index a4aa81a2173b..b83550fa7f96 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -21,22 +21,20 @@ * * Authors: Ben Skeggs */ +#include <subdev/mmu.h> +#include <subdev/bar.h> +#include <subdev/fb.h> +#include <subdev/timer.h> -#include <core/device.h> +#include <core/engine.h> #include <core/gpuobj.h> -#include <subdev/timer.h> -#include <subdev/fb.h> -#include <subdev/bar.h> -#include <subdev/vm.h> - -struct nv50_vmmgr_priv { - struct nouveau_vmmgr base; +struct nv50_mmu_priv { + struct nvkm_mmu base; }; static void -nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, - struct nouveau_gpuobj *pgt[2]) +nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_gpuobj *pgt[2]) { u64 phys = 0xdeadcafe00000000ULL; u32 coverage = 0; @@ -64,7 +62,7 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, } static inline u64 -vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) +vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target) { phys |= 1; /* present */ phys |= (u64)memtype << 40; @@ -77,8 +75,8 @@ vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) } static void -nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) +nv50_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) { u32 comp = (mem->memtype & 0x180) >> 7; u32 block, target; @@ -86,8 +84,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, /* IGPs don't have real VRAM, re-target to stolen system memory */ target = 0; - if (nouveau_fb(vma->vm->vmm)->ram->stolen) { - phys += nouveau_fb(vma->vm->vmm)->ram->stolen; + if (nvkm_fb(vma->vm->mmu)->ram->stolen) { + phys += nvkm_fb(vma->vm->mmu)->ram->stolen; target = 3; } @@ -124,8 +122,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +nv50_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; pte <<= 3; @@ -138,7 +136,7 @@ nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +nv50_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { pte <<= 3; while (cnt--) { @@ -149,11 +147,11 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nv50_vm_flush(struct nouveau_vm *vm) +nv50_vm_flush(struct nvkm_vm *vm) { - struct nv50_vmmgr_priv *priv = (void *)vm->vmm; - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_engine *engine; + struct nv50_mmu_priv *priv = (void *)vm->mmu; + struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_engine *engine; int i, vme; bar->flush(bar); @@ -164,21 +162,24 @@ nv50_vm_flush(struct nouveau_vm *vm) continue; /* unfortunate hw bug workaround... */ - engine = nouveau_engine(priv, i); + engine = nvkm_engine(priv, i); if (engine && engine->tlb_flush) { engine->tlb_flush(engine); continue; } switch (i) { - case NVDEV_ENGINE_GR : vme = 0x00; break; - case NVDEV_ENGINE_VP : vme = 0x01; break; - case NVDEV_SUBDEV_BAR : vme = 0x06; break; - case NVDEV_ENGINE_PPP : - case NVDEV_ENGINE_MPEG : vme = 0x08; break; - case NVDEV_ENGINE_BSP : vme = 0x09; break; - case NVDEV_ENGINE_CRYPT: vme = 0x0a; break; - case NVDEV_ENGINE_COPY0: vme = 0x0d; break; + case NVDEV_ENGINE_GR : vme = 0x00; break; + case NVDEV_ENGINE_VP : + case NVDEV_ENGINE_MSPDEC: vme = 0x01; break; + case NVDEV_SUBDEV_BAR : vme = 0x06; break; + case NVDEV_ENGINE_MSPPP : + case NVDEV_ENGINE_MPEG : vme = 0x08; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : vme = 0x09; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : vme = 0x0a; break; + case NVDEV_ENGINE_CE0 : vme = 0x0d; break; default: continue; } @@ -191,25 +192,25 @@ nv50_vm_flush(struct nouveau_vm *vm) } static int -nv50_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **pvm) +nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, + u64 mm_offset, struct nvkm_vm **pvm) { - u32 block = (1 << (vmm->pgt_bits + 12)); + u32 block = (1 << (mmu->pgt_bits + 12)); if (block > length) block = length; - return nouveau_vm_create(vmm, offset, length, mm_offset, block, pvm); + return nvkm_vm_create(mmu, offset, length, mm_offset, block, pvm); } static int -nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv50_vmmgr_priv *priv; + struct nv50_mmu_priv *priv; int ret; - ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -228,13 +229,13 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass -nv50_vmmgr_oclass = { - .handle = NV_SUBDEV(VM, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv50_vmmgr_ctor, - .dtor = _nouveau_vmmgr_dtor, - .init = _nouveau_vmmgr_init, - .fini = _nouveau_vmmgr_fini, +struct nvkm_oclass +nv50_mmu_oclass = { + .handle = NV_SUBDEV(MMU, 0x50), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_mmu_ctor, + .dtor = _nvkm_mmu_dtor, + .init = _nvkm_mmu_init, + .fini = _nvkm_mmu_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild new file mode 100644 index 000000000000..1a479e050b54 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild @@ -0,0 +1,3 @@ +nvkm-y += nvkm/subdev/mxm/base.o +nvkm-y += nvkm/subdev/mxm/mxms.o +nvkm-y += nvkm/subdev/mxm/nv50.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c index 51fcf7960417..0ca9dcabb6d3 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c @@ -21,18 +21,16 @@ * * Authors: Ben Skeggs */ +#include "mxms.h" +#include <core/device.h> #include <core/option.h> - -#include <subdev/i2c.h> -#include <subdev/mxm.h> #include <subdev/bios.h> #include <subdev/bios/mxm.h> - -#include "mxms.h" +#include <subdev/i2c.h> static bool -mxm_shadow_rom_fetch(struct nouveau_i2c_port *i2c, u8 addr, +mxm_shadow_rom_fetch(struct nvkm_i2c_port *i2c, u8 addr, u8 offset, u8 size, u8 *data) { struct i2c_msg msgs[] = { @@ -44,11 +42,11 @@ mxm_shadow_rom_fetch(struct nouveau_i2c_port *i2c, u8 addr, } static bool -mxm_shadow_rom(struct nouveau_mxm *mxm, u8 version) +mxm_shadow_rom(struct nvkm_mxm *mxm, u8 version) { - struct nouveau_bios *bios = nouveau_bios(mxm); - struct nouveau_i2c *i2c = nouveau_i2c(mxm); - struct nouveau_i2c_port *port = NULL; + struct nvkm_bios *bios = nvkm_bios(mxm); + struct nvkm_i2c *i2c = nvkm_i2c(mxm); + struct nvkm_i2c_port *port = NULL; u8 i2cidx, mxms[6], addr, size; i2cidx = mxm_ddc_map(bios, 1 /* LVDS_DDC */) & 0x0f; @@ -79,9 +77,9 @@ mxm_shadow_rom(struct nouveau_mxm *mxm, u8 version) #if defined(CONFIG_ACPI) static bool -mxm_shadow_dsm(struct nouveau_mxm *mxm, u8 version) +mxm_shadow_dsm(struct nvkm_mxm *mxm, u8 version) { - struct nouveau_device *device = nv_device(mxm); + struct nvkm_device *device = nv_device(mxm); static char muid[] = { 0x00, 0xA4, 0x04, 0x40, 0x7D, 0x91, 0xF2, 0x4C, 0xB8, 0x9C, 0x79, 0xB6, 0x2F, 0xD5, 0x56, 0x65 @@ -129,7 +127,7 @@ mxm_shadow_dsm(struct nouveau_mxm *mxm, u8 version) #define WMI_WMMX_GUID "F6CB5C3C-9CAE-4EBD-B577-931EA32A2CC0" static u8 -wmi_wmmx_mxmi(struct nouveau_mxm *mxm, u8 version) +wmi_wmmx_mxmi(struct nvkm_mxm *mxm, u8 version) { u32 mxmi_args[] = { 0x494D584D /* MXMI */, version, 0 }; struct acpi_buffer args = { sizeof(mxmi_args), mxmi_args }; @@ -158,7 +156,7 @@ wmi_wmmx_mxmi(struct nouveau_mxm *mxm, u8 version) } static bool -mxm_shadow_wmi(struct nouveau_mxm *mxm, u8 version) +mxm_shadow_wmi(struct nvkm_mxm *mxm, u8 version) { u32 mxms_args[] = { 0x534D584D /* MXMS */, version, 0 }; struct acpi_buffer args = { sizeof(mxms_args), mxms_args }; @@ -186,7 +184,7 @@ mxm_shadow_wmi(struct nouveau_mxm *mxm, u8 version) obj = retn.pointer; if (obj->type == ACPI_TYPE_BUFFER) { mxm->mxms = kmemdup(obj->buffer.pointer, - obj->buffer.length, GFP_KERNEL); + obj->buffer.length, GFP_KERNEL); } kfree(obj); @@ -196,7 +194,7 @@ mxm_shadow_wmi(struct nouveau_mxm *mxm, u8 version) static struct mxm_shadow_h { const char *name; - bool (*exec)(struct nouveau_mxm *, u8 version); + bool (*exec)(struct nvkm_mxm *, u8 version); } _mxm_shadow[] = { { "ROM", mxm_shadow_rom }, #if defined(CONFIG_ACPI) @@ -209,7 +207,7 @@ static struct mxm_shadow_h { }; static int -mxm_shadow(struct nouveau_mxm *mxm, u8 version) +mxm_shadow(struct nvkm_mxm *mxm, u8 version) { struct mxm_shadow_h *shadow = _mxm_shadow; do { @@ -225,19 +223,18 @@ mxm_shadow(struct nouveau_mxm *mxm, u8 version) } int -nouveau_mxm_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) +nvkm_mxm_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_device *device = nv_device(parent); - struct nouveau_bios *bios = nouveau_bios(device); - struct nouveau_mxm *mxm; + struct nvkm_device *device = nv_device(parent); + struct nvkm_bios *bios = nvkm_bios(device); + struct nvkm_mxm *mxm; u8 ver, len; u16 data; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "MXM", "mxm", - length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "MXM", "mxm", + length, pobject); mxm = *pobject; if (ret) return ret; @@ -268,7 +265,7 @@ nouveau_mxm_create_(struct nouveau_object *parent, mxms_version(mxm) >> 8, mxms_version(mxm) & 0xff); mxms_foreach(mxm, 0, NULL, NULL); - if (nouveau_boolopt(device->cfgopt, "NvMXMDCB", true)) + if (nvkm_boolopt(device->cfgopt, "NvMXMDCB", true)) mxm->action |= MXM_SANITISE_DCB; return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c index 4bde7f7f7b81..a9b1d63fed58 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c @@ -21,22 +21,20 @@ * * Authors: Ben Skeggs */ - -#include <subdev/mxm.h> #include "mxms.h" #define ROM16(x) le16_to_cpu(*(u16 *)&(x)) #define ROM32(x) le32_to_cpu(*(u32 *)&(x)) static u8 * -mxms_data(struct nouveau_mxm *mxm) +mxms_data(struct nvkm_mxm *mxm) { return mxm->mxms; } u16 -mxms_version(struct nouveau_mxm *mxm) +mxms_version(struct nvkm_mxm *mxm) { u8 *mxms = mxms_data(mxm); u16 version = (mxms[4] << 8) | mxms[5]; @@ -54,19 +52,19 @@ mxms_version(struct nouveau_mxm *mxm) } u16 -mxms_headerlen(struct nouveau_mxm *mxm) +mxms_headerlen(struct nvkm_mxm *mxm) { return 8; } u16 -mxms_structlen(struct nouveau_mxm *mxm) +mxms_structlen(struct nvkm_mxm *mxm) { return *(u16 *)&mxms_data(mxm)[6]; } bool -mxms_checksum(struct nouveau_mxm *mxm) +mxms_checksum(struct nvkm_mxm *mxm) { u16 size = mxms_headerlen(mxm) + mxms_structlen(mxm); u8 *mxms = mxms_data(mxm), sum = 0; @@ -80,7 +78,7 @@ mxms_checksum(struct nouveau_mxm *mxm) } bool -mxms_valid(struct nouveau_mxm *mxm) +mxms_valid(struct nvkm_mxm *mxm) { u8 *mxms = mxms_data(mxm); if (*(u32 *)mxms != 0x5f4d584d) { @@ -95,8 +93,8 @@ mxms_valid(struct nouveau_mxm *mxm) } bool -mxms_foreach(struct nouveau_mxm *mxm, u8 types, - bool (*exec)(struct nouveau_mxm *, u8 *, void *), void *info) +mxms_foreach(struct nvkm_mxm *mxm, u8 types, + bool (*exec)(struct nvkm_mxm *, u8 *, void *), void *info) { u8 *mxms = mxms_data(mxm); u8 *desc = mxms + mxms_headerlen(mxm); @@ -180,7 +178,7 @@ mxms_foreach(struct nouveau_mxm *mxm, u8 types, } void -mxms_output_device(struct nouveau_mxm *mxm, u8 *pdata, struct mxms_odev *desc) +mxms_output_device(struct nvkm_mxm *mxm, u8 *pdata, struct mxms_odev *desc) { u64 data = ROM32(pdata[0]); if (mxms_version(mxm) >= 0x0300) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h new file mode 100644 index 000000000000..4ef804012d06 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h @@ -0,0 +1,22 @@ +#ifndef __NVMXM_MXMS_H__ +#define __NVMXM_MXMS_H__ +#include <subdev/mxm.h> + +struct mxms_odev { + u8 outp_type; + u8 conn_type; + u8 ddc_port; + u8 dig_conn; +}; + +void mxms_output_device(struct nvkm_mxm *, u8 *, struct mxms_odev *); + +u16 mxms_version(struct nvkm_mxm *); +u16 mxms_headerlen(struct nvkm_mxm *); +u16 mxms_structlen(struct nvkm_mxm *); +bool mxms_checksum(struct nvkm_mxm *); +bool mxms_valid(struct nvkm_mxm *); + +bool mxms_foreach(struct nvkm_mxm *, u8, + bool (*)(struct nvkm_mxm *, u8 *, void *), void *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c index fcaabe8456e3..42cac13ca629 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c @@ -21,17 +21,15 @@ * * Authors: Ben Skeggs */ +#include "mxms.h" -#include <subdev/mxm.h> #include <subdev/bios.h> #include <subdev/bios/conn.h> #include <subdev/bios/dcb.h> #include <subdev/bios/mxm.h> -#include "mxms.h" - struct nv50_mxm_priv { - struct nouveau_mxm base; + struct nvkm_mxm base; }; struct context { @@ -40,7 +38,7 @@ struct context { }; static bool -mxm_match_tmds_partner(struct nouveau_mxm *mxm, u8 *data, void *info) +mxm_match_tmds_partner(struct nvkm_mxm *mxm, u8 *data, void *info) { struct context *ctx = info; struct mxms_odev desc; @@ -53,9 +51,9 @@ mxm_match_tmds_partner(struct nouveau_mxm *mxm, u8 *data, void *info) } static bool -mxm_match_dcb(struct nouveau_mxm *mxm, u8 *data, void *info) +mxm_match_dcb(struct nvkm_mxm *mxm, u8 *data, void *info) { - struct nouveau_bios *bios = nouveau_bios(mxm); + struct nvkm_bios *bios = nvkm_bios(mxm); struct context *ctx = info; u64 desc = *(u64 *)data; @@ -98,9 +96,9 @@ mxm_match_dcb(struct nouveau_mxm *mxm, u8 *data, void *info) } static int -mxm_dcb_sanitise_entry(struct nouveau_bios *bios, void *data, int idx, u16 pdcb) +mxm_dcb_sanitise_entry(struct nvkm_bios *bios, void *data, int idx, u16 pdcb) { - struct nouveau_mxm *mxm = data; + struct nvkm_mxm *mxm = data; struct context ctx = { .outp = (u32 *)(bios->data + pdcb) }; u8 type, i2cidx, link, ver, len; u8 *conn; @@ -180,7 +178,7 @@ mxm_dcb_sanitise_entry(struct nouveau_bios *bios, void *data, int idx, u16 pdcb) } static bool -mxm_show_unmatched(struct nouveau_mxm *mxm, u8 *data, void *info) +mxm_show_unmatched(struct nvkm_mxm *mxm, u8 *data, void *info) { u64 desc = *(u64 *)data; if ((desc & 0xf0) != 0xf0) @@ -189,9 +187,9 @@ mxm_show_unmatched(struct nouveau_mxm *mxm, u8 *data, void *info) } static void -mxm_dcb_sanitise(struct nouveau_mxm *mxm) +mxm_dcb_sanitise(struct nvkm_mxm *mxm) { - struct nouveau_bios *bios = nouveau_bios(mxm); + struct nvkm_bios *bios = nvkm_bios(mxm); u8 ver, hdr, cnt, len; u16 dcb = dcb_table(bios, &ver, &hdr, &cnt, &len); if (dcb == 0x0000 || ver != 0x40) { @@ -204,14 +202,14 @@ mxm_dcb_sanitise(struct nouveau_mxm *mxm) } static int -nv50_mxm_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_mxm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_mxm_priv *priv; int ret; - ret = nouveau_mxm_create(parent, engine, oclass, &priv); + ret = nvkm_mxm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -221,13 +219,13 @@ nv50_mxm_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv50_mxm_oclass = { .handle = NV_SUBDEV(MXM, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_mxm_ctor, - .dtor = _nouveau_mxm_dtor, - .init = _nouveau_mxm_init, - .fini = _nouveau_mxm_fini, + .dtor = _nvkm_mxm_dtor, + .init = _nvkm_mxm_init, + .fini = _nvkm_mxm_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild new file mode 100644 index 000000000000..9a150d520225 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild @@ -0,0 +1,8 @@ +nvkm-y += nvkm/subdev/pmu/base.o +nvkm-y += nvkm/subdev/pmu/memx.o +nvkm-y += nvkm/subdev/pmu/gt215.o +nvkm-y += nvkm/subdev/pmu/gf100.o +nvkm-y += nvkm/subdev/pmu/gf110.o +nvkm-y += nvkm/subdev/pmu/gk104.o +nvkm-y += nvkm/subdev/pmu/gk208.o +nvkm-y += nvkm/subdev/pmu/gk20a.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c new file mode 100644 index 000000000000..054b2d2eec35 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -0,0 +1,268 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include <subdev/timer.h> + +void +nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) +{ + const struct nvkm_pmu_impl *impl = (void *)nv_oclass(pmu); + if (impl->pgob) + impl->pgob(pmu, enable); +} + +static int +nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], + u32 process, u32 message, u32 data0, u32 data1) +{ + struct nvkm_subdev *subdev = nv_subdev(pmu); + u32 addr; + + /* wait for a free slot in the fifo */ + addr = nv_rd32(pmu, 0x10a4a0); + if (!nv_wait_ne(pmu, 0x10a4b0, 0xffffffff, addr ^ 8)) + return -EBUSY; + + /* we currently only support a single process at a time waiting + * on a synchronous reply, take the PMU mutex and tell the + * receive handler what we're waiting for + */ + if (reply) { + mutex_lock(&subdev->mutex); + pmu->recv.message = message; + pmu->recv.process = process; + } + + /* acquire data segment access */ + do { + nv_wr32(pmu, 0x10a580, 0x00000001); + } while (nv_rd32(pmu, 0x10a580) != 0x00000001); + + /* write the packet */ + nv_wr32(pmu, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) + + pmu->send.base)); + nv_wr32(pmu, 0x10a1c4, process); + nv_wr32(pmu, 0x10a1c4, message); + nv_wr32(pmu, 0x10a1c4, data0); + nv_wr32(pmu, 0x10a1c4, data1); + nv_wr32(pmu, 0x10a4a0, (addr + 1) & 0x0f); + + /* release data segment access */ + nv_wr32(pmu, 0x10a580, 0x00000000); + + /* wait for reply, if requested */ + if (reply) { + wait_event(pmu->recv.wait, (pmu->recv.process == 0)); + reply[0] = pmu->recv.data[0]; + reply[1] = pmu->recv.data[1]; + mutex_unlock(&subdev->mutex); + } + + return 0; +} + +static void +nvkm_pmu_recv(struct work_struct *work) +{ + struct nvkm_pmu *pmu = container_of(work, struct nvkm_pmu, recv.work); + u32 process, message, data0, data1; + + /* nothing to do if GET == PUT */ + u32 addr = nv_rd32(pmu, 0x10a4cc); + if (addr == nv_rd32(pmu, 0x10a4c8)) + return; + + /* acquire data segment access */ + do { + nv_wr32(pmu, 0x10a580, 0x00000002); + } while (nv_rd32(pmu, 0x10a580) != 0x00000002); + + /* read the packet */ + nv_wr32(pmu, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) + + pmu->recv.base)); + process = nv_rd32(pmu, 0x10a1c4); + message = nv_rd32(pmu, 0x10a1c4); + data0 = nv_rd32(pmu, 0x10a1c4); + data1 = nv_rd32(pmu, 0x10a1c4); + nv_wr32(pmu, 0x10a4cc, (addr + 1) & 0x0f); + + /* release data segment access */ + nv_wr32(pmu, 0x10a580, 0x00000000); + + /* wake process if it's waiting on a synchronous reply */ + if (pmu->recv.process) { + if (process == pmu->recv.process && + message == pmu->recv.message) { + pmu->recv.data[0] = data0; + pmu->recv.data[1] = data1; + pmu->recv.process = 0; + wake_up(&pmu->recv.wait); + return; + } + } + + /* right now there's no other expected responses from the engine, + * so assume that any unexpected message is an error. + */ + nv_warn(pmu, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n", + (char)((process & 0x000000ff) >> 0), + (char)((process & 0x0000ff00) >> 8), + (char)((process & 0x00ff0000) >> 16), + (char)((process & 0xff000000) >> 24), + process, message, data0, data1); +} + +static void +nvkm_pmu_intr(struct nvkm_subdev *subdev) +{ + struct nvkm_pmu *pmu = (void *)subdev; + u32 disp = nv_rd32(pmu, 0x10a01c); + u32 intr = nv_rd32(pmu, 0x10a008) & disp & ~(disp >> 16); + + if (intr & 0x00000020) { + u32 stat = nv_rd32(pmu, 0x10a16c); + if (stat & 0x80000000) { + nv_error(pmu, "UAS fault at 0x%06x addr 0x%08x\n", + stat & 0x00ffffff, nv_rd32(pmu, 0x10a168)); + nv_wr32(pmu, 0x10a16c, 0x00000000); + intr &= ~0x00000020; + } + } + + if (intr & 0x00000040) { + schedule_work(&pmu->recv.work); + nv_wr32(pmu, 0x10a004, 0x00000040); + intr &= ~0x00000040; + } + + if (intr & 0x00000080) { + nv_info(pmu, "wr32 0x%06x 0x%08x\n", nv_rd32(pmu, 0x10a7a0), + nv_rd32(pmu, 0x10a7a4)); + nv_wr32(pmu, 0x10a004, 0x00000080); + intr &= ~0x00000080; + } + + if (intr) { + nv_error(pmu, "intr 0x%08x\n", intr); + nv_wr32(pmu, 0x10a004, intr); + } +} + +int +_nvkm_pmu_fini(struct nvkm_object *object, bool suspend) +{ + struct nvkm_pmu *pmu = (void *)object; + + nv_wr32(pmu, 0x10a014, 0x00000060); + flush_work(&pmu->recv.work); + + return nvkm_subdev_fini(&pmu->base, suspend); +} + +int +_nvkm_pmu_init(struct nvkm_object *object) +{ + const struct nvkm_pmu_impl *impl = (void *)object->oclass; + struct nvkm_pmu *pmu = (void *)object; + int ret, i; + + ret = nvkm_subdev_init(&pmu->base); + if (ret) + return ret; + + nv_subdev(pmu)->intr = nvkm_pmu_intr; + pmu->message = nvkm_pmu_send; + pmu->pgob = nvkm_pmu_pgob; + + /* prevent previous ucode from running, wait for idle, reset */ + nv_wr32(pmu, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */ + nv_wait(pmu, 0x10a04c, 0xffffffff, 0x00000000); + nv_mask(pmu, 0x000200, 0x00002000, 0x00000000); + nv_mask(pmu, 0x000200, 0x00002000, 0x00002000); + nv_rd32(pmu, 0x000200); + nv_wait(pmu, 0x10a10c, 0x00000006, 0x00000000); + + /* upload data segment */ + nv_wr32(pmu, 0x10a1c0, 0x01000000); + for (i = 0; i < impl->data.size / 4; i++) + nv_wr32(pmu, 0x10a1c4, impl->data.data[i]); + + /* upload code segment */ + nv_wr32(pmu, 0x10a180, 0x01000000); + for (i = 0; i < impl->code.size / 4; i++) { + if ((i & 0x3f) == 0) + nv_wr32(pmu, 0x10a188, i >> 6); + nv_wr32(pmu, 0x10a184, impl->code.data[i]); + } + + /* start it running */ + nv_wr32(pmu, 0x10a10c, 0x00000000); + nv_wr32(pmu, 0x10a104, 0x00000000); + nv_wr32(pmu, 0x10a100, 0x00000002); + + /* wait for valid host->pmu ring configuration */ + if (!nv_wait_ne(pmu, 0x10a4d0, 0xffffffff, 0x00000000)) + return -EBUSY; + pmu->send.base = nv_rd32(pmu, 0x10a4d0) & 0x0000ffff; + pmu->send.size = nv_rd32(pmu, 0x10a4d0) >> 16; + + /* wait for valid pmu->host ring configuration */ + if (!nv_wait_ne(pmu, 0x10a4dc, 0xffffffff, 0x00000000)) + return -EBUSY; + pmu->recv.base = nv_rd32(pmu, 0x10a4dc) & 0x0000ffff; + pmu->recv.size = nv_rd32(pmu, 0x10a4dc) >> 16; + + nv_wr32(pmu, 0x10a010, 0x000000e0); + return 0; +} + +int +nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) +{ + struct nvkm_pmu *pmu; + int ret; + + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU", + "pmu", length, pobject); + pmu = *pobject; + if (ret) + return ret; + + INIT_WORK(&pmu->recv.work, nvkm_pmu_recv); + init_waitqueue_head(&pmu->recv.wait); + return 0; +} + +int +_nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_pmu *pmu; + int ret = nvkm_pmu_create(parent, engine, oclass, &pmu); + *pobject = nv_object(pmu); + return ret; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/arith.fuc index 214a6d9e088d..214a6d9e088d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/arith.fuc diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3 index 21bf8cc7618f..37e8407b7462 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3 @@ -32,7 +32,7 @@ #include "macros.fuc" -.section #nvc0_pwr_data +.section #gf100_pmu_data #define INCLUDE_PROC #include "kernel.fuc" #include "arith.fuc" @@ -56,7 +56,7 @@ #undef INCLUDE_DATA .align 256 -.section #nvc0_pwr_code +.section #gf100_pmu_code #define INCLUDE_CODE #include "kernel.fuc" #include "arith.fuc" diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h index 90221d973f84..302557c52d03 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nvc0_pwr_data[] = { +uint32_t gf100_pmu_data[] = { /* 0x0000: proc_kern */ 0x52544e49, 0x00000000, @@ -916,7 +916,7 @@ uint32_t nvc0_pwr_data[] = { 0x00000000, }; -uint32_t nvc0_pwr_code[] = { +uint32_t gf100_pmu_code[] = { 0x039e0ef5, /* 0x0004: rd32 */ 0x07a007f1, diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4 index b85443261569..ae9c3f18ae01 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4 @@ -32,7 +32,7 @@ #include "macros.fuc" -.section #nvd0_pwr_data +.section #gf110_pmu_data #define INCLUDE_PROC #include "kernel.fuc" #include "arith.fuc" @@ -56,7 +56,7 @@ #undef INCLUDE_DATA .align 256 -.section #nvd0_pwr_code +.section #gf110_pmu_code #define INCLUDE_CODE #include "kernel.fuc" #include "arith.fuc" diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h index 7e16aab44d85..a0c499e4543c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h @@ -1,4 +1,4 @@ -uint32_t nvd0_pwr_data[] = { +uint32_t gf110_pmu_data[] = { /* 0x0000: proc_kern */ 0x52544e49, 0x00000000, @@ -915,7 +915,7 @@ uint32_t nvd0_pwr_data[] = { 0x00000000, }; -uint32_t nvd0_pwr_code[] = { +uint32_t gf110_pmu_code[] = { 0x034d0ef5, /* 0x0004: rd32 */ 0x07a007f1, diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5 index b439519ec866..093dc81880f4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5 @@ -32,7 +32,7 @@ #include "macros.fuc" -.section #nv108_pwr_data +.section #gk208_pmu_data #define INCLUDE_PROC #include "kernel.fuc" #include "arith.fuc" @@ -56,7 +56,7 @@ #undef INCLUDE_DATA .align 256 -.section #nv108_pwr_code +.section #gk208_pmu_code #define INCLUDE_CODE #include "kernel.fuc" #include "arith.fuc" diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h index 713e11e2953d..fe4f63deeaab 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h @@ -1,4 +1,4 @@ -uint32_t nv108_pwr_data[] = { +uint32_t gk208_pmu_data[] = { /* 0x0000: proc_kern */ 0x52544e49, 0x00000000, @@ -915,7 +915,7 @@ uint32_t nv108_pwr_data[] = { 0x00000000, }; -uint32_t nv108_pwr_code[] = { +uint32_t gk208_pmu_code[] = { 0x031c0ef5, /* 0x0004: rd32 */ 0xf607a040, diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3 index daa06c1c655e..393049fc8b2d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3 @@ -32,7 +32,7 @@ #include "macros.fuc" -.section #nva3_pwr_data +.section #gt215_pmu_data #define INCLUDE_PROC #include "kernel.fuc" #include "arith.fuc" @@ -56,7 +56,7 @@ #undef INCLUDE_DATA .align 256 -.section #nva3_pwr_code +.section #gt215_pmu_code #define INCLUDE_CODE #include "kernel.fuc" #include "arith.fuc" diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h index d1f9b6cb66d7..2686f8fad0f5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nva3_pwr_data[] = { +uint32_t gt215_pmu_data[] = { /* 0x0000: proc_kern */ 0x52544e49, 0x00000000, @@ -916,7 +916,7 @@ uint32_t nva3_pwr_data[] = { 0x00000000, }; -uint32_t nva3_pwr_code[] = { +uint32_t gt215_pmu_code[] = { 0x039e0ef5, /* 0x0004: rd32 */ 0x07a007f1, diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/host.fuc index c2bb616a8da5..c2bb616a8da5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/host.fuc diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/i2c_.fuc index 757dda700024..757dda700024 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/i2c_.fuc diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/idle.fuc index 98f1c3738b42..98f1c3738b42 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/idle.fuc diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/kernel.fuc index 5cf5be63cbef..5cf5be63cbef 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/kernel.fuc diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc index 96fc984dafdc..96fc984dafdc 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc index ec03f9a4290b..ec03f9a4290b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h index c8b06cb77e72..c8b06cb77e72 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/perf.fuc index 38eadf705cbf..38eadf705cbf 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/perf.fuc diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/test.fuc index 0c3a71bf5459..0c3a71bf5459 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/test.fuc diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c index 9a773e66efa4..78a4ea0101f1 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c @@ -21,21 +21,20 @@ * * Authors: Ben Skeggs */ - #include "priv.h" -#include "fuc/nvc0.fuc.h" +#include "fuc/gf100.fuc3.h" -struct nouveau_oclass * -nvc0_pwr_oclass = &(struct nvkm_pwr_impl) { - .base.handle = NV_SUBDEV(PWR, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_pwr_ctor, - .dtor = _nouveau_pwr_dtor, - .init = _nouveau_pwr_init, - .fini = _nouveau_pwr_fini, +struct nvkm_oclass * +gf100_pmu_oclass = &(struct nvkm_pmu_impl) { + .base.handle = NV_SUBDEV(PMU, 0xc0), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_pmu_ctor, + .dtor = _nvkm_pmu_dtor, + .init = _nvkm_pmu_init, + .fini = _nvkm_pmu_fini, }, - .code.data = nvc0_pwr_code, - .code.size = sizeof(nvc0_pwr_code), - .data.data = nvc0_pwr_data, - .data.size = sizeof(nvc0_pwr_data), + .code.data = gf100_pmu_code, + .code.size = sizeof(gf100_pmu_code), + .data.data = gf100_pmu_data, + .data.size = sizeof(gf100_pmu_data), }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c index 2b29be5d08ac..6b3a23839ff0 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c @@ -21,21 +21,20 @@ * * Authors: Ben Skeggs */ - #include "priv.h" -#include "fuc/nvd0.fuc.h" +#include "fuc/gf110.fuc4.h" -struct nouveau_oclass * -nvd0_pwr_oclass = &(struct nvkm_pwr_impl) { - .base.handle = NV_SUBDEV(PWR, 0xd0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_pwr_ctor, - .dtor = _nouveau_pwr_dtor, - .init = _nouveau_pwr_init, - .fini = _nouveau_pwr_fini, +struct nvkm_oclass * +gf110_pmu_oclass = &(struct nvkm_pmu_impl) { + .base.handle = NV_SUBDEV(PMU, 0xd0), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_pmu_ctor, + .dtor = _nvkm_pmu_dtor, + .init = _nvkm_pmu_init, + .fini = _nvkm_pmu_fini, }, - .code.data = nvd0_pwr_code, - .code.size = sizeof(nvd0_pwr_code), - .data.data = nvd0_pwr_data, - .data.size = sizeof(nvd0_pwr_data), + .code.data = gf110_pmu_code, + .code.size = sizeof(gf110_pmu_code), + .data.data = gf110_pmu_data, + .data.size = sizeof(gf110_pmu_data), }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c index d76612999b9f..28fdb8ea9ed8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c @@ -21,49 +21,47 @@ * * Authors: Ben Skeggs */ - +#define gf110_pmu_code gk104_pmu_code +#define gf110_pmu_data gk104_pmu_data #include "priv.h" - -#define nvd0_pwr_code gk104_pwr_code -#define nvd0_pwr_data gk104_pwr_data -#include "fuc/nvd0.fuc.h" +#include "fuc/gf110.fuc4.h" static void -gk104_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) +gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable) { - nv_mask(ppwr, 0x000200, 0x00001000, 0x00000000); - nv_rd32(ppwr, 0x000200); - nv_mask(ppwr, 0x000200, 0x08000000, 0x08000000); + nv_mask(pmu, 0x000200, 0x00001000, 0x00000000); + nv_rd32(pmu, 0x000200); + nv_mask(pmu, 0x000200, 0x08000000, 0x08000000); msleep(50); - nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000002); - nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001); - nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000); + nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002); + nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001); + nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000); - nv_mask(ppwr, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000); + nv_mask(pmu, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000); msleep(50); - nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000000); - nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001); - nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000); + nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000); + nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001); + nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000); - nv_mask(ppwr, 0x000200, 0x08000000, 0x00000000); - nv_mask(ppwr, 0x000200, 0x00001000, 0x00001000); - nv_rd32(ppwr, 0x000200); + nv_mask(pmu, 0x000200, 0x08000000, 0x00000000); + nv_mask(pmu, 0x000200, 0x00001000, 0x00001000); + nv_rd32(pmu, 0x000200); } -struct nouveau_oclass * -gk104_pwr_oclass = &(struct nvkm_pwr_impl) { - .base.handle = NV_SUBDEV(PWR, 0xe4), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_pwr_ctor, - .dtor = _nouveau_pwr_dtor, - .init = _nouveau_pwr_init, - .fini = _nouveau_pwr_fini, +struct nvkm_oclass * +gk104_pmu_oclass = &(struct nvkm_pmu_impl) { + .base.handle = NV_SUBDEV(PMU, 0xe4), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_pmu_ctor, + .dtor = _nvkm_pmu_dtor, + .init = _nvkm_pmu_init, + .fini = _nvkm_pmu_fini, }, - .code.data = gk104_pwr_code, - .code.size = sizeof(gk104_pwr_code), - .data.data = gk104_pwr_data, - .data.size = sizeof(gk104_pwr_data), - .pgob = gk104_pwr_pgob, + .code.data = gk104_pmu_code, + .code.size = sizeof(gk104_pmu_code), + .data.data = gk104_pmu_data, + .data.size = sizeof(gk104_pmu_data), + .pgob = gk104_pmu_pgob, }.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c index 04ff7c3c34e9..6f9c09af1a49 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c @@ -21,21 +21,20 @@ * * Authors: Ben Skeggs */ - #include "priv.h" -#include "fuc/nv108.fuc.h" +#include "fuc/gk208.fuc5.h" -struct nouveau_oclass * -nv108_pwr_oclass = &(struct nvkm_pwr_impl) { - .base.handle = NV_SUBDEV(PWR, 0x00), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_pwr_ctor, - .dtor = _nouveau_pwr_dtor, - .init = _nouveau_pwr_init, - .fini = _nouveau_pwr_fini, +struct nvkm_oclass * +gk208_pmu_oclass = &(struct nvkm_pmu_impl) { + .base.handle = NV_SUBDEV(PMU, 0x00), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_pmu_ctor, + .dtor = _nvkm_pmu_dtor, + .init = _nvkm_pmu_init, + .fini = _nvkm_pmu_fini, }, - .code.data = nv108_pwr_code, - .code.size = sizeof(nv108_pwr_code), - .data.data = nv108_pwr_data, - .data.size = sizeof(nv108_pwr_data), + .code.data = gk208_pmu_code, + .code.size = sizeof(gk208_pmu_code), + .data.data = gk208_pmu_data, + .data.size = sizeof(gk208_pmu_data), }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c new file mode 100644 index 000000000000..a49934bbe637 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include <subdev/clk.h> +#include <subdev/timer.h> +#include <subdev/volt.h> + +#define BUSY_SLOT 0 +#define CLK_SLOT 7 + +struct gk20a_pmu_dvfs_data { + int p_load_target; + int p_load_max; + int p_smooth; + unsigned int avg_load; +}; + +struct gk20a_pmu_priv { + struct nvkm_pmu base; + struct nvkm_alarm alarm; + struct gk20a_pmu_dvfs_data *data; +}; + +struct gk20a_pmu_dvfs_dev_status { + unsigned long total; + unsigned long busy; + int cur_state; +}; + +static int +gk20a_pmu_dvfs_target(struct gk20a_pmu_priv *priv, int *state) +{ + struct nvkm_clk *clk = nvkm_clk(priv); + + return nvkm_clk_astate(clk, *state, 0, false); +} + +static int +gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu_priv *priv, int *state) +{ + struct nvkm_clk *clk = nvkm_clk(priv); + + *state = clk->pstate; + return 0; +} + +static int +gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu_priv *priv, + int *state, int load) +{ + struct gk20a_pmu_dvfs_data *data = priv->data; + struct nvkm_clk *clk = nvkm_clk(priv); + int cur_level, level; + + /* For GK20A, the performance level is directly mapped to pstate */ + level = cur_level = clk->pstate; + + if (load > data->p_load_max) { + level = min(clk->state_nr - 1, level + (clk->state_nr / 3)); + } else { + level += ((load - data->p_load_target) * 10 / + data->p_load_target) / 2; + level = max(0, level); + level = min(clk->state_nr - 1, level); + } + + nv_trace(priv, "cur level = %d, new level = %d\n", cur_level, level); + + *state = level; + + if (level == cur_level) + return 0; + else + return 1; +} + +static int +gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu_priv *priv, + struct gk20a_pmu_dvfs_dev_status *status) +{ + status->busy = nv_rd32(priv, 0x10a508 + (BUSY_SLOT * 0x10)); + status->total= nv_rd32(priv, 0x10a508 + (CLK_SLOT * 0x10)); + return 0; +} + +static void +gk20a_pmu_dvfs_reset_dev_status(struct gk20a_pmu_priv *priv) +{ + nv_wr32(priv, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000); + nv_wr32(priv, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000); +} + +static void +gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm) +{ + struct gk20a_pmu_priv *priv = + container_of(alarm, struct gk20a_pmu_priv, alarm); + struct gk20a_pmu_dvfs_data *data = priv->data; + struct gk20a_pmu_dvfs_dev_status status; + struct nvkm_clk *clk = nvkm_clk(priv); + struct nvkm_volt *volt = nvkm_volt(priv); + u32 utilization = 0; + int state, ret; + + /* + * The PMU is initialized before CLK and VOLT, so we have to make sure the + * CLK and VOLT are ready here. + */ + if (!clk || !volt) + goto resched; + + ret = gk20a_pmu_dvfs_get_dev_status(priv, &status); + if (ret) { + nv_warn(priv, "failed to get device status\n"); + goto resched; + } + + if (status.total) + utilization = div_u64((u64)status.busy * 100, status.total); + + data->avg_load = (data->p_smooth * data->avg_load) + utilization; + data->avg_load /= data->p_smooth + 1; + nv_trace(priv, "utilization = %d %%, avg_load = %d %%\n", + utilization, data->avg_load); + + ret = gk20a_pmu_dvfs_get_cur_state(priv, &state); + if (ret) { + nv_warn(priv, "failed to get current state\n"); + goto resched; + } + + if (gk20a_pmu_dvfs_get_target_state(priv, &state, data->avg_load)) { + nv_trace(priv, "set new state to %d\n", state); + gk20a_pmu_dvfs_target(priv, &state); + } + +resched: + gk20a_pmu_dvfs_reset_dev_status(priv); + nvkm_timer_alarm(priv, 100000000, alarm); +} + +int +gk20a_pmu_fini(struct nvkm_object *object, bool suspend) +{ + struct nvkm_pmu *pmu = (void *)object; + struct gk20a_pmu_priv *priv = (void *)pmu; + + nvkm_timer_alarm_cancel(priv, &priv->alarm); + + return nvkm_subdev_fini(&pmu->base, suspend); +} + +int +gk20a_pmu_init(struct nvkm_object *object) +{ + struct nvkm_pmu *pmu = (void *)object; + struct gk20a_pmu_priv *priv = (void *)pmu; + int ret; + + ret = nvkm_subdev_init(&pmu->base); + if (ret) + return ret; + + pmu->pgob = nvkm_pmu_pgob; + + /* init pwr perf counter */ + nv_wr32(pmu, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); + nv_wr32(pmu, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); + nv_wr32(pmu, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); + + nvkm_timer_alarm(pmu, 2000000000, &priv->alarm); + return ret; +} + +struct gk20a_pmu_dvfs_data gk20a_dvfs_data= { + .p_load_target = 70, + .p_load_max = 90, + .p_smooth = 1, +}; + +static int +gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gk20a_pmu_priv *priv; + int ret; + + ret = nvkm_pmu_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv->data = &gk20a_dvfs_data; + + nvkm_alarm_init(&priv->alarm, gk20a_pmu_dvfs_work); + return 0; +} + +struct nvkm_oclass * +gk20a_pmu_oclass = &(struct nvkm_pmu_impl) { + .base.handle = NV_SUBDEV(PMU, 0xea), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk20a_pmu_ctor, + .dtor = _nvkm_pmu_dtor, + .init = gk20a_pmu_init, + .fini = gk20a_pmu_fini, + }, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c index 998d53076b8b..30aaeb21de41 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c @@ -21,30 +21,29 @@ * * Authors: Ben Skeggs */ - #include "priv.h" -#include "fuc/nva3.fuc.h" +#include "fuc/gt215.fuc3.h" static int -nva3_pwr_init(struct nouveau_object *object) +gt215_pmu_init(struct nvkm_object *object) { - struct nouveau_pwr *ppwr = (void *)object; - nv_mask(ppwr, 0x022210, 0x00000001, 0x00000000); - nv_mask(ppwr, 0x022210, 0x00000001, 0x00000001); - return nouveau_pwr_init(ppwr); + struct nvkm_pmu *pmu = (void *)object; + nv_mask(pmu, 0x022210, 0x00000001, 0x00000000); + nv_mask(pmu, 0x022210, 0x00000001, 0x00000001); + return nvkm_pmu_init(pmu); } -struct nouveau_oclass * -nva3_pwr_oclass = &(struct nvkm_pwr_impl) { - .base.handle = NV_SUBDEV(PWR, 0xa3), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_pwr_ctor, - .dtor = _nouveau_pwr_dtor, - .init = nva3_pwr_init, - .fini = _nouveau_pwr_fini, +struct nvkm_oclass * +gt215_pmu_oclass = &(struct nvkm_pmu_impl) { + .base.handle = NV_SUBDEV(PMU, 0xa3), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_pmu_ctor, + .dtor = _nvkm_pmu_dtor, + .init = gt215_pmu_init, + .fini = _nvkm_pmu_fini, }, - .code.data = nva3_pwr_code, - .code.size = sizeof(nva3_pwr_code), - .data.data = nva3_pwr_data, - .data.size = sizeof(nva3_pwr_data), + .code.data = gt215_pmu_code, + .code.size = sizeof(gt215_pmu_code), + .data.data = gt215_pmu_data, + .data.size = sizeof(gt215_pmu_data), }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c new file mode 100644 index 000000000000..b75c5b885980 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c @@ -0,0 +1,200 @@ +#ifndef __NVKM_PMU_MEMX_H__ +#define __NVKM_PMU_MEMX_H__ +#include "priv.h" + +#include <core/device.h> + +struct nvkm_memx { + struct nvkm_pmu *pmu; + u32 base; + u32 size; + struct { + u32 mthd; + u32 size; + u32 data[64]; + } c; +}; + +static void +memx_out(struct nvkm_memx *memx) +{ + struct nvkm_pmu *pmu = memx->pmu; + int i; + + if (memx->c.mthd) { + nv_wr32(pmu, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd); + for (i = 0; i < memx->c.size; i++) + nv_wr32(pmu, 0x10a1c4, memx->c.data[i]); + memx->c.mthd = 0; + memx->c.size = 0; + } +} + +static void +memx_cmd(struct nvkm_memx *memx, u32 mthd, u32 size, u32 data[]) +{ + if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) || + (memx->c.mthd && memx->c.mthd != mthd)) + memx_out(memx); + memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0])); + memx->c.size += size; + memx->c.mthd = mthd; +} + +int +nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx) +{ + struct nvkm_memx *memx; + u32 reply[2]; + int ret; + + ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO, + MEMX_INFO_DATA, 0); + if (ret) + return ret; + + memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL); + if (!memx) + return -ENOMEM; + memx->pmu = pmu; + memx->base = reply[0]; + memx->size = reply[1]; + + /* acquire data segment access */ + do { + nv_wr32(pmu, 0x10a580, 0x00000003); + } while (nv_rd32(pmu, 0x10a580) != 0x00000003); + nv_wr32(pmu, 0x10a1c0, 0x01000000 | memx->base); + return 0; +} + +int +nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec) +{ + struct nvkm_memx *memx = *pmemx; + struct nvkm_pmu *pmu = memx->pmu; + u32 finish, reply[2]; + + /* flush the cache... */ + memx_out(memx); + + /* release data segment access */ + finish = nv_rd32(pmu, 0x10a1c0) & 0x00ffffff; + nv_wr32(pmu, 0x10a580, 0x00000000); + + /* call MEMX process to execute the script, and wait for reply */ + if (exec) { + pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC, + memx->base, finish); + } + + nv_debug(memx->pmu, "Exec took %uns, PMU_IN %08x\n", + reply[0], reply[1]); + kfree(memx); + return 0; +} + +void +nvkm_memx_wr32(struct nvkm_memx *memx, u32 addr, u32 data) +{ + nv_debug(memx->pmu, "R[%06x] = 0x%08x\n", addr, data); + memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data }); +} + +void +nvkm_memx_wait(struct nvkm_memx *memx, + u32 addr, u32 mask, u32 data, u32 nsec) +{ + nv_debug(memx->pmu, "R[%06x] & 0x%08x == 0x%08x, %d us\n", + addr, mask, data, nsec); + memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, mask, data, nsec }); + memx_out(memx); /* fuc can't handle multiple */ +} + +void +nvkm_memx_nsec(struct nvkm_memx *memx, u32 nsec) +{ + nv_debug(memx->pmu, " DELAY = %d ns\n", nsec); + memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec }); + memx_out(memx); /* fuc can't handle multiple */ +} + +void +nvkm_memx_wait_vblank(struct nvkm_memx *memx) +{ + struct nvkm_pmu *pmu = memx->pmu; + u32 heads, x, y, px = 0; + int i, head_sync; + + if (nv_device(pmu)->chipset < 0xd0) { + heads = nv_rd32(pmu, 0x610050); + for (i = 0; i < 2; i++) { + /* Heuristic: sync to head with biggest resolution */ + if (heads & (2 << (i << 3))) { + x = nv_rd32(pmu, 0x610b40 + (0x540 * i)); + y = (x & 0xffff0000) >> 16; + x &= 0x0000ffff; + if ((x * y) > px) { + px = (x * y); + head_sync = i; + } + } + } + } + + if (px == 0) { + nv_debug(memx->pmu, "WAIT VBLANK !NO ACTIVE HEAD\n"); + return; + } + + nv_debug(memx->pmu, "WAIT VBLANK HEAD%d\n", head_sync); + memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync }); + memx_out(memx); /* fuc can't handle multiple */ +} + +void +nvkm_memx_train(struct nvkm_memx *memx) +{ + nv_debug(memx->pmu, " MEM TRAIN\n"); + memx_cmd(memx, MEMX_TRAIN, 0, NULL); +} + +int +nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize) +{ + u32 reply[2], base, size, i; + int ret; + + ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO, + MEMX_INFO_TRAIN, 0); + if (ret) + return ret; + + base = reply[0]; + size = reply[1] >> 2; + if (size > rsize) + return -ENOMEM; + + /* read the packet */ + nv_wr32(pmu, 0x10a1c0, 0x02000000 | base); + + for (i = 0; i < size; i++) + res[i] = nv_rd32(pmu, 0x10a1c4); + + return 0; +} + +void +nvkm_memx_block(struct nvkm_memx *memx) +{ + nv_debug(memx->pmu, " HOST BLOCKED\n"); + memx_cmd(memx, MEMX_ENTER, 0, NULL); +} + +void +nvkm_memx_unblock(struct nvkm_memx *memx) +{ + nv_debug(memx->pmu, " HOST UNBLOCKED\n"); + memx_cmd(memx, MEMX_LEAVE, 0, NULL); +} +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h new file mode 100644 index 000000000000..998410563bfd --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h @@ -0,0 +1,43 @@ +#ifndef __NVKM_PMU_PRIV_H__ +#define __NVKM_PMU_PRIV_H__ +#include <subdev/pmu.h> +#include <subdev/pmu/fuc/os.h> + +#define nvkm_pmu_create(p, e, o, d) \ + nvkm_pmu_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_pmu_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_pmu_init(p) ({ \ + struct nvkm_pmu *_pmu = (p); \ + _nvkm_pmu_init(nv_object(_pmu)); \ +}) +#define nvkm_pmu_fini(p,s) ({ \ + struct nvkm_pmu *_pmu = (p); \ + _nvkm_pmu_fini(nv_object(_pmu), (s)); \ +}) + +int nvkm_pmu_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); + +int _nvkm_pmu_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +#define _nvkm_pmu_dtor _nvkm_subdev_dtor +int _nvkm_pmu_init(struct nvkm_object *); +int _nvkm_pmu_fini(struct nvkm_object *, bool); +void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable); + +struct nvkm_pmu_impl { + struct nvkm_oclass base; + struct { + u32 *data; + u32 size; + } code; + struct { + u32 *data; + u32 size; + } data; + + void (*pgob)(struct nvkm_pmu *, bool); +}; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild new file mode 100644 index 000000000000..5837cf1292d9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild @@ -0,0 +1,13 @@ +nvkm-y += nvkm/subdev/therm/base.o +nvkm-y += nvkm/subdev/therm/fan.o +nvkm-y += nvkm/subdev/therm/fannil.o +nvkm-y += nvkm/subdev/therm/fanpwm.o +nvkm-y += nvkm/subdev/therm/fantog.o +nvkm-y += nvkm/subdev/therm/ic.o +nvkm-y += nvkm/subdev/therm/temp.o +nvkm-y += nvkm/subdev/therm/nv40.o +nvkm-y += nvkm/subdev/therm/nv50.o +nvkm-y += nvkm/subdev/therm/g84.o +nvkm-y += nvkm/subdev/therm/gt215.o +nvkm-y += nvkm/subdev/therm/gf110.o +nvkm-y += nvkm/subdev/therm/gm107.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c index 9ad01da6eacb..ec327cb64a0d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c @@ -21,21 +21,17 @@ * * Authors: Martin Peres */ +#include "priv.h" -#include <core/object.h> #include <core/device.h> -#include <subdev/bios.h> - -#include "priv.h" - static int -nouveau_therm_update_trip(struct nouveau_therm *therm) +nvkm_therm_update_trip(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; - struct nouveau_therm_trip_point *trip = priv->fan->bios.trip, - *cur_trip = NULL, - *last_trip = priv->last_trip; + struct nvkm_therm_priv *priv = (void *)therm; + struct nvbios_therm_trip_point *trip = priv->fan->bios.trip, + *cur_trip = NULL, + *last_trip = priv->last_trip; u8 temp = therm->temp_get(therm); u16 duty, i; @@ -63,9 +59,9 @@ nouveau_therm_update_trip(struct nouveau_therm *therm) } static int -nouveau_therm_update_linear(struct nouveau_therm *therm) +nvkm_therm_update_linear(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; u8 linear_min_temp = priv->fan->bios.linear_min_temp; u8 linear_max_temp = priv->fan->bios.linear_max_temp; u8 temp = therm->temp_get(therm); @@ -82,15 +78,14 @@ nouveau_therm_update_linear(struct nouveau_therm *therm) duty *= (priv->fan->bios.max_duty - priv->fan->bios.min_duty); duty /= (linear_max_temp - linear_min_temp); duty += priv->fan->bios.min_duty; - return duty; } static void -nouveau_therm_update(struct nouveau_therm *therm, int mode) +nvkm_therm_update(struct nvkm_therm *therm, int mode) { - struct nouveau_timer *ptimer = nouveau_timer(therm); - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_timer *ptimer = nvkm_timer(therm); + struct nvkm_therm_priv *priv = (void *)therm; unsigned long flags; bool immd = true; bool poll = true; @@ -102,20 +97,20 @@ nouveau_therm_update(struct nouveau_therm *therm, int mode) priv->mode = mode; switch (mode) { - case NOUVEAU_THERM_CTRL_MANUAL: + case NVKM_THERM_CTRL_MANUAL: ptimer->alarm_cancel(ptimer, &priv->alarm); - duty = nouveau_therm_fan_get(therm); + duty = nvkm_therm_fan_get(therm); if (duty < 0) duty = 100; poll = false; break; - case NOUVEAU_THERM_CTRL_AUTO: + case NVKM_THERM_CTRL_AUTO: switch(priv->fan->bios.fan_mode) { case NVBIOS_THERM_FAN_TRIP: - duty = nouveau_therm_update_trip(therm); + duty = nvkm_therm_update_trip(therm); break; case NVBIOS_THERM_FAN_LINEAR: - duty = nouveau_therm_update_linear(therm); + duty = nvkm_therm_update_linear(therm); break; case NVBIOS_THERM_FAN_OTHER: if (priv->cstate) @@ -125,7 +120,7 @@ nouveau_therm_update(struct nouveau_therm *therm, int mode) } immd = false; break; - case NOUVEAU_THERM_CTRL_NONE: + case NVKM_THERM_CTRL_NONE: default: ptimer->alarm_cancel(ptimer, &priv->alarm); poll = false; @@ -137,36 +132,36 @@ nouveau_therm_update(struct nouveau_therm *therm, int mode) if (duty >= 0) { nv_debug(therm, "FAN target request: %d%%\n", duty); - nouveau_therm_fan_set(therm, immd, duty); + nvkm_therm_fan_set(therm, immd, duty); } } int -nouveau_therm_cstate(struct nouveau_therm *ptherm, int fan, int dir) +nvkm_therm_cstate(struct nvkm_therm *ptherm, int fan, int dir) { - struct nouveau_therm_priv *priv = (void *)ptherm; + struct nvkm_therm_priv *priv = (void *)ptherm; if (!dir || (dir < 0 && fan < priv->cstate) || (dir > 0 && fan > priv->cstate)) { nv_debug(ptherm, "default fan speed -> %d%%\n", fan); priv->cstate = fan; - nouveau_therm_update(ptherm, -1); + nvkm_therm_update(ptherm, -1); } return 0; } static void -nouveau_therm_alarm(struct nouveau_alarm *alarm) +nvkm_therm_alarm(struct nvkm_alarm *alarm) { - struct nouveau_therm_priv *priv = - container_of(alarm, struct nouveau_therm_priv, alarm); - nouveau_therm_update(&priv->base, -1); + struct nvkm_therm_priv *priv = + container_of(alarm, struct nvkm_therm_priv, alarm); + nvkm_therm_update(&priv->base, -1); } int -nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode) +nvkm_therm_fan_mode(struct nvkm_therm *therm, int mode) { - struct nouveau_therm_priv *priv = (void *)therm; - struct nouveau_device *device = nv_device(therm); + struct nvkm_therm_priv *priv = (void *)therm; + struct nvkm_device *device = nv_device(therm); static const char *name[] = { "disabled", "manual", @@ -175,51 +170,51 @@ nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode) /* The default PPWR ucode on fermi interferes with fan management */ if ((mode >= ARRAY_SIZE(name)) || - (mode != NOUVEAU_THERM_CTRL_NONE && device->card_type >= NV_C0 && - !nouveau_subdev(device, NVDEV_SUBDEV_PWR))) + (mode != NVKM_THERM_CTRL_NONE && device->card_type >= NV_C0 && + !nvkm_subdev(device, NVDEV_SUBDEV_PMU))) return -EINVAL; /* do not allow automatic fan management if the thermal sensor is * not available */ - if (mode == NOUVEAU_THERM_CTRL_AUTO && therm->temp_get(therm) < 0) + if (mode == NVKM_THERM_CTRL_AUTO && therm->temp_get(therm) < 0) return -EINVAL; if (priv->mode == mode) return 0; nv_info(therm, "fan management: %s\n", name[mode]); - nouveau_therm_update(therm, mode); + nvkm_therm_update(therm, mode); return 0; } int -nouveau_therm_attr_get(struct nouveau_therm *therm, - enum nouveau_therm_attr_type type) +nvkm_therm_attr_get(struct nvkm_therm *therm, + enum nvkm_therm_attr_type type) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; switch (type) { - case NOUVEAU_THERM_ATTR_FAN_MIN_DUTY: + case NVKM_THERM_ATTR_FAN_MIN_DUTY: return priv->fan->bios.min_duty; - case NOUVEAU_THERM_ATTR_FAN_MAX_DUTY: + case NVKM_THERM_ATTR_FAN_MAX_DUTY: return priv->fan->bios.max_duty; - case NOUVEAU_THERM_ATTR_FAN_MODE: + case NVKM_THERM_ATTR_FAN_MODE: return priv->mode; - case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST: + case NVKM_THERM_ATTR_THRS_FAN_BOOST: return priv->bios_sensor.thrs_fan_boost.temp; - case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST: + case NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST: return priv->bios_sensor.thrs_fan_boost.hysteresis; - case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK: + case NVKM_THERM_ATTR_THRS_DOWN_CLK: return priv->bios_sensor.thrs_down_clock.temp; - case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST: + case NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST: return priv->bios_sensor.thrs_down_clock.hysteresis; - case NOUVEAU_THERM_ATTR_THRS_CRITICAL: + case NVKM_THERM_ATTR_THRS_CRITICAL: return priv->bios_sensor.thrs_critical.temp; - case NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST: + case NVKM_THERM_ATTR_THRS_CRITICAL_HYST: return priv->bios_sensor.thrs_critical.hysteresis; - case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN: + case NVKM_THERM_ATTR_THRS_SHUTDOWN: return priv->bios_sensor.thrs_shutdown.temp; - case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST: + case NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST: return priv->bios_sensor.thrs_shutdown.hysteresis; } @@ -227,57 +222,57 @@ nouveau_therm_attr_get(struct nouveau_therm *therm, } int -nouveau_therm_attr_set(struct nouveau_therm *therm, - enum nouveau_therm_attr_type type, int value) +nvkm_therm_attr_set(struct nvkm_therm *therm, + enum nvkm_therm_attr_type type, int value) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; switch (type) { - case NOUVEAU_THERM_ATTR_FAN_MIN_DUTY: + case NVKM_THERM_ATTR_FAN_MIN_DUTY: if (value < 0) value = 0; if (value > priv->fan->bios.max_duty) value = priv->fan->bios.max_duty; priv->fan->bios.min_duty = value; return 0; - case NOUVEAU_THERM_ATTR_FAN_MAX_DUTY: + case NVKM_THERM_ATTR_FAN_MAX_DUTY: if (value < 0) value = 0; if (value < priv->fan->bios.min_duty) value = priv->fan->bios.min_duty; priv->fan->bios.max_duty = value; return 0; - case NOUVEAU_THERM_ATTR_FAN_MODE: - return nouveau_therm_fan_mode(therm, value); - case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST: + case NVKM_THERM_ATTR_FAN_MODE: + return nvkm_therm_fan_mode(therm, value); + case NVKM_THERM_ATTR_THRS_FAN_BOOST: priv->bios_sensor.thrs_fan_boost.temp = value; priv->sensor.program_alarms(therm); return 0; - case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST: + case NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST: priv->bios_sensor.thrs_fan_boost.hysteresis = value; priv->sensor.program_alarms(therm); return 0; - case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK: + case NVKM_THERM_ATTR_THRS_DOWN_CLK: priv->bios_sensor.thrs_down_clock.temp = value; priv->sensor.program_alarms(therm); return 0; - case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST: + case NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST: priv->bios_sensor.thrs_down_clock.hysteresis = value; priv->sensor.program_alarms(therm); return 0; - case NOUVEAU_THERM_ATTR_THRS_CRITICAL: + case NVKM_THERM_ATTR_THRS_CRITICAL: priv->bios_sensor.thrs_critical.temp = value; priv->sensor.program_alarms(therm); return 0; - case NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST: + case NVKM_THERM_ATTR_THRS_CRITICAL_HYST: priv->bios_sensor.thrs_critical.hysteresis = value; priv->sensor.program_alarms(therm); return 0; - case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN: + case NVKM_THERM_ATTR_THRS_SHUTDOWN: priv->bios_sensor.thrs_shutdown.temp = value; priv->sensor.program_alarms(therm); return 0; - case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST: + case NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST: priv->bios_sensor.thrs_shutdown.hysteresis = value; priv->sensor.program_alarms(therm); return 0; @@ -287,88 +282,86 @@ nouveau_therm_attr_set(struct nouveau_therm *therm, } int -_nouveau_therm_init(struct nouveau_object *object) +_nvkm_therm_init(struct nvkm_object *object) { - struct nouveau_therm *therm = (void *)object; - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm *therm = (void *)object; + struct nvkm_therm_priv *priv = (void *)therm; int ret; - ret = nouveau_subdev_init(&therm->base); + ret = nvkm_subdev_init(&therm->base); if (ret) return ret; if (priv->suspend >= 0) { /* restore the pwm value only when on manual or auto mode */ if (priv->suspend > 0) - nouveau_therm_fan_set(therm, true, priv->fan->percent); + nvkm_therm_fan_set(therm, true, priv->fan->percent); - nouveau_therm_fan_mode(therm, priv->suspend); + nvkm_therm_fan_mode(therm, priv->suspend); } - nouveau_therm_sensor_init(therm); - nouveau_therm_fan_init(therm); + nvkm_therm_sensor_init(therm); + nvkm_therm_fan_init(therm); return 0; } int -_nouveau_therm_fini(struct nouveau_object *object, bool suspend) +_nvkm_therm_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_therm *therm = (void *)object; - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm *therm = (void *)object; + struct nvkm_therm_priv *priv = (void *)therm; - nouveau_therm_fan_fini(therm, suspend); - nouveau_therm_sensor_fini(therm, suspend); + nvkm_therm_fan_fini(therm, suspend); + nvkm_therm_sensor_fini(therm, suspend); if (suspend) { priv->suspend = priv->mode; - priv->mode = NOUVEAU_THERM_CTRL_NONE; + priv->mode = NVKM_THERM_CTRL_NONE; } - return nouveau_subdev_fini(&therm->base, suspend); + return nvkm_subdev_fini(&therm->base, suspend); } int -nouveau_therm_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int length, void **pobject) +nvkm_therm_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_therm_priv *priv; + struct nvkm_therm_priv *priv; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PTHERM", - "therm", length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PTHERM", + "therm", length, pobject); priv = *pobject; if (ret) return ret; - nouveau_alarm_init(&priv->alarm, nouveau_therm_alarm); + nvkm_alarm_init(&priv->alarm, nvkm_therm_alarm); spin_lock_init(&priv->lock); spin_lock_init(&priv->sensor.alarm_program_lock); - priv->base.fan_get = nouveau_therm_fan_user_get; - priv->base.fan_set = nouveau_therm_fan_user_set; - priv->base.fan_sense = nouveau_therm_fan_sense; - priv->base.attr_get = nouveau_therm_attr_get; - priv->base.attr_set = nouveau_therm_attr_set; + priv->base.fan_get = nvkm_therm_fan_user_get; + priv->base.fan_set = nvkm_therm_fan_user_set; + priv->base.fan_sense = nvkm_therm_fan_sense; + priv->base.attr_get = nvkm_therm_attr_get; + priv->base.attr_set = nvkm_therm_attr_set; priv->mode = priv->suspend = -1; /* undefined */ return 0; } int -nouveau_therm_preinit(struct nouveau_therm *therm) +nvkm_therm_preinit(struct nvkm_therm *therm) { - nouveau_therm_sensor_ctor(therm); - nouveau_therm_ic_ctor(therm); - nouveau_therm_fan_ctor(therm); + nvkm_therm_sensor_ctor(therm); + nvkm_therm_ic_ctor(therm); + nvkm_therm_fan_ctor(therm); - nouveau_therm_fan_mode(therm, NOUVEAU_THERM_CTRL_AUTO); - nouveau_therm_sensor_preinit(therm); + nvkm_therm_fan_mode(therm, NVKM_THERM_CTRL_AUTO); + nvkm_therm_sensor_preinit(therm); return 0; } void -_nouveau_therm_dtor(struct nouveau_object *object) +_nvkm_therm_dtor(struct nvkm_object *object) { - struct nouveau_therm_priv *priv = (void *)object; + struct nvkm_therm_priv *priv = (void *)object; kfree(priv->fan); - nouveau_subdev_destroy(&priv->base.base); + nvkm_subdev_destroy(&priv->base.base); } diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c index 3656d605168f..434fa745ca40 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c @@ -22,23 +22,18 @@ * Authors: Ben Skeggs * Martin Peres */ - #include "priv.h" -#include <core/object.h> -#include <core/device.h> - +#include <subdev/bios/fan.h> #include <subdev/gpio.h> #include <subdev/timer.h> -#include <subdev/bios/fan.h> - static int -nouveau_fan_update(struct nouveau_fan *fan, bool immediate, int target) +nvkm_fan_update(struct nvkm_fan *fan, bool immediate, int target) { - struct nouveau_therm *therm = fan->parent; - struct nouveau_therm_priv *priv = (void *)therm; - struct nouveau_timer *ptimer = nouveau_timer(priv); + struct nvkm_therm *therm = fan->parent; + struct nvkm_therm_priv *priv = (void *)therm; + struct nvkm_timer *ptimer = nvkm_timer(priv); unsigned long flags; int ret = 0; int duty; @@ -107,32 +102,32 @@ nouveau_fan_update(struct nouveau_fan *fan, bool immediate, int target) } static void -nouveau_fan_alarm(struct nouveau_alarm *alarm) +nvkm_fan_alarm(struct nvkm_alarm *alarm) { - struct nouveau_fan *fan = container_of(alarm, struct nouveau_fan, alarm); - nouveau_fan_update(fan, false, -1); + struct nvkm_fan *fan = container_of(alarm, struct nvkm_fan, alarm); + nvkm_fan_update(fan, false, -1); } int -nouveau_therm_fan_get(struct nouveau_therm *therm) +nvkm_therm_fan_get(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; return priv->fan->get(therm); } int -nouveau_therm_fan_set(struct nouveau_therm *therm, bool immediate, int percent) +nvkm_therm_fan_set(struct nvkm_therm *therm, bool immediate, int percent) { - struct nouveau_therm_priv *priv = (void *)therm; - return nouveau_fan_update(priv->fan, immediate, percent); + struct nvkm_therm_priv *priv = (void *)therm; + return nvkm_fan_update(priv->fan, immediate, percent); } int -nouveau_therm_fan_sense(struct nouveau_therm *therm) +nvkm_therm_fan_sense(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; - struct nouveau_timer *ptimer = nouveau_timer(therm); - struct nouveau_gpio *gpio = nouveau_gpio(therm); + struct nvkm_therm_priv *priv = (void *)therm; + struct nvkm_timer *ptimer = nvkm_timer(therm); + struct nvkm_gpio *gpio = nvkm_gpio(therm); u32 cycles, cur, prev; u64 start, end, tach; @@ -168,26 +163,26 @@ nouveau_therm_fan_sense(struct nouveau_therm *therm) } int -nouveau_therm_fan_user_get(struct nouveau_therm *therm) +nvkm_therm_fan_user_get(struct nvkm_therm *therm) { - return nouveau_therm_fan_get(therm); + return nvkm_therm_fan_get(therm); } int -nouveau_therm_fan_user_set(struct nouveau_therm *therm, int percent) +nvkm_therm_fan_user_set(struct nvkm_therm *therm, int percent) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; - if (priv->mode != NOUVEAU_THERM_CTRL_MANUAL) + if (priv->mode != NVKM_THERM_CTRL_MANUAL) return -EINVAL; - return nouveau_therm_fan_set(therm, true, percent); + return nvkm_therm_fan_set(therm, true, percent); } static void -nouveau_therm_fan_set_defaults(struct nouveau_therm *therm) +nvkm_therm_fan_set_defaults(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; priv->fan->bios.pwm_freq = 0; priv->fan->bios.min_duty = 0; @@ -199,9 +194,9 @@ nouveau_therm_fan_set_defaults(struct nouveau_therm *therm) } static void -nouveau_therm_fan_safety_checks(struct nouveau_therm *therm) +nvkm_therm_fan_safety_checks(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; if (priv->fan->bios.min_duty > 100) priv->fan->bios.min_duty = 100; @@ -213,16 +208,16 @@ nouveau_therm_fan_safety_checks(struct nouveau_therm *therm) } int -nouveau_therm_fan_init(struct nouveau_therm *therm) +nvkm_therm_fan_init(struct nvkm_therm *therm) { return 0; } int -nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend) +nvkm_therm_fan_fini(struct nvkm_therm *therm, bool suspend) { - struct nouveau_therm_priv *priv = (void *)therm; - struct nouveau_timer *ptimer = nouveau_timer(therm); + struct nvkm_therm_priv *priv = (void *)therm; + struct nvkm_timer *ptimer = nvkm_timer(therm); if (suspend) ptimer->alarm_cancel(ptimer, &priv->fan->alarm); @@ -230,11 +225,11 @@ nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend) } int -nouveau_therm_fan_ctor(struct nouveau_therm *therm) +nvkm_therm_fan_ctor(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; - struct nouveau_gpio *gpio = nouveau_gpio(therm); - struct nouveau_bios *bios = nouveau_bios(therm); + struct nvkm_therm_priv *priv = (void *)therm; + struct nvkm_gpio *gpio = nvkm_gpio(therm); + struct nvkm_bios *bios = nvkm_bios(therm); struct dcb_gpio_func func; int ret; @@ -246,15 +241,15 @@ nouveau_therm_fan_ctor(struct nouveau_therm *therm) nv_debug(therm, "GPIO_FAN is in input mode\n"); ret = -EINVAL; } else { - ret = nouveau_fanpwm_create(therm, &func); + ret = nvkm_fanpwm_create(therm, &func); if (ret != 0) - ret = nouveau_fantog_create(therm, &func); + ret = nvkm_fantog_create(therm, &func); } } /* no controllable fan found, create a dummy fan module */ if (ret != 0) { - ret = nouveau_fannil_create(therm); + ret = nvkm_fannil_create(therm); if (ret) return ret; } @@ -262,7 +257,7 @@ nouveau_therm_fan_ctor(struct nouveau_therm *therm) nv_info(therm, "FAN control: %s\n", priv->fan->type); /* read the current speed, it is useful when resuming */ - priv->fan->percent = nouveau_therm_fan_get(therm); + priv->fan->percent = nvkm_therm_fan_get(therm); /* attempt to detect a tachometer connection */ ret = gpio->find(gpio, 0, DCB_GPIO_FAN_SENSE, 0xff, &priv->fan->tach); @@ -271,17 +266,17 @@ nouveau_therm_fan_ctor(struct nouveau_therm *therm) /* initialise fan bump/slow update handling */ priv->fan->parent = therm; - nouveau_alarm_init(&priv->fan->alarm, nouveau_fan_alarm); + nvkm_alarm_init(&priv->fan->alarm, nvkm_fan_alarm); spin_lock_init(&priv->fan->lock); /* other random init... */ - nouveau_therm_fan_set_defaults(therm); + nvkm_therm_fan_set_defaults(therm); nvbios_perf_fan_parse(bios, &priv->fan->perf); if (!nvbios_fan_parse(bios, &priv->fan->bios)) { nv_debug(therm, "parsing the fan table failed\n"); if (nvbios_therm_fan_parse(bios, &priv->fan->bios)) nv_error(therm, "parsing both fan tables failed\n"); } - nouveau_therm_fan_safety_checks(therm); + nvkm_therm_fan_safety_checks(therm); return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.c index b78c182e1d51..534e5970ec9c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.c @@ -21,26 +21,25 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static int -nouveau_fannil_get(struct nouveau_therm *therm) +nvkm_fannil_get(struct nvkm_therm *therm) { return -ENODEV; } static int -nouveau_fannil_set(struct nouveau_therm *therm, int percent) +nvkm_fannil_set(struct nvkm_therm *therm, int percent) { return -ENODEV; } int -nouveau_fannil_create(struct nouveau_therm *therm) +nvkm_fannil_create(struct nvkm_therm *therm) { - struct nouveau_therm_priv *tpriv = (void *)therm; - struct nouveau_fan *priv; + struct nvkm_therm_priv *tpriv = (void *)therm; + struct nvkm_fan *priv; priv = kzalloc(sizeof(*priv), GFP_KERNEL); tpriv->fan = priv; @@ -48,7 +47,7 @@ nouveau_fannil_create(struct nouveau_therm *therm) return -ENOMEM; priv->type = "none / external"; - priv->get = nouveau_fannil_get; - priv->set = nouveau_fannil_set; + priv->get = nvkm_fannil_get; + priv->set = nvkm_fannil_set; return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c index c629d7f2a6a4..bde5ceaeb70a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c @@ -22,25 +22,25 @@ * Authors: Ben Skeggs * Martin Peres */ +#include "priv.h" +#include <core/device.h> #include <core/option.h> -#include <subdev/gpio.h> #include <subdev/bios.h> #include <subdev/bios/fan.h> +#include <subdev/gpio.h> -#include "priv.h" - -struct nouveau_fanpwm_priv { - struct nouveau_fan base; +struct nvkm_fanpwm_priv { + struct nvkm_fan base; struct dcb_gpio_func func; }; static int -nouveau_fanpwm_get(struct nouveau_therm *therm) +nvkm_fanpwm_get(struct nvkm_therm *therm) { - struct nouveau_therm_priv *tpriv = (void *)therm; - struct nouveau_fanpwm_priv *priv = (void *)tpriv->fan; - struct nouveau_gpio *gpio = nouveau_gpio(therm); + struct nvkm_therm_priv *tpriv = (void *)therm; + struct nvkm_fanpwm_priv *priv = (void *)tpriv->fan; + struct nvkm_gpio *gpio = nvkm_gpio(therm); int card_type = nv_device(therm)->card_type; u32 divs, duty; int ret; @@ -57,10 +57,10 @@ nouveau_fanpwm_get(struct nouveau_therm *therm) } static int -nouveau_fanpwm_set(struct nouveau_therm *therm, int percent) +nvkm_fanpwm_set(struct nvkm_therm *therm, int percent) { - struct nouveau_therm_priv *tpriv = (void *)therm; - struct nouveau_fanpwm_priv *priv = (void *)tpriv->fan; + struct nvkm_therm_priv *tpriv = (void *)therm; + struct nvkm_fanpwm_priv *priv = (void *)tpriv->fan; int card_type = nv_device(therm)->card_type; u32 divs, duty; int ret; @@ -84,18 +84,18 @@ nouveau_fanpwm_set(struct nouveau_therm *therm, int percent) } int -nouveau_fanpwm_create(struct nouveau_therm *therm, struct dcb_gpio_func *func) +nvkm_fanpwm_create(struct nvkm_therm *therm, struct dcb_gpio_func *func) { - struct nouveau_device *device = nv_device(therm); - struct nouveau_therm_priv *tpriv = (void *)therm; - struct nouveau_bios *bios = nouveau_bios(therm); - struct nouveau_fanpwm_priv *priv; + struct nvkm_device *device = nv_device(therm); + struct nvkm_therm_priv *tpriv = (void *)therm; + struct nvkm_bios *bios = nvkm_bios(therm); + struct nvkm_fanpwm_priv *priv; struct nvbios_therm_fan fan; u32 divs, duty; nvbios_fan_parse(bios, &fan); - if (!nouveau_boolopt(device->cfgopt, "NvFanPWM", func->param) || + if (!nvkm_boolopt(device->cfgopt, "NvFanPWM", func->param) || !therm->pwm_ctrl || fan.type == NVBIOS_THERM_FAN_TOGGLE || therm->pwm_get(therm, func->line, &divs, &duty) == -ENODEV) return -ENODEV; @@ -106,8 +106,8 @@ nouveau_fanpwm_create(struct nouveau_therm *therm, struct dcb_gpio_func *func) return -ENOMEM; priv->base.type = "PWM"; - priv->base.get = nouveau_fanpwm_get; - priv->base.set = nouveau_fanpwm_set; + priv->base.get = nvkm_fanpwm_get; + priv->base.set = nvkm_fanpwm_set; priv->func = *func; return 0; } diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c index f69dab11f720..4ce041e81371 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c @@ -21,18 +21,14 @@ * * Authors: Martin Peres */ - #include "priv.h" -#include <core/object.h> -#include <core/device.h> - #include <subdev/gpio.h> #include <subdev/timer.h> -struct nouveau_fantog_priv { - struct nouveau_fan base; - struct nouveau_alarm alarm; +struct nvkm_fantog_priv { + struct nvkm_fan base; + struct nvkm_alarm alarm; spinlock_t lock; u32 period_us; u32 percent; @@ -40,11 +36,11 @@ struct nouveau_fantog_priv { }; static void -nouveau_fantog_update(struct nouveau_fantog_priv *priv, int percent) +nvkm_fantog_update(struct nvkm_fantog_priv *priv, int percent) { - struct nouveau_therm_priv *tpriv = (void *)priv->base.parent; - struct nouveau_timer *ptimer = nouveau_timer(tpriv); - struct nouveau_gpio *gpio = nouveau_gpio(tpriv); + struct nvkm_therm_priv *tpriv = (void *)priv->base.parent; + struct nvkm_timer *ptimer = nvkm_timer(tpriv); + struct nvkm_gpio *gpio = nvkm_gpio(tpriv); unsigned long flags; int duty; @@ -66,37 +62,37 @@ nouveau_fantog_update(struct nouveau_fantog_priv *priv, int percent) } static void -nouveau_fantog_alarm(struct nouveau_alarm *alarm) +nvkm_fantog_alarm(struct nvkm_alarm *alarm) { - struct nouveau_fantog_priv *priv = - container_of(alarm, struct nouveau_fantog_priv, alarm); - nouveau_fantog_update(priv, -1); + struct nvkm_fantog_priv *priv = + container_of(alarm, struct nvkm_fantog_priv, alarm); + nvkm_fantog_update(priv, -1); } static int -nouveau_fantog_get(struct nouveau_therm *therm) +nvkm_fantog_get(struct nvkm_therm *therm) { - struct nouveau_therm_priv *tpriv = (void *)therm; - struct nouveau_fantog_priv *priv = (void *)tpriv->fan; + struct nvkm_therm_priv *tpriv = (void *)therm; + struct nvkm_fantog_priv *priv = (void *)tpriv->fan; return priv->percent; } static int -nouveau_fantog_set(struct nouveau_therm *therm, int percent) +nvkm_fantog_set(struct nvkm_therm *therm, int percent) { - struct nouveau_therm_priv *tpriv = (void *)therm; - struct nouveau_fantog_priv *priv = (void *)tpriv->fan; + struct nvkm_therm_priv *tpriv = (void *)therm; + struct nvkm_fantog_priv *priv = (void *)tpriv->fan; if (therm->pwm_ctrl) therm->pwm_ctrl(therm, priv->func.line, false); - nouveau_fantog_update(priv, percent); + nvkm_fantog_update(priv, percent); return 0; } int -nouveau_fantog_create(struct nouveau_therm *therm, struct dcb_gpio_func *func) +nvkm_fantog_create(struct nvkm_therm *therm, struct dcb_gpio_func *func) { - struct nouveau_therm_priv *tpriv = (void *)therm; - struct nouveau_fantog_priv *priv; + struct nvkm_therm_priv *tpriv = (void *)therm; + struct nvkm_fantog_priv *priv; int ret; if (therm->pwm_ctrl) { @@ -111,9 +107,9 @@ nouveau_fantog_create(struct nouveau_therm *therm, struct dcb_gpio_func *func) return -ENOMEM; priv->base.type = "toggle"; - priv->base.get = nouveau_fantog_get; - priv->base.set = nouveau_fantog_set; - nouveau_alarm_init(&priv->alarm, nouveau_fantog_alarm); + priv->base.get = nvkm_fantog_get; + priv->base.set = nvkm_fantog_set; + nvkm_alarm_init(&priv->alarm, nvkm_fantog_alarm); priv->period_us = 100000; /* 10Hz */ priv->percent = 100; priv->func = *func; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c index 14e2e09bfc24..85b5d0c18c0b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c @@ -22,18 +22,18 @@ * Authors: Ben Skeggs * Martin Peres */ - #include "priv.h" + #include <subdev/fuse.h> -struct nv84_therm_priv { - struct nouveau_therm_priv base; +struct g84_therm_priv { + struct nvkm_therm_priv base; }; int -nv84_temp_get(struct nouveau_therm *therm) +g84_temp_get(struct nvkm_therm *therm) { - struct nouveau_fuse *fuse = nouveau_fuse(therm); + struct nvkm_fuse *fuse = nvkm_fuse(therm); if (nv_ro32(fuse, 0x1a8) == 1) return nv_rd32(therm, 0x20400); @@ -42,9 +42,9 @@ nv84_temp_get(struct nouveau_therm *therm) } void -nv84_sensor_setup(struct nouveau_therm *therm) +g84_sensor_setup(struct nvkm_therm *therm) { - struct nouveau_fuse *fuse = nouveau_fuse(therm); + struct nvkm_fuse *fuse = nvkm_fuse(therm); /* enable temperature reading for cards with insane defaults */ if (nv_ro32(fuse, 0x1a8) == 1) { @@ -55,9 +55,9 @@ nv84_sensor_setup(struct nouveau_therm *therm) } static void -nv84_therm_program_alarms(struct nouveau_therm *therm) +g84_therm_program_alarms(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; struct nvbios_therm_sensor *sensor = &priv->bios_sensor; unsigned long flags; @@ -92,53 +92,53 @@ nv84_therm_program_alarms(struct nouveau_therm *therm) /* must be called with alarm_program_lock taken ! */ static void -nv84_therm_threshold_hyst_emulation(struct nouveau_therm *therm, +g84_therm_threshold_hyst_emulation(struct nvkm_therm *therm, uint32_t thrs_reg, u8 status_bit, const struct nvbios_therm_threshold *thrs, - enum nouveau_therm_thrs thrs_name) + enum nvkm_therm_thrs thrs_name) { - enum nouveau_therm_thrs_direction direction; - enum nouveau_therm_thrs_state prev_state, new_state; + enum nvkm_therm_thrs_direction direction; + enum nvkm_therm_thrs_state prev_state, new_state; int temp, cur; - prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name); + prev_state = nvkm_therm_sensor_get_threshold_state(therm, thrs_name); temp = nv_rd32(therm, thrs_reg); /* program the next threshold */ if (temp == thrs->temp) { nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis); - new_state = NOUVEAU_THERM_THRS_HIGHER; + new_state = NVKM_THERM_THRS_HIGHER; } else { nv_wr32(therm, thrs_reg, thrs->temp); - new_state = NOUVEAU_THERM_THRS_LOWER; + new_state = NVKM_THERM_THRS_LOWER; } /* fix the state (in case someone reprogrammed the alarms) */ cur = therm->temp_get(therm); - if (new_state == NOUVEAU_THERM_THRS_LOWER && cur > thrs->temp) - new_state = NOUVEAU_THERM_THRS_HIGHER; - else if (new_state == NOUVEAU_THERM_THRS_HIGHER && + if (new_state == NVKM_THERM_THRS_LOWER && cur > thrs->temp) + new_state = NVKM_THERM_THRS_HIGHER; + else if (new_state == NVKM_THERM_THRS_HIGHER && cur < thrs->temp - thrs->hysteresis) - new_state = NOUVEAU_THERM_THRS_LOWER; - nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state); + new_state = NVKM_THERM_THRS_LOWER; + nvkm_therm_sensor_set_threshold_state(therm, thrs_name, new_state); /* find the direction */ if (prev_state < new_state) - direction = NOUVEAU_THERM_THRS_RISING; + direction = NVKM_THERM_THRS_RISING; else if (prev_state > new_state) - direction = NOUVEAU_THERM_THRS_FALLING; + direction = NVKM_THERM_THRS_FALLING; else return; /* advertise a change in direction */ - nouveau_therm_sensor_event(therm, thrs_name, direction); + nvkm_therm_sensor_event(therm, thrs_name, direction); } static void -nv84_therm_intr(struct nouveau_subdev *subdev) +g84_therm_intr(struct nvkm_subdev *subdev) { - struct nouveau_therm *therm = nouveau_therm(subdev); - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm *therm = nvkm_therm(subdev); + struct nvkm_therm_priv *priv = (void *)therm; struct nvbios_therm_sensor *sensor = &priv->bios_sensor; unsigned long flags; uint32_t intr; @@ -149,33 +149,33 @@ nv84_therm_intr(struct nouveau_subdev *subdev) /* THRS_4: downclock */ if (intr & 0x002) { - nv84_therm_threshold_hyst_emulation(therm, 0x20414, 24, - &sensor->thrs_down_clock, - NOUVEAU_THERM_THRS_DOWNCLOCK); + g84_therm_threshold_hyst_emulation(therm, 0x20414, 24, + &sensor->thrs_down_clock, + NVKM_THERM_THRS_DOWNCLOCK); intr &= ~0x002; } /* shutdown */ if (intr & 0x004) { - nv84_therm_threshold_hyst_emulation(therm, 0x20480, 20, + g84_therm_threshold_hyst_emulation(therm, 0x20480, 20, &sensor->thrs_shutdown, - NOUVEAU_THERM_THRS_SHUTDOWN); + NVKM_THERM_THRS_SHUTDOWN); intr &= ~0x004; } /* THRS_1 : fan boost */ if (intr & 0x008) { - nv84_therm_threshold_hyst_emulation(therm, 0x204c4, 21, + g84_therm_threshold_hyst_emulation(therm, 0x204c4, 21, &sensor->thrs_fan_boost, - NOUVEAU_THERM_THRS_FANBOOST); + NVKM_THERM_THRS_FANBOOST); intr &= ~0x008; } /* THRS_2 : critical */ if (intr & 0x010) { - nv84_therm_threshold_hyst_emulation(therm, 0x204c0, 22, + g84_therm_threshold_hyst_emulation(therm, 0x204c0, 22, &sensor->thrs_critical, - NOUVEAU_THERM_THRS_CRITICAL); + NVKM_THERM_THRS_CRITICAL); intr &= ~0x010; } @@ -190,30 +190,28 @@ nv84_therm_intr(struct nouveau_subdev *subdev) } static int -nv84_therm_init(struct nouveau_object *object) +g84_therm_init(struct nvkm_object *object) { - struct nv84_therm_priv *priv = (void *)object; + struct g84_therm_priv *priv = (void *)object; int ret; - ret = nouveau_therm_init(&priv->base.base); + ret = nvkm_therm_init(&priv->base.base); if (ret) return ret; - nv84_sensor_setup(&priv->base.base); - + g84_sensor_setup(&priv->base.base); return 0; } static int -nv84_therm_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +g84_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nv84_therm_priv *priv; + struct g84_therm_priv *priv; int ret; - ret = nouveau_therm_create(parent, engine, oclass, &priv); + ret = nvkm_therm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -222,29 +220,29 @@ nv84_therm_ctor(struct nouveau_object *parent, priv->base.base.pwm_get = nv50_fan_pwm_get; priv->base.base.pwm_set = nv50_fan_pwm_set; priv->base.base.pwm_clock = nv50_fan_pwm_clock; - priv->base.base.temp_get = nv84_temp_get; - priv->base.sensor.program_alarms = nv84_therm_program_alarms; - nv_subdev(priv)->intr = nv84_therm_intr; + priv->base.base.temp_get = g84_temp_get; + priv->base.sensor.program_alarms = g84_therm_program_alarms; + nv_subdev(priv)->intr = g84_therm_intr; /* init the thresholds */ - nouveau_therm_sensor_set_threshold_state(&priv->base.base, - NOUVEAU_THERM_THRS_SHUTDOWN, - NOUVEAU_THERM_THRS_LOWER); - nouveau_therm_sensor_set_threshold_state(&priv->base.base, - NOUVEAU_THERM_THRS_FANBOOST, - NOUVEAU_THERM_THRS_LOWER); - nouveau_therm_sensor_set_threshold_state(&priv->base.base, - NOUVEAU_THERM_THRS_CRITICAL, - NOUVEAU_THERM_THRS_LOWER); - nouveau_therm_sensor_set_threshold_state(&priv->base.base, - NOUVEAU_THERM_THRS_DOWNCLOCK, - NOUVEAU_THERM_THRS_LOWER); - - return nouveau_therm_preinit(&priv->base.base); + nvkm_therm_sensor_set_threshold_state(&priv->base.base, + NVKM_THERM_THRS_SHUTDOWN, + NVKM_THERM_THRS_LOWER); + nvkm_therm_sensor_set_threshold_state(&priv->base.base, + NVKM_THERM_THRS_FANBOOST, + NVKM_THERM_THRS_LOWER); + nvkm_therm_sensor_set_threshold_state(&priv->base.base, + NVKM_THERM_THRS_CRITICAL, + NVKM_THERM_THRS_LOWER); + nvkm_therm_sensor_set_threshold_state(&priv->base.base, + NVKM_THERM_THRS_DOWNCLOCK, + NVKM_THERM_THRS_LOWER); + + return nvkm_therm_preinit(&priv->base.base); } int -nv84_therm_fini(struct nouveau_object *object, bool suspend) +g84_therm_fini(struct nvkm_object *object, bool suspend) { /* Disable PTherm IRQs */ nv_wr32(object, 0x20000, 0x00000000); @@ -253,16 +251,16 @@ nv84_therm_fini(struct nouveau_object *object, bool suspend) nv_wr32(object, 0x20100, 0xffffffff); nv_wr32(object, 0x1100, 0x10000); /* PBUS */ - return _nouveau_therm_fini(object, suspend); + return _nvkm_therm_fini(object, suspend); } -struct nouveau_oclass -nv84_therm_oclass = { +struct nvkm_oclass +g84_therm_oclass = { .handle = NV_SUBDEV(THERM, 0x84), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_therm_ctor, - .dtor = _nouveau_therm_dtor, - .init = nv84_therm_init, - .fini = nv84_therm_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_therm_ctor, + .dtor = _nvkm_therm_dtor, + .init = g84_therm_init, + .fini = g84_therm_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c index b70f7cc649b8..46b7e656a752 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c @@ -21,15 +21,16 @@ * * Authors: Ben Skeggs */ - #include "priv.h" -struct nvd0_therm_priv { - struct nouveau_therm_priv base; +#include <core/device.h> + +struct gf110_therm_priv { + struct nvkm_therm_priv base; }; static int -pwm_info(struct nouveau_therm *therm, int line) +pwm_info(struct nvkm_therm *therm, int line) { u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04)); @@ -53,7 +54,7 @@ pwm_info(struct nouveau_therm *therm, int line) } static int -nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) +gf110_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable) { u32 data = enable ? 0x00000040 : 0x00000000; int indx = pwm_info(therm, line); @@ -66,7 +67,7 @@ nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) } static int -nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) +gf110_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) { int indx = pwm_info(therm, line); if (indx < 0) @@ -87,7 +88,7 @@ nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) } static int -nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) +gf110_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) { int indx = pwm_info(therm, line); if (indx < 0) @@ -103,7 +104,7 @@ nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) } static int -nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line) +gf110_fan_pwm_clock(struct nvkm_therm *therm, int line) { int indx = pwm_info(therm, line); if (indx < 0) @@ -115,12 +116,12 @@ nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line) } int -nvd0_therm_init(struct nouveau_object *object) +gf110_therm_init(struct nvkm_object *object) { - struct nvd0_therm_priv *priv = (void *)object; + struct gf110_therm_priv *priv = (void *)object; int ret; - ret = nouveau_therm_init(&priv->base.base); + ret = nvkm_therm_init(&priv->base.base); if (ret) return ret; @@ -137,38 +138,37 @@ nvd0_therm_init(struct nouveau_object *object) } static int -nvd0_therm_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf110_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvd0_therm_priv *priv; + struct gf110_therm_priv *priv; int ret; - ret = nouveau_therm_create(parent, engine, oclass, &priv); + ret = nvkm_therm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; - nv84_sensor_setup(&priv->base.base); + g84_sensor_setup(&priv->base.base); - priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl; - priv->base.base.pwm_get = nvd0_fan_pwm_get; - priv->base.base.pwm_set = nvd0_fan_pwm_set; - priv->base.base.pwm_clock = nvd0_fan_pwm_clock; - priv->base.base.temp_get = nv84_temp_get; - priv->base.base.fan_sense = nva3_therm_fan_sense; - priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; - return nouveau_therm_preinit(&priv->base.base); + priv->base.base.pwm_ctrl = gf110_fan_pwm_ctrl; + priv->base.base.pwm_get = gf110_fan_pwm_get; + priv->base.base.pwm_set = gf110_fan_pwm_set; + priv->base.base.pwm_clock = gf110_fan_pwm_clock; + priv->base.base.temp_get = g84_temp_get; + priv->base.base.fan_sense = gt215_therm_fan_sense; + priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling; + return nvkm_therm_preinit(&priv->base.base); } -struct nouveau_oclass -nvd0_therm_oclass = { +struct nvkm_oclass +gf110_therm_oclass = { .handle = NV_SUBDEV(THERM, 0xd0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvd0_therm_ctor, - .dtor = _nouveau_therm_dtor, - .init = nvd0_therm_init, - .fini = nv84_therm_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf110_therm_ctor, + .dtor = _nvkm_therm_dtor, + .init = gf110_therm_init, + .fini = g84_therm_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c index 668cf3322285..2fd110f09878 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c @@ -21,22 +21,23 @@ * * Authors: Martin Peres */ - #include "priv.h" +#include <core/device.h> + struct gm107_therm_priv { - struct nouveau_therm_priv base; + struct nvkm_therm_priv base; }; static int -gm107_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) +gm107_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable) { /* nothing to do, it seems hardwired */ return 0; } static int -gm107_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) +gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) { *divs = nv_rd32(therm, 0x10eb20) & 0x1fff; *duty = nv_rd32(therm, 0x10eb24) & 0x1fff; @@ -44,7 +45,7 @@ gm107_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) } static int -gm107_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) +gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) { nv_mask(therm, 0x10eb10, 0x1fff, divs); /* keep the high bits */ nv_wr32(therm, 0x10eb14, duty | 0x80000000); @@ -52,21 +53,20 @@ gm107_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) } static int -gm107_fan_pwm_clock(struct nouveau_therm *therm, int line) +gm107_fan_pwm_clock(struct nvkm_therm *therm, int line) { return nv_device(therm)->crystal * 1000; } static int -gm107_therm_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gm107_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct gm107_therm_priv *priv; int ret; - ret = nouveau_therm_create(parent, engine, oclass, &priv); + ret = nvkm_therm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -75,19 +75,19 @@ gm107_therm_ctor(struct nouveau_object *parent, priv->base.base.pwm_get = gm107_fan_pwm_get; priv->base.base.pwm_set = gm107_fan_pwm_set; priv->base.base.pwm_clock = gm107_fan_pwm_clock; - priv->base.base.temp_get = nv84_temp_get; - priv->base.base.fan_sense = nva3_therm_fan_sense; - priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; - return nouveau_therm_preinit(&priv->base.base); + priv->base.base.temp_get = g84_temp_get; + priv->base.base.fan_sense = gt215_therm_fan_sense; + priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling; + return nvkm_therm_preinit(&priv->base.base); } -struct nouveau_oclass +struct nvkm_oclass gm107_therm_oclass = { .handle = NV_SUBDEV(THERM, 0x117), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm107_therm_ctor, - .dtor = _nouveau_therm_dtor, - .init = nvd0_therm_init, - .fini = nv84_therm_fini, + .dtor = _nvkm_therm_dtor, + .init = gf110_therm_init, + .fini = g84_therm_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c index 7893357a7e9f..e99be20332f2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c @@ -21,17 +21,17 @@ * * Authors: Ben Skeggs */ +#include "priv.h" +#include <core/device.h> #include <subdev/gpio.h> -#include "priv.h" - -struct nva3_therm_priv { - struct nouveau_therm_priv base; +struct gt215_therm_priv { + struct nvkm_therm_priv base; }; int -nva3_therm_fan_sense(struct nouveau_therm *therm) +gt215_therm_fan_sense(struct nvkm_therm *therm) { u32 tach = nv_rd32(therm, 0x00e728) & 0x0000ffff; u32 ctrl = nv_rd32(therm, 0x00e720); @@ -41,17 +41,17 @@ nva3_therm_fan_sense(struct nouveau_therm *therm) } static int -nva3_therm_init(struct nouveau_object *object) +gt215_therm_init(struct nvkm_object *object) { - struct nva3_therm_priv *priv = (void *)object; + struct gt215_therm_priv *priv = (void *)object; struct dcb_gpio_func *tach = &priv->base.fan->tach; int ret; - ret = nouveau_therm_init(&priv->base.base); + ret = nvkm_therm_init(&priv->base.base); if (ret) return ret; - nv84_sensor_setup(&priv->base.base); + g84_sensor_setup(&priv->base.base); /* enable fan tach, count revolutions per-second */ nv_mask(priv, 0x00e720, 0x00000003, 0x00000002); @@ -66,15 +66,14 @@ nva3_therm_init(struct nouveau_object *object) } static int -nva3_therm_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gt215_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nva3_therm_priv *priv; + struct gt215_therm_priv *priv; int ret; - ret = nouveau_therm_create(parent, engine, oclass, &priv); + ret = nvkm_therm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -83,19 +82,19 @@ nva3_therm_ctor(struct nouveau_object *parent, priv->base.base.pwm_get = nv50_fan_pwm_get; priv->base.base.pwm_set = nv50_fan_pwm_set; priv->base.base.pwm_clock = nv50_fan_pwm_clock; - priv->base.base.temp_get = nv84_temp_get; - priv->base.base.fan_sense = nva3_therm_fan_sense; - priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; - return nouveau_therm_preinit(&priv->base.base); + priv->base.base.temp_get = g84_temp_get; + priv->base.base.fan_sense = gt215_therm_fan_sense; + priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling; + return nvkm_therm_preinit(&priv->base.base); } -struct nouveau_oclass -nva3_therm_oclass = { +struct nvkm_oclass +gt215_therm_oclass = { .handle = NV_SUBDEV(THERM, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_therm_ctor, - .dtor = _nouveau_therm_dtor, - .init = nva3_therm_init, - .fini = nv84_therm_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gt215_therm_ctor, + .dtor = _nvkm_therm_dtor, + .init = gt215_therm_init, + .fini = g84_therm_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c index ca9ad9fd47be..09fc4605e853 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c @@ -21,17 +21,16 @@ * * Authors: Martin Peres */ - #include "priv.h" -#include <subdev/i2c.h> #include <subdev/bios/extdev.h> +#include <subdev/i2c.h> static bool -probe_monitoring_device(struct nouveau_i2c_port *i2c, +probe_monitoring_device(struct nvkm_i2c_port *i2c, struct i2c_board_info *info, void *data) { - struct nouveau_therm_priv *priv = data; + struct nvkm_therm_priv *priv = data; struct nvbios_therm_sensor *sensor = &priv->bios_sensor; struct i2c_client *client; @@ -52,11 +51,10 @@ probe_monitoring_device(struct nouveau_i2c_port *i2c, "temp offset %+i C)\n", info->type, info->addr, sensor->offset_constant); priv->ic = client; - return true; } -static struct nouveau_i2c_board_info +static struct nvkm_i2c_board_info nv_board_infos[] = { { { I2C_BOARD_INFO("w83l785ts", 0x2d) }, 0 }, { { I2C_BOARD_INFO("w83781d", 0x2d) }, 0 }, @@ -82,15 +80,15 @@ nv_board_infos[] = { }; void -nouveau_therm_ic_ctor(struct nouveau_therm *therm) +nvkm_therm_ic_ctor(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; - struct nouveau_bios *bios = nouveau_bios(therm); - struct nouveau_i2c *i2c = nouveau_i2c(therm); + struct nvkm_therm_priv *priv = (void *)therm; + struct nvkm_bios *bios = nvkm_bios(therm); + struct nvkm_i2c *i2c = nvkm_i2c(therm); struct nvbios_extdev_func extdev_entry; if (!nvbios_extdev_find(bios, NVBIOS_EXTDEV_LM89, &extdev_entry)) { - struct nouveau_i2c_board_info board[] = { + struct nvkm_i2c_board_info board[] = { { { I2C_BOARD_INFO("lm90", extdev_entry.addr >> 1) }, 0}, { } }; @@ -102,7 +100,7 @@ nouveau_therm_ic_ctor(struct nouveau_therm *therm) } if (!nvbios_extdev_find(bios, NVBIOS_EXTDEV_ADT7473, &extdev_entry)) { - struct nouveau_i2c_board_info board[] = { + struct nvkm_i2c_board_info board[] = { { { I2C_BOARD_INFO("adt7473", extdev_entry.addr >> 1) }, 20 }, { } }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c index 002e51b3af93..8496fffd4688 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c @@ -22,19 +22,20 @@ * Authors: Ben Skeggs * Martin Peres */ - #include "priv.h" +#include <core/device.h> + struct nv40_therm_priv { - struct nouveau_therm_priv base; + struct nvkm_therm_priv base; }; enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 }; static enum nv40_sensor_style -nv40_sensor_style(struct nouveau_therm *therm) +nv40_sensor_style(struct nvkm_therm *therm) { - struct nouveau_device *device = nv_device(therm); + struct nvkm_device *device = nv_device(therm); switch (device->chipset) { case 0x43: @@ -58,7 +59,7 @@ nv40_sensor_style(struct nouveau_therm *therm) } static int -nv40_sensor_setup(struct nouveau_therm *therm) +nv40_sensor_setup(struct nvkm_therm *therm) { enum nv40_sensor_style style = nv40_sensor_style(therm); @@ -77,9 +78,9 @@ nv40_sensor_setup(struct nouveau_therm *therm) } static int -nv40_temp_get(struct nouveau_therm *therm) +nv40_temp_get(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; struct nvbios_therm_sensor *sensor = &priv->bios_sensor; enum nv40_sensor_style style = nv40_sensor_style(therm); int core_temp; @@ -110,7 +111,7 @@ nv40_temp_get(struct nouveau_therm *therm) } static int -nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) +nv40_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable) { u32 mask = enable ? 0x80000000 : 0x0000000; if (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask); @@ -123,7 +124,7 @@ nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) } static int -nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) +nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) { if (line == 2) { u32 reg = nv_rd32(therm, 0x0010f0); @@ -149,7 +150,7 @@ nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) } static int -nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) +nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) { if (line == 2) { nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); @@ -166,9 +167,9 @@ nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) } void -nv40_therm_intr(struct nouveau_subdev *subdev) +nv40_therm_intr(struct nvkm_subdev *subdev) { - struct nouveau_therm *therm = nouveau_therm(subdev); + struct nvkm_therm *therm = nvkm_therm(subdev); uint32_t stat = nv_rd32(therm, 0x1100); /* traitement */ @@ -180,15 +181,15 @@ nv40_therm_intr(struct nouveau_subdev *subdev) } static int -nv40_therm_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_therm_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv40_therm_priv *priv; int ret; - ret = nouveau_therm_create(parent, engine, oclass, &priv); + ret = nvkm_therm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -197,28 +198,28 @@ nv40_therm_ctor(struct nouveau_object *parent, priv->base.base.pwm_get = nv40_fan_pwm_get; priv->base.base.pwm_set = nv40_fan_pwm_set; priv->base.base.temp_get = nv40_temp_get; - priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; + priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling; nv_subdev(priv)->intr = nv40_therm_intr; - return nouveau_therm_preinit(&priv->base.base); + return nvkm_therm_preinit(&priv->base.base); } static int -nv40_therm_init(struct nouveau_object *object) +nv40_therm_init(struct nvkm_object *object) { - struct nouveau_therm *therm = (void *)object; + struct nvkm_therm *therm = (void *)object; nv40_sensor_setup(therm); - return _nouveau_therm_init(object); + return _nvkm_therm_init(object); } -struct nouveau_oclass +struct nvkm_oclass nv40_therm_oclass = { .handle = NV_SUBDEV(THERM, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_therm_ctor, - .dtor = _nouveau_therm_dtor, + .dtor = _nvkm_therm_dtor, .init = nv40_therm_init, - .fini = _nouveau_therm_fini, + .fini = _nvkm_therm_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c index 321db927d638..1ef59e8922d4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c @@ -22,15 +22,16 @@ * Authors: Ben Skeggs * Martin Peres */ - #include "priv.h" +#include <core/device.h> + struct nv50_therm_priv { - struct nouveau_therm_priv base; + struct nvkm_therm_priv base; }; static int -pwm_info(struct nouveau_therm *therm, int *line, int *ctrl, int *indx) +pwm_info(struct nvkm_therm *therm, int *line, int *ctrl, int *indx) { if (*line == 0x04) { *ctrl = 0x00e100; @@ -55,7 +56,7 @@ pwm_info(struct nouveau_therm *therm, int *line, int *ctrl, int *indx) } int -nv50_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) +nv50_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable) { u32 data = enable ? 0x00000001 : 0x00000000; int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); @@ -65,7 +66,7 @@ nv50_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) } int -nv50_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) +nv50_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) { int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); if (ret) @@ -81,7 +82,7 @@ nv50_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) } int -nv50_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) +nv50_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) { int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); if (ret) @@ -93,7 +94,7 @@ nv50_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) } int -nv50_fan_pwm_clock(struct nouveau_therm *therm, int line) +nv50_fan_pwm_clock(struct nvkm_therm *therm, int line) { int chipset = nv_device(therm)->chipset; int crystal = nv_device(therm)->crystal; @@ -119,16 +120,16 @@ nv50_fan_pwm_clock(struct nouveau_therm *therm, int line) } static void -nv50_sensor_setup(struct nouveau_therm *therm) +nv50_sensor_setup(struct nvkm_therm *therm) { nv_mask(therm, 0x20010, 0x40000000, 0x0); mdelay(20); /* wait for the temperature to stabilize */ } static int -nv50_temp_get(struct nouveau_therm *therm) +nv50_temp_get(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; struct nvbios_therm_sensor *sensor = &priv->bios_sensor; int core_temp; @@ -151,15 +152,15 @@ nv50_temp_get(struct nouveau_therm *therm) } static int -nv50_therm_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_therm_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_therm_priv *priv; int ret; - ret = nouveau_therm_create(parent, engine, oclass, &priv); + ret = nvkm_therm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -169,29 +170,29 @@ nv50_therm_ctor(struct nouveau_object *parent, priv->base.base.pwm_set = nv50_fan_pwm_set; priv->base.base.pwm_clock = nv50_fan_pwm_clock; priv->base.base.temp_get = nv50_temp_get; - priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; + priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling; nv_subdev(priv)->intr = nv40_therm_intr; - return nouveau_therm_preinit(&priv->base.base); + return nvkm_therm_preinit(&priv->base.base); } static int -nv50_therm_init(struct nouveau_object *object) +nv50_therm_init(struct nvkm_object *object) { - struct nouveau_therm *therm = (void *)object; + struct nvkm_therm *therm = (void *)object; nv50_sensor_setup(therm); - return _nouveau_therm_init(object); + return _nvkm_therm_init(object); } -struct nouveau_oclass +struct nvkm_oclass nv50_therm_oclass = { .handle = NV_SUBDEV(THERM, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_therm_ctor, - .dtor = _nouveau_therm_dtor, + .dtor = _nvkm_therm_dtor, .init = nv50_therm_init, - .fini = _nouveau_therm_fini, + .fini = _nvkm_therm_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h new file mode 100644 index 000000000000..916a149efe6e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h @@ -0,0 +1,153 @@ +#ifndef __NVTHERM_PRIV_H__ +#define __NVTHERM_PRIV_H__ +/* + * Copyright 2012 The Nouveau community + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Martin Peres + */ +#include <subdev/therm.h> +#include <subdev/bios.h> +#include <subdev/bios/extdev.h> +#include <subdev/bios/gpio.h> +#include <subdev/bios/perf.h> +#include <subdev/bios/therm.h> +#include <subdev/timer.h> + +struct nvkm_fan { + struct nvkm_therm *parent; + const char *type; + + struct nvbios_therm_fan bios; + struct nvbios_perf_fan perf; + + struct nvkm_alarm alarm; + spinlock_t lock; + int percent; + + int (*get)(struct nvkm_therm *); + int (*set)(struct nvkm_therm *, int percent); + + struct dcb_gpio_func tach; +}; + +enum nvkm_therm_thrs_direction { + NVKM_THERM_THRS_FALLING = 0, + NVKM_THERM_THRS_RISING = 1 +}; + +enum nvkm_therm_thrs_state { + NVKM_THERM_THRS_LOWER = 0, + NVKM_THERM_THRS_HIGHER = 1 +}; + +enum nvkm_therm_thrs { + NVKM_THERM_THRS_FANBOOST = 0, + NVKM_THERM_THRS_DOWNCLOCK = 1, + NVKM_THERM_THRS_CRITICAL = 2, + NVKM_THERM_THRS_SHUTDOWN = 3, + NVKM_THERM_THRS_NR +}; + +struct nvkm_therm_priv { + struct nvkm_therm base; + + /* automatic thermal management */ + struct nvkm_alarm alarm; + spinlock_t lock; + struct nvbios_therm_trip_point *last_trip; + int mode; + int cstate; + int suspend; + + /* bios */ + struct nvbios_therm_sensor bios_sensor; + + /* fan priv */ + struct nvkm_fan *fan; + + /* alarms priv */ + struct { + spinlock_t alarm_program_lock; + struct nvkm_alarm therm_poll_alarm; + enum nvkm_therm_thrs_state alarm_state[NVKM_THERM_THRS_NR]; + void (*program_alarms)(struct nvkm_therm *); + } sensor; + + /* what should be done if the card overheats */ + struct { + void (*downclock)(struct nvkm_therm *, bool active); + void (*pause)(struct nvkm_therm *, bool active); + } emergency; + + /* ic */ + struct i2c_client *ic; +}; + +int nvkm_therm_fan_mode(struct nvkm_therm *, int mode); +int nvkm_therm_attr_get(struct nvkm_therm *, enum nvkm_therm_attr_type); +int nvkm_therm_attr_set(struct nvkm_therm *, enum nvkm_therm_attr_type, int); + +void nvkm_therm_ic_ctor(struct nvkm_therm *); + +int nvkm_therm_sensor_ctor(struct nvkm_therm *); + +int nvkm_therm_fan_ctor(struct nvkm_therm *); +int nvkm_therm_fan_init(struct nvkm_therm *); +int nvkm_therm_fan_fini(struct nvkm_therm *, bool suspend); +int nvkm_therm_fan_get(struct nvkm_therm *); +int nvkm_therm_fan_set(struct nvkm_therm *, bool now, int percent); +int nvkm_therm_fan_user_get(struct nvkm_therm *); +int nvkm_therm_fan_user_set(struct nvkm_therm *, int percent); + +int nvkm_therm_fan_sense(struct nvkm_therm *); + +int nvkm_therm_preinit(struct nvkm_therm *); + +int nvkm_therm_sensor_init(struct nvkm_therm *); +int nvkm_therm_sensor_fini(struct nvkm_therm *, bool suspend); +void nvkm_therm_sensor_preinit(struct nvkm_therm *); +void nvkm_therm_sensor_set_threshold_state(struct nvkm_therm *, + enum nvkm_therm_thrs, + enum nvkm_therm_thrs_state); +enum nvkm_therm_thrs_state +nvkm_therm_sensor_get_threshold_state(struct nvkm_therm *, + enum nvkm_therm_thrs); +void nvkm_therm_sensor_event(struct nvkm_therm *, enum nvkm_therm_thrs, + enum nvkm_therm_thrs_direction); +void nvkm_therm_program_alarms_polling(struct nvkm_therm *); + +void nv40_therm_intr(struct nvkm_subdev *); +int nv50_fan_pwm_ctrl(struct nvkm_therm *, int, bool); +int nv50_fan_pwm_get(struct nvkm_therm *, int, u32 *, u32 *); +int nv50_fan_pwm_set(struct nvkm_therm *, int, u32, u32); +int nv50_fan_pwm_clock(struct nvkm_therm *, int); +int g84_temp_get(struct nvkm_therm *); +void g84_sensor_setup(struct nvkm_therm *); +int g84_therm_fini(struct nvkm_object *, bool suspend); + +int gt215_therm_fan_sense(struct nvkm_therm *); + +int gf110_therm_init(struct nvkm_object *); + +int nvkm_fanpwm_create(struct nvkm_therm *, struct dcb_gpio_func *); +int nvkm_fantog_create(struct nvkm_therm *, struct dcb_gpio_func *); +int nvkm_fannil_create(struct nvkm_therm *); +#endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c index 6212537b90c5..aa13744f3854 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/therm/temp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c @@ -21,18 +21,12 @@ * * Authors: Martin Peres */ - #include "priv.h" -#include <core/object.h> -#include <core/device.h> - -#include <subdev/bios.h> - static void -nouveau_therm_temp_set_defaults(struct nouveau_therm *therm) +nvkm_therm_temp_set_defaults(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; priv->bios_sensor.offset_constant = 0; @@ -51,9 +45,9 @@ nouveau_therm_temp_set_defaults(struct nouveau_therm *therm) static void -nouveau_therm_temp_safety_checks(struct nouveau_therm *therm) +nvkm_therm_temp_safety_checks(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; struct nvbios_therm_sensor *s = &priv->bios_sensor; /* enforce a minimum hysteresis on thresholds */ @@ -64,20 +58,21 @@ nouveau_therm_temp_safety_checks(struct nouveau_therm *therm) } /* must be called with alarm_program_lock taken ! */ -void nouveau_therm_sensor_set_threshold_state(struct nouveau_therm *therm, - enum nouveau_therm_thrs thrs, - enum nouveau_therm_thrs_state st) +void +nvkm_therm_sensor_set_threshold_state(struct nvkm_therm *therm, + enum nvkm_therm_thrs thrs, + enum nvkm_therm_thrs_state st) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; priv->sensor.alarm_state[thrs] = st; } /* must be called with alarm_program_lock taken ! */ -enum nouveau_therm_thrs_state -nouveau_therm_sensor_get_threshold_state(struct nouveau_therm *therm, - enum nouveau_therm_thrs thrs) +enum nvkm_therm_thrs_state +nvkm_therm_sensor_get_threshold_state(struct nvkm_therm *therm, + enum nvkm_therm_thrs thrs) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; return priv->sensor.alarm_state[thrs]; } @@ -88,11 +83,11 @@ nv_poweroff_work(struct work_struct *work) kfree(work); } -void nouveau_therm_sensor_event(struct nouveau_therm *therm, - enum nouveau_therm_thrs thrs, - enum nouveau_therm_thrs_direction dir) +void +nvkm_therm_sensor_event(struct nvkm_therm *therm, enum nvkm_therm_thrs thrs, + enum nvkm_therm_thrs_direction dir) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; bool active; const char *thresolds[] = { "fanboost", "downclock", "critical", "shutdown" @@ -102,30 +97,30 @@ void nouveau_therm_sensor_event(struct nouveau_therm *therm, if (thrs < 0 || thrs > 3) return; - if (dir == NOUVEAU_THERM_THRS_FALLING) + if (dir == NVKM_THERM_THRS_FALLING) nv_info(therm, "temperature (%i C) went below the '%s' threshold\n", temperature, thresolds[thrs]); else nv_info(therm, "temperature (%i C) hit the '%s' threshold\n", temperature, thresolds[thrs]); - active = (dir == NOUVEAU_THERM_THRS_RISING); + active = (dir == NVKM_THERM_THRS_RISING); switch (thrs) { - case NOUVEAU_THERM_THRS_FANBOOST: + case NVKM_THERM_THRS_FANBOOST: if (active) { - nouveau_therm_fan_set(therm, true, 100); - nouveau_therm_fan_mode(therm, NOUVEAU_THERM_CTRL_AUTO); + nvkm_therm_fan_set(therm, true, 100); + nvkm_therm_fan_mode(therm, NVKM_THERM_CTRL_AUTO); } break; - case NOUVEAU_THERM_THRS_DOWNCLOCK: + case NVKM_THERM_THRS_DOWNCLOCK: if (priv->emergency.downclock) priv->emergency.downclock(therm, active); break; - case NOUVEAU_THERM_THRS_CRITICAL: + case NVKM_THERM_THRS_CRITICAL: if (priv->emergency.pause) priv->emergency.pause(therm, active); break; - case NOUVEAU_THERM_THRS_SHUTDOWN: + case NVKM_THERM_THRS_SHUTDOWN: if (active) { struct work_struct *work; @@ -136,7 +131,7 @@ void nouveau_therm_sensor_event(struct nouveau_therm *therm, } } break; - case NOUVEAU_THERM_THRS_NR: + case NVKM_THERM_THRS_NR: break; } @@ -144,53 +139,53 @@ void nouveau_therm_sensor_event(struct nouveau_therm *therm, /* must be called with alarm_program_lock taken ! */ static void -nouveau_therm_threshold_hyst_polling(struct nouveau_therm *therm, - const struct nvbios_therm_threshold *thrs, - enum nouveau_therm_thrs thrs_name) +nvkm_therm_threshold_hyst_polling(struct nvkm_therm *therm, + const struct nvbios_therm_threshold *thrs, + enum nvkm_therm_thrs thrs_name) { - enum nouveau_therm_thrs_direction direction; - enum nouveau_therm_thrs_state prev_state, new_state; + enum nvkm_therm_thrs_direction direction; + enum nvkm_therm_thrs_state prev_state, new_state; int temp = therm->temp_get(therm); - prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name); + prev_state = nvkm_therm_sensor_get_threshold_state(therm, thrs_name); - if (temp >= thrs->temp && prev_state == NOUVEAU_THERM_THRS_LOWER) { - direction = NOUVEAU_THERM_THRS_RISING; - new_state = NOUVEAU_THERM_THRS_HIGHER; + if (temp >= thrs->temp && prev_state == NVKM_THERM_THRS_LOWER) { + direction = NVKM_THERM_THRS_RISING; + new_state = NVKM_THERM_THRS_HIGHER; } else if (temp <= thrs->temp - thrs->hysteresis && - prev_state == NOUVEAU_THERM_THRS_HIGHER) { - direction = NOUVEAU_THERM_THRS_FALLING; - new_state = NOUVEAU_THERM_THRS_LOWER; + prev_state == NVKM_THERM_THRS_HIGHER) { + direction = NVKM_THERM_THRS_FALLING; + new_state = NVKM_THERM_THRS_LOWER; } else return; /* nothing to do */ - nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state); - nouveau_therm_sensor_event(therm, thrs_name, direction); + nvkm_therm_sensor_set_threshold_state(therm, thrs_name, new_state); + nvkm_therm_sensor_event(therm, thrs_name, direction); } static void -alarm_timer_callback(struct nouveau_alarm *alarm) +alarm_timer_callback(struct nvkm_alarm *alarm) { - struct nouveau_therm_priv *priv = - container_of(alarm, struct nouveau_therm_priv, sensor.therm_poll_alarm); + struct nvkm_therm_priv *priv = + container_of(alarm, struct nvkm_therm_priv, sensor.therm_poll_alarm); struct nvbios_therm_sensor *sensor = &priv->bios_sensor; - struct nouveau_timer *ptimer = nouveau_timer(priv); - struct nouveau_therm *therm = &priv->base; + struct nvkm_timer *ptimer = nvkm_timer(priv); + struct nvkm_therm *therm = &priv->base; unsigned long flags; spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags); - nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_fan_boost, - NOUVEAU_THERM_THRS_FANBOOST); + nvkm_therm_threshold_hyst_polling(therm, &sensor->thrs_fan_boost, + NVKM_THERM_THRS_FANBOOST); - nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_down_clock, - NOUVEAU_THERM_THRS_DOWNCLOCK); + nvkm_therm_threshold_hyst_polling(therm, &sensor->thrs_down_clock, + NVKM_THERM_THRS_DOWNCLOCK); - nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_critical, - NOUVEAU_THERM_THRS_CRITICAL); + nvkm_therm_threshold_hyst_polling(therm, &sensor->thrs_critical, + NVKM_THERM_THRS_CRITICAL); - nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_shutdown, - NOUVEAU_THERM_THRS_SHUTDOWN); + nvkm_therm_threshold_hyst_polling(therm, &sensor->thrs_shutdown, + NVKM_THERM_THRS_SHUTDOWN); spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags); @@ -200,9 +195,9 @@ alarm_timer_callback(struct nouveau_alarm *alarm) } void -nouveau_therm_program_alarms_polling(struct nouveau_therm *therm) +nvkm_therm_program_alarms_polling(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; struct nvbios_therm_sensor *sensor = &priv->bios_sensor; nv_debug(therm, @@ -217,18 +212,18 @@ nouveau_therm_program_alarms_polling(struct nouveau_therm *therm) } int -nouveau_therm_sensor_init(struct nouveau_therm *therm) +nvkm_therm_sensor_init(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; + struct nvkm_therm_priv *priv = (void *)therm; priv->sensor.program_alarms(therm); return 0; } int -nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend) +nvkm_therm_sensor_fini(struct nvkm_therm *therm, bool suspend) { - struct nouveau_therm_priv *priv = (void *)therm; - struct nouveau_timer *ptimer = nouveau_timer(therm); + struct nvkm_therm_priv *priv = (void *)therm; + struct nvkm_timer *ptimer = nvkm_timer(therm); if (suspend) ptimer->alarm_cancel(ptimer, &priv->sensor.therm_poll_alarm); @@ -236,7 +231,7 @@ nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend) } void -nouveau_therm_sensor_preinit(struct nouveau_therm *therm) +nvkm_therm_sensor_preinit(struct nvkm_therm *therm) { const char *sensor_avail = "yes"; @@ -247,18 +242,18 @@ nouveau_therm_sensor_preinit(struct nouveau_therm *therm) } int -nouveau_therm_sensor_ctor(struct nouveau_therm *therm) +nvkm_therm_sensor_ctor(struct nvkm_therm *therm) { - struct nouveau_therm_priv *priv = (void *)therm; - struct nouveau_bios *bios = nouveau_bios(therm); + struct nvkm_therm_priv *priv = (void *)therm; + struct nvkm_bios *bios = nvkm_bios(therm); - nouveau_alarm_init(&priv->sensor.therm_poll_alarm, alarm_timer_callback); + nvkm_alarm_init(&priv->sensor.therm_poll_alarm, alarm_timer_callback); - nouveau_therm_temp_set_defaults(therm); + nvkm_therm_temp_set_defaults(therm); if (nvbios_therm_sensor_parse(bios, NVBIOS_THERM_DOMAIN_CORE, &priv->bios_sensor)) nv_error(therm, "nvbios_therm_sensor_parse failed\n"); - nouveau_therm_temp_safety_checks(therm); + nvkm_therm_temp_safety_checks(therm); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild new file mode 100644 index 000000000000..d1d38b4ba30a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild @@ -0,0 +1,3 @@ +nvkm-y += nvkm/subdev/timer/base.o +nvkm-y += nvkm/subdev/timer/nv04.o +nvkm-y += nvkm/subdev/timer/gk20a.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c index cf8a0e0f8ee3..d894061ced52 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/timer/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c @@ -21,13 +21,12 @@ * * Authors: Ben Skeggs */ - -#include "subdev/timer.h" +#include <subdev/timer.h> bool -nouveau_timer_wait_eq(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) +nvkm_timer_wait_eq(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) { - struct nouveau_timer *ptimer = nouveau_timer(obj); + struct nvkm_timer *ptimer = nvkm_timer(obj); u64 time0; time0 = ptimer->read(ptimer); @@ -45,9 +44,9 @@ nouveau_timer_wait_eq(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) } bool -nouveau_timer_wait_ne(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) +nvkm_timer_wait_ne(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) { - struct nouveau_timer *ptimer = nouveau_timer(obj); + struct nvkm_timer *ptimer = nvkm_timer(obj); u64 time0; time0 = ptimer->read(ptimer); @@ -65,9 +64,9 @@ nouveau_timer_wait_ne(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) } bool -nouveau_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data) +nvkm_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data) { - struct nouveau_timer *ptimer = nouveau_timer(obj); + struct nvkm_timer *ptimer = nvkm_timer(obj); u64 time0; time0 = ptimer->read(ptimer); @@ -80,15 +79,15 @@ nouveau_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data) } void -nouveau_timer_alarm(void *obj, u32 nsec, struct nouveau_alarm *alarm) +nvkm_timer_alarm(void *obj, u32 nsec, struct nvkm_alarm *alarm) { - struct nouveau_timer *ptimer = nouveau_timer(obj); + struct nvkm_timer *ptimer = nvkm_timer(obj); ptimer->alarm(ptimer, nsec, alarm); } void -nouveau_timer_alarm_cancel(void *obj, struct nouveau_alarm *alarm) +nvkm_timer_alarm_cancel(void *obj, struct nvkm_alarm *alarm) { - struct nouveau_timer *ptimer = nouveau_timer(obj); + struct nvkm_timer *ptimer = nvkm_timer(obj); ptimer->alarm_cancel(ptimer, alarm); } diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c index 37484db1f7fc..80e38063dd9b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c @@ -21,18 +21,17 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" static int -gk20a_timer_init(struct nouveau_object *object) +gk20a_timer_init(struct nvkm_object *object) { struct nv04_timer_priv *priv = (void *)object; u32 hi = upper_32_bits(priv->suspend_time); u32 lo = lower_32_bits(priv->suspend_time); int ret; - ret = nouveau_timer_init(&priv->base); + ret = nvkm_timer_init(&priv->base); if (ret) return ret; @@ -45,10 +44,10 @@ gk20a_timer_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass +struct nvkm_oclass gk20a_timer_oclass = { .handle = NV_SUBDEV(TIMER, 0xff), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_timer_ctor, .dtor = nv04_timer_dtor, .init = gk20a_timer_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c index 240ed0b983a9..6b7facbe59a2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c @@ -21,11 +21,12 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" +#include <core/device.h> + static u64 -nv04_timer_read(struct nouveau_timer *ptimer) +nv04_timer_read(struct nvkm_timer *ptimer) { struct nv04_timer_priv *priv = (void *)ptimer; u32 hi, lo; @@ -39,10 +40,10 @@ nv04_timer_read(struct nouveau_timer *ptimer) } static void -nv04_timer_alarm_trigger(struct nouveau_timer *ptimer) +nv04_timer_alarm_trigger(struct nvkm_timer *ptimer) { struct nv04_timer_priv *priv = (void *)ptimer; - struct nouveau_alarm *alarm, *atemp; + struct nvkm_alarm *alarm, *atemp; unsigned long flags; LIST_HEAD(exec); @@ -71,11 +72,10 @@ nv04_timer_alarm_trigger(struct nouveau_timer *ptimer) } static void -nv04_timer_alarm(struct nouveau_timer *ptimer, u64 time, - struct nouveau_alarm *alarm) +nv04_timer_alarm(struct nvkm_timer *ptimer, u64 time, struct nvkm_alarm *alarm) { struct nv04_timer_priv *priv = (void *)ptimer; - struct nouveau_alarm *list; + struct nvkm_alarm *list; unsigned long flags; alarm->timestamp = ptimer->read(ptimer) + time; @@ -99,8 +99,7 @@ nv04_timer_alarm(struct nouveau_timer *ptimer, u64 time, } static void -nv04_timer_alarm_cancel(struct nouveau_timer *ptimer, - struct nouveau_alarm *alarm) +nv04_timer_alarm_cancel(struct nvkm_timer *ptimer, struct nvkm_alarm *alarm) { struct nv04_timer_priv *priv = (void *)ptimer; unsigned long flags; @@ -110,7 +109,7 @@ nv04_timer_alarm_cancel(struct nouveau_timer *ptimer, } static void -nv04_timer_intr(struct nouveau_subdev *subdev) +nv04_timer_intr(struct nvkm_subdev *subdev) { struct nv04_timer_priv *priv = (void *)subdev; u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0); @@ -128,24 +127,24 @@ nv04_timer_intr(struct nouveau_subdev *subdev) } int -nv04_timer_fini(struct nouveau_object *object, bool suspend) +nv04_timer_fini(struct nvkm_object *object, bool suspend) { struct nv04_timer_priv *priv = (void *)object; if (suspend) priv->suspend_time = nv04_timer_read(&priv->base); nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); - return nouveau_timer_fini(&priv->base, suspend); + return nvkm_timer_fini(&priv->base, suspend); } static int -nv04_timer_init(struct nouveau_object *object) +nv04_timer_init(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); + struct nvkm_device *device = nv_device(object); struct nv04_timer_priv *priv = (void *)object; u32 m = 1, f, n, d, lo, hi; int ret; - ret = nouveau_timer_init(&priv->base); + ret = nvkm_timer_init(&priv->base); if (ret) return ret; @@ -155,7 +154,7 @@ nv04_timer_init(struct nouveau_object *object) /* determine base clock for timer source */ #if 0 /*XXX*/ if (device->chipset < 0x40) { - n = nouveau_hw_get_clock(device, PLL_CORE); + n = nvkm_hw_get_clock(device, PLL_CORE); } else #endif if (device->chipset <= 0x40) { @@ -217,26 +216,25 @@ nv04_timer_init(struct nouveau_object *object) nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); nv_wr32(priv, NV04_PTIMER_TIME_1, hi); nv_wr32(priv, NV04_PTIMER_TIME_0, lo); - return 0; } void -nv04_timer_dtor(struct nouveau_object *object) +nv04_timer_dtor(struct nvkm_object *object) { struct nv04_timer_priv *priv = (void *)object; - return nouveau_timer_destroy(&priv->base); + return nvkm_timer_destroy(&priv->base); } int -nv04_timer_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_timer_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_timer_priv *priv; int ret; - ret = nouveau_timer_create(parent, engine, oclass, &priv); + ret = nvkm_timer_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -252,10 +250,10 @@ nv04_timer_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv04_timer_oclass = { .handle = NV_SUBDEV(TIMER, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_timer_ctor, .dtor = nv04_timer_dtor, .init = nv04_timer_init, diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h index 4bc152697c37..89996a9826b1 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h @@ -1,6 +1,5 @@ #ifndef __NVKM_TIMER_NV04_H__ #define __NVKM_TIMER_NV04_H__ - #include "priv.h" #define NV04_PTIMER_INTR_0 0x009100 @@ -12,16 +11,15 @@ #define NV04_PTIMER_ALARM_0 0x009420 struct nv04_timer_priv { - struct nouveau_timer base; + struct nvkm_timer base; struct list_head alarms; spinlock_t lock; u64 suspend_time; }; -int nv04_timer_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nv04_timer_dtor(struct nouveau_object *); -int nv04_timer_fini(struct nouveau_object *, bool); - +int nv04_timer_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nv04_timer_dtor(struct nvkm_object *); +int nv04_timer_fini(struct nvkm_object *, bool); #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h index 799dae3f2300..08e29a3da188 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/timer/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h @@ -1,6 +1,4 @@ #ifndef __NVKM_TIMER_PRIV_H__ #define __NVKM_TIMER_PRIV_H__ - #include <subdev/timer.h> - #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild new file mode 100644 index 000000000000..6b46ff4213a3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild @@ -0,0 +1,4 @@ +nvkm-y += nvkm/subdev/volt/base.o +nvkm-y += nvkm/subdev/volt/gpio.o +nvkm-y += nvkm/subdev/volt/nv40.o +nvkm-y += nvkm/subdev/volt/gk20a.o diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c index 26ccd8df193f..39f15803f2d4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/volt/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c @@ -21,15 +21,13 @@ * * Authors: Ben Skeggs */ - #include <subdev/volt.h> - #include <subdev/bios.h> #include <subdev/bios/vmap.h> #include <subdev/bios/volt.h> static int -nouveau_volt_get(struct nouveau_volt *volt) +nvkm_volt_get(struct nvkm_volt *volt) { if (volt->vid_get) { int ret = volt->vid_get(volt), i; @@ -46,7 +44,7 @@ nouveau_volt_get(struct nouveau_volt *volt) } static int -nouveau_volt_set(struct nouveau_volt *volt, u32 uv) +nvkm_volt_set(struct nvkm_volt *volt, u32 uv) { if (volt->vid_set) { int i, ret = -EINVAL; @@ -63,9 +61,9 @@ nouveau_volt_set(struct nouveau_volt *volt, u32 uv) } static int -nouveau_volt_map(struct nouveau_volt *volt, u8 id) +nvkm_volt_map(struct nvkm_volt *volt, u8 id) { - struct nouveau_bios *bios = nouveau_bios(volt); + struct nvkm_bios *bios = nvkm_bios(volt); struct nvbios_vmap_entry info; u8 ver, len; u16 vmap; @@ -73,7 +71,7 @@ nouveau_volt_map(struct nouveau_volt *volt, u8 id) vmap = nvbios_vmap_entry_parse(bios, id, &ver, &len, &info); if (vmap) { if (info.link != 0xff) { - int ret = nouveau_volt_map(volt, info.link); + int ret = nvkm_volt_map(volt, info.link); if (ret < 0) return ret; info.min += ret; @@ -85,15 +83,15 @@ nouveau_volt_map(struct nouveau_volt *volt, u8 id) } static int -nouveau_volt_set_id(struct nouveau_volt *volt, u8 id, int condition) +nvkm_volt_set_id(struct nvkm_volt *volt, u8 id, int condition) { - int ret = nouveau_volt_map(volt, id); + int ret = nvkm_volt_map(volt, id); if (ret >= 0) { - int prev = nouveau_volt_get(volt); + int prev = nvkm_volt_get(volt); if (!condition || prev < 0 || (condition < 0 && ret < prev) || (condition > 0 && ret > prev)) { - ret = nouveau_volt_set(volt, ret); + ret = nvkm_volt_set(volt, ret); } else { ret = 0; } @@ -101,8 +99,8 @@ nouveau_volt_set_id(struct nouveau_volt *volt, u8 id, int condition) return ret; } -static void nouveau_volt_parse_bios(struct nouveau_bios *bios, - struct nouveau_volt *volt) +static void +nvkm_volt_parse_bios(struct nvkm_bios *bios, struct nvkm_volt *volt) { struct nvbios_volt_entry ivid; struct nvbios_volt info; @@ -125,7 +123,7 @@ static void nouveau_volt_parse_bios(struct nouveau_bios *bios, } else if (data && info.vidmask) { for (i = 0; i < cnt; i++) { data = nvbios_volt_entry_parse(bios, i, &ver, &hdr, - &ivid); + &ivid); if (data) { volt->vid[volt->vid_nr].uv = ivid.voltage; volt->vid[volt->vid_nr].vid = ivid.vid; @@ -137,12 +135,12 @@ static void nouveau_volt_parse_bios(struct nouveau_bios *bios, } int -_nouveau_volt_init(struct nouveau_object *object) +_nvkm_volt_init(struct nvkm_object *object) { - struct nouveau_volt *volt = (void *)object; + struct nvkm_volt *volt = (void *)object; int ret; - ret = nouveau_subdev_init(&volt->base); + ret = nvkm_subdev_init(&volt->base); if (ret) return ret; @@ -158,34 +156,33 @@ _nouveau_volt_init(struct nouveau_object *object) } void -_nouveau_volt_dtor(struct nouveau_object *object) +_nvkm_volt_dtor(struct nvkm_object *object) { - struct nouveau_volt *volt = (void *)object; - nouveau_subdev_destroy(&volt->base); + struct nvkm_volt *volt = (void *)object; + nvkm_subdev_destroy(&volt->base); } int -nouveau_volt_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) +nvkm_volt_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_bios *bios = nouveau_bios(parent); - struct nouveau_volt *volt; + struct nvkm_bios *bios = nvkm_bios(parent); + struct nvkm_volt *volt; int ret, i; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "VOLT", - "voltage", length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "VOLT", + "voltage", length, pobject); volt = *pobject; if (ret) return ret; - volt->get = nouveau_volt_get; - volt->set = nouveau_volt_set; - volt->set_id = nouveau_volt_set_id; + volt->get = nvkm_volt_get; + volt->set = nvkm_volt_set; + volt->set_id = nvkm_volt_set_id; /* Assuming the non-bios device should build the voltage table later */ if (bios) - nouveau_volt_parse_bios(bios, volt); + nvkm_volt_parse_bios(bios, volt); if (volt->vid_nr) { for (i = 0; i < volt->vid_nr; i++) { @@ -196,10 +193,10 @@ nouveau_volt_create_(struct nouveau_object *parent, /*XXX: this is an assumption.. there probably exists boards * out there with i2c-connected voltage controllers too.. */ - ret = nouveau_voltgpio_init(volt); + ret = nvkm_voltgpio_init(volt); if (ret == 0) { - volt->vid_get = nouveau_voltgpio_get; - volt->vid_set = nouveau_voltgpio_set; + volt->vid_get = nvkm_voltgpio_get; + volt->vid_set = nvkm_voltgpio_set; } } diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c index 717368ef31ac..871fd51011db 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/volt/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c @@ -19,11 +19,10 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - +#include <subdev/volt.h> #ifdef __KERNEL__ #include <nouveau_platform.h> #endif -#include <subdev/volt.h> struct cvb_coef { int c0; @@ -35,7 +34,7 @@ struct cvb_coef { }; struct gk20a_volt_priv { - struct nouveau_volt base; + struct nvkm_volt base; struct regulator *vdd; }; @@ -62,8 +61,7 @@ const struct cvb_coef gk20a_cvb_coef[] = { * cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) */ static inline int -gk20a_volt_get_cvb_voltage(int speedo, int s_scale, - const struct cvb_coef *coef) +gk20a_volt_get_cvb_voltage(int speedo, int s_scale, const struct cvb_coef *coef) { int mv; @@ -79,7 +77,7 @@ gk20a_volt_get_cvb_voltage(int speedo, int s_scale, */ static inline int gk20a_volt_get_cvb_t_voltage(int speedo, int temp, int s_scale, int t_scale, - const struct cvb_coef *coef) + const struct cvb_coef *coef) { int cvb_mv, mv; @@ -103,7 +101,7 @@ gk20a_volt_calc_voltage(const struct cvb_coef *coef, int speedo) } static int -gk20a_volt_vid_get(struct nouveau_volt *volt) +gk20a_volt_vid_get(struct nvkm_volt *volt) { struct gk20a_volt_priv *priv = (void *)volt; int i, uv; @@ -118,7 +116,7 @@ gk20a_volt_vid_get(struct nouveau_volt *volt) } static int -gk20a_volt_vid_set(struct nouveau_volt *volt, u8 vid) +gk20a_volt_vid_set(struct nvkm_volt *volt, u8 vid) { struct gk20a_volt_priv *priv = (void *)volt; @@ -127,7 +125,7 @@ gk20a_volt_vid_set(struct nouveau_volt *volt, u8 vid) } static int -gk20a_volt_set_id(struct nouveau_volt *volt, u8 id, int condition) +gk20a_volt_set_id(struct nvkm_volt *volt, u8 id, int condition) { struct gk20a_volt_priv *priv = (void *)volt; int prev_uv = regulator_get_voltage(priv->vdd); @@ -148,16 +146,16 @@ gk20a_volt_set_id(struct nouveau_volt *volt, u8 id, int condition) } static int -gk20a_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk20a_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct gk20a_volt_priv *priv; - struct nouveau_volt *volt; + struct nvkm_volt *volt; struct nouveau_platform_device *plat; int i, ret, uv; - ret = nouveau_volt_create(parent, engine, oclass, &priv); + ret = nvkm_volt_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -187,13 +185,13 @@ gk20a_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass gk20a_volt_oclass = { .handle = NV_SUBDEV(VOLT, 0xea), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk20a_volt_ctor, - .dtor = _nouveau_volt_dtor, - .init = _nouveau_volt_init, - .fini = _nouveau_volt_fini, + .dtor = _nvkm_volt_dtor, + .init = _nvkm_volt_init, + .fini = _nvkm_volt_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c index 755fa91bcd09..b778deb32d93 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c @@ -21,10 +21,10 @@ * * Authors: Ben Skeggs */ - #include <subdev/volt.h> -#include <subdev/gpio.h> +#include <subdev/bios.h> #include <subdev/bios/gpio.h> +#include <subdev/gpio.h> static const u8 tags[] = { DCB_GPIO_VID0, DCB_GPIO_VID1, DCB_GPIO_VID2, DCB_GPIO_VID3, @@ -32,9 +32,9 @@ static const u8 tags[] = { }; int -nouveau_voltgpio_get(struct nouveau_volt *volt) +nvkm_voltgpio_get(struct nvkm_volt *volt) { - struct nouveau_gpio *gpio = nouveau_gpio(volt); + struct nvkm_gpio *gpio = nvkm_gpio(volt); u8 vid = 0; int i; @@ -51,9 +51,9 @@ nouveau_voltgpio_get(struct nouveau_volt *volt) } int -nouveau_voltgpio_set(struct nouveau_volt *volt, u8 vid) +nvkm_voltgpio_set(struct nvkm_volt *volt, u8 vid) { - struct nouveau_gpio *gpio = nouveau_gpio(volt); + struct nvkm_gpio *gpio = nvkm_gpio(volt); int i; for (i = 0; i < ARRAY_SIZE(tags); i++, vid >>= 1) { @@ -68,9 +68,9 @@ nouveau_voltgpio_set(struct nouveau_volt *volt, u8 vid) } int -nouveau_voltgpio_init(struct nouveau_volt *volt) +nvkm_voltgpio_init(struct nvkm_volt *volt) { - struct nouveau_gpio *gpio = nouveau_gpio(volt); + struct nvkm_gpio *gpio = nvkm_gpio(volt); struct dcb_gpio_func func; int i; diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c index 87d5358376a6..0ac5a3f8c9a8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c @@ -21,22 +21,21 @@ * * Authors: Ben Skeggs */ - #include <subdev/volt.h> struct nv40_volt_priv { - struct nouveau_volt base; + struct nvkm_volt base; }; static int -nv40_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv40_volt_priv *priv; int ret; - ret = nouveau_volt_create(parent, engine, oclass, &priv); + ret = nvkm_volt_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -44,13 +43,13 @@ nv40_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv40_volt_oclass = { .handle = NV_SUBDEV(VOLT, 0x40), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_volt_ctor, - .dtor = _nouveau_volt_dtor, - .init = _nouveau_volt_init, - .fini = _nouveau_volt_fini, + .dtor = _nvkm_volt_dtor, + .init = _nvkm_volt_init, + .fini = _nvkm_volt_fini, }, }; diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index e95385bf8356..6049d245c20e 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -61,6 +61,8 @@ struct panel_desc { unsigned int disable; unsigned int unprepare; } delay; + + u32 bus_format; }; struct panel_simple { @@ -111,6 +113,9 @@ static int panel_simple_get_fixed_modes(struct panel_simple *panel) connector->display_info.bpc = panel->desc->bpc; connector->display_info.width_mm = panel->desc->size.width; connector->display_info.height_mm = panel->desc->size.height; + if (panel->desc->bus_format) + drm_display_info_set_bus_formats(&connector->display_info, + &panel->desc->bus_format, 1); return num; } @@ -558,6 +563,7 @@ static const struct panel_desc foxlink_fl500wvr00_a0t = { .width = 108, .height = 65, }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, }; static const struct drm_display_mode hannstar_hsd070pww1_mode = { diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 12bc21219a0e..c58cfd3c3917 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -2,7 +2,7 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -ccflags-y := -Iinclude/drm +ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include hostprogs-y := mkregtable clean-files := rn50_reg_safe.h r100_reg_safe.h r200_reg_safe.h rv515_reg_safe.h r300_reg_safe.h r420_reg_safe.h rs600_reg_safe.h r600_reg_safe.h evergreen_reg_safe.h cayman_reg_safe.h diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index d59ec491dbb9..ed644a4f6f57 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1851,10 +1851,9 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) return pll; } /* otherwise, pick one of the plls */ - if ((rdev->family == CHIP_KAVERI) || - (rdev->family == CHIP_KABINI) || + if ((rdev->family == CHIP_KABINI) || (rdev->family == CHIP_MULLINS)) { - /* KB/KV/ML has PPLL1 and PPLL2 */ + /* KB/ML has PPLL1 and PPLL2 */ pll_in_use = radeon_get_pll_use_mask(crtc); if (!(pll_in_use & (1 << ATOM_PPLL2))) return ATOM_PPLL2; @@ -1863,7 +1862,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) DRM_ERROR("unable to allocate a PPLL\n"); return ATOM_PPLL_INVALID; } else { - /* CI has PPLL0, PPLL1, and PPLL2 */ + /* CI/KV has PPLL0, PPLL1, and PPLL2 */ pll_in_use = radeon_get_pll_use_mask(crtc); if (!(pll_in_use & (1 << ATOM_PPLL2))) return ATOM_PPLL2; @@ -2155,6 +2154,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) case ATOM_PPLL0: /* disable the ppll */ if ((rdev->family == CHIP_ARUBA) || + (rdev->family == CHIP_KAVERI) || (rdev->family == CHIP_BONAIRE) || (rdev->family == CHIP_HAWAII)) atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 11ba9d21b89b..db42a670f995 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -492,6 +492,10 @@ int radeon_dp_mode_valid_helper(struct drm_connector *connector, struct radeon_connector_atom_dig *dig_connector; int dp_clock; + if ((mode->clock > 340000) && + (!radeon_connector_is_dp12_capable(connector))) + return MODE_CLOCK_HIGH; + if (!radeon_connector->con_priv) return MODE_CLOCK_HIGH; dig_connector = radeon_connector->con_priv; diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 6dcde3798b45..ed336fbfab7c 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -5707,6 +5707,28 @@ void cik_pcie_gart_tlb_flush(struct radeon_device *rdev) WREG32(VM_INVALIDATE_REQUEST, 0x1); } +static void cik_pcie_init_compute_vmid(struct radeon_device *rdev) +{ + int i; + uint32_t sh_mem_bases, sh_mem_config; + + sh_mem_bases = 0x6000 | 0x6000 << 16; + sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED); + sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED); + + mutex_lock(&rdev->srbm_mutex); + for (i = 8; i < 16; i++) { + cik_srbm_select(rdev, 0, 0, 0, i); + /* CP and shaders */ + WREG32(SH_MEM_CONFIG, sh_mem_config); + WREG32(SH_MEM_APE1_BASE, 1); + WREG32(SH_MEM_APE1_LIMIT, 0); + WREG32(SH_MEM_BASES, sh_mem_bases); + } + cik_srbm_select(rdev, 0, 0, 0, 0); + mutex_unlock(&rdev->srbm_mutex); +} + /** * cik_pcie_gart_enable - gart enable * @@ -5820,6 +5842,8 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) cik_srbm_select(rdev, 0, 0, 0, 0); mutex_unlock(&rdev->srbm_mutex); + cik_pcie_init_compute_vmid(rdev); + cik_pcie_gart_tlb_flush(rdev); DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned)(rdev->mc.gtt_size >> 20), @@ -6033,6 +6057,17 @@ void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, radeon_ring_write(ring, 0); radeon_ring_write(ring, 1 << vm_id); + /* wait for the invalidate to complete */ + radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ + WAIT_REG_MEM_FUNCTION(0) | /* always */ + WAIT_REG_MEM_ENGINE(0))); /* me */ + radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 0); /* ref */ + radeon_ring_write(ring, 0); /* mask */ + radeon_ring_write(ring, 0x20); /* poll interval */ + /* compute doesn't have PFP */ if (usepfp) { /* sync PFP to ME, otherwise we might get invalid PFP reads */ diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h index bbb8f2e43637..f667347d8157 100644 --- a/drivers/gpu/drm/radeon/cik_reg.h +++ b/drivers/gpu/drm/radeon/cik_reg.h @@ -184,268 +184,4 @@ #define SDMA0_CNTL 0xD010 #define SDMA1_CNTL 0xD810 -struct cik_mqd { - uint32_t header; - uint32_t compute_dispatch_initiator; - uint32_t compute_dim_x; - uint32_t compute_dim_y; - uint32_t compute_dim_z; - uint32_t compute_start_x; - uint32_t compute_start_y; - uint32_t compute_start_z; - uint32_t compute_num_thread_x; - uint32_t compute_num_thread_y; - uint32_t compute_num_thread_z; - uint32_t compute_pipelinestat_enable; - uint32_t compute_perfcount_enable; - uint32_t compute_pgm_lo; - uint32_t compute_pgm_hi; - uint32_t compute_tba_lo; - uint32_t compute_tba_hi; - uint32_t compute_tma_lo; - uint32_t compute_tma_hi; - uint32_t compute_pgm_rsrc1; - uint32_t compute_pgm_rsrc2; - uint32_t compute_vmid; - uint32_t compute_resource_limits; - uint32_t compute_static_thread_mgmt_se0; - uint32_t compute_static_thread_mgmt_se1; - uint32_t compute_tmpring_size; - uint32_t compute_static_thread_mgmt_se2; - uint32_t compute_static_thread_mgmt_se3; - uint32_t compute_restart_x; - uint32_t compute_restart_y; - uint32_t compute_restart_z; - uint32_t compute_thread_trace_enable; - uint32_t compute_misc_reserved; - uint32_t compute_user_data_0; - uint32_t compute_user_data_1; - uint32_t compute_user_data_2; - uint32_t compute_user_data_3; - uint32_t compute_user_data_4; - uint32_t compute_user_data_5; - uint32_t compute_user_data_6; - uint32_t compute_user_data_7; - uint32_t compute_user_data_8; - uint32_t compute_user_data_9; - uint32_t compute_user_data_10; - uint32_t compute_user_data_11; - uint32_t compute_user_data_12; - uint32_t compute_user_data_13; - uint32_t compute_user_data_14; - uint32_t compute_user_data_15; - uint32_t cp_compute_csinvoc_count_lo; - uint32_t cp_compute_csinvoc_count_hi; - uint32_t cp_mqd_base_addr_lo; - uint32_t cp_mqd_base_addr_hi; - uint32_t cp_hqd_active; - uint32_t cp_hqd_vmid; - uint32_t cp_hqd_persistent_state; - uint32_t cp_hqd_pipe_priority; - uint32_t cp_hqd_queue_priority; - uint32_t cp_hqd_quantum; - uint32_t cp_hqd_pq_base_lo; - uint32_t cp_hqd_pq_base_hi; - uint32_t cp_hqd_pq_rptr; - uint32_t cp_hqd_pq_rptr_report_addr_lo; - uint32_t cp_hqd_pq_rptr_report_addr_hi; - uint32_t cp_hqd_pq_wptr_poll_addr_lo; - uint32_t cp_hqd_pq_wptr_poll_addr_hi; - uint32_t cp_hqd_pq_doorbell_control; - uint32_t cp_hqd_pq_wptr; - uint32_t cp_hqd_pq_control; - uint32_t cp_hqd_ib_base_addr_lo; - uint32_t cp_hqd_ib_base_addr_hi; - uint32_t cp_hqd_ib_rptr; - uint32_t cp_hqd_ib_control; - uint32_t cp_hqd_iq_timer; - uint32_t cp_hqd_iq_rptr; - uint32_t cp_hqd_dequeue_request; - uint32_t cp_hqd_dma_offload; - uint32_t cp_hqd_sema_cmd; - uint32_t cp_hqd_msg_type; - uint32_t cp_hqd_atomic0_preop_lo; - uint32_t cp_hqd_atomic0_preop_hi; - uint32_t cp_hqd_atomic1_preop_lo; - uint32_t cp_hqd_atomic1_preop_hi; - uint32_t cp_hqd_hq_status0; - uint32_t cp_hqd_hq_control0; - uint32_t cp_mqd_control; - uint32_t cp_mqd_query_time_lo; - uint32_t cp_mqd_query_time_hi; - uint32_t cp_mqd_connect_start_time_lo; - uint32_t cp_mqd_connect_start_time_hi; - uint32_t cp_mqd_connect_end_time_lo; - uint32_t cp_mqd_connect_end_time_hi; - uint32_t cp_mqd_connect_end_wf_count; - uint32_t cp_mqd_connect_end_pq_rptr; - uint32_t cp_mqd_connect_end_pq_wptr; - uint32_t cp_mqd_connect_end_ib_rptr; - uint32_t reserved_96; - uint32_t reserved_97; - uint32_t reserved_98; - uint32_t reserved_99; - uint32_t iqtimer_pkt_header; - uint32_t iqtimer_pkt_dw0; - uint32_t iqtimer_pkt_dw1; - uint32_t iqtimer_pkt_dw2; - uint32_t iqtimer_pkt_dw3; - uint32_t iqtimer_pkt_dw4; - uint32_t iqtimer_pkt_dw5; - uint32_t iqtimer_pkt_dw6; - uint32_t reserved_108; - uint32_t reserved_109; - uint32_t reserved_110; - uint32_t reserved_111; - uint32_t queue_doorbell_id0; - uint32_t queue_doorbell_id1; - uint32_t queue_doorbell_id2; - uint32_t queue_doorbell_id3; - uint32_t queue_doorbell_id4; - uint32_t queue_doorbell_id5; - uint32_t queue_doorbell_id6; - uint32_t queue_doorbell_id7; - uint32_t queue_doorbell_id8; - uint32_t queue_doorbell_id9; - uint32_t queue_doorbell_id10; - uint32_t queue_doorbell_id11; - uint32_t queue_doorbell_id12; - uint32_t queue_doorbell_id13; - uint32_t queue_doorbell_id14; - uint32_t queue_doorbell_id15; -}; - -struct cik_sdma_rlc_registers { - uint32_t sdma_rlc_rb_cntl; - uint32_t sdma_rlc_rb_base; - uint32_t sdma_rlc_rb_base_hi; - uint32_t sdma_rlc_rb_rptr; - uint32_t sdma_rlc_rb_wptr; - uint32_t sdma_rlc_rb_wptr_poll_cntl; - uint32_t sdma_rlc_rb_wptr_poll_addr_hi; - uint32_t sdma_rlc_rb_wptr_poll_addr_lo; - uint32_t sdma_rlc_rb_rptr_addr_hi; - uint32_t sdma_rlc_rb_rptr_addr_lo; - uint32_t sdma_rlc_ib_cntl; - uint32_t sdma_rlc_ib_rptr; - uint32_t sdma_rlc_ib_offset; - uint32_t sdma_rlc_ib_base_lo; - uint32_t sdma_rlc_ib_base_hi; - uint32_t sdma_rlc_ib_size; - uint32_t sdma_rlc_skip_cntl; - uint32_t sdma_rlc_context_status; - uint32_t sdma_rlc_doorbell; - uint32_t sdma_rlc_virtual_addr; - uint32_t sdma_rlc_ape1_cntl; - uint32_t sdma_rlc_doorbell_log; - uint32_t reserved_22; - uint32_t reserved_23; - uint32_t reserved_24; - uint32_t reserved_25; - uint32_t reserved_26; - uint32_t reserved_27; - uint32_t reserved_28; - uint32_t reserved_29; - uint32_t reserved_30; - uint32_t reserved_31; - uint32_t reserved_32; - uint32_t reserved_33; - uint32_t reserved_34; - uint32_t reserved_35; - uint32_t reserved_36; - uint32_t reserved_37; - uint32_t reserved_38; - uint32_t reserved_39; - uint32_t reserved_40; - uint32_t reserved_41; - uint32_t reserved_42; - uint32_t reserved_43; - uint32_t reserved_44; - uint32_t reserved_45; - uint32_t reserved_46; - uint32_t reserved_47; - uint32_t reserved_48; - uint32_t reserved_49; - uint32_t reserved_50; - uint32_t reserved_51; - uint32_t reserved_52; - uint32_t reserved_53; - uint32_t reserved_54; - uint32_t reserved_55; - uint32_t reserved_56; - uint32_t reserved_57; - uint32_t reserved_58; - uint32_t reserved_59; - uint32_t reserved_60; - uint32_t reserved_61; - uint32_t reserved_62; - uint32_t reserved_63; - uint32_t reserved_64; - uint32_t reserved_65; - uint32_t reserved_66; - uint32_t reserved_67; - uint32_t reserved_68; - uint32_t reserved_69; - uint32_t reserved_70; - uint32_t reserved_71; - uint32_t reserved_72; - uint32_t reserved_73; - uint32_t reserved_74; - uint32_t reserved_75; - uint32_t reserved_76; - uint32_t reserved_77; - uint32_t reserved_78; - uint32_t reserved_79; - uint32_t reserved_80; - uint32_t reserved_81; - uint32_t reserved_82; - uint32_t reserved_83; - uint32_t reserved_84; - uint32_t reserved_85; - uint32_t reserved_86; - uint32_t reserved_87; - uint32_t reserved_88; - uint32_t reserved_89; - uint32_t reserved_90; - uint32_t reserved_91; - uint32_t reserved_92; - uint32_t reserved_93; - uint32_t reserved_94; - uint32_t reserved_95; - uint32_t reserved_96; - uint32_t reserved_97; - uint32_t reserved_98; - uint32_t reserved_99; - uint32_t reserved_100; - uint32_t reserved_101; - uint32_t reserved_102; - uint32_t reserved_103; - uint32_t reserved_104; - uint32_t reserved_105; - uint32_t reserved_106; - uint32_t reserved_107; - uint32_t reserved_108; - uint32_t reserved_109; - uint32_t reserved_110; - uint32_t reserved_111; - uint32_t reserved_112; - uint32_t reserved_113; - uint32_t reserved_114; - uint32_t reserved_115; - uint32_t reserved_116; - uint32_t reserved_117; - uint32_t reserved_118; - uint32_t reserved_119; - uint32_t reserved_120; - uint32_t reserved_121; - uint32_t reserved_122; - uint32_t reserved_123; - uint32_t reserved_124; - uint32_t reserved_125; - uint32_t reserved_126; - uint32_t reserved_127; - uint32_t sdma_engine_id; - uint32_t sdma_queue_id; -}; - #endif diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c index 1f4ded181662..479519c24a1f 100644 --- a/drivers/gpu/drm/radeon/cik_sdma.c +++ b/drivers/gpu/drm/radeon/cik_sdma.c @@ -932,6 +932,9 @@ void cik_sdma_vm_pad_ib(struct radeon_ib *ib) void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, unsigned vm_id, uint64_t pd_addr) { + u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | + SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ + radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); if (vm_id < 8) { radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); @@ -972,5 +975,12 @@ void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); radeon_ring_write(ring, 1 << vm_id); + + radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); + radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 0); /* reference */ + radeon_ring_write(ring, 0); /* mask */ + radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ } diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index ba85986febea..03003f8a6de6 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -2156,4 +2156,6 @@ #define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu #define ATC_VM_APERTURE1_LOW_ADDR 0x3304u +#define IH_VMID_0_LUT 0x3D40u + #endif diff --git a/drivers/gpu/drm/radeon/dce3_1_afmt.c b/drivers/gpu/drm/radeon/dce3_1_afmt.c index 2fe8cfc966d9..bafdf92a5732 100644 --- a/drivers/gpu/drm/radeon/dce3_1_afmt.c +++ b/drivers/gpu/drm/radeon/dce3_1_afmt.c @@ -103,7 +103,7 @@ static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder) } sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); - if (sad_count < 0) { + if (sad_count <= 0) { DRM_ERROR("Couldn't read SADs: %d\n", sad_count); return; } diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c index 9b42001295ba..e3e9c10cfba9 100644 --- a/drivers/gpu/drm/radeon/kv_dpm.c +++ b/drivers/gpu/drm/radeon/kv_dpm.c @@ -2745,13 +2745,11 @@ int kv_dpm_init(struct radeon_device *rdev) pi->enable_auto_thermal_throttling = true; pi->disable_nb_ps3_in_battery = false; if (radeon_bapm == -1) { - /* There are stability issues reported on with - * bapm enabled on an asrock system. - */ - if (rdev->pdev->subsystem_vendor == 0x1849) - pi->bapm_enable = false; - else + /* only enable bapm on KB, ML by default */ + if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) pi->bapm_enable = true; + else + pi->bapm_enable = false; } else if (radeon_bapm == 0) { pi->bapm_enable = false; } else { diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 360de9f1f491..aea48c89b241 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -2516,6 +2516,16 @@ void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); radeon_ring_write(ring, 1 << vm_id); + /* wait for the invalidate to complete */ + radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ + WAIT_REG_MEM_ENGINE(0))); /* me */ + radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 0); /* ref */ + radeon_ring_write(ring, 0); /* mask */ + radeon_ring_write(ring, 0x20); /* poll interval */ + /* sync PFP to ME, otherwise we might get invalid PFP reads */ radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write(ring, 0x0); diff --git a/drivers/gpu/drm/radeon/ni_dma.c b/drivers/gpu/drm/radeon/ni_dma.c index 50f88611ff60..4be2bb7cbef3 100644 --- a/drivers/gpu/drm/radeon/ni_dma.c +++ b/drivers/gpu/drm/radeon/ni_dma.c @@ -463,5 +463,11 @@ void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); radeon_ring_write(ring, 1 << vm_id); + + /* wait for invalidate to complete */ + radeon_ring_write(ring, DMA_SRBM_READ_PACKET); + radeon_ring_write(ring, (0xff << 20) | (VM_INVALIDATE_REQUEST >> 2)); + radeon_ring_write(ring, 0); /* mask */ + radeon_ring_write(ring, 0); /* value */ } diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h index 2e12e4d69253..ad7125486894 100644 --- a/drivers/gpu/drm/radeon/nid.h +++ b/drivers/gpu/drm/radeon/nid.h @@ -1133,6 +1133,23 @@ #define PACKET3_MEM_SEMAPHORE 0x39 #define PACKET3_MPEG_INDEX 0x3A #define PACKET3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) + /* 0 - always + * 1 - < + * 2 - <= + * 3 - == + * 4 - != + * 5 - >= + * 6 - > + */ +#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) + /* 0 - reg + * 1 - mem + */ +#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) + /* 0 - me + * 1 - pfp + */ #define PACKET3_MEM_WRITE 0x3D #define PACKET3_PFP_SYNC_ME 0x42 #define PACKET3_SURFACE_SYNC 0x43 @@ -1272,6 +1289,13 @@ (1 << 21) | \ (((n) & 0xFFFFF) << 0)) +#define DMA_SRBM_POLL_PACKET ((9 << 28) | \ + (1 << 27) | \ + (1 << 26)) + +#define DMA_SRBM_READ_PACKET ((9 << 28) | \ + (1 << 27)) + /* async DMA Packet types */ #define DMA_PACKET_WRITE 0x2 #define DMA_PACKET_COPY 0x3 diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 850de57069be..121aff6a3b41 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -333,6 +333,20 @@ static struct radeon_asic_ring r300_gfx_ring = { .set_wptr = &r100_gfx_set_wptr, }; +static struct radeon_asic_ring rv515_gfx_ring = { + .ib_execute = &r100_ring_ib_execute, + .emit_fence = &r300_fence_ring_emit, + .emit_semaphore = &r100_semaphore_ring_emit, + .cs_parse = &r300_cs_parse, + .ring_start = &rv515_ring_start, + .ring_test = &r100_ring_test, + .ib_test = &r100_ib_test, + .is_lockup = &r100_gpu_is_lockup, + .get_rptr = &r100_gfx_get_rptr, + .get_wptr = &r100_gfx_get_wptr, + .set_wptr = &r100_gfx_set_wptr, +}; + static struct radeon_asic r300_asic = { .init = &r300_init, .fini = &r300_fini, @@ -748,7 +762,7 @@ static struct radeon_asic rv515_asic = { .set_page = &rv370_pcie_gart_set_page, }, .ring = { - [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring + [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring }, .irq = { .set = &rs600_irq_set, @@ -814,7 +828,7 @@ static struct radeon_asic r520_asic = { .set_page = &rv370_pcie_gart_set_page, }, .ring = { - [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring + [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring }, .irq = { .set = &rs600_irq_set, diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index a46f73737994..d0b4f7d1140d 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -576,7 +576,7 @@ error_unreserve: error_free: drm_free_large(vm_bos); - if (r) + if (r && r != -ERESTARTSYS) DRM_ERROR("Couldn't update BO_VA (%d)\n", r); } diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c index cae11eefecf0..7b274205eeaf 100644 --- a/drivers/gpu/drm/radeon/radeon_kfd.c +++ b/drivers/gpu/drm/radeon/radeon_kfd.c @@ -30,6 +30,7 @@ #include "radeon_kfd.h" #include "radeon_ucode.h" #include <linux/firmware.h> +#include "cik_structs.h" #define CIK_PIPE_PER_MEC (4) @@ -63,15 +64,13 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, unsigned int vmid); -static int kgd_init_memory(struct kgd_dev *kgd); - static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); -static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address, +static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, @@ -89,11 +88,10 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, .program_sh_mem_settings = kgd_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, - .init_memory = kgd_init_memory, .init_pipeline = kgd_init_pipeline, .hqd_load = kgd_hqd_load, .hqd_sdma_load = kgd_hqd_sdma_load, - .hqd_is_occupies = kgd_hqd_is_occupies, + .hqd_is_occupied = kgd_hqd_is_occupied, .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, .hqd_destroy = kgd_hqd_destroy, .hqd_sdma_destroy = kgd_hqd_sdma_destroy, @@ -104,6 +102,7 @@ static const struct kgd2kfd_calls *kgd2kfd; bool radeon_kfd_init(void) { +#if defined(CONFIG_HSA_AMD_MODULE) bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*, const struct kgd2kfd_calls**); @@ -120,6 +119,17 @@ bool radeon_kfd_init(void) } return true; +#elif defined(CONFIG_HSA_AMD) + if (!kgd2kfd_init(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) { + kgd2kfd = NULL; + + return false; + } + + return true; +#else + return false; +#endif } void radeon_kfd_fini(void) @@ -372,41 +382,9 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, cpu_relax(); write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); - return 0; -} - -static int kgd_init_memory(struct kgd_dev *kgd) -{ - /* - * Configure apertures: - * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) - * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) - * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) - */ - int i; - uint32_t sh_mem_bases = PRIVATE_BASE(0x6000) | SHARED_BASE(0x6000); - - for (i = 8; i < 16; i++) { - uint32_t sh_mem_config; - - lock_srbm(kgd, 0, 0, 0, i); - - sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED); - sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED); - - write_register(kgd, SH_MEM_CONFIG, sh_mem_config); - - write_register(kgd, SH_MEM_BASES, sh_mem_bases); - - /* Scratch aperture is not supported for now. */ - write_register(kgd, SH_STATIC_MEM_CONFIG, 0); - - /* APE1 disabled for now. */ - write_register(kgd, SH_MEM_APE1_BASE, 1); - write_register(kgd, SH_MEM_APE1_LIMIT, 0); - - unlock_srbm(kgd); - } + /* Mapping vmid to pasid also for IH block */ + write_register(kgd, IH_VMID_0_LUT + vmid * sizeof(uint32_t), + pasid_mapping); return 0; } @@ -567,7 +545,7 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd) return 0; } -static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address, +static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id) { uint32_t act; @@ -624,6 +602,7 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, if (timeout == 0) { pr_err("kfd: cp queue preemption time out (%dms)\n", temp); + release_queue(kgd); return -ETIME; } msleep(20); diff --git a/drivers/gpu/drm/radeon/radeon_kfd.h b/drivers/gpu/drm/radeon/radeon_kfd.h index f90e161ca507..1103f9082f6b 100644 --- a/drivers/gpu/drm/radeon/radeon_kfd.h +++ b/drivers/gpu/drm/radeon/radeon_kfd.h @@ -29,7 +29,7 @@ #define RADEON_KFD_H_INCLUDED #include <linux/types.h> -#include "../amd/include/kgd_kfd_interface.h" +#include "kgd_kfd_interface.h" struct radeon_device; diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 32522cc940a1..f7da8fe96a66 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -1287,8 +1287,39 @@ dpm_failed: return ret; } +struct radeon_dpm_quirk { + u32 chip_vendor; + u32 chip_device; + u32 subsys_vendor; + u32 subsys_device; +}; + +/* cards with dpm stability problems */ +static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { + /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ + { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, + /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ + { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, + { 0, 0, 0, 0 }, +}; + int radeon_pm_init(struct radeon_device *rdev) { + struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; + bool disable_dpm = false; + + /* Apply dpm quirks */ + while (p && p->chip_device != 0) { + if (rdev->pdev->vendor == p->chip_vendor && + rdev->pdev->device == p->chip_device && + rdev->pdev->subsystem_vendor == p->subsys_vendor && + rdev->pdev->subsystem_device == p->subsys_device) { + disable_dpm = true; + break; + } + ++p; + } + /* enable dpm on rv6xx+ */ switch (rdev->family) { case CHIP_RV610: @@ -1344,6 +1375,8 @@ int radeon_pm_init(struct radeon_device *rdev) (!(rdev->flags & RADEON_IS_IGP)) && (!rdev->smc_fw)) rdev->pm.pm_method = PM_METHOD_PROFILE; + else if (disable_dpm && (radeon_dpm == -1)) + rdev->pm.pm_method = PM_METHOD_PROFILE; else if (radeon_dpm == 0) rdev->pm.pm_method = PM_METHOD_PROFILE; else diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c index 535403e0c8a2..15aee723db77 100644 --- a/drivers/gpu/drm/radeon/radeon_state.c +++ b/drivers/gpu/drm/radeon/radeon_state.c @@ -1703,7 +1703,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, u32 format; u32 *buffer; const u8 __user *data; - int size, dwords, tex_width, blit_width, spitch; + unsigned int size, dwords, tex_width, blit_width, spitch; u32 height; int i; u32 texpitch, microtile; diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 60df444bd075..5d89b874a1a2 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -5057,6 +5057,16 @@ void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, radeon_ring_write(ring, 0); radeon_ring_write(ring, 1 << vm_id); + /* wait for the invalidate to complete */ + radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ + WAIT_REG_MEM_ENGINE(0))); /* me */ + radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 0); /* ref */ + radeon_ring_write(ring, 0); /* mask */ + radeon_ring_write(ring, 0x20); /* poll interval */ + /* sync PFP to ME, otherwise we might get invalid PFP reads */ radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write(ring, 0x0); diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c index f5cc777e1c5f..aa7b872b2c43 100644 --- a/drivers/gpu/drm/radeon/si_dma.c +++ b/drivers/gpu/drm/radeon/si_dma.c @@ -206,6 +206,14 @@ void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); radeon_ring_write(ring, 1 << vm_id); + + /* wait for invalidate to complete */ + radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0)); + radeon_ring_write(ring, VM_INVALIDATE_REQUEST); + radeon_ring_write(ring, 0xff << 16); /* retry */ + radeon_ring_write(ring, 1 << vm_id); /* mask */ + radeon_ring_write(ring, 0); /* value */ + radeon_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ } /** diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index 32e354b8b0ab..eff8a6444956 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -2908,6 +2908,22 @@ static int si_init_smc_spll_table(struct radeon_device *rdev) return ret; } +struct si_dpm_quirk { + u32 chip_vendor; + u32 chip_device; + u32 subsys_vendor; + u32 subsys_device; + u32 max_sclk; + u32 max_mclk; +}; + +/* cards with dpm stability problems */ +static struct si_dpm_quirk si_dpm_quirk_list[] = { + /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ + { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, + { 0, 0, 0, 0 }, +}; + static void si_apply_state_adjust_rules(struct radeon_device *rdev, struct radeon_ps *rps) { @@ -2918,7 +2934,22 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, u32 mclk, sclk; u16 vddc, vddci; u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; + u32 max_sclk = 0, max_mclk = 0; int i; + struct si_dpm_quirk *p = si_dpm_quirk_list; + + /* Apply dpm quirks */ + while (p && p->chip_device != 0) { + if (rdev->pdev->vendor == p->chip_vendor && + rdev->pdev->device == p->chip_device && + rdev->pdev->subsystem_vendor == p->subsys_vendor && + rdev->pdev->subsystem_device == p->subsys_device) { + max_sclk = p->max_sclk; + max_mclk = p->max_mclk; + break; + } + ++p; + } if ((rdev->pm.dpm.new_active_crtc_count > 1) || ni_dpm_vblank_too_short(rdev)) @@ -2972,6 +3003,14 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, if (ps->performance_levels[i].mclk > max_mclk_vddc) ps->performance_levels[i].mclk = max_mclk_vddc; } + if (max_mclk) { + if (ps->performance_levels[i].mclk > max_mclk) + ps->performance_levels[i].mclk = max_mclk; + } + if (max_sclk) { + if (ps->performance_levels[i].sclk > max_sclk) + ps->performance_levels[i].sclk = max_sclk; + } } /* XXX validate the min clocks required for display */ diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 4069be89e585..84999242c747 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h @@ -1632,6 +1632,23 @@ #define PACKET3_MPEG_INDEX 0x3A #define PACKET3_COPY_DW 0x3B #define PACKET3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) + /* 0 - always + * 1 - < + * 2 - <= + * 3 - == + * 4 - != + * 5 - >= + * 6 - > + */ +#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) + /* 0 - reg + * 1 - mem + */ +#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) + /* 0 - me + * 1 - pfp + */ #define PACKET3_MEM_WRITE 0x3D #define PACKET3_COPY_DATA 0x40 #define PACKET3_CP_DMA 0x41 @@ -1835,6 +1852,7 @@ #define DMA_PACKET_TRAP 0x7 #define DMA_PACKET_SRBM_WRITE 0x9 #define DMA_PACKET_CONSTANT_FILL 0xd +#define DMA_PACKET_POLL_REG_MEM 0xe #define DMA_PACKET_NOP 0xf #define VCE_STATUS 0x20004 diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile index 6ba9d27c1b90..f0f1e4ee2d92 100644 --- a/drivers/gpu/drm/sti/Makefile +++ b/drivers/gpu/drm/sti/Makefile @@ -12,6 +12,9 @@ stihdmi-y := sti_hdmi.o \ sti_hdmi_tx3g0c55phy.o \ sti_hdmi_tx3g4c28phy.o \ +stidvo-y := sti_dvo.o \ + sti_awg_utils.o + obj-$(CONFIG_DRM_STI) = \ sti_vtg.o \ sti_vtac.o \ @@ -20,4 +23,5 @@ obj-$(CONFIG_DRM_STI) = \ sti_tvout.o \ sticompositor.o \ sti_hqvdp.o \ + stidvo.o \ sti_drm_drv.o diff --git a/drivers/gpu/drm/sti/sti_awg_utils.c b/drivers/gpu/drm/sti/sti_awg_utils.c new file mode 100644 index 000000000000..9fde3ee8b1a5 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_awg_utils.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) STMicroelectronics SA 2014 + * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include "sti_awg_utils.h" + +#define AWG_OPCODE_OFFSET 10 + +enum opcode { + SET, + RPTSET, + RPLSET, + SKIP, + STOP, + REPEAT, + REPLAY, + JUMP, + HOLD, +}; + +static int awg_generate_instr(enum opcode opcode, + long int arg, + long int mux_sel, + long int data_en, + struct awg_code_generation_params *fwparams) +{ + u32 instruction = 0; + u32 mux = (mux_sel << 8) & 0x1ff; + u32 data_enable = (data_en << 9) & 0x2ff; + long int arg_tmp = arg; + + /* skip, repeat and replay arg should not exceed 1023. + * If user wants to exceed this value, the instruction should be + * duplicate and arg should be adjust for each duplicated instruction. + */ + + while (arg_tmp > 0) { + arg = arg_tmp; + if (fwparams->instruction_offset >= AWG_MAX_INST) { + DRM_ERROR("too many number of instructions\n"); + return -EINVAL; + } + + switch (opcode) { + case SKIP: + /* leave 'arg' + 1 pixel elapsing without changing + * output bus */ + arg--; /* pixel adjustment */ + arg_tmp--; + + if (arg < 0) { + /* SKIP instruction not needed */ + return 0; + } + + if (arg == 0) { + /* SKIP 0 not permitted but we want to skip 1 + * pixel. So we transform SKIP into SET + * instruction */ + opcode = SET; + arg = (arg << 24) >> 24; + arg &= (0x0ff); + break; + } + + mux = 0; + data_enable = 0; + arg = (arg << 22) >> 22; + arg &= (0x3ff); + break; + case REPEAT: + case REPLAY: + if (arg == 0) { + /* REPEAT or REPLAY instruction not needed */ + return 0; + } + + mux = 0; + data_enable = 0; + arg = (arg << 22) >> 22; + arg &= (0x3ff); + break; + case JUMP: + mux = 0; + data_enable = 0; + arg |= 0x40; /* for jump instruction 7th bit is 1 */ + arg = (arg << 22) >> 22; + arg &= 0x3ff; + break; + case STOP: + arg = 0; + break; + case SET: + case RPTSET: + case RPLSET: + case HOLD: + arg = (arg << 24) >> 24; + arg &= (0x0ff); + break; + default: + DRM_ERROR("instruction %d does not exist\n", opcode); + return -EINVAL; + } + + arg_tmp = arg_tmp - arg; + + arg = ((arg + mux) + data_enable); + + instruction = ((opcode) << AWG_OPCODE_OFFSET) | arg; + fwparams->ram_code[fwparams->instruction_offset] = + instruction & (0x3fff); + fwparams->instruction_offset++; + } + return 0; +} + +int sti_awg_generate_code_data_enable_mode( + struct awg_code_generation_params *fwparams, + struct awg_timing *timing) +{ + long int val; + long int data_en; + int ret = 0; + + if (timing->trailing_lines > 0) { + /* skip trailing lines */ + val = timing->blanking_level; + data_en = 0; + ret |= awg_generate_instr(RPLSET, val, 0, data_en, fwparams); + + val = timing->trailing_lines - 1; + data_en = 0; + ret |= awg_generate_instr(REPLAY, val, 0, data_en, fwparams); + } + + if (timing->trailing_pixels > 0) { + /* skip trailing pixel */ + val = timing->blanking_level; + data_en = 0; + ret |= awg_generate_instr(RPLSET, val, 0, data_en, fwparams); + + val = timing->trailing_pixels - 1; + data_en = 0; + ret |= awg_generate_instr(SKIP, val, 0, data_en, fwparams); + } + + /* set DE signal high */ + val = timing->blanking_level; + data_en = 1; + ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, + val, 0, data_en, fwparams); + + if (timing->blanking_pixels > 0) { + /* skip the number of active pixel */ + val = timing->active_pixels - 1; + data_en = 1; + ret |= awg_generate_instr(SKIP, val, 0, data_en, fwparams); + + /* set DE signal low */ + val = timing->blanking_level; + data_en = 0; + ret |= awg_generate_instr(SET, val, 0, data_en, fwparams); + } + + /* replay the sequence as many active lines defined */ + val = timing->active_lines - 1; + data_en = 0; + ret |= awg_generate_instr(REPLAY, val, 0, data_en, fwparams); + + if (timing->blanking_lines > 0) { + /* skip blanking lines */ + val = timing->blanking_level; + data_en = 0; + ret |= awg_generate_instr(RPLSET, val, 0, data_en, fwparams); + + val = timing->blanking_lines - 1; + data_en = 0; + ret |= awg_generate_instr(REPLAY, val, 0, data_en, fwparams); + } + + return ret; +} diff --git a/drivers/gpu/drm/sti/sti_awg_utils.h b/drivers/gpu/drm/sti/sti_awg_utils.h new file mode 100644 index 000000000000..45d599bd570a --- /dev/null +++ b/drivers/gpu/drm/sti/sti_awg_utils.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) STMicroelectronics SA 2014 + * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_AWG_UTILS_H_ +#define _STI_AWG_UTILS_H_ + +#include <drm/drmP.h> + +#define AWG_MAX_INST 64 + +struct awg_code_generation_params { + u32 *ram_code; + u8 instruction_offset; +}; + +struct awg_timing { + u32 total_lines; + u32 active_lines; + u32 blanking_lines; + u32 trailing_lines; + u32 total_pixels; + u32 active_pixels; + u32 blanking_pixels; + u32 trailing_pixels; + u32 blanking_level; +}; + +int sti_awg_generate_code_data_enable_mode( + struct awg_code_generation_params *fw_gen_params, + struct awg_timing *timing); +#endif diff --git a/drivers/gpu/drm/sti/sti_dvo.c b/drivers/gpu/drm/sti/sti_dvo.c new file mode 100644 index 000000000000..651afad21f92 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_dvo.c @@ -0,0 +1,551 @@ +/* + * Copyright (C) STMicroelectronics SA 2014 + * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> + +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_panel.h> + +#include "sti_awg_utils.h" +#include "sti_mixer.h" + +/* DVO registers */ +#define DVO_AWG_DIGSYNC_CTRL 0x0000 +#define DVO_DOF_CFG 0x0004 +#define DVO_LUT_PROG_LOW 0x0008 +#define DVO_LUT_PROG_MID 0x000C +#define DVO_LUT_PROG_HIGH 0x0010 +#define DVO_DIGSYNC_INSTR_I 0x0100 + +#define DVO_AWG_CTRL_EN BIT(0) +#define DVO_AWG_FRAME_BASED_SYNC BIT(2) + +#define DVO_DOF_EN_LOWBYTE BIT(0) +#define DVO_DOF_EN_MIDBYTE BIT(1) +#define DVO_DOF_EN_HIGHBYTE BIT(2) +#define DVO_DOF_EN BIT(6) +#define DVO_DOF_MOD_COUNT_SHIFT 8 + +#define DVO_LUT_ZERO 0 +#define DVO_LUT_Y_G 1 +#define DVO_LUT_Y_G_DEL 2 +#define DVO_LUT_CB_B 3 +#define DVO_LUT_CB_B_DEL 4 +#define DVO_LUT_CR_R 5 +#define DVO_LUT_CR_R_DEL 6 +#define DVO_LUT_HOLD 7 + +struct dvo_config { + u32 flags; + u32 lowbyte; + u32 midbyte; + u32 highbyte; + int (*awg_fwgen_fct)( + struct awg_code_generation_params *fw_gen_params, + struct awg_timing *timing); +}; + +static struct dvo_config rgb_24bit_de_cfg = { + .flags = (0L << DVO_DOF_MOD_COUNT_SHIFT), + .lowbyte = DVO_LUT_CR_R, + .midbyte = DVO_LUT_Y_G, + .highbyte = DVO_LUT_CB_B, + .awg_fwgen_fct = sti_awg_generate_code_data_enable_mode, +}; + +/** + * STI digital video output structure + * + * @dev: driver device + * @drm_dev: pointer to drm device + * @mode: current display mode selected + * @regs: dvo registers + * @clk_pix: pixel clock for dvo + * @clk: clock for dvo + * @clk_main_parent: dvo parent clock if main path used + * @clk_aux_parent: dvo parent clock if aux path used + * @panel_node: panel node reference from device tree + * @panel: reference to the panel connected to the dvo + * @enabled: true if dvo is enabled else false + * @encoder: drm_encoder it is bound + */ +struct sti_dvo { + struct device dev; + struct drm_device *drm_dev; + struct drm_display_mode mode; + void __iomem *regs; + struct clk *clk_pix; + struct clk *clk; + struct clk *clk_main_parent; + struct clk *clk_aux_parent; + struct device_node *panel_node; + struct drm_panel *panel; + struct dvo_config *config; + bool enabled; + struct drm_encoder *encoder; +}; + +struct sti_dvo_connector { + struct drm_connector drm_connector; + struct drm_encoder *encoder; + struct sti_dvo *dvo; +}; + +#define to_sti_dvo_connector(x) \ + container_of(x, struct sti_dvo_connector, drm_connector) + +#define BLANKING_LEVEL 16 +int dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code) +{ + struct drm_display_mode *mode = &dvo->mode; + struct dvo_config *config = dvo->config; + struct awg_code_generation_params fw_gen_params; + struct awg_timing timing; + + fw_gen_params.ram_code = ram_code; + fw_gen_params.instruction_offset = 0; + + timing.total_lines = mode->vtotal; + timing.active_lines = mode->vdisplay; + timing.blanking_lines = mode->vsync_start - mode->vdisplay; + timing.trailing_lines = mode->vtotal - mode->vsync_start; + timing.total_pixels = mode->htotal; + timing.active_pixels = mode->hdisplay; + timing.blanking_pixels = mode->hsync_start - mode->hdisplay; + timing.trailing_pixels = mode->htotal - mode->hsync_start; + timing.blanking_level = BLANKING_LEVEL; + + if (config->awg_fwgen_fct(&fw_gen_params, &timing)) { + DRM_ERROR("AWG firmware not properly generated\n"); + return -EINVAL; + } + + *ram_size = fw_gen_params.instruction_offset; + + return 0; +} + +/* Configure AWG, writing instructions + * + * @dvo: pointer to DVO structure + * @awg_ram_code: pointer to AWG instructions table + * @nb: nb of AWG instructions + */ +static void dvo_awg_configure(struct sti_dvo *dvo, u32 *awg_ram_code, int nb) +{ + int i; + + DRM_DEBUG_DRIVER("\n"); + + for (i = 0; i < nb; i++) + writel(awg_ram_code[i], + dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4); + for (i = nb; i < AWG_MAX_INST; i++) + writel(0, dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4); + + writel(DVO_AWG_CTRL_EN, dvo->regs + DVO_AWG_DIGSYNC_CTRL); +} + +static void sti_dvo_disable(struct drm_bridge *bridge) +{ + struct sti_dvo *dvo = bridge->driver_private; + + if (!dvo->enabled) + return; + + DRM_DEBUG_DRIVER("\n"); + + if (dvo->config->awg_fwgen_fct) + writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL); + + writel(0x00000000, dvo->regs + DVO_DOF_CFG); + + if (dvo->panel) + dvo->panel->funcs->disable(dvo->panel); + + /* Disable/unprepare dvo clock */ + clk_disable_unprepare(dvo->clk_pix); + clk_disable_unprepare(dvo->clk); + + dvo->enabled = false; +} + +static void sti_dvo_pre_enable(struct drm_bridge *bridge) +{ + struct sti_dvo *dvo = bridge->driver_private; + struct dvo_config *config = dvo->config; + u32 val; + + DRM_DEBUG_DRIVER("\n"); + + if (dvo->enabled) + return; + + /* Make sure DVO is disabled */ + writel(0x00000000, dvo->regs + DVO_DOF_CFG); + writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL); + + if (config->awg_fwgen_fct) { + u8 nb_instr; + u32 awg_ram_code[AWG_MAX_INST]; + /* Configure AWG */ + if (!dvo_awg_generate_code(dvo, &nb_instr, awg_ram_code)) + dvo_awg_configure(dvo, awg_ram_code, nb_instr); + else + return; + } + + /* Prepare/enable clocks */ + if (clk_prepare_enable(dvo->clk_pix)) + DRM_ERROR("Failed to prepare/enable dvo_pix clk\n"); + if (clk_prepare_enable(dvo->clk)) + DRM_ERROR("Failed to prepare/enable dvo clk\n"); + + if (dvo->panel) + dvo->panel->funcs->enable(dvo->panel); + + /* Set LUT */ + writel(config->lowbyte, dvo->regs + DVO_LUT_PROG_LOW); + writel(config->midbyte, dvo->regs + DVO_LUT_PROG_MID); + writel(config->highbyte, dvo->regs + DVO_LUT_PROG_HIGH); + + /* Digital output formatter config */ + val = (config->flags | DVO_DOF_EN); + writel(val, dvo->regs + DVO_DOF_CFG); + + dvo->enabled = true; +} + +static void sti_dvo_set_mode(struct drm_bridge *bridge, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct sti_dvo *dvo = bridge->driver_private; + struct sti_mixer *mixer = to_sti_mixer(dvo->encoder->crtc); + int rate = mode->clock * 1000; + struct clk *clkp; + int ret; + + DRM_DEBUG_DRIVER("\n"); + + memcpy(&dvo->mode, mode, sizeof(struct drm_display_mode)); + + /* According to the path used (main or aux), the dvo clocks should + * have a different parent clock. */ + if (mixer->id == STI_MIXER_MAIN) + clkp = dvo->clk_main_parent; + else + clkp = dvo->clk_aux_parent; + + if (clkp) { + clk_set_parent(dvo->clk_pix, clkp); + clk_set_parent(dvo->clk, clkp); + } + + /* DVO clocks = compositor clock */ + ret = clk_set_rate(dvo->clk_pix, rate); + if (ret < 0) { + DRM_ERROR("Cannot set rate (%dHz) for dvo_pix clk\n", rate); + return; + } + + ret = clk_set_rate(dvo->clk, rate); + if (ret < 0) { + DRM_ERROR("Cannot set rate (%dHz) for dvo clk\n", rate); + return; + } + + /* For now, we only support 24bit data enable (DE) synchro format */ + dvo->config = &rgb_24bit_de_cfg; +} + +static void sti_dvo_bridge_nope(struct drm_bridge *bridge) +{ + /* do nothing */ +} + +static void sti_dvo_brigde_destroy(struct drm_bridge *bridge) +{ + drm_bridge_cleanup(bridge); + kfree(bridge); +} + +static const struct drm_bridge_funcs sti_dvo_bridge_funcs = { + .pre_enable = sti_dvo_pre_enable, + .enable = sti_dvo_bridge_nope, + .disable = sti_dvo_disable, + .post_disable = sti_dvo_bridge_nope, + .mode_set = sti_dvo_set_mode, + .destroy = sti_dvo_brigde_destroy, +}; + +static int sti_dvo_connector_get_modes(struct drm_connector *connector) +{ + struct sti_dvo_connector *dvo_connector + = to_sti_dvo_connector(connector); + struct sti_dvo *dvo = dvo_connector->dvo; + + if (dvo->panel) + return dvo->panel->funcs->get_modes(dvo->panel); + + return 0; +} + +#define CLK_TOLERANCE_HZ 50 + +static int sti_dvo_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + int target = mode->clock * 1000; + int target_min = target - CLK_TOLERANCE_HZ; + int target_max = target + CLK_TOLERANCE_HZ; + int result; + struct sti_dvo_connector *dvo_connector + = to_sti_dvo_connector(connector); + struct sti_dvo *dvo = dvo_connector->dvo; + + result = clk_round_rate(dvo->clk_pix, target); + + DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", + target, result); + + if ((result < target_min) || (result > target_max)) { + DRM_DEBUG_DRIVER("dvo pixclk=%d not supported\n", target); + return MODE_BAD; + } + + return MODE_OK; +} + +struct drm_encoder *sti_dvo_best_encoder(struct drm_connector *connector) +{ + struct sti_dvo_connector *dvo_connector + = to_sti_dvo_connector(connector); + + /* Best encoder is the one associated during connector creation */ + return dvo_connector->encoder; +} + +static struct drm_connector_helper_funcs sti_dvo_connector_helper_funcs = { + .get_modes = sti_dvo_connector_get_modes, + .mode_valid = sti_dvo_connector_mode_valid, + .best_encoder = sti_dvo_best_encoder, +}; + +static enum drm_connector_status +sti_dvo_connector_detect(struct drm_connector *connector, bool force) +{ + struct sti_dvo_connector *dvo_connector + = to_sti_dvo_connector(connector); + struct sti_dvo *dvo = dvo_connector->dvo; + + DRM_DEBUG_DRIVER("\n"); + + if (!dvo->panel) + dvo->panel = of_drm_find_panel(dvo->panel_node); + + if (dvo->panel) + if (!drm_panel_attach(dvo->panel, connector)) + return connector_status_connected; + + return connector_status_disconnected; +} + +static void sti_dvo_connector_destroy(struct drm_connector *connector) +{ + struct sti_dvo_connector *dvo_connector + = to_sti_dvo_connector(connector); + + drm_connector_unregister(connector); + drm_connector_cleanup(connector); + kfree(dvo_connector); +} + +static struct drm_connector_funcs sti_dvo_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = sti_dvo_connector_detect, + .destroy = sti_dvo_connector_destroy, +}; + +static struct drm_encoder *sti_dvo_find_encoder(struct drm_device *dev) +{ + struct drm_encoder *encoder; + + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) + return encoder; + } + + return NULL; +} + +static int sti_dvo_bind(struct device *dev, struct device *master, void *data) +{ + struct sti_dvo *dvo = dev_get_drvdata(dev); + struct drm_device *drm_dev = data; + struct drm_encoder *encoder; + struct sti_dvo_connector *connector; + struct drm_connector *drm_connector; + struct drm_bridge *bridge; + int err; + + /* Set the drm device handle */ + dvo->drm_dev = drm_dev; + + encoder = sti_dvo_find_encoder(drm_dev); + if (!encoder) + return -ENOMEM; + + connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); + if (!connector) + return -ENOMEM; + + connector->dvo = dvo; + + bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); + if (!bridge) + return -ENOMEM; + + bridge->driver_private = dvo; + drm_bridge_init(drm_dev, bridge, &sti_dvo_bridge_funcs); + + encoder->bridge = bridge; + connector->encoder = encoder; + dvo->encoder = encoder; + + drm_connector = (struct drm_connector *)connector; + + drm_connector->polled = DRM_CONNECTOR_POLL_HPD; + + drm_connector_init(drm_dev, drm_connector, + &sti_dvo_connector_funcs, DRM_MODE_CONNECTOR_LVDS); + drm_connector_helper_add(drm_connector, + &sti_dvo_connector_helper_funcs); + + err = drm_connector_register(drm_connector); + if (err) + goto err_connector; + + err = drm_mode_connector_attach_encoder(drm_connector, encoder); + if (err) { + DRM_ERROR("Failed to attach a connector to a encoder\n"); + goto err_sysfs; + } + + return 0; + +err_sysfs: + drm_connector_unregister(drm_connector); +err_connector: + drm_bridge_cleanup(bridge); + drm_connector_cleanup(drm_connector); + return -EINVAL; +} + +static void sti_dvo_unbind(struct device *dev, + struct device *master, void *data) +{ + /* do nothing */ +} + +static const struct component_ops sti_dvo_ops = { + .bind = sti_dvo_bind, + .unbind = sti_dvo_unbind, +}; + +static int sti_dvo_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sti_dvo *dvo; + struct resource *res; + struct device_node *np = dev->of_node; + + DRM_INFO("%s\n", __func__); + + dvo = devm_kzalloc(dev, sizeof(*dvo), GFP_KERNEL); + if (!dvo) { + DRM_ERROR("Failed to allocate memory for DVO\n"); + return -ENOMEM; + } + + dvo->dev = pdev->dev; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvo-reg"); + if (!res) { + DRM_ERROR("Invalid dvo resource\n"); + return -ENOMEM; + } + dvo->regs = devm_ioremap_nocache(dev, res->start, + resource_size(res)); + if (IS_ERR(dvo->regs)) + return PTR_ERR(dvo->regs); + + dvo->clk_pix = devm_clk_get(dev, "dvo_pix"); + if (IS_ERR(dvo->clk_pix)) { + DRM_ERROR("Cannot get dvo_pix clock\n"); + return PTR_ERR(dvo->clk_pix); + } + + dvo->clk = devm_clk_get(dev, "dvo"); + if (IS_ERR(dvo->clk)) { + DRM_ERROR("Cannot get dvo clock\n"); + return PTR_ERR(dvo->clk); + } + + dvo->clk_main_parent = devm_clk_get(dev, "main_parent"); + if (IS_ERR(dvo->clk_main_parent)) { + DRM_DEBUG_DRIVER("Cannot get main_parent clock\n"); + dvo->clk_main_parent = NULL; + } + + dvo->clk_aux_parent = devm_clk_get(dev, "aux_parent"); + if (IS_ERR(dvo->clk_aux_parent)) { + DRM_DEBUG_DRIVER("Cannot get aux_parent clock\n"); + dvo->clk_aux_parent = NULL; + } + + dvo->panel_node = of_parse_phandle(np, "sti,panel", 0); + if (!dvo->panel_node) + DRM_ERROR("No panel associated to the dvo output\n"); + + platform_set_drvdata(pdev, dvo); + + return component_add(&pdev->dev, &sti_dvo_ops); +} + +static int sti_dvo_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &sti_dvo_ops); + return 0; +} + +static struct of_device_id dvo_of_match[] = { + { .compatible = "st,stih407-dvo", }, + { /* end node */ } +}; +MODULE_DEVICE_TABLE(of, dvo_of_match); + +struct platform_driver sti_dvo_driver = { + .driver = { + .name = "sti-dvo", + .owner = THIS_MODULE, + .of_match_table = dvo_of_match, + }, + .probe = sti_dvo_probe, + .remove = sti_dvo_remove, +}; + +module_platform_driver(sti_dvo_driver); + +MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); +MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c index cb924aa2b321..5cc53116508e 100644 --- a/drivers/gpu/drm/sti/sti_tvout.c +++ b/drivers/gpu/drm/sti/sti_tvout.c @@ -48,6 +48,9 @@ #define TVO_HDMI_CLIP_VALUE_R_CR 0x514 #define TVO_HDMI_SYNC_SEL 0x518 #define TVO_HDMI_DFV_OBS 0x540 +#define TVO_VIP_DVO 0x600 +#define TVO_DVO_SYNC_SEL 0x618 +#define TVO_DVO_CONFIG 0x620 #define TVO_IN_FMT_SIGNED BIT(0) #define TVO_SYNC_EXT BIT(4) @@ -98,6 +101,9 @@ #define TVO_SYNC_HD_DCS_SHIFT 8 +#define TVO_SYNC_DVO_PAD_HSYNC_SHIFT 8 +#define TVO_SYNC_DVO_PAD_VSYNC_SHIFT 16 + #define ENCODER_CRTC_MASK (BIT(0) | BIT(1)) /* enum listing the supported output data format */ @@ -113,6 +119,7 @@ struct sti_tvout { struct reset_control *reset; struct drm_encoder *hdmi; struct drm_encoder *hda; + struct drm_encoder *dvo; }; struct sti_tvout_encoder { @@ -262,6 +269,66 @@ static void tvout_vip_set_in_vid_fmt(struct sti_tvout *tvout, } /** + * Start VIP block for DVO output + * + * @tvout: pointer on tvout structure + * @main_path: true if main path has to be used in the vip configuration + * else aux path is used. + */ +static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path) +{ + struct device_node *node = tvout->dev->of_node; + bool sel_input_logic_inverted = false; + u32 tvo_in_vid_format; + int val; + + dev_dbg(tvout->dev, "%s\n", __func__); + + if (main_path) { + DRM_DEBUG_DRIVER("main vip for DVO\n"); + /* Select the input sync for dvo = VTG set 4 */ + val = TVO_SYNC_MAIN_VTG_SET_4 << TVO_SYNC_DVO_PAD_VSYNC_SHIFT; + val |= TVO_SYNC_MAIN_VTG_SET_4 << TVO_SYNC_DVO_PAD_HSYNC_SHIFT; + val |= TVO_SYNC_MAIN_VTG_SET_4; + tvout_write(tvout, val, TVO_DVO_SYNC_SEL); + tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT; + } else { + DRM_DEBUG_DRIVER("aux vip for DVO\n"); + /* Select the input sync for dvo = VTG set 4 */ + val = TVO_SYNC_AUX_VTG_SET_4 << TVO_SYNC_DVO_PAD_VSYNC_SHIFT; + val |= TVO_SYNC_AUX_VTG_SET_4 << TVO_SYNC_DVO_PAD_HSYNC_SHIFT; + val |= TVO_SYNC_AUX_VTG_SET_4; + tvout_write(tvout, val, TVO_DVO_SYNC_SEL); + tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT; + } + + /* Set color channel order */ + tvout_vip_set_color_order(tvout, TVO_VIP_DVO, + TVO_VIP_REORDER_CR_R_SEL, + TVO_VIP_REORDER_Y_G_SEL, + TVO_VIP_REORDER_CB_B_SEL); + + /* Set clipping mode (Limited range RGB/Y) */ + tvout_vip_set_clip_mode(tvout, TVO_VIP_DVO, + TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y); + + /* Set round mode (rounded to 8-bit per component) */ + tvout_vip_set_rnd(tvout, TVO_VIP_DVO, TVO_VIP_RND_8BIT_ROUNDED); + + if (of_device_is_compatible(node, "st,stih407-tvout")) { + /* Set input video format */ + tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, + TVO_IN_FMT_SIGNED); + sel_input_logic_inverted = true; + } + + /* Input selection */ + tvout_vip_set_sel_input(tvout, TVO_VIP_DVO, main_path, + sel_input_logic_inverted, + STI_TVOUT_VIDEO_OUT_RGB); +} + +/** * Start VIP block for HDMI output * * @tvout: pointer on tvout structure @@ -402,6 +469,56 @@ static const struct drm_encoder_funcs sti_tvout_encoder_funcs = { .destroy = sti_tvout_encoder_destroy, }; +static void sti_dvo_encoder_commit(struct drm_encoder *encoder) +{ + struct sti_tvout *tvout = to_sti_tvout(encoder); + + tvout_dvo_start(tvout, sti_drm_crtc_is_main(encoder->crtc)); +} + +static void sti_dvo_encoder_disable(struct drm_encoder *encoder) +{ + struct sti_tvout *tvout = to_sti_tvout(encoder); + + /* Reset VIP register */ + tvout_write(tvout, 0x0, TVO_VIP_DVO); +} + +static const struct drm_encoder_helper_funcs sti_dvo_encoder_helper_funcs = { + .dpms = sti_tvout_encoder_dpms, + .mode_fixup = sti_tvout_encoder_mode_fixup, + .mode_set = sti_tvout_encoder_mode_set, + .prepare = sti_tvout_encoder_prepare, + .commit = sti_dvo_encoder_commit, + .disable = sti_dvo_encoder_disable, +}; + +static struct drm_encoder * +sti_tvout_create_dvo_encoder(struct drm_device *dev, + struct sti_tvout *tvout) +{ + struct sti_tvout_encoder *encoder; + struct drm_encoder *drm_encoder; + + encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL); + if (!encoder) + return NULL; + + encoder->tvout = tvout; + + drm_encoder = (struct drm_encoder *)encoder; + + drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; + drm_encoder->possible_clones = 1 << 0; + + drm_encoder_init(dev, drm_encoder, + &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_LVDS); + + drm_encoder_helper_add(drm_encoder, &sti_dvo_encoder_helper_funcs); + + return drm_encoder; +} + static void sti_hda_encoder_commit(struct drm_encoder *encoder) { struct sti_tvout *tvout = to_sti_tvout(encoder); @@ -508,6 +625,7 @@ static void sti_tvout_create_encoders(struct drm_device *dev, { tvout->hdmi = sti_tvout_create_hdmi_encoder(dev, tvout); tvout->hda = sti_tvout_create_hda_encoder(dev, tvout); + tvout->dvo = sti_tvout_create_dvo_encoder(dev, tvout); } static void sti_tvout_destroy_encoders(struct sti_tvout *tvout) diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig index 230b6f887cd8..dfdc26970022 100644 --- a/drivers/hid/Kconfig +++ b/drivers/hid/Kconfig @@ -27,7 +27,8 @@ if HID config HID_BATTERY_STRENGTH bool "Battery level reporting for HID devices" - depends on HID && POWER_SUPPLY && HID = POWER_SUPPLY + depends on HID + select POWER_SUPPLY default n ---help--- This option adds support of reporting battery strength (for HID devices diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index c3d0ac1a0988..8b638792cb43 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -1805,6 +1805,7 @@ static const struct hid_device_id hid_have_special_driver[] = { { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_ERGO_525V) }, { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_I405X) }, { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X) }, + { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2) }, { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X) }, { HID_USB_DEVICE(USB_VENDOR_ID_LABTEC, USB_DEVICE_ID_LABTEC_WIRELESS_KEYBOARD) }, { HID_USB_DEVICE(USB_VENDOR_ID_LCPOWER, USB_DEVICE_ID_LCPOWER_LC1000 ) }, diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index 7460f3402298..9243359c1821 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -526,6 +526,7 @@ #define USB_DEVICE_ID_KYE_GPEN_560 0x5003 #define USB_DEVICE_ID_KYE_EASYPEN_I405X 0x5010 #define USB_DEVICE_ID_KYE_MOUSEPEN_I608X 0x5011 +#define USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2 0x501a #define USB_DEVICE_ID_KYE_EASYPEN_M610X 0x5013 #define USB_VENDOR_ID_LABTEC 0x1020 diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c index e0a0f06ac5ef..9505605b6e22 100644 --- a/drivers/hid/hid-input.c +++ b/drivers/hid/hid-input.c @@ -312,6 +312,9 @@ static const struct hid_device_id hid_battery_quirks[] = { USB_DEVICE_ID_APPLE_ALU_WIRELESS_2011_ANSI), HID_BATTERY_QUIRK_PERCENT | HID_BATTERY_QUIRK_FEATURE }, { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, + USB_DEVICE_ID_APPLE_ALU_WIRELESS_2011_ISO), + HID_BATTERY_QUIRK_PERCENT | HID_BATTERY_QUIRK_FEATURE }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI), HID_BATTERY_QUIRK_PERCENT | HID_BATTERY_QUIRK_FEATURE }, {} diff --git a/drivers/hid/hid-kye.c b/drivers/hid/hid-kye.c index b92bf01a1ae8..158fcf577fae 100644 --- a/drivers/hid/hid-kye.c +++ b/drivers/hid/hid-kye.c @@ -323,6 +323,7 @@ static __u8 *kye_report_fixup(struct hid_device *hdev, __u8 *rdesc, } break; case USB_DEVICE_ID_KYE_MOUSEPEN_I608X: + case USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2: if (*rsize == MOUSEPEN_I608X_RDESC_ORIG_SIZE) { rdesc = mousepen_i608x_rdesc_fixed; *rsize = sizeof(mousepen_i608x_rdesc_fixed); @@ -415,6 +416,7 @@ static int kye_probe(struct hid_device *hdev, const struct hid_device_id *id) switch (id->product) { case USB_DEVICE_ID_KYE_EASYPEN_I405X: case USB_DEVICE_ID_KYE_MOUSEPEN_I608X: + case USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2: case USB_DEVICE_ID_KYE_EASYPEN_M610X: ret = kye_tablet_enable(hdev); if (ret) { @@ -446,6 +448,8 @@ static const struct hid_device_id kye_devices[] = { { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X) }, { HID_USB_DEVICE(USB_VENDOR_ID_KYE, + USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2) }, + { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X) }, { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE) }, diff --git a/drivers/hid/hid-logitech-dj.c b/drivers/hid/hid-logitech-dj.c index c917ab61aafa..5bc6d80d5be7 100644 --- a/drivers/hid/hid-logitech-dj.c +++ b/drivers/hid/hid-logitech-dj.c @@ -962,10 +962,24 @@ static int logi_dj_raw_event(struct hid_device *hdev, switch (data[0]) { case REPORT_ID_DJ_SHORT: + if (size != DJREPORT_SHORT_LENGTH) { + dev_err(&hdev->dev, "DJ report of bad size (%d)", size); + return false; + } return logi_dj_dj_event(hdev, report, data, size); case REPORT_ID_HIDPP_SHORT: - /* intentional fallthrough */ + if (size != HIDPP_REPORT_SHORT_LENGTH) { + dev_err(&hdev->dev, + "Short HID++ report of bad size (%d)", size); + return false; + } + return logi_dj_hidpp_event(hdev, report, data, size); case REPORT_ID_HIDPP_LONG: + if (size != HIDPP_REPORT_LONG_LENGTH) { + dev_err(&hdev->dev, + "Long HID++ report of bad size (%d)", size); + return false; + } return logi_dj_hidpp_event(hdev, report, data, size); } diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c index 2f420c0b6609..a93cefe0e522 100644 --- a/drivers/hid/hid-logitech-hidpp.c +++ b/drivers/hid/hid-logitech-hidpp.c @@ -282,6 +282,33 @@ static inline bool hidpp_report_is_connect_event(struct hidpp_report *report) (report->rap.sub_id == 0x41); } +/** + * hidpp_prefix_name() prefixes the current given name with "Logitech ". + */ +static void hidpp_prefix_name(char **name, int name_length) +{ +#define PREFIX_LENGTH 9 /* "Logitech " */ + + int new_length; + char *new_name; + + if (name_length > PREFIX_LENGTH && + strncmp(*name, "Logitech ", PREFIX_LENGTH) == 0) + /* The prefix has is already in the name */ + return; + + new_length = PREFIX_LENGTH + name_length; + new_name = kzalloc(new_length, GFP_KERNEL); + if (!new_name) + return; + + snprintf(new_name, new_length, "Logitech %s", *name); + + kfree(*name); + + *name = new_name; +} + /* -------------------------------------------------------------------------- */ /* HIDP++ 1.0 commands */ /* -------------------------------------------------------------------------- */ @@ -321,6 +348,10 @@ static char *hidpp_get_unifying_name(struct hidpp_device *hidpp_dev) return NULL; memcpy(name, &response.rap.params[2], len); + + /* include the terminating '\0' */ + hidpp_prefix_name(&name, len + 1); + return name; } @@ -498,6 +529,9 @@ static char *hidpp_get_device_name(struct hidpp_device *hidpp) index += ret; } + /* include the terminating '\0' */ + hidpp_prefix_name(&name, __name_length + 1); + return name; } @@ -794,18 +828,25 @@ static int wtp_raw_event(struct hid_device *hdev, u8 *data, int size) switch (data[0]) { case 0x02: + if (size < 2) { + hid_err(hdev, "Received HID report of bad size (%d)", + size); + return 1; + } if (hidpp->quirks & HIDPP_QUIRK_WTP_PHYSICAL_BUTTONS) { input_event(wd->input, EV_KEY, BTN_LEFT, !!(data[1] & 0x01)); input_event(wd->input, EV_KEY, BTN_RIGHT, !!(data[1] & 0x02)); input_sync(wd->input); + return 0; } else { if (size < 21) return 1; return wtp_mouse_raw_xy_event(hidpp, &data[7]); } case REPORT_ID_HIDPP_LONG: + /* size is already checked in hidpp_raw_event. */ if ((report->fap.feature_index != wd->mt_feature_index) || (report->fap.funcindex_clientid != EVENT_TOUCHPAD_RAW_XY)) return 1; diff --git a/drivers/hid/hid-roccat-pyra.c b/drivers/hid/hid-roccat-pyra.c index 1a07e07d99a0..47d7e74231e5 100644 --- a/drivers/hid/hid-roccat-pyra.c +++ b/drivers/hid/hid-roccat-pyra.c @@ -35,6 +35,8 @@ static struct class *pyra_class; static void profile_activated(struct pyra_device *pyra, unsigned int new_profile) { + if (new_profile >= ARRAY_SIZE(pyra->profile_settings)) + return; pyra->actual_profile = new_profile; pyra->actual_cpi = pyra->profile_settings[pyra->actual_profile].y_cpi; } @@ -257,9 +259,11 @@ static ssize_t pyra_sysfs_write_settings(struct file *fp, if (off != 0 || count != PYRA_SIZE_SETTINGS) return -EINVAL; - mutex_lock(&pyra->pyra_lock); - settings = (struct pyra_settings const *)buf; + if (settings->startup_profile >= ARRAY_SIZE(pyra->profile_settings)) + return -EINVAL; + + mutex_lock(&pyra->pyra_lock); retval = pyra_set_settings(usb_dev, settings); if (retval) { diff --git a/drivers/hid/i2c-hid/i2c-hid.c b/drivers/hid/i2c-hid/i2c-hid.c index d32037cbf9db..d43e967e7533 100644 --- a/drivers/hid/i2c-hid/i2c-hid.c +++ b/drivers/hid/i2c-hid/i2c-hid.c @@ -706,12 +706,7 @@ static int i2c_hid_start(struct hid_device *hid) static void i2c_hid_stop(struct hid_device *hid) { - struct i2c_client *client = hid->driver_data; - struct i2c_hid *ihid = i2c_get_clientdata(client); - hid->claimed = 0; - - i2c_hid_free_buffers(ihid); } static int i2c_hid_open(struct hid_device *hid) diff --git a/drivers/hid/usbhid/hid-quirks.c b/drivers/hid/usbhid/hid-quirks.c index dc89be90b35e..b27b3d33ebab 100644 --- a/drivers/hid/usbhid/hid-quirks.c +++ b/drivers/hid/usbhid/hid-quirks.c @@ -124,6 +124,7 @@ static const struct hid_blacklist { { USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_WIRELESS, HID_QUIRK_MULTI_INPUT }, { USB_VENDOR_ID_SIGMA_MICRO, USB_DEVICE_ID_SIGMA_MICRO_KEYBOARD, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X, HID_QUIRK_MULTI_INPUT }, + { USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2, HID_QUIRK_MULTI_INPUT }, { USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X, HID_QUIRK_MULTI_INPUT }, { USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_DUOSENSE, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD, HID_QUIRK_NO_INIT_REPORTS }, diff --git a/drivers/iio/adc/ad799x.c b/drivers/iio/adc/ad799x.c index e37412da15f5..b99de00e57b8 100644 --- a/drivers/iio/adc/ad799x.c +++ b/drivers/iio/adc/ad799x.c @@ -143,9 +143,15 @@ static int ad799x_write_config(struct ad799x_state *st, u16 val) case ad7998: return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG, val); - default: + case ad7992: + case ad7993: + case ad7994: return i2c_smbus_write_byte_data(st->client, AD7998_CONF_REG, val); + default: + /* Will be written when doing a conversion */ + st->config = val; + return 0; } } @@ -155,8 +161,13 @@ static int ad799x_read_config(struct ad799x_state *st) case ad7997: case ad7998: return i2c_smbus_read_word_swapped(st->client, AD7998_CONF_REG); - default: + case ad7992: + case ad7993: + case ad7994: return i2c_smbus_read_byte_data(st->client, AD7998_CONF_REG); + default: + /* No readback support */ + return st->config; } } diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c index 866fe904cba2..90c8cb727cc7 100644 --- a/drivers/iio/inkern.c +++ b/drivers/iio/inkern.c @@ -449,6 +449,9 @@ static int iio_channel_read(struct iio_channel *chan, int *val, int *val2, if (val2 == NULL) val2 = &unused; + if(!iio_channel_has_info(chan->channel, info)) + return -EINVAL; + if (chan->indio_dev->info->read_raw_multi) { ret = chan->indio_dev->info->read_raw_multi(chan->indio_dev, chan->channel, INDIO_MAX_RAW_ELEMENTS, diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c index 57ecc5b204f3..9117b7a2d5f8 100644 --- a/drivers/infiniband/hw/mlx4/main.c +++ b/drivers/infiniband/hw/mlx4/main.c @@ -1114,7 +1114,8 @@ static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_ struct mlx4_dev *dev = to_mdev(qp->device)->dev; int err = 0; - if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) + if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || + dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) return 0; /* do nothing */ ib_flow = flow_attr + 1; diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c index f2b978026407..77ecf6d32237 100644 --- a/drivers/input/mouse/elantech.c +++ b/drivers/input/mouse/elantech.c @@ -1520,6 +1520,8 @@ static int elantech_set_properties(struct elantech_data *etd) case 7: case 8: case 9: + case 10: + case 13: etd->hw_version = 4; break; default: diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index c66d1b53843e..764857b4e268 100644 --- a/drivers/input/serio/i8042-x86ia64io.h +++ b/drivers/input/serio/i8042-x86ia64io.h @@ -415,6 +415,13 @@ static const struct dmi_system_id __initconst i8042_dmi_nomux_table[] = { }, }, { + /* Acer Aspire 7738 */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Acer"), + DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 7738"), + }, + }, + { /* Gericom Bellagio */ .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Gericom"), @@ -745,6 +752,35 @@ static const struct dmi_system_id __initconst i8042_dmi_dritek_table[] = { { } }; +/* + * Some laptops need keyboard reset before probing for the trackpad to get + * it detected, initialised & finally work. + */ +static const struct dmi_system_id __initconst i8042_dmi_kbdreset_table[] = { + { + /* Gigabyte P35 v2 - Elantech touchpad */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "GIGABYTE"), + DMI_MATCH(DMI_PRODUCT_NAME, "P35V2"), + }, + }, + { + /* Aorus branded Gigabyte X3 Plus - Elantech touchpad */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "GIGABYTE"), + DMI_MATCH(DMI_PRODUCT_NAME, "X3"), + }, + }, + { + /* Gigabyte P34 - Elantech touchpad */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "GIGABYTE"), + DMI_MATCH(DMI_PRODUCT_NAME, "P34"), + }, + }, + { } +}; + #endif /* CONFIG_X86 */ #ifdef CONFIG_PNP @@ -1040,6 +1076,9 @@ static int __init i8042_platform_init(void) if (dmi_check_system(i8042_dmi_dritek_table)) i8042_dritek = true; + if (dmi_check_system(i8042_dmi_kbdreset_table)) + i8042_kbdreset = true; + /* * A20 was already enabled during early kernel init. But some buggy * BIOSes (in MSI Laptops) require A20 to be enabled using 8042 to diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c index 924e4bf357fb..986a71c614b0 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c @@ -67,6 +67,10 @@ static bool i8042_notimeout; module_param_named(notimeout, i8042_notimeout, bool, 0); MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); +static bool i8042_kbdreset; +module_param_named(kbdreset, i8042_kbdreset, bool, 0); +MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); + #ifdef CONFIG_X86 static bool i8042_dritek; module_param_named(dritek, i8042_dritek, bool, 0); @@ -790,6 +794,16 @@ static int __init i8042_check_aux(void) return -1; /* + * Reset keyboard (needed on some laptops to successfully detect + * touchpad, e.g., some Gigabyte laptop models with Elantech + * touchpads). + */ + if (i8042_kbdreset) { + pr_warn("Attempting to reset device connected to KBD port\n"); + i8042_kbd_write(NULL, (unsigned char) 0xff); + } + +/* * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and * used it for a PCI card or somethig else. */ diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 1232336b960e..40dfbc0444c0 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -4029,14 +4029,6 @@ static int device_notifier(struct notifier_block *nb, if (action != BUS_NOTIFY_REMOVED_DEVICE) return 0; - /* - * If the device is still attached to a device driver we can't - * tear down the domain yet as DMA mappings may still be in use. - * Wait for the BUS_NOTIFY_UNBOUND_DRIVER event to do that. - */ - if (action == BUS_NOTIFY_DEL_DEVICE && dev->driver != NULL) - return 0; - domain = find_domain(dev); if (!domain) return 0; @@ -4428,6 +4420,10 @@ static int intel_iommu_attach_device(struct iommu_domain *domain, domain_remove_one_dev_info(old_domain, dev); else domain_remove_dev_info(old_domain); + + if (!domain_type_is_vm_or_si(old_domain) && + list_empty(&old_domain->devices)) + domain_exit(old_domain); } } diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index 68dfb0fd5ee9..748693192c20 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -558,7 +558,7 @@ static pmd_t *ipmmu_alloc_pmd(struct ipmmu_vmsa_device *mmu, pgd_t *pgd, static u64 ipmmu_page_prot(unsigned int prot, u64 type) { - u64 pgprot = ARM_VMSA_PTE_XN | ARM_VMSA_PTE_nG | ARM_VMSA_PTE_AF + u64 pgprot = ARM_VMSA_PTE_nG | ARM_VMSA_PTE_AF | ARM_VMSA_PTE_SH_IS | ARM_VMSA_PTE_AP_UNPRIV | ARM_VMSA_PTE_NS | type; @@ -568,8 +568,8 @@ static u64 ipmmu_page_prot(unsigned int prot, u64 type) if (prot & IOMMU_CACHE) pgprot |= IMMAIR_ATTR_IDX_WBRWA << ARM_VMSA_PTE_ATTRINDX_SHIFT; - if (prot & IOMMU_EXEC) - pgprot &= ~ARM_VMSA_PTE_XN; + if (prot & IOMMU_NOEXEC) + pgprot |= ARM_VMSA_PTE_XN; else if (!(prot & (IOMMU_READ | IOMMU_WRITE))) /* If no access create a faulting entry to avoid TLB fills. */ pgprot &= ~ARM_VMSA_PTE_PAGE; diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index b2023af384b9..6a8b1ec4a48a 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -1009,7 +1009,6 @@ static struct platform_driver rk_iommu_driver = { .remove = rk_iommu_remove, .driver = { .name = "rk_iommu", - .owner = THIS_MODULE, .of_match_table = of_match_ptr(rk_iommu_dt_ids), }, }; diff --git a/drivers/isdn/hardware/eicon/message.c b/drivers/isdn/hardware/eicon/message.c index a82e542ffc21..0b380603a578 100644 --- a/drivers/isdn/hardware/eicon/message.c +++ b/drivers/isdn/hardware/eicon/message.c @@ -4880,7 +4880,7 @@ static void sig_ind(PLCI *plci) byte SS_Ind[] = "\x05\x02\x00\x02\x00\x00"; /* Hold_Ind struct*/ byte CF_Ind[] = "\x09\x02\x00\x06\x00\x00\x00\x00\x00\x00"; byte Interr_Err_Ind[] = "\x0a\x02\x00\x07\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"; - byte CONF_Ind[] = "\x09\x16\x00\x06\x00\x00\0x00\0x00\0x00\0x00"; + byte CONF_Ind[] = "\x09\x16\x00\x06\x00\x00\x00\x00\x00\x00"; byte force_mt_info = false; byte dir; dword d; diff --git a/drivers/leds/leds-netxbig.c b/drivers/leds/leds-netxbig.c index 26515c27ea8c..25e419752a7b 100644 --- a/drivers/leds/leds-netxbig.c +++ b/drivers/leds/leds-netxbig.c @@ -330,18 +330,18 @@ create_netxbig_led(struct platform_device *pdev, led_dat->sata = 0; led_dat->cdev.brightness = LED_OFF; led_dat->cdev.flags |= LED_CORE_SUSPENDRESUME; - /* - * If available, expose the SATA activity blink capability through - * a "sata" sysfs attribute. - */ - if (led_dat->mode_val[NETXBIG_LED_SATA] != NETXBIG_LED_INVALID_MODE) - led_dat->cdev.groups = netxbig_led_groups; led_dat->mode_addr = template->mode_addr; led_dat->mode_val = template->mode_val; led_dat->bright_addr = template->bright_addr; led_dat->bright_max = (1 << pdata->gpio_ext->num_data) - 1; led_dat->timer = pdata->timer; led_dat->num_timer = pdata->num_timer; + /* + * If available, expose the SATA activity blink capability through + * a "sata" sysfs attribute. + */ + if (led_dat->mode_val[NETXBIG_LED_SATA] != NETXBIG_LED_INVALID_MODE) + led_dat->cdev.groups = netxbig_led_groups; return led_classdev_register(&pdev->dev, &led_dat->cdev); } diff --git a/drivers/mcb/mcb-internal.h b/drivers/mcb/mcb-internal.h index f956ef26c0ce..fb7493dcfb79 100644 --- a/drivers/mcb/mcb-internal.h +++ b/drivers/mcb/mcb-internal.h @@ -7,6 +7,7 @@ #define PCI_DEVICE_ID_MEN_CHAMELEON 0x4d45 #define CHAMELEON_FILENAME_LEN 12 #define CHAMELEONV2_MAGIC 0xabce +#define CHAM_HEADER_SIZE 0x200 enum chameleon_descriptor_type { CHAMELEON_DTYPE_GENERAL = 0x0, diff --git a/drivers/mcb/mcb-pci.c b/drivers/mcb/mcb-pci.c index b59181965643..5e1bd5db02c8 100644 --- a/drivers/mcb/mcb-pci.c +++ b/drivers/mcb/mcb-pci.c @@ -17,6 +17,7 @@ struct priv { struct mcb_bus *bus; + phys_addr_t mapbase; void __iomem *base; }; @@ -31,8 +32,8 @@ static int mcb_pci_get_irq(struct mcb_device *mdev) static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { + struct resource *res; struct priv *priv; - phys_addr_t mapbase; int ret; int num_cells; unsigned long flags; @@ -47,19 +48,21 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return -ENODEV; } - mapbase = pci_resource_start(pdev, 0); - if (!mapbase) { + priv->mapbase = pci_resource_start(pdev, 0); + if (!priv->mapbase) { dev_err(&pdev->dev, "No PCI resource\n"); goto err_start; } - ret = pci_request_region(pdev, 0, KBUILD_MODNAME); - if (ret) { - dev_err(&pdev->dev, "Failed to request PCI BARs\n"); + res = request_mem_region(priv->mapbase, CHAM_HEADER_SIZE, + KBUILD_MODNAME); + if (IS_ERR(res)) { + dev_err(&pdev->dev, "Failed to request PCI memory\n"); + ret = PTR_ERR(res); goto err_start; } - priv->base = pci_iomap(pdev, 0, 0); + priv->base = ioremap(priv->mapbase, CHAM_HEADER_SIZE); if (!priv->base) { dev_err(&pdev->dev, "Cannot ioremap\n"); ret = -ENOMEM; @@ -84,7 +87,7 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) priv->bus->get_irq = mcb_pci_get_irq; - ret = chameleon_parse_cells(priv->bus, mapbase, priv->base); + ret = chameleon_parse_cells(priv->bus, priv->mapbase, priv->base); if (ret < 0) goto err_drvdata; num_cells = ret; @@ -93,8 +96,10 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) mcb_bus_add_devices(priv->bus); + return 0; + err_drvdata: - pci_iounmap(pdev, priv->base); + iounmap(priv->base); err_ioremap: pci_release_region(pdev, 0); err_start: @@ -107,6 +112,10 @@ static void mcb_pci_remove(struct pci_dev *pdev) struct priv *priv = pci_get_drvdata(pdev); mcb_release_bus(priv->bus); + + iounmap(priv->base); + release_region(priv->mapbase, CHAM_HEADER_SIZE); + pci_disable_device(pdev); } static const struct pci_device_id mcb_pci_tbl[] = { diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c index 52a0c2f6264f..ae498b53ee40 100644 --- a/drivers/mfd/da9052-core.c +++ b/drivers/mfd/da9052-core.c @@ -554,7 +554,8 @@ int da9052_device_init(struct da9052 *da9052, u8 chip_id) return ret; } - ret = mfd_add_devices(da9052->dev, -1, da9052_subdev_info, + ret = mfd_add_devices(da9052->dev, PLATFORM_DEVID_AUTO, + da9052_subdev_info, ARRAY_SIZE(da9052_subdev_info), NULL, 0, NULL); if (ret) { dev_err(da9052->dev, "mfd_add_devices failed: %d\n", ret); diff --git a/drivers/mfd/rtsx_usb.c b/drivers/mfd/rtsx_usb.c index dbdd0faeb6ce..210d1f85679e 100644 --- a/drivers/mfd/rtsx_usb.c +++ b/drivers/mfd/rtsx_usb.c @@ -681,21 +681,9 @@ static void rtsx_usb_disconnect(struct usb_interface *intf) #ifdef CONFIG_PM static int rtsx_usb_suspend(struct usb_interface *intf, pm_message_t message) { - struct rtsx_ucr *ucr = - (struct rtsx_ucr *)usb_get_intfdata(intf); - dev_dbg(&intf->dev, "%s called with pm message 0x%04x\n", __func__, message.event); - /* - * Call to make sure LED is off during suspend to save more power. - * It is NOT a permanent state and could be turned on anytime later. - * Thus no need to call turn_on when resunming. - */ - mutex_lock(&ucr->dev_mutex); - rtsx_usb_turn_off_led(ucr); - mutex_unlock(&ucr->dev_mutex); - return 0; } diff --git a/drivers/mfd/tps65218.c b/drivers/mfd/tps65218.c index 0d256cb002eb..d6b764349f9d 100644 --- a/drivers/mfd/tps65218.c +++ b/drivers/mfd/tps65218.c @@ -125,10 +125,21 @@ int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg, } EXPORT_SYMBOL_GPL(tps65218_clear_bits); +static const struct regmap_range tps65218_yes_ranges[] = { + regmap_reg_range(TPS65218_REG_INT1, TPS65218_REG_INT2), + regmap_reg_range(TPS65218_REG_STATUS, TPS65218_REG_STATUS), +}; + +static const struct regmap_access_table tps65218_volatile_table = { + .yes_ranges = tps65218_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(tps65218_yes_ranges), +}; + static struct regmap_config tps65218_regmap_config = { .reg_bits = 8, .val_bits = 8, .cache_type = REGCACHE_RBTREE, + .volatile_table = &tps65218_volatile_table, }; static const struct regmap_irq tps65218_irqs[] = { @@ -193,6 +204,7 @@ static struct regmap_irq_chip tps65218_irq_chip = { .num_regs = 2, .mask_base = TPS65218_REG_INT_MASK1, + .status_base = TPS65218_REG_INT1, }; static const struct of_device_id of_tps65218_match_table[] = { diff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c index 51fd6b524371..d1b55fe62817 100644 --- a/drivers/misc/cxl/context.c +++ b/drivers/misc/cxl/context.c @@ -100,6 +100,46 @@ int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master, return 0; } +static int cxl_mmap_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ + struct cxl_context *ctx = vma->vm_file->private_data; + unsigned long address = (unsigned long)vmf->virtual_address; + u64 area, offset; + + offset = vmf->pgoff << PAGE_SHIFT; + + pr_devel("%s: pe: %i address: 0x%lx offset: 0x%llx\n", + __func__, ctx->pe, address, offset); + + if (ctx->afu->current_mode == CXL_MODE_DEDICATED) { + area = ctx->afu->psn_phys; + if (offset > ctx->afu->adapter->ps_size) + return VM_FAULT_SIGBUS; + } else { + area = ctx->psn_phys; + if (offset > ctx->psn_size) + return VM_FAULT_SIGBUS; + } + + mutex_lock(&ctx->status_mutex); + + if (ctx->status != STARTED) { + mutex_unlock(&ctx->status_mutex); + pr_devel("%s: Context not started, failing problem state access\n", __func__); + return VM_FAULT_SIGBUS; + } + + vm_insert_pfn(vma, address, (area + offset) >> PAGE_SHIFT); + + mutex_unlock(&ctx->status_mutex); + + return VM_FAULT_NOPAGE; +} + +static const struct vm_operations_struct cxl_mmap_vmops = { + .fault = cxl_mmap_fault, +}; + /* * Map a per-context mmio space into the given vma. */ @@ -108,26 +148,25 @@ int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma) u64 len = vma->vm_end - vma->vm_start; len = min(len, ctx->psn_size); - if (ctx->afu->current_mode == CXL_MODE_DEDICATED) { - vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - return vm_iomap_memory(vma, ctx->afu->psn_phys, ctx->afu->adapter->ps_size); - } + if (ctx->afu->current_mode != CXL_MODE_DEDICATED) { + /* make sure there is a valid per process space for this AFU */ + if ((ctx->master && !ctx->afu->psa) || (!ctx->afu->pp_psa)) { + pr_devel("AFU doesn't support mmio space\n"); + return -EINVAL; + } - /* make sure there is a valid per process space for this AFU */ - if ((ctx->master && !ctx->afu->psa) || (!ctx->afu->pp_psa)) { - pr_devel("AFU doesn't support mmio space\n"); - return -EINVAL; + /* Can't mmap until the AFU is enabled */ + if (!ctx->afu->enabled) + return -EBUSY; } - /* Can't mmap until the AFU is enabled */ - if (!ctx->afu->enabled) - return -EBUSY; - pr_devel("%s: mmio physical: %llx pe: %i master:%i\n", __func__, ctx->psn_phys, ctx->pe , ctx->master); + vma->vm_flags |= VM_IO | VM_PFNMAP; vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - return vm_iomap_memory(vma, ctx->psn_phys, len); + vma->vm_ops = &cxl_mmap_vmops; + return 0; } /* @@ -150,12 +189,6 @@ static void __detach_context(struct cxl_context *ctx) afu_release_irqs(ctx); flush_work(&ctx->fault_work); /* Only needed for dedicated process */ wake_up_all(&ctx->wq); - - /* Release Problem State Area mapping */ - mutex_lock(&ctx->mapping_lock); - if (ctx->mapping) - unmap_mapping_range(ctx->mapping, 0, 0, 1); - mutex_unlock(&ctx->mapping_lock); } /* @@ -184,6 +217,17 @@ void cxl_context_detach_all(struct cxl_afu *afu) * created and torn down after the IDR removed */ __detach_context(ctx); + + /* + * We are force detaching - remove any active PSA mappings so + * userspace cannot interfere with the card if it comes back. + * Easiest way to exercise this is to unbind and rebind the + * driver via sysfs while it is in use. + */ + mutex_lock(&ctx->mapping_lock); + if (ctx->mapping) + unmap_mapping_range(ctx->mapping, 0, 0, 1); + mutex_unlock(&ctx->mapping_lock); } mutex_unlock(&afu->contexts_lock); } diff --git a/drivers/misc/cxl/file.c b/drivers/misc/cxl/file.c index e9f2f10dbb37..b15d8113877c 100644 --- a/drivers/misc/cxl/file.c +++ b/drivers/misc/cxl/file.c @@ -140,18 +140,20 @@ static long afu_ioctl_start_work(struct cxl_context *ctx, pr_devel("%s: pe: %i\n", __func__, ctx->pe); - mutex_lock(&ctx->status_mutex); - if (ctx->status != OPENED) { - rc = -EIO; - goto out; - } - + /* Do this outside the status_mutex to avoid a circular dependency with + * the locking in cxl_mmap_fault() */ if (copy_from_user(&work, uwork, sizeof(struct cxl_ioctl_start_work))) { rc = -EFAULT; goto out; } + mutex_lock(&ctx->status_mutex); + if (ctx->status != OPENED) { + rc = -EIO; + goto out; + } + /* * if any of the reserved fields are set or any of the unused * flags are set it's invalid diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index ff2755062b44..06ff0a2ec960 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -234,6 +234,18 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) struct mei_me_hw *hw = to_me_hw(dev); u32 hcsr = mei_hcsr_read(hw); + /* H_RST may be found lit before reset is started, + * for example if preceding reset flow hasn't completed. + * In that case asserting H_RST will be ignored, therefore + * we need to clean H_RST bit to start a successful reset sequence. + */ + if ((hcsr & H_RST) == H_RST) { + dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); + hcsr &= ~H_RST; + mei_me_reg_write(hw, H_CSR, hcsr); + hcsr = mei_hcsr_read(hw); + } + hcsr |= H_RST | H_IG | H_IS; if (intr_enable) diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c index e3e56d35f0ee..970314e0aac8 100644 --- a/drivers/mmc/host/sdhci-acpi.c +++ b/drivers/mmc/host/sdhci-acpi.c @@ -247,6 +247,7 @@ static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = { { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd }, { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio }, { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio }, + { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio }, { "PNP0D40" }, { }, }; @@ -257,6 +258,7 @@ static const struct acpi_device_id sdhci_acpi_ids[] = { { "INT33BB" }, { "INT33C6" }, { "INT3436" }, + { "INT344D" }, { "PNP0D40" }, { }, }; diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c index 03427755b902..4f38554ce679 100644 --- a/drivers/mmc/host/sdhci-pci.c +++ b/drivers/mmc/host/sdhci-pci.c @@ -993,6 +993,31 @@ static const struct pci_device_id pci_ids[] = { .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc, }, + + { + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, + }, + + { + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, + }, + + { + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_SPT_SD, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, + }, + { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8120, diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index d57c3d169914..1ec684d06d54 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -21,6 +21,9 @@ #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 +#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b +#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c +#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d /* * PCI registers diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 45238871192d..ca3424e7ef71 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -300,13 +300,6 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) if (IS_ERR(host)) return PTR_ERR(host); - if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) { - ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info()); - if (ret < 0) - goto err_mbus_win; - } - - pltfm_host = sdhci_priv(host); pltfm_host->priv = pxa; @@ -325,6 +318,12 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) if (!IS_ERR(pxa->clk_core)) clk_prepare_enable(pxa->clk_core); + if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) { + ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info()); + if (ret < 0) + goto err_mbus_win; + } + /* enable 1/8V DDR capable */ host->mmc->caps |= MMC_CAP_1_8V_DDR; @@ -396,11 +395,11 @@ err_add_host: pm_runtime_disable(&pdev->dev); err_of_parse: err_cd_req: +err_mbus_win: clk_disable_unprepare(pxa->clk_io); if (!IS_ERR(pxa->clk_core)) clk_disable_unprepare(pxa->clk_core); err_clk_get: -err_mbus_win: sdhci_pltfm_free(pdev); return ret; } diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index cbb245b58538..f1a488ee432f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -259,8 +259,6 @@ static void sdhci_reinit(struct sdhci_host *host) del_timer_sync(&host->tuning_timer); host->flags &= ~SDHCI_NEEDS_RETUNING; - host->mmc->max_blk_count = - (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; } sdhci_enable_card_detection(host); } @@ -1273,6 +1271,12 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, spin_unlock_irq(&host->lock); mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); spin_lock_irq(&host->lock); + + if (mode != MMC_POWER_OFF) + sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); + else + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + return; } @@ -1353,6 +1357,8 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) sdhci_runtime_pm_get(host); + present = mmc_gpio_get_cd(host->mmc); + spin_lock_irqsave(&host->lock, flags); WARN_ON(host->mrq != NULL); @@ -1381,7 +1387,6 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) * zero: cd-gpio is used, and card is removed * one: cd-gpio is used, and card is present */ - present = mmc_gpio_get_cd(host->mmc); if (present < 0) { /* If polling, assume that the card is always present. */ if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) @@ -1880,6 +1885,18 @@ static int sdhci_card_busy(struct mmc_host *mmc) return !(present_state & SDHCI_DATA_LVL_MASK); } +static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + host->flags |= SDHCI_HS400_TUNING; + spin_unlock_irqrestore(&host->lock, flags); + + return 0; +} + static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) { struct sdhci_host *host = mmc_priv(mmc); @@ -1887,10 +1904,18 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) int tuning_loop_counter = MAX_TUNING_LOOP; int err = 0; unsigned long flags; + unsigned int tuning_count = 0; + bool hs400_tuning; sdhci_runtime_pm_get(host); spin_lock_irqsave(&host->lock, flags); + hs400_tuning = host->flags & SDHCI_HS400_TUNING; + host->flags &= ~SDHCI_HS400_TUNING; + + if (host->tuning_mode == SDHCI_TUNING_MODE_1) + tuning_count = host->tuning_count; + /* * The Host Controller needs tuning only in case of SDR104 mode * and for SDR50 mode when Use Tuning for SDR50 is set in the @@ -1899,8 +1924,20 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) * tuning function has to be executed. */ switch (host->timing) { + /* HS400 tuning is done in HS200 mode */ case MMC_TIMING_MMC_HS400: + err = -EINVAL; + goto out_unlock; + case MMC_TIMING_MMC_HS200: + /* + * Periodic re-tuning for HS400 is not expected to be needed, so + * disable it here. + */ + if (hs400_tuning) + tuning_count = 0; + break; + case MMC_TIMING_UHS_SDR104: break; @@ -1911,9 +1948,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) /* FALLTHROUGH */ default: - spin_unlock_irqrestore(&host->lock, flags); - sdhci_runtime_pm_put(host); - return 0; + goto out_unlock; } if (host->ops->platform_execute_tuning) { @@ -2037,24 +2072,11 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) } out: - /* - * If this is the very first time we are here, we start the retuning - * timer. Since only during the first time, SDHCI_NEEDS_RETUNING - * flag won't be set, we check this condition before actually starting - * the timer. - */ - if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && - (host->tuning_mode == SDHCI_TUNING_MODE_1)) { + host->flags &= ~SDHCI_NEEDS_RETUNING; + + if (tuning_count) { host->flags |= SDHCI_USING_RETUNING_TIMER; - mod_timer(&host->tuning_timer, jiffies + - host->tuning_count * HZ); - /* Tuning mode 1 limits the maximum data length to 4MB */ - mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; - } else if (host->flags & SDHCI_USING_RETUNING_TIMER) { - host->flags &= ~SDHCI_NEEDS_RETUNING; - /* Reload the new initial value for timer */ - mod_timer(&host->tuning_timer, jiffies + - host->tuning_count * HZ); + mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ); } /* @@ -2070,6 +2092,7 @@ out: sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); +out_unlock: spin_unlock_irqrestore(&host->lock, flags); sdhci_runtime_pm_put(host); @@ -2110,15 +2133,18 @@ static void sdhci_card_event(struct mmc_host *mmc) { struct sdhci_host *host = mmc_priv(mmc); unsigned long flags; + int present; /* First check if client has provided their own card event */ if (host->ops->card_event) host->ops->card_event(host); + present = sdhci_do_get_cd(host); + spin_lock_irqsave(&host->lock, flags); /* Check host->mrq first in case we are runtime suspended */ - if (host->mrq && !sdhci_do_get_cd(host)) { + if (host->mrq && !present) { pr_err("%s: Card removed during transfer!\n", mmc_hostname(host->mmc)); pr_err("%s: Resetting controller.\n", @@ -2142,6 +2168,7 @@ static const struct mmc_host_ops sdhci_ops = { .hw_reset = sdhci_hw_reset, .enable_sdio_irq = sdhci_enable_sdio_irq, .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, + .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, .execute_tuning = sdhci_execute_tuning, .card_event = sdhci_card_event, .card_busy = sdhci_card_busy, @@ -3260,8 +3287,9 @@ int sdhci_add_host(struct sdhci_host *host) mmc->max_segs = SDHCI_MAX_SEGS; /* - * Maximum number of sectors in one transfer. Limited by DMA boundary - * size (512KiB). + * Maximum number of sectors in one transfer. Limited by SDMA boundary + * size (512KiB). Note some tuning modes impose a 4MiB limit, but this + * is less anyway. */ mmc->max_req_size = 524288; diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c index f363972cd77d..e36d10520e24 100644 --- a/drivers/net/can/c_can/c_can_platform.c +++ b/drivers/net/can/c_can/c_can_platform.c @@ -103,27 +103,34 @@ static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable) mask = 1 << raminit->bits.start | 1 << raminit->bits.done; regmap_read(raminit->syscon, raminit->reg, &ctrl); - /* We clear the done and start bit first. The start bit is + /* We clear the start bit first. The start bit is * looking at the 0 -> transition, but is not self clearing; - * And we clear the init done bit as well. * NOTE: DONE must be written with 1 to clear it. + * We can't clear the DONE bit here using regmap_update_bits() + * as it will bypass the write if initial condition is START:0 DONE:1 + * e.g. on DRA7 which needs START pulse. */ - ctrl &= ~(1 << raminit->bits.start); - ctrl |= 1 << raminit->bits.done; - regmap_write(raminit->syscon, raminit->reg, ctrl); + ctrl &= ~mask; /* START = 0, DONE = 0 */ + regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); - ctrl &= ~(1 << raminit->bits.done); - c_can_hw_raminit_wait_syscon(priv, mask, ctrl); + /* check if START bit is 0. Ignore DONE bit for now + * as it can be either 0 or 1. + */ + c_can_hw_raminit_wait_syscon(priv, 1 << raminit->bits.start, ctrl); if (enable) { - /* Set start bit and wait for the done bit. */ + /* Clear DONE bit & set START bit. */ ctrl |= 1 << raminit->bits.start; - regmap_write(raminit->syscon, raminit->reg, ctrl); - + /* DONE must be written with 1 to clear it */ + ctrl |= 1 << raminit->bits.done; + regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); + /* prevent further clearing of DONE bit */ + ctrl &= ~(1 << raminit->bits.done); /* clear START bit if start pulse is needed */ if (raminit->needs_pulse) { ctrl &= ~(1 << raminit->bits.start); - regmap_write(raminit->syscon, raminit->reg, ctrl); + regmap_update_bits(raminit->syscon, raminit->reg, + mask, ctrl); } ctrl |= 1 << raminit->bits.done; diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c index 3ec8f6f25e5f..847c1f813261 100644 --- a/drivers/net/can/dev.c +++ b/drivers/net/can/dev.c @@ -807,10 +807,14 @@ static int can_changelink(struct net_device *dev, if (dev->flags & IFF_UP) return -EBUSY; cm = nla_data(data[IFLA_CAN_CTRLMODE]); - if (cm->flags & ~priv->ctrlmode_supported) + + /* check whether changed bits are allowed to be modified */ + if (cm->mask & ~priv->ctrlmode_supported) return -EOPNOTSUPP; + + /* clear bits to be modified and copy the flag values */ priv->ctrlmode &= ~cm->mask; - priv->ctrlmode |= cm->flags; + priv->ctrlmode |= (cm->flags & cm->mask); /* CAN_CTRLMODE_FD can only be set when driver supports FD */ if (priv->ctrlmode & CAN_CTRLMODE_FD) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index d7bc462aafdc..244529881be9 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -955,6 +955,11 @@ static struct net_device *alloc_m_can_dev(void) priv->can.data_bittiming_const = &m_can_data_bittiming_const; priv->can.do_set_mode = m_can_set_mode; priv->can.do_get_berr_counter = m_can_get_berr_counter; + + /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.1 */ + priv->can.ctrlmode = CAN_CTRLMODE_FD_NON_ISO; + + /* CAN_CTRLMODE_FD_NON_ISO can not be changed with M_CAN IP v3.0.1 */ priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING | diff --git a/drivers/net/can/usb/kvaser_usb.c b/drivers/net/can/usb/kvaser_usb.c index 541fb7a05625..c32cd61073bc 100644 --- a/drivers/net/can/usb/kvaser_usb.c +++ b/drivers/net/can/usb/kvaser_usb.c @@ -520,10 +520,10 @@ static void kvaser_usb_tx_acknowledge(const struct kvaser_usb *dev, skb = alloc_can_err_skb(priv->netdev, &cf); if (skb) { cf->can_id |= CAN_ERR_RESTARTED; - netif_rx(skb); stats->rx_packets++; stats->rx_bytes += cf->can_dlc; + netif_rx(skb); } else { netdev_err(priv->netdev, "No memory left for err_skb\n"); @@ -770,10 +770,9 @@ static void kvaser_usb_rx_error(const struct kvaser_usb *dev, priv->can.state = new_state; - netif_rx(skb); - stats->rx_packets++; stats->rx_bytes += cf->can_dlc; + netif_rx(skb); } static void kvaser_usb_rx_can_err(const struct kvaser_usb_net_priv *priv, @@ -805,10 +804,9 @@ static void kvaser_usb_rx_can_err(const struct kvaser_usb_net_priv *priv, stats->rx_over_errors++; stats->rx_errors++; - netif_rx(skb); - stats->rx_packets++; stats->rx_bytes += cf->can_dlc; + netif_rx(skb); } } @@ -887,10 +885,9 @@ static void kvaser_usb_rx_can_msg(const struct kvaser_usb *dev, cf->can_dlc); } - netif_rx(skb); - stats->rx_packets++; stats->rx_bytes += cf->can_dlc; + netif_rx(skb); } static void kvaser_usb_start_chip_reply(const struct kvaser_usb *dev, @@ -1246,6 +1243,9 @@ static int kvaser_usb_close(struct net_device *netdev) if (err) netdev_warn(netdev, "Cannot stop device, error %d\n", err); + /* reset tx contexts */ + kvaser_usb_unlink_tx_urbs(priv); + priv->can.state = CAN_STATE_STOPPED; close_candev(priv->netdev); @@ -1294,12 +1294,14 @@ static netdev_tx_t kvaser_usb_start_xmit(struct sk_buff *skb, if (!urb) { netdev_err(netdev, "No memory left for URBs\n"); stats->tx_dropped++; - goto nourbmem; + dev_kfree_skb(skb); + return NETDEV_TX_OK; } buf = kmalloc(sizeof(struct kvaser_msg), GFP_ATOMIC); if (!buf) { stats->tx_dropped++; + dev_kfree_skb(skb); goto nobufmem; } @@ -1334,6 +1336,7 @@ static netdev_tx_t kvaser_usb_start_xmit(struct sk_buff *skb, } } + /* This should never happen; it implies a flow control bug */ if (!context) { netdev_warn(netdev, "cannot find free context\n"); ret = NETDEV_TX_BUSY; @@ -1364,9 +1367,6 @@ static netdev_tx_t kvaser_usb_start_xmit(struct sk_buff *skb, if (unlikely(err)) { can_free_echo_skb(netdev, context->echo_index); - skb = NULL; /* set to NULL to avoid double free in - * dev_kfree_skb(skb) */ - atomic_dec(&priv->active_tx_urbs); usb_unanchor_urb(urb); @@ -1388,8 +1388,6 @@ releasebuf: kfree(buf); nobufmem: usb_free_urb(urb); -nourbmem: - dev_kfree_skb(skb); return ret; } @@ -1502,6 +1500,10 @@ static int kvaser_usb_init_one(struct usb_interface *intf, struct kvaser_usb_net_priv *priv; int i, err; + err = kvaser_usb_send_simple_msg(dev, CMD_RESET_CHIP, channel); + if (err) + return err; + netdev = alloc_candev(sizeof(*priv), MAX_TX_URBS); if (!netdev) { dev_err(&intf->dev, "Cannot alloc candev\n"); @@ -1606,9 +1608,6 @@ static int kvaser_usb_probe(struct usb_interface *intf, usb_set_intfdata(intf, dev); - for (i = 0; i < MAX_NET_DEVICES; i++) - kvaser_usb_send_simple_msg(dev, CMD_RESET_CHIP, i); - err = kvaser_usb_get_software_info(dev); if (err) { dev_err(&intf->dev, diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c b/drivers/net/ethernet/allwinner/sun4i-emac.c index 1fcd5568a352..f3470d96837a 100644 --- a/drivers/net/ethernet/allwinner/sun4i-emac.c +++ b/drivers/net/ethernet/allwinner/sun4i-emac.c @@ -850,8 +850,10 @@ static int emac_probe(struct platform_device *pdev) } db->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(db->clk)) + if (IS_ERR(db->clk)) { + ret = PTR_ERR(db->clk); goto out; + } clk_prepare_enable(db->clk); diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c index 3498760dc22a..760c72c6e2ac 100644 --- a/drivers/net/ethernet/altera/altera_tse_main.c +++ b/drivers/net/ethernet/altera/altera_tse_main.c @@ -1170,10 +1170,6 @@ tx_request_irq_error: init_error: free_skbufs(dev); alloc_skbuf_error: - if (priv->phydev) { - phy_disconnect(priv->phydev); - priv->phydev = NULL; - } phy_error: return ret; } @@ -1186,12 +1182,9 @@ static int tse_shutdown(struct net_device *dev) int ret; unsigned long int flags; - /* Stop and disconnect the PHY */ - if (priv->phydev) { + /* Stop the PHY */ + if (priv->phydev) phy_stop(priv->phydev); - phy_disconnect(priv->phydev); - priv->phydev = NULL; - } netif_stop_queue(dev); napi_disable(&priv->napi); @@ -1525,6 +1518,10 @@ err_free_netdev: static int altera_tse_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); + struct altera_tse_private *priv = netdev_priv(ndev); + + if (priv->phydev) + phy_disconnect(priv->phydev); platform_set_drvdata(pdev, NULL); altera_tse_mdio_destroy(ndev); diff --git a/drivers/net/ethernet/atheros/alx/main.c b/drivers/net/ethernet/atheros/alx/main.c index e398eda07298..c8af3ce3ea38 100644 --- a/drivers/net/ethernet/atheros/alx/main.c +++ b/drivers/net/ethernet/atheros/alx/main.c @@ -184,15 +184,16 @@ static void alx_schedule_reset(struct alx_priv *alx) schedule_work(&alx->reset_wk); } -static bool alx_clean_rx_irq(struct alx_priv *alx, int budget) +static int alx_clean_rx_irq(struct alx_priv *alx, int budget) { struct alx_rx_queue *rxq = &alx->rxq; struct alx_rrd *rrd; struct alx_buffer *rxb; struct sk_buff *skb; u16 length, rfd_cleaned = 0; + int work = 0; - while (budget > 0) { + while (work < budget) { rrd = &rxq->rrd[rxq->rrd_read_idx]; if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT))) break; @@ -203,7 +204,7 @@ static bool alx_clean_rx_irq(struct alx_priv *alx, int budget) ALX_GET_FIELD(le32_to_cpu(rrd->word0), RRD_NOR) != 1) { alx_schedule_reset(alx); - return 0; + return work; } rxb = &rxq->bufs[rxq->read_idx]; @@ -243,7 +244,7 @@ static bool alx_clean_rx_irq(struct alx_priv *alx, int budget) } napi_gro_receive(&alx->napi, skb); - budget--; + work++; next_pkt: if (++rxq->read_idx == alx->rx_ringsz) @@ -258,21 +259,22 @@ next_pkt: if (rfd_cleaned) alx_refill_rx_ring(alx, GFP_ATOMIC); - return budget > 0; + return work; } static int alx_poll(struct napi_struct *napi, int budget) { struct alx_priv *alx = container_of(napi, struct alx_priv, napi); struct alx_hw *hw = &alx->hw; - bool complete = true; unsigned long flags; + bool tx_complete; + int work; - complete = alx_clean_tx_irq(alx) && - alx_clean_rx_irq(alx, budget); + tx_complete = alx_clean_tx_irq(alx); + work = alx_clean_rx_irq(alx, budget); - if (!complete) - return 1; + if (!tx_complete || work == budget) + return budget; napi_complete(&alx->napi); @@ -284,7 +286,7 @@ static int alx_poll(struct napi_struct *napi, int budget) alx_post_write(hw); - return 0; + return work; } static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr) diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c index 05c6af6c418f..3007d95fbb9f 100644 --- a/drivers/net/ethernet/broadcom/bgmac.c +++ b/drivers/net/ethernet/broadcom/bgmac.c @@ -1167,10 +1167,10 @@ static int bgmac_poll(struct napi_struct *napi, int weight) bgmac->int_status = 0; } - if (handled < weight) + if (handled < weight) { napi_complete(napi); - - bgmac_chip_intrs_on(bgmac); + bgmac_chip_intrs_on(bgmac); + } return handled; } @@ -1515,6 +1515,8 @@ static int bgmac_probe(struct bcma_device *core) if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); + netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); + err = bgmac_mii_register(bgmac); if (err) { bgmac_err(bgmac, "Cannot register MDIO\n"); @@ -1529,8 +1531,6 @@ static int bgmac_probe(struct bcma_device *core) netif_carrier_off(net_dev); - netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); - return 0; err_mii_unregister: @@ -1549,9 +1549,9 @@ static void bgmac_remove(struct bcma_device *core) { struct bgmac *bgmac = bcma_get_drvdata(core); - netif_napi_del(&bgmac->napi); unregister_netdev(bgmac->net_dev); bgmac_mii_unregister(bgmac); + netif_napi_del(&bgmac->napi); bgmac_dma_free(bgmac); bcma_set_drvdata(core, NULL); free_netdev(bgmac->net_dev); diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 553dcd8a9df2..96bf01ba32dd 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -7413,6 +7413,8 @@ static inline void tg3_netif_start(struct tg3 *tp) } static void tg3_irq_quiesce(struct tg3 *tp) + __releases(tp->lock) + __acquires(tp->lock) { int i; @@ -7421,8 +7423,12 @@ static void tg3_irq_quiesce(struct tg3 *tp) tp->irq_sync = 1; smp_mb(); + spin_unlock_bh(&tp->lock); + for (i = 0; i < tp->irq_cnt; i++) synchronize_irq(tp->napi[i].irq_vec); + + spin_lock_bh(&tp->lock); } /* Fully shutdown all tg3 driver activity elsewhere in the system. @@ -9018,6 +9024,8 @@ static void tg3_restore_clk(struct tg3 *tp) /* tp->lock is held. */ static int tg3_chip_reset(struct tg3 *tp) + __releases(tp->lock) + __acquires(tp->lock) { u32 val; void (*write_op)(struct tg3 *, u32, u32); @@ -9073,9 +9081,13 @@ static int tg3_chip_reset(struct tg3 *tp) } smp_mb(); + tg3_full_unlock(tp); + for (i = 0; i < tp->irq_cnt; i++) synchronize_irq(tp->napi[i].irq_vec); + tg3_full_lock(tp, 0); + if (tg3_asic_rev(tp) == ASIC_REV_57780) { val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); @@ -10903,11 +10915,13 @@ static void tg3_timer(unsigned long __opaque) { struct tg3 *tp = (struct tg3 *) __opaque; - if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) - goto restart_timer; - spin_lock(&tp->lock); + if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { + spin_unlock(&tp->lock); + goto restart_timer; + } + if (tg3_asic_rev(tp) == ASIC_REV_5717 || tg3_flag(tp, 57765_CLASS)) tg3_chk_missed_msi(tp); @@ -11101,11 +11115,13 @@ static void tg3_reset_task(struct work_struct *work) struct tg3 *tp = container_of(work, struct tg3, reset_task); int err; + rtnl_lock(); tg3_full_lock(tp, 0); if (!netif_running(tp->dev)) { tg3_flag_clear(tp, RESET_TASK_PENDING); tg3_full_unlock(tp); + rtnl_unlock(); return; } @@ -11138,6 +11154,7 @@ out: tg3_phy_start(tp); tg3_flag_clear(tp, RESET_TASK_PENDING); + rtnl_unlock(); } static int tg3_request_irq(struct tg3 *tp, int irq_num) diff --git a/drivers/net/ethernet/cadence/at91_ether.c b/drivers/net/ethernet/cadence/at91_ether.c index 55eb7f2af2b4..7ef55f5fa664 100644 --- a/drivers/net/ethernet/cadence/at91_ether.c +++ b/drivers/net/ethernet/cadence/at91_ether.c @@ -340,7 +340,7 @@ static int __init at91ether_probe(struct platform_device *pdev) res = PTR_ERR(lp->pclk); goto err_free_dev; } - clk_enable(lp->pclk); + clk_prepare_enable(lp->pclk); lp->hclk = ERR_PTR(-ENOENT); lp->tx_clk = ERR_PTR(-ENOENT); @@ -406,7 +406,7 @@ static int __init at91ether_probe(struct platform_device *pdev) err_out_unregister_netdev: unregister_netdev(dev); err_disable_clock: - clk_disable(lp->pclk); + clk_disable_unprepare(lp->pclk); err_free_dev: free_netdev(dev); return res; @@ -424,7 +424,7 @@ static int at91ether_remove(struct platform_device *pdev) kfree(lp->mii_bus->irq); mdiobus_free(lp->mii_bus); unregister_netdev(dev); - clk_disable(lp->pclk); + clk_disable_unprepare(lp->pclk); free_netdev(dev); return 0; @@ -440,7 +440,7 @@ static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg) netif_stop_queue(net_dev); netif_device_detach(net_dev); - clk_disable(lp->pclk); + clk_disable_unprepare(lp->pclk); } return 0; } @@ -451,7 +451,7 @@ static int at91ether_resume(struct platform_device *pdev) struct macb *lp = netdev_priv(net_dev); if (netif_running(net_dev)) { - clk_enable(lp->pclk); + clk_prepare_enable(lp->pclk); netif_device_attach(net_dev); netif_start_queue(net_dev); diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c index 2215d432a059..a936ee8958c7 100644 --- a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c +++ b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c @@ -2430,7 +2430,7 @@ static void cfg_queues(struct adapter *adapter) */ n10g = 0; for_each_port(adapter, pidx) - n10g += is_10g_port(&adap2pinfo(adapter, pidx)->link_cfg); + n10g += is_x_10g_port(&adap2pinfo(adapter, pidx)->link_cfg); /* * We default to 1 queue per non-10G port and up to # of cores queues diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c index 21dc9a20308c..60426cf890a7 100644 --- a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c @@ -323,6 +323,8 @@ int t4vf_port_init(struct adapter *adapter, int pidx) return v; v = be32_to_cpu(port_rpl.u.info.lstatus_to_modtype); + pi->mdio_addr = (v & FW_PORT_CMD_MDIOCAP_F) ? + FW_PORT_CMD_MDIOADDR_G(v) : -1; pi->port_type = FW_PORT_CMD_PTYPE_G(v); pi->mod_type = FW_PORT_MOD_TYPE_NA; diff --git a/drivers/net/ethernet/cisco/enic/enic_main.c b/drivers/net/ethernet/cisco/enic/enic_main.c index 705f334ebb85..b29e027c476e 100644 --- a/drivers/net/ethernet/cisco/enic/enic_main.c +++ b/drivers/net/ethernet/cisco/enic/enic_main.c @@ -1616,7 +1616,7 @@ static int enic_open(struct net_device *netdev) if (vnic_rq_desc_used(&enic->rq[i]) == 0) { netdev_err(netdev, "Unable to alloc receive buffers\n"); err = -ENOMEM; - goto err_out_notify_unset; + goto err_out_free_rq; } } @@ -1649,7 +1649,9 @@ static int enic_open(struct net_device *netdev) return 0; -err_out_notify_unset: +err_out_free_rq: + for (i = 0; i < enic->rq_count; i++) + vnic_rq_clean(&enic->rq[i], enic_free_rq_buf); enic_dev_notify_unset(enic); err_out_free_intr: enic_free_intr(enic); diff --git a/drivers/net/ethernet/dnet.c b/drivers/net/ethernet/dnet.c index a379c3e4b57f..13d00a38a5bd 100644 --- a/drivers/net/ethernet/dnet.c +++ b/drivers/net/ethernet/dnet.c @@ -398,13 +398,8 @@ static int dnet_poll(struct napi_struct *napi, int budget) * break out of while loop if there are no more * packets waiting */ - if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) { - napi_complete(napi); - int_enable = dnet_readl(bp, INTR_ENB); - int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; - dnet_writel(bp, int_enable, INTR_ENB); - return 0; - } + if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) + break; cmd_word = dnet_readl(bp, RX_LEN_FIFO); pkt_len = cmd_word & 0xFFFF; @@ -433,20 +428,17 @@ static int dnet_poll(struct napi_struct *napi, int budget) "size %u.\n", dev->name, pkt_len); } - budget -= npackets; - if (npackets < budget) { /* We processed all packets available. Tell NAPI it can - * stop polling then re-enable rx interrupts */ + * stop polling then re-enable rx interrupts. + */ napi_complete(napi); int_enable = dnet_readl(bp, INTR_ENB); int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; dnet_writel(bp, int_enable, INTR_ENB); - return 0; } - /* There are still packets waiting */ - return 1; + return npackets; } static irqreturn_t dnet_interrupt(int irq, void *dev_id) diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c index 41a0a5498da7..d48806b5cd88 100644 --- a/drivers/net/ethernet/emulex/benet/be_main.c +++ b/drivers/net/ethernet/emulex/benet/be_main.c @@ -4383,8 +4383,9 @@ static int be_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, * distinguish various types of transports (VxLAN, GRE, NVGRE ..). So, offload * is expected to work across all types of IP tunnels once exported. Skyhawk * supports offloads for either VxLAN or NVGRE, exclusively. So we export VxLAN - * offloads in hw_enc_features only when a VxLAN port is added. Note this only - * ensures that other tunnels work fine while VxLAN offloads are not enabled. + * offloads in hw_enc_features only when a VxLAN port is added. If other (non + * VxLAN) tunnels are configured while VxLAN offloads are enabled, offloads for + * those other tunnels are unexported on the fly through ndo_features_check(). * * Skyhawk supports VxLAN offloads only for one UDP dport. So, if the stack * adds more than one port, disable offloads and don't re-enable them again @@ -4463,7 +4464,41 @@ static netdev_features_t be_features_check(struct sk_buff *skb, struct net_device *dev, netdev_features_t features) { - return vxlan_features_check(skb, features); + struct be_adapter *adapter = netdev_priv(dev); + u8 l4_hdr = 0; + + /* The code below restricts offload features for some tunneled packets. + * Offload features for normal (non tunnel) packets are unchanged. + */ + if (!skb->encapsulation || + !(adapter->flags & BE_FLAGS_VXLAN_OFFLOADS)) + return features; + + /* It's an encapsulated packet and VxLAN offloads are enabled. We + * should disable tunnel offload features if it's not a VxLAN packet, + * as tunnel offloads have been enabled only for VxLAN. This is done to + * allow other tunneled traffic like GRE work fine while VxLAN + * offloads are configured in Skyhawk-R. + */ + switch (vlan_get_protocol(skb)) { + case htons(ETH_P_IP): + l4_hdr = ip_hdr(skb)->protocol; + break; + case htons(ETH_P_IPV6): + l4_hdr = ipv6_hdr(skb)->nexthdr; + break; + default: + return features; + } + + if (l4_hdr != IPPROTO_UDP || + skb->inner_protocol_type != ENCAP_TYPE_ETHER || + skb->inner_protocol != htons(ETH_P_TEB) || + skb_inner_mac_header(skb) - skb_transport_header(skb) != + sizeof(struct udphdr) + sizeof(struct vxlanhdr)) + return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK); + + return features; } #endif diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h index 469691ad4a1e..40132929daf7 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -424,6 +424,8 @@ struct bufdesc_ex { * (40ns * 6). */ #define FEC_QUIRK_BUG_CAPTURE (1 << 10) +/* Controller has only one MDIO bus */ +#define FEC_QUIRK_SINGLE_MDIO (1 << 11) struct fec_enet_priv_tx_q { int index; diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 5ebdf8dc8a31..bba87775419d 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -91,7 +91,8 @@ static struct platform_device_id fec_devtype[] = { .driver_data = 0, }, { .name = "imx28-fec", - .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, + .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | + FEC_QUIRK_SINGLE_MDIO, }, { .name = "imx6q-fec", .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | @@ -1937,7 +1938,7 @@ static int fec_enet_mii_init(struct platform_device *pdev) int err = -ENXIO, i; /* - * The dual fec interfaces are not equivalent with enet-mac. + * The i.MX28 dual fec interfaces are not equal. * Here are the differences: * * - fec0 supports MII & RMII modes while fec1 only supports RMII @@ -1952,7 +1953,7 @@ static int fec_enet_mii_init(struct platform_device *pdev) * mdio interface in board design, and need to be configured by * fec0 mii_bus. */ - if ((fep->quirks & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { + if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { /* fec1 uses fec0 mii_bus */ if (mii_cnt && fec0_mii_bus) { fep->mii_bus = fec0_mii_bus; @@ -2015,7 +2016,7 @@ static int fec_enet_mii_init(struct platform_device *pdev) mii_cnt++; /* save fec0 mii_bus */ - if (fep->quirks & FEC_QUIRK_ENET_MAC) + if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) fec0_mii_bus = fep->mii_bus; return 0; @@ -3129,6 +3130,7 @@ fec_probe(struct platform_device *pdev) pdev->id_entry = of_id->data; fep->quirks = pdev->id_entry->driver_data; + fep->netdev = ndev; fep->num_rx_queues = num_rx_qs; fep->num_tx_queues = num_tx_qs; diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig index 5b8300a32bf5..4d61ef50b465 100644 --- a/drivers/net/ethernet/intel/Kconfig +++ b/drivers/net/ethernet/intel/Kconfig @@ -281,6 +281,17 @@ config I40E_DCB If unsure, say N. +config I40E_FCOE + bool "Fibre Channel over Ethernet (FCoE)" + default n + depends on I40E && DCB && FCOE + ---help--- + Say Y here if you want to use Fibre Channel over Ethernet (FCoE) + in the driver. This will create new netdev for exclusive FCoE + use with XL710 FCoE offloads enabled. + + If unsure, say N. + config I40EVF tristate "Intel(R) XL710 X710 Virtual Function Ethernet support" depends on PCI_MSI diff --git a/drivers/net/ethernet/intel/e100.c b/drivers/net/ethernet/intel/e100.c index 781065eb5431..e9c3a87e5b11 100644 --- a/drivers/net/ethernet/intel/e100.c +++ b/drivers/net/ethernet/intel/e100.c @@ -1543,7 +1543,7 @@ static int e100_phy_init(struct nic *nic) mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr); } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) && (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) && - !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) { + (nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) { /* enable/disable MDI/MDI-X auto-switching. */ mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH); diff --git a/drivers/net/ethernet/intel/i40e/Makefile b/drivers/net/ethernet/intel/i40e/Makefile index 4b94ddb29c24..c40581999121 100644 --- a/drivers/net/ethernet/intel/i40e/Makefile +++ b/drivers/net/ethernet/intel/i40e/Makefile @@ -44,4 +44,4 @@ i40e-objs := i40e_main.o \ i40e_virtchnl_pf.o i40e-$(CONFIG_I40E_DCB) += i40e_dcb.o i40e_dcb_nl.o -i40e-$(CONFIG_FCOE:m=y) += i40e_fcoe.o +i40e-$(CONFIG_I40E_FCOE) += i40e_fcoe.o diff --git a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c index 433a55886ad2..cb0de455683e 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c +++ b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c @@ -829,7 +829,7 @@ static void i40e_dbg_dump_desc(int cnt, int vsi_seid, int ring_id, int desc_n, if (desc_n >= ring->count || desc_n < 0) { dev_info(&pf->pdev->dev, "descriptor %d not found\n", desc_n); - return; + goto out; } if (!is_rx_ring) { txd = I40E_TX_DESC(ring, desc_n); @@ -855,6 +855,8 @@ static void i40e_dbg_dump_desc(int cnt, int vsi_seid, int ring_id, int desc_n, } else { dev_info(&pf->pdev->dev, "dump desc rx/tx <vsi_seid> <ring_id> [<desc_n>]\n"); } + +out: kfree(ring); } diff --git a/drivers/net/ethernet/intel/i40e/i40e_osdep.h b/drivers/net/ethernet/intel/i40e/i40e_osdep.h index 045b5c4b98b3..ad802dd0f67a 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_osdep.h +++ b/drivers/net/ethernet/intel/i40e/i40e_osdep.h @@ -78,7 +78,7 @@ do { \ } while (0) typedef enum i40e_status_code i40e_status; -#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) +#ifdef CONFIG_I40E_FCOE #define I40E_FCOE -#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ +#endif #endif /* _I40E_OSDEP_H_ */ diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c index 04b441460bbd..cecb340898fe 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c @@ -658,6 +658,8 @@ static inline u32 i40e_get_head(struct i40e_ring *tx_ring) return le32_to_cpu(*(volatile __le32 *)head); } +#define WB_STRIDE 0x3 + /** * i40e_clean_tx_irq - Reclaim resources after transmit completes * @tx_ring: tx ring to clean @@ -759,6 +761,18 @@ static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget) tx_ring->q_vector->tx.total_bytes += total_bytes; tx_ring->q_vector->tx.total_packets += total_packets; + /* check to see if there are any non-cache aligned descriptors + * waiting to be written back, and kick the hardware to force + * them to be written back in case of napi polling + */ + if (budget && + !((i & WB_STRIDE) == WB_STRIDE) && + !test_bit(__I40E_DOWN, &tx_ring->vsi->state) && + (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) + tx_ring->arm_wb = true; + else + tx_ring->arm_wb = false; + if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) { /* schedule immediate reset if we believe we hung */ dev_info(tx_ring->dev, "Detected Tx Unit Hang\n" @@ -777,13 +791,16 @@ static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget) netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); dev_info(tx_ring->dev, - "tx hang detected on queue %d, resetting adapter\n", + "tx hang detected on queue %d, reset requested\n", tx_ring->queue_index); - tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev); + /* do not fire the reset immediately, wait for the stack to + * decide we are truly stuck, also prevents every queue from + * simultaneously requesting a reset + */ - /* the adapter is about to reset, no point in enabling stuff */ - return true; + /* the adapter is about to reset, no point in enabling polling */ + budget = 1; } netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev, @@ -806,7 +823,25 @@ static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget) } } - return budget > 0; + return !!budget; +} + +/** + * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors + * @vsi: the VSI we care about + * @q_vector: the vector on which to force writeback + * + **/ +static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) +{ + u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | + I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | + I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK + /* allow 00 to be written to the index */; + + wr32(&vsi->back->hw, + I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), + val); } /** @@ -1290,9 +1325,7 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi, * so the total length of IPv4 header is IHL*4 bytes * The UDP_0 bit *may* bet set if the *inner* header is UDP */ - if (ipv4_tunnel && - (decoded.inner_prot != I40E_RX_PTYPE_INNER_PROT_UDP) && - !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) { + if (ipv4_tunnel) { skb->transport_header = skb->mac_header + sizeof(struct ethhdr) + (ip_hdr(skb)->ihl * 4); @@ -1302,15 +1335,19 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi, skb->protocol == htons(ETH_P_8021AD)) ? VLAN_HLEN : 0; - rx_udp_csum = udp_csum(skb); - iph = ip_hdr(skb); - csum = csum_tcpudp_magic( - iph->saddr, iph->daddr, - (skb->len - skb_transport_offset(skb)), - IPPROTO_UDP, rx_udp_csum); + if ((ip_hdr(skb)->protocol == IPPROTO_UDP) && + (udp_hdr(skb)->check != 0)) { + rx_udp_csum = udp_csum(skb); + iph = ip_hdr(skb); + csum = csum_tcpudp_magic( + iph->saddr, iph->daddr, + (skb->len - skb_transport_offset(skb)), + IPPROTO_UDP, rx_udp_csum); - if (udp_hdr(skb)->check != csum) - goto checksum_fail; + if (udp_hdr(skb)->check != csum) + goto checksum_fail; + + } /* else its GRE and so no outer UDP header */ } skb->ip_summed = CHECKSUM_UNNECESSARY; @@ -1581,6 +1618,7 @@ int i40e_napi_poll(struct napi_struct *napi, int budget) struct i40e_vsi *vsi = q_vector->vsi; struct i40e_ring *ring; bool clean_complete = true; + bool arm_wb = false; int budget_per_ring; if (test_bit(__I40E_DOWN, &vsi->state)) { @@ -1591,8 +1629,10 @@ int i40e_napi_poll(struct napi_struct *napi, int budget) /* Since the actual Tx work is minimal, we can give the Tx a larger * budget and be more aggressive about cleaning up the Tx descriptors. */ - i40e_for_each_ring(ring, q_vector->tx) + i40e_for_each_ring(ring, q_vector->tx) { clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit); + arm_wb |= ring->arm_wb; + } /* We attempt to distribute budget to each Rx queue fairly, but don't * allow the budget to go below 1 because that would exit polling early. @@ -1603,8 +1643,11 @@ int i40e_napi_poll(struct napi_struct *napi, int budget) clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring); /* If work not completed, return budget and polling will return */ - if (!clean_complete) + if (!clean_complete) { + if (arm_wb) + i40e_force_wb(vsi, q_vector); return budget; + } /* Work is done so exit the polling mode and re-enable the interrupt */ napi_complete(napi); @@ -1840,17 +1883,16 @@ static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb, if (err < 0) return err; - if (protocol == htons(ETH_P_IP)) { - iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb); + iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb); + ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); + + if (iph->version == 4) { tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); iph->tot_len = 0; iph->check = 0; tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, IPPROTO_TCP, 0); - } else if (skb_is_gso_v6(skb)) { - - ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) - : ipv6_hdr(skb); + } else if (ipv6h->version == 6) { tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); ipv6h->payload_len = 0; tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, @@ -1946,13 +1988,9 @@ static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags, I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; } } else if (tx_flags & I40E_TX_FLAGS_IPV6) { - if (tx_flags & I40E_TX_FLAGS_TSO) { - *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6; + *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6; + if (tx_flags & I40E_TX_FLAGS_TSO) ip_hdr(skb)->check = 0; - } else { - *cd_tunneling |= - I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; - } } /* Now set the ctx descriptor fields */ @@ -1962,7 +2000,10 @@ static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags, ((skb_inner_network_offset(skb) - skb_transport_offset(skb)) >> 1) << I40E_TXD_CTX_QW0_NATLEN_SHIFT; - + if (this_ip_hdr->version == 6) { + tx_flags &= ~I40E_TX_FLAGS_IPV4; + tx_flags |= I40E_TX_FLAGS_IPV6; + } } else { network_hdr_len = skb_network_header_len(skb); this_ip_hdr = ip_hdr(skb); @@ -2198,7 +2239,6 @@ static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, /* Place RS bit on last descriptor of any packet that spans across the * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline. */ -#define WB_STRIDE 0x3 if (((i & WB_STRIDE) != WB_STRIDE) && (first <= &tx_ring->tx_bi[i]) && (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) { diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.h b/drivers/net/ethernet/intel/i40e/i40e_txrx.h index e60d3accb2e2..18b00231d2f1 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.h +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.h @@ -241,6 +241,7 @@ struct i40e_ring { unsigned long last_rx_timestamp; bool ring_active; /* is ring online or not */ + bool arm_wb; /* do something to arm write back */ /* stats structs */ struct i40e_queue_stats stats; diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c index 051ea94bdcd3..0f69ef81751a 100644 --- a/drivers/net/ethernet/intel/igb/e1000_82575.c +++ b/drivers/net/ethernet/intel/igb/e1000_82575.c @@ -1125,7 +1125,7 @@ static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) u32 swmask = mask; u32 fwmask = mask << 16; s32 ret_val = 0; - s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ + s32 i = 0, timeout = 200; while (i < timeout) { if (igb_get_hw_semaphore(hw)) { diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c index d0d6dc1b8e46..ac6a8f1eea6c 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c @@ -475,7 +475,8 @@ static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *ad { int err; - if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) + if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || + priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) return 0; /* do nothing */ err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn, diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c index 943cbd47d832..6e08352ec994 100644 --- a/drivers/net/ethernet/mellanox/mlx4/main.c +++ b/drivers/net/ethernet/mellanox/mlx4/main.c @@ -1744,8 +1744,7 @@ static void choose_tunnel_offload_mode(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) { if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && - dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS && - dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC) + dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; else dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; @@ -1829,7 +1828,7 @@ static int mlx4_init_hca(struct mlx4_dev *dev) err = mlx4_dev_cap(dev, &dev_cap); if (err) { mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); - goto err_stop_fw; + return err; } choose_steering_mode(dev, &dev_cap); @@ -1860,7 +1859,7 @@ static int mlx4_init_hca(struct mlx4_dev *dev) &init_hca); if ((long long) icm_size < 0) { err = icm_size; - goto err_stop_fw; + return err; } dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; @@ -1874,7 +1873,7 @@ static int mlx4_init_hca(struct mlx4_dev *dev) err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); if (err) - goto err_stop_fw; + return err; err = mlx4_INIT_HCA(dev, &init_hca); if (err) { @@ -1886,7 +1885,7 @@ static int mlx4_init_hca(struct mlx4_dev *dev) err = mlx4_query_func(dev, &dev_cap); if (err < 0) { mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); - goto err_stop_fw; + goto err_close; } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { dev->caps.num_eqs = dev_cap.max_eqs; dev->caps.reserved_eqs = dev_cap.reserved_eqs; @@ -2006,11 +2005,6 @@ err_free_icm: if (!mlx4_is_slave(dev)) mlx4_free_icms(dev); -err_stop_fw: - if (!mlx4_is_slave(dev)) { - mlx4_UNMAP_FA(dev); - mlx4_free_icm(dev, priv->fw.fw_icm, 0); - } return err; } diff --git a/drivers/net/ethernet/mellanox/mlx4/mr.c b/drivers/net/ethernet/mellanox/mlx4/mr.c index d6f549685c0f..7094a9c70fd5 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mr.c +++ b/drivers/net/ethernet/mellanox/mlx4/mr.c @@ -584,6 +584,7 @@ EXPORT_SYMBOL_GPL(mlx4_mr_free); void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr) { mlx4_mtt_cleanup(dev, &mr->mtt); + mr->mtt.order = -1; } EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_cleanup); @@ -593,14 +594,14 @@ int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, { int err; - mpt_entry->start = cpu_to_be64(iova); - mpt_entry->length = cpu_to_be64(size); - mpt_entry->entity_size = cpu_to_be32(page_shift); - err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt); if (err) return err; + mpt_entry->start = cpu_to_be64(mr->iova); + mpt_entry->length = cpu_to_be64(mr->size); + mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift); + mpt_entry->pd_flags &= cpu_to_be32(MLX4_MPT_PD_MASK | MLX4_MPT_PD_FLAG_EN_INV); mpt_entry->flags &= cpu_to_be32(MLX4_MPT_FLAG_FREE | diff --git a/drivers/net/ethernet/myricom/myri10ge/myri10ge.c b/drivers/net/ethernet/myricom/myri10ge/myri10ge.c index af099057f0e9..71af98bb72cb 100644 --- a/drivers/net/ethernet/myricom/myri10ge/myri10ge.c +++ b/drivers/net/ethernet/myricom/myri10ge/myri10ge.c @@ -4033,8 +4033,10 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd), &mgp->cmd_bus, GFP_KERNEL); - if (mgp->cmd == NULL) + if (!mgp->cmd) { + status = -ENOMEM; goto abort_with_enabled; + } mgp->board_span = pci_resource_len(pdev, 0); mgp->iomem_base = pci_resource_start(pdev, 0); diff --git a/drivers/net/ethernet/neterion/s2io.c b/drivers/net/ethernet/neterion/s2io.c index f5e4b820128b..db0c7a9aee60 100644 --- a/drivers/net/ethernet/neterion/s2io.c +++ b/drivers/net/ethernet/neterion/s2io.c @@ -6987,7 +6987,9 @@ static int s2io_add_isr(struct s2io_nic *sp) if (sp->s2io_entries[i].in_use == MSIX_FLG) { if (sp->s2io_entries[i].type == MSIX_RING_TYPE) { - sprintf(sp->desc[i], "%s:MSI-X-%d-RX", + snprintf(sp->desc[i], + sizeof(sp->desc[i]), + "%s:MSI-X-%d-RX", dev->name, i); err = request_irq(sp->entries[i].vector, s2io_msix_ring_handle, @@ -6996,7 +6998,9 @@ static int s2io_add_isr(struct s2io_nic *sp) sp->s2io_entries[i].arg); } else if (sp->s2io_entries[i].type == MSIX_ALARM_TYPE) { - sprintf(sp->desc[i], "%s:MSI-X-%d-TX", + snprintf(sp->desc[i], + sizeof(sp->desc[i]), + "%s:MSI-X-%d-TX", dev->name, i); err = request_irq(sp->entries[i].vector, s2io_msix_fifo_handle, @@ -8154,7 +8158,8 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) "%s: UDP Fragmentation Offload(UFO) enabled\n", dev->name); /* Initialize device name */ - sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name); + snprintf(sp->name, sizeof(sp->name), "%s Neterion %s", dev->name, + sp->product_name); if (vlan_tag_strip) sp->vlan_strip_flag = 1; diff --git a/drivers/net/ethernet/qlogic/qla3xxx.c b/drivers/net/ethernet/qlogic/qla3xxx.c index c2f09af5c25b..4847713211ca 100644 --- a/drivers/net/ethernet/qlogic/qla3xxx.c +++ b/drivers/net/ethernet/qlogic/qla3xxx.c @@ -146,10 +146,7 @@ static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev) { int i = 0; - while (i < 10) { - if (i) - ssleep(1); - + do { if (ql_sem_lock(qdev, QL_DRVR_SEM_MASK, (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) @@ -158,7 +155,8 @@ static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev) "driver lock acquired\n"); return 1; } - } + ssleep(1); + } while (++i < 10); netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n"); return 0; diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c index 9929b97cfb36..2528c3fb6b90 100644 --- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c +++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c @@ -2605,6 +2605,7 @@ qlcnic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) } else { dev_err(&pdev->dev, "%s: failed. Please Reboot\n", __func__); + err = -ENODEV; goto err_out_free_hw; } diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index c29ba80ae02b..6576243222af 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -473,6 +473,7 @@ static struct sh_eth_cpu_data r8a777x_data = { .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, + .fdr_value = 0x00000f0f, .apr = 1, .mpr = 1, @@ -495,6 +496,9 @@ static struct sh_eth_cpu_data r8a779x_data = { .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, + .fdr_value = 0x00000f0f, + + .trscer_err_mask = DESC_I_RINT8, .apr = 1, .mpr = 1, @@ -856,6 +860,9 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) if (!cd->eesr_err_check) cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; + + if (!cd->trscer_err_mask) + cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; } static int sh_eth_check_reset(struct net_device *ndev) @@ -1294,7 +1301,7 @@ static int sh_eth_dev_init(struct net_device *ndev, bool start) /* Frame recv control (enable multiple-packets per rx irq) */ sh_eth_write(ndev, RMCR_RNC, RMCR); - sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER); + sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); if (mdp->cd->bculr) sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ @@ -1820,6 +1827,9 @@ static int sh_eth_get_settings(struct net_device *ndev, unsigned long flags; int ret; + if (!mdp->phydev) + return -ENODEV; + spin_lock_irqsave(&mdp->lock, flags); ret = phy_ethtool_gset(mdp->phydev, ecmd); spin_unlock_irqrestore(&mdp->lock, flags); @@ -1834,6 +1844,9 @@ static int sh_eth_set_settings(struct net_device *ndev, unsigned long flags; int ret; + if (!mdp->phydev) + return -ENODEV; + spin_lock_irqsave(&mdp->lock, flags); /* disable tx and rx */ @@ -1868,6 +1881,9 @@ static int sh_eth_nway_reset(struct net_device *ndev) unsigned long flags; int ret; + if (!mdp->phydev) + return -ENODEV; + spin_lock_irqsave(&mdp->lock, flags); ret = phy_start_aneg(mdp->phydev); spin_unlock_irqrestore(&mdp->lock, flags); @@ -2177,6 +2193,7 @@ static int sh_eth_close(struct net_device *ndev) if (mdp->phydev) { phy_stop(mdp->phydev); phy_disconnect(mdp->phydev); + mdp->phydev = NULL; } free_irq(ndev->irq, ndev); @@ -2410,7 +2427,7 @@ static int sh_eth_tsu_purge_all(struct net_device *ndev) struct sh_eth_private *mdp = netdev_priv(ndev); int i, ret; - if (unlikely(!mdp->cd->tsu)) + if (!mdp->cd->tsu) return 0; for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { @@ -2433,7 +2450,7 @@ static void sh_eth_tsu_purge_mcast(struct net_device *ndev) void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); int i; - if (unlikely(!mdp->cd->tsu)) + if (!mdp->cd->tsu) return; for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { @@ -2443,8 +2460,8 @@ static void sh_eth_tsu_purge_mcast(struct net_device *ndev) } } -/* Multicast reception directions set */ -static void sh_eth_set_multicast_list(struct net_device *ndev) +/* Update promiscuous flag and multicast filter */ +static void sh_eth_set_rx_mode(struct net_device *ndev) { struct sh_eth_private *mdp = netdev_priv(ndev); u32 ecmr_bits; @@ -2455,7 +2472,9 @@ static void sh_eth_set_multicast_list(struct net_device *ndev) /* Initial condition is MCT = 1, PRM = 0. * Depending on ndev->flags, set PRM or clear MCT */ - ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT; + ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; + if (mdp->cd->tsu) + ecmr_bits |= ECMR_MCT; if (!(ndev->flags & IFF_MULTICAST)) { sh_eth_tsu_purge_mcast(ndev); @@ -2484,9 +2503,6 @@ static void sh_eth_set_multicast_list(struct net_device *ndev) } } } - } else { - /* Normal, unicast/broadcast-only mode. */ - ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT; } /* update the ethernet mode */ @@ -2694,6 +2710,7 @@ static const struct net_device_ops sh_eth_netdev_ops = { .ndo_stop = sh_eth_close, .ndo_start_xmit = sh_eth_start_xmit, .ndo_get_stats = sh_eth_get_stats, + .ndo_set_rx_mode = sh_eth_set_rx_mode, .ndo_tx_timeout = sh_eth_tx_timeout, .ndo_do_ioctl = sh_eth_do_ioctl, .ndo_validate_addr = eth_validate_addr, @@ -2706,7 +2723,7 @@ static const struct net_device_ops sh_eth_netdev_ops_tsu = { .ndo_stop = sh_eth_close, .ndo_start_xmit = sh_eth_start_xmit, .ndo_get_stats = sh_eth_get_stats, - .ndo_set_rx_mode = sh_eth_set_multicast_list, + .ndo_set_rx_mode = sh_eth_set_rx_mode, .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, .ndo_tx_timeout = sh_eth_tx_timeout, diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h index 22301bf9c21d..71f5de1171bd 100644 --- a/drivers/net/ethernet/renesas/sh_eth.h +++ b/drivers/net/ethernet/renesas/sh_eth.h @@ -369,6 +369,8 @@ enum DESC_I_BIT { DESC_I_RINT1 = 0x0001, }; +#define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2) + /* RPADIR */ enum RPADIR_BIT { RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, @@ -470,6 +472,9 @@ struct sh_eth_cpu_data { unsigned long tx_check; unsigned long eesr_err_check; + /* Error mask */ + unsigned long trscer_err_mask; + /* hardware features */ unsigned long irq_flags; /* IRQ configuration flags */ unsigned no_psr:1; /* EtherC DO NOT have PSR */ diff --git a/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c b/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c index 698494481d18..b1a271853d85 100644 --- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c +++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c @@ -474,13 +474,19 @@ static int init_rx_ring(struct net_device *dev, u8 queue_no, /* allocate memory for RX skbuff array */ rx_ring->rx_skbuff_dma = kmalloc_array(rx_rsize, sizeof(dma_addr_t), GFP_KERNEL); - if (rx_ring->rx_skbuff_dma == NULL) - goto dmamem_err; + if (!rx_ring->rx_skbuff_dma) { + dma_free_coherent(priv->device, + rx_rsize * sizeof(struct sxgbe_rx_norm_desc), + rx_ring->dma_rx, rx_ring->dma_rx_phy); + goto error; + } rx_ring->rx_skbuff = kmalloc_array(rx_rsize, sizeof(struct sk_buff *), GFP_KERNEL); - if (rx_ring->rx_skbuff == NULL) - goto rxbuff_err; + if (!rx_ring->rx_skbuff) { + kfree(rx_ring->rx_skbuff_dma); + goto error; + } /* initialise the buffers */ for (desc_index = 0; desc_index < rx_rsize; desc_index++) { @@ -502,13 +508,6 @@ static int init_rx_ring(struct net_device *dev, u8 queue_no, err_init_rx_buffers: while (--desc_index >= 0) free_rx_ring(priv->device, rx_ring, desc_index); - kfree(rx_ring->rx_skbuff); -rxbuff_err: - kfree(rx_ring->rx_skbuff_dma); -dmamem_err: - dma_free_coherent(priv->device, - rx_rsize * sizeof(struct sxgbe_rx_norm_desc), - rx_ring->dma_rx, rx_ring->dma_rx_phy); error: return -ENOMEM; } diff --git a/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c b/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c index 866560ea9e18..b02eed12bfc5 100644 --- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c +++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c @@ -108,10 +108,6 @@ static int sxgbe_platform_probe(struct platform_device *pdev) } } - /* Get MAC address if available (DT) */ - if (mac) - ether_addr_copy(priv->dev->dev_addr, mac); - priv = sxgbe_drv_probe(&(pdev->dev), plat_dat, addr); if (!priv) { pr_err("%s: main driver probe failed\n", __func__); @@ -125,6 +121,10 @@ static int sxgbe_platform_probe(struct platform_device *pdev) goto err_drv_remove; } + /* Get MAC address if available (DT) */ + if (mac) + ether_addr_copy(priv->dev->dev_addr, mac); + /* Get the TX/RX IRQ numbers */ for (i = 0, chan = 1; i < SXGBE_TX_QUEUES; i++) { priv->txq[i]->irq_no = irq_of_parse_and_map(node, chan++); diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index c560f9aeb55d..e068d48b0f21 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -610,7 +610,7 @@ static void cpsw_set_promiscious(struct net_device *ndev, bool enable) /* Clear all mcast from ALE */ cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS << - priv->host_port); + priv->host_port, -1); /* Flood All Unicast Packets to Host port */ cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); @@ -634,6 +634,12 @@ static void cpsw_set_promiscious(struct net_device *ndev, bool enable) static void cpsw_ndo_set_rx_mode(struct net_device *ndev) { struct cpsw_priv *priv = netdev_priv(ndev); + int vid; + + if (priv->data.dual_emac) + vid = priv->slaves[priv->emac_port].port_vlan; + else + vid = priv->data.default_vlan; if (ndev->flags & IFF_PROMISC) { /* Enable promiscuous mode */ @@ -649,7 +655,8 @@ static void cpsw_ndo_set_rx_mode(struct net_device *ndev) cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI); /* Clear all mcast from ALE */ - cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); + cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port, + vid); if (!netdev_mc_empty(ndev)) { struct netdev_hw_addr *ha; @@ -757,6 +764,14 @@ requeue: static irqreturn_t cpsw_interrupt(int irq, void *dev_id) { struct cpsw_priv *priv = dev_id; + int value = irq - priv->irqs_table[0]; + + /* NOTICE: Ending IRQ here. The trick with the 'value' variable above + * is to make sure we will always write the correct value to the EOI + * register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2 + * for TX Interrupt and 3 for MISC Interrupt. + */ + cpdma_ctlr_eoi(priv->dma, value); cpsw_intr_disable(priv); if (priv->irq_enabled == true) { @@ -786,8 +801,6 @@ static int cpsw_poll(struct napi_struct *napi, int budget) int num_tx, num_rx; num_tx = cpdma_chan_process(priv->txch, 128); - if (num_tx) - cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); num_rx = cpdma_chan_process(priv->rxch, budget); if (num_rx < budget) { @@ -795,7 +808,6 @@ static int cpsw_poll(struct napi_struct *napi, int budget) napi_complete(napi); cpsw_intr_enable(priv); - cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); prim_cpsw = cpsw_get_slave_priv(priv, 0); if (prim_cpsw->irq_enabled == false) { prim_cpsw->irq_enabled = true; @@ -1310,8 +1322,6 @@ static int cpsw_ndo_open(struct net_device *ndev) napi_enable(&priv->napi); cpdma_ctlr_start(priv->dma); cpsw_intr_enable(priv); - cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); - cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); prim_cpsw = cpsw_get_slave_priv(priv, 0); if (prim_cpsw->irq_enabled == false) { @@ -1578,9 +1588,6 @@ static void cpsw_ndo_tx_timeout(struct net_device *ndev) cpdma_chan_start(priv->txch); cpdma_ctlr_int_ctrl(priv->dma, true); cpsw_intr_enable(priv); - cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); - cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); - } static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) @@ -1620,9 +1627,6 @@ static void cpsw_ndo_poll_controller(struct net_device *ndev) cpsw_interrupt(ndev->irq, priv); cpdma_ctlr_int_ctrl(priv->dma, true); cpsw_intr_enable(priv); - cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); - cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); - } #endif @@ -1630,16 +1634,24 @@ static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, unsigned short vid) { int ret; - int unreg_mcast_mask; + int unreg_mcast_mask = 0; + u32 port_mask; - if (priv->ndev->flags & IFF_ALLMULTI) - unreg_mcast_mask = ALE_ALL_PORTS; - else - unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; + if (priv->data.dual_emac) { + port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST; + + if (priv->ndev->flags & IFF_ALLMULTI) + unreg_mcast_mask = port_mask; + } else { + port_mask = ALE_ALL_PORTS; + + if (priv->ndev->flags & IFF_ALLMULTI) + unreg_mcast_mask = ALE_ALL_PORTS; + else + unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2; + } - ret = cpsw_ale_add_vlan(priv->ale, vid, - ALE_ALL_PORTS << priv->host_port, - 0, ALE_ALL_PORTS << priv->host_port, + ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask, unreg_mcast_mask << priv->host_port); if (ret != 0) return ret; @@ -1650,8 +1662,7 @@ static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, goto clean_vid; ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, - ALE_ALL_PORTS << priv->host_port, - ALE_VLAN, vid, 0); + port_mask, ALE_VLAN, vid, 0); if (ret != 0) goto clean_vlan_ucast; return 0; diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 097ebe7077ac..5246b3a18ff8 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -234,7 +234,7 @@ static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry, cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); } -int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask) +int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid) { u32 ale_entry[ALE_ENTRY_WORDS]; int ret, idx; @@ -245,6 +245,14 @@ int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask) if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR) continue; + /* if vid passed is -1 then remove all multicast entry from + * the table irrespective of vlan id, if a valid vlan id is + * passed then remove only multicast added to that vlan id. + * if vlan id doesn't match then move on to next entry. + */ + if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid) + continue; + if (cpsw_ale_get_mcast(ale_entry)) { u8 addr[6]; diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index c0d4127aa549..af1e7ecd87c6 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -92,7 +92,7 @@ void cpsw_ale_stop(struct cpsw_ale *ale); int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout); int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask); -int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask); +int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid); int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags, u16 vid); int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port, diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c index ea712512c7d1..5fae4354722c 100644 --- a/drivers/net/ethernet/ti/davinci_emac.c +++ b/drivers/net/ethernet/ti/davinci_emac.c @@ -62,6 +62,7 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_device.h> +#include <linux/of_mdio.h> #include <linux/of_irq.h> #include <linux/of_net.h> @@ -343,9 +344,7 @@ struct emac_priv { u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; u32 rx_addr_type; const char *phy_id; -#ifdef CONFIG_OF struct device_node *phy_node; -#endif struct phy_device *phydev; spinlock_t lock; /*platform specific members*/ @@ -922,6 +921,16 @@ static void emac_int_disable(struct emac_priv *priv) if (priv->int_disable) priv->int_disable(); + /* NOTE: Rx Threshold and Misc interrupts are not enabled */ + + /* ack rxen only then a new pulse will be generated */ + emac_write(EMAC_DM646X_MACEOIVECTOR, + EMAC_DM646X_MAC_EOI_C0_RXEN); + + /* ack txen- only then a new pulse will be generated */ + emac_write(EMAC_DM646X_MACEOIVECTOR, + EMAC_DM646X_MAC_EOI_C0_TXEN); + local_irq_restore(flags); } else { @@ -951,15 +960,6 @@ static void emac_int_enable(struct emac_priv *priv) * register */ /* NOTE: Rx Threshold and Misc interrupts are not enabled */ - - /* ack rxen only then a new pulse will be generated */ - emac_write(EMAC_DM646X_MACEOIVECTOR, - EMAC_DM646X_MAC_EOI_C0_RXEN); - - /* ack txen- only then a new pulse will be generated */ - emac_write(EMAC_DM646X_MACEOIVECTOR, - EMAC_DM646X_MAC_EOI_C0_TXEN); - } else { /* Set DM644x control registers for interrupt control */ emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); @@ -1537,7 +1537,13 @@ static int emac_dev_open(struct net_device *ndev) int i = 0; struct emac_priv *priv = netdev_priv(ndev); - pm_runtime_get(&priv->pdev->dev); + ret = pm_runtime_get_sync(&priv->pdev->dev); + if (ret < 0) { + pm_runtime_put_noidle(&priv->pdev->dev); + dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", + __func__, ret); + return ret; + } netif_carrier_off(ndev); for (cnt = 0; cnt < ETH_ALEN; cnt++) @@ -1596,8 +1602,20 @@ static int emac_dev_open(struct net_device *ndev) cpdma_ctlr_start(priv->dma); priv->phydev = NULL; + + if (priv->phy_node) { + priv->phydev = of_phy_connect(ndev, priv->phy_node, + &emac_adjust_link, 0, 0); + if (!priv->phydev) { + dev_err(emac_dev, "could not connect to phy %s\n", + priv->phy_node->full_name); + ret = -ENODEV; + goto err; + } + } + /* use the first phy on the bus if pdata did not give us a phy id */ - if (!priv->phy_id) { + if (!priv->phydev && !priv->phy_id) { struct device *phy; phy = bus_find_device(&mdio_bus_type, NULL, NULL, @@ -1606,7 +1624,7 @@ static int emac_dev_open(struct net_device *ndev) priv->phy_id = dev_name(phy); } - if (priv->phy_id && *priv->phy_id) { + if (!priv->phydev && priv->phy_id && *priv->phy_id) { priv->phydev = phy_connect(ndev, priv->phy_id, &emac_adjust_link, PHY_INTERFACE_MODE_MII); @@ -1627,7 +1645,9 @@ static int emac_dev_open(struct net_device *ndev) "(mii_bus:phy_addr=%s, id=%x)\n", priv->phydev->drv->name, dev_name(&priv->phydev->dev), priv->phydev->phy_id); - } else { + } + + if (!priv->phydev) { /* No PHY , fix the link, speed and duplex settings */ dev_notice(emac_dev, "no phy, defaulting to 100/full\n"); priv->link = 1; @@ -1724,6 +1744,15 @@ static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) struct emac_priv *priv = netdev_priv(ndev); u32 mac_control; u32 stats_clear_mask; + int err; + + err = pm_runtime_get_sync(&priv->pdev->dev); + if (err < 0) { + pm_runtime_put_noidle(&priv->pdev->dev); + dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", + __func__, err); + return &ndev->stats; + } /* update emac hardware stats and reset the registers*/ @@ -1766,6 +1795,8 @@ static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN); emac_write(EMAC_TXUNDERRUN, stats_clear_mask); + pm_runtime_put(&priv->pdev->dev); + return &ndev->stats; } @@ -1859,7 +1890,7 @@ davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv) static int davinci_emac_probe(struct platform_device *pdev) { int rc = 0; - struct resource *res; + struct resource *res, *res_ctrl; struct net_device *ndev; struct emac_priv *priv; unsigned long hw_ram_addr; @@ -1876,6 +1907,7 @@ static int davinci_emac_probe(struct platform_device *pdev) return -EBUSY; } emac_bus_frequency = clk_get_rate(emac_clk); + devm_clk_put(&pdev->dev, emac_clk); /* TODO: Probe PHY here if possible */ @@ -1917,11 +1949,20 @@ static int davinci_emac_probe(struct platform_device *pdev) rc = PTR_ERR(priv->remap_addr); goto no_pdata; } + + res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res_ctrl) { + priv->ctrl_base = + devm_ioremap_resource(&pdev->dev, res_ctrl); + if (IS_ERR(priv->ctrl_base)) + goto no_pdata; + } else { + priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; + } + priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; ndev->base_addr = (unsigned long)priv->remap_addr; - priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; - hw_ram_addr = pdata->hw_ram_addr; if (!hw_ram_addr) hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset; @@ -1980,12 +2021,22 @@ static int davinci_emac_probe(struct platform_device *pdev) ndev->ethtool_ops = ðtool_ops; netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); + pm_runtime_enable(&pdev->dev); + rc = pm_runtime_get_sync(&pdev->dev); + if (rc < 0) { + pm_runtime_put_noidle(&pdev->dev); + dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n", + __func__, rc); + goto no_cpdma_chan; + } + /* register the network device */ SET_NETDEV_DEV(ndev, &pdev->dev); rc = register_netdev(ndev); if (rc) { dev_err(&pdev->dev, "error in register_netdev\n"); rc = -ENODEV; + pm_runtime_put(&pdev->dev); goto no_cpdma_chan; } @@ -1995,9 +2046,7 @@ static int davinci_emac_probe(struct platform_device *pdev) "(regs: %p, irq: %d)\n", (void *)priv->emac_base_phys, ndev->irq); } - - pm_runtime_enable(&pdev->dev); - pm_runtime_resume(&pdev->dev); + pm_runtime_put(&pdev->dev); return 0; @@ -2071,9 +2120,14 @@ static const struct emac_platform_data am3517_emac_data = { .hw_ram_addr = 0x01e20000, }; +static const struct emac_platform_data dm816_emac_data = { + .version = EMAC_VERSION_2, +}; + static const struct of_device_id davinci_emac_of_match[] = { {.compatible = "ti,davinci-dm6467-emac", }, {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, }, + {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, }, {}, }; MODULE_DEVICE_TABLE(of, davinci_emac_of_match); diff --git a/drivers/net/ethernet/xilinx/ll_temac_main.c b/drivers/net/ethernet/xilinx/ll_temac_main.c index 9c2d91ea0af4..dbcbf0c5bcfa 100644 --- a/drivers/net/ethernet/xilinx/ll_temac_main.c +++ b/drivers/net/ethernet/xilinx/ll_temac_main.c @@ -1043,6 +1043,7 @@ static int temac_of_probe(struct platform_device *op) lp->regs = of_iomap(op->dev.of_node, 0); if (!lp->regs) { dev_err(&op->dev, "could not map temac regs.\n"); + rc = -ENOMEM; goto nodev; } @@ -1062,6 +1063,7 @@ static int temac_of_probe(struct platform_device *op) np = of_parse_phandle(op->dev.of_node, "llink-connected", 0); if (!np) { dev_err(&op->dev, "could not find DMA node\n"); + rc = -ENODEV; goto err_iounmap; } diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index c18a0c637c44..a6d2860b712c 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -1501,6 +1501,7 @@ static int axienet_of_probe(struct platform_device *op) lp->regs = of_iomap(op->dev.of_node, 0); if (!lp->regs) { dev_err(&op->dev, "could not map Axi Ethernet regs.\n"); + ret = -ENOMEM; goto nodev; } /* Setup checksum offload, but default to off if not specified */ @@ -1563,6 +1564,7 @@ static int axienet_of_probe(struct platform_device *op) np = of_parse_phandle(op->dev.of_node, "axistream-connected", 0); if (!np) { dev_err(&op->dev, "could not find DMA node\n"); + ret = -ENODEV; goto err_iounmap; } lp->dma_regs = of_iomap(np, 0); diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index 24858799c204..9d4ce388510a 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -1109,6 +1109,7 @@ static int xemaclite_of_probe(struct platform_device *ofdev) res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0); if (!res) { dev_err(dev, "no IRQ found\n"); + rc = -ENXIO; goto error; } diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c index 93e224217e24..f7ff493f1e73 100644 --- a/drivers/net/team/team.c +++ b/drivers/net/team/team.c @@ -629,6 +629,7 @@ static int team_change_mode(struct team *team, const char *kind) static void team_notify_peers_work(struct work_struct *work) { struct team *team; + int val; team = container_of(work, struct team, notify_peers.dw.work); @@ -636,9 +637,14 @@ static void team_notify_peers_work(struct work_struct *work) schedule_delayed_work(&team->notify_peers.dw, 0); return; } + val = atomic_dec_if_positive(&team->notify_peers.count_pending); + if (val < 0) { + rtnl_unlock(); + return; + } call_netdevice_notifiers(NETDEV_NOTIFY_PEERS, team->dev); rtnl_unlock(); - if (!atomic_dec_and_test(&team->notify_peers.count_pending)) + if (val) schedule_delayed_work(&team->notify_peers.dw, msecs_to_jiffies(team->notify_peers.interval)); } @@ -669,6 +675,7 @@ static void team_notify_peers_fini(struct team *team) static void team_mcast_rejoin_work(struct work_struct *work) { struct team *team; + int val; team = container_of(work, struct team, mcast_rejoin.dw.work); @@ -676,9 +683,14 @@ static void team_mcast_rejoin_work(struct work_struct *work) schedule_delayed_work(&team->mcast_rejoin.dw, 0); return; } + val = atomic_dec_if_positive(&team->mcast_rejoin.count_pending); + if (val < 0) { + rtnl_unlock(); + return; + } call_netdevice_notifiers(NETDEV_RESEND_IGMP, team->dev); rtnl_unlock(); - if (!atomic_dec_and_test(&team->mcast_rejoin.count_pending)) + if (val) schedule_delayed_work(&team->mcast_rejoin.dw, msecs_to_jiffies(team->mcast_rejoin.interval)); } diff --git a/drivers/net/usb/kaweth.c b/drivers/net/usb/kaweth.c index dcb6d33141e0..1e9cdca37014 100644 --- a/drivers/net/usb/kaweth.c +++ b/drivers/net/usb/kaweth.c @@ -1276,7 +1276,7 @@ static int usb_start_wait_urb(struct urb *urb, int timeout, int* actual_length) awd.done = 0; urb->context = &awd; - status = usb_submit_urb(urb, GFP_NOIO); + status = usb_submit_urb(urb, GFP_ATOMIC); if (status) { // something went wrong usb_free_urb(urb); diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index b8a82b86f909..602dc6668c3a 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -56,6 +56,8 @@ struct qmi_wwan_state { /* default ethernet address used by the modem */ static const u8 default_modem_addr[ETH_ALEN] = {0x02, 0x50, 0xf3}; +static const u8 buggy_fw_addr[ETH_ALEN] = {0x00, 0xa0, 0xc6, 0x00, 0x00, 0x00}; + /* Make up an ethernet header if the packet doesn't have one. * * A firmware bug common among several devices cause them to send raw @@ -332,10 +334,12 @@ next_desc: usb_driver_release_interface(driver, info->data); } - /* Never use the same address on both ends of the link, even - * if the buggy firmware told us to. + /* Never use the same address on both ends of the link, even if the + * buggy firmware told us to. Or, if device is assigned the well-known + * buggy firmware MAC address, replace it with a random address, */ - if (ether_addr_equal(dev->net->dev_addr, default_modem_addr)) + if (ether_addr_equal(dev->net->dev_addr, default_modem_addr) || + ether_addr_equal(dev->net->dev_addr, buggy_fw_addr)) eth_hw_addr_random(dev->net); /* make MAC addr easily distinguishable from an IP header */ diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 2d1c77e81836..bf405f134d3a 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -833,9 +833,6 @@ static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) index &= ~3; } - generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); - - data |= __le32_to_cpu(tmp) & ~mask; tmp = __cpu_to_le32(data); generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); @@ -874,9 +871,6 @@ static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) index &= ~3; } - generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); - - data |= __le32_to_cpu(tmp) & ~mask; tmp = __cpu_to_le32(data); generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); @@ -926,12 +920,6 @@ static void sram_write(struct r8152 *tp, u16 addr, u16 data) ocp_reg_write(tp, OCP_SRAM_DATA, data); } -static u16 sram_read(struct r8152 *tp, u16 addr) -{ - ocp_reg_write(tp, OCP_SRAM_ADDR, addr); - return ocp_reg_read(tp, OCP_SRAM_DATA); -} - static int read_mii_word(struct net_device *netdev, int phy_id, int reg) { struct r8152 *tp = netdev_priv(netdev); @@ -1897,6 +1885,22 @@ static void _rtl8152_set_rx_mode(struct net_device *netdev) netif_wake_queue(netdev); } +static netdev_features_t +rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, + netdev_features_t features) +{ + u32 mss = skb_shinfo(skb)->gso_size; + int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; + int offset = skb_transport_offset(skb); + + if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) + features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK); + else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) + features &= ~NETIF_F_GSO_MASK; + + return features; +} + static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, struct net_device *netdev) { @@ -2502,24 +2506,18 @@ static void r8153_hw_phy_cfg(struct r8152 *tp) data = ocp_reg_read(tp, OCP_POWER_CFG); data |= EN_10M_PLLOFF; ocp_reg_write(tp, OCP_POWER_CFG, data); - data = sram_read(tp, SRAM_IMPEDANCE); - data &= ~RX_DRIVING_MASK; - sram_write(tp, SRAM_IMPEDANCE, data); + sram_write(tp, SRAM_IMPEDANCE, 0x0b13); ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); ocp_data |= PFM_PWM_SWITCH; ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); - data = sram_read(tp, SRAM_LPF_CFG); - data |= LPF_AUTO_TUNE; - sram_write(tp, SRAM_LPF_CFG, data); + /* Enable LPF corner auto tune */ + sram_write(tp, SRAM_LPF_CFG, 0xf70f); - data = sram_read(tp, SRAM_10M_AMP1); - data |= GDAC_IB_UPALL; - sram_write(tp, SRAM_10M_AMP1, data); - data = sram_read(tp, SRAM_10M_AMP2); - data |= AMP_DN; - sram_write(tp, SRAM_10M_AMP2, data); + /* Adjust 10M Amplitude */ + sram_write(tp, SRAM_10M_AMP1, 0x00af); + sram_write(tp, SRAM_10M_AMP2, 0x0208); set_bit(PHY_RESET, &tp->flags); } @@ -3706,6 +3704,7 @@ static const struct net_device_ops rtl8152_netdev_ops = { .ndo_set_mac_address = rtl8152_set_mac_address, .ndo_change_mtu = rtl8152_change_mtu, .ndo_validate_addr = eth_validate_addr, + .ndo_features_check = rtl8152_features_check, }; static void r8152b_get_version(struct r8152 *tp) diff --git a/drivers/net/wireless/iwlwifi/iwl-7000.c b/drivers/net/wireless/iwlwifi/iwl-7000.c index e5be2d21868f..a5f9198d5747 100644 --- a/drivers/net/wireless/iwlwifi/iwl-7000.c +++ b/drivers/net/wireless/iwlwifi/iwl-7000.c @@ -69,8 +69,8 @@ #include "iwl-agn-hw.h" /* Highest firmware API version supported */ -#define IWL7260_UCODE_API_MAX 10 -#define IWL3160_UCODE_API_MAX 10 +#define IWL7260_UCODE_API_MAX 12 +#define IWL3160_UCODE_API_MAX 12 /* Oldest version we won't warn about */ #define IWL7260_UCODE_API_OK 10 @@ -105,7 +105,7 @@ #define IWL7265_MODULE_FIRMWARE(api) IWL7265_FW_PRE __stringify(api) ".ucode" #define IWL7265D_FW_PRE "iwlwifi-7265D-" -#define IWL7265D_MODULE_FIRMWARE(api) IWL7265_FW_PRE __stringify(api) ".ucode" +#define IWL7265D_MODULE_FIRMWARE(api) IWL7265D_FW_PRE __stringify(api) ".ucode" #define NVM_HW_SECTION_NUM_FAMILY_7000 0 diff --git a/drivers/net/wireless/iwlwifi/iwl-8000.c b/drivers/net/wireless/iwlwifi/iwl-8000.c index bf0a95cb7153..3668fc57e770 100644 --- a/drivers/net/wireless/iwlwifi/iwl-8000.c +++ b/drivers/net/wireless/iwlwifi/iwl-8000.c @@ -69,7 +69,7 @@ #include "iwl-agn-hw.h" /* Highest firmware API version supported */ -#define IWL8000_UCODE_API_MAX 10 +#define IWL8000_UCODE_API_MAX 12 /* Oldest version we won't warn about */ #define IWL8000_UCODE_API_OK 10 diff --git a/drivers/net/wireless/iwlwifi/iwl-fw-file.h b/drivers/net/wireless/iwlwifi/iwl-fw-file.h index f2a047f6bb3e..1bbe4fc47b97 100644 --- a/drivers/net/wireless/iwlwifi/iwl-fw-file.h +++ b/drivers/net/wireless/iwlwifi/iwl-fw-file.h @@ -243,6 +243,9 @@ enum iwl_ucode_tlv_flag { * @IWL_UCODE_TLV_API_SF_NO_DUMMY_NOTIF: ucode supports disabling dummy notif. * @IWL_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time * longer than the passive one, which is essential for fragmented scan. + * @IWL_UCODE_TLV_API_BASIC_DWELL: use only basic dwell time in scan command, + * regardless of the band or the number of the probes. FW will calculate + * the actual dwell time. */ enum iwl_ucode_tlv_api { IWL_UCODE_TLV_API_WOWLAN_CONFIG_TID = BIT(0), @@ -253,6 +256,7 @@ enum iwl_ucode_tlv_api { IWL_UCODE_TLV_API_LMAC_SCAN = BIT(6), IWL_UCODE_TLV_API_SF_NO_DUMMY_NOTIF = BIT(7), IWL_UCODE_TLV_API_FRAGMENTED_SCAN = BIT(8), + IWL_UCODE_TLV_API_BASIC_DWELL = BIT(13), }; /** diff --git a/drivers/net/wireless/iwlwifi/mvm/fw-api-scan.h b/drivers/net/wireless/iwlwifi/mvm/fw-api-scan.h index 1f2acf47bfb2..201846de94e7 100644 --- a/drivers/net/wireless/iwlwifi/mvm/fw-api-scan.h +++ b/drivers/net/wireless/iwlwifi/mvm/fw-api-scan.h @@ -672,6 +672,7 @@ struct iwl_scan_channel_opt { * @IWL_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented * @IWL_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report * and DS parameter set IEs into probe requests. + * @IWL_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches */ enum iwl_mvm_lmac_scan_flags { IWL_MVM_LMAC_SCAN_FLAG_PASS_ALL = BIT(0), @@ -681,6 +682,7 @@ enum iwl_mvm_lmac_scan_flags { IWL_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = BIT(4), IWL_MVM_LMAC_SCAN_FLAG_FRAGMENTED = BIT(5), IWL_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = BIT(6), + IWL_MVM_LMAC_SCAN_FLAG_MATCH = BIT(9), }; enum iwl_scan_priority { diff --git a/drivers/net/wireless/iwlwifi/mvm/scan.c b/drivers/net/wireless/iwlwifi/mvm/scan.c index e5294d01181e..ec9a8e7bae1d 100644 --- a/drivers/net/wireless/iwlwifi/mvm/scan.c +++ b/drivers/net/wireless/iwlwifi/mvm/scan.c @@ -171,15 +171,21 @@ static void iwl_mvm_scan_fill_ssids(struct iwl_ssid_ie *cmd_ssid, * already included in the probe template, so we need to set only * req->n_ssids - 1 bits in addition to the first bit. */ -static u16 iwl_mvm_get_active_dwell(enum ieee80211_band band, int n_ssids) +static u16 iwl_mvm_get_active_dwell(struct iwl_mvm *mvm, + enum ieee80211_band band, int n_ssids) { + if (mvm->fw->ucode_capa.api[0] & IWL_UCODE_TLV_API_BASIC_DWELL) + return 10; if (band == IEEE80211_BAND_2GHZ) return 20 + 3 * (n_ssids + 1); return 10 + 2 * (n_ssids + 1); } -static u16 iwl_mvm_get_passive_dwell(enum ieee80211_band band) +static u16 iwl_mvm_get_passive_dwell(struct iwl_mvm *mvm, + enum ieee80211_band band) { + if (mvm->fw->ucode_capa.api[0] & IWL_UCODE_TLV_API_BASIC_DWELL) + return 110; return band == IEEE80211_BAND_2GHZ ? 100 + 20 : 100 + 10; } @@ -331,7 +337,8 @@ static void iwl_mvm_scan_calc_params(struct iwl_mvm *mvm, */ if (vif->type == NL80211_IFTYPE_P2P_DEVICE) { u32 passive_dwell = - iwl_mvm_get_passive_dwell(IEEE80211_BAND_2GHZ); + iwl_mvm_get_passive_dwell(mvm, + IEEE80211_BAND_2GHZ); params->max_out_time = passive_dwell; } else { params->passive_fragmented = true; @@ -348,8 +355,8 @@ not_bound: params->dwell[band].passive = frag_passive_dwell; else params->dwell[band].passive = - iwl_mvm_get_passive_dwell(band); - params->dwell[band].active = iwl_mvm_get_active_dwell(band, + iwl_mvm_get_passive_dwell(mvm, band); + params->dwell[band].active = iwl_mvm_get_active_dwell(mvm, band, n_ssids); } } @@ -1448,6 +1455,8 @@ int iwl_mvm_unified_sched_scan_lmac(struct iwl_mvm *mvm, if (iwl_mvm_scan_pass_all(mvm, req)) flags |= IWL_MVM_LMAC_SCAN_FLAG_PASS_ALL; + else + flags |= IWL_MVM_LMAC_SCAN_FLAG_MATCH; if (req->n_ssids == 1 && req->ssids[0].ssid_len != 0) flags |= IWL_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION; diff --git a/drivers/net/wireless/iwlwifi/mvm/tx.c b/drivers/net/wireless/iwlwifi/mvm/tx.c index 4f15d9decc81..4333306ccdee 100644 --- a/drivers/net/wireless/iwlwifi/mvm/tx.c +++ b/drivers/net/wireless/iwlwifi/mvm/tx.c @@ -108,8 +108,12 @@ void iwl_mvm_set_tx_cmd(struct iwl_mvm *mvm, struct sk_buff *skb, tx_flags &= ~TX_CMD_FLG_SEQ_CTL; } - /* tid_tspec will default to 0 = BE when QOS isn't enabled */ - ac = tid_to_mac80211_ac[tx_cmd->tid_tspec]; + /* Default to 0 (BE) when tid_spec is set to IWL_TID_NON_QOS */ + if (tx_cmd->tid_tspec < IWL_MAX_TID_COUNT) + ac = tid_to_mac80211_ac[tx_cmd->tid_tspec]; + else + ac = tid_to_mac80211_ac[0]; + tx_flags |= iwl_mvm_bt_coex_tx_prio(mvm, hdr, info, ac) << TX_CMD_FLG_BT_PRIO_POS; diff --git a/drivers/net/wireless/iwlwifi/mvm/utils.c b/drivers/net/wireless/iwlwifi/mvm/utils.c index e56e77ef5d2e..917431e30f74 100644 --- a/drivers/net/wireless/iwlwifi/mvm/utils.c +++ b/drivers/net/wireless/iwlwifi/mvm/utils.c @@ -665,7 +665,7 @@ bool iwl_mvm_rx_diversity_allowed(struct iwl_mvm *mvm) if (num_of_ant(mvm->fw->valid_rx_ant) == 1) return false; - if (!mvm->cfg->rx_with_siso_diversity) + if (mvm->cfg->rx_with_siso_diversity) return false; ieee80211_iterate_active_interfaces_atomic( diff --git a/drivers/net/wireless/iwlwifi/pcie/drv.c b/drivers/net/wireless/iwlwifi/pcie/drv.c index 2f0c4b170344..d5aadb00dd9e 100644 --- a/drivers/net/wireless/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/iwlwifi/pcie/drv.c @@ -527,8 +527,10 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) else if (cfg == &iwl7265_n_cfg) cfg_7265d = &iwl7265d_n_cfg; if (cfg_7265d && - (iwl_trans->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_7265D) + (iwl_trans->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_7265D) { cfg = cfg_7265d; + iwl_trans->cfg = cfg_7265d; + } #endif pci_set_drvdata(pdev, iwl_trans); diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c index 846a2e6e34d8..c70efb9a6e78 100644 --- a/drivers/net/wireless/rtlwifi/pci.c +++ b/drivers/net/wireless/rtlwifi/pci.c @@ -666,7 +666,8 @@ tx_status_ok: } static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, - u8 *entry, int rxring_idx, int desc_idx) + struct sk_buff *new_skb, u8 *entry, + int rxring_idx, int desc_idx) { struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); @@ -674,11 +675,15 @@ static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, u8 tmp_one = 1; struct sk_buff *skb; + if (likely(new_skb)) { + skb = new_skb; + goto remap; + } skb = dev_alloc_skb(rtlpci->rxbuffersize); if (!skb) return 0; - rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; +remap: /* just set skb->cb to mapping addr for pci_unmap_single use */ *((dma_addr_t *)skb->cb) = pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), @@ -686,6 +691,7 @@ static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, bufferaddress = *((dma_addr_t *)skb->cb); if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) return 0; + rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; if (rtlpriv->use_new_trx_flow) { rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, HW_DESC_RX_PREPARE, @@ -781,6 +787,7 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) /*rx pkt */ struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ rtlpci->rx_ring[rxring_idx].idx]; + struct sk_buff *new_skb; if (rtlpriv->use_new_trx_flow) { rx_remained_cnt = @@ -807,6 +814,13 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); + /* get a new skb - if fail, old one will be reused */ + new_skb = dev_alloc_skb(rtlpci->rxbuffersize); + if (unlikely(!new_skb)) { + pr_err("Allocation of new skb failed in %s\n", + __func__); + goto no_new; + } if (rtlpriv->use_new_trx_flow) { buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc @@ -911,14 +925,16 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) schedule_work(&rtlpriv->works.lps_change_work); } end: + skb = new_skb; +no_new: if (rtlpriv->use_new_trx_flow) { - _rtl_pci_init_one_rxdesc(hw, (u8 *)buffer_desc, + _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, rxring_idx, - rtlpci->rx_ring[rxring_idx].idx); + rtlpci->rx_ring[rxring_idx].idx); } else { - _rtl_pci_init_one_rxdesc(hw, (u8 *)pdesc, rxring_idx, + _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, + rxring_idx, rtlpci->rx_ring[rxring_idx].idx); - if (rtlpci->rx_ring[rxring_idx].idx == rtlpci->rxringcount - 1) rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, @@ -1307,7 +1323,7 @@ static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) rtlpci->rx_ring[rxring_idx].idx = 0; for (i = 0; i < rtlpci->rxringcount; i++) { entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; - if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry, + if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, rxring_idx, i)) return -ENOMEM; } @@ -1332,7 +1348,7 @@ static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) for (i = 0; i < rtlpci->rxringcount; i++) { entry = &rtlpci->rx_ring[rxring_idx].desc[i]; - if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry, + if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, rxring_idx, i)) return -ENOMEM; } diff --git a/drivers/net/xen-netback/xenbus.c b/drivers/net/xen-netback/xenbus.c index efbaf2ae1999..794204e34fba 100644 --- a/drivers/net/xen-netback/xenbus.c +++ b/drivers/net/xen-netback/xenbus.c @@ -737,6 +737,7 @@ static void connect(struct backend_info *be) } queue->remaining_credit = credit_bytes; + queue->credit_usec = credit_usec; err = connect_rings(be, queue); if (err) { diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c index 22bcb4e12e2a..d8c10764f130 100644 --- a/drivers/net/xen-netfront.c +++ b/drivers/net/xen-netfront.c @@ -88,10 +88,8 @@ struct netfront_cb { #define IRQ_NAME_SIZE (QUEUE_NAME_SIZE + 3) struct netfront_stats { - u64 rx_packets; - u64 tx_packets; - u64 rx_bytes; - u64 tx_bytes; + u64 packets; + u64 bytes; struct u64_stats_sync syncp; }; @@ -160,7 +158,8 @@ struct netfront_info { struct netfront_queue *queues; /* Statistics */ - struct netfront_stats __percpu *stats; + struct netfront_stats __percpu *rx_stats; + struct netfront_stats __percpu *tx_stats; atomic_t rx_gso_checksum_fixup; }; @@ -565,7 +564,7 @@ static int xennet_start_xmit(struct sk_buff *skb, struct net_device *dev) { unsigned short id; struct netfront_info *np = netdev_priv(dev); - struct netfront_stats *stats = this_cpu_ptr(np->stats); + struct netfront_stats *tx_stats = this_cpu_ptr(np->tx_stats); struct xen_netif_tx_request *tx; char *data = skb->data; RING_IDX i; @@ -672,10 +671,10 @@ static int xennet_start_xmit(struct sk_buff *skb, struct net_device *dev) if (notify) notify_remote_via_irq(queue->tx_irq); - u64_stats_update_begin(&stats->syncp); - stats->tx_bytes += skb->len; - stats->tx_packets++; - u64_stats_update_end(&stats->syncp); + u64_stats_update_begin(&tx_stats->syncp); + tx_stats->bytes += skb->len; + tx_stats->packets++; + u64_stats_update_end(&tx_stats->syncp); /* Note: It is not safe to access skb after xennet_tx_buf_gc()! */ xennet_tx_buf_gc(queue); @@ -931,7 +930,7 @@ static int checksum_setup(struct net_device *dev, struct sk_buff *skb) static int handle_incoming_queue(struct netfront_queue *queue, struct sk_buff_head *rxq) { - struct netfront_stats *stats = this_cpu_ptr(queue->info->stats); + struct netfront_stats *rx_stats = this_cpu_ptr(queue->info->rx_stats); int packets_dropped = 0; struct sk_buff *skb; @@ -952,10 +951,10 @@ static int handle_incoming_queue(struct netfront_queue *queue, continue; } - u64_stats_update_begin(&stats->syncp); - stats->rx_packets++; - stats->rx_bytes += skb->len; - u64_stats_update_end(&stats->syncp); + u64_stats_update_begin(&rx_stats->syncp); + rx_stats->packets++; + rx_stats->bytes += skb->len; + u64_stats_update_end(&rx_stats->syncp); /* Pass it up. */ napi_gro_receive(&queue->napi, skb); @@ -1079,18 +1078,22 @@ static struct rtnl_link_stats64 *xennet_get_stats64(struct net_device *dev, int cpu; for_each_possible_cpu(cpu) { - struct netfront_stats *stats = per_cpu_ptr(np->stats, cpu); + struct netfront_stats *rx_stats = per_cpu_ptr(np->rx_stats, cpu); + struct netfront_stats *tx_stats = per_cpu_ptr(np->tx_stats, cpu); u64 rx_packets, rx_bytes, tx_packets, tx_bytes; unsigned int start; do { - start = u64_stats_fetch_begin_irq(&stats->syncp); + start = u64_stats_fetch_begin_irq(&tx_stats->syncp); + tx_packets = tx_stats->packets; + tx_bytes = tx_stats->bytes; + } while (u64_stats_fetch_retry_irq(&tx_stats->syncp, start)); - rx_packets = stats->rx_packets; - tx_packets = stats->tx_packets; - rx_bytes = stats->rx_bytes; - tx_bytes = stats->tx_bytes; - } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); + do { + start = u64_stats_fetch_begin_irq(&rx_stats->syncp); + rx_packets = rx_stats->packets; + rx_bytes = rx_stats->bytes; + } while (u64_stats_fetch_retry_irq(&rx_stats->syncp, start)); tot->rx_packets += rx_packets; tot->tx_packets += tx_packets; @@ -1275,6 +1278,15 @@ static const struct net_device_ops xennet_netdev_ops = { #endif }; +static void xennet_free_netdev(struct net_device *netdev) +{ + struct netfront_info *np = netdev_priv(netdev); + + free_percpu(np->rx_stats); + free_percpu(np->tx_stats); + free_netdev(netdev); +} + static struct net_device *xennet_create_dev(struct xenbus_device *dev) { int err; @@ -1295,8 +1307,11 @@ static struct net_device *xennet_create_dev(struct xenbus_device *dev) np->queues = NULL; err = -ENOMEM; - np->stats = netdev_alloc_pcpu_stats(struct netfront_stats); - if (np->stats == NULL) + np->rx_stats = netdev_alloc_pcpu_stats(struct netfront_stats); + if (np->rx_stats == NULL) + goto exit; + np->tx_stats = netdev_alloc_pcpu_stats(struct netfront_stats); + if (np->tx_stats == NULL) goto exit; netdev->netdev_ops = &xennet_netdev_ops; @@ -1327,7 +1342,7 @@ static struct net_device *xennet_create_dev(struct xenbus_device *dev) return netdev; exit: - free_netdev(netdev); + xennet_free_netdev(netdev); return ERR_PTR(err); } @@ -1369,7 +1384,7 @@ static int netfront_probe(struct xenbus_device *dev, return 0; fail: - free_netdev(netdev); + xennet_free_netdev(netdev); dev_set_drvdata(&dev->dev, NULL); return err; } @@ -2189,9 +2204,7 @@ static int xennet_remove(struct xenbus_device *dev) info->queues = NULL; } - free_percpu(info->stats); - - free_netdev(info->netdev); + xennet_free_netdev(info->netdev); return 0; } diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c index e34da13885e8..27fa62ce6136 100644 --- a/drivers/phy/phy-miphy28lp.c +++ b/drivers/phy/phy-miphy28lp.c @@ -1050,7 +1050,8 @@ static int miphy28lp_init(struct phy *phy) ret = miphy28lp_init_usb3(miphy_phy); break; default: - return -EINVAL; + ret = -EINVAL; + break; } mutex_unlock(&miphy_dev->miphy_mutex); diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c index c96e8183a8ff..efe724f97e02 100644 --- a/drivers/phy/phy-omap-control.c +++ b/drivers/phy/phy-omap-control.c @@ -29,10 +29,9 @@ /** * omap_control_pcie_pcs - set the PCS delay count * @dev: the control module device - * @id: index of the pcie PHY (should be 1 or 2) * @delay: 8 bit delay value */ -void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay) +void omap_control_pcie_pcs(struct device *dev, u8 delay) { u32 val; struct omap_control_phy *control_phy; @@ -55,8 +54,8 @@ void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay) val = readl(control_phy->pcie_pcs); val &= ~(OMAP_CTRL_PCIE_PCS_MASK << - (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT)); - val |= delay << (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT); + OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT); + val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT); writel(val, control_phy->pcie_pcs); } EXPORT_SYMBOL_GPL(omap_control_pcie_pcs); diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c index fb02a67c9181..a2b08f3ccb03 100644 --- a/drivers/phy/phy-sun4i-usb.c +++ b/drivers/phy/phy-sun4i-usb.c @@ -244,7 +244,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) else data->num_phys = 3; - if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy")) + if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy") || + of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy")) data->disc_thresh = 3; else data->disc_thresh = 2; diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c index 1387b4d4afe3..465de2c800f2 100644 --- a/drivers/phy/phy-ti-pipe3.c +++ b/drivers/phy/phy-ti-pipe3.c @@ -82,7 +82,6 @@ struct ti_pipe3 { struct clk *refclk; struct clk *div_clk; struct pipe3_dpll_map *dpll_map; - u8 id; }; static struct pipe3_dpll_map dpll_map_usb[] = { @@ -217,8 +216,13 @@ static int ti_pipe3_init(struct phy *x) u32 val; int ret = 0; + /* + * Set pcie_pcs register to 0x96 for proper functioning of phy + * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table + * 18-1804. + */ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) { - omap_control_pcie_pcs(phy->control_dev, phy->id, 0xF1); + omap_control_pcie_pcs(phy->control_dev, 0x96); return 0; } @@ -347,8 +351,6 @@ static int ti_pipe3_probe(struct platform_device *pdev) } if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) { - if (of_property_read_u8(node, "id", &phy->id) < 0) - phy->id = 1; clk = devm_clk_get(phy->dev, "dpll_ref"); if (IS_ERR(clk)) { diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index e4f65510c87e..89dca77ca038 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1801,14 +1801,15 @@ void pinctrl_unregister(struct pinctrl_dev *pctldev) if (pctldev == NULL) return; - mutex_lock(&pinctrldev_list_mutex); mutex_lock(&pctldev->mutex); - pinctrl_remove_device_debugfs(pctldev); + mutex_unlock(&pctldev->mutex); if (!IS_ERR(pctldev->p)) pinctrl_put(pctldev->p); + mutex_lock(&pinctrldev_list_mutex); + mutex_lock(&pctldev->mutex); /* TODO: check that no pinmuxes are still active? */ list_del(&pctldev->node); /* Destroy descriptor tree */ diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index ba74f0aa60c7..43eacc924b7e 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -89,6 +89,7 @@ struct rockchip_iomux { * @reg_pull: optional separate register for additional pull settings * @clk: clock of the gpio bank * @irq: interrupt of the gpio bank + * @saved_enables: Saved content of GPIO_INTEN at suspend time. * @pin_base: first pin number * @nr_pins: number of pins in this bank * @name: name of the bank @@ -107,6 +108,7 @@ struct rockchip_pin_bank { struct regmap *regmap_pull; struct clk *clk; int irq; + u32 saved_enables; u32 pin_base; u8 nr_pins; char *name; @@ -1396,10 +1398,7 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) { struct irq_chip *chip = irq_get_chip(irq); struct rockchip_pin_bank *bank = irq_get_handler_data(irq); - u32 polarity = 0, data = 0; u32 pend; - bool edge_changed = false; - unsigned long flags; dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); @@ -1407,12 +1406,6 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); - if (bank->toggle_edge_mode) { - polarity = readl_relaxed(bank->reg_base + - GPIO_INT_POLARITY); - data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); - } - while (pend) { unsigned int virq; @@ -1432,27 +1425,31 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) * needs manual intervention. */ if (bank->toggle_edge_mode & BIT(irq)) { - if (data & BIT(irq)) - polarity &= ~BIT(irq); - else - polarity |= BIT(irq); + u32 data, data_old, polarity; + unsigned long flags; - edge_changed = true; - } + data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); + do { + spin_lock_irqsave(&bank->slock, flags); - generic_handle_irq(virq); - } + polarity = readl_relaxed(bank->reg_base + + GPIO_INT_POLARITY); + if (data & BIT(irq)) + polarity &= ~BIT(irq); + else + polarity |= BIT(irq); + writel(polarity, + bank->reg_base + GPIO_INT_POLARITY); - if (bank->toggle_edge_mode && edge_changed) { - /* Interrupt params should only be set with ints disabled */ - spin_lock_irqsave(&bank->slock, flags); + spin_unlock_irqrestore(&bank->slock, flags); - data = readl_relaxed(bank->reg_base + GPIO_INTEN); - writel_relaxed(0, bank->reg_base + GPIO_INTEN); - writel(polarity, bank->reg_base + GPIO_INT_POLARITY); - writel(data, bank->reg_base + GPIO_INTEN); + data_old = data; + data = readl_relaxed(bank->reg_base + + GPIO_EXT_PORT); + } while ((data & BIT(irq)) != (data_old & BIT(irq))); + } - spin_unlock_irqrestore(&bank->slock, flags); + generic_handle_irq(virq); } chained_irq_exit(chip, desc); @@ -1543,6 +1540,51 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) return 0; } +static void rockchip_irq_suspend(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + + bank->saved_enables = irq_reg_readl(gc, GPIO_INTEN); + irq_reg_writel(gc, gc->wake_active, GPIO_INTEN); +} + +static void rockchip_irq_resume(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + + irq_reg_writel(gc, bank->saved_enables, GPIO_INTEN); +} + +static void rockchip_irq_disable(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + u32 val; + + irq_gc_lock(gc); + + val = irq_reg_readl(gc, GPIO_INTEN); + val &= ~d->mask; + irq_reg_writel(gc, val, GPIO_INTEN); + + irq_gc_unlock(gc); +} + +static void rockchip_irq_enable(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + u32 val; + + irq_gc_lock(gc); + + val = irq_reg_readl(gc, GPIO_INTEN); + val |= d->mask; + irq_reg_writel(gc, val, GPIO_INTEN); + + irq_gc_unlock(gc); +} + static int rockchip_interrupts_register(struct platform_device *pdev, struct rockchip_pinctrl *info) { @@ -1581,12 +1623,16 @@ static int rockchip_interrupts_register(struct platform_device *pdev, gc = irq_get_domain_generic_chip(bank->domain, 0); gc->reg_base = bank->reg_base; gc->private = bank; - gc->chip_types[0].regs.mask = GPIO_INTEN; + gc->chip_types[0].regs.mask = GPIO_INTMASK; gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; - gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; - gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; + gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; + gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; + gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; gc->wake_enabled = IRQ_MSK(bank->nr_pins); diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 7c9d51382248..9e5ec00084bb 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1012,8 +1012,10 @@ static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin_id) { unsigned long config; - st_pinconf_get(pctldev, pin_id, &config); + mutex_unlock(&pctldev->mutex); + st_pinconf_get(pctldev, pin_id, &config); + mutex_lock(&pctldev->mutex); seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n" "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," "de:%ld,rt-clk:%ld,rt-delay:%ld]", @@ -1443,6 +1445,7 @@ static struct gpio_chip st_gpio_template = { static struct irq_chip st_gpio_irqchip = { .name = "GPIO", + .irq_disable = st_gpio_irq_mask, .irq_mask = st_gpio_irq_mask, .irq_unmask = st_gpio_irq_unmask, .irq_set_type = st_gpio_irq_set_type, diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index c5cef59f5965..779950c62e53 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -798,10 +798,8 @@ static int pinmux_xway_probe(struct platform_device *pdev) /* load the gpio chip */ xway_chip.dev = &pdev->dev; - of_gpiochip_add(&xway_chip); ret = gpiochip_add(&xway_chip); if (ret) { - of_gpiochip_remove(&xway_chip); dev_err(&pdev->dev, "Failed to register gpio chip\n"); return ret; } diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index e730935fa457..ed7017df065d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -865,10 +865,10 @@ static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) { - int i = 0; + int i; const struct msm_function *func = pctrl->soc->functions; - for (; i <= pctrl->soc->nfunctions; i++) + for (i = 0; i < pctrl->soc->nfunctions; i++) if (!strcmp(func[i].name, "ps_hold")) { pctrl->restart_nb.notifier_call = msm_ps_hold_restart; pctrl->restart_nb.priority = 128; diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c index eebc52cb6984..3d95c87160b3 100644 --- a/drivers/reset/reset-sunxi.c +++ b/drivers/reset/reset-sunxi.c @@ -102,6 +102,8 @@ static int sunxi_reset_init(struct device_node *np) goto err_alloc; } + spin_lock_init(&data->lock); + data->rcdev.owner = THIS_MODULE; data->rcdev.nr_resets = size * 32; data->rcdev.ops = &sunxi_reset_ops; @@ -157,6 +159,8 @@ static int sunxi_reset_probe(struct platform_device *pdev) if (IS_ERR(data->membase)) return PTR_ERR(data->membase); + spin_lock_init(&data->lock); + data->rcdev.owner = THIS_MODULE; data->rcdev.nr_resets = resource_size(res) * 32; data->rcdev.ops = &sunxi_reset_ops; diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c index 91e97ec01418..4d41bf75c233 100644 --- a/drivers/s390/crypto/ap_bus.c +++ b/drivers/s390/crypto/ap_bus.c @@ -1163,9 +1163,13 @@ static inline int ap_test_config_card_id(unsigned int id) */ static inline int ap_test_config_domain(unsigned int domain) { - if (!ap_configuration) - return 1; - return ap_test_config(ap_configuration->aqm, domain); + if (!ap_configuration) /* QCI not supported */ + if (domain < 16) + return 1; /* then domains 0...15 are configured */ + else + return 0; + else + return ap_test_config(ap_configuration->aqm, domain); } /** diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 12ca291c1380..cce1cbc1a927 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -734,7 +734,9 @@ qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) * Return target busy if we've received a non-zero retry_delay_timer * in a FCP_RSP. */ - if (time_after(jiffies, fcport->retry_delay_timestamp)) + if (fcport->retry_delay_timestamp == 0) { + /* retry delay not set */ + } else if (time_after(jiffies, fcport->retry_delay_timestamp)) fcport->retry_delay_timestamp = 0; else goto qc24_target_busy; diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index 9ea95dd3e260..6d5c0b8cb0bb 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c @@ -591,7 +591,6 @@ static void scsi_free_sgtable(struct scsi_data_buffer *sdb, bool mq) static int scsi_alloc_sgtable(struct scsi_data_buffer *sdb, int nents, bool mq) { struct scatterlist *first_chunk = NULL; - gfp_t gfp_mask = mq ? GFP_NOIO : GFP_ATOMIC; int ret; BUG_ON(!nents); @@ -606,7 +605,7 @@ static int scsi_alloc_sgtable(struct scsi_data_buffer *sdb, int nents, bool mq) } ret = __sg_alloc_table(&sdb->table, nents, SCSI_MAX_SG_SEGMENTS, - first_chunk, gfp_mask, scsi_sg_alloc); + first_chunk, GFP_ATOMIC, scsi_sg_alloc); if (unlikely(ret)) scsi_free_sgtable(sdb, mq); return ret; diff --git a/drivers/staging/vt6655/baseband.c b/drivers/staging/vt6655/baseband.c index 86c72ba0a0cd..f8c5fc371c4c 100644 --- a/drivers/staging/vt6655/baseband.c +++ b/drivers/staging/vt6655/baseband.c @@ -2177,7 +2177,7 @@ bool BBbVT3253Init(struct vnt_private *priv) /* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/ /* Select VC1/VC2, CR215 = 0x02->0x06 */ - bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06); + bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06); /* }} */ for (ii = 0; ii < CB_VT3253B0_AGC; ii++) diff --git a/drivers/staging/vt6655/channel.c b/drivers/staging/vt6655/channel.c index c8f739dd346e..70f870541f92 100644 --- a/drivers/staging/vt6655/channel.c +++ b/drivers/staging/vt6655/channel.c @@ -182,6 +182,14 @@ bool set_channel(void *pDeviceHandler, unsigned int uConnectionChannel) if (pDevice->byCurrentCh == uConnectionChannel) return bResult; + /* Set VGA to max sensitivity */ + if (pDevice->bUpdateBBVGA && + pDevice->byBBVGACurrent != pDevice->abyBBVGA[0]) { + pDevice->byBBVGACurrent = pDevice->abyBBVGA[0]; + + BBvSetVGAGainOffset(pDevice, pDevice->byBBVGACurrent); + } + /* clear NAV */ MACvRegBitsOn(pDevice->PortOffset, MAC_REG_MACCR, MACCR_CLRNAV); diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c index 83e4162c0094..cd1a277d853b 100644 --- a/drivers/staging/vt6655/device_main.c +++ b/drivers/staging/vt6655/device_main.c @@ -1232,7 +1232,7 @@ static int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) head_td = priv->apCurrTD[dma_idx]; - head_td->m_td1TD1.byTCR = (TCR_EDP|TCR_STP); + head_td->m_td1TD1.byTCR = 0; head_td->pTDInfo->skb = skb; @@ -1257,6 +1257,11 @@ static int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) priv->bPWBitOn = false; + /* Set TSR1 & ReqCount in TxDescHead */ + head_td->m_td1TD1.byTCR |= (TCR_STP | TCR_EDP | EDMSDU); + head_td->m_td1TD1.wReqCount = + cpu_to_le16((u16)head_td->pTDInfo->dwReqCount); + head_td->pTDInfo->byFlags = TD_FLAGS_NETIF_SKB; if (dma_idx == TYPE_AC0DMA) @@ -1500,9 +1505,11 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw, if (conf->enable_beacon) { vnt_beacon_enable(priv, vif, conf); - MACvRegBitsOn(priv, MAC_REG_TCR, TCR_AUTOBCNTX); + MACvRegBitsOn(priv->PortOffset, MAC_REG_TCR, + TCR_AUTOBCNTX); } else { - MACvRegBitsOff(priv, MAC_REG_TCR, TCR_AUTOBCNTX); + MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR, + TCR_AUTOBCNTX); } } diff --git a/drivers/staging/vt6655/rxtx.c b/drivers/staging/vt6655/rxtx.c index 61c39dd7ad01..b5b0155961f2 100644 --- a/drivers/staging/vt6655/rxtx.c +++ b/drivers/staging/vt6655/rxtx.c @@ -1204,13 +1204,10 @@ s_cbFillTxBufHead(struct vnt_private *pDevice, unsigned char byPktType, ptdCurr = (PSTxDesc)pHeadTD; - ptdCurr->pTDInfo->dwReqCount = cbReqCount - uPadding; + ptdCurr->pTDInfo->dwReqCount = cbReqCount; ptdCurr->pTDInfo->dwHeaderLength = cbHeaderLength; ptdCurr->pTDInfo->skb_dma = ptdCurr->pTDInfo->buf_dma; ptdCurr->buff_addr = cpu_to_le32(ptdCurr->pTDInfo->skb_dma); - /* Set TSR1 & ReqCount in TxDescHead */ - ptdCurr->m_td1TD1.byTCR |= (TCR_STP | TCR_EDP | EDMSDU); - ptdCurr->m_td1TD1.wReqCount = cpu_to_le16((unsigned short)(cbReqCount)); return cbHeaderLength; } diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c index 55f6774f706f..aebde3289c50 100644 --- a/drivers/target/iscsi/iscsi_target.c +++ b/drivers/target/iscsi/iscsi_target.c @@ -2027,10 +2027,10 @@ iscsit_process_text_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd, goto reject; } if (!strncmp("=All", text_ptr, 4)) { - cmd->cmd_flags |= IFC_SENDTARGETS_ALL; + cmd->cmd_flags |= ICF_SENDTARGETS_ALL; } else if (!strncmp("=iqn.", text_ptr, 5) || !strncmp("=eui.", text_ptr, 5)) { - cmd->cmd_flags |= IFC_SENDTARGETS_SINGLE; + cmd->cmd_flags |= ICF_SENDTARGETS_SINGLE; } else { pr_err("Unable to locate valid SendTargets=%s value\n", text_ptr); goto reject; @@ -3415,10 +3415,10 @@ iscsit_build_sendtargets_response(struct iscsi_cmd *cmd, return -ENOMEM; } /* - * Locate pointer to iqn./eui. string for IFC_SENDTARGETS_SINGLE + * Locate pointer to iqn./eui. string for ICF_SENDTARGETS_SINGLE * explicit case.. */ - if (cmd->cmd_flags & IFC_SENDTARGETS_SINGLE) { + if (cmd->cmd_flags & ICF_SENDTARGETS_SINGLE) { text_ptr = strchr(text_in, '='); if (!text_ptr) { pr_err("Unable to locate '=' string in text_in:" @@ -3434,7 +3434,7 @@ iscsit_build_sendtargets_response(struct iscsi_cmd *cmd, spin_lock(&tiqn_lock); list_for_each_entry(tiqn, &g_tiqn_list, tiqn_list) { - if ((cmd->cmd_flags & IFC_SENDTARGETS_SINGLE) && + if ((cmd->cmd_flags & ICF_SENDTARGETS_SINGLE) && strcmp(tiqn->tiqn, text_ptr)) { continue; } @@ -3512,7 +3512,7 @@ eob: if (end_of_buf) break; - if (cmd->cmd_flags & IFC_SENDTARGETS_SINGLE) + if (cmd->cmd_flags & ICF_SENDTARGETS_SINGLE) break; } spin_unlock(&tiqn_lock); diff --git a/drivers/target/iscsi/iscsi_target_core.h b/drivers/target/iscsi/iscsi_target_core.h index 09a522bae222..cbcff38ac9b7 100644 --- a/drivers/target/iscsi/iscsi_target_core.h +++ b/drivers/target/iscsi/iscsi_target_core.h @@ -135,8 +135,8 @@ enum cmd_flags_table { ICF_CONTIG_MEMORY = 0x00000020, ICF_ATTACHED_TO_RQUEUE = 0x00000040, ICF_OOO_CMDSN = 0x00000080, - IFC_SENDTARGETS_ALL = 0x00000100, - IFC_SENDTARGETS_SINGLE = 0x00000200, + ICF_SENDTARGETS_ALL = 0x00000100, + ICF_SENDTARGETS_SINGLE = 0x00000200, }; /* struct iscsi_cmd->i_state */ diff --git a/drivers/target/target_core_device.c b/drivers/target/target_core_device.c index 7653cfb027a2..58f49ff69b14 100644 --- a/drivers/target/target_core_device.c +++ b/drivers/target/target_core_device.c @@ -1103,51 +1103,6 @@ int se_dev_set_queue_depth(struct se_device *dev, u32 queue_depth) } EXPORT_SYMBOL(se_dev_set_queue_depth); -int se_dev_set_fabric_max_sectors(struct se_device *dev, u32 fabric_max_sectors) -{ - int block_size = dev->dev_attrib.block_size; - - if (dev->export_count) { - pr_err("dev[%p]: Unable to change SE Device" - " fabric_max_sectors while export_count is %d\n", - dev, dev->export_count); - return -EINVAL; - } - if (!fabric_max_sectors) { - pr_err("dev[%p]: Illegal ZERO value for" - " fabric_max_sectors\n", dev); - return -EINVAL; - } - if (fabric_max_sectors < DA_STATUS_MAX_SECTORS_MIN) { - pr_err("dev[%p]: Passed fabric_max_sectors: %u less than" - " DA_STATUS_MAX_SECTORS_MIN: %u\n", dev, fabric_max_sectors, - DA_STATUS_MAX_SECTORS_MIN); - return -EINVAL; - } - if (fabric_max_sectors > DA_STATUS_MAX_SECTORS_MAX) { - pr_err("dev[%p]: Passed fabric_max_sectors: %u" - " greater than DA_STATUS_MAX_SECTORS_MAX:" - " %u\n", dev, fabric_max_sectors, - DA_STATUS_MAX_SECTORS_MAX); - return -EINVAL; - } - /* - * Align max_sectors down to PAGE_SIZE to follow transport_allocate_data_tasks() - */ - if (!block_size) { - block_size = 512; - pr_warn("Defaulting to 512 for zero block_size\n"); - } - fabric_max_sectors = se_dev_align_max_sectors(fabric_max_sectors, - block_size); - - dev->dev_attrib.fabric_max_sectors = fabric_max_sectors; - pr_debug("dev[%p]: SE Device max_sectors changed to %u\n", - dev, fabric_max_sectors); - return 0; -} -EXPORT_SYMBOL(se_dev_set_fabric_max_sectors); - int se_dev_set_optimal_sectors(struct se_device *dev, u32 optimal_sectors) { if (dev->export_count) { @@ -1156,10 +1111,10 @@ int se_dev_set_optimal_sectors(struct se_device *dev, u32 optimal_sectors) dev, dev->export_count); return -EINVAL; } - if (optimal_sectors > dev->dev_attrib.fabric_max_sectors) { + if (optimal_sectors > dev->dev_attrib.hw_max_sectors) { pr_err("dev[%p]: Passed optimal_sectors %u cannot be" - " greater than fabric_max_sectors: %u\n", dev, - optimal_sectors, dev->dev_attrib.fabric_max_sectors); + " greater than hw_max_sectors: %u\n", dev, + optimal_sectors, dev->dev_attrib.hw_max_sectors); return -EINVAL; } @@ -1553,8 +1508,6 @@ struct se_device *target_alloc_device(struct se_hba *hba, const char *name) dev->dev_attrib.unmap_granularity_alignment = DA_UNMAP_GRANULARITY_ALIGNMENT_DEFAULT; dev->dev_attrib.max_write_same_len = DA_MAX_WRITE_SAME_LEN; - dev->dev_attrib.fabric_max_sectors = DA_FABRIC_MAX_SECTORS; - dev->dev_attrib.optimal_sectors = DA_FABRIC_MAX_SECTORS; xcopy_lun = &dev->xcopy_lun; xcopy_lun->lun_se_dev = dev; @@ -1595,6 +1548,7 @@ int target_configure_device(struct se_device *dev) dev->dev_attrib.hw_max_sectors = se_dev_align_max_sectors(dev->dev_attrib.hw_max_sectors, dev->dev_attrib.hw_block_size); + dev->dev_attrib.optimal_sectors = dev->dev_attrib.hw_max_sectors; dev->dev_index = scsi_get_new_index(SCSI_DEVICE_INDEX); dev->creation_time = get_jiffies_64(); diff --git a/drivers/target/target_core_file.c b/drivers/target/target_core_file.c index c2aea099ea4a..d836de200a03 100644 --- a/drivers/target/target_core_file.c +++ b/drivers/target/target_core_file.c @@ -621,7 +621,16 @@ fd_execute_rw(struct se_cmd *cmd, struct scatterlist *sgl, u32 sgl_nents, struct fd_prot fd_prot; sense_reason_t rc; int ret = 0; - + /* + * We are currently limited by the number of iovecs (2048) per + * single vfs_[writev,readv] call. + */ + if (cmd->data_length > FD_MAX_BYTES) { + pr_err("FILEIO: Not able to process I/O of %u bytes due to" + "FD_MAX_BYTES: %u iovec count limitiation\n", + cmd->data_length, FD_MAX_BYTES); + return TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE; + } /* * Call vectorized fileio functions to map struct scatterlist * physical memory addresses to struct iovec virtual memory. @@ -959,7 +968,6 @@ static struct configfs_attribute *fileio_backend_dev_attrs[] = { &fileio_dev_attrib_hw_block_size.attr, &fileio_dev_attrib_block_size.attr, &fileio_dev_attrib_hw_max_sectors.attr, - &fileio_dev_attrib_fabric_max_sectors.attr, &fileio_dev_attrib_optimal_sectors.attr, &fileio_dev_attrib_hw_queue_depth.attr, &fileio_dev_attrib_queue_depth.attr, diff --git a/drivers/target/target_core_iblock.c b/drivers/target/target_core_iblock.c index 3efff94fbd97..78346b850968 100644 --- a/drivers/target/target_core_iblock.c +++ b/drivers/target/target_core_iblock.c @@ -124,7 +124,7 @@ static int iblock_configure_device(struct se_device *dev) q = bdev_get_queue(bd); dev->dev_attrib.hw_block_size = bdev_logical_block_size(bd); - dev->dev_attrib.hw_max_sectors = UINT_MAX; + dev->dev_attrib.hw_max_sectors = queue_max_hw_sectors(q); dev->dev_attrib.hw_queue_depth = q->nr_requests; /* @@ -883,7 +883,6 @@ static struct configfs_attribute *iblock_backend_dev_attrs[] = { &iblock_dev_attrib_hw_block_size.attr, &iblock_dev_attrib_block_size.attr, &iblock_dev_attrib_hw_max_sectors.attr, - &iblock_dev_attrib_fabric_max_sectors.attr, &iblock_dev_attrib_optimal_sectors.attr, &iblock_dev_attrib_hw_queue_depth.attr, &iblock_dev_attrib_queue_depth.attr, diff --git a/drivers/target/target_core_pr.c b/drivers/target/target_core_pr.c index d56f2aaba9af..283cf786ef98 100644 --- a/drivers/target/target_core_pr.c +++ b/drivers/target/target_core_pr.c @@ -528,6 +528,18 @@ static int core_scsi3_pr_seq_non_holder( return 0; } + } else if (we && registered_nexus) { + /* + * Reads are allowed for Write Exclusive locks + * from all registrants. + */ + if (cmd->data_direction == DMA_FROM_DEVICE) { + pr_debug("Allowing READ CDB: 0x%02x for %s" + " reservation\n", cdb[0], + core_scsi3_pr_dump_type(pr_reg_type)); + + return 0; + } } pr_debug("%s Conflict for %sregistered nexus %s CDB: 0x%2x" " for %s reservation\n", transport_dump_cmd_direction(cmd), diff --git a/drivers/target/target_core_rd.c b/drivers/target/target_core_rd.c index 60ebd170a561..98e83ac5661b 100644 --- a/drivers/target/target_core_rd.c +++ b/drivers/target/target_core_rd.c @@ -657,7 +657,6 @@ static struct configfs_attribute *rd_mcp_backend_dev_attrs[] = { &rd_mcp_dev_attrib_hw_block_size.attr, &rd_mcp_dev_attrib_block_size.attr, &rd_mcp_dev_attrib_hw_max_sectors.attr, - &rd_mcp_dev_attrib_fabric_max_sectors.attr, &rd_mcp_dev_attrib_optimal_sectors.attr, &rd_mcp_dev_attrib_hw_queue_depth.attr, &rd_mcp_dev_attrib_queue_depth.attr, diff --git a/drivers/target/target_core_sbc.c b/drivers/target/target_core_sbc.c index 11bea1952435..cd4bed7b2757 100644 --- a/drivers/target/target_core_sbc.c +++ b/drivers/target/target_core_sbc.c @@ -953,21 +953,6 @@ sbc_parse_cdb(struct se_cmd *cmd, struct sbc_ops *ops) if (cmd->se_cmd_flags & SCF_SCSI_DATA_CDB) { unsigned long long end_lba; - - if (sectors > dev->dev_attrib.fabric_max_sectors) { - printk_ratelimited(KERN_ERR "SCSI OP %02xh with too" - " big sectors %u exceeds fabric_max_sectors:" - " %u\n", cdb[0], sectors, - dev->dev_attrib.fabric_max_sectors); - return TCM_INVALID_CDB_FIELD; - } - if (sectors > dev->dev_attrib.hw_max_sectors) { - printk_ratelimited(KERN_ERR "SCSI OP %02xh with too" - " big sectors %u exceeds backend hw_max_sectors:" - " %u\n", cdb[0], sectors, - dev->dev_attrib.hw_max_sectors); - return TCM_INVALID_CDB_FIELD; - } check_lba: end_lba = dev->transport->get_blocks(dev) + 1; if (cmd->t_task_lba + sectors > end_lba) { diff --git a/drivers/target/target_core_spc.c b/drivers/target/target_core_spc.c index 1307600fe726..4c71657da56a 100644 --- a/drivers/target/target_core_spc.c +++ b/drivers/target/target_core_spc.c @@ -505,7 +505,6 @@ static sense_reason_t spc_emulate_evpd_b0(struct se_cmd *cmd, unsigned char *buf) { struct se_device *dev = cmd->se_dev; - u32 max_sectors; int have_tp = 0; int opt, min; @@ -539,9 +538,7 @@ spc_emulate_evpd_b0(struct se_cmd *cmd, unsigned char *buf) /* * Set MAXIMUM TRANSFER LENGTH */ - max_sectors = min(dev->dev_attrib.fabric_max_sectors, - dev->dev_attrib.hw_max_sectors); - put_unaligned_be32(max_sectors, &buf[8]); + put_unaligned_be32(dev->dev_attrib.hw_max_sectors, &buf[8]); /* * Set OPTIMAL TRANSFER LENGTH diff --git a/drivers/target/target_core_user.c b/drivers/target/target_core_user.c index 8bfa61c9693d..1157b559683b 100644 --- a/drivers/target/target_core_user.c +++ b/drivers/target/target_core_user.c @@ -1118,7 +1118,6 @@ static struct configfs_attribute *tcmu_backend_dev_attrs[] = { &tcmu_dev_attrib_hw_block_size.attr, &tcmu_dev_attrib_block_size.attr, &tcmu_dev_attrib_hw_max_sectors.attr, - &tcmu_dev_attrib_fabric_max_sectors.attr, &tcmu_dev_attrib_optimal_sectors.attr, &tcmu_dev_attrib_hw_queue_depth.attr, &tcmu_dev_attrib_queue_depth.attr, diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index c1188ac053c9..2ccbc0788353 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -608,6 +608,7 @@ static int imx_thermal_suspend(struct device *dev) regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP); regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN); data->mode = THERMAL_DEVICE_DISABLED; + clk_disable_unprepare(data->thermal_clk); return 0; } @@ -617,6 +618,7 @@ static int imx_thermal_resume(struct device *dev) struct imx_thermal_data *data = dev_get_drvdata(dev); struct regmap *map = data->tempmon; + clk_prepare_enable(data->thermal_clk); /* Enabled thermal sensor after resume */ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN); regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP); diff --git a/drivers/thermal/int340x_thermal/acpi_thermal_rel.c b/drivers/thermal/int340x_thermal/acpi_thermal_rel.c index 231cabc16e16..2c2ec7666eb1 100644 --- a/drivers/thermal/int340x_thermal/acpi_thermal_rel.c +++ b/drivers/thermal/int340x_thermal/acpi_thermal_rel.c @@ -119,15 +119,11 @@ int acpi_parse_trt(acpi_handle handle, int *trt_count, struct trt **trtp, continue; result = acpi_bus_get_device(trt->source, &adev); - if (!result) - acpi_create_platform_device(adev); - else + if (result) pr_warn("Failed to get source ACPI device\n"); result = acpi_bus_get_device(trt->target, &adev); - if (!result) - acpi_create_platform_device(adev); - else + if (result) pr_warn("Failed to get target ACPI device\n"); } @@ -206,16 +202,12 @@ int acpi_parse_art(acpi_handle handle, int *art_count, struct art **artp, if (art->source) { result = acpi_bus_get_device(art->source, &adev); - if (!result) - acpi_create_platform_device(adev); - else + if (result) pr_warn("Failed to get source ACPI device\n"); } if (art->target) { result = acpi_bus_get_device(art->target, &adev); - if (!result) - acpi_create_platform_device(adev); - else + if (result) pr_warn("Failed to get source ACPI device\n"); } } diff --git a/drivers/thermal/int340x_thermal/processor_thermal_device.c b/drivers/thermal/int340x_thermal/processor_thermal_device.c index 31bb553aac26..0fe5dbbea968 100644 --- a/drivers/thermal/int340x_thermal/processor_thermal_device.c +++ b/drivers/thermal/int340x_thermal/processor_thermal_device.c @@ -130,6 +130,8 @@ static int proc_thermal_add(struct device *dev, int ret; adev = ACPI_COMPANION(dev); + if (!adev) + return -ENODEV; status = acpi_evaluate_object(adev->handle, "PPCC", NULL, &buf); if (ACPI_FAILURE(status)) diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c index e145b66df444..d717f3dab6f1 100644 --- a/drivers/thermal/of-thermal.c +++ b/drivers/thermal/of-thermal.c @@ -149,7 +149,7 @@ EXPORT_SYMBOL_GPL(of_thermal_is_trip_valid); * * Return: pointer to trip points table, NULL otherwise */ -const struct thermal_trip * const +const struct thermal_trip * of_thermal_get_trip_points(struct thermal_zone_device *tz) { struct __thermal_zone *data = tz->devdata; diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c index 8803e693fe68..2580a4872f90 100644 --- a/drivers/thermal/rcar_thermal.c +++ b/drivers/thermal/rcar_thermal.c @@ -63,7 +63,7 @@ struct rcar_thermal_priv { struct mutex lock; struct list_head list; int id; - int ctemp; + u32 ctemp; }; #define rcar_thermal_for_each_priv(pos, common) \ @@ -145,7 +145,7 @@ static int rcar_thermal_update_temp(struct rcar_thermal_priv *priv) { struct device *dev = rcar_priv_to_dev(priv); int i; - int ctemp, old, new; + u32 ctemp, old, new; int ret = -EINVAL; mutex_lock(&priv->lock); @@ -372,6 +372,7 @@ static int rcar_thermal_probe(struct platform_device *pdev) int i; int ret = -ENODEV; int idle = IDLE_INTERVAL; + u32 enr_bits = 0; common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); if (!common) @@ -390,7 +391,7 @@ static int rcar_thermal_probe(struct platform_device *pdev) /* * platform has IRQ support. - * Then, drier use common register + * Then, driver uses common registers */ ret = devm_request_irq(dev, irq->start, rcar_thermal_irq, 0, @@ -408,9 +409,6 @@ static int rcar_thermal_probe(struct platform_device *pdev) if (IS_ERR(common->base)) return PTR_ERR(common->base); - /* enable temperature comparation */ - rcar_thermal_common_write(common, ENR, 0x00030303); - idle = 0; /* polling delay is not needed */ } @@ -452,8 +450,15 @@ static int rcar_thermal_probe(struct platform_device *pdev) rcar_thermal_irq_enable(priv); list_move_tail(&priv->list, &common->head); + + /* update ENR bits */ + enr_bits |= 3 << (i * 8); } + /* enable temperature comparation */ + if (irq) + rcar_thermal_common_write(common, ENR, enr_bits); + platform_set_drvdata(pdev, common); dev_info(dev, "%d sensor probed\n", i); diff --git a/drivers/thermal/thermal_core.h b/drivers/thermal/thermal_core.h index 9083e7520623..0531c752fbbb 100644 --- a/drivers/thermal/thermal_core.h +++ b/drivers/thermal/thermal_core.h @@ -91,7 +91,7 @@ int of_parse_thermal_zones(void); void of_thermal_destroy_zones(void); int of_thermal_get_ntrips(struct thermal_zone_device *); bool of_thermal_is_trip_valid(struct thermal_zone_device *, int); -const struct thermal_trip * const +const struct thermal_trip * of_thermal_get_trip_points(struct thermal_zone_device *); #else static inline int of_parse_thermal_zones(void) { return 0; } @@ -105,7 +105,7 @@ static inline bool of_thermal_is_trip_valid(struct thermal_zone_device *tz, { return 0; } -static inline const struct thermal_trip * const +static inline const struct thermal_trip * of_thermal_get_trip_points(struct thermal_zone_device *tz) { return NULL; diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c index d2b496750d59..4ddfa60c9222 100644 --- a/drivers/tty/n_tty.c +++ b/drivers/tty/n_tty.c @@ -2399,17 +2399,12 @@ static unsigned int n_tty_poll(struct tty_struct *tty, struct file *file, poll_wait(file, &tty->read_wait, wait); poll_wait(file, &tty->write_wait, wait); - if (test_bit(TTY_OTHER_CLOSED, &tty->flags)) - mask |= POLLHUP; if (input_available_p(tty, 1)) mask |= POLLIN | POLLRDNORM; - else if (mask & POLLHUP) { - tty_flush_to_ldisc(tty); - if (input_available_p(tty, 1)) - mask |= POLLIN | POLLRDNORM; - } if (tty->packet && tty->link->ctrl_status) mask |= POLLPRI | POLLIN | POLLRDNORM; + if (test_bit(TTY_OTHER_CLOSED, &tty->flags)) + mask |= POLLHUP; if (tty_hung_up_p(file)) mask |= POLLHUP; if (!(mask & (POLLHUP | POLLIN | POLLRDNORM))) { diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 31feeb2d0a66..d1f8dc6aabcb 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -1815,7 +1815,7 @@ pci_wch_ch353_setup(struct serial_private *priv, } static int -pci_wch_ch382_setup(struct serial_private *priv, +pci_wch_ch38x_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { @@ -1880,6 +1880,7 @@ pci_wch_ch382_setup(struct serial_private *priv, #define PCIE_VENDOR_ID_WCH 0x1c00 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 +#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 @@ -2571,13 +2572,21 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { .subdevice = PCI_ANY_ID, .setup = pci_wch_ch353_setup, }, - /* WCH CH382 2S1P card (16750 clone) */ + /* WCH CH382 2S1P card (16850 clone) */ { .vendor = PCIE_VENDOR_ID_WCH, .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, - .setup = pci_wch_ch382_setup, + .setup = pci_wch_ch38x_setup, + }, + /* WCH CH384 4S card (16850 clone) */ + { + .vendor = PCIE_VENDOR_ID_WCH, + .device = PCIE_DEVICE_ID_WCH_CH384_4S, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .setup = pci_wch_ch38x_setup, }, /* * ASIX devices with FIFO bug @@ -2876,6 +2885,7 @@ enum pci_board_num_t { pbn_fintek_4, pbn_fintek_8, pbn_fintek_12, + pbn_wch384_4, }; /* @@ -3675,6 +3685,14 @@ static struct pciserial_board pci_boards[] = { .base_baud = 115200, .first_offset = 0x40, }, + + [pbn_wch384_4] = { + .flags = FL_BASE0, + .num_ports = 4, + .base_baud = 115200, + .uart_offset = 8, + .first_offset = 0xC0, + }, }; static const struct pci_device_id blacklist[] = { @@ -3687,6 +3705,7 @@ static const struct pci_device_id blacklist[] = { { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ + { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */ }; /* @@ -5400,6 +5419,10 @@ static struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b0_bt_2_115200 }, + { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, pbn_wch384_4 }, + /* * Commtech, Inc. Fastcom adapters */ diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 19273e31d224..107e80722575 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -1757,32 +1757,43 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { #endif #if defined(CONFIG_ARCH_EXYNOS) +#define EXYNOS_COMMON_SERIAL_DRV_DATA \ + .info = &(struct s3c24xx_uart_info) { \ + .name = "Samsung Exynos UART", \ + .type = PORT_S3C6400, \ + .has_divslot = 1, \ + .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ + .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ + .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ + .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ + .def_clk_sel = S3C2410_UCON_CLKSEL0, \ + .num_clks = 1, \ + .clksel_mask = 0, \ + .clksel_shift = 0, \ + }, \ + .def_cfg = &(struct s3c2410_uartcfg) { \ + .ucon = S5PV210_UCON_DEFAULT, \ + .ufcon = S5PV210_UFCON_DEFAULT, \ + .has_fracval = 1, \ + } \ + static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { - .info = &(struct s3c24xx_uart_info) { - .name = "Samsung Exynos4 UART", - .type = PORT_S3C6400, - .has_divslot = 1, - .rx_fifomask = S5PV210_UFSTAT_RXMASK, - .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, - .rx_fifofull = S5PV210_UFSTAT_RXFULL, - .tx_fifofull = S5PV210_UFSTAT_TXFULL, - .tx_fifomask = S5PV210_UFSTAT_TXMASK, - .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, - .def_clk_sel = S3C2410_UCON_CLKSEL0, - .num_clks = 1, - .clksel_mask = 0, - .clksel_shift = 0, - }, - .def_cfg = &(struct s3c2410_uartcfg) { - .ucon = S5PV210_UCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, - .has_fracval = 1, - }, + EXYNOS_COMMON_SERIAL_DRV_DATA, .fifosize = { 256, 64, 16, 16 }, }; + +static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { + EXYNOS_COMMON_SERIAL_DRV_DATA, + .fifosize = { 64, 256, 16, 256 }, +}; + #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) +#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) #else #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL +#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL #endif static struct platform_device_id s3c24xx_serial_driver_ids[] = { @@ -1804,6 +1815,9 @@ static struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "exynos4210-uart", .driver_data = EXYNOS4210_SERIAL_DRV_DATA, + }, { + .name = "exynos5433-uart", + .driver_data = EXYNOS5433_SERIAL_DRV_DATA, }, { }, }; @@ -1823,6 +1837,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = (void *)S5PV210_SERIAL_DRV_DATA }, { .compatible = "samsung,exynos4210-uart", .data = (void *)EXYNOS4210_SERIAL_DRV_DATA }, + { .compatible = "samsung,exynos5433-uart", + .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c index 57ca61b14670..984605bb5bf1 100644 --- a/drivers/tty/serial/serial_core.c +++ b/drivers/tty/serial/serial_core.c @@ -2164,7 +2164,9 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port) break; } - dev_info(port->dev, "%s%d at %s (irq = %d, base_baud = %d) is a %s\n", + printk(KERN_INFO "%s%s%s%d at %s (irq = %d, base_baud = %d) is a %s\n", + port->dev ? dev_name(port->dev) : "", + port->dev ? ": " : "", drv->dev_name, drv->tty_driver->name_base + port->line, address, port->irq, port->uartclk / 16, uart_type(port)); diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c index 4f35b43e2475..51f066aa375e 100644 --- a/drivers/tty/tty_io.c +++ b/drivers/tty/tty_io.c @@ -1464,6 +1464,9 @@ static int tty_reopen(struct tty_struct *tty) driver->subtype == PTY_TYPE_MASTER) return -EIO; + if (test_bit(TTY_EXCLUSIVE, &tty->flags) && !capable(CAP_SYS_ADMIN)) + return -EBUSY; + tty->count++; WARN_ON(!tty->ldisc); @@ -2106,10 +2109,6 @@ retry_open: retval = -ENODEV; filp->f_flags = saved_flags; - if (!retval && test_bit(TTY_EXCLUSIVE, &tty->flags) && - !capable(CAP_SYS_ADMIN)) - retval = -EBUSY; - if (retval) { #ifdef TTY_DEBUG_HANGUP printk(KERN_DEBUG "%s: error %d in opening %s...\n", __func__, diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 5b9825a4538a..a57dc8866fc5 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -669,7 +669,6 @@ static int ci_hdrc_probe(struct platform_device *pdev) if (!ci) return -ENOMEM; - platform_set_drvdata(pdev, ci); ci->dev = dev; ci->platdata = dev_get_platdata(dev); ci->imx28_write_fix = !!(ci->platdata->flags & @@ -783,6 +782,7 @@ static int ci_hdrc_probe(struct platform_device *pdev) } } + platform_set_drvdata(pdev, ci); ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, ci); if (ret) diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c index c1694cff1eaf..48731d0bab35 100644 --- a/drivers/usb/chipidea/host.c +++ b/drivers/usb/chipidea/host.c @@ -91,6 +91,7 @@ static int host_start(struct ci_hdrc *ci) if (!hcd) return -ENOMEM; + dev_set_drvdata(ci->dev, ci); hcd->rsrc_start = ci->hw_bank.phys; hcd->rsrc_len = ci->hw_bank.size; hcd->regs = ci->hw_bank.abs; diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c index 200168ec2d75..79242008085b 100644 --- a/drivers/usb/dwc2/gadget.c +++ b/drivers/usb/dwc2/gadget.c @@ -2567,7 +2567,7 @@ error: * s3c_hsotg_ep_disable - disable given endpoint * @ep: The endpoint to disable. */ -static int s3c_hsotg_ep_disable(struct usb_ep *ep) +static int s3c_hsotg_ep_disable_force(struct usb_ep *ep, bool force) { struct s3c_hsotg_ep *hs_ep = our_ep(ep); struct dwc2_hsotg *hsotg = hs_ep->parent; @@ -2588,7 +2588,7 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep) spin_lock_irqsave(&hsotg->lock, flags); /* terminate all requests with shutdown */ - kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false); + kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, force); hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); hs_ep->fifo_index = 0; @@ -2609,6 +2609,10 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep) return 0; } +static int s3c_hsotg_ep_disable(struct usb_ep *ep) +{ + return s3c_hsotg_ep_disable_force(ep, false); +} /** * on_list - check request is on the given endpoint * @ep: The endpoint to check. @@ -2924,7 +2928,7 @@ static int s3c_hsotg_udc_stop(struct usb_gadget *gadget) /* all endpoints should be shutdown */ for (ep = 1; ep < hsotg->num_of_eps; ep++) - s3c_hsotg_ep_disable(&hsotg->eps[ep].ep); + s3c_hsotg_ep_disable_force(&hsotg->eps[ep].ep, true); spin_lock_irqsave(&hsotg->lock, flags); diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index 7c4faf738747..b642a2f998f9 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -33,6 +33,8 @@ #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e #define PCI_DEVICE_ID_INTEL_BSW 0x22B7 +#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 +#define PCI_DEVICE_ID_INTEL_SPTH 0xa130 struct dwc3_pci { struct device *dev; @@ -219,6 +221,8 @@ static const struct pci_device_id dwc3_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), }, { } /* Terminating Entry */ }; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index f03b136ecfce..8f65ab3a3b92 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -882,8 +882,7 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) if (i == (request->num_mapped_sgs - 1) || sg_is_last(s)) { - if (list_is_last(&req->list, - &dep->request_list)) + if (list_empty(&dep->request_list)) last_one = true; chain = false; } @@ -901,6 +900,9 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) if (last_one) break; } + + if (last_one) + break; } else { dma = req->request.dma; length = req->request.length; diff --git a/drivers/usb/gadget/function/f_hid.c b/drivers/usb/gadget/function/f_hid.c index 6e04e302dc3a..a1bc3e3a0b09 100644 --- a/drivers/usb/gadget/function/f_hid.c +++ b/drivers/usb/gadget/function/f_hid.c @@ -399,8 +399,9 @@ static int hidg_setup(struct usb_function *f, value = __le16_to_cpu(ctrl->wValue); length = __le16_to_cpu(ctrl->wLength); - VDBG(cdev, "hid_setup crtl_request : bRequestType:0x%x bRequest:0x%x " - "Value:0x%x\n", ctrl->bRequestType, ctrl->bRequest, value); + VDBG(cdev, + "%s crtl_request : bRequestType:0x%x bRequest:0x%x Value:0x%x\n", + __func__, ctrl->bRequestType, ctrl->bRequest, value); switch ((ctrl->bRequestType << 8) | ctrl->bRequest) { case ((USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8 diff --git a/drivers/usb/gadget/function/f_midi.c b/drivers/usb/gadget/function/f_midi.c index a90440300735..259b656c0b3e 100644 --- a/drivers/usb/gadget/function/f_midi.c +++ b/drivers/usb/gadget/function/f_midi.c @@ -520,7 +520,7 @@ static void f_midi_transmit(struct f_midi *midi, struct usb_request *req) req = midi_alloc_ep_req(ep, midi->buflen); if (!req) { - ERROR(midi, "gmidi_transmit: alloc_ep_request failed\n"); + ERROR(midi, "%s: alloc_ep_request failed\n", __func__); return; } req->length = 0; diff --git a/drivers/usb/gadget/function/f_uac1.c b/drivers/usb/gadget/function/f_uac1.c index f7b203293205..e9715845f82e 100644 --- a/drivers/usb/gadget/function/f_uac1.c +++ b/drivers/usb/gadget/function/f_uac1.c @@ -897,7 +897,6 @@ static void f_audio_free_inst(struct usb_function_instance *f) struct f_uac1_opts *opts; opts = container_of(f, struct f_uac1_opts, func_inst); - gaudio_cleanup(opts->card); if (opts->fn_play_alloc) kfree(opts->fn_play); if (opts->fn_cap_alloc) @@ -935,6 +934,7 @@ static void f_audio_free(struct usb_function *f) struct f_audio *audio = func_to_audio(f); struct f_uac1_opts *opts; + gaudio_cleanup(&audio->card); opts = container_of(f->fi, struct f_uac1_opts, func_inst); kfree(audio); mutex_lock(&opts->lock); diff --git a/drivers/usb/gadget/legacy/inode.c b/drivers/usb/gadget/legacy/inode.c index c744e4975d74..db49ec4c748e 100644 --- a/drivers/usb/gadget/legacy/inode.c +++ b/drivers/usb/gadget/legacy/inode.c @@ -441,6 +441,7 @@ ep_write (struct file *fd, const char __user *buf, size_t len, loff_t *ptr) kbuf = memdup_user(buf, len); if (IS_ERR(kbuf)) { value = PTR_ERR(kbuf); + kbuf = NULL; goto free1; } @@ -449,6 +450,7 @@ ep_write (struct file *fd, const char __user *buf, size_t len, loff_t *ptr) data->name, len, (int) value); free1: mutex_unlock(&data->lock); + kfree (kbuf); return value; } diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c b/drivers/usb/gadget/udc/atmel_usba_udc.c index ce882371786b..9f93bed42052 100644 --- a/drivers/usb/gadget/udc/atmel_usba_udc.c +++ b/drivers/usb/gadget/udc/atmel_usba_udc.c @@ -716,10 +716,10 @@ static int queue_dma(struct usba_udc *udc, struct usba_ep *ep, req->using_dma = 1; req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length) | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE - | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE; + | USBA_DMA_END_BUF_EN; - if (ep->is_in) - req->ctrl |= USBA_DMA_END_BUF_EN; + if (!ep->is_in) + req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE; /* * Add this request to the queue and submit for DMA if @@ -828,7 +828,7 @@ static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct usba_ep *ep = to_usba_ep(_ep); struct usba_udc *udc = ep->udc; - struct usba_request *req = to_usba_req(_req); + struct usba_request *req; unsigned long flags; u32 status; @@ -837,6 +837,16 @@ static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&udc->lock, flags); + list_for_each_entry(req, &ep->queue, queue) { + if (&req->req == _req) + break; + } + + if (&req->req != _req) { + spin_unlock_irqrestore(&udc->lock, flags); + return -EINVAL; + } + if (req->using_dma) { /* * If this request is currently being transferred, @@ -1563,7 +1573,6 @@ static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep) if ((epstatus & epctrl) & USBA_RX_BK_RDY) { DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name); receive_data(ep); - usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); } } diff --git a/drivers/usb/gadget/udc/bdc/bdc_ep.c b/drivers/usb/gadget/udc/bdc/bdc_ep.c index ff67ceac77c4..d4fe8d769bd6 100644 --- a/drivers/usb/gadget/udc/bdc/bdc_ep.c +++ b/drivers/usb/gadget/udc/bdc/bdc_ep.c @@ -718,10 +718,11 @@ static int ep_queue(struct bdc_ep *ep, struct bdc_req *req) struct bdc *bdc; int ret = 0; - bdc = ep->bdc; if (!req || !ep || !ep->usb_ep.desc) return -EINVAL; + bdc = ep->bdc; + req->usb_req.actual = 0; req->usb_req.status = -EINPROGRESS; req->epnum = ep->ep_num; diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c index e113fd73aeae..f9a332775c47 100644 --- a/drivers/usb/host/ehci-sched.c +++ b/drivers/usb/host/ehci-sched.c @@ -1581,6 +1581,10 @@ iso_stream_schedule ( else next = (now + 2 + 7) & ~0x07; /* full frame cache */ + /* If needed, initialize last_iso_frame so that this URB will be seen */ + if (ehci->isoc_count == 0) + ehci->last_iso_frame = now >> 3; + /* * Use ehci->last_iso_frame as the base. There can't be any * TDs scheduled for earlier than that. @@ -1600,11 +1604,11 @@ iso_stream_schedule ( */ now2 = (now - base) & (mod - 1); - /* Is the schedule already full? */ + /* Is the schedule about to wrap around? */ if (unlikely(!empty && start < period)) { - ehci_dbg(ehci, "iso sched full %p (%u-%u < %u mod %u)\n", + ehci_dbg(ehci, "request %p would overflow (%u-%u < %u mod %u)\n", urb, stream->next_uframe, base, period, mod); - status = -ENOSPC; + status = -EFBIG; goto fail; } @@ -1671,10 +1675,6 @@ iso_stream_schedule ( urb->start_frame = start & (mod - 1); if (!stream->highspeed) urb->start_frame >>= 3; - - /* Make sure scan_isoc() sees these */ - if (ehci->isoc_count == 0) - ehci->last_iso_frame = now >> 3; return status; fail: diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 19a9af1b4d74..ff9af29b4e9f 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -451,7 +451,7 @@ static int tegra_ehci_probe(struct platform_device *pdev) u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0); if (IS_ERR(u_phy)) { - err = PTR_ERR(u_phy); + err = -EPROBE_DEFER; goto cleanup_clk_en; } hcd->usb_phy = u_phy; diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c index dd483c13565b..ce636466edb7 100644 --- a/drivers/usb/host/pci-quirks.c +++ b/drivers/usb/host/pci-quirks.c @@ -567,7 +567,8 @@ static void quirk_usb_handoff_ohci(struct pci_dev *pdev) { void __iomem *base; u32 control; - u32 fminterval; + u32 fminterval = 0; + bool no_fminterval = false; int cnt; if (!mmio_resource_enabled(pdev, 0)) @@ -577,6 +578,13 @@ static void quirk_usb_handoff_ohci(struct pci_dev *pdev) if (base == NULL) return; + /* + * ULi M5237 OHCI controller locks the whole system when accessing + * the OHCI_FMINTERVAL offset. + */ + if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237) + no_fminterval = true; + control = readl(base + OHCI_CONTROL); /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ @@ -615,7 +623,9 @@ static void quirk_usb_handoff_ohci(struct pci_dev *pdev) } /* software reset of the controller, preserving HcFmInterval */ - fminterval = readl(base + OHCI_FMINTERVAL); + if (!no_fminterval) + fminterval = readl(base + OHCI_FMINTERVAL); + writel(OHCI_HCR, base + OHCI_CMDSTATUS); /* reset requires max 10 us delay */ @@ -624,7 +634,9 @@ static void quirk_usb_handoff_ohci(struct pci_dev *pdev) break; udelay(1); } - writel(fminterval, base + OHCI_FMINTERVAL); + + if (!no_fminterval) + writel(fminterval, base + OHCI_FMINTERVAL); /* Now the controller is safely in SUSPEND and nothing can wake it up */ iounmap(base); diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 142b601f9563..7f76c8a12f89 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -82,6 +82,8 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) "must be suspended extra slowly", pdev->revision); } + if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) + xhci->quirks |= XHCI_BROKEN_STREAMS; /* Fresco Logic confirms: all revisions of this chip do not * support MSI, even though some of them claim to in their PCI * capabilities. diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 01fcbb5eb06e..c50d8d202618 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -3803,6 +3803,15 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, return -EINVAL; } + if (setup == SETUP_CONTEXT_ONLY) { + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); + if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == + SLOT_STATE_DEFAULT) { + xhci_dbg(xhci, "Slot already in default state\n"); + return 0; + } + } + command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); if (!command) return -ENOMEM; diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig index 9d68372dd9aa..b005010240e5 100644 --- a/drivers/usb/musb/Kconfig +++ b/drivers/usb/musb/Kconfig @@ -72,6 +72,8 @@ config USB_MUSB_DA8XX config USB_MUSB_TUSB6010 tristate "TUSB6010" + depends on ARCH_OMAP2PLUS || COMPILE_TEST + depends on NOP_USB_XCEIV = USB_MUSB_HDRC # both built-in or both modules config USB_MUSB_OMAP2PLUS tristate "OMAP2430 and onwards" @@ -85,6 +87,7 @@ config USB_MUSB_AM35X config USB_MUSB_DSPS tristate "TI DSPS platforms" select USB_MUSB_AM335X_CHILD + depends on ARCH_OMAP2PLUS || COMPILE_TEST depends on OF_IRQ config USB_MUSB_BLACKFIN @@ -93,6 +96,7 @@ config USB_MUSB_BLACKFIN config USB_MUSB_UX500 tristate "Ux500 platforms" + depends on ARCH_U8500 || COMPILE_TEST config USB_MUSB_JZ4740 tristate "JZ4740" diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c index a441a2de8619..178250145613 100644 --- a/drivers/usb/musb/blackfin.c +++ b/drivers/usb/musb/blackfin.c @@ -63,7 +63,7 @@ static void bfin_writew(void __iomem *addr, unsigned offset, u16 data) bfin_write16(addr + offset, data); } -static void binf_writel(void __iomem *addr, unsigned offset, u32 data) +static void bfin_writel(void __iomem *addr, unsigned offset, u32 data) { bfin_write16(addr + offset, (u16)data); } diff --git a/drivers/usb/musb/musb_cppi41.c b/drivers/usb/musb/musb_cppi41.c index f64fd964dc6d..c39a16ad7832 100644 --- a/drivers/usb/musb/musb_cppi41.c +++ b/drivers/usb/musb/musb_cppi41.c @@ -628,9 +628,9 @@ static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller) ret = of_property_read_string_index(np, "dma-names", i, &str); if (ret) goto err; - if (!strncmp(str, "tx", 2)) + if (strstarts(str, "tx")) is_tx = 1; - else if (!strncmp(str, "rx", 2)) + else if (strstarts(str, "rx")) is_tx = 0; else { dev_err(dev, "Wrong dmatype %s\n", str); diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c index ad3701a97389..48131aa8472c 100644 --- a/drivers/usb/musb/musb_debugfs.c +++ b/drivers/usb/musb/musb_debugfs.c @@ -59,20 +59,12 @@ static const struct musb_register_map musb_regmap[] = { { "RxMaxPp", MUSB_RXMAXP, 16 }, { "RxCSR", MUSB_RXCSR, 16 }, { "RxCount", MUSB_RXCOUNT, 16 }, - { "ConfigData", MUSB_CONFIGDATA,8 }, { "IntrRxE", MUSB_INTRRXE, 16 }, { "IntrTxE", MUSB_INTRTXE, 16 }, { "IntrUsbE", MUSB_INTRUSBE, 8 }, { "DevCtl", MUSB_DEVCTL, 8 }, - { "BabbleCtl", MUSB_BABBLE_CTL,8 }, - { "TxFIFOsz", MUSB_TXFIFOSZ, 8 }, - { "RxFIFOsz", MUSB_RXFIFOSZ, 8 }, - { "TxFIFOadd", MUSB_TXFIFOADD, 16 }, - { "RxFIFOadd", MUSB_RXFIFOADD, 16 }, { "VControl", 0x68, 32 }, { "HWVers", 0x69, 16 }, - { "EPInfo", MUSB_EPINFO, 8 }, - { "RAMInfo", MUSB_RAMINFO, 8 }, { "LinkInfo", MUSB_LINKINFO, 8 }, { "VPLen", MUSB_VPLEN, 8 }, { "HS_EOF1", MUSB_HS_EOF1, 8 }, @@ -103,6 +95,16 @@ static const struct musb_register_map musb_regmap[] = { { "DMA_CNTLch7", 0x274, 16 }, { "DMA_ADDRch7", 0x278, 32 }, { "DMA_COUNTch7", 0x27C, 32 }, +#ifndef CONFIG_BLACKFIN + { "ConfigData", MUSB_CONFIGDATA,8 }, + { "BabbleCtl", MUSB_BABBLE_CTL,8 }, + { "TxFIFOsz", MUSB_TXFIFOSZ, 8 }, + { "RxFIFOsz", MUSB_RXFIFOSZ, 8 }, + { "TxFIFOadd", MUSB_TXFIFOADD, 16 }, + { "RxFIFOadd", MUSB_RXFIFOADD, 16 }, + { "EPInfo", MUSB_EPINFO, 8 }, + { "RAMInfo", MUSB_RAMINFO, 8 }, +#endif { } /* Terminating Entry */ }; @@ -197,30 +199,30 @@ static ssize_t musb_test_mode_write(struct file *file, if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) return -EFAULT; - if (!strncmp(buf, "force host", 9)) + if (strstarts(buf, "force host")) test = MUSB_TEST_FORCE_HOST; - if (!strncmp(buf, "fifo access", 11)) + if (strstarts(buf, "fifo access")) test = MUSB_TEST_FIFO_ACCESS; - if (!strncmp(buf, "force full-speed", 15)) + if (strstarts(buf, "force full-speed")) test = MUSB_TEST_FORCE_FS; - if (!strncmp(buf, "force high-speed", 15)) + if (strstarts(buf, "force high-speed")) test = MUSB_TEST_FORCE_HS; - if (!strncmp(buf, "test packet", 10)) { + if (strstarts(buf, "test packet")) { test = MUSB_TEST_PACKET; musb_load_testpacket(musb); } - if (!strncmp(buf, "test K", 6)) + if (strstarts(buf, "test K")) test = MUSB_TEST_K; - if (!strncmp(buf, "test J", 6)) + if (strstarts(buf, "test J")) test = MUSB_TEST_J; - if (!strncmp(buf, "test SE0 NAK", 12)) + if (strstarts(buf, "test SE0 NAK")) test = MUSB_TEST_SE0_NAK; musb_writeb(musb->mregs, MUSB_TESTMODE, test); diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c index 23d474d3d7f4..883a9adfdfff 100644 --- a/drivers/usb/musb/musb_host.c +++ b/drivers/usb/musb/musb_host.c @@ -2663,7 +2663,6 @@ void musb_host_cleanup(struct musb *musb) if (musb->port_mode == MUSB_PORT_MODE_GADGET) return; usb_remove_hcd(musb->hcd); - musb->hcd = NULL; } void musb_host_free(struct musb *musb) diff --git a/drivers/usb/phy/phy-mv-usb.c b/drivers/usb/phy/phy-mv-usb.c index 699e38c73d82..697a741a0cb1 100644 --- a/drivers/usb/phy/phy-mv-usb.c +++ b/drivers/usb/phy/phy-mv-usb.c @@ -338,7 +338,6 @@ static void mv_otg_update_inputs(struct mv_otg *mvotg) static void mv_otg_update_state(struct mv_otg *mvotg) { struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl; - struct usb_phy *phy = &mvotg->phy; int old_state = mvotg->phy.otg->state; switch (old_state) { @@ -858,10 +857,10 @@ static int mv_otg_suspend(struct platform_device *pdev, pm_message_t state) { struct mv_otg *mvotg = platform_get_drvdata(pdev); - if (mvotg->phy.state != OTG_STATE_B_IDLE) { + if (mvotg->phy.otg->state != OTG_STATE_B_IDLE) { dev_info(&pdev->dev, "OTG state is not B_IDLE, it is %d!\n", - mvotg->phy.state); + mvotg->phy.otg->state); return -EAGAIN; } diff --git a/drivers/usb/phy/phy.c b/drivers/usb/phy/phy.c index b4066a001ba0..ccfdfb24b240 100644 --- a/drivers/usb/phy/phy.c +++ b/drivers/usb/phy/phy.c @@ -34,7 +34,7 @@ static struct usb_phy *__usb_find_phy(struct list_head *list, return phy; } - return ERR_PTR(-ENODEV); + return ERR_PTR(-EPROBE_DEFER); } static struct usb_phy *__usb_find_phy_dev(struct device *dev, @@ -59,6 +59,9 @@ static struct usb_phy *__of_usb_find_phy(struct device_node *node) { struct usb_phy *phy; + if (!of_device_is_available(node)) + return ERR_PTR(-ENODEV); + list_for_each_entry(phy, &phy_list, head) { if (node != phy->dev->of_node) continue; @@ -66,7 +69,7 @@ static struct usb_phy *__of_usb_find_phy(struct device_node *node) return phy; } - return ERR_PTR(-ENODEV); + return ERR_PTR(-EPROBE_DEFER); } static void devm_usb_phy_release(struct device *dev, void *res) @@ -190,10 +193,13 @@ struct usb_phy *devm_usb_get_phy_by_phandle(struct device *dev, spin_lock_irqsave(&phy_lock, flags); phy = __of_usb_find_phy(node); - if (IS_ERR(phy) || !try_module_get(phy->dev->driver->owner)) { - if (!IS_ERR(phy)) - phy = ERR_PTR(-EPROBE_DEFER); + if (IS_ERR(phy)) { + devres_free(ptr); + goto err1; + } + if (!try_module_get(phy->dev->driver->owner)) { + phy = ERR_PTR(-ENODEV); devres_free(ptr); goto err1; } diff --git a/drivers/usb/serial/console.c b/drivers/usb/serial/console.c index 8d7fc48b1f30..29fa1c3d0089 100644 --- a/drivers/usb/serial/console.c +++ b/drivers/usb/serial/console.c @@ -46,6 +46,8 @@ static struct console usbcons; * ------------------------------------------------------------ */ +static const struct tty_operations usb_console_fake_tty_ops = { +}; /* * The parsing of the command line works exactly like the @@ -137,13 +139,17 @@ static int usb_console_setup(struct console *co, char *options) goto reset_open_count; } kref_init(&tty->kref); - tty_port_tty_set(&port->port, tty); tty->driver = usb_serial_tty_driver; tty->index = co->index; + init_ldsem(&tty->ldisc_sem); + INIT_LIST_HEAD(&tty->tty_files); + kref_get(&tty->driver->kref); + tty->ops = &usb_console_fake_tty_ops; if (tty_init_termios(tty)) { retval = -ENOMEM; - goto free_tty; + goto put_tty; } + tty_port_tty_set(&port->port, tty); } /* only call the device specific open if this @@ -161,7 +167,7 @@ static int usb_console_setup(struct console *co, char *options) serial->type->set_termios(tty, port, &dummy); tty_port_tty_set(&port->port, NULL); - kfree(tty); + tty_kref_put(tty); } set_bit(ASYNCB_INITIALIZED, &port->port.flags); } @@ -177,8 +183,8 @@ static int usb_console_setup(struct console *co, char *options) fail: tty_port_tty_set(&port->port, NULL); - free_tty: - kfree(tty); + put_tty: + tty_kref_put(tty); reset_open_count: port->port.count = 0; usb_autopm_put_interface(serial->interface); diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c index 6c4eb3cf5efd..f4c56fc1a9f6 100644 --- a/drivers/usb/serial/cp210x.c +++ b/drivers/usb/serial/cp210x.c @@ -120,10 +120,12 @@ static const struct usb_device_id id_table[] = { { USB_DEVICE(0x10C4, 0x85F8) }, /* Virtenio Preon32 */ { USB_DEVICE(0x10C4, 0x8664) }, /* AC-Services CAN-IF */ { USB_DEVICE(0x10C4, 0x8665) }, /* AC-Services OBD-IF */ - { USB_DEVICE(0x10C4, 0x8875) }, /* CEL MeshConnect USB Stick */ + { USB_DEVICE(0x10C4, 0x8856) }, /* CEL EM357 ZigBee USB Stick - LR */ + { USB_DEVICE(0x10C4, 0x8857) }, /* CEL EM357 ZigBee USB Stick */ { USB_DEVICE(0x10C4, 0x88A4) }, /* MMB Networks ZigBee USB Device */ { USB_DEVICE(0x10C4, 0x88A5) }, /* Planet Innovation Ingeni ZigBee USB Device */ { USB_DEVICE(0x10C4, 0x8946) }, /* Ketra N1 Wireless Interface */ + { USB_DEVICE(0x10C4, 0x8977) }, /* CEL MeshWorks DevKit Device */ { USB_DEVICE(0x10C4, 0xEA60) }, /* Silicon Labs factory default */ { USB_DEVICE(0x10C4, 0xEA61) }, /* Silicon Labs factory default */ { USB_DEVICE(0x10C4, 0xEA70) }, /* Silicon Labs factory default */ diff --git a/drivers/usb/serial/generic.c b/drivers/usb/serial/generic.c index 1bd192290b08..ccf1df7c4b80 100644 --- a/drivers/usb/serial/generic.c +++ b/drivers/usb/serial/generic.c @@ -286,7 +286,7 @@ static int usb_serial_generic_submit_read_urb(struct usb_serial_port *port, res = usb_submit_urb(port->read_urbs[index], mem_flags); if (res) { - if (res != -EPERM) { + if (res != -EPERM && res != -ENODEV) { dev_err(&port->dev, "%s - usb_submit_urb failed: %d\n", __func__, res); @@ -373,7 +373,7 @@ void usb_serial_generic_read_bulk_callback(struct urb *urb) __func__, urb->status); return; default: - dev_err(&port->dev, "%s - nonzero urb status: %d\n", + dev_dbg(&port->dev, "%s - nonzero urb status: %d\n", __func__, urb->status); goto resubmit; } diff --git a/drivers/usb/serial/keyspan.c b/drivers/usb/serial/keyspan.c index 077c714f1285..e07b15ed5814 100644 --- a/drivers/usb/serial/keyspan.c +++ b/drivers/usb/serial/keyspan.c @@ -410,6 +410,8 @@ static void usa26_instat_callback(struct urb *urb) } port = serial->port[msg->port]; p_priv = usb_get_serial_port_data(port); + if (!p_priv) + goto resubmit; /* Update handshaking pin state information */ old_dcd_state = p_priv->dcd_state; @@ -420,7 +422,7 @@ static void usa26_instat_callback(struct urb *urb) if (old_dcd_state != p_priv->dcd_state) tty_port_tty_hangup(&port->port, true); - +resubmit: /* Resubmit urb so we continue receiving */ err = usb_submit_urb(urb, GFP_ATOMIC); if (err != 0) @@ -527,6 +529,8 @@ static void usa28_instat_callback(struct urb *urb) } port = serial->port[msg->port]; p_priv = usb_get_serial_port_data(port); + if (!p_priv) + goto resubmit; /* Update handshaking pin state information */ old_dcd_state = p_priv->dcd_state; @@ -537,7 +541,7 @@ static void usa28_instat_callback(struct urb *urb) if (old_dcd_state != p_priv->dcd_state && old_dcd_state) tty_port_tty_hangup(&port->port, true); - +resubmit: /* Resubmit urb so we continue receiving */ err = usb_submit_urb(urb, GFP_ATOMIC); if (err != 0) @@ -607,6 +611,8 @@ static void usa49_instat_callback(struct urb *urb) } port = serial->port[msg->portNumber]; p_priv = usb_get_serial_port_data(port); + if (!p_priv) + goto resubmit; /* Update handshaking pin state information */ old_dcd_state = p_priv->dcd_state; @@ -617,7 +623,7 @@ static void usa49_instat_callback(struct urb *urb) if (old_dcd_state != p_priv->dcd_state && old_dcd_state) tty_port_tty_hangup(&port->port, true); - +resubmit: /* Resubmit urb so we continue receiving */ err = usb_submit_urb(urb, GFP_ATOMIC); if (err != 0) @@ -855,6 +861,8 @@ static void usa90_instat_callback(struct urb *urb) port = serial->port[0]; p_priv = usb_get_serial_port_data(port); + if (!p_priv) + goto resubmit; /* Update handshaking pin state information */ old_dcd_state = p_priv->dcd_state; @@ -865,7 +873,7 @@ static void usa90_instat_callback(struct urb *urb) if (old_dcd_state != p_priv->dcd_state && old_dcd_state) tty_port_tty_hangup(&port->port, true); - +resubmit: /* Resubmit urb so we continue receiving */ err = usb_submit_urb(urb, GFP_ATOMIC); if (err != 0) @@ -926,6 +934,8 @@ static void usa67_instat_callback(struct urb *urb) port = serial->port[msg->port]; p_priv = usb_get_serial_port_data(port); + if (!p_priv) + goto resubmit; /* Update handshaking pin state information */ old_dcd_state = p_priv->dcd_state; @@ -934,7 +944,7 @@ static void usa67_instat_callback(struct urb *urb) if (old_dcd_state != p_priv->dcd_state && old_dcd_state) tty_port_tty_hangup(&port->port, true); - +resubmit: /* Resubmit urb so we continue receiving */ err = usb_submit_urb(urb, GFP_ATOMIC); if (err != 0) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 7a4c21b4f676..efdcee15b520 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -234,6 +234,8 @@ static void option_instat_callback(struct urb *urb); #define QUALCOMM_VENDOR_ID 0x05C6 +#define SIERRA_VENDOR_ID 0x1199 + #define CMOTECH_VENDOR_ID 0x16d8 #define CMOTECH_PRODUCT_6001 0x6001 #define CMOTECH_PRODUCT_CMU_300 0x6002 @@ -512,7 +514,7 @@ enum option_blacklist_reason { OPTION_BLACKLIST_RESERVED_IF = 2 }; -#define MAX_BL_NUM 8 +#define MAX_BL_NUM 11 struct option_blacklist_info { /* bitfield of interface numbers for OPTION_BLACKLIST_SENDSETUP */ const unsigned long sendsetup; @@ -601,6 +603,11 @@ static const struct option_blacklist_info telit_le920_blacklist = { .reserved = BIT(1) | BIT(5), }; +static const struct option_blacklist_info sierra_mc73xx_blacklist = { + .sendsetup = BIT(0) | BIT(2), + .reserved = BIT(8) | BIT(10) | BIT(11), +}; + static const struct usb_device_id option_ids[] = { { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) }, { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA) }, @@ -1098,6 +1105,8 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6613)}, /* Onda H600/ZTE MF330 */ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000)}, /* SIMCom SIM5218 */ + { USB_DEVICE_INTERFACE_CLASS(SIERRA_VENDOR_ID, 0x68c0, 0xff), + .driver_info = (kernel_ulong_t)&sierra_mc73xx_blacklist }, /* MC73xx */ { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6001) }, { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_CMU_300) }, { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6003), diff --git a/drivers/usb/serial/qcserial.c b/drivers/usb/serial/qcserial.c index cb3e14780a7e..9c63897b3a56 100644 --- a/drivers/usb/serial/qcserial.c +++ b/drivers/usb/serial/qcserial.c @@ -142,7 +142,6 @@ static const struct usb_device_id id_table[] = { {DEVICE_SWI(0x0f3d, 0x68a2)}, /* Sierra Wireless MC7700 */ {DEVICE_SWI(0x114f, 0x68a2)}, /* Sierra Wireless MC7750 */ {DEVICE_SWI(0x1199, 0x68a2)}, /* Sierra Wireless MC7710 */ - {DEVICE_SWI(0x1199, 0x68c0)}, /* Sierra Wireless MC73xx */ {DEVICE_SWI(0x1199, 0x901c)}, /* Sierra Wireless EM7700 */ {DEVICE_SWI(0x1199, 0x901f)}, /* Sierra Wireless EM7355 */ {DEVICE_SWI(0x1199, 0x9040)}, /* Sierra Wireless Modem */ diff --git a/drivers/usb/storage/uas-detect.h b/drivers/usb/storage/uas-detect.h index 8a6f371ed6e7..9893d696fc97 100644 --- a/drivers/usb/storage/uas-detect.h +++ b/drivers/usb/storage/uas-detect.h @@ -69,16 +69,39 @@ static int uas_use_uas_driver(struct usb_interface *intf, return 0; /* - * ASM1051 and older ASM1053 devices have the same usb-id, and UAS is - * broken on the ASM1051, use the number of streams to differentiate. - * New ASM1053-s also support 32 streams, but have a different prod-id. + * ASMedia has a number of usb3 to sata bridge chips, at the time of + * this writing the following versions exist: + * ASM1051 - no uas support version + * ASM1051 - with broken (*) uas support + * ASM1053 - with working uas support + * ASM1153 - with working uas support + * + * Devices with these chips re-use a number of device-ids over the + * entire line, so the device-id is useless to determine if we're + * dealing with an ASM1051 (which we want to avoid). + * + * The ASM1153 can be identified by config.MaxPower == 0, + * where as the ASM105x models have config.MaxPower == 36. + * + * Differentiating between the ASM1053 and ASM1051 is trickier, when + * connected over USB-3 we can look at the number of streams supported, + * ASM1051 supports 32 streams, where as early ASM1053 versions support + * 16 streams, newer ASM1053-s also support 32 streams, but have a + * different prod-id. + * + * (*) ASM1051 chips do work with UAS with some disks (with the + * US_FL_NO_REPORT_OPCODES quirk), but are broken with other disks */ if (le16_to_cpu(udev->descriptor.idVendor) == 0x174c && - le16_to_cpu(udev->descriptor.idProduct) == 0x55aa) { - if (udev->speed < USB_SPEED_SUPER) { + (le16_to_cpu(udev->descriptor.idProduct) == 0x5106 || + le16_to_cpu(udev->descriptor.idProduct) == 0x55aa)) { + if (udev->actconfig->desc.bMaxPower == 0) { + /* ASM1153, do nothing */ + } else if (udev->speed < USB_SPEED_SUPER) { /* No streams info, assume ASM1051 */ flags |= US_FL_IGNORE_UAS; } else if (usb_ss_max_streams(&eps[1]->ss_ep_comp) == 32) { + /* Possibly an ASM1051, disable uas */ flags |= US_FL_IGNORE_UAS; } } diff --git a/drivers/usb/storage/unusual_uas.h b/drivers/usb/storage/unusual_uas.h index 18a283d6de1c..6df4357d9ee3 100644 --- a/drivers/usb/storage/unusual_uas.h +++ b/drivers/usb/storage/unusual_uas.h @@ -40,6 +40,16 @@ * and don't forget to CC: the USB development list <linux-usb@vger.kernel.org> */ +/* + * Apricorn USB3 dongle sometimes returns "USBSUSBSUSBS" in response to SCSI + * commands in UAS mode. Observed with the 1.28 firmware; are there others? + */ +UNUSUAL_DEV(0x0984, 0x0301, 0x0128, 0x0128, + "Apricorn", + "", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + US_FL_IGNORE_UAS), + /* https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ UNUSUAL_DEV(0x0bc2, 0x2312, 0x0000, 0x9999, "Seagate", @@ -68,6 +78,20 @@ UNUSUAL_DEV(0x0bc2, 0xa003, 0x0000, 0x9999, USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_NO_ATA_1X), +/* Reported-by: Marcin Zajączkowski <mszpak@wp.pl> */ +UNUSUAL_DEV(0x0bc2, 0xa013, 0x0000, 0x9999, + "Seagate", + "Backup Plus", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + US_FL_NO_ATA_1X), + +/* Reported-by: Hans de Goede <hdegoede@redhat.com> */ +UNUSUAL_DEV(0x0bc2, 0xa0a4, 0x0000, 0x9999, + "Seagate", + "Backup Plus Desk", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + US_FL_NO_ATA_1X), + /* https://bbs.archlinux.org/viewtopic.php?id=183190 */ UNUSUAL_DEV(0x0bc2, 0xab20, 0x0000, 0x9999, "Seagate", @@ -82,6 +106,13 @@ UNUSUAL_DEV(0x0bc2, 0xab21, 0x0000, 0x9999, USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_NO_ATA_1X), +/* Reported-by: G. Richard Bellamy <rbellamy@pteradigm.com> */ +UNUSUAL_DEV(0x0bc2, 0xab2a, 0x0000, 0x9999, + "Seagate", + "BUP Fast HDD", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + US_FL_NO_ATA_1X), + /* Reported-by: Claudio Bizzarri <claudio.bizzarri@gmail.com> */ UNUSUAL_DEV(0x152d, 0x0567, 0x0000, 0x9999, "JMicron", @@ -89,14 +120,6 @@ UNUSUAL_DEV(0x152d, 0x0567, 0x0000, 0x9999, USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_NO_REPORT_OPCODES), -/* Most ASM1051 based devices have issues with uas, blacklist them all */ -/* Reported-by: Hans de Goede <hdegoede@redhat.com> */ -UNUSUAL_DEV(0x174c, 0x5106, 0x0000, 0x9999, - "ASMedia", - "ASM1051", - USB_SC_DEVICE, USB_PR_DEVICE, NULL, - US_FL_IGNORE_UAS), - /* Reported-by: Hans de Goede <hdegoede@redhat.com> */ UNUSUAL_DEV(0x2109, 0x0711, 0x0000, 0x9999, "VIA", @@ -104,6 +127,13 @@ UNUSUAL_DEV(0x2109, 0x0711, 0x0000, 0x9999, USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_NO_ATA_1X), +/* Reported-by: Takeo Nakayama <javhera@gmx.com> */ +UNUSUAL_DEV(0x357d, 0x7788, 0x0000, 0x9999, + "JMicron", + "JMS566", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + US_FL_NO_REPORT_OPCODES), + /* Reported-by: Hans de Goede <hdegoede@redhat.com> */ UNUSUAL_DEV(0x4971, 0x1012, 0x0000, 0x9999, "Hitachi", diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c index 255201f22126..7cc0122a18ce 100644 --- a/drivers/vfio/pci/vfio_pci.c +++ b/drivers/vfio/pci/vfio_pci.c @@ -840,13 +840,11 @@ static const struct vfio_device_ops vfio_pci_ops = { static int vfio_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { - u8 type; struct vfio_pci_device *vdev; struct iommu_group *group; int ret; - pci_read_config_byte(pdev, PCI_HEADER_TYPE, &type); - if ((type & PCI_HEADER_TYPE) != PCI_HEADER_TYPE_NORMAL) + if (pdev->hdr_type != PCI_HEADER_TYPE_NORMAL) return -EINVAL; group = iommu_group_get(&pdev->dev); diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c index 14419a8ccbb6..d415d69dc237 100644 --- a/drivers/vhost/net.c +++ b/drivers/vhost/net.c @@ -538,7 +538,7 @@ static int get_rx_bufs(struct vhost_virtqueue *vq, ++headcount; seg += in; } - heads[headcount - 1].len = cpu_to_vhost32(vq, len - datalen); + heads[headcount - 1].len = cpu_to_vhost32(vq, len + datalen); *iovcount = seg; if (unlikely(log)) *log_num = nlogs; diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index 01c01cb3933f..d695b1673ae5 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -911,6 +911,23 @@ vhost_scsi_map_iov_to_prot(struct tcm_vhost_cmd *cmd, return 0; } +static int vhost_scsi_to_tcm_attr(int attr) +{ + switch (attr) { + case VIRTIO_SCSI_S_SIMPLE: + return TCM_SIMPLE_TAG; + case VIRTIO_SCSI_S_ORDERED: + return TCM_ORDERED_TAG; + case VIRTIO_SCSI_S_HEAD: + return TCM_HEAD_TAG; + case VIRTIO_SCSI_S_ACA: + return TCM_ACA_TAG; + default: + break; + } + return TCM_SIMPLE_TAG; +} + static void tcm_vhost_submission_work(struct work_struct *work) { struct tcm_vhost_cmd *cmd = @@ -936,9 +953,10 @@ static void tcm_vhost_submission_work(struct work_struct *work) rc = target_submit_cmd_map_sgls(se_cmd, tv_nexus->tvn_se_sess, cmd->tvc_cdb, &cmd->tvc_sense_buf[0], cmd->tvc_lun, cmd->tvc_exp_data_len, - cmd->tvc_task_attr, cmd->tvc_data_direction, - TARGET_SCF_ACK_KREF, sg_ptr, cmd->tvc_sgl_count, - NULL, 0, sg_prot_ptr, cmd->tvc_prot_sgl_count); + vhost_scsi_to_tcm_attr(cmd->tvc_task_attr), + cmd->tvc_data_direction, TARGET_SCF_ACK_KREF, + sg_ptr, cmd->tvc_sgl_count, NULL, 0, sg_prot_ptr, + cmd->tvc_prot_sgl_count); if (rc < 0) { transport_send_check_condition_and_sense(se_cmd, TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE, 0); diff --git a/drivers/video/fbdev/broadsheetfb.c b/drivers/video/fbdev/broadsheetfb.c index 1c29bd19e3d5..0e5fde1d3ffb 100644 --- a/drivers/video/fbdev/broadsheetfb.c +++ b/drivers/video/fbdev/broadsheetfb.c @@ -636,7 +636,7 @@ static int broadsheet_spiflash_rewrite_sector(struct broadsheetfb_par *par, err = broadsheet_spiflash_read_range(par, start_sector_addr, data_start_addr, sector_buffer); if (err) - return err; + goto out; } /* now we copy our data into the right place in the sector buffer */ @@ -657,7 +657,7 @@ static int broadsheet_spiflash_rewrite_sector(struct broadsheetfb_par *par, err = broadsheet_spiflash_read_range(par, tail_start_addr, tail_len, sector_buffer + tail_start_addr); if (err) - return err; + goto out; } /* if we got here we have the full sector that we want to rewrite. */ @@ -665,11 +665,13 @@ static int broadsheet_spiflash_rewrite_sector(struct broadsheetfb_par *par, /* first erase the sector */ err = broadsheet_spiflash_erase_sector(par, start_sector_addr); if (err) - return err; + goto out; /* now write it */ err = broadsheet_spiflash_write_sector(par, start_sector_addr, sector_buffer, sector_size); +out: + kfree(sector_buffer); return err; } diff --git a/drivers/video/fbdev/simplefb.c b/drivers/video/fbdev/simplefb.c index 92cac803dee3..1085c0432158 100644 --- a/drivers/video/fbdev/simplefb.c +++ b/drivers/video/fbdev/simplefb.c @@ -402,7 +402,7 @@ static int __init simplefb_init(void) if (ret) return ret; - if (IS_ENABLED(CONFIG_OF) && of_chosen) { + if (IS_ENABLED(CONFIG_OF_ADDRESS) && of_chosen) { for_each_child_of_node(of_chosen, np) { if (of_device_is_compatible(np, "simple-framebuffer")) of_platform_device_create(np, NULL, NULL); diff --git a/drivers/virtio/virtio_pci_common.c b/drivers/virtio/virtio_pci_common.c index 2ef9529809d8..9756f21b809e 100644 --- a/drivers/virtio/virtio_pci_common.c +++ b/drivers/virtio/virtio_pci_common.c @@ -282,6 +282,7 @@ void vp_del_vqs(struct virtio_device *vdev) vp_free_vectors(vdev); kfree(vp_dev->vqs); + vp_dev->vqs = NULL; } static int vp_try_to_find_vqs(struct virtio_device *vdev, unsigned nvqs, @@ -421,15 +422,6 @@ int vp_set_vq_affinity(struct virtqueue *vq, int cpu) return 0; } -void virtio_pci_release_dev(struct device *_d) -{ - /* - * No need for a release method as we allocate/free - * all devices together with the pci devices. - * Provide an empty one to avoid getting a warning from core. - */ -} - #ifdef CONFIG_PM_SLEEP static int virtio_pci_freeze(struct device *dev) { diff --git a/drivers/virtio/virtio_pci_common.h b/drivers/virtio/virtio_pci_common.h index adddb647b21d..5a497289b7e9 100644 --- a/drivers/virtio/virtio_pci_common.h +++ b/drivers/virtio/virtio_pci_common.h @@ -126,7 +126,6 @@ const char *vp_bus_name(struct virtio_device *vdev); * - ignore the affinity request if we're using INTX */ int vp_set_vq_affinity(struct virtqueue *vq, int cpu); -void virtio_pci_release_dev(struct device *); int virtio_pci_legacy_probe(struct pci_dev *pci_dev, const struct pci_device_id *id); diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c index 6c76f0f5658c..a5486e65e04b 100644 --- a/drivers/virtio/virtio_pci_legacy.c +++ b/drivers/virtio/virtio_pci_legacy.c @@ -211,6 +211,17 @@ static const struct virtio_config_ops virtio_pci_config_ops = { .set_vq_affinity = vp_set_vq_affinity, }; +static void virtio_pci_release_dev(struct device *_d) +{ + struct virtio_device *vdev = dev_to_virtio(_d); + struct virtio_pci_device *vp_dev = to_vp_device(vdev); + + /* As struct device is a kobject, it's not safe to + * free the memory (including the reference counter itself) + * until it's release callback. */ + kfree(vp_dev); +} + /* the PCI probing function */ int virtio_pci_legacy_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) @@ -302,5 +313,4 @@ void virtio_pci_legacy_remove(struct pci_dev *pci_dev) pci_iounmap(pci_dev, vp_dev->ioaddr); pci_release_regions(pci_dev); pci_disable_device(pci_dev); - kfree(vp_dev); } diff --git a/fs/btrfs/backref.c b/fs/btrfs/backref.c index 2d3e32ebfd15..8729cf68d2fe 100644 --- a/fs/btrfs/backref.c +++ b/fs/btrfs/backref.c @@ -1552,7 +1552,6 @@ int tree_backref_for_extent(unsigned long *ptr, struct extent_buffer *eb, { int ret; int type; - struct btrfs_tree_block_info *info; struct btrfs_extent_inline_ref *eiref; if (*ptr == (unsigned long)-1) @@ -1573,9 +1572,17 @@ int tree_backref_for_extent(unsigned long *ptr, struct extent_buffer *eb, } /* we can treat both ref types equally here */ - info = (struct btrfs_tree_block_info *)(ei + 1); *out_root = btrfs_extent_inline_ref_offset(eb, eiref); - *out_level = btrfs_tree_block_level(eb, info); + + if (key->type == BTRFS_EXTENT_ITEM_KEY) { + struct btrfs_tree_block_info *info; + + info = (struct btrfs_tree_block_info *)(ei + 1); + *out_level = btrfs_tree_block_level(eb, info); + } else { + ASSERT(key->type == BTRFS_METADATA_ITEM_KEY); + *out_level = (u8)key->offset; + } if (ret == 1) *ptr = (unsigned long)-1; diff --git a/fs/btrfs/delayed-inode.c b/fs/btrfs/delayed-inode.c index 054577bddaf2..de4e70fb3cbb 100644 --- a/fs/btrfs/delayed-inode.c +++ b/fs/btrfs/delayed-inode.c @@ -1857,6 +1857,14 @@ int btrfs_delayed_delete_inode_ref(struct inode *inode) { struct btrfs_delayed_node *delayed_node; + /* + * we don't do delayed inode updates during log recovery because it + * leads to enospc problems. This means we also can't do + * delayed inode refs + */ + if (BTRFS_I(inode)->root->fs_info->log_root_recovering) + return -EAGAIN; + delayed_node = btrfs_get_or_create_delayed_node(inode); if (IS_ERR(delayed_node)) return PTR_ERR(delayed_node); diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c index a80b97100d90..15116585e714 100644 --- a/fs/btrfs/extent-tree.c +++ b/fs/btrfs/extent-tree.c @@ -3139,9 +3139,11 @@ static int write_one_cache_group(struct btrfs_trans_handle *trans, struct extent_buffer *leaf; ret = btrfs_search_slot(trans, extent_root, &cache->key, path, 0, 1); - if (ret < 0) + if (ret) { + if (ret > 0) + ret = -ENOENT; goto fail; - BUG_ON(ret); /* Corruption */ + } leaf = path->nodes[0]; bi = btrfs_item_ptr_offset(leaf, path->slots[0]); @@ -3149,11 +3151,9 @@ static int write_one_cache_group(struct btrfs_trans_handle *trans, btrfs_mark_buffer_dirty(leaf); btrfs_release_path(path); fail: - if (ret) { + if (ret) btrfs_abort_transaction(trans, root, ret); - return ret; - } - return 0; + return ret; } diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index e687bb0dc73a..8bf326affb94 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -6255,8 +6255,10 @@ static int btrfs_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) out_fail: btrfs_end_transaction(trans, root); - if (drop_on_err) + if (drop_on_err) { + inode_dec_link_count(inode); iput(inode); + } btrfs_balance_delayed_items(root); btrfs_btree_balance_dirty(root); return err; diff --git a/fs/btrfs/scrub.c b/fs/btrfs/scrub.c index f2bb13a23f86..9e1569ffbf6e 100644 --- a/fs/btrfs/scrub.c +++ b/fs/btrfs/scrub.c @@ -2607,9 +2607,9 @@ static int scrub_extent_for_parity(struct scrub_parity *sparity, ret = scrub_pages_for_parity(sparity, logical, l, physical, dev, flags, gen, mirror_num, have_csum ? csum : NULL); -skip: if (ret) return ret; +skip: len -= l; logical += l; physical += l; diff --git a/fs/ceph/addr.c b/fs/ceph/addr.c index f5013d92a7e6..c81c0e004588 100644 --- a/fs/ceph/addr.c +++ b/fs/ceph/addr.c @@ -1416,7 +1416,7 @@ void ceph_fill_inline_data(struct inode *inode, struct page *locked_page, } } - dout("fill_inline_data %p %llx.%llx len %lu locked_page %p\n", + dout("fill_inline_data %p %llx.%llx len %zu locked_page %p\n", inode, ceph_vinop(inode), len, locked_page); if (len > 0) { diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c index e5d3eadf47b1..bed43081720f 100644 --- a/fs/ext4/extents.c +++ b/fs/ext4/extents.c @@ -5166,8 +5166,8 @@ int ext4_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo, /* fallback to generic here if not in extents fmt */ if (!(ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS))) - return __generic_block_fiemap(inode, fieinfo, start, len, - ext4_get_block); + return generic_block_fiemap(inode, fieinfo, start, len, + ext4_get_block); if (fiemap_check_flags(fieinfo, EXT4_FIEMAP_FLAGS)) return -EBADR; diff --git a/fs/ext4/file.c b/fs/ext4/file.c index 513c12cf444c..8131be8c0af3 100644 --- a/fs/ext4/file.c +++ b/fs/ext4/file.c @@ -273,19 +273,24 @@ static int ext4_file_open(struct inode * inode, struct file * filp) * we determine this extent as a data or a hole according to whether the * page cache has data or not. */ -static int ext4_find_unwritten_pgoff(struct inode *inode, int whence, - loff_t endoff, loff_t *offset) +static int ext4_find_unwritten_pgoff(struct inode *inode, + int whence, + struct ext4_map_blocks *map, + loff_t *offset) { struct pagevec pvec; + unsigned int blkbits; pgoff_t index; pgoff_t end; + loff_t endoff; loff_t startoff; loff_t lastoff; int found = 0; + blkbits = inode->i_sb->s_blocksize_bits; startoff = *offset; lastoff = startoff; - + endoff = (loff_t)(map->m_lblk + map->m_len) << blkbits; index = startoff >> PAGE_CACHE_SHIFT; end = endoff >> PAGE_CACHE_SHIFT; @@ -403,144 +408,147 @@ out: static loff_t ext4_seek_data(struct file *file, loff_t offset, loff_t maxsize) { struct inode *inode = file->f_mapping->host; - struct fiemap_extent_info fie; - struct fiemap_extent ext[2]; - loff_t next; - int i, ret = 0; + struct ext4_map_blocks map; + struct extent_status es; + ext4_lblk_t start, last, end; + loff_t dataoff, isize; + int blkbits; + int ret = 0; mutex_lock(&inode->i_mutex); - if (offset >= inode->i_size) { + + isize = i_size_read(inode); + if (offset >= isize) { mutex_unlock(&inode->i_mutex); return -ENXIO; } - fie.fi_flags = 0; - fie.fi_extents_max = 2; - fie.fi_extents_start = (struct fiemap_extent __user *) &ext; - while (1) { - mm_segment_t old_fs = get_fs(); - - fie.fi_extents_mapped = 0; - memset(ext, 0, sizeof(*ext) * fie.fi_extents_max); - - set_fs(get_ds()); - ret = ext4_fiemap(inode, &fie, offset, maxsize - offset); - set_fs(old_fs); - if (ret) + + blkbits = inode->i_sb->s_blocksize_bits; + start = offset >> blkbits; + last = start; + end = isize >> blkbits; + dataoff = offset; + + do { + map.m_lblk = last; + map.m_len = end - last + 1; + ret = ext4_map_blocks(NULL, inode, &map, 0); + if (ret > 0 && !(map.m_flags & EXT4_MAP_UNWRITTEN)) { + if (last != start) + dataoff = (loff_t)last << blkbits; break; + } - /* No extents found, EOF */ - if (!fie.fi_extents_mapped) { - ret = -ENXIO; + /* + * If there is a delay extent at this offset, + * it will be as a data. + */ + ext4_es_find_delayed_extent_range(inode, last, last, &es); + if (es.es_len != 0 && in_range(last, es.es_lblk, es.es_len)) { + if (last != start) + dataoff = (loff_t)last << blkbits; break; } - for (i = 0; i < fie.fi_extents_mapped; i++) { - next = (loff_t)(ext[i].fe_length + ext[i].fe_logical); - if (offset < (loff_t)ext[i].fe_logical) - offset = (loff_t)ext[i].fe_logical; - /* - * If extent is not unwritten, then it contains valid - * data, mapped or delayed. - */ - if (!(ext[i].fe_flags & FIEMAP_EXTENT_UNWRITTEN)) - goto out; + /* + * If there is a unwritten extent at this offset, + * it will be as a data or a hole according to page + * cache that has data or not. + */ + if (map.m_flags & EXT4_MAP_UNWRITTEN) { + int unwritten; + unwritten = ext4_find_unwritten_pgoff(inode, SEEK_DATA, + &map, &dataoff); + if (unwritten) + break; + } - /* - * If there is a unwritten extent at this offset, - * it will be as a data or a hole according to page - * cache that has data or not. - */ - if (ext4_find_unwritten_pgoff(inode, SEEK_DATA, - next, &offset)) - goto out; + last++; + dataoff = (loff_t)last << blkbits; + } while (last <= end); - if (ext[i].fe_flags & FIEMAP_EXTENT_LAST) { - ret = -ENXIO; - goto out; - } - offset = next; - } - } - if (offset > inode->i_size) - offset = inode->i_size; -out: mutex_unlock(&inode->i_mutex); - if (ret) - return ret; - return vfs_setpos(file, offset, maxsize); + if (dataoff > isize) + return -ENXIO; + + return vfs_setpos(file, dataoff, maxsize); } /* - * ext4_seek_hole() retrieves the offset for SEEK_HOLE + * ext4_seek_hole() retrieves the offset for SEEK_HOLE. */ static loff_t ext4_seek_hole(struct file *file, loff_t offset, loff_t maxsize) { struct inode *inode = file->f_mapping->host; - struct fiemap_extent_info fie; - struct fiemap_extent ext[2]; - loff_t next; - int i, ret = 0; + struct ext4_map_blocks map; + struct extent_status es; + ext4_lblk_t start, last, end; + loff_t holeoff, isize; + int blkbits; + int ret = 0; mutex_lock(&inode->i_mutex); - if (offset >= inode->i_size) { + + isize = i_size_read(inode); + if (offset >= isize) { mutex_unlock(&inode->i_mutex); return -ENXIO; } - fie.fi_flags = 0; - fie.fi_extents_max = 2; - fie.fi_extents_start = (struct fiemap_extent __user *)&ext; - while (1) { - mm_segment_t old_fs = get_fs(); - - fie.fi_extents_mapped = 0; - memset(ext, 0, sizeof(*ext)); + blkbits = inode->i_sb->s_blocksize_bits; + start = offset >> blkbits; + last = start; + end = isize >> blkbits; + holeoff = offset; - set_fs(get_ds()); - ret = ext4_fiemap(inode, &fie, offset, maxsize - offset); - set_fs(old_fs); - if (ret) - break; + do { + map.m_lblk = last; + map.m_len = end - last + 1; + ret = ext4_map_blocks(NULL, inode, &map, 0); + if (ret > 0 && !(map.m_flags & EXT4_MAP_UNWRITTEN)) { + last += ret; + holeoff = (loff_t)last << blkbits; + continue; + } - /* No extents found */ - if (!fie.fi_extents_mapped) - break; + /* + * If there is a delay extent at this offset, + * we will skip this extent. + */ + ext4_es_find_delayed_extent_range(inode, last, last, &es); + if (es.es_len != 0 && in_range(last, es.es_lblk, es.es_len)) { + last = es.es_lblk + es.es_len; + holeoff = (loff_t)last << blkbits; + continue; + } - for (i = 0; i < fie.fi_extents_mapped; i++) { - next = (loff_t)(ext[i].fe_logical + ext[i].fe_length); - /* - * If extent is not unwritten, then it contains valid - * data, mapped or delayed. - */ - if (!(ext[i].fe_flags & FIEMAP_EXTENT_UNWRITTEN)) { - if (offset < (loff_t)ext[i].fe_logical) - goto out; - offset = next; + /* + * If there is a unwritten extent at this offset, + * it will be as a data or a hole according to page + * cache that has data or not. + */ + if (map.m_flags & EXT4_MAP_UNWRITTEN) { + int unwritten; + unwritten = ext4_find_unwritten_pgoff(inode, SEEK_HOLE, + &map, &holeoff); + if (!unwritten) { + last += ret; + holeoff = (loff_t)last << blkbits; continue; } - /* - * If there is a unwritten extent at this offset, - * it will be as a data or a hole according to page - * cache that has data or not. - */ - if (ext4_find_unwritten_pgoff(inode, SEEK_HOLE, - next, &offset)) - goto out; - - offset = next; - if (ext[i].fe_flags & FIEMAP_EXTENT_LAST) - goto out; } - } - if (offset > inode->i_size) - offset = inode->i_size; -out: + + /* find a hole */ + break; + } while (last <= end); + mutex_unlock(&inode->i_mutex); - if (ret) - return ret; - return vfs_setpos(file, offset, maxsize); + if (holeoff > isize) + holeoff = isize; + + return vfs_setpos(file, holeoff, maxsize); } /* diff --git a/fs/ext4/resize.c b/fs/ext4/resize.c index bf76f405a5f9..8a8ec6293b19 100644 --- a/fs/ext4/resize.c +++ b/fs/ext4/resize.c @@ -24,6 +24,18 @@ int ext4_resize_begin(struct super_block *sb) return -EPERM; /* + * If we are not using the primary superblock/GDT copy don't resize, + * because the user tools have no way of handling this. Probably a + * bad time to do it anyways. + */ + if (EXT4_SB(sb)->s_sbh->b_blocknr != + le32_to_cpu(EXT4_SB(sb)->s_es->s_first_data_block)) { + ext4_warning(sb, "won't resize using backup superblock at %llu", + (unsigned long long)EXT4_SB(sb)->s_sbh->b_blocknr); + return -EPERM; + } + + /* * We are not allowed to do online-resizing on a filesystem mounted * with error, because it can destroy the filesystem easily. */ @@ -758,18 +770,6 @@ static int add_new_gdb(handle_t *handle, struct inode *inode, "EXT4-fs: ext4_add_new_gdb: adding group block %lu\n", gdb_num); - /* - * If we are not using the primary superblock/GDT copy don't resize, - * because the user tools have no way of handling this. Probably a - * bad time to do it anyways. - */ - if (EXT4_SB(sb)->s_sbh->b_blocknr != - le32_to_cpu(EXT4_SB(sb)->s_es->s_first_data_block)) { - ext4_warning(sb, "won't resize using backup superblock at %llu", - (unsigned long long)EXT4_SB(sb)->s_sbh->b_blocknr); - return -EPERM; - } - gdb_bh = sb_bread(sb, gdblock); if (!gdb_bh) return -EIO; diff --git a/fs/ext4/super.c b/fs/ext4/super.c index 43c92b1685cb..74c5f53595fb 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -3482,7 +3482,7 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent) if (EXT4_HAS_RO_COMPAT_FEATURE(sb, EXT4_FEATURE_RO_COMPAT_METADATA_CSUM) && EXT4_HAS_RO_COMPAT_FEATURE(sb, EXT4_FEATURE_RO_COMPAT_GDT_CSUM)) - ext4_warning(sb, KERN_INFO "metadata_csum and uninit_bg are " + ext4_warning(sb, "metadata_csum and uninit_bg are " "redundant flags; please run fsck."); /* Check for a known checksum algorithm */ diff --git a/fs/fcntl.c b/fs/fcntl.c index 99d440a4a6ba..ee85cd4e136a 100644 --- a/fs/fcntl.c +++ b/fs/fcntl.c @@ -740,14 +740,15 @@ static int __init fcntl_init(void) * Exceptions: O_NONBLOCK is a two bit define on parisc; O_NDELAY * is defined as O_NONBLOCK on some platforms and not on others. */ - BUILD_BUG_ON(20 - 1 /* for O_RDONLY being 0 */ != HWEIGHT32( + BUILD_BUG_ON(21 - 1 /* for O_RDONLY being 0 */ != HWEIGHT32( O_RDONLY | O_WRONLY | O_RDWR | O_CREAT | O_EXCL | O_NOCTTY | O_TRUNC | O_APPEND | /* O_NONBLOCK | */ __O_SYNC | O_DSYNC | FASYNC | O_DIRECT | O_LARGEFILE | O_DIRECTORY | O_NOFOLLOW | O_NOATIME | O_CLOEXEC | - __FMODE_EXEC | O_PATH | __O_TMPFILE + __FMODE_EXEC | O_PATH | __O_TMPFILE | + __FMODE_NONOTIFY )); fasync_cache = kmem_cache_create("fasync_cache", diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index ba1107977f2e..ed19a7d622fa 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -131,6 +131,13 @@ static void fuse_req_init_context(struct fuse_req *req) req->in.h.pid = current->pid; } +void fuse_set_initialized(struct fuse_conn *fc) +{ + /* Make sure stores before this are seen on another CPU */ + smp_wmb(); + fc->initialized = 1; +} + static bool fuse_block_alloc(struct fuse_conn *fc, bool for_background) { return !fc->initialized || (for_background && fc->blocked); @@ -155,6 +162,8 @@ static struct fuse_req *__fuse_get_req(struct fuse_conn *fc, unsigned npages, if (intr) goto out; } + /* Matches smp_wmb() in fuse_set_initialized() */ + smp_rmb(); err = -ENOTCONN; if (!fc->connected) @@ -253,6 +262,8 @@ struct fuse_req *fuse_get_req_nofail_nopages(struct fuse_conn *fc, atomic_inc(&fc->num_waiting); wait_event(fc->blocked_waitq, fc->initialized); + /* Matches smp_wmb() in fuse_set_initialized() */ + smp_rmb(); req = fuse_request_alloc(0); if (!req) req = get_reserved_req(fc, file); @@ -511,6 +522,39 @@ void fuse_request_send(struct fuse_conn *fc, struct fuse_req *req) } EXPORT_SYMBOL_GPL(fuse_request_send); +static void fuse_adjust_compat(struct fuse_conn *fc, struct fuse_args *args) +{ + if (fc->minor < 4 && args->in.h.opcode == FUSE_STATFS) + args->out.args[0].size = FUSE_COMPAT_STATFS_SIZE; + + if (fc->minor < 9) { + switch (args->in.h.opcode) { + case FUSE_LOOKUP: + case FUSE_CREATE: + case FUSE_MKNOD: + case FUSE_MKDIR: + case FUSE_SYMLINK: + case FUSE_LINK: + args->out.args[0].size = FUSE_COMPAT_ENTRY_OUT_SIZE; + break; + case FUSE_GETATTR: + case FUSE_SETATTR: + args->out.args[0].size = FUSE_COMPAT_ATTR_OUT_SIZE; + break; + } + } + if (fc->minor < 12) { + switch (args->in.h.opcode) { + case FUSE_CREATE: + args->in.args[0].size = sizeof(struct fuse_open_in); + break; + case FUSE_MKNOD: + args->in.args[0].size = FUSE_COMPAT_MKNOD_IN_SIZE; + break; + } + } +} + ssize_t fuse_simple_request(struct fuse_conn *fc, struct fuse_args *args) { struct fuse_req *req; @@ -520,6 +564,9 @@ ssize_t fuse_simple_request(struct fuse_conn *fc, struct fuse_args *args) if (IS_ERR(req)) return PTR_ERR(req); + /* Needs to be done after fuse_get_req() so that fc->minor is valid */ + fuse_adjust_compat(fc, args); + req->in.h.opcode = args->in.h.opcode; req->in.h.nodeid = args->in.h.nodeid; req->in.numargs = args->in.numargs; @@ -2127,7 +2174,7 @@ void fuse_abort_conn(struct fuse_conn *fc) if (fc->connected) { fc->connected = 0; fc->blocked = 0; - fc->initialized = 1; + fuse_set_initialized(fc); end_io_requests(fc); end_queued_requests(fc); end_polls(fc); @@ -2146,7 +2193,7 @@ int fuse_dev_release(struct inode *inode, struct file *file) spin_lock(&fc->lock); fc->connected = 0; fc->blocked = 0; - fc->initialized = 1; + fuse_set_initialized(fc); end_queued_requests(fc); end_polls(fc); wake_up_all(&fc->blocked_waitq); diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index 252b8a5de8b5..08e7b1a9d5d0 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -156,10 +156,7 @@ static void fuse_lookup_init(struct fuse_conn *fc, struct fuse_args *args, args->in.args[0].size = name->len + 1; args->in.args[0].value = name->name; args->out.numargs = 1; - if (fc->minor < 9) - args->out.args[0].size = FUSE_COMPAT_ENTRY_OUT_SIZE; - else - args->out.args[0].size = sizeof(struct fuse_entry_out); + args->out.args[0].size = sizeof(struct fuse_entry_out); args->out.args[0].value = outarg; } @@ -422,16 +419,12 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, args.in.h.opcode = FUSE_CREATE; args.in.h.nodeid = get_node_id(dir); args.in.numargs = 2; - args.in.args[0].size = fc->minor < 12 ? sizeof(struct fuse_open_in) : - sizeof(inarg); + args.in.args[0].size = sizeof(inarg); args.in.args[0].value = &inarg; args.in.args[1].size = entry->d_name.len + 1; args.in.args[1].value = entry->d_name.name; args.out.numargs = 2; - if (fc->minor < 9) - args.out.args[0].size = FUSE_COMPAT_ENTRY_OUT_SIZE; - else - args.out.args[0].size = sizeof(outentry); + args.out.args[0].size = sizeof(outentry); args.out.args[0].value = &outentry; args.out.args[1].size = sizeof(outopen); args.out.args[1].value = &outopen; @@ -539,10 +532,7 @@ static int create_new_entry(struct fuse_conn *fc, struct fuse_args *args, memset(&outarg, 0, sizeof(outarg)); args->in.h.nodeid = get_node_id(dir); args->out.numargs = 1; - if (fc->minor < 9) - args->out.args[0].size = FUSE_COMPAT_ENTRY_OUT_SIZE; - else - args->out.args[0].size = sizeof(outarg); + args->out.args[0].size = sizeof(outarg); args->out.args[0].value = &outarg; err = fuse_simple_request(fc, args); if (err) @@ -592,8 +582,7 @@ static int fuse_mknod(struct inode *dir, struct dentry *entry, umode_t mode, inarg.umask = current_umask(); args.in.h.opcode = FUSE_MKNOD; args.in.numargs = 2; - args.in.args[0].size = fc->minor < 12 ? FUSE_COMPAT_MKNOD_IN_SIZE : - sizeof(inarg); + args.in.args[0].size = sizeof(inarg); args.in.args[0].value = &inarg; args.in.args[1].size = entry->d_name.len + 1; args.in.args[1].value = entry->d_name.name; @@ -899,10 +888,7 @@ static int fuse_do_getattr(struct inode *inode, struct kstat *stat, args.in.args[0].size = sizeof(inarg); args.in.args[0].value = &inarg; args.out.numargs = 1; - if (fc->minor < 9) - args.out.args[0].size = FUSE_COMPAT_ATTR_OUT_SIZE; - else - args.out.args[0].size = sizeof(outarg); + args.out.args[0].size = sizeof(outarg); args.out.args[0].value = &outarg; err = fuse_simple_request(fc, &args); if (!err) { @@ -1574,10 +1560,7 @@ static void fuse_setattr_fill(struct fuse_conn *fc, struct fuse_args *args, args->in.args[0].size = sizeof(*inarg_p); args->in.args[0].value = inarg_p; args->out.numargs = 1; - if (fc->minor < 9) - args->out.args[0].size = FUSE_COMPAT_ATTR_OUT_SIZE; - else - args->out.args[0].size = sizeof(*outarg_p); + args->out.args[0].size = sizeof(*outarg_p); args->out.args[0].value = outarg_p; } diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h index e0fc6725d1d0..1cdfb07c1376 100644 --- a/fs/fuse/fuse_i.h +++ b/fs/fuse/fuse_i.h @@ -906,4 +906,6 @@ int fuse_write_inode(struct inode *inode, struct writeback_control *wbc); int fuse_do_setattr(struct inode *inode, struct iattr *attr, struct file *file); +void fuse_set_initialized(struct fuse_conn *fc); + #endif /* _FS_FUSE_I_H */ diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c index 6749109f255d..f38256e4476e 100644 --- a/fs/fuse/inode.c +++ b/fs/fuse/inode.c @@ -424,8 +424,7 @@ static int fuse_statfs(struct dentry *dentry, struct kstatfs *buf) args.in.h.opcode = FUSE_STATFS; args.in.h.nodeid = get_node_id(dentry->d_inode); args.out.numargs = 1; - args.out.args[0].size = - fc->minor < 4 ? FUSE_COMPAT_STATFS_SIZE : sizeof(outarg); + args.out.args[0].size = sizeof(outarg); args.out.args[0].value = &outarg; err = fuse_simple_request(fc, &args); if (!err) @@ -898,7 +897,7 @@ static void process_init_reply(struct fuse_conn *fc, struct fuse_req *req) fc->max_write = max_t(unsigned, 4096, fc->max_write); fc->conn_init = 1; } - fc->initialized = 1; + fuse_set_initialized(fc); wake_up_all(&fc->blocked_waitq); } diff --git a/fs/kernfs/dir.c b/fs/kernfs/dir.c index 37989f02a226..2d881b381d2b 100644 --- a/fs/kernfs/dir.c +++ b/fs/kernfs/dir.c @@ -201,10 +201,14 @@ static unsigned int kernfs_name_hash(const char *name, const void *ns) static int kernfs_name_compare(unsigned int hash, const char *name, const void *ns, const struct kernfs_node *kn) { - if (hash != kn->hash) - return hash - kn->hash; - if (ns != kn->ns) - return ns - kn->ns; + if (hash < kn->hash) + return -1; + if (hash > kn->hash) + return 1; + if (ns < kn->ns) + return -1; + if (ns > kn->ns) + return 1; return strcmp(name, kn->name); } diff --git a/fs/lockd/svc.c b/fs/lockd/svc.c index e94c887da2d7..55505cbe11af 100644 --- a/fs/lockd/svc.c +++ b/fs/lockd/svc.c @@ -138,10 +138,6 @@ lockd(void *vrqstp) dprintk("NFS locking service started (ver " LOCKD_VERSION ").\n"); - if (!nlm_timeout) - nlm_timeout = LOCKD_DFLT_TIMEO; - nlmsvc_timeout = nlm_timeout * HZ; - /* * The main request loop. We don't terminate until the last * NFS mount or NFS daemon has gone away. @@ -350,6 +346,10 @@ static struct svc_serv *lockd_create_svc(void) printk(KERN_WARNING "lockd_up: no pid, %d users??\n", nlmsvc_users); + if (!nlm_timeout) + nlm_timeout = LOCKD_DFLT_TIMEO; + nlmsvc_timeout = nlm_timeout * HZ; + serv = svc_create(&nlmsvc_program, LOCKD_BUFSIZE, svc_rpcb_cleanup); if (!serv) { printk(KERN_WARNING "lockd_up: create service failed\n"); diff --git a/fs/locks.c b/fs/locks.c index 735b8d3fa78c..59e2f905e4ff 100644 --- a/fs/locks.c +++ b/fs/locks.c @@ -1702,7 +1702,7 @@ static int generic_delete_lease(struct file *filp) break; } trace_generic_delete_lease(inode, fl); - if (fl) + if (fl && IS_LEASE(fl)) error = fl->fl_lmops->lm_change(before, F_UNLCK, &dispose); spin_unlock(&inode->i_lock); locks_dispose_list(&dispose); diff --git a/fs/nfs/nfs4client.c b/fs/nfs/nfs4client.c index 03311259b0c4..953daa44a282 100644 --- a/fs/nfs/nfs4client.c +++ b/fs/nfs/nfs4client.c @@ -228,6 +228,7 @@ static void nfs4_shutdown_client(struct nfs_client *clp) kfree(clp->cl_serverowner); kfree(clp->cl_serverscope); kfree(clp->cl_implid); + kfree(clp->cl_owner_id); } void nfs4_free_client(struct nfs_client *clp) @@ -452,6 +453,14 @@ static void nfs4_swap_callback_idents(struct nfs_client *keep, spin_unlock(&nn->nfs_client_lock); } +static bool nfs4_match_client_owner_id(const struct nfs_client *clp1, + const struct nfs_client *clp2) +{ + if (clp1->cl_owner_id == NULL || clp2->cl_owner_id == NULL) + return true; + return strcmp(clp1->cl_owner_id, clp2->cl_owner_id) == 0; +} + /** * nfs40_walk_client_list - Find server that recognizes a client ID * @@ -483,9 +492,6 @@ int nfs40_walk_client_list(struct nfs_client *new, if (pos->rpc_ops != new->rpc_ops) continue; - if (pos->cl_proto != new->cl_proto) - continue; - if (pos->cl_minorversion != new->cl_minorversion) continue; @@ -510,6 +516,9 @@ int nfs40_walk_client_list(struct nfs_client *new, if (pos->cl_clientid != new->cl_clientid) continue; + if (!nfs4_match_client_owner_id(pos, new)) + continue; + atomic_inc(&pos->cl_count); spin_unlock(&nn->nfs_client_lock); @@ -566,20 +575,14 @@ static bool nfs4_match_clientids(struct nfs_client *a, struct nfs_client *b) } /* - * Returns true if the server owners match + * Returns true if the server major ids match */ static bool -nfs4_match_serverowners(struct nfs_client *a, struct nfs_client *b) +nfs4_check_clientid_trunking(struct nfs_client *a, struct nfs_client *b) { struct nfs41_server_owner *o1 = a->cl_serverowner; struct nfs41_server_owner *o2 = b->cl_serverowner; - if (o1->minor_id != o2->minor_id) { - dprintk("NFS: --> %s server owner minor IDs do not match\n", - __func__); - return false; - } - if (o1->major_id_sz != o2->major_id_sz) goto out_major_mismatch; if (memcmp(o1->major_id, o2->major_id, o1->major_id_sz) != 0) @@ -621,9 +624,6 @@ int nfs41_walk_client_list(struct nfs_client *new, if (pos->rpc_ops != new->rpc_ops) continue; - if (pos->cl_proto != new->cl_proto) - continue; - if (pos->cl_minorversion != new->cl_minorversion) continue; @@ -654,7 +654,19 @@ int nfs41_walk_client_list(struct nfs_client *new, if (!nfs4_match_clientids(pos, new)) continue; - if (!nfs4_match_serverowners(pos, new)) + /* + * Note that session trunking is just a special subcase of + * client id trunking. In either case, we want to fall back + * to using the existing nfs_client. + */ + if (!nfs4_check_clientid_trunking(pos, new)) + continue; + + /* Unlike NFSv4.0, we know that NFSv4.1 always uses the + * uniform string, however someone might switch the + * uniquifier string on us. + */ + if (!nfs4_match_client_owner_id(pos, new)) continue; atomic_inc(&pos->cl_count); diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c index e7f8d5ff2581..c347705b0161 100644 --- a/fs/nfs/nfs4proc.c +++ b/fs/nfs/nfs4proc.c @@ -1117,8 +1117,6 @@ static int can_open_delegated(struct nfs_delegation *delegation, fmode_t fmode) return 0; if ((delegation->type & fmode) != fmode) return 0; - if (test_bit(NFS_DELEGATION_NEED_RECLAIM, &delegation->flags)) - return 0; if (test_bit(NFS_DELEGATION_RETURNING, &delegation->flags)) return 0; nfs_mark_delegation_referenced(delegation); @@ -4917,11 +4915,14 @@ static void nfs4_init_boot_verifier(const struct nfs_client *clp, } static unsigned int -nfs4_init_nonuniform_client_string(const struct nfs_client *clp, +nfs4_init_nonuniform_client_string(struct nfs_client *clp, char *buf, size_t len) { unsigned int result; + if (clp->cl_owner_id != NULL) + return strlcpy(buf, clp->cl_owner_id, len); + rcu_read_lock(); result = scnprintf(buf, len, "Linux NFSv4.0 %s/%s %s", clp->cl_ipaddr, @@ -4930,24 +4931,32 @@ nfs4_init_nonuniform_client_string(const struct nfs_client *clp, rpc_peeraddr2str(clp->cl_rpcclient, RPC_DISPLAY_PROTO)); rcu_read_unlock(); + clp->cl_owner_id = kstrdup(buf, GFP_KERNEL); return result; } static unsigned int -nfs4_init_uniform_client_string(const struct nfs_client *clp, +nfs4_init_uniform_client_string(struct nfs_client *clp, char *buf, size_t len) { const char *nodename = clp->cl_rpcclient->cl_nodename; + unsigned int result; + + if (clp->cl_owner_id != NULL) + return strlcpy(buf, clp->cl_owner_id, len); if (nfs4_client_id_uniquifier[0] != '\0') - return scnprintf(buf, len, "Linux NFSv%u.%u %s/%s", + result = scnprintf(buf, len, "Linux NFSv%u.%u %s/%s", clp->rpc_ops->version, clp->cl_minorversion, nfs4_client_id_uniquifier, nodename); - return scnprintf(buf, len, "Linux NFSv%u.%u %s", + else + result = scnprintf(buf, len, "Linux NFSv%u.%u %s", clp->rpc_ops->version, clp->cl_minorversion, nodename); + clp->cl_owner_id = kstrdup(buf, GFP_KERNEL); + return result; } /* diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 3550a9c87616..c06a1ba80d73 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -3897,11 +3897,11 @@ nfs4_set_delegation(struct nfs4_client *clp, struct svc_fh *fh, status = nfs4_setlease(dp); goto out; } - atomic_inc(&fp->fi_delegees); if (fp->fi_had_conflict) { status = -EAGAIN; goto out_unlock; } + atomic_inc(&fp->fi_delegees); hash_delegation_locked(dp, fp); status = 0; out_unlock: diff --git a/fs/notify/fanotify/fanotify_user.c b/fs/notify/fanotify/fanotify_user.c index c991616acca9..bff8567aa42d 100644 --- a/fs/notify/fanotify/fanotify_user.c +++ b/fs/notify/fanotify/fanotify_user.c @@ -259,16 +259,15 @@ static ssize_t fanotify_read(struct file *file, char __user *buf, struct fsnotify_event *kevent; char __user *start; int ret; - DEFINE_WAIT(wait); + DEFINE_WAIT_FUNC(wait, woken_wake_function); start = buf; group = file->private_data; pr_debug("%s: group=%p\n", __func__, group); + add_wait_queue(&group->notification_waitq, &wait); while (1) { - prepare_to_wait(&group->notification_waitq, &wait, TASK_INTERRUPTIBLE); - mutex_lock(&group->notification_mutex); kevent = get_one_event(group, count); mutex_unlock(&group->notification_mutex); @@ -289,7 +288,8 @@ static ssize_t fanotify_read(struct file *file, char __user *buf, if (start != buf) break; - schedule(); + + wait_woken(&wait, TASK_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT); continue; } @@ -318,8 +318,8 @@ static ssize_t fanotify_read(struct file *file, char __user *buf, buf += ret; count -= ret; } + remove_wait_queue(&group->notification_waitq, &wait); - finish_wait(&group->notification_waitq, &wait); if (start != buf && ret != -EFAULT) ret = buf - start; return ret; diff --git a/fs/ocfs2/dlm/dlmrecovery.c b/fs/ocfs2/dlm/dlmrecovery.c index 79b5af5e6a7b..cecd875653e4 100644 --- a/fs/ocfs2/dlm/dlmrecovery.c +++ b/fs/ocfs2/dlm/dlmrecovery.c @@ -2023,11 +2023,8 @@ leave: dlm_lockres_drop_inflight_ref(dlm, res); spin_unlock(&res->spinlock); - if (ret < 0) { + if (ret < 0) mlog_errno(ret); - if (newlock) - dlm_lock_put(newlock); - } return ret; } diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c index b931e04e3388..914c121ec890 100644 --- a/fs/ocfs2/namei.c +++ b/fs/ocfs2/namei.c @@ -94,6 +94,14 @@ static int ocfs2_create_symlink_data(struct ocfs2_super *osb, struct inode *inode, const char *symname); +static int ocfs2_double_lock(struct ocfs2_super *osb, + struct buffer_head **bh1, + struct inode *inode1, + struct buffer_head **bh2, + struct inode *inode2, + int rename); + +static void ocfs2_double_unlock(struct inode *inode1, struct inode *inode2); /* An orphan dir name is an 8 byte value, printed as a hex string */ #define OCFS2_ORPHAN_NAMELEN ((int)(2 * sizeof(u64))) @@ -678,8 +686,10 @@ static int ocfs2_link(struct dentry *old_dentry, { handle_t *handle; struct inode *inode = old_dentry->d_inode; + struct inode *old_dir = old_dentry->d_parent->d_inode; int err; struct buffer_head *fe_bh = NULL; + struct buffer_head *old_dir_bh = NULL; struct buffer_head *parent_fe_bh = NULL; struct ocfs2_dinode *fe = NULL; struct ocfs2_super *osb = OCFS2_SB(dir->i_sb); @@ -696,19 +706,33 @@ static int ocfs2_link(struct dentry *old_dentry, dquot_initialize(dir); - err = ocfs2_inode_lock_nested(dir, &parent_fe_bh, 1, OI_LS_PARENT); + err = ocfs2_double_lock(osb, &old_dir_bh, old_dir, + &parent_fe_bh, dir, 0); if (err < 0) { if (err != -ENOENT) mlog_errno(err); return err; } + /* make sure both dirs have bhs + * get an extra ref on old_dir_bh if old==new */ + if (!parent_fe_bh) { + if (old_dir_bh) { + parent_fe_bh = old_dir_bh; + get_bh(parent_fe_bh); + } else { + mlog(ML_ERROR, "%s: no old_dir_bh!\n", osb->uuid_str); + err = -EIO; + goto out; + } + } + if (!dir->i_nlink) { err = -ENOENT; goto out; } - err = ocfs2_lookup_ino_from_name(dir, old_dentry->d_name.name, + err = ocfs2_lookup_ino_from_name(old_dir, old_dentry->d_name.name, old_dentry->d_name.len, &old_de_ino); if (err) { err = -ENOENT; @@ -801,10 +825,11 @@ out_unlock_inode: ocfs2_inode_unlock(inode, 1); out: - ocfs2_inode_unlock(dir, 1); + ocfs2_double_unlock(old_dir, dir); brelse(fe_bh); brelse(parent_fe_bh); + brelse(old_dir_bh); ocfs2_free_dir_lookup_result(&lookup); @@ -1072,14 +1097,15 @@ static int ocfs2_check_if_ancestor(struct ocfs2_super *osb, } /* - * The only place this should be used is rename! + * The only place this should be used is rename and link! * if they have the same id, then the 1st one is the only one locked. */ static int ocfs2_double_lock(struct ocfs2_super *osb, struct buffer_head **bh1, struct inode *inode1, struct buffer_head **bh2, - struct inode *inode2) + struct inode *inode2, + int rename) { int status; int inode1_is_ancestor, inode2_is_ancestor; @@ -1127,7 +1153,7 @@ static int ocfs2_double_lock(struct ocfs2_super *osb, } /* lock id2 */ status = ocfs2_inode_lock_nested(inode2, bh2, 1, - OI_LS_RENAME1); + rename == 1 ? OI_LS_RENAME1 : OI_LS_PARENT); if (status < 0) { if (status != -ENOENT) mlog_errno(status); @@ -1136,7 +1162,8 @@ static int ocfs2_double_lock(struct ocfs2_super *osb, } /* lock id1 */ - status = ocfs2_inode_lock_nested(inode1, bh1, 1, OI_LS_RENAME2); + status = ocfs2_inode_lock_nested(inode1, bh1, 1, + rename == 1 ? OI_LS_RENAME2 : OI_LS_PARENT); if (status < 0) { /* * An error return must mean that no cluster locks @@ -1252,7 +1279,7 @@ static int ocfs2_rename(struct inode *old_dir, /* if old and new are the same, this'll just do one lock. */ status = ocfs2_double_lock(osb, &old_dir_bh, old_dir, - &new_dir_bh, new_dir); + &new_dir_bh, new_dir, 1); if (status < 0) { mlog_errno(status); goto bail; diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 3ca9b751f122..b95dc32a6e6b 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -196,8 +196,8 @@ struct acpi_processor_flags { struct acpi_processor { acpi_handle handle; u32 acpi_id; - u32 apic_id; - u32 id; + u32 phys_id; /* CPU hardware ID such as APIC ID for x86 */ + u32 id; /* CPU logical ID allocated by OS */ u32 pblk; int performance_platform_limit; int throttling_platform_limit; @@ -310,8 +310,8 @@ static inline int acpi_processor_get_bios_limit(int cpu, unsigned int *limit) #endif /* CONFIG_CPU_FREQ */ /* in processor_core.c */ -int acpi_get_apicid(acpi_handle, int type, u32 acpi_id); -int acpi_map_cpuid(int apic_id, u32 acpi_id); +int acpi_get_phys_id(acpi_handle, int type, u32 acpi_id); +int acpi_map_cpuid(int phys_id, u32 acpi_id); int acpi_get_cpuid(acpi_handle, int type, u32 acpi_id); /* in processor_pdc.c */ diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h index 08848050922e..db284bff29dc 100644 --- a/include/asm-generic/tlb.h +++ b/include/asm-generic/tlb.h @@ -136,8 +136,12 @@ static inline void __tlb_adjust_range(struct mmu_gather *tlb, static inline void __tlb_reset_range(struct mmu_gather *tlb) { - tlb->start = TASK_SIZE; - tlb->end = 0; + if (tlb->fullmm) { + tlb->start = tlb->end = ~0; + } else { + tlb->start = TASK_SIZE; + tlb->end = 0; + } } /* diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 65da9fb939a7..ac55ab0dc88b 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -31,6 +31,7 @@ #include <linux/idr.h> #include <linux/fb.h> #include <linux/hdmi.h> +#include <linux/media-bus-format.h> #include <uapi/drm/drm_mode.h> #include <uapi/drm/drm_fourcc.h> #include <drm/drm_modeset_lock.h> @@ -139,6 +140,9 @@ struct drm_display_info { enum subpixel_order subpixel_order; u32 color_formats; + const u32 *bus_formats; + unsigned int num_bus_formats; + /* Mask of supported hdmi deep color modes */ u8 edid_hdmi_dc_modes; @@ -1283,6 +1287,10 @@ int drm_mode_connector_set_tile_property(struct drm_connector *connector); extern int drm_mode_connector_update_edid_property(struct drm_connector *connector, const struct edid *edid); +extern int drm_display_info_set_bus_formats(struct drm_display_info *info, + const u32 *formats, + unsigned int num_formats); + static inline bool drm_property_type_is(struct drm_property *property, uint32_t type) { diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 856d381b1d5b..d459cd17b477 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -147,8 +147,8 @@ void acpi_numa_arch_fixup(void); #ifdef CONFIG_ACPI_HOTPLUG_CPU /* Arch dependent functions for cpu hotplug support */ -int acpi_map_lsapic(acpi_handle handle, int physid, int *pcpu); -int acpi_unmap_lsapic(int cpu); +int acpi_map_cpu(acpi_handle handle, int physid, int *pcpu); +int acpi_unmap_cpu(int cpu); #endif /* CONFIG_ACPI_HOTPLUG_CPU */ int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base); diff --git a/include/linux/blk-mq.h b/include/linux/blk-mq.h index 8aded9ab2e4e..5735e7130d63 100644 --- a/include/linux/blk-mq.h +++ b/include/linux/blk-mq.h @@ -34,7 +34,6 @@ struct blk_mq_hw_ctx { unsigned long flags; /* BLK_MQ_F_* flags */ struct request_queue *queue; - unsigned int queue_num; struct blk_flush_queue *fq; void *driver_data; @@ -54,7 +53,7 @@ struct blk_mq_hw_ctx { unsigned long dispatched[BLK_MQ_MAX_DISPATCH_ORDER]; unsigned int numa_node; - unsigned int cmd_size; /* per-request extra data */ + unsigned int queue_num; atomic_t nr_active; @@ -195,13 +194,16 @@ static inline u16 blk_mq_unique_tag_to_tag(u32 unique_tag) struct blk_mq_hw_ctx *blk_mq_map_queue(struct request_queue *, const int ctx_index); struct blk_mq_hw_ctx *blk_mq_alloc_single_hw_queue(struct blk_mq_tag_set *, unsigned int, int); +int blk_mq_request_started(struct request *rq); void blk_mq_start_request(struct request *rq); void blk_mq_end_request(struct request *rq, int error); void __blk_mq_end_request(struct request *rq, int error); void blk_mq_requeue_request(struct request *rq); void blk_mq_add_to_requeue_list(struct request *rq, bool at_head); +void blk_mq_cancel_requeue_work(struct request_queue *q); void blk_mq_kick_requeue_list(struct request_queue *q); +void blk_mq_abort_requeue_list(struct request_queue *q); void blk_mq_complete_request(struct request *rq); void blk_mq_stop_hw_queue(struct blk_mq_hw_ctx *hctx); @@ -212,6 +214,8 @@ void blk_mq_start_stopped_hw_queues(struct request_queue *q, bool async); void blk_mq_delay_queue(struct blk_mq_hw_ctx *hctx, unsigned long msecs); void blk_mq_tag_busy_iter(struct blk_mq_hw_ctx *hctx, busy_iter_fn *fn, void *priv); +void blk_mq_unfreeze_queue(struct request_queue *q); +void blk_mq_freeze_queue_start(struct request_queue *q); /* * Driver command data is immediately after the request. So subtract request diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h index 445d59231bc4..c294e3e25e37 100644 --- a/include/linux/blk_types.h +++ b/include/linux/blk_types.h @@ -190,6 +190,7 @@ enum rq_flag_bits { __REQ_PM, /* runtime pm request */ __REQ_HASHED, /* on IO scheduler merge hash */ __REQ_MQ_INFLIGHT, /* track inflight for MQ */ + __REQ_NO_TIMEOUT, /* requests may never expire */ __REQ_NR_BITS, /* stops here */ }; @@ -243,5 +244,6 @@ enum rq_flag_bits { #define REQ_PM (1ULL << __REQ_PM) #define REQ_HASHED (1ULL << __REQ_HASHED) #define REQ_MQ_INFLIGHT (1ULL << __REQ_MQ_INFLIGHT) +#define REQ_NO_TIMEOUT (1ULL << __REQ_NO_TIMEOUT) #endif /* __LINUX_BLK_TYPES_H */ diff --git a/include/linux/ceph/osd_client.h b/include/linux/ceph/osd_client.h index 5d86416d35f2..61b19c46bdb3 100644 --- a/include/linux/ceph/osd_client.h +++ b/include/linux/ceph/osd_client.h @@ -87,8 +87,8 @@ struct ceph_osd_req_op { struct ceph_osd_data osd_data; } extent; struct { - __le32 name_len; - __le32 value_len; + u32 name_len; + u32 value_len; __u8 cmp_op; /* CEPH_OSD_CMPXATTR_OP_* */ __u8 cmp_mode; /* CEPH_OSD_CMPXATTR_MODE_* */ struct ceph_osd_data osd_data; diff --git a/include/linux/compiler.h b/include/linux/compiler.h index a1c81f80978e..33063f872ee3 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -215,7 +215,7 @@ static __always_inline void __read_once_size(volatile void *p, void *res, int si } } -static __always_inline void __assign_once_size(volatile void *p, void *res, int size) +static __always_inline void __write_once_size(volatile void *p, void *res, int size) { switch (size) { case 1: *(volatile __u8 *)p = *(__u8 *)res; break; @@ -235,15 +235,15 @@ static __always_inline void __assign_once_size(volatile void *p, void *res, int /* * Prevent the compiler from merging or refetching reads or writes. The * compiler is also forbidden from reordering successive instances of - * READ_ONCE, ASSIGN_ONCE and ACCESS_ONCE (see below), but only when the + * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the * compiler is aware of some particular ordering. One way to make the * compiler aware of ordering is to put the two invocations of READ_ONCE, - * ASSIGN_ONCE or ACCESS_ONCE() in different C statements. + * WRITE_ONCE or ACCESS_ONCE() in different C statements. * * In contrast to ACCESS_ONCE these two macros will also work on aggregate * data types like structs or unions. If the size of the accessed data * type exceeds the word size of the machine (e.g., 32 bits or 64 bits) - * READ_ONCE() and ASSIGN_ONCE() will fall back to memcpy and print a + * READ_ONCE() and WRITE_ONCE() will fall back to memcpy and print a * compile-time warning. * * Their two major use cases are: (1) Mediating communication between @@ -257,8 +257,8 @@ static __always_inline void __assign_once_size(volatile void *p, void *res, int #define READ_ONCE(x) \ ({ typeof(x) __val; __read_once_size(&x, &__val, sizeof(__val)); __val; }) -#define ASSIGN_ONCE(val, x) \ - ({ typeof(x) __val; __val = val; __assign_once_size(&x, &__val, sizeof(__val)); __val; }) +#define WRITE_ONCE(x, val) \ + ({ typeof(x) __val; __val = val; __write_once_size(&x, &__val, sizeof(__val)); __val; }) #endif /* __KERNEL__ */ diff --git a/include/linux/fs.h b/include/linux/fs.h index f90c0282c114..42efe13077b6 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -135,7 +135,7 @@ typedef void (dio_iodone_t)(struct kiocb *iocb, loff_t offset, #define FMODE_CAN_WRITE ((__force fmode_t)0x40000) /* File was opened by fanotify and shouldn't generate fanotify events */ -#define FMODE_NONOTIFY ((__force fmode_t)0x1000000) +#define FMODE_NONOTIFY ((__force fmode_t)0x4000000) /* * Flag for rw_copy_check_uvector and compat_rw_copy_check_uvector diff --git a/include/linux/genetlink.h b/include/linux/genetlink.h index 55b685719d52..09460d6d6682 100644 --- a/include/linux/genetlink.h +++ b/include/linux/genetlink.h @@ -11,6 +11,10 @@ extern void genl_unlock(void); extern int lockdep_genl_is_held(void); #endif +/* for synchronisation between af_netlink and genetlink */ +extern atomic_t genl_sk_destructing_cnt; +extern wait_queue_head_t genl_sk_destructing_waitq; + /** * rcu_dereference_genl - rcu_dereference with debug checking * @p: The pointer to read, prior to dereferencing diff --git a/include/linux/kdb.h b/include/linux/kdb.h index 290db1269c4c..75ae2e2631fc 100644 --- a/include/linux/kdb.h +++ b/include/linux/kdb.h @@ -13,11 +13,54 @@ * Copyright (C) 2009 Jason Wessel <jason.wessel@windriver.com> */ +/* Shifted versions of the command enable bits are be used if the command + * has no arguments (see kdb_check_flags). This allows commands, such as + * go, to have different permissions depending upon whether it is called + * with an argument. + */ +#define KDB_ENABLE_NO_ARGS_SHIFT 10 + typedef enum { - KDB_REPEAT_NONE = 0, /* Do not repeat this command */ - KDB_REPEAT_NO_ARGS, /* Repeat the command without arguments */ - KDB_REPEAT_WITH_ARGS, /* Repeat the command including its arguments */ -} kdb_repeat_t; + KDB_ENABLE_ALL = (1 << 0), /* Enable everything */ + KDB_ENABLE_MEM_READ = (1 << 1), + KDB_ENABLE_MEM_WRITE = (1 << 2), + KDB_ENABLE_REG_READ = (1 << 3), + KDB_ENABLE_REG_WRITE = (1 << 4), + KDB_ENABLE_INSPECT = (1 << 5), + KDB_ENABLE_FLOW_CTRL = (1 << 6), + KDB_ENABLE_SIGNAL = (1 << 7), + KDB_ENABLE_REBOOT = (1 << 8), + /* User exposed values stop here, all remaining flags are + * exclusively used to describe a commands behaviour. + */ + + KDB_ENABLE_ALWAYS_SAFE = (1 << 9), + KDB_ENABLE_MASK = (1 << KDB_ENABLE_NO_ARGS_SHIFT) - 1, + + KDB_ENABLE_ALL_NO_ARGS = KDB_ENABLE_ALL << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_MEM_READ_NO_ARGS = KDB_ENABLE_MEM_READ + << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_MEM_WRITE_NO_ARGS = KDB_ENABLE_MEM_WRITE + << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_REG_READ_NO_ARGS = KDB_ENABLE_REG_READ + << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_REG_WRITE_NO_ARGS = KDB_ENABLE_REG_WRITE + << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_INSPECT_NO_ARGS = KDB_ENABLE_INSPECT + << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_FLOW_CTRL_NO_ARGS = KDB_ENABLE_FLOW_CTRL + << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_SIGNAL_NO_ARGS = KDB_ENABLE_SIGNAL + << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_REBOOT_NO_ARGS = KDB_ENABLE_REBOOT + << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_ALWAYS_SAFE_NO_ARGS = KDB_ENABLE_ALWAYS_SAFE + << KDB_ENABLE_NO_ARGS_SHIFT, + KDB_ENABLE_MASK_NO_ARGS = KDB_ENABLE_MASK << KDB_ENABLE_NO_ARGS_SHIFT, + + KDB_REPEAT_NO_ARGS = 0x40000000, /* Repeat the command w/o arguments */ + KDB_REPEAT_WITH_ARGS = 0x80000000, /* Repeat the command with args */ +} kdb_cmdflags_t; typedef int (*kdb_func_t)(int, const char **); @@ -62,6 +105,7 @@ extern atomic_t kdb_event; #define KDB_BADLENGTH (-19) #define KDB_NOBP (-20) #define KDB_BADADDR (-21) +#define KDB_NOPERM (-22) /* * kdb_diemsg @@ -146,17 +190,17 @@ static inline const char *kdb_walk_kallsyms(loff_t *pos) /* Dynamic kdb shell command registration */ extern int kdb_register(char *, kdb_func_t, char *, char *, short); -extern int kdb_register_repeat(char *, kdb_func_t, char *, char *, - short, kdb_repeat_t); +extern int kdb_register_flags(char *, kdb_func_t, char *, char *, + short, kdb_cmdflags_t); extern int kdb_unregister(char *); #else /* ! CONFIG_KGDB_KDB */ static inline __printf(1, 2) int kdb_printf(const char *fmt, ...) { return 0; } static inline void kdb_init(int level) {} static inline int kdb_register(char *cmd, kdb_func_t func, char *usage, char *help, short minlen) { return 0; } -static inline int kdb_register_repeat(char *cmd, kdb_func_t func, char *usage, - char *help, short minlen, - kdb_repeat_t repeat) { return 0; } +static inline int kdb_register_flags(char *cmd, kdb_func_t func, char *usage, + char *help, short minlen, + kdb_cmdflags_t flags) { return 0; } static inline int kdb_unregister(char *cmd) { return 0; } #endif /* CONFIG_KGDB_KDB */ enum { diff --git a/include/linux/libata.h b/include/linux/libata.h index 2d182413b1db..91f705de2c0b 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -231,6 +231,7 @@ enum { ATA_FLAG_SW_ACTIVITY = (1 << 22), /* driver supports sw activity * led */ ATA_FLAG_NO_DIPM = (1 << 23), /* host not happy with DIPM */ + ATA_FLAG_LOWTAG = (1 << 24), /* host wants lowest available tag */ /* bits 24:31 of ap->flags are reserved for LLD specific flags */ @@ -422,6 +423,7 @@ enum { ATA_HORKAGE_NO_NCQ_TRIM = (1 << 19), /* don't use queued TRIM */ ATA_HORKAGE_NOLPM = (1 << 20), /* don't use LPM */ ATA_HORKAGE_WD_BROKEN_LPM = (1 << 21), /* some WDs have broken LPM */ + ATA_HORKAGE_ZERO_AFTER_TRIM = (1 << 22),/* guarantees zero after trim */ /* DMA mask for user DMA control: User visible values; DO NOT renumber */ diff --git a/include/linux/mm.h b/include/linux/mm.h index f80d0194c9bc..80fc92a49649 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -1952,7 +1952,7 @@ extern int expand_downwards(struct vm_area_struct *vma, #if VM_GROWSUP extern int expand_upwards(struct vm_area_struct *vma, unsigned long address); #else - #define expand_upwards(vma, address) do { } while (0) + #define expand_upwards(vma, address) (0) #endif /* Look up the first VMA which satisfies addr < vm_end, NULL if none. */ diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index 375af80bde7d..f767a0de611f 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -137,6 +137,7 @@ struct sdhci_host { #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */ #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */ #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ +#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ unsigned int version; /* SDHCI spec. version */ diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 679e6e90aa4c..52fd8e8694cf 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -852,11 +852,11 @@ typedef u16 (*select_queue_fallback_t)(struct net_device *dev, * 3. Update dev->stats asynchronously and atomically, and define * neither operation. * - * int (*ndo_vlan_rx_add_vid)(struct net_device *dev, __be16 proto, u16t vid); + * int (*ndo_vlan_rx_add_vid)(struct net_device *dev, __be16 proto, u16 vid); * If device support VLAN filtering this function is called when a * VLAN id is registered. * - * int (*ndo_vlan_rx_kill_vid)(struct net_device *dev, unsigned short vid); + * int (*ndo_vlan_rx_kill_vid)(struct net_device *dev, __be16 proto, u16 vid); * If device support VLAN filtering this function is called when a * VLAN id is unregistered. * @@ -2085,7 +2085,7 @@ extern rwlock_t dev_base_lock; /* Device list lock */ list_for_each_entry_continue_rcu(d, &(net)->dev_base_head, dev_list) #define for_each_netdev_in_bond_rcu(bond, slave) \ for_each_netdev_rcu(&init_net, slave) \ - if (netdev_master_upper_dev_get_rcu(slave) == bond) + if (netdev_master_upper_dev_get_rcu(slave) == (bond)) #define net_device_entry(lh) list_entry(lh, struct net_device, dev_list) static inline struct net_device *next_net_device(struct net_device *dev) diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h index 1e37fbb78f7a..ddea982355f3 100644 --- a/include/linux/nfs_fs_sb.h +++ b/include/linux/nfs_fs_sb.h @@ -74,6 +74,9 @@ struct nfs_client { /* idmapper */ struct idmap * cl_idmap; + /* Client owner identifier */ + const char * cl_owner_id; + /* Our own IP address, as a null-terminated string. * This is used to generate the mv0 callback address. */ diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 486e84ccb1f9..4f7a61ca4b39 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -79,11 +79,6 @@ struct perf_branch_stack { struct perf_branch_entry entries[0]; }; -struct perf_regs { - __u64 abi; - struct pt_regs *regs; -}; - struct task_struct; /* @@ -610,7 +605,14 @@ struct perf_sample_data { u32 reserved; } cpu_entry; struct perf_callchain_entry *callchain; + + /* + * regs_user may point to task_pt_regs or to regs_user_copy, depending + * on arch details. + */ struct perf_regs regs_user; + struct pt_regs regs_user_copy; + struct perf_regs regs_intr; u64 stack_user_size; } ____cacheline_aligned; diff --git a/include/linux/perf_regs.h b/include/linux/perf_regs.h index 3c73d5fe18be..a5f98d53d732 100644 --- a/include/linux/perf_regs.h +++ b/include/linux/perf_regs.h @@ -1,11 +1,19 @@ #ifndef _LINUX_PERF_REGS_H #define _LINUX_PERF_REGS_H +struct perf_regs { + __u64 abi; + struct pt_regs *regs; +}; + #ifdef CONFIG_HAVE_PERF_REGS #include <asm/perf_regs.h> u64 perf_reg_value(struct pt_regs *regs, int idx); int perf_reg_validate(u64 mask); u64 perf_reg_abi(struct task_struct *task); +void perf_get_regs_user(struct perf_regs *regs_user, + struct pt_regs *regs, + struct pt_regs *regs_user_copy); #else static inline u64 perf_reg_value(struct pt_regs *regs, int idx) { @@ -21,5 +29,13 @@ static inline u64 perf_reg_abi(struct task_struct *task) { return PERF_SAMPLE_REGS_ABI_NONE; } + +static inline void perf_get_regs_user(struct perf_regs *regs_user, + struct pt_regs *regs, + struct pt_regs *regs_user_copy) +{ + regs_user->regs = task_pt_regs(current); + regs_user->abi = perf_reg_abi(current); +} #endif /* CONFIG_HAVE_PERF_REGS */ #endif /* _LINUX_PERF_REGS_H */ diff --git a/include/linux/phy/omap_control_phy.h b/include/linux/phy/omap_control_phy.h index e9e6cfbfbb58..eb7d4a135a9e 100644 --- a/include/linux/phy/omap_control_phy.h +++ b/include/linux/phy/omap_control_phy.h @@ -66,7 +66,7 @@ enum omap_control_usb_mode { #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 #define OMAP_CTRL_PCIE_PCS_MASK 0xff -#define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT 0x8 +#define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT 16 #define OMAP_CTRL_USB2_PHY_PD BIT(28) @@ -79,7 +79,7 @@ enum omap_control_usb_mode { void omap_control_phy_power(struct device *dev, int on); void omap_control_usb_set_mode(struct device *dev, enum omap_control_usb_mode mode); -void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay); +void omap_control_pcie_pcs(struct device *dev, u8 delay); #else static inline void omap_control_phy_power(struct device *dev, int on) @@ -91,7 +91,7 @@ static inline void omap_control_usb_set_mode(struct device *dev, { } -static inline void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay) +static inline void omap_control_pcie_pcs(struct device *dev, u8 delay) { } #endif diff --git a/include/linux/rmap.h b/include/linux/rmap.h index c0c2bce6b0b7..d9d7e7e56352 100644 --- a/include/linux/rmap.h +++ b/include/linux/rmap.h @@ -37,6 +37,16 @@ struct anon_vma { atomic_t refcount; /* + * Count of child anon_vmas and VMAs which points to this anon_vma. + * + * This counter is used for making decision about reusing anon_vma + * instead of forking new one. See comments in function anon_vma_clone. + */ + unsigned degree; + + struct anon_vma *parent; /* Parent of this anon_vma */ + + /* * NOTE: the LSB of the rb_root.rb_node is set by * mm_take_all_locks() _after_ taking the above lock. So the * rb_root must only be read/written after taking the above lock diff --git a/include/linux/writeback.h b/include/linux/writeback.h index a219be961c0a..00048339c23e 100644 --- a/include/linux/writeback.h +++ b/include/linux/writeback.h @@ -177,7 +177,6 @@ int write_cache_pages(struct address_space *mapping, struct writeback_control *wbc, writepage_t writepage, void *data); int do_writepages(struct address_space *mapping, struct writeback_control *wbc); -void set_page_dirty_balance(struct page *page); void writeback_set_ratelimit(void); void tag_pages_for_writeback(struct address_space *mapping, pgoff_t start, pgoff_t end); diff --git a/include/net/genetlink.h b/include/net/genetlink.h index 84125088c309..6c92415311ca 100644 --- a/include/net/genetlink.h +++ b/include/net/genetlink.h @@ -27,13 +27,18 @@ struct genl_info; * @maxattr: maximum number of attributes supported * @netnsok: set to true if the family can handle network * namespaces and should be presented in all of them + * @parallel_ops: operations can be called in parallel and aren't + * synchronized by the core genetlink code * @pre_doit: called before an operation's doit callback, it may * do additional, common, filtering and return an error * @post_doit: called after an operation's doit callback, it may * undo operations done by pre_doit, for example release locks * @mcast_bind: a socket bound to the given multicast group (which * is given as the offset into the groups array) - * @mcast_unbind: a socket was unbound from the given multicast group + * @mcast_unbind: a socket was unbound from the given multicast group. + * Note that unbind() will not be called symmetrically if the + * generic netlink family is removed while there are still open + * sockets. * @attrbuf: buffer to store parsed attributes * @family_list: family list * @mcgrps: multicast groups used by this family (private) diff --git a/include/net/mac80211.h b/include/net/mac80211.h index 58d719ddaa60..29c7be8808d5 100644 --- a/include/net/mac80211.h +++ b/include/net/mac80211.h @@ -1270,8 +1270,7 @@ struct ieee80211_vif *wdev_to_ieee80211_vif(struct wireless_dev *wdev); * * @IEEE80211_KEY_FLAG_GENERATE_IV: This flag should be set by the * driver to indicate that it requires IV generation for this - * particular key. Setting this flag does not necessarily mean that SKBs - * will have sufficient tailroom for ICV or MIC. + * particular key. * @IEEE80211_KEY_FLAG_GENERATE_MMIC: This flag should be set by * the driver for a TKIP key if it requires Michael MIC * generation in software. @@ -1283,9 +1282,7 @@ struct ieee80211_vif *wdev_to_ieee80211_vif(struct wireless_dev *wdev); * @IEEE80211_KEY_FLAG_PUT_IV_SPACE: This flag should be set by the driver * if space should be prepared for the IV, but the IV * itself should not be generated. Do not set together with - * @IEEE80211_KEY_FLAG_GENERATE_IV on the same key. Setting this flag does - * not necessarily mean that SKBs will have sufficient tailroom for ICV or - * MIC. + * @IEEE80211_KEY_FLAG_GENERATE_IV on the same key. * @IEEE80211_KEY_FLAG_RX_MGMT: This key will be used to decrypt received * management frames. The flag can help drivers that have a hardware * crypto implementation that doesn't deal with management frames diff --git a/include/target/target_core_backend.h b/include/target/target_core_backend.h index 430cfaf92285..db81c65b8f48 100644 --- a/include/target/target_core_backend.h +++ b/include/target/target_core_backend.h @@ -135,7 +135,6 @@ int se_dev_set_is_nonrot(struct se_device *, int); int se_dev_set_emulate_rest_reord(struct se_device *dev, int); int se_dev_set_queue_depth(struct se_device *, u32); int se_dev_set_max_sectors(struct se_device *, u32); -int se_dev_set_fabric_max_sectors(struct se_device *, u32); int se_dev_set_optimal_sectors(struct se_device *, u32); int se_dev_set_block_size(struct se_device *, u32); diff --git a/include/target/target_core_backend_configfs.h b/include/target/target_core_backend_configfs.h index 3247d7530107..186f7a923570 100644 --- a/include/target/target_core_backend_configfs.h +++ b/include/target/target_core_backend_configfs.h @@ -98,8 +98,6 @@ static struct target_backend_dev_attrib_attribute _backend##_dev_attrib_##_name TB_DEV_ATTR(_backend, block_size, S_IRUGO | S_IWUSR); \ DEF_TB_DEV_ATTRIB_RO(_backend, hw_max_sectors); \ TB_DEV_ATTR_RO(_backend, hw_max_sectors); \ - DEF_TB_DEV_ATTRIB(_backend, fabric_max_sectors); \ - TB_DEV_ATTR(_backend, fabric_max_sectors, S_IRUGO | S_IWUSR); \ DEF_TB_DEV_ATTRIB(_backend, optimal_sectors); \ TB_DEV_ATTR(_backend, optimal_sectors, S_IRUGO | S_IWUSR); \ DEF_TB_DEV_ATTRIB_RO(_backend, hw_queue_depth); \ diff --git a/include/target/target_core_base.h b/include/target/target_core_base.h index 397fb635766a..4a8795a87b9e 100644 --- a/include/target/target_core_base.h +++ b/include/target/target_core_base.h @@ -77,8 +77,6 @@ #define DA_UNMAP_GRANULARITY_ALIGNMENT_DEFAULT 0 /* Default max_write_same_len, disabled by default */ #define DA_MAX_WRITE_SAME_LEN 0 -/* Default max transfer length */ -#define DA_FABRIC_MAX_SECTORS 8192 /* Use a model alias based on the configfs backend device name */ #define DA_EMULATE_MODEL_ALIAS 0 /* Emulation for Direct Page Out */ @@ -694,7 +692,6 @@ struct se_dev_attrib { u32 hw_block_size; u32 block_size; u32 hw_max_sectors; - u32 fabric_max_sectors; u32 optimal_sectors; u32 hw_queue_depth; u32 queue_depth; diff --git a/include/uapi/asm-generic/fcntl.h b/include/uapi/asm-generic/fcntl.h index 7543b3e51331..e063effe0cc1 100644 --- a/include/uapi/asm-generic/fcntl.h +++ b/include/uapi/asm-generic/fcntl.h @@ -5,7 +5,7 @@ /* * FMODE_EXEC is 0x20 - * FMODE_NONOTIFY is 0x1000000 + * FMODE_NONOTIFY is 0x4000000 * These cannot be used by userspace O_* until internal and external open * flags are split. * -Eric Paris diff --git a/include/uapi/linux/can/netlink.h b/include/uapi/linux/can/netlink.h index 3e4323a3918d..94ffe0c83ce7 100644 --- a/include/uapi/linux/can/netlink.h +++ b/include/uapi/linux/can/netlink.h @@ -98,6 +98,7 @@ struct can_ctrlmode { #define CAN_CTRLMODE_BERR_REPORTING 0x10 /* Bus-error reporting */ #define CAN_CTRLMODE_FD 0x20 /* CAN FD mode */ #define CAN_CTRLMODE_PRESUME_ACK 0x40 /* Ignore missing CAN ACKs */ +#define CAN_CTRLMODE_FD_NON_ISO 0x80 /* CAN FD in non-ISO mode */ /* * CAN device statistics diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 7acef41fc209..af94f31e33ac 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -128,27 +128,34 @@ struct kfd_ioctl_get_process_apertures_args { uint32_t pad; }; -#define KFD_IOC_MAGIC 'K' +#define AMDKFD_IOCTL_BASE 'K' +#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) +#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) +#define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) +#define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) -#define KFD_IOC_GET_VERSION \ - _IOR(KFD_IOC_MAGIC, 1, struct kfd_ioctl_get_version_args) +#define AMDKFD_IOC_GET_VERSION \ + AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) -#define KFD_IOC_CREATE_QUEUE \ - _IOWR(KFD_IOC_MAGIC, 2, struct kfd_ioctl_create_queue_args) +#define AMDKFD_IOC_CREATE_QUEUE \ + AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) -#define KFD_IOC_DESTROY_QUEUE \ - _IOWR(KFD_IOC_MAGIC, 3, struct kfd_ioctl_destroy_queue_args) +#define AMDKFD_IOC_DESTROY_QUEUE \ + AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) -#define KFD_IOC_SET_MEMORY_POLICY \ - _IOW(KFD_IOC_MAGIC, 4, struct kfd_ioctl_set_memory_policy_args) +#define AMDKFD_IOC_SET_MEMORY_POLICY \ + AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) -#define KFD_IOC_GET_CLOCK_COUNTERS \ - _IOWR(KFD_IOC_MAGIC, 5, struct kfd_ioctl_get_clock_counters_args) +#define AMDKFD_IOC_GET_CLOCK_COUNTERS \ + AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) -#define KFD_IOC_GET_PROCESS_APERTURES \ - _IOR(KFD_IOC_MAGIC, 6, struct kfd_ioctl_get_process_apertures_args) +#define AMDKFD_IOC_GET_PROCESS_APERTURES \ + AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) -#define KFD_IOC_UPDATE_QUEUE \ - _IOW(KFD_IOC_MAGIC, 7, struct kfd_ioctl_update_queue_args) +#define AMDKFD_IOC_UPDATE_QUEUE \ + AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) + +#define AMDKFD_COMMAND_START 0x01 +#define AMDKFD_COMMAND_END 0x08 #endif diff --git a/include/uapi/linux/openvswitch.h b/include/uapi/linux/openvswitch.h index 3a6dcaa359b7..f714e8633352 100644 --- a/include/uapi/linux/openvswitch.h +++ b/include/uapi/linux/openvswitch.h @@ -174,6 +174,10 @@ enum ovs_packet_attr { OVS_PACKET_ATTR_USERDATA, /* OVS_ACTION_ATTR_USERSPACE arg. */ OVS_PACKET_ATTR_EGRESS_TUN_KEY, /* Nested OVS_TUNNEL_KEY_ATTR_* attributes. */ + OVS_PACKET_ATTR_UNUSED1, + OVS_PACKET_ATTR_UNUSED2, + OVS_PACKET_ATTR_PROBE, /* Packet operation is a feature probe, + error logging should be suppressed. */ __OVS_PACKET_ATTR_MAX }; diff --git a/include/uapi/linux/uinput.h b/include/uapi/linux/uinput.h index baeab83deb64..013c9d8db372 100644 --- a/include/uapi/linux/uinput.h +++ b/include/uapi/linux/uinput.h @@ -82,7 +82,7 @@ struct uinput_ff_erase { * The complete sysfs path is then /sys/devices/virtual/input/--NAME-- * Usually, it is in the form "inputN" */ -#define UI_GET_SYSNAME(len) _IOC(_IOC_READ, UINPUT_IOCTL_BASE, 300, len) +#define UI_GET_SYSNAME(len) _IOC(_IOC_READ, UINPUT_IOCTL_BASE, 44, len) /** * UI_GET_VERSION - Return version of uinput protocol @@ -91,7 +91,7 @@ struct uinput_ff_erase { * the integer pointed to by the ioctl argument. The protocol version * is hard-coded in the kernel and is independent of the uinput device. */ -#define UI_GET_VERSION _IOR(UINPUT_IOCTL_BASE, 301, unsigned int) +#define UI_GET_VERSION _IOR(UINPUT_IOCTL_BASE, 45, unsigned int) /* * To write a force-feedback-capable driver, the upload_effect diff --git a/include/xen/interface/nmi.h b/include/xen/interface/nmi.h new file mode 100644 index 000000000000..b47d9d06fade --- /dev/null +++ b/include/xen/interface/nmi.h @@ -0,0 +1,51 @@ +/****************************************************************************** + * nmi.h + * + * NMI callback registration and reason codes. + * + * Copyright (c) 2005, Keir Fraser <keir@xensource.com> + */ + +#ifndef __XEN_PUBLIC_NMI_H__ +#define __XEN_PUBLIC_NMI_H__ + +#include <xen/interface/xen.h> + +/* + * NMI reason codes: + * Currently these are x86-specific, stored in arch_shared_info.nmi_reason. + */ + /* I/O-check error reported via ISA port 0x61, bit 6. */ +#define _XEN_NMIREASON_io_error 0 +#define XEN_NMIREASON_io_error (1UL << _XEN_NMIREASON_io_error) + /* PCI SERR reported via ISA port 0x61, bit 7. */ +#define _XEN_NMIREASON_pci_serr 1 +#define XEN_NMIREASON_pci_serr (1UL << _XEN_NMIREASON_pci_serr) + /* Unknown hardware-generated NMI. */ +#define _XEN_NMIREASON_unknown 2 +#define XEN_NMIREASON_unknown (1UL << _XEN_NMIREASON_unknown) + +/* + * long nmi_op(unsigned int cmd, void *arg) + * NB. All ops return zero on success, else a negative error code. + */ + +/* + * Register NMI callback for this (calling) VCPU. Currently this only makes + * sense for domain 0, vcpu 0. All other callers will be returned EINVAL. + * arg == pointer to xennmi_callback structure. + */ +#define XENNMI_register_callback 0 +struct xennmi_callback { + unsigned long handler_address; + unsigned long pad; +}; +DEFINE_GUEST_HANDLE_STRUCT(xennmi_callback); + +/* + * Deregister NMI callback for this (calling) VCPU. + * arg == NULL. + */ +#define XENNMI_unregister_callback 1 + +#endif /* __XEN_PUBLIC_NMI_H__ */ diff --git a/kernel/debug/debug_core.c b/kernel/debug/debug_core.c index 1adf62b39b96..07ce18ca71e0 100644 --- a/kernel/debug/debug_core.c +++ b/kernel/debug/debug_core.c @@ -27,6 +27,9 @@ * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ + +#define pr_fmt(fmt) "KGDB: " fmt + #include <linux/pid_namespace.h> #include <linux/clocksource.h> #include <linux/serial_core.h> @@ -196,8 +199,8 @@ int __weak kgdb_validate_break_address(unsigned long addr) return err; err = kgdb_arch_remove_breakpoint(&tmp); if (err) - printk(KERN_ERR "KGDB: Critical breakpoint error, kernel " - "memory destroyed at: %lx", addr); + pr_err("Critical breakpoint error, kernel memory destroyed at: %lx\n", + addr); return err; } @@ -256,8 +259,8 @@ int dbg_activate_sw_breakpoints(void) error = kgdb_arch_set_breakpoint(&kgdb_break[i]); if (error) { ret = error; - printk(KERN_INFO "KGDB: BP install failed: %lx", - kgdb_break[i].bpt_addr); + pr_info("BP install failed: %lx\n", + kgdb_break[i].bpt_addr); continue; } @@ -319,8 +322,8 @@ int dbg_deactivate_sw_breakpoints(void) continue; error = kgdb_arch_remove_breakpoint(&kgdb_break[i]); if (error) { - printk(KERN_INFO "KGDB: BP remove failed: %lx\n", - kgdb_break[i].bpt_addr); + pr_info("BP remove failed: %lx\n", + kgdb_break[i].bpt_addr); ret = error; } @@ -367,7 +370,7 @@ int dbg_remove_all_break(void) goto setundefined; error = kgdb_arch_remove_breakpoint(&kgdb_break[i]); if (error) - printk(KERN_ERR "KGDB: breakpoint remove failed: %lx\n", + pr_err("breakpoint remove failed: %lx\n", kgdb_break[i].bpt_addr); setundefined: kgdb_break[i].state = BP_UNDEFINED; @@ -400,9 +403,9 @@ static int kgdb_io_ready(int print_wait) if (print_wait) { #ifdef CONFIG_KGDB_KDB if (!dbg_kdb_mode) - printk(KERN_CRIT "KGDB: waiting... or $3#33 for KDB\n"); + pr_crit("waiting... or $3#33 for KDB\n"); #else - printk(KERN_CRIT "KGDB: Waiting for remote debugger\n"); + pr_crit("Waiting for remote debugger\n"); #endif } return 1; @@ -430,8 +433,7 @@ static int kgdb_reenter_check(struct kgdb_state *ks) exception_level = 0; kgdb_skipexception(ks->ex_vector, ks->linux_regs); dbg_activate_sw_breakpoints(); - printk(KERN_CRIT "KGDB: re-enter error: breakpoint removed %lx\n", - addr); + pr_crit("re-enter error: breakpoint removed %lx\n", addr); WARN_ON_ONCE(1); return 1; @@ -444,7 +446,7 @@ static int kgdb_reenter_check(struct kgdb_state *ks) panic("Recursive entry to debugger"); } - printk(KERN_CRIT "KGDB: re-enter exception: ALL breakpoints killed\n"); + pr_crit("re-enter exception: ALL breakpoints killed\n"); #ifdef CONFIG_KGDB_KDB /* Allow kdb to debug itself one level */ return 0; @@ -471,6 +473,7 @@ static int kgdb_cpu_enter(struct kgdb_state *ks, struct pt_regs *regs, int cpu; int trace_on = 0; int online_cpus = num_online_cpus(); + u64 time_left; kgdb_info[ks->cpu].enter_kgdb++; kgdb_info[ks->cpu].exception_state |= exception_state; @@ -595,9 +598,13 @@ return_normal: /* * Wait for the other CPUs to be notified and be waiting for us: */ - while (kgdb_do_roundup && (atomic_read(&masters_in_kgdb) + - atomic_read(&slaves_in_kgdb)) != online_cpus) + time_left = loops_per_jiffy * HZ; + while (kgdb_do_roundup && --time_left && + (atomic_read(&masters_in_kgdb) + atomic_read(&slaves_in_kgdb)) != + online_cpus) cpu_relax(); + if (!time_left) + pr_crit("KGDB: Timed out waiting for secondary CPUs.\n"); /* * At this point the primary processor is completely @@ -795,15 +802,15 @@ static struct console kgdbcons = { static void sysrq_handle_dbg(int key) { if (!dbg_io_ops) { - printk(KERN_CRIT "ERROR: No KGDB I/O module available\n"); + pr_crit("ERROR: No KGDB I/O module available\n"); return; } if (!kgdb_connected) { #ifdef CONFIG_KGDB_KDB if (!dbg_kdb_mode) - printk(KERN_CRIT "KGDB or $3#33 for KDB\n"); + pr_crit("KGDB or $3#33 for KDB\n"); #else - printk(KERN_CRIT "Entering KGDB\n"); + pr_crit("Entering KGDB\n"); #endif } @@ -945,7 +952,7 @@ static void kgdb_initial_breakpoint(void) { kgdb_break_asap = 0; - printk(KERN_CRIT "kgdb: Waiting for connection from remote gdb...\n"); + pr_crit("Waiting for connection from remote gdb...\n"); kgdb_breakpoint(); } @@ -964,8 +971,7 @@ int kgdb_register_io_module(struct kgdb_io *new_dbg_io_ops) if (dbg_io_ops) { spin_unlock(&kgdb_registration_lock); - printk(KERN_ERR "kgdb: Another I/O driver is already " - "registered with KGDB.\n"); + pr_err("Another I/O driver is already registered with KGDB\n"); return -EBUSY; } @@ -981,8 +987,7 @@ int kgdb_register_io_module(struct kgdb_io *new_dbg_io_ops) spin_unlock(&kgdb_registration_lock); - printk(KERN_INFO "kgdb: Registered I/O driver %s.\n", - new_dbg_io_ops->name); + pr_info("Registered I/O driver %s\n", new_dbg_io_ops->name); /* Arm KGDB now. */ kgdb_register_callbacks(); @@ -1017,8 +1022,7 @@ void kgdb_unregister_io_module(struct kgdb_io *old_dbg_io_ops) spin_unlock(&kgdb_registration_lock); - printk(KERN_INFO - "kgdb: Unregistered I/O driver %s, debugger disabled.\n", + pr_info("Unregistered I/O driver %s, debugger disabled\n", old_dbg_io_ops->name); } EXPORT_SYMBOL_GPL(kgdb_unregister_io_module); diff --git a/kernel/debug/kdb/kdb_bp.c b/kernel/debug/kdb/kdb_bp.c index b20d544f20c2..e1dbf4a2c69e 100644 --- a/kernel/debug/kdb/kdb_bp.c +++ b/kernel/debug/kdb/kdb_bp.c @@ -531,22 +531,29 @@ void __init kdb_initbptab(void) for (i = 0, bp = kdb_breakpoints; i < KDB_MAXBPT; i++, bp++) bp->bp_free = 1; - kdb_register_repeat("bp", kdb_bp, "[<vaddr>]", - "Set/Display breakpoints", 0, KDB_REPEAT_NO_ARGS); - kdb_register_repeat("bl", kdb_bp, "[<vaddr>]", - "Display breakpoints", 0, KDB_REPEAT_NO_ARGS); + kdb_register_flags("bp", kdb_bp, "[<vaddr>]", + "Set/Display breakpoints", 0, + KDB_ENABLE_FLOW_CTRL | KDB_REPEAT_NO_ARGS); + kdb_register_flags("bl", kdb_bp, "[<vaddr>]", + "Display breakpoints", 0, + KDB_ENABLE_FLOW_CTRL | KDB_REPEAT_NO_ARGS); if (arch_kgdb_ops.flags & KGDB_HW_BREAKPOINT) - kdb_register_repeat("bph", kdb_bp, "[<vaddr>]", - "[datar [length]|dataw [length]] Set hw brk", 0, KDB_REPEAT_NO_ARGS); - kdb_register_repeat("bc", kdb_bc, "<bpnum>", - "Clear Breakpoint", 0, KDB_REPEAT_NONE); - kdb_register_repeat("be", kdb_bc, "<bpnum>", - "Enable Breakpoint", 0, KDB_REPEAT_NONE); - kdb_register_repeat("bd", kdb_bc, "<bpnum>", - "Disable Breakpoint", 0, KDB_REPEAT_NONE); - - kdb_register_repeat("ss", kdb_ss, "", - "Single Step", 1, KDB_REPEAT_NO_ARGS); + kdb_register_flags("bph", kdb_bp, "[<vaddr>]", + "[datar [length]|dataw [length]] Set hw brk", 0, + KDB_ENABLE_FLOW_CTRL | KDB_REPEAT_NO_ARGS); + kdb_register_flags("bc", kdb_bc, "<bpnum>", + "Clear Breakpoint", 0, + KDB_ENABLE_FLOW_CTRL); + kdb_register_flags("be", kdb_bc, "<bpnum>", + "Enable Breakpoint", 0, + KDB_ENABLE_FLOW_CTRL); + kdb_register_flags("bd", kdb_bc, "<bpnum>", + "Disable Breakpoint", 0, + KDB_ENABLE_FLOW_CTRL); + + kdb_register_flags("ss", kdb_ss, "", + "Single Step", 1, + KDB_ENABLE_FLOW_CTRL | KDB_REPEAT_NO_ARGS); /* * Architecture dependent initialization. */ diff --git a/kernel/debug/kdb/kdb_debugger.c b/kernel/debug/kdb/kdb_debugger.c index 8859ca34dcfe..15e1a7af5dd0 100644 --- a/kernel/debug/kdb/kdb_debugger.c +++ b/kernel/debug/kdb/kdb_debugger.c @@ -129,6 +129,10 @@ int kdb_stub(struct kgdb_state *ks) ks->pass_exception = 1; KDB_FLAG_SET(CATASTROPHIC); } + /* set CATASTROPHIC if the system contains unresponsive processors */ + for_each_online_cpu(i) + if (!kgdb_info[i].enter_kgdb) + KDB_FLAG_SET(CATASTROPHIC); if (KDB_STATE(SSBPT) && reason == KDB_REASON_SSTEP) { KDB_STATE_CLEAR(SSBPT); KDB_STATE_CLEAR(DOING_SS); diff --git a/kernel/debug/kdb/kdb_main.c b/kernel/debug/kdb/kdb_main.c index 379650b984f8..f191bddf64b8 100644 --- a/kernel/debug/kdb/kdb_main.c +++ b/kernel/debug/kdb/kdb_main.c @@ -12,6 +12,7 @@ */ #include <linux/ctype.h> +#include <linux/types.h> #include <linux/string.h> #include <linux/kernel.h> #include <linux/kmsg_dump.h> @@ -23,6 +24,7 @@ #include <linux/vmalloc.h> #include <linux/atomic.h> #include <linux/module.h> +#include <linux/moduleparam.h> #include <linux/mm.h> #include <linux/init.h> #include <linux/kallsyms.h> @@ -42,6 +44,12 @@ #include <linux/slab.h> #include "kdb_private.h" +#undef MODULE_PARAM_PREFIX +#define MODULE_PARAM_PREFIX "kdb." + +static int kdb_cmd_enabled = CONFIG_KDB_DEFAULT_ENABLE; +module_param_named(cmd_enable, kdb_cmd_enabled, int, 0600); + #define GREP_LEN 256 char kdb_grep_string[GREP_LEN]; int kdb_grepping_flag; @@ -121,6 +129,7 @@ static kdbmsg_t kdbmsgs[] = { KDBMSG(BADLENGTH, "Invalid length field"), KDBMSG(NOBP, "No Breakpoint exists"), KDBMSG(BADADDR, "Invalid address"), + KDBMSG(NOPERM, "Permission denied"), }; #undef KDBMSG @@ -188,6 +197,26 @@ struct task_struct *kdb_curr_task(int cpu) } /* + * Check whether the flags of the current command and the permissions + * of the kdb console has allow a command to be run. + */ +static inline bool kdb_check_flags(kdb_cmdflags_t flags, int permissions, + bool no_args) +{ + /* permissions comes from userspace so needs massaging slightly */ + permissions &= KDB_ENABLE_MASK; + permissions |= KDB_ENABLE_ALWAYS_SAFE; + + /* some commands change group when launched with no arguments */ + if (no_args) + permissions |= permissions << KDB_ENABLE_NO_ARGS_SHIFT; + + flags |= KDB_ENABLE_ALL; + + return permissions & flags; +} + +/* * kdbgetenv - This function will return the character string value of * an environment variable. * Parameters: @@ -476,6 +505,15 @@ int kdbgetaddrarg(int argc, const char **argv, int *nextarg, kdb_symtab_t symtab; /* + * If the enable flags prohibit both arbitrary memory access + * and flow control then there are no reasonable grounds to + * provide symbol lookup. + */ + if (!kdb_check_flags(KDB_ENABLE_MEM_READ | KDB_ENABLE_FLOW_CTRL, + kdb_cmd_enabled, false)) + return KDB_NOPERM; + + /* * Process arguments which follow the following syntax: * * symbol | numeric-address [+/- numeric-offset] @@ -641,8 +679,13 @@ static int kdb_defcmd2(const char *cmdstr, const char *argv0) if (!s->count) s->usable = 0; if (s->usable) - kdb_register(s->name, kdb_exec_defcmd, - s->usage, s->help, 0); + /* macros are always safe because when executed each + * internal command re-enters kdb_parse() and is + * safety checked individually. + */ + kdb_register_flags(s->name, kdb_exec_defcmd, s->usage, + s->help, 0, + KDB_ENABLE_ALWAYS_SAFE); return 0; } if (!s->usable) @@ -1003,25 +1046,22 @@ int kdb_parse(const char *cmdstr) if (i < kdb_max_commands) { int result; + + if (!kdb_check_flags(tp->cmd_flags, kdb_cmd_enabled, argc <= 1)) + return KDB_NOPERM; + KDB_STATE_SET(CMD); result = (*tp->cmd_func)(argc-1, (const char **)argv); if (result && ignore_errors && result > KDB_CMD_GO) result = 0; KDB_STATE_CLEAR(CMD); - switch (tp->cmd_repeat) { - case KDB_REPEAT_NONE: - argc = 0; - if (argv[0]) - *(argv[0]) = '\0'; - break; - case KDB_REPEAT_NO_ARGS: - argc = 1; - if (argv[1]) - *(argv[1]) = '\0'; - break; - case KDB_REPEAT_WITH_ARGS: - break; - } + + if (tp->cmd_flags & KDB_REPEAT_WITH_ARGS) + return result; + + argc = tp->cmd_flags & KDB_REPEAT_NO_ARGS ? 1 : 0; + if (argv[argc]) + *(argv[argc]) = '\0'; return result; } @@ -1921,10 +1961,14 @@ static int kdb_rm(int argc, const char **argv) */ static int kdb_sr(int argc, const char **argv) { + bool check_mask = + !kdb_check_flags(KDB_ENABLE_ALL, kdb_cmd_enabled, false); + if (argc != 1) return KDB_ARGCOUNT; + kdb_trap_printk++; - __handle_sysrq(*argv[1], false); + __handle_sysrq(*argv[1], check_mask); kdb_trap_printk--; return 0; @@ -2157,6 +2201,8 @@ static void kdb_cpu_status(void) for (start_cpu = -1, i = 0; i < NR_CPUS; i++) { if (!cpu_online(i)) { state = 'F'; /* cpu is offline */ + } else if (!kgdb_info[i].enter_kgdb) { + state = 'D'; /* cpu is online but unresponsive */ } else { state = ' '; /* cpu is responding to kdb */ if (kdb_task_state_char(KDB_TSK(i)) == 'I') @@ -2210,7 +2256,7 @@ static int kdb_cpu(int argc, const char **argv) /* * Validate cpunum */ - if ((cpunum > NR_CPUS) || !cpu_online(cpunum)) + if ((cpunum > NR_CPUS) || !kgdb_info[cpunum].enter_kgdb) return KDB_BADCPUNUM; dbg_switch_cpu = cpunum; @@ -2375,6 +2421,8 @@ static int kdb_help(int argc, const char **argv) return 0; if (!kt->cmd_name) continue; + if (!kdb_check_flags(kt->cmd_flags, kdb_cmd_enabled, true)) + continue; if (strlen(kt->cmd_usage) > 20) space = "\n "; kdb_printf("%-15.15s %-20s%s%s\n", kt->cmd_name, @@ -2629,7 +2677,7 @@ static int kdb_grep_help(int argc, const char **argv) } /* - * kdb_register_repeat - This function is used to register a kernel + * kdb_register_flags - This function is used to register a kernel * debugger command. * Inputs: * cmd Command name @@ -2641,12 +2689,12 @@ static int kdb_grep_help(int argc, const char **argv) * zero for success, one if a duplicate command. */ #define kdb_command_extend 50 /* arbitrary */ -int kdb_register_repeat(char *cmd, - kdb_func_t func, - char *usage, - char *help, - short minlen, - kdb_repeat_t repeat) +int kdb_register_flags(char *cmd, + kdb_func_t func, + char *usage, + char *help, + short minlen, + kdb_cmdflags_t flags) { int i; kdbtab_t *kp; @@ -2694,19 +2742,18 @@ int kdb_register_repeat(char *cmd, kp->cmd_func = func; kp->cmd_usage = usage; kp->cmd_help = help; - kp->cmd_flags = 0; kp->cmd_minlen = minlen; - kp->cmd_repeat = repeat; + kp->cmd_flags = flags; return 0; } -EXPORT_SYMBOL_GPL(kdb_register_repeat); +EXPORT_SYMBOL_GPL(kdb_register_flags); /* * kdb_register - Compatibility register function for commands that do * not need to specify a repeat state. Equivalent to - * kdb_register_repeat with KDB_REPEAT_NONE. + * kdb_register_flags with flags set to 0. * Inputs: * cmd Command name * func Function to execute the command @@ -2721,8 +2768,7 @@ int kdb_register(char *cmd, char *help, short minlen) { - return kdb_register_repeat(cmd, func, usage, help, minlen, - KDB_REPEAT_NONE); + return kdb_register_flags(cmd, func, usage, help, minlen, 0); } EXPORT_SYMBOL_GPL(kdb_register); @@ -2764,80 +2810,109 @@ static void __init kdb_inittab(void) for_each_kdbcmd(kp, i) kp->cmd_name = NULL; - kdb_register_repeat("md", kdb_md, "<vaddr>", + kdb_register_flags("md", kdb_md, "<vaddr>", "Display Memory Contents, also mdWcN, e.g. md8c1", 1, - KDB_REPEAT_NO_ARGS); - kdb_register_repeat("mdr", kdb_md, "<vaddr> <bytes>", - "Display Raw Memory", 0, KDB_REPEAT_NO_ARGS); - kdb_register_repeat("mdp", kdb_md, "<paddr> <bytes>", - "Display Physical Memory", 0, KDB_REPEAT_NO_ARGS); - kdb_register_repeat("mds", kdb_md, "<vaddr>", - "Display Memory Symbolically", 0, KDB_REPEAT_NO_ARGS); - kdb_register_repeat("mm", kdb_mm, "<vaddr> <contents>", - "Modify Memory Contents", 0, KDB_REPEAT_NO_ARGS); - kdb_register_repeat("go", kdb_go, "[<vaddr>]", - "Continue Execution", 1, KDB_REPEAT_NONE); - kdb_register_repeat("rd", kdb_rd, "", - "Display Registers", 0, KDB_REPEAT_NONE); - kdb_register_repeat("rm", kdb_rm, "<reg> <contents>", - "Modify Registers", 0, KDB_REPEAT_NONE); - kdb_register_repeat("ef", kdb_ef, "<vaddr>", - "Display exception frame", 0, KDB_REPEAT_NONE); - kdb_register_repeat("bt", kdb_bt, "[<vaddr>]", - "Stack traceback", 1, KDB_REPEAT_NONE); - kdb_register_repeat("btp", kdb_bt, "<pid>", - "Display stack for process <pid>", 0, KDB_REPEAT_NONE); - kdb_register_repeat("bta", kdb_bt, "[D|R|S|T|C|Z|E|U|I|M|A]", - "Backtrace all processes matching state flag", 0, KDB_REPEAT_NONE); - kdb_register_repeat("btc", kdb_bt, "", - "Backtrace current process on each cpu", 0, KDB_REPEAT_NONE); - kdb_register_repeat("btt", kdb_bt, "<vaddr>", + KDB_ENABLE_MEM_READ | KDB_REPEAT_NO_ARGS); + kdb_register_flags("mdr", kdb_md, "<vaddr> <bytes>", + "Display Raw Memory", 0, + KDB_ENABLE_MEM_READ | KDB_REPEAT_NO_ARGS); + kdb_register_flags("mdp", kdb_md, "<paddr> <bytes>", + "Display Physical Memory", 0, + KDB_ENABLE_MEM_READ | KDB_REPEAT_NO_ARGS); + kdb_register_flags("mds", kdb_md, "<vaddr>", + "Display Memory Symbolically", 0, + KDB_ENABLE_MEM_READ | KDB_REPEAT_NO_ARGS); + kdb_register_flags("mm", kdb_mm, "<vaddr> <contents>", + "Modify Memory Contents", 0, + KDB_ENABLE_MEM_WRITE | KDB_REPEAT_NO_ARGS); + kdb_register_flags("go", kdb_go, "[<vaddr>]", + "Continue Execution", 1, + KDB_ENABLE_REG_WRITE | KDB_ENABLE_ALWAYS_SAFE_NO_ARGS); + kdb_register_flags("rd", kdb_rd, "", + "Display Registers", 0, + KDB_ENABLE_REG_READ); + kdb_register_flags("rm", kdb_rm, "<reg> <contents>", + "Modify Registers", 0, + KDB_ENABLE_REG_WRITE); + kdb_register_flags("ef", kdb_ef, "<vaddr>", + "Display exception frame", 0, + KDB_ENABLE_MEM_READ); + kdb_register_flags("bt", kdb_bt, "[<vaddr>]", + "Stack traceback", 1, + KDB_ENABLE_MEM_READ | KDB_ENABLE_INSPECT_NO_ARGS); + kdb_register_flags("btp", kdb_bt, "<pid>", + "Display stack for process <pid>", 0, + KDB_ENABLE_INSPECT); + kdb_register_flags("bta", kdb_bt, "[D|R|S|T|C|Z|E|U|I|M|A]", + "Backtrace all processes matching state flag", 0, + KDB_ENABLE_INSPECT); + kdb_register_flags("btc", kdb_bt, "", + "Backtrace current process on each cpu", 0, + KDB_ENABLE_INSPECT); + kdb_register_flags("btt", kdb_bt, "<vaddr>", "Backtrace process given its struct task address", 0, - KDB_REPEAT_NONE); - kdb_register_repeat("env", kdb_env, "", - "Show environment variables", 0, KDB_REPEAT_NONE); - kdb_register_repeat("set", kdb_set, "", - "Set environment variables", 0, KDB_REPEAT_NONE); - kdb_register_repeat("help", kdb_help, "", - "Display Help Message", 1, KDB_REPEAT_NONE); - kdb_register_repeat("?", kdb_help, "", - "Display Help Message", 0, KDB_REPEAT_NONE); - kdb_register_repeat("cpu", kdb_cpu, "<cpunum>", - "Switch to new cpu", 0, KDB_REPEAT_NONE); - kdb_register_repeat("kgdb", kdb_kgdb, "", - "Enter kgdb mode", 0, KDB_REPEAT_NONE); - kdb_register_repeat("ps", kdb_ps, "[<flags>|A]", - "Display active task list", 0, KDB_REPEAT_NONE); - kdb_register_repeat("pid", kdb_pid, "<pidnum>", - "Switch to another task", 0, KDB_REPEAT_NONE); - kdb_register_repeat("reboot", kdb_reboot, "", - "Reboot the machine immediately", 0, KDB_REPEAT_NONE); + KDB_ENABLE_MEM_READ | KDB_ENABLE_INSPECT_NO_ARGS); + kdb_register_flags("env", kdb_env, "", + "Show environment variables", 0, + KDB_ENABLE_ALWAYS_SAFE); + kdb_register_flags("set", kdb_set, "", + "Set environment variables", 0, + KDB_ENABLE_ALWAYS_SAFE); + kdb_register_flags("help", kdb_help, "", + "Display Help Message", 1, + KDB_ENABLE_ALWAYS_SAFE); + kdb_register_flags("?", kdb_help, "", + "Display Help Message", 0, + KDB_ENABLE_ALWAYS_SAFE); + kdb_register_flags("cpu", kdb_cpu, "<cpunum>", + "Switch to new cpu", 0, + KDB_ENABLE_ALWAYS_SAFE_NO_ARGS); + kdb_register_flags("kgdb", kdb_kgdb, "", + "Enter kgdb mode", 0, 0); + kdb_register_flags("ps", kdb_ps, "[<flags>|A]", + "Display active task list", 0, + KDB_ENABLE_INSPECT); + kdb_register_flags("pid", kdb_pid, "<pidnum>", + "Switch to another task", 0, + KDB_ENABLE_INSPECT); + kdb_register_flags("reboot", kdb_reboot, "", + "Reboot the machine immediately", 0, + KDB_ENABLE_REBOOT); #if defined(CONFIG_MODULES) - kdb_register_repeat("lsmod", kdb_lsmod, "", - "List loaded kernel modules", 0, KDB_REPEAT_NONE); + kdb_register_flags("lsmod", kdb_lsmod, "", + "List loaded kernel modules", 0, + KDB_ENABLE_INSPECT); #endif #if defined(CONFIG_MAGIC_SYSRQ) - kdb_register_repeat("sr", kdb_sr, "<key>", - "Magic SysRq key", 0, KDB_REPEAT_NONE); + kdb_register_flags("sr", kdb_sr, "<key>", + "Magic SysRq key", 0, + KDB_ENABLE_ALWAYS_SAFE); #endif #if defined(CONFIG_PRINTK) - kdb_register_repeat("dmesg", kdb_dmesg, "[lines]", - "Display syslog buffer", 0, KDB_REPEAT_NONE); + kdb_register_flags("dmesg", kdb_dmesg, "[lines]", + "Display syslog buffer", 0, + KDB_ENABLE_ALWAYS_SAFE); #endif if (arch_kgdb_ops.enable_nmi) { - kdb_register_repeat("disable_nmi", kdb_disable_nmi, "", - "Disable NMI entry to KDB", 0, KDB_REPEAT_NONE); - } - kdb_register_repeat("defcmd", kdb_defcmd, "name \"usage\" \"help\"", - "Define a set of commands, down to endefcmd", 0, KDB_REPEAT_NONE); - kdb_register_repeat("kill", kdb_kill, "<-signal> <pid>", - "Send a signal to a process", 0, KDB_REPEAT_NONE); - kdb_register_repeat("summary", kdb_summary, "", - "Summarize the system", 4, KDB_REPEAT_NONE); - kdb_register_repeat("per_cpu", kdb_per_cpu, "<sym> [<bytes>] [<cpu>]", - "Display per_cpu variables", 3, KDB_REPEAT_NONE); - kdb_register_repeat("grephelp", kdb_grep_help, "", - "Display help on | grep", 0, KDB_REPEAT_NONE); + kdb_register_flags("disable_nmi", kdb_disable_nmi, "", + "Disable NMI entry to KDB", 0, + KDB_ENABLE_ALWAYS_SAFE); + } + kdb_register_flags("defcmd", kdb_defcmd, "name \"usage\" \"help\"", + "Define a set of commands, down to endefcmd", 0, + KDB_ENABLE_ALWAYS_SAFE); + kdb_register_flags("kill", kdb_kill, "<-signal> <pid>", + "Send a signal to a process", 0, + KDB_ENABLE_SIGNAL); + kdb_register_flags("summary", kdb_summary, "", + "Summarize the system", 4, + KDB_ENABLE_ALWAYS_SAFE); + kdb_register_flags("per_cpu", kdb_per_cpu, "<sym> [<bytes>] [<cpu>]", + "Display per_cpu variables", 3, + KDB_ENABLE_MEM_READ); + kdb_register_flags("grephelp", kdb_grep_help, "", + "Display help on | grep", 0, + KDB_ENABLE_ALWAYS_SAFE); } /* Execute any commands defined in kdb_cmds. */ diff --git a/kernel/debug/kdb/kdb_private.h b/kernel/debug/kdb/kdb_private.h index 7afd3c8c41d5..eaacd1693954 100644 --- a/kernel/debug/kdb/kdb_private.h +++ b/kernel/debug/kdb/kdb_private.h @@ -172,10 +172,9 @@ typedef struct _kdbtab { kdb_func_t cmd_func; /* Function to execute command */ char *cmd_usage; /* Usage String for this command */ char *cmd_help; /* Help message for this command */ - short cmd_flags; /* Parsing flags */ short cmd_minlen; /* Minimum legal # command * chars required */ - kdb_repeat_t cmd_repeat; /* Does command auto repeat on enter? */ + kdb_cmdflags_t cmd_flags; /* Command behaviour flags */ } kdbtab_t; extern int kdb_bt(int, const char **); /* KDB display back trace */ diff --git a/kernel/events/core.c b/kernel/events/core.c index 4c1ee7f2bebc..882f835a0d85 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -4461,18 +4461,14 @@ perf_output_sample_regs(struct perf_output_handle *handle, } static void perf_sample_regs_user(struct perf_regs *regs_user, - struct pt_regs *regs) + struct pt_regs *regs, + struct pt_regs *regs_user_copy) { - if (!user_mode(regs)) { - if (current->mm) - regs = task_pt_regs(current); - else - regs = NULL; - } - - if (regs) { - regs_user->abi = perf_reg_abi(current); + if (user_mode(regs)) { + regs_user->abi = perf_reg_abi(current); regs_user->regs = regs; + } else if (current->mm) { + perf_get_regs_user(regs_user, regs, regs_user_copy); } else { regs_user->abi = PERF_SAMPLE_REGS_ABI_NONE; regs_user->regs = NULL; @@ -4951,7 +4947,8 @@ void perf_prepare_sample(struct perf_event_header *header, } if (sample_type & (PERF_SAMPLE_REGS_USER | PERF_SAMPLE_STACK_USER)) - perf_sample_regs_user(&data->regs_user, regs); + perf_sample_regs_user(&data->regs_user, regs, + &data->regs_user_copy); if (sample_type & PERF_SAMPLE_REGS_USER) { /* regs dump ABI info */ diff --git a/kernel/exit.c b/kernel/exit.c index 1ea4369890a3..6806c55475ee 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -1287,9 +1287,15 @@ static int wait_task_continued(struct wait_opts *wo, struct task_struct *p) static int wait_consider_task(struct wait_opts *wo, int ptrace, struct task_struct *p) { + /* + * We can race with wait_task_zombie() from another thread. + * Ensure that EXIT_ZOMBIE -> EXIT_DEAD/EXIT_TRACE transition + * can't confuse the checks below. + */ + int exit_state = ACCESS_ONCE(p->exit_state); int ret; - if (unlikely(p->exit_state == EXIT_DEAD)) + if (unlikely(exit_state == EXIT_DEAD)) return 0; ret = eligible_child(wo, p); @@ -1310,7 +1316,7 @@ static int wait_consider_task(struct wait_opts *wo, int ptrace, return 0; } - if (unlikely(p->exit_state == EXIT_TRACE)) { + if (unlikely(exit_state == EXIT_TRACE)) { /* * ptrace == 0 means we are the natural parent. In this case * we should clear notask_error, debugger will notify us. @@ -1337,7 +1343,7 @@ static int wait_consider_task(struct wait_opts *wo, int ptrace, } /* slay zombie? */ - if (p->exit_state == EXIT_ZOMBIE) { + if (exit_state == EXIT_ZOMBIE) { /* we don't reap group leaders with subthreads */ if (!delay_group_leader(p)) { /* diff --git a/kernel/locking/mutex-debug.c b/kernel/locking/mutex-debug.c index 5cf6731b98e9..3ef3736002d8 100644 --- a/kernel/locking/mutex-debug.c +++ b/kernel/locking/mutex-debug.c @@ -80,13 +80,13 @@ void debug_mutex_unlock(struct mutex *lock) DEBUG_LOCKS_WARN_ON(lock->owner != current); DEBUG_LOCKS_WARN_ON(!lock->wait_list.prev && !lock->wait_list.next); - mutex_clear_owner(lock); } /* * __mutex_slowpath_needs_to_unlock() is explicitly 0 for debug * mutexes so that we can do it here after we've verified state. */ + mutex_clear_owner(lock); atomic_set(&lock->count, 1); } diff --git a/kernel/range.c b/kernel/range.c index 322ea8e93e4b..82cfc285b046 100644 --- a/kernel/range.c +++ b/kernel/range.c @@ -113,12 +113,12 @@ static int cmp_range(const void *x1, const void *x2) { const struct range *r1 = x1; const struct range *r2 = x2; - s64 start1, start2; - start1 = r1->start; - start2 = r2->start; - - return start1 - start2; + if (r1->start < r2->start) + return -1; + if (r1->start > r2->start) + return 1; + return 0; } int clean_sort_range(struct range *range, int az) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index b5797b78add6..c0accc00566e 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -7113,9 +7113,6 @@ void __init sched_init(void) #ifdef CONFIG_RT_GROUP_SCHED alloc_size += 2 * nr_cpu_ids * sizeof(void **); #endif -#ifdef CONFIG_CPUMASK_OFFSTACK - alloc_size += num_possible_cpus() * cpumask_size(); -#endif if (alloc_size) { ptr = (unsigned long)kzalloc(alloc_size, GFP_NOWAIT); @@ -7135,13 +7132,13 @@ void __init sched_init(void) ptr += nr_cpu_ids * sizeof(void **); #endif /* CONFIG_RT_GROUP_SCHED */ + } #ifdef CONFIG_CPUMASK_OFFSTACK - for_each_possible_cpu(i) { - per_cpu(load_balance_mask, i) = (void *)ptr; - ptr += cpumask_size(); - } -#endif /* CONFIG_CPUMASK_OFFSTACK */ + for_each_possible_cpu(i) { + per_cpu(load_balance_mask, i) = (cpumask_var_t)kzalloc_node( + cpumask_size(), GFP_KERNEL, cpu_to_node(i)); } +#endif /* CONFIG_CPUMASK_OFFSTACK */ init_rt_bandwidth(&def_rt_bandwidth, global_rt_period(), global_rt_runtime()); diff --git a/kernel/sched/deadline.c b/kernel/sched/deadline.c index e5db8c6feebd..b52092f2636d 100644 --- a/kernel/sched/deadline.c +++ b/kernel/sched/deadline.c @@ -570,24 +570,7 @@ void init_dl_task_timer(struct sched_dl_entity *dl_se) static int dl_runtime_exceeded(struct rq *rq, struct sched_dl_entity *dl_se) { - int dmiss = dl_time_before(dl_se->deadline, rq_clock(rq)); - int rorun = dl_se->runtime <= 0; - - if (!rorun && !dmiss) - return 0; - - /* - * If we are beyond our current deadline and we are still - * executing, then we have already used some of the runtime of - * the next instance. Thus, if we do not account that, we are - * stealing bandwidth from the system at each deadline miss! - */ - if (dmiss) { - dl_se->runtime = rorun ? dl_se->runtime : 0; - dl_se->runtime -= rq_clock(rq) - dl_se->deadline; - } - - return 1; + return (dl_se->runtime <= 0); } extern bool sched_rt_bandwidth_account(struct rt_rq *rt_rq); @@ -826,10 +809,10 @@ enqueue_dl_entity(struct sched_dl_entity *dl_se, * parameters of the task might need updating. Otherwise, * we want a replenishment of its runtime. */ - if (!dl_se->dl_new && flags & ENQUEUE_REPLENISH) - replenish_dl_entity(dl_se, pi_se); - else + if (dl_se->dl_new || flags & ENQUEUE_WAKEUP) update_dl_entity(dl_se, pi_se); + else if (flags & ENQUEUE_REPLENISH) + replenish_dl_entity(dl_se, pi_se); __enqueue_dl_entity(dl_se); } diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index df2cdf77f899..40667cbf371b 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -4005,6 +4005,10 @@ void __start_cfs_bandwidth(struct cfs_bandwidth *cfs_b, bool force) static void destroy_cfs_bandwidth(struct cfs_bandwidth *cfs_b) { + /* init_cfs_bandwidth() was not called */ + if (!cfs_b->throttled_cfs_rq.next) + return; + hrtimer_cancel(&cfs_b->period_timer); hrtimer_cancel(&cfs_b->slack_timer); } @@ -4424,7 +4428,7 @@ static long effective_load(struct task_group *tg, int cpu, long wl, long wg) * wl = S * s'_i; see (2) */ if (W > 0 && w < W) - wl = (w * tg->shares) / W; + wl = (w * (long)tg->shares) / W; else wl = tg->shares; diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 929a733d302e..224e768bdc73 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -2497,12 +2497,14 @@ static void ftrace_run_update_code(int command) } static void ftrace_run_modify_code(struct ftrace_ops *ops, int command, - struct ftrace_hash *old_hash) + struct ftrace_ops_hash *old_hash) { ops->flags |= FTRACE_OPS_FL_MODIFYING; - ops->old_hash.filter_hash = old_hash; + ops->old_hash.filter_hash = old_hash->filter_hash; + ops->old_hash.notrace_hash = old_hash->notrace_hash; ftrace_run_update_code(command); ops->old_hash.filter_hash = NULL; + ops->old_hash.notrace_hash = NULL; ops->flags &= ~FTRACE_OPS_FL_MODIFYING; } @@ -3579,7 +3581,7 @@ static struct ftrace_ops trace_probe_ops __read_mostly = static int ftrace_probe_registered; -static void __enable_ftrace_function_probe(struct ftrace_hash *old_hash) +static void __enable_ftrace_function_probe(struct ftrace_ops_hash *old_hash) { int ret; int i; @@ -3637,6 +3639,7 @@ int register_ftrace_function_probe(char *glob, struct ftrace_probe_ops *ops, void *data) { + struct ftrace_ops_hash old_hash_ops; struct ftrace_func_probe *entry; struct ftrace_hash **orig_hash = &trace_probe_ops.func_hash->filter_hash; struct ftrace_hash *old_hash = *orig_hash; @@ -3658,6 +3661,10 @@ register_ftrace_function_probe(char *glob, struct ftrace_probe_ops *ops, mutex_lock(&trace_probe_ops.func_hash->regex_lock); + old_hash_ops.filter_hash = old_hash; + /* Probes only have filters */ + old_hash_ops.notrace_hash = NULL; + hash = alloc_and_copy_ftrace_hash(FTRACE_HASH_DEFAULT_BITS, old_hash); if (!hash) { count = -ENOMEM; @@ -3718,7 +3725,7 @@ register_ftrace_function_probe(char *glob, struct ftrace_probe_ops *ops, ret = ftrace_hash_move(&trace_probe_ops, 1, orig_hash, hash); - __enable_ftrace_function_probe(old_hash); + __enable_ftrace_function_probe(&old_hash_ops); if (!ret) free_ftrace_hash_rcu(old_hash); @@ -4006,10 +4013,34 @@ ftrace_match_addr(struct ftrace_hash *hash, unsigned long ip, int remove) } static void ftrace_ops_update_code(struct ftrace_ops *ops, - struct ftrace_hash *old_hash) + struct ftrace_ops_hash *old_hash) { - if (ops->flags & FTRACE_OPS_FL_ENABLED && ftrace_enabled) + struct ftrace_ops *op; + + if (!ftrace_enabled) + return; + + if (ops->flags & FTRACE_OPS_FL_ENABLED) { ftrace_run_modify_code(ops, FTRACE_UPDATE_CALLS, old_hash); + return; + } + + /* + * If this is the shared global_ops filter, then we need to + * check if there is another ops that shares it, is enabled. + * If so, we still need to run the modify code. + */ + if (ops->func_hash != &global_ops.local_hash) + return; + + do_for_each_ftrace_op(op, ftrace_ops_list) { + if (op->func_hash == &global_ops.local_hash && + op->flags & FTRACE_OPS_FL_ENABLED) { + ftrace_run_modify_code(op, FTRACE_UPDATE_CALLS, old_hash); + /* Only need to do this once */ + return; + } + } while_for_each_ftrace_op(op); } static int @@ -4017,6 +4048,7 @@ ftrace_set_hash(struct ftrace_ops *ops, unsigned char *buf, int len, unsigned long ip, int remove, int reset, int enable) { struct ftrace_hash **orig_hash; + struct ftrace_ops_hash old_hash_ops; struct ftrace_hash *old_hash; struct ftrace_hash *hash; int ret; @@ -4053,9 +4085,11 @@ ftrace_set_hash(struct ftrace_ops *ops, unsigned char *buf, int len, mutex_lock(&ftrace_lock); old_hash = *orig_hash; + old_hash_ops.filter_hash = ops->func_hash->filter_hash; + old_hash_ops.notrace_hash = ops->func_hash->notrace_hash; ret = ftrace_hash_move(ops, enable, orig_hash, hash); if (!ret) { - ftrace_ops_update_code(ops, old_hash); + ftrace_ops_update_code(ops, &old_hash_ops); free_ftrace_hash_rcu(old_hash); } mutex_unlock(&ftrace_lock); @@ -4267,6 +4301,7 @@ static void __init set_ftrace_early_filters(void) int ftrace_regex_release(struct inode *inode, struct file *file) { struct seq_file *m = (struct seq_file *)file->private_data; + struct ftrace_ops_hash old_hash_ops; struct ftrace_iterator *iter; struct ftrace_hash **orig_hash; struct ftrace_hash *old_hash; @@ -4300,10 +4335,12 @@ int ftrace_regex_release(struct inode *inode, struct file *file) mutex_lock(&ftrace_lock); old_hash = *orig_hash; + old_hash_ops.filter_hash = iter->ops->func_hash->filter_hash; + old_hash_ops.notrace_hash = iter->ops->func_hash->notrace_hash; ret = ftrace_hash_move(iter->ops, filter_hash, orig_hash, iter->hash); if (!ret) { - ftrace_ops_update_code(iter->ops, old_hash); + ftrace_ops_update_code(iter->ops, &old_hash_ops); free_ftrace_hash_rcu(old_hash); } mutex_unlock(&ftrace_lock); diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 2e767972e99c..4a9079b9f082 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -6918,7 +6918,6 @@ void __init trace_init(void) tracepoint_printk = 0; } tracer_alloc_buffers(); - init_ftrace_syscalls(); trace_event_init(); } diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c index 366a78a3e61e..b03a0ea77b99 100644 --- a/kernel/trace/trace_events.c +++ b/kernel/trace/trace_events.c @@ -2429,12 +2429,39 @@ static __init int event_trace_memsetup(void) return 0; } +static __init void +early_enable_events(struct trace_array *tr, bool disable_first) +{ + char *buf = bootup_event_buf; + char *token; + int ret; + + while (true) { + token = strsep(&buf, ","); + + if (!token) + break; + if (!*token) + continue; + + /* Restarting syscalls requires that we stop them first */ + if (disable_first) + ftrace_set_clr_event(tr, token, 0); + + ret = ftrace_set_clr_event(tr, token, 1); + if (ret) + pr_warn("Failed to enable trace event: %s\n", token); + + /* Put back the comma to allow this to be called again */ + if (buf) + *(buf - 1) = ','; + } +} + static __init int event_trace_enable(void) { struct trace_array *tr = top_trace_array(); struct ftrace_event_call **iter, *call; - char *buf = bootup_event_buf; - char *token; int ret; if (!tr) @@ -2456,18 +2483,7 @@ static __init int event_trace_enable(void) */ __trace_early_add_events(tr); - while (true) { - token = strsep(&buf, ","); - - if (!token) - break; - if (!*token) - continue; - - ret = ftrace_set_clr_event(tr, token, 1); - if (ret) - pr_warn("Failed to enable trace event: %s\n", token); - } + early_enable_events(tr, false); trace_printk_start_comm(); @@ -2478,6 +2494,31 @@ static __init int event_trace_enable(void) return 0; } +/* + * event_trace_enable() is called from trace_event_init() first to + * initialize events and perhaps start any events that are on the + * command line. Unfortunately, there are some events that will not + * start this early, like the system call tracepoints that need + * to set the TIF_SYSCALL_TRACEPOINT flag of pid 1. But event_trace_enable() + * is called before pid 1 starts, and this flag is never set, making + * the syscall tracepoint never get reached, but the event is enabled + * regardless (and not doing anything). + */ +static __init int event_trace_enable_again(void) +{ + struct trace_array *tr; + + tr = top_trace_array(); + if (!tr) + return -ENODEV; + + early_enable_events(tr, true); + + return 0; +} + +early_initcall(event_trace_enable_again); + static __init int event_trace_init(void) { struct trace_array *tr; diff --git a/kernel/trace/trace_kdb.c b/kernel/trace/trace_kdb.c index b0b1c44e923a..3ccf5c2c1320 100644 --- a/kernel/trace/trace_kdb.c +++ b/kernel/trace/trace_kdb.c @@ -132,8 +132,8 @@ static int kdb_ftdump(int argc, const char **argv) static __init int kdb_ftrace_register(void) { - kdb_register_repeat("ftdump", kdb_ftdump, "[skip_#lines] [cpu]", - "Dump ftrace log", 0, KDB_REPEAT_NONE); + kdb_register_flags("ftdump", kdb_ftdump, "[skip_#lines] [cpu]", + "Dump ftrace log", 0, KDB_ENABLE_ALWAYS_SAFE); return 0; } diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 6202b08f1933..beeeac9e0e3e 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -1841,17 +1841,11 @@ static void pool_mayday_timeout(unsigned long __pool) * spin_lock_irq(pool->lock) which may be released and regrabbed * multiple times. Does GFP_KERNEL allocations. Called only from * manager. - * - * Return: - * %false if no action was taken and pool->lock stayed locked, %true - * otherwise. */ -static bool maybe_create_worker(struct worker_pool *pool) +static void maybe_create_worker(struct worker_pool *pool) __releases(&pool->lock) __acquires(&pool->lock) { - if (!need_to_create_worker(pool)) - return false; restart: spin_unlock_irq(&pool->lock); @@ -1877,7 +1871,6 @@ restart: */ if (need_to_create_worker(pool)) goto restart; - return true; } /** @@ -1897,16 +1890,14 @@ restart: * multiple times. Does GFP_KERNEL allocations. * * Return: - * %false if the pool don't need management and the caller can safely start - * processing works, %true indicates that the function released pool->lock - * and reacquired it to perform some management function and that the - * conditions that the caller verified while holding the lock before - * calling the function might no longer be true. + * %false if the pool doesn't need management and the caller can safely + * start processing works, %true if management function was performed and + * the conditions that the caller verified before calling the function may + * no longer be true. */ static bool manage_workers(struct worker *worker) { struct worker_pool *pool = worker->pool; - bool ret = false; /* * Anyone who successfully grabs manager_arb wins the arbitration @@ -1919,12 +1910,12 @@ static bool manage_workers(struct worker *worker) * actual management, the pool may stall indefinitely. */ if (!mutex_trylock(&pool->manager_arb)) - return ret; + return false; - ret |= maybe_create_worker(pool); + maybe_create_worker(pool); mutex_unlock(&pool->manager_arb); - return ret; + return true; } /** diff --git a/lib/Kconfig.kgdb b/lib/Kconfig.kgdb index 358eb81fa28d..c635a107a7de 100644 --- a/lib/Kconfig.kgdb +++ b/lib/Kconfig.kgdb @@ -73,6 +73,31 @@ config KGDB_KDB help KDB frontend for kernel +config KDB_DEFAULT_ENABLE + hex "KDB: Select kdb command functions to be enabled by default" + depends on KGDB_KDB + default 0x1 + help + Specifiers which kdb commands are enabled by default. This may + be set to 1 or 0 to enable all commands or disable almost all + commands. + + Alternatively the following bitmask applies: + + 0x0002 - allow arbitrary reads from memory and symbol lookup + 0x0004 - allow arbitrary writes to memory + 0x0008 - allow current register state to be inspected + 0x0010 - allow current register state to be modified + 0x0020 - allow passive inspection (backtrace, process list, lsmod) + 0x0040 - allow flow control management (breakpoint, single step) + 0x0080 - enable signalling of processes + 0x0100 - allow machine to be rebooted + + The config option merely sets the default at boot time. Both + issuing 'echo X > /sys/module/kdb/parameters/cmd_enable' or + setting with kdb.cmd_enable=X kernel command line option will + override the default settings. + config KDB_KEYBOARD bool "KGDB_KDB: keyboard as input device" depends on VT && KGDB_KDB diff --git a/lib/assoc_array.c b/lib/assoc_array.c index 2404d03e251a..03dd576e6773 100644 --- a/lib/assoc_array.c +++ b/lib/assoc_array.c @@ -11,6 +11,7 @@ * 2 of the Licence, or (at your option) any later version. */ //#define DEBUG +#include <linux/rcupdate.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/assoc_array_priv.h> diff --git a/mm/Kconfig.debug b/mm/Kconfig.debug index 56badfc4810a..957d3da53ddd 100644 --- a/mm/Kconfig.debug +++ b/mm/Kconfig.debug @@ -14,7 +14,6 @@ config DEBUG_PAGEALLOC depends on !KMEMCHECK select PAGE_EXTENSION select PAGE_POISONING if !ARCH_SUPPORTS_DEBUG_PAGEALLOC - select PAGE_GUARD if ARCH_SUPPORTS_DEBUG_PAGEALLOC ---help--- Unmap pages from the kernel linear mapping after free_pages(). This results in a large slowdown, but helps to find certain types @@ -27,13 +26,5 @@ config DEBUG_PAGEALLOC that would result in incorrect warnings of memory corruption after a resume because free pages are not saved to the suspend image. -config WANT_PAGE_DEBUG_FLAGS - bool - config PAGE_POISONING bool - select WANT_PAGE_DEBUG_FLAGS - -config PAGE_GUARD - bool - select WANT_PAGE_DEBUG_FLAGS diff --git a/mm/memcontrol.c b/mm/memcontrol.c index ef91e856c7e4..851924fa5170 100644 --- a/mm/memcontrol.c +++ b/mm/memcontrol.c @@ -3043,18 +3043,6 @@ static int mem_cgroup_move_swap_account(swp_entry_t entry, if (swap_cgroup_cmpxchg(entry, old_id, new_id) == old_id) { mem_cgroup_swap_statistics(from, false); mem_cgroup_swap_statistics(to, true); - /* - * This function is only called from task migration context now. - * It postpones page_counter and refcount handling till the end - * of task migration(mem_cgroup_clear_mc()) for performance - * improvement. But we cannot postpone css_get(to) because if - * the process that has been moved to @to does swap-in, the - * refcount of @to might be decreased to 0. - * - * We are in attach() phase, so the cgroup is guaranteed to be - * alive, so we can just call css_get(). - */ - css_get(&to->css); return 0; } return -EINVAL; @@ -4679,6 +4667,7 @@ mem_cgroup_css_alloc(struct cgroup_subsys_state *parent_css) if (parent_css == NULL) { root_mem_cgroup = memcg; page_counter_init(&memcg->memory, NULL); + memcg->soft_limit = PAGE_COUNTER_MAX; page_counter_init(&memcg->memsw, NULL); page_counter_init(&memcg->kmem, NULL); } @@ -4724,6 +4713,7 @@ mem_cgroup_css_online(struct cgroup_subsys_state *css) if (parent->use_hierarchy) { page_counter_init(&memcg->memory, &parent->memory); + memcg->soft_limit = PAGE_COUNTER_MAX; page_counter_init(&memcg->memsw, &parent->memsw); page_counter_init(&memcg->kmem, &parent->kmem); @@ -4733,6 +4723,7 @@ mem_cgroup_css_online(struct cgroup_subsys_state *css) */ } else { page_counter_init(&memcg->memory, NULL); + memcg->soft_limit = PAGE_COUNTER_MAX; page_counter_init(&memcg->memsw, NULL); page_counter_init(&memcg->kmem, NULL); /* @@ -4807,7 +4798,7 @@ static void mem_cgroup_css_reset(struct cgroup_subsys_state *css) mem_cgroup_resize_limit(memcg, PAGE_COUNTER_MAX); mem_cgroup_resize_memsw_limit(memcg, PAGE_COUNTER_MAX); memcg_update_kmem_limit(memcg, PAGE_COUNTER_MAX); - memcg->soft_limit = 0; + memcg->soft_limit = PAGE_COUNTER_MAX; } #ifdef CONFIG_MMU diff --git a/mm/memory.c b/mm/memory.c index ca920d1fd314..54f3a9b00956 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -235,6 +235,9 @@ void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long static void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb) { + if (!tlb->end) + return; + tlb_flush(tlb); mmu_notifier_invalidate_range(tlb->mm, tlb->start, tlb->end); #ifdef CONFIG_HAVE_RCU_TABLE_FREE @@ -247,7 +250,7 @@ static void tlb_flush_mmu_free(struct mmu_gather *tlb) { struct mmu_gather_batch *batch; - for (batch = &tlb->local; batch; batch = batch->next) { + for (batch = &tlb->local; batch && batch->nr; batch = batch->next) { free_pages_and_swap_cache(batch->pages, batch->nr); batch->nr = 0; } @@ -256,9 +259,6 @@ static void tlb_flush_mmu_free(struct mmu_gather *tlb) void tlb_flush_mmu(struct mmu_gather *tlb) { - if (!tlb->end) - return; - tlb_flush_mmu_tlbonly(tlb); tlb_flush_mmu_free(tlb); } @@ -2137,17 +2137,24 @@ reuse: if (!dirty_page) return ret; - /* - * Yes, Virginia, this is actually required to prevent a race - * with clear_page_dirty_for_io() from clearing the page dirty - * bit after it clear all dirty ptes, but before a racing - * do_wp_page installs a dirty pte. - * - * do_shared_fault is protected similarly. - */ if (!page_mkwrite) { - wait_on_page_locked(dirty_page); - set_page_dirty_balance(dirty_page); + struct address_space *mapping; + int dirtied; + + lock_page(dirty_page); + dirtied = set_page_dirty(dirty_page); + VM_BUG_ON_PAGE(PageAnon(dirty_page), dirty_page); + mapping = dirty_page->mapping; + unlock_page(dirty_page); + + if (dirtied && mapping) { + /* + * Some device drivers do not set page.mapping + * but still dirty their pages + */ + balance_dirty_pages_ratelimited(mapping); + } + /* file_update_time outside page_lock */ if (vma->vm_file) file_update_time(vma->vm_file); @@ -2593,7 +2600,7 @@ static inline int check_stack_guard_page(struct vm_area_struct *vma, unsigned lo if (prev && prev->vm_end == address) return prev->vm_flags & VM_GROWSDOWN ? 0 : -ENOMEM; - expand_downwards(vma, address - PAGE_SIZE); + return expand_downwards(vma, address - PAGE_SIZE); } if ((vma->vm_flags & VM_GROWSUP) && address + PAGE_SIZE == vma->vm_end) { struct vm_area_struct *next = vma->vm_next; @@ -2602,7 +2609,7 @@ static inline int check_stack_guard_page(struct vm_area_struct *vma, unsigned lo if (next && next->vm_start == address + PAGE_SIZE) return next->vm_flags & VM_GROWSUP ? 0 : -ENOMEM; - expand_upwards(vma, address + PAGE_SIZE); + return expand_upwards(vma, address + PAGE_SIZE); } return 0; } diff --git a/mm/mmap.c b/mm/mmap.c index 7b36aa7cc89a..7f684d5a8087 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -778,10 +778,12 @@ again: remove_next = 1 + (end > next->vm_end); if (exporter && exporter->anon_vma && !importer->anon_vma) { int error; + importer->anon_vma = exporter->anon_vma; error = anon_vma_clone(importer, exporter); - if (error) + if (error) { + importer->anon_vma = NULL; return error; - importer->anon_vma = exporter->anon_vma; + } } } @@ -2099,14 +2101,17 @@ static int acct_stack_growth(struct vm_area_struct *vma, unsigned long size, uns { struct mm_struct *mm = vma->vm_mm; struct rlimit *rlim = current->signal->rlim; - unsigned long new_start; + unsigned long new_start, actual_size; /* address space limit tests */ if (!may_expand_vm(mm, grow)) return -ENOMEM; /* Stack limit test */ - if (size > ACCESS_ONCE(rlim[RLIMIT_STACK].rlim_cur)) + actual_size = size; + if (size && (vma->vm_flags & (VM_GROWSUP | VM_GROWSDOWN))) + actual_size -= PAGE_SIZE; + if (actual_size > ACCESS_ONCE(rlim[RLIMIT_STACK].rlim_cur)) return -ENOMEM; /* mlock limit tests */ diff --git a/mm/page-writeback.c b/mm/page-writeback.c index d5d81f5384d1..6f4335238e33 100644 --- a/mm/page-writeback.c +++ b/mm/page-writeback.c @@ -1541,16 +1541,6 @@ pause: bdi_start_background_writeback(bdi); } -void set_page_dirty_balance(struct page *page) -{ - if (set_page_dirty(page)) { - struct address_space *mapping = page_mapping(page); - - if (mapping) - balance_dirty_pages_ratelimited(mapping); - } -} - static DEFINE_PER_CPU(int, bdp_ratelimits); /* @@ -2123,32 +2113,25 @@ EXPORT_SYMBOL(account_page_dirtied); * page dirty in that case, but not all the buffers. This is a "bottom-up" * dirtying, whereas __set_page_dirty_buffers() is a "top-down" dirtying. * - * Most callers have locked the page, which pins the address_space in memory. - * But zap_pte_range() does not lock the page, however in that case the - * mapping is pinned by the vma's ->vm_file reference. - * - * We take care to handle the case where the page was truncated from the - * mapping by re-checking page_mapping() inside tree_lock. + * The caller must ensure this doesn't race with truncation. Most will simply + * hold the page lock, but e.g. zap_pte_range() calls with the page mapped and + * the pte lock held, which also locks out truncation. */ int __set_page_dirty_nobuffers(struct page *page) { if (!TestSetPageDirty(page)) { struct address_space *mapping = page_mapping(page); - struct address_space *mapping2; unsigned long flags; if (!mapping) return 1; spin_lock_irqsave(&mapping->tree_lock, flags); - mapping2 = page_mapping(page); - if (mapping2) { /* Race with truncate? */ - BUG_ON(mapping2 != mapping); - WARN_ON_ONCE(!PagePrivate(page) && !PageUptodate(page)); - account_page_dirtied(page, mapping); - radix_tree_tag_set(&mapping->page_tree, - page_index(page), PAGECACHE_TAG_DIRTY); - } + BUG_ON(page_mapping(page) != mapping); + WARN_ON_ONCE(!PagePrivate(page) && !PageUptodate(page)); + account_page_dirtied(page, mapping); + radix_tree_tag_set(&mapping->page_tree, page_index(page), + PAGECACHE_TAG_DIRTY); spin_unlock_irqrestore(&mapping->tree_lock, flags); if (mapping->host) { /* !PageAnon && !swapper_space */ @@ -2305,12 +2288,10 @@ int clear_page_dirty_for_io(struct page *page) /* * We carefully synchronise fault handlers against * installing a dirty pte and marking the page dirty - * at this point. We do this by having them hold the - * page lock at some point after installing their - * pte, but before marking the page dirty. - * Pages are always locked coming in here, so we get - * the desired exclusion. See mm/memory.c:do_wp_page() - * for more comments. + * at this point. We do this by having them hold the + * page lock while dirtying the page, and pages are + * always locked coming in here, so we get the desired + * exclusion. */ if (TestClearPageDirty(page)) { dec_zone_page_state(page, NR_FILE_DIRTY); diff --git a/mm/rmap.c b/mm/rmap.c index c5bc241127b2..71cd5bd0c17d 100644 --- a/mm/rmap.c +++ b/mm/rmap.c @@ -72,6 +72,8 @@ static inline struct anon_vma *anon_vma_alloc(void) anon_vma = kmem_cache_alloc(anon_vma_cachep, GFP_KERNEL); if (anon_vma) { atomic_set(&anon_vma->refcount, 1); + anon_vma->degree = 1; /* Reference for first vma */ + anon_vma->parent = anon_vma; /* * Initialise the anon_vma root to point to itself. If called * from fork, the root will be reset to the parents anon_vma. @@ -188,6 +190,8 @@ int anon_vma_prepare(struct vm_area_struct *vma) if (likely(!vma->anon_vma)) { vma->anon_vma = anon_vma; anon_vma_chain_link(vma, avc, anon_vma); + /* vma reference or self-parent link for new root */ + anon_vma->degree++; allocated = NULL; avc = NULL; } @@ -236,6 +240,14 @@ static inline void unlock_anon_vma_root(struct anon_vma *root) /* * Attach the anon_vmas from src to dst. * Returns 0 on success, -ENOMEM on failure. + * + * If dst->anon_vma is NULL this function tries to find and reuse existing + * anon_vma which has no vmas and only one child anon_vma. This prevents + * degradation of anon_vma hierarchy to endless linear chain in case of + * constantly forking task. On the other hand, an anon_vma with more than one + * child isn't reused even if there was no alive vma, thus rmap walker has a + * good chance of avoiding scanning the whole hierarchy when it searches where + * page is mapped. */ int anon_vma_clone(struct vm_area_struct *dst, struct vm_area_struct *src) { @@ -256,7 +268,21 @@ int anon_vma_clone(struct vm_area_struct *dst, struct vm_area_struct *src) anon_vma = pavc->anon_vma; root = lock_anon_vma_root(root, anon_vma); anon_vma_chain_link(dst, avc, anon_vma); + + /* + * Reuse existing anon_vma if its degree lower than two, + * that means it has no vma and only one anon_vma child. + * + * Do not chose parent anon_vma, otherwise first child + * will always reuse it. Root anon_vma is never reused: + * it has self-parent reference and at least one child. + */ + if (!dst->anon_vma && anon_vma != src->anon_vma && + anon_vma->degree < 2) + dst->anon_vma = anon_vma; } + if (dst->anon_vma) + dst->anon_vma->degree++; unlock_anon_vma_root(root); return 0; @@ -280,6 +306,9 @@ int anon_vma_fork(struct vm_area_struct *vma, struct vm_area_struct *pvma) if (!pvma->anon_vma) return 0; + /* Drop inherited anon_vma, we'll reuse existing or allocate new. */ + vma->anon_vma = NULL; + /* * First, attach the new VMA to the parent VMA's anon_vmas, * so rmap can find non-COWed pages in child processes. @@ -288,6 +317,10 @@ int anon_vma_fork(struct vm_area_struct *vma, struct vm_area_struct *pvma) if (error) return error; + /* An existing anon_vma has been reused, all done then. */ + if (vma->anon_vma) + return 0; + /* Then add our own anon_vma. */ anon_vma = anon_vma_alloc(); if (!anon_vma) @@ -301,6 +334,7 @@ int anon_vma_fork(struct vm_area_struct *vma, struct vm_area_struct *pvma) * lock any of the anon_vmas in this anon_vma tree. */ anon_vma->root = pvma->anon_vma->root; + anon_vma->parent = pvma->anon_vma; /* * With refcounts, an anon_vma can stay around longer than the * process it belongs to. The root anon_vma needs to be pinned until @@ -311,6 +345,7 @@ int anon_vma_fork(struct vm_area_struct *vma, struct vm_area_struct *pvma) vma->anon_vma = anon_vma; anon_vma_lock_write(anon_vma); anon_vma_chain_link(vma, avc, anon_vma); + anon_vma->parent->degree++; anon_vma_unlock_write(anon_vma); return 0; @@ -341,12 +376,16 @@ void unlink_anon_vmas(struct vm_area_struct *vma) * Leave empty anon_vmas on the list - we'll need * to free them outside the lock. */ - if (RB_EMPTY_ROOT(&anon_vma->rb_root)) + if (RB_EMPTY_ROOT(&anon_vma->rb_root)) { + anon_vma->parent->degree--; continue; + } list_del(&avc->same_vma); anon_vma_chain_free(avc); } + if (vma->anon_vma) + vma->anon_vma->degree--; unlock_anon_vma_root(root); /* @@ -357,6 +396,7 @@ void unlink_anon_vmas(struct vm_area_struct *vma) list_for_each_entry_safe(avc, next, &vma->anon_vma_chain, same_vma) { struct anon_vma *anon_vma = avc->anon_vma; + BUG_ON(anon_vma->degree); put_anon_vma(anon_vma); list_del(&avc->same_vma); diff --git a/mm/vmscan.c b/mm/vmscan.c index bd9a72bc4a1b..ab2505c3ef54 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -2921,18 +2921,20 @@ static bool prepare_kswapd_sleep(pg_data_t *pgdat, int order, long remaining, return false; /* - * There is a potential race between when kswapd checks its watermarks - * and a process gets throttled. There is also a potential race if - * processes get throttled, kswapd wakes, a large process exits therby - * balancing the zones that causes kswapd to miss a wakeup. If kswapd - * is going to sleep, no process should be sleeping on pfmemalloc_wait - * so wake them now if necessary. If necessary, processes will wake - * kswapd and get throttled again + * The throttled processes are normally woken up in balance_pgdat() as + * soon as pfmemalloc_watermark_ok() is true. But there is a potential + * race between when kswapd checks the watermarks and a process gets + * throttled. There is also a potential race if processes get + * throttled, kswapd wakes, a large process exits thereby balancing the + * zones, which causes kswapd to exit balance_pgdat() before reaching + * the wake up checks. If kswapd is going to sleep, no process should + * be sleeping on pfmemalloc_wait, so wake them now if necessary. If + * the wake up is premature, processes will wake kswapd and get + * throttled again. The difference from wake ups in balance_pgdat() is + * that here we are under prepare_to_wait(). */ - if (waitqueue_active(&pgdat->pfmemalloc_wait)) { - wake_up(&pgdat->pfmemalloc_wait); - return false; - } + if (waitqueue_active(&pgdat->pfmemalloc_wait)) + wake_up_all(&pgdat->pfmemalloc_wait); return pgdat_balanced(pgdat, order, classzone_idx); } diff --git a/net/batman-adv/multicast.c b/net/batman-adv/multicast.c index ab6bb2af1d45..b24e4bb64fb5 100644 --- a/net/batman-adv/multicast.c +++ b/net/batman-adv/multicast.c @@ -685,11 +685,13 @@ static void batadv_mcast_tvlv_ogm_handler_v1(struct batadv_priv *bat_priv, if (orig_initialized) atomic_dec(&bat_priv->mcast.num_disabled); orig->capabilities |= BATADV_ORIG_CAPA_HAS_MCAST; - /* If mcast support is being switched off increase the disabled - * mcast node counter. + /* If mcast support is being switched off or if this is an initial + * OGM without mcast support then increase the disabled mcast + * node counter. */ } else if (!orig_mcast_enabled && - orig->capabilities & BATADV_ORIG_CAPA_HAS_MCAST) { + (orig->capabilities & BATADV_ORIG_CAPA_HAS_MCAST || + !orig_initialized)) { atomic_inc(&bat_priv->mcast.num_disabled); orig->capabilities &= ~BATADV_ORIG_CAPA_HAS_MCAST; } @@ -738,7 +740,8 @@ void batadv_mcast_purge_orig(struct batadv_orig_node *orig) { struct batadv_priv *bat_priv = orig->bat_priv; - if (!(orig->capabilities & BATADV_ORIG_CAPA_HAS_MCAST)) + if (!(orig->capabilities & BATADV_ORIG_CAPA_HAS_MCAST) && + orig->capa_initialized & BATADV_ORIG_CAPA_HAS_MCAST) atomic_dec(&bat_priv->mcast.num_disabled); batadv_mcast_want_unsnoop_update(bat_priv, orig, BATADV_NO_FLAGS); diff --git a/net/batman-adv/network-coding.c b/net/batman-adv/network-coding.c index 8d04d174669e..fab47f1f3ef9 100644 --- a/net/batman-adv/network-coding.c +++ b/net/batman-adv/network-coding.c @@ -133,7 +133,7 @@ int batadv_nc_mesh_init(struct batadv_priv *bat_priv) if (!bat_priv->nc.decoding_hash) goto err; - batadv_hash_set_lock_class(bat_priv->nc.coding_hash, + batadv_hash_set_lock_class(bat_priv->nc.decoding_hash, &batadv_nc_decoding_hash_lock_class_key); INIT_DELAYED_WORK(&bat_priv->nc.work, batadv_nc_worker); diff --git a/net/batman-adv/originator.c b/net/batman-adv/originator.c index 6a484514cd3e..bea8198d0198 100644 --- a/net/batman-adv/originator.c +++ b/net/batman-adv/originator.c @@ -570,9 +570,6 @@ static void batadv_orig_node_free_rcu(struct rcu_head *rcu) batadv_frag_purge_orig(orig_node, NULL); - batadv_tt_global_del_orig(orig_node->bat_priv, orig_node, -1, - "originator timed out"); - if (orig_node->bat_priv->bat_algo_ops->bat_orig_free) orig_node->bat_priv->bat_algo_ops->bat_orig_free(orig_node); @@ -678,6 +675,7 @@ struct batadv_orig_node *batadv_orig_node_new(struct batadv_priv *bat_priv, atomic_set(&orig_node->last_ttvn, 0); orig_node->tt_buff = NULL; orig_node->tt_buff_len = 0; + orig_node->last_seen = jiffies; reset_time = jiffies - 1 - msecs_to_jiffies(BATADV_RESET_PROTECTION_MS); orig_node->bcast_seqno_reset = reset_time; #ifdef CONFIG_BATMAN_ADV_MCAST @@ -977,6 +975,9 @@ static void _batadv_purge_orig(struct batadv_priv *bat_priv) if (batadv_purge_orig_node(bat_priv, orig_node)) { batadv_gw_node_delete(bat_priv, orig_node); hlist_del_rcu(&orig_node->hash_entry); + batadv_tt_global_del_orig(orig_node->bat_priv, + orig_node, -1, + "originator timed out"); batadv_orig_node_free_ref(orig_node); continue; } diff --git a/net/batman-adv/routing.c b/net/batman-adv/routing.c index 35f76f2f7824..6648f321864d 100644 --- a/net/batman-adv/routing.c +++ b/net/batman-adv/routing.c @@ -443,11 +443,13 @@ batadv_find_router(struct batadv_priv *bat_priv, router = batadv_orig_router_get(orig_node, recv_if); + if (!router) + return router; + /* only consider bonding for recv_if == BATADV_IF_DEFAULT (first hop) * and if activated. */ - if (recv_if == BATADV_IF_DEFAULT || !atomic_read(&bat_priv->bonding) || - !router) + if (!(recv_if == BATADV_IF_DEFAULT && atomic_read(&bat_priv->bonding))) return router; /* bonding: loop through the list of possible routers found diff --git a/net/bridge/br_input.c b/net/bridge/br_input.c index 1f1de715197c..e2aa7be3a847 100644 --- a/net/bridge/br_input.c +++ b/net/bridge/br_input.c @@ -154,7 +154,8 @@ int br_handle_frame_finish(struct sk_buff *skb) dst = NULL; if (is_broadcast_ether_addr(dest)) { - if (p->flags & BR_PROXYARP && + if (IS_ENABLED(CONFIG_INET) && + p->flags & BR_PROXYARP && skb->protocol == htons(ETH_P_ARP)) br_do_proxy_arp(skb, br, vid); diff --git a/net/ceph/auth_x.c b/net/ceph/auth_x.c index 15845814a0f2..ba6eb17226da 100644 --- a/net/ceph/auth_x.c +++ b/net/ceph/auth_x.c @@ -676,7 +676,7 @@ static int calcu_signature(struct ceph_x_authorizer *au, int ret; char tmp_enc[40]; __le32 tmp[5] = { - 16u, msg->hdr.crc, msg->footer.front_crc, + cpu_to_le32(16), msg->hdr.crc, msg->footer.front_crc, msg->footer.middle_crc, msg->footer.data_crc, }; ret = ceph_x_encrypt(&au->session_key, &tmp, sizeof(tmp), diff --git a/net/ceph/mon_client.c b/net/ceph/mon_client.c index a83062ceeec9..f2148e22b148 100644 --- a/net/ceph/mon_client.c +++ b/net/ceph/mon_client.c @@ -717,7 +717,7 @@ static int get_poolop_reply_buf(const char *src, size_t src_len, if (src_len != sizeof(u32) + dst_len) return -EINVAL; - buf_len = le32_to_cpu(*(u32 *)src); + buf_len = le32_to_cpu(*(__le32 *)src); if (buf_len != dst_len) return -EINVAL; diff --git a/net/core/dev.c b/net/core/dev.c index 683d493aa1bf..171420e75b03 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -7072,10 +7072,20 @@ static int dev_cpu_callback(struct notifier_block *nfb, oldsd->output_queue = NULL; oldsd->output_queue_tailp = &oldsd->output_queue; } - /* Append NAPI poll list from offline CPU. */ - if (!list_empty(&oldsd->poll_list)) { - list_splice_init(&oldsd->poll_list, &sd->poll_list); - raise_softirq_irqoff(NET_RX_SOFTIRQ); + /* Append NAPI poll list from offline CPU, with one exception : + * process_backlog() must be called by cpu owning percpu backlog. + * We properly handle process_queue & input_pkt_queue later. + */ + while (!list_empty(&oldsd->poll_list)) { + struct napi_struct *napi = list_first_entry(&oldsd->poll_list, + struct napi_struct, + poll_list); + + list_del_init(&napi->poll_list); + if (napi->poll == process_backlog) + napi->state = 0; + else + ____napi_schedule(sd, napi); } raise_softirq_irqoff(NET_TX_SOFTIRQ); @@ -7086,7 +7096,7 @@ static int dev_cpu_callback(struct notifier_block *nfb, netif_rx_internal(skb); input_queue_head_incr(oldsd); } - while ((skb = __skb_dequeue(&oldsd->input_pkt_queue))) { + while ((skb = skb_dequeue(&oldsd->input_pkt_queue))) { netif_rx_internal(skb); input_queue_head_incr(oldsd); } diff --git a/net/core/neighbour.c b/net/core/neighbour.c index 8e38f17288d3..8d614c93f86a 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -2043,6 +2043,12 @@ static int neightbl_set(struct sk_buff *skb, struct nlmsghdr *nlh) case NDTPA_BASE_REACHABLE_TIME: NEIGH_VAR_SET(p, BASE_REACHABLE_TIME, nla_get_msecs(tbp[i])); + /* update reachable_time as well, otherwise, the change will + * only be effective after the next time neigh_periodic_work + * decides to recompute it (can be multiple minutes) + */ + p->reachable_time = + neigh_rand_reach_time(NEIGH_VAR(p, BASE_REACHABLE_TIME)); break; case NDTPA_GC_STALETIME: NEIGH_VAR_SET(p, GC_STALETIME, @@ -2921,6 +2927,31 @@ static int neigh_proc_dointvec_unres_qlen(struct ctl_table *ctl, int write, return ret; } +static int neigh_proc_base_reachable_time(struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos) +{ + struct neigh_parms *p = ctl->extra2; + int ret; + + if (strcmp(ctl->procname, "base_reachable_time") == 0) + ret = neigh_proc_dointvec_jiffies(ctl, write, buffer, lenp, ppos); + else if (strcmp(ctl->procname, "base_reachable_time_ms") == 0) + ret = neigh_proc_dointvec_ms_jiffies(ctl, write, buffer, lenp, ppos); + else + ret = -1; + + if (write && ret == 0) { + /* update reachable_time as well, otherwise, the change will + * only be effective after the next time neigh_periodic_work + * decides to recompute it + */ + p->reachable_time = + neigh_rand_reach_time(NEIGH_VAR(p, BASE_REACHABLE_TIME)); + } + return ret; +} + #define NEIGH_PARMS_DATA_OFFSET(index) \ (&((struct neigh_parms *) 0)->data[index]) @@ -3047,6 +3078,19 @@ int neigh_sysctl_register(struct net_device *dev, struct neigh_parms *p, t->neigh_vars[NEIGH_VAR_RETRANS_TIME_MS].proc_handler = handler; /* ReachableTime (in milliseconds) */ t->neigh_vars[NEIGH_VAR_BASE_REACHABLE_TIME_MS].proc_handler = handler; + } else { + /* Those handlers will update p->reachable_time after + * base_reachable_time(_ms) is set to ensure the new timer starts being + * applied after the next neighbour update instead of waiting for + * neigh_periodic_work to update its value (can be multiple minutes) + * So any handler that replaces them should do this as well + */ + /* ReachableTime */ + t->neigh_vars[NEIGH_VAR_BASE_REACHABLE_TIME].proc_handler = + neigh_proc_base_reachable_time; + /* ReachableTime (in milliseconds) */ + t->neigh_vars[NEIGH_VAR_BASE_REACHABLE_TIME_MS].proc_handler = + neigh_proc_base_reachable_time; } /* Don't export sysctls to unprivileged users */ diff --git a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c index 8a89c738b7a3..6b85adb05003 100644 --- a/net/ipv4/ip_sockglue.c +++ b/net/ipv4/ip_sockglue.c @@ -461,17 +461,13 @@ int ip_recv_error(struct sock *sk, struct msghdr *msg, int len, int *addr_len) memcpy(&errhdr.ee, &serr->ee, sizeof(struct sock_extended_err)); sin = &errhdr.offender; - sin->sin_family = AF_UNSPEC; + memset(sin, 0, sizeof(*sin)); if (serr->ee.ee_origin == SO_EE_ORIGIN_ICMP || ipv4_pktinfo_prepare_errqueue(sk, skb, serr->ee.ee_origin)) { - struct inet_sock *inet = inet_sk(sk); - sin->sin_family = AF_INET; sin->sin_addr.s_addr = ip_hdr(skb)->saddr; - sin->sin_port = 0; - memset(&sin->sin_zero, 0, sizeof(sin->sin_zero)); - if (inet->cmsg_flags) + if (inet_sk(sk)->cmsg_flags) ip_cmsg_recv(msg, skb); } diff --git a/net/ipv4/netfilter/nft_redir_ipv4.c b/net/ipv4/netfilter/nft_redir_ipv4.c index ff2d23d8c87a..6ecfce63201a 100644 --- a/net/ipv4/netfilter/nft_redir_ipv4.c +++ b/net/ipv4/netfilter/nft_redir_ipv4.c @@ -27,10 +27,10 @@ static void nft_redir_ipv4_eval(const struct nft_expr *expr, memset(&mr, 0, sizeof(mr)); if (priv->sreg_proto_min) { - mr.range[0].min.all = (__force __be16) - data[priv->sreg_proto_min].data[0]; - mr.range[0].max.all = (__force __be16) - data[priv->sreg_proto_max].data[0]; + mr.range[0].min.all = + *(__be16 *)&data[priv->sreg_proto_min].data[0]; + mr.range[0].max.all = + *(__be16 *)&data[priv->sreg_proto_max].data[0]; mr.range[0].flags |= NF_NAT_RANGE_PROTO_SPECIFIED; } diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 7f18262e2326..65caf8b95e17 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -2019,7 +2019,7 @@ static bool tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle, if (unlikely(!tcp_snd_wnd_test(tp, skb, mss_now))) break; - if (tso_segs == 1) { + if (tso_segs == 1 || !max_segs) { if (unlikely(!tcp_nagle_test(tp, skb, mss_now, (tcp_skb_is_last(sk, skb) ? nonagle : TCP_NAGLE_PUSH)))) @@ -2032,7 +2032,7 @@ static bool tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle, } limit = mss_now; - if (tso_segs > 1 && !tcp_urg_mode(tp)) + if (tso_segs > 1 && max_segs && !tcp_urg_mode(tp)) limit = tcp_mss_split_point(sk, skb, mss_now, min_t(unsigned int, cwnd_quota, diff --git a/net/ipv6/datagram.c b/net/ipv6/datagram.c index 100c589a2a6c..49f5e73db122 100644 --- a/net/ipv6/datagram.c +++ b/net/ipv6/datagram.c @@ -393,11 +393,10 @@ int ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len, int *addr_len) memcpy(&errhdr.ee, &serr->ee, sizeof(struct sock_extended_err)); sin = &errhdr.offender; - sin->sin6_family = AF_UNSPEC; + memset(sin, 0, sizeof(*sin)); + if (serr->ee.ee_origin != SO_EE_ORIGIN_LOCAL) { sin->sin6_family = AF_INET6; - sin->sin6_flowinfo = 0; - sin->sin6_port = 0; if (np->rxopt.all) { if (serr->ee.ee_origin != SO_EE_ORIGIN_ICMP && serr->ee.ee_origin != SO_EE_ORIGIN_ICMP6) @@ -412,12 +411,9 @@ int ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len, int *addr_len) ipv6_iface_scope_id(&sin->sin6_addr, IP6CB(skb)->iif); } else { - struct inet_sock *inet = inet_sk(sk); - ipv6_addr_set_v4mapped(ip_hdr(skb)->saddr, &sin->sin6_addr); - sin->sin6_scope_id = 0; - if (inet->cmsg_flags) + if (inet_sk(sk)->cmsg_flags) ip_cmsg_recv(msg, skb); } } diff --git a/net/ipv6/netfilter/nft_redir_ipv6.c b/net/ipv6/netfilter/nft_redir_ipv6.c index 2433a6bfb191..11820b6b3613 100644 --- a/net/ipv6/netfilter/nft_redir_ipv6.c +++ b/net/ipv6/netfilter/nft_redir_ipv6.c @@ -27,10 +27,10 @@ static void nft_redir_ipv6_eval(const struct nft_expr *expr, memset(&range, 0, sizeof(range)); if (priv->sreg_proto_min) { - range.min_proto.all = (__force __be16) - data[priv->sreg_proto_min].data[0]; - range.max_proto.all = (__force __be16) - data[priv->sreg_proto_max].data[0]; + range.min_proto.all = + *(__be16 *)&data[priv->sreg_proto_min].data[0]; + range.max_proto.all = + *(__be16 *)&data[priv->sreg_proto_max].data[0]; range.flags |= NF_NAT_RANGE_PROTO_SPECIFIED; } diff --git a/net/ipv6/route.c b/net/ipv6/route.c index c91083156edb..166e33bed222 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c @@ -1160,12 +1160,9 @@ static void ip6_rt_update_pmtu(struct dst_entry *dst, struct sock *sk, struct net *net = dev_net(dst->dev); rt6->rt6i_flags |= RTF_MODIFIED; - if (mtu < IPV6_MIN_MTU) { - u32 features = dst_metric(dst, RTAX_FEATURES); + if (mtu < IPV6_MIN_MTU) mtu = IPV6_MIN_MTU; - features |= RTAX_FEATURE_ALLFRAG; - dst_metric_set(dst, RTAX_FEATURES, features); - } + dst_metric_set(dst, RTAX_MTU, mtu); rt6_update_expires(rt6, net->ipv6.sysctl.ip6_rt_mtu_expires); } diff --git a/net/mac80211/key.c b/net/mac80211/key.c index 0bb7038121ac..bd4e46ec32bd 100644 --- a/net/mac80211/key.c +++ b/net/mac80211/key.c @@ -140,7 +140,9 @@ static int ieee80211_key_enable_hw_accel(struct ieee80211_key *key) if (!ret) { key->flags |= KEY_FLAG_UPLOADED_TO_HARDWARE; - if (!(key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_MMIC)) + if (!((key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_MMIC) || + (key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_IV) || + (key->conf.flags & IEEE80211_KEY_FLAG_PUT_IV_SPACE))) sdata->crypto_tx_tailroom_needed_cnt--; WARN_ON((key->conf.flags & IEEE80211_KEY_FLAG_PUT_IV_SPACE) && @@ -188,7 +190,9 @@ static void ieee80211_key_disable_hw_accel(struct ieee80211_key *key) sta = key->sta; sdata = key->sdata; - if (!(key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_MMIC)) + if (!((key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_MMIC) || + (key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_IV) || + (key->conf.flags & IEEE80211_KEY_FLAG_PUT_IV_SPACE))) increment_tailroom_need_count(sdata); ret = drv_set_key(key->local, DISABLE_KEY, sdata, @@ -884,7 +888,9 @@ void ieee80211_remove_key(struct ieee80211_key_conf *keyconf) if (key->flags & KEY_FLAG_UPLOADED_TO_HARDWARE) { key->flags &= ~KEY_FLAG_UPLOADED_TO_HARDWARE; - if (!(key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_MMIC)) + if (!((key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_MMIC) || + (key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_IV) || + (key->conf.flags & IEEE80211_KEY_FLAG_PUT_IV_SPACE))) increment_tailroom_need_count(key->sdata); } diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c index 2c36c4765f47..837a406a9dd6 100644 --- a/net/mac80211/mlme.c +++ b/net/mac80211/mlme.c @@ -1643,7 +1643,7 @@ __ieee80211_sta_handle_tspec_ac_params(struct ieee80211_sub_if_data *sdata) { struct ieee80211_local *local = sdata->local; struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; - bool ret; + bool ret = false; int ac; if (local->hw.queues < IEEE80211_NUM_ACS) diff --git a/net/netfilter/ipvs/ip_vs_ftp.c b/net/netfilter/ipvs/ip_vs_ftp.c index 1d5341f3761d..5d3daae98bf0 100644 --- a/net/netfilter/ipvs/ip_vs_ftp.c +++ b/net/netfilter/ipvs/ip_vs_ftp.c @@ -183,6 +183,8 @@ static int ip_vs_ftp_out(struct ip_vs_app *app, struct ip_vs_conn *cp, struct nf_conn *ct; struct net *net; + *diff = 0; + #ifdef CONFIG_IP_VS_IPV6 /* This application helper doesn't work with IPv6 yet, * so turn this into a no-op for IPv6 packets @@ -191,8 +193,6 @@ static int ip_vs_ftp_out(struct ip_vs_app *app, struct ip_vs_conn *cp, return 1; #endif - *diff = 0; - /* Only useful for established sessions */ if (cp->state != IP_VS_TCP_S_ESTABLISHED) return 1; @@ -322,6 +322,9 @@ static int ip_vs_ftp_in(struct ip_vs_app *app, struct ip_vs_conn *cp, struct ip_vs_conn *n_cp; struct net *net; + /* no diff required for incoming packets */ + *diff = 0; + #ifdef CONFIG_IP_VS_IPV6 /* This application helper doesn't work with IPv6 yet, * so turn this into a no-op for IPv6 packets @@ -330,9 +333,6 @@ static int ip_vs_ftp_in(struct ip_vs_app *app, struct ip_vs_conn *cp, return 1; #endif - /* no diff required for incoming packets */ - *diff = 0; - /* Only useful for established sessions */ if (cp->state != IP_VS_TCP_S_ESTABLISHED) return 1; diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c index a11674806707..46d1b26a468e 100644 --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c @@ -611,16 +611,15 @@ __nf_conntrack_confirm(struct sk_buff *skb) */ NF_CT_ASSERT(!nf_ct_is_confirmed(ct)); pr_debug("Confirming conntrack %p\n", ct); - /* We have to check the DYING flag inside the lock to prevent - a race against nf_ct_get_next_corpse() possibly called from - user context, else we insert an already 'dead' hash, blocking - further use of that particular connection -JM */ + /* We have to check the DYING flag after unlink to prevent + * a race against nf_ct_get_next_corpse() possibly called from + * user context, else we insert an already 'dead' hash, blocking + * further use of that particular connection -JM. + */ + nf_ct_del_from_dying_or_unconfirmed_list(ct); - if (unlikely(nf_ct_is_dying(ct))) { - nf_conntrack_double_unlock(hash, reply_hash); - local_bh_enable(); - return NF_ACCEPT; - } + if (unlikely(nf_ct_is_dying(ct))) + goto out; /* See if there's one in the list already, including reverse: NAT could have grabbed it without realizing, since we're @@ -636,8 +635,6 @@ __nf_conntrack_confirm(struct sk_buff *skb) zone == nf_ct_zone(nf_ct_tuplehash_to_ctrack(h))) goto out; - nf_ct_del_from_dying_or_unconfirmed_list(ct); - /* Timer relative to confirmation time, not original setting time, otherwise we'd get timer wrap in weird delay cases. */ @@ -673,6 +670,7 @@ __nf_conntrack_confirm(struct sk_buff *skb) return NF_ACCEPT; out: + nf_ct_add_to_dying_list(ct); nf_conntrack_double_unlock(hash, reply_hash); NF_CT_STAT_INC(net, insert_failed); local_bh_enable(); diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 129a8daa4abf..3b3ddb4fb9ee 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -713,16 +713,12 @@ static int nft_flush_table(struct nft_ctx *ctx) struct nft_chain *chain, *nc; struct nft_set *set, *ns; - list_for_each_entry_safe(chain, nc, &ctx->table->chains, list) { + list_for_each_entry(chain, &ctx->table->chains, list) { ctx->chain = chain; err = nft_delrule_by_chain(ctx); if (err < 0) goto out; - - err = nft_delchain(ctx); - if (err < 0) - goto out; } list_for_each_entry_safe(set, ns, &ctx->table->sets, list) { @@ -735,6 +731,14 @@ static int nft_flush_table(struct nft_ctx *ctx) goto out; } + list_for_each_entry_safe(chain, nc, &ctx->table->chains, list) { + ctx->chain = chain; + + err = nft_delchain(ctx); + if (err < 0) + goto out; + } + err = nft_deltable(ctx); out: return err; diff --git a/net/netfilter/nfnetlink.c b/net/netfilter/nfnetlink.c index cde4a6702fa3..c421d94c4652 100644 --- a/net/netfilter/nfnetlink.c +++ b/net/netfilter/nfnetlink.c @@ -321,7 +321,8 @@ replay: nlh = nlmsg_hdr(skb); err = 0; - if (nlh->nlmsg_len < NLMSG_HDRLEN) { + if (nlmsg_len(nlh) < sizeof(struct nfgenmsg) || + skb->len < nlh->nlmsg_len) { err = -EINVAL; goto ack; } @@ -469,7 +470,7 @@ static int nfnetlink_bind(struct net *net, int group) int type; if (group <= NFNLGRP_NONE || group > NFNLGRP_MAX) - return -EINVAL; + return 0; type = nfnl_group2type[group]; diff --git a/net/netfilter/nft_nat.c b/net/netfilter/nft_nat.c index afe2b0b45ec4..aff54fb1c8a0 100644 --- a/net/netfilter/nft_nat.c +++ b/net/netfilter/nft_nat.c @@ -65,10 +65,10 @@ static void nft_nat_eval(const struct nft_expr *expr, } if (priv->sreg_proto_min) { - range.min_proto.all = (__force __be16) - data[priv->sreg_proto_min].data[0]; - range.max_proto.all = (__force __be16) - data[priv->sreg_proto_max].data[0]; + range.min_proto.all = + *(__be16 *)&data[priv->sreg_proto_min].data[0]; + range.max_proto.all = + *(__be16 *)&data[priv->sreg_proto_max].data[0]; range.flags |= NF_NAT_RANGE_PROTO_SPECIFIED; } diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index 84ea76ca3f1f..02fdde28dada 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -61,6 +61,7 @@ #include <linux/rhashtable.h> #include <asm/cacheflush.h> #include <linux/hash.h> +#include <linux/genetlink.h> #include <net/net_namespace.h> #include <net/sock.h> @@ -1095,6 +1096,8 @@ static void netlink_remove(struct sock *sk) __sk_del_bind_node(sk); netlink_update_listeners(sk); } + if (sk->sk_protocol == NETLINK_GENERIC) + atomic_inc(&genl_sk_destructing_cnt); netlink_table_ungrab(); } @@ -1211,6 +1214,20 @@ static int netlink_release(struct socket *sock) * will be purged. */ + /* must not acquire netlink_table_lock in any way again before unbind + * and notifying genetlink is done as otherwise it might deadlock + */ + if (nlk->netlink_unbind) { + int i; + + for (i = 0; i < nlk->ngroups; i++) + if (test_bit(i, nlk->groups)) + nlk->netlink_unbind(sock_net(sk), i + 1); + } + if (sk->sk_protocol == NETLINK_GENERIC && + atomic_dec_return(&genl_sk_destructing_cnt) == 0) + wake_up(&genl_sk_destructing_waitq); + sock->sk = NULL; wake_up_interruptible_all(&nlk->wait); @@ -1246,13 +1263,6 @@ static int netlink_release(struct socket *sock) netlink_table_ungrab(); } - if (nlk->netlink_unbind) { - int i; - - for (i = 0; i < nlk->ngroups; i++) - if (test_bit(i, nlk->groups)) - nlk->netlink_unbind(sock_net(sk), i + 1); - } kfree(nlk->groups); nlk->groups = NULL; diff --git a/net/netlink/af_netlink.h b/net/netlink/af_netlink.h index f123a88496f8..f1c31b39aa3e 100644 --- a/net/netlink/af_netlink.h +++ b/net/netlink/af_netlink.h @@ -2,6 +2,7 @@ #define _AF_NETLINK_H #include <linux/rhashtable.h> +#include <linux/atomic.h> #include <net/sock.h> #define NLGRPSZ(x) (ALIGN(x, sizeof(unsigned long) * 8) / 8) diff --git a/net/netlink/genetlink.c b/net/netlink/genetlink.c index 2e11061ef885..ee57459fc258 100644 --- a/net/netlink/genetlink.c +++ b/net/netlink/genetlink.c @@ -23,6 +23,9 @@ static DEFINE_MUTEX(genl_mutex); /* serialization of message processing */ static DECLARE_RWSEM(cb_lock); +atomic_t genl_sk_destructing_cnt = ATOMIC_INIT(0); +DECLARE_WAIT_QUEUE_HEAD(genl_sk_destructing_waitq); + void genl_lock(void) { mutex_lock(&genl_mutex); @@ -435,15 +438,18 @@ int genl_unregister_family(struct genl_family *family) genl_lock_all(); - genl_unregister_mc_groups(family); - list_for_each_entry(rc, genl_family_chain(family->id), family_list) { if (family->id != rc->id || strcmp(rc->name, family->name)) continue; + genl_unregister_mc_groups(family); + list_del(&rc->family_list); family->n_ops = 0; - genl_unlock_all(); + up_write(&cb_lock); + wait_event(genl_sk_destructing_waitq, + atomic_read(&genl_sk_destructing_cnt) == 0); + genl_unlock(); kfree(family->attrbuf); genl_ctrl_event(CTRL_CMD_DELFAMILY, family, NULL, 0); @@ -985,7 +991,7 @@ static struct genl_multicast_group genl_ctrl_groups[] = { static int genl_bind(struct net *net, int group) { - int i, err = 0; + int i, err = -ENOENT; down_read(&cb_lock); for (i = 0; i < GENL_FAM_TAB_SIZE; i++) { @@ -1014,7 +1020,6 @@ static int genl_bind(struct net *net, int group) static void genl_unbind(struct net *net, int group) { int i; - bool found = false; down_read(&cb_lock); for (i = 0; i < GENL_FAM_TAB_SIZE; i++) { @@ -1027,14 +1032,11 @@ static void genl_unbind(struct net *net, int group) if (f->mcast_unbind) f->mcast_unbind(net, fam_grp); - found = true; break; } } } up_read(&cb_lock); - - WARN_ON(!found); } static int __net_init genl_pernet_init(struct net *net) diff --git a/net/openvswitch/datapath.c b/net/openvswitch/datapath.c index 4e9a5f035cbc..b07349e82d78 100644 --- a/net/openvswitch/datapath.c +++ b/net/openvswitch/datapath.c @@ -524,7 +524,7 @@ static int ovs_packet_cmd_execute(struct sk_buff *skb, struct genl_info *info) struct vport *input_vport; int len; int err; - bool log = !a[OVS_FLOW_ATTR_PROBE]; + bool log = !a[OVS_PACKET_ATTR_PROBE]; err = -EINVAL; if (!a[OVS_PACKET_ATTR_PACKET] || !a[OVS_PACKET_ATTR_KEY] || @@ -610,6 +610,7 @@ static const struct nla_policy packet_policy[OVS_PACKET_ATTR_MAX + 1] = { [OVS_PACKET_ATTR_PACKET] = { .len = ETH_HLEN }, [OVS_PACKET_ATTR_KEY] = { .type = NLA_NESTED }, [OVS_PACKET_ATTR_ACTIONS] = { .type = NLA_NESTED }, + [OVS_PACKET_ATTR_PROBE] = { .type = NLA_FLAG }, }; static const struct genl_ops dp_packet_genl_ops[] = { diff --git a/net/openvswitch/flow.c b/net/openvswitch/flow.c index 70bef2ab7f2b..da2fae0873a5 100644 --- a/net/openvswitch/flow.c +++ b/net/openvswitch/flow.c @@ -70,6 +70,7 @@ void ovs_flow_stats_update(struct sw_flow *flow, __be16 tcp_flags, { struct flow_stats *stats; int node = numa_node_id(); + int len = skb->len + (vlan_tx_tag_present(skb) ? VLAN_HLEN : 0); stats = rcu_dereference(flow->stats[node]); @@ -105,7 +106,7 @@ void ovs_flow_stats_update(struct sw_flow *flow, __be16 tcp_flags, if (likely(new_stats)) { new_stats->used = jiffies; new_stats->packet_count = 1; - new_stats->byte_count = skb->len; + new_stats->byte_count = len; new_stats->tcp_flags = tcp_flags; spin_lock_init(&new_stats->lock); @@ -120,7 +121,7 @@ void ovs_flow_stats_update(struct sw_flow *flow, __be16 tcp_flags, stats->used = jiffies; stats->packet_count++; - stats->byte_count += skb->len; + stats->byte_count += len; stats->tcp_flags |= tcp_flags; unlock: spin_unlock(&stats->lock); diff --git a/net/openvswitch/vport.c b/net/openvswitch/vport.c index 53f3ebbfceab..2034c6d9cb5a 100644 --- a/net/openvswitch/vport.c +++ b/net/openvswitch/vport.c @@ -480,7 +480,7 @@ void ovs_vport_receive(struct vport *vport, struct sk_buff *skb, stats = this_cpu_ptr(vport->percpu_stats); u64_stats_update_begin(&stats->syncp); stats->rx_packets++; - stats->rx_bytes += skb->len; + stats->rx_bytes += skb->len + (vlan_tx_tag_present(skb) ? VLAN_HLEN : 0); u64_stats_update_end(&stats->syncp); OVS_CB(skb)->input_vport = vport; diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 6880f34a529a..9cfe2e1dd8b5 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -2517,7 +2517,7 @@ static int packet_snd(struct socket *sock, struct msghdr *msg, size_t len) err = -EINVAL; if (sock->type == SOCK_DGRAM) { offset = dev_hard_header(skb, dev, ntohs(proto), addr, NULL, len); - if (unlikely(offset) < 0) + if (unlikely(offset < 0)) goto out_free; } else { if (ll_header_truncated(dev, len)) diff --git a/net/sctp/socket.c b/net/sctp/socket.c index 2625eccb77d5..aafe94bf292e 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -1603,7 +1603,7 @@ static int sctp_sendmsg(struct kiocb *iocb, struct sock *sk, sctp_assoc_t associd = 0; sctp_cmsgs_t cmsgs = { NULL }; sctp_scope_t scope; - bool fill_sinfo_ttl = false; + bool fill_sinfo_ttl = false, wait_connect = false; struct sctp_datamsg *datamsg; int msg_flags = msg->msg_flags; __u16 sinfo_flags = 0; @@ -1943,6 +1943,7 @@ static int sctp_sendmsg(struct kiocb *iocb, struct sock *sk, if (err < 0) goto out_free; + wait_connect = true; pr_debug("%s: we associated primitively\n", __func__); } @@ -1980,6 +1981,11 @@ static int sctp_sendmsg(struct kiocb *iocb, struct sock *sk, sctp_datamsg_put(datamsg); err = msg_len; + if (unlikely(wait_connect)) { + timeo = sock_sndtimeo(sk, msg_flags & MSG_DONTWAIT); + sctp_wait_for_connect(asoc, &timeo); + } + /* If we are already past ASSOCIATE, the lower * layers are responsible for association cleanup. */ diff --git a/net/sunrpc/xdr.c b/net/sunrpc/xdr.c index 1cb61242e55e..4439ac4c1b53 100644 --- a/net/sunrpc/xdr.c +++ b/net/sunrpc/xdr.c @@ -606,7 +606,7 @@ void xdr_truncate_encode(struct xdr_stream *xdr, size_t len) struct kvec *head = buf->head; struct kvec *tail = buf->tail; int fraglen; - int new, old; + int new; if (len > buf->len) { WARN_ON_ONCE(1); @@ -629,8 +629,8 @@ void xdr_truncate_encode(struct xdr_stream *xdr, size_t len) buf->len -= fraglen; new = buf->page_base + buf->page_len; - old = new + fraglen; - xdr->page_ptr -= (old >> PAGE_SHIFT) - (new >> PAGE_SHIFT); + + xdr->page_ptr = buf->pages + (new >> PAGE_SHIFT); if (buf->page_len) { xdr->p = page_address(*xdr->page_ptr); diff --git a/net/tipc/bcast.c b/net/tipc/bcast.c index 96ceefeb9daf..a9e174fc0f91 100644 --- a/net/tipc/bcast.c +++ b/net/tipc/bcast.c @@ -220,10 +220,11 @@ static void bclink_retransmit_pkt(u32 after, u32 to) struct sk_buff *skb; skb_queue_walk(&bcl->outqueue, skb) { - if (more(buf_seqno(skb), after)) + if (more(buf_seqno(skb), after)) { + tipc_link_retransmit(bcl, skb, mod(to - after)); break; + } } - tipc_link_retransmit(bcl, skb, mod(to - after)); } /** diff --git a/net/wireless/reg.c b/net/wireless/reg.c index 7b8309840d4e..d39d1cbc86b1 100644 --- a/net/wireless/reg.c +++ b/net/wireless/reg.c @@ -1530,45 +1530,40 @@ static void reg_call_notifier(struct wiphy *wiphy, static bool reg_wdev_chan_valid(struct wiphy *wiphy, struct wireless_dev *wdev) { - struct ieee80211_channel *ch; struct cfg80211_chan_def chandef; struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); - bool ret = true; + enum nl80211_iftype iftype; wdev_lock(wdev); + iftype = wdev->iftype; + /* make sure the interface is active */ if (!wdev->netdev || !netif_running(wdev->netdev)) - goto out; + goto wdev_inactive_unlock; - switch (wdev->iftype) { + switch (iftype) { case NL80211_IFTYPE_AP: case NL80211_IFTYPE_P2P_GO: if (!wdev->beacon_interval) - goto out; - - ret = cfg80211_reg_can_beacon(wiphy, - &wdev->chandef, wdev->iftype); + goto wdev_inactive_unlock; + chandef = wdev->chandef; break; case NL80211_IFTYPE_ADHOC: if (!wdev->ssid_len) - goto out; - - ret = cfg80211_reg_can_beacon(wiphy, - &wdev->chandef, wdev->iftype); + goto wdev_inactive_unlock; + chandef = wdev->chandef; break; case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: if (!wdev->current_bss || !wdev->current_bss->pub.channel) - goto out; + goto wdev_inactive_unlock; - ch = wdev->current_bss->pub.channel; - if (rdev->ops->get_channel && - !rdev_get_channel(rdev, wdev, &chandef)) - ret = cfg80211_chandef_usable(wiphy, &chandef, - IEEE80211_CHAN_DISABLED); - else - ret = !(ch->flags & IEEE80211_CHAN_DISABLED); + if (!rdev->ops->get_channel || + rdev_get_channel(rdev, wdev, &chandef)) + cfg80211_chandef_create(&chandef, + wdev->current_bss->pub.channel, + NL80211_CHAN_NO_HT); break; case NL80211_IFTYPE_MONITOR: case NL80211_IFTYPE_AP_VLAN: @@ -1581,9 +1576,26 @@ static bool reg_wdev_chan_valid(struct wiphy *wiphy, struct wireless_dev *wdev) break; } -out: wdev_unlock(wdev); - return ret; + + switch (iftype) { + case NL80211_IFTYPE_AP: + case NL80211_IFTYPE_P2P_GO: + case NL80211_IFTYPE_ADHOC: + return cfg80211_reg_can_beacon(wiphy, &chandef, iftype); + case NL80211_IFTYPE_STATION: + case NL80211_IFTYPE_P2P_CLIENT: + return cfg80211_chandef_usable(wiphy, &chandef, + IEEE80211_CHAN_DISABLED); + default: + break; + } + + return true; + +wdev_inactive_unlock: + wdev_unlock(wdev); + return true; } static void reg_leave_invalid_chans(struct wiphy *wiphy) diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean index 1bca180db8ad..627f8cbbedb8 100644 --- a/scripts/Makefile.clean +++ b/scripts/Makefile.clean @@ -42,19 +42,19 @@ __clean-files := $(extra-y) $(extra-m) $(extra-) \ __clean-files := $(filter-out $(no-clean-files), $(__clean-files)) -# as clean-files is given relative to the current directory, this adds -# a $(obj) prefix, except for absolute paths +# clean-files is given relative to the current directory, unless it +# starts with $(objtree)/ (which means "./", so do not add "./" unless +# you want to delete a file from the toplevel object directory). __clean-files := $(wildcard \ - $(addprefix $(obj)/, $(filter-out /%, $(__clean-files))) \ - $(filter /%, $(__clean-files))) + $(addprefix $(obj)/, $(filter-out $(objtree)/%, $(__clean-files))) \ + $(filter $(objtree)/%, $(__clean-files))) -# as clean-dirs is given relative to the current directory, this adds -# a $(obj) prefix, except for absolute paths +# same as clean-files __clean-dirs := $(wildcard \ - $(addprefix $(obj)/, $(filter-out /%, $(clean-dirs))) \ - $(filter /%, $(clean-dirs))) + $(addprefix $(obj)/, $(filter-out $(objtree)/%, $(clean-dirs))) \ + $(filter $(objtree)/%, $(clean-dirs))) # ========================================================================== diff --git a/scripts/recordmcount.pl b/scripts/recordmcount.pl index 56ea99a12ab7..537c38ca2e1c 100755 --- a/scripts/recordmcount.pl +++ b/scripts/recordmcount.pl @@ -255,7 +255,6 @@ if ($arch eq "x86_64") { # force flags for this arch $ld .= " -m shlelf_linux"; $objcopy .= " -O elf32-sh-linux"; - $cc .= " -m32"; } elsif ($arch eq "powerpc") { $local_regex = "^[0-9a-fA-F]+\\s+t\\s+(\\.?\\S+)"; diff --git a/security/keys/gc.c b/security/keys/gc.c index 9609a7f0faea..c7952375ac53 100644 --- a/security/keys/gc.c +++ b/security/keys/gc.c @@ -148,12 +148,12 @@ static noinline void key_gc_unused_keys(struct list_head *keys) if (test_bit(KEY_FLAG_INSTANTIATED, &key->flags)) atomic_dec(&key->user->nikeys); - key_user_put(key->user); - /* now throw away the key memory */ if (key->type->destroy) key->type->destroy(key); + key_user_put(key->user); + kfree(key->description); #ifdef KEY_DEBUGGING diff --git a/sound/firewire/amdtp.c b/sound/firewire/amdtp.c index 3badc70124ab..0d580186ef1a 100644 --- a/sound/firewire/amdtp.c +++ b/sound/firewire/amdtp.c @@ -21,7 +21,19 @@ #define CYCLES_PER_SECOND 8000 #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND) -#define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 µs */ +/* + * Nominally 3125 bytes/second, but the MIDI port's clock might be + * 1% too slow, and the bus clock 100 ppm too fast. + */ +#define MIDI_BYTES_PER_SECOND 3093 + +/* + * Several devices look only at the first eight data blocks. + * In any case, this is more than enough for the MIDI data rate. + */ +#define MAX_MIDI_RX_BLOCKS 8 + +#define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 µs */ /* isochronous header parameters */ #define ISO_DATA_LENGTH_SHIFT 16 @@ -78,8 +90,6 @@ int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit, s->callbacked = false; s->sync_slave = NULL; - s->rx_blocks_for_midi = UINT_MAX; - return 0; } EXPORT_SYMBOL(amdtp_stream_init); @@ -222,6 +232,14 @@ sfc_found: for (i = 0; i < pcm_channels; i++) s->pcm_positions[i] = i; s->midi_position = s->pcm_channels; + + /* + * We do not know the actual MIDI FIFO size of most devices. Just + * assume two bytes, i.e., one byte can be received over the bus while + * the previous one is transmitted over MIDI. + * (The value here is adjusted for midi_ratelimit_per_packet().) + */ + s->midi_fifo_limit = rate - MIDI_BYTES_PER_SECOND * s->syt_interval + 1; } EXPORT_SYMBOL(amdtp_stream_set_parameters); @@ -463,6 +481,36 @@ static void amdtp_fill_pcm_silence(struct amdtp_stream *s, } } +/* + * To avoid sending MIDI bytes at too high a rate, assume that the receiving + * device has a FIFO, and track how much it is filled. This values increases + * by one whenever we send one byte in a packet, but the FIFO empties at + * a constant rate independent of our packet rate. One packet has syt_interval + * samples, so the number of bytes that empty out of the FIFO, per packet(!), + * is MIDI_BYTES_PER_SECOND * syt_interval / sample_rate. To avoid storing + * fractional values, the values in midi_fifo_used[] are measured in bytes + * multiplied by the sample rate. + */ +static bool midi_ratelimit_per_packet(struct amdtp_stream *s, unsigned int port) +{ + int used; + + used = s->midi_fifo_used[port]; + if (used == 0) /* common shortcut */ + return true; + + used -= MIDI_BYTES_PER_SECOND * s->syt_interval; + used = max(used, 0); + s->midi_fifo_used[port] = used; + + return used < s->midi_fifo_limit; +} + +static void midi_rate_use_one_byte(struct amdtp_stream *s, unsigned int port) +{ + s->midi_fifo_used[port] += amdtp_rate_table[s->sfc]; +} + static void amdtp_fill_midi(struct amdtp_stream *s, __be32 *buffer, unsigned int frames) { @@ -470,16 +518,21 @@ static void amdtp_fill_midi(struct amdtp_stream *s, u8 *b; for (f = 0; f < frames; f++) { - buffer[s->midi_position] = 0; b = (u8 *)&buffer[s->midi_position]; port = (s->data_block_counter + f) % 8; - if ((f >= s->rx_blocks_for_midi) || - (s->midi[port] == NULL) || - (snd_rawmidi_transmit(s->midi[port], b + 1, 1) <= 0)) - b[0] = 0x80; - else + if (f < MAX_MIDI_RX_BLOCKS && + midi_ratelimit_per_packet(s, port) && + s->midi[port] != NULL && + snd_rawmidi_transmit(s->midi[port], &b[1], 1) == 1) { + midi_rate_use_one_byte(s, port); b[0] = 0x81; + } else { + b[0] = 0x80; + b[1] = 0; + } + b[2] = 0; + b[3] = 0; buffer += s->data_block_quadlets; } diff --git a/sound/firewire/amdtp.h b/sound/firewire/amdtp.h index e6e8926275b0..8a03a91e728b 100644 --- a/sound/firewire/amdtp.h +++ b/sound/firewire/amdtp.h @@ -148,13 +148,12 @@ struct amdtp_stream { bool double_pcm_frames; struct snd_rawmidi_substream *midi[AMDTP_MAX_CHANNELS_FOR_MIDI * 8]; + int midi_fifo_limit; + int midi_fifo_used[AMDTP_MAX_CHANNELS_FOR_MIDI * 8]; /* quirk: fixed interval of dbc between previos/current packets. */ unsigned int tx_dbc_interval; - /* quirk: the first count of data blocks in an rx packet for MIDI */ - unsigned int rx_blocks_for_midi; - bool callbacked; wait_queue_head_t callback_wait; struct amdtp_stream *sync_slave; diff --git a/sound/firewire/bebob/bebob_stream.c b/sound/firewire/bebob/bebob_stream.c index 1aab0a32870c..0ebcabfdc7ce 100644 --- a/sound/firewire/bebob/bebob_stream.c +++ b/sound/firewire/bebob/bebob_stream.c @@ -484,13 +484,6 @@ int snd_bebob_stream_init_duplex(struct snd_bebob *bebob) amdtp_stream_destroy(&bebob->rx_stream); destroy_both_connections(bebob); } - /* - * The firmware for these devices ignore MIDI messages in more than - * first 8 data blocks of an received AMDTP packet. - */ - if (bebob->spec == &maudio_fw410_spec || - bebob->spec == &maudio_special_spec) - bebob->rx_stream.rx_blocks_for_midi = 8; end: return err; } diff --git a/sound/firewire/fireworks/fireworks_stream.c b/sound/firewire/fireworks/fireworks_stream.c index b985fc5ebdc6..4f440e163667 100644 --- a/sound/firewire/fireworks/fireworks_stream.c +++ b/sound/firewire/fireworks/fireworks_stream.c @@ -179,11 +179,6 @@ int snd_efw_stream_init_duplex(struct snd_efw *efw) destroy_stream(efw, &efw->tx_stream); goto end; } - /* - * Fireworks ignores MIDI messages in more than first 8 data - * blocks of an received AMDTP packet. - */ - efw->rx_stream.rx_blocks_for_midi = 8; /* set IEC61883 compliant mode (actually not fully compliant...) */ err = snd_efw_command_set_tx_mode(efw, SND_EFW_TRANSPORT_MODE_IEC61883); diff --git a/sound/firewire/fireworks/fireworks_transaction.c b/sound/firewire/fireworks/fireworks_transaction.c index 255dabc6fc33..2a85e4209f0b 100644 --- a/sound/firewire/fireworks/fireworks_transaction.c +++ b/sound/firewire/fireworks/fireworks_transaction.c @@ -124,7 +124,7 @@ copy_resp_to_buf(struct snd_efw *efw, void *data, size_t length, int *rcode) spin_lock_irq(&efw->lock); t = (struct snd_efw_transaction *)data; - length = min_t(size_t, t->length * sizeof(t->length), length); + length = min_t(size_t, be32_to_cpu(t->length) * sizeof(u32), length); if (efw->push_ptr < efw->pull_ptr) capacity = (unsigned int)(efw->pull_ptr - efw->push_ptr); diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index 5f13d2d18079..b422e406a9cb 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -3353,6 +3353,7 @@ static const struct hda_codec_preset snd_hda_preset_hdmi[] = { { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch }, { .id = 0x10de0070, .name = "GPU 70 HDMI/DP", .patch = patch_nvhdmi }, { .id = 0x10de0071, .name = "GPU 71 HDMI/DP", .patch = patch_nvhdmi }, +{ .id = 0x10de0072, .name = "GPU 72 HDMI/DP", .patch = patch_nvhdmi }, { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch }, { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi }, { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi }, @@ -3413,6 +3414,7 @@ MODULE_ALIAS("snd-hda-codec-id:10de0060"); MODULE_ALIAS("snd-hda-codec-id:10de0067"); MODULE_ALIAS("snd-hda-codec-id:10de0070"); MODULE_ALIAS("snd-hda-codec-id:10de0071"); +MODULE_ALIAS("snd-hda-codec-id:10de0072"); MODULE_ALIAS("snd-hda-codec-id:10de8001"); MODULE_ALIAS("snd-hda-codec-id:11069f80"); MODULE_ALIAS("snd-hda-codec-id:11069f81"); diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index 4f6413e01c13..605d14003d25 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c @@ -568,9 +568,9 @@ static void stac_store_hints(struct hda_codec *codec) spec->gpio_mask; } if (get_int_hint(codec, "gpio_dir", &spec->gpio_dir)) - spec->gpio_mask &= spec->gpio_mask; - if (get_int_hint(codec, "gpio_data", &spec->gpio_data)) spec->gpio_dir &= spec->gpio_mask; + if (get_int_hint(codec, "gpio_data", &spec->gpio_data)) + spec->gpio_data &= spec->gpio_mask; if (get_int_hint(codec, "eapd_mask", &spec->eapd_mask)) spec->eapd_mask &= spec->gpio_mask; if (get_int_hint(codec, "gpio_mute", &spec->gpio_mute)) diff --git a/sound/usb/caiaq/audio.c b/sound/usb/caiaq/audio.c index 272844746135..327f8642ca80 100644 --- a/sound/usb/caiaq/audio.c +++ b/sound/usb/caiaq/audio.c @@ -816,7 +816,7 @@ int snd_usb_caiaq_audio_init(struct snd_usb_caiaqdev *cdev) return -EINVAL; } - if (cdev->n_streams < 2) { + if (cdev->n_streams < 1) { dev_err(dev, "bogus number of streams: %d\n", cdev->n_streams); return -EINVAL; } diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index 41650d5b93b7..3e2ef61c627b 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -913,6 +913,7 @@ static void volume_control_quirks(struct usb_mixer_elem_info *cval, case USB_ID(0x046d, 0x0807): /* Logitech Webcam C500 */ case USB_ID(0x046d, 0x0808): case USB_ID(0x046d, 0x0809): + case USB_ID(0x046d, 0x0819): /* Logitech Webcam C210 */ case USB_ID(0x046d, 0x081b): /* HD Webcam c310 */ case USB_ID(0x046d, 0x081d): /* HD Webcam c510 */ case USB_ID(0x046d, 0x0825): /* HD Webcam c270 */ diff --git a/tools/include/asm-generic/bitops.h b/tools/include/asm-generic/bitops.h index 6eedba1f7732..653d1bad77de 100644 --- a/tools/include/asm-generic/bitops.h +++ b/tools/include/asm-generic/bitops.h @@ -22,6 +22,8 @@ #error only <linux/bitops.h> can be included directly #endif +#include <asm-generic/bitops/hweight.h> + #include <asm-generic/bitops/atomic.h> #endif /* __TOOLS_ASM_GENERIC_BITOPS_H */ diff --git a/tools/include/asm-generic/bitops/arch_hweight.h b/tools/include/asm-generic/bitops/arch_hweight.h new file mode 100644 index 000000000000..318bb2b202b0 --- /dev/null +++ b/tools/include/asm-generic/bitops/arch_hweight.h @@ -0,0 +1 @@ +#include "../../../../include/asm-generic/bitops/arch_hweight.h" diff --git a/tools/include/asm-generic/bitops/const_hweight.h b/tools/include/asm-generic/bitops/const_hweight.h new file mode 100644 index 000000000000..0afd644aff83 --- /dev/null +++ b/tools/include/asm-generic/bitops/const_hweight.h @@ -0,0 +1 @@ +#include "../../../../include/asm-generic/bitops/const_hweight.h" diff --git a/tools/include/asm-generic/bitops/hweight.h b/tools/include/asm-generic/bitops/hweight.h new file mode 100644 index 000000000000..290120c01a8e --- /dev/null +++ b/tools/include/asm-generic/bitops/hweight.h @@ -0,0 +1,7 @@ +#ifndef _TOOLS_LINUX_ASM_GENERIC_BITOPS_HWEIGHT_H_ +#define _TOOLS_LINUX_ASM_GENERIC_BITOPS_HWEIGHT_H_ + +#include <asm-generic/bitops/arch_hweight.h> +#include <asm-generic/bitops/const_hweight.h> + +#endif /* _TOOLS_LINUX_ASM_GENERIC_BITOPS_HWEIGHT_H_ */ diff --git a/tools/include/linux/bitops.h b/tools/include/linux/bitops.h index 26005a15e7e2..5ad9ee1dd7f6 100644 --- a/tools/include/linux/bitops.h +++ b/tools/include/linux/bitops.h @@ -1,9 +1,9 @@ #ifndef _TOOLS_LINUX_BITOPS_H_ #define _TOOLS_LINUX_BITOPS_H_ +#include <asm/types.h> #include <linux/kernel.h> #include <linux/compiler.h> -#include <asm/hweight.h> #ifndef __WORDSIZE #define __WORDSIZE (__SIZEOF_LONG__ * 8) @@ -19,6 +19,11 @@ #define BITS_TO_U32(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(u32)) #define BITS_TO_BYTES(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE) +extern unsigned int __sw_hweight8(unsigned int w); +extern unsigned int __sw_hweight16(unsigned int w); +extern unsigned int __sw_hweight32(unsigned int w); +extern unsigned long __sw_hweight64(__u64 w); + /* * Include this here because some architectures need generic_ffs/fls in * scope diff --git a/tools/lib/api/fs/debugfs.c b/tools/lib/api/fs/debugfs.c index a74fba6d7743..86ea2d7b8845 100644 --- a/tools/lib/api/fs/debugfs.c +++ b/tools/lib/api/fs/debugfs.c @@ -67,7 +67,7 @@ int debugfs_valid_mountpoint(const char *debugfs) if (statfs(debugfs, &st_fs) < 0) return -ENOENT; - else if (st_fs.f_type != (long) DEBUGFS_MAGIC) + else if ((long)st_fs.f_type != (long)DEBUGFS_MAGIC) return -ENOENT; return 0; diff --git a/tools/lib/api/fs/fs.c b/tools/lib/api/fs/fs.c index 65d9be3f9887..128ef6332a6b 100644 --- a/tools/lib/api/fs/fs.c +++ b/tools/lib/api/fs/fs.c @@ -79,7 +79,7 @@ static int fs__valid_mount(const char *fs, long magic) if (statfs(fs, &st_fs) < 0) return -ENOENT; - else if (st_fs.f_type != magic) + else if ((long)st_fs.f_type != magic) return -ENOENT; return 0; diff --git a/tools/lib/lockdep/preload.c b/tools/lib/lockdep/preload.c index 6f803609e498..0b0112c80f22 100644 --- a/tools/lib/lockdep/preload.c +++ b/tools/lib/lockdep/preload.c @@ -317,7 +317,7 @@ int pthread_mutex_destroy(pthread_mutex_t *mutex) * * TODO: Hook into free() and add that check there as well. */ - debug_check_no_locks_freed(mutex, mutex + sizeof(*mutex)); + debug_check_no_locks_freed(mutex, sizeof(*mutex)); __del_lock(__get_lock(mutex)); return ll_pthread_mutex_destroy(mutex); } @@ -341,7 +341,7 @@ int pthread_rwlock_destroy(pthread_rwlock_t *rwlock) { try_init_preload(); - debug_check_no_locks_freed(rwlock, rwlock + sizeof(*rwlock)); + debug_check_no_locks_freed(rwlock, sizeof(*rwlock)); __del_lock(__get_lock(rwlock)); return ll_pthread_rwlock_destroy(rwlock); } diff --git a/tools/perf/MANIFEST b/tools/perf/MANIFEST index 83e2887f91a3..fbbfdc39271d 100644 --- a/tools/perf/MANIFEST +++ b/tools/perf/MANIFEST @@ -6,12 +6,15 @@ tools/lib/symbol/kallsyms.c tools/lib/symbol/kallsyms.h tools/lib/util/find_next_bit.c tools/include/asm/bug.h +tools/include/asm-generic/bitops/arch_hweight.h tools/include/asm-generic/bitops/atomic.h +tools/include/asm-generic/bitops/const_hweight.h tools/include/asm-generic/bitops/__ffs.h tools/include/asm-generic/bitops/__fls.h tools/include/asm-generic/bitops/find.h tools/include/asm-generic/bitops/fls64.h tools/include/asm-generic/bitops/fls.h +tools/include/asm-generic/bitops/hweight.h tools/include/asm-generic/bitops.h tools/include/linux/bitops.h tools/include/linux/compiler.h @@ -19,6 +22,8 @@ tools/include/linux/export.h tools/include/linux/hash.h tools/include/linux/log2.h tools/include/linux/types.h +include/asm-generic/bitops/arch_hweight.h +include/asm-generic/bitops/const_hweight.h include/asm-generic/bitops/fls64.h include/asm-generic/bitops/__fls.h include/asm-generic/bitops/fls.h @@ -29,6 +34,7 @@ include/linux/list.h include/linux/hash.h include/linux/stringify.h lib/find_next_bit.c +lib/hweight.c lib/rbtree.c include/linux/swab.h arch/*/include/asm/unistd*.h diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 67a03a825b3c..aa6a50447c32 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -232,12 +232,15 @@ LIB_H += ../include/linux/hash.h LIB_H += ../../include/linux/stringify.h LIB_H += util/include/linux/bitmap.h LIB_H += ../include/linux/bitops.h +LIB_H += ../include/asm-generic/bitops/arch_hweight.h LIB_H += ../include/asm-generic/bitops/atomic.h +LIB_H += ../include/asm-generic/bitops/const_hweight.h LIB_H += ../include/asm-generic/bitops/find.h LIB_H += ../include/asm-generic/bitops/fls64.h LIB_H += ../include/asm-generic/bitops/fls.h LIB_H += ../include/asm-generic/bitops/__ffs.h LIB_H += ../include/asm-generic/bitops/__fls.h +LIB_H += ../include/asm-generic/bitops/hweight.h LIB_H += ../include/asm-generic/bitops.h LIB_H += ../include/linux/compiler.h LIB_H += ../include/linux/log2.h @@ -255,7 +258,6 @@ LIB_H += util/include/linux/linkage.h LIB_H += util/include/asm/asm-offsets.h LIB_H += ../include/asm/bug.h LIB_H += util/include/asm/byteorder.h -LIB_H += util/include/asm/hweight.h LIB_H += util/include/asm/swab.h LIB_H += util/include/asm/system.h LIB_H += util/include/asm/uaccess.h @@ -462,10 +464,12 @@ BUILTIN_OBJS += $(OUTPUT)builtin-bench.o # Benchmark modules BUILTIN_OBJS += $(OUTPUT)bench/sched-messaging.o BUILTIN_OBJS += $(OUTPUT)bench/sched-pipe.o -ifeq ($(RAW_ARCH),x86_64) +ifeq ($(ARCH), x86) +ifeq ($(IS_64_BIT), 1) BUILTIN_OBJS += $(OUTPUT)bench/mem-memcpy-x86-64-asm.o BUILTIN_OBJS += $(OUTPUT)bench/mem-memset-x86-64-asm.o endif +endif BUILTIN_OBJS += $(OUTPUT)bench/mem-memcpy.o BUILTIN_OBJS += $(OUTPUT)bench/futex-hash.o BUILTIN_OBJS += $(OUTPUT)bench/futex-wake.o @@ -743,6 +747,9 @@ $(OUTPUT)util/kallsyms.o: ../lib/symbol/kallsyms.c $(OUTPUT)PERF-CFLAGS $(OUTPUT)util/rbtree.o: ../../lib/rbtree.c $(OUTPUT)PERF-CFLAGS $(QUIET_CC)$(CC) -o $@ -c $(CFLAGS) -Wno-unused-parameter -DETC_PERFCONFIG='"$(ETC_PERFCONFIG_SQ)"' $< +$(OUTPUT)util/hweight.o: ../../lib/hweight.c $(OUTPUT)PERF-CFLAGS + $(QUIET_CC)$(CC) -o $@ -c $(CFLAGS) -Wno-unused-parameter -DETC_PERFCONFIG='"$(ETC_PERFCONFIG_SQ)"' $< + $(OUTPUT)util/find_next_bit.o: ../lib/util/find_next_bit.c $(OUTPUT)PERF-CFLAGS $(QUIET_CC)$(CC) -o $@ -c $(CFLAGS) -Wno-unused-parameter -DETC_PERFCONFIG='"$(ETC_PERFCONFIG_SQ)"' $< diff --git a/tools/perf/arch/powerpc/util/skip-callchain-idx.c b/tools/perf/arch/powerpc/util/skip-callchain-idx.c index 3bb50eac5542..0c370f81e002 100644 --- a/tools/perf/arch/powerpc/util/skip-callchain-idx.c +++ b/tools/perf/arch/powerpc/util/skip-callchain-idx.c @@ -103,7 +103,7 @@ static Dwarf_Frame *get_eh_frame(Dwfl_Module *mod, Dwarf_Addr pc) return NULL; } - result = dwarf_cfi_addrframe(cfi, pc, &frame); + result = dwarf_cfi_addrframe(cfi, pc-bias, &frame); if (result) { pr_debug("%s(): %s\n", __func__, dwfl_errmsg(-1)); return NULL; @@ -128,7 +128,7 @@ static Dwarf_Frame *get_dwarf_frame(Dwfl_Module *mod, Dwarf_Addr pc) return NULL; } - result = dwarf_cfi_addrframe(cfi, pc, &frame); + result = dwarf_cfi_addrframe(cfi, pc-bias, &frame); if (result) { pr_debug("%s(): %s\n", __func__, dwfl_errmsg(-1)); return NULL; @@ -145,7 +145,7 @@ static Dwarf_Frame *get_dwarf_frame(Dwfl_Module *mod, Dwarf_Addr pc) * yet used) * -1 in case of errors */ -static int check_return_addr(struct dso *dso, Dwarf_Addr pc) +static int check_return_addr(struct dso *dso, u64 map_start, Dwarf_Addr pc) { int rc = -1; Dwfl *dwfl; @@ -155,6 +155,7 @@ static int check_return_addr(struct dso *dso, Dwarf_Addr pc) Dwarf_Addr start = pc; Dwarf_Addr end = pc; bool signalp; + const char *exec_file = dso->long_name; dwfl = dso->dwfl; @@ -165,8 +166,10 @@ static int check_return_addr(struct dso *dso, Dwarf_Addr pc) return -1; } - if (dwfl_report_offline(dwfl, "", dso->long_name, -1) == NULL) { - pr_debug("dwfl_report_offline() failed %s\n", + mod = dwfl_report_elf(dwfl, exec_file, exec_file, -1, + map_start, false); + if (!mod) { + pr_debug("dwfl_report_elf() failed %s\n", dwarf_errmsg(-1)); /* * We normally cache the DWARF debug info and never @@ -256,10 +259,10 @@ int arch_skip_callchain_idx(struct thread *thread, struct ip_callchain *chain) return skip_slot; } - rc = check_return_addr(dso, ip); + rc = check_return_addr(dso, al.map->start, ip); - pr_debug("DSO %s, nr %" PRIx64 ", ip 0x%" PRIx64 "rc %d\n", - dso->long_name, chain->nr, ip, rc); + pr_debug("[DSO %s, sym %s, ip 0x%" PRIx64 "] rc %d\n", + dso->long_name, al.sym->name, ip, rc); if (rc == 0) { /* diff --git a/tools/perf/bench/sched-pipe.c b/tools/perf/bench/sched-pipe.c index 07a8d7646a15..005cc283790c 100644 --- a/tools/perf/bench/sched-pipe.c +++ b/tools/perf/bench/sched-pipe.c @@ -19,12 +19,12 @@ #include <stdlib.h> #include <signal.h> #include <sys/wait.h> -#include <linux/unistd.h> #include <string.h> #include <errno.h> #include <assert.h> #include <sys/time.h> #include <sys/types.h> +#include <sys/syscall.h> #include <pthread.h> diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index e7417fe97a97..747f86103599 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -232,7 +232,7 @@ static int __cmd_annotate(struct perf_annotate *ann) if (nr_samples > 0) { total_nr_samples += nr_samples; hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); if (symbol_conf.event_group && !perf_evsel__is_group_leader(pos)) diff --git a/tools/perf/builtin-diff.c b/tools/perf/builtin-diff.c index 1ce425d101a9..1fd96c13f199 100644 --- a/tools/perf/builtin-diff.c +++ b/tools/perf/builtin-diff.c @@ -545,6 +545,42 @@ hist_entry__cmp_compute(struct hist_entry *left, struct hist_entry *right, return __hist_entry__cmp_compute(p_left, p_right, c); } +static int64_t +hist_entry__cmp_nop(struct hist_entry *left __maybe_unused, + struct hist_entry *right __maybe_unused) +{ + return 0; +} + +static int64_t +hist_entry__cmp_baseline(struct hist_entry *left, struct hist_entry *right) +{ + if (sort_compute) + return 0; + + if (left->stat.period == right->stat.period) + return 0; + return left->stat.period > right->stat.period ? 1 : -1; +} + +static int64_t +hist_entry__cmp_delta(struct hist_entry *left, struct hist_entry *right) +{ + return hist_entry__cmp_compute(right, left, COMPUTE_DELTA); +} + +static int64_t +hist_entry__cmp_ratio(struct hist_entry *left, struct hist_entry *right) +{ + return hist_entry__cmp_compute(right, left, COMPUTE_RATIO); +} + +static int64_t +hist_entry__cmp_wdiff(struct hist_entry *left, struct hist_entry *right) +{ + return hist_entry__cmp_compute(right, left, COMPUTE_WEIGHTED_DIFF); +} + static void insert_hist_entry_by_compute(struct rb_root *root, struct hist_entry *he, int c) @@ -605,7 +641,7 @@ static void hists__process(struct hists *hists) hists__precompute(hists); hists__compute_resort(hists); } else { - hists__output_resort(hists); + hists__output_resort(hists, NULL); } hists__fprintf(hists, true, 0, 0, 0, stdout); @@ -1038,27 +1074,35 @@ static void data__hpp_register(struct data__file *d, int idx) fmt->header = hpp__header; fmt->width = hpp__width; fmt->entry = hpp__entry_global; + fmt->cmp = hist_entry__cmp_nop; + fmt->collapse = hist_entry__cmp_nop; /* TODO more colors */ switch (idx) { case PERF_HPP_DIFF__BASELINE: fmt->color = hpp__color_baseline; + fmt->sort = hist_entry__cmp_baseline; break; case PERF_HPP_DIFF__DELTA: fmt->color = hpp__color_delta; + fmt->sort = hist_entry__cmp_delta; break; case PERF_HPP_DIFF__RATIO: fmt->color = hpp__color_ratio; + fmt->sort = hist_entry__cmp_ratio; break; case PERF_HPP_DIFF__WEIGHTED_DIFF: fmt->color = hpp__color_wdiff; + fmt->sort = hist_entry__cmp_wdiff; break; default: + fmt->sort = hist_entry__cmp_nop; break; } init_header(d, dfmt); perf_hpp__column_register(fmt); + perf_hpp__register_sort_field(fmt); } static void ui_init(void) diff --git a/tools/perf/builtin-list.c b/tools/perf/builtin-list.c index 011195e38f21..198f3c3aff95 100644 --- a/tools/perf/builtin-list.c +++ b/tools/perf/builtin-list.c @@ -19,7 +19,9 @@ int cmd_list(int argc, const char **argv, const char *prefix __maybe_unused) { int i; - const struct option list_options[] = { + bool raw_dump = false; + struct option list_options[] = { + OPT_BOOLEAN(0, "raw-dump", &raw_dump, "Dump raw events"), OPT_END() }; const char * const list_usage[] = { @@ -27,11 +29,18 @@ int cmd_list(int argc, const char **argv, const char *prefix __maybe_unused) NULL }; + set_option_flag(list_options, 0, "raw-dump", PARSE_OPT_HIDDEN); + argc = parse_options(argc, argv, list_options, list_usage, PARSE_OPT_STOP_AT_NON_OPTION); setup_pager(); + if (raw_dump) { + print_events(NULL, true); + return 0; + } + if (argc == 0) { print_events(NULL, false); return 0; @@ -53,8 +62,6 @@ int cmd_list(int argc, const char **argv, const char *prefix __maybe_unused) print_hwcache_events(NULL, false); else if (strcmp(argv[i], "pmu") == 0) print_pmu_events(NULL, false); - else if (strcmp(argv[i], "--raw-dump") == 0) - print_events(NULL, true); else { char *sep = strchr(argv[i], ':'), *s; int sep_idx; diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 39367609c707..072ae8ad67fc 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -457,6 +457,19 @@ static void report__collapse_hists(struct report *rep) ui_progress__finish(); } +static void report__output_resort(struct report *rep) +{ + struct ui_progress prog; + struct perf_evsel *pos; + + ui_progress__init(&prog, rep->nr_entries, "Sorting events for output..."); + + evlist__for_each(rep->session->evlist, pos) + hists__output_resort(evsel__hists(pos), &prog); + + ui_progress__finish(); +} + static int __cmd_report(struct report *rep) { int ret; @@ -505,13 +518,20 @@ static int __cmd_report(struct report *rep) if (session_done()) return 0; + /* + * recalculate number of entries after collapsing since it + * might be changed during the collapse phase. + */ + rep->nr_entries = 0; + evlist__for_each(session->evlist, pos) + rep->nr_entries += evsel__hists(pos)->nr_entries; + if (rep->nr_entries == 0) { ui__error("The %s file has no samples!\n", file->path); return 0; } - evlist__for_each(session->evlist, pos) - hists__output_resort(evsel__hists(pos)); + report__output_resort(rep); return report__browse_hists(rep); } diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 0aa7747ff139..616f0fcb4701 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -66,7 +66,6 @@ #include <sys/utsname.h> #include <sys/mman.h> -#include <linux/unistd.h> #include <linux/types.h> static volatile int done; @@ -285,7 +284,7 @@ static void perf_top__print_sym_table(struct perf_top *top) } hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); hists__output_recalc_col_len(hists, top->print_entries - printed); putchar('\n'); @@ -554,7 +553,7 @@ static void perf_top__sort_new_samples(void *arg) } hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); } static void *display_thread_tui(void *arg) diff --git a/tools/perf/config/Makefile b/tools/perf/config/Makefile index 5d4b039fe1ed..648e31ff4021 100644 --- a/tools/perf/config/Makefile +++ b/tools/perf/config/Makefile @@ -20,7 +20,7 @@ NO_PERF_REGS := 1 # Additional ARCH settings for x86 ifeq ($(ARCH),x86) - ifeq (${IS_X86_64}, 1) + ifeq (${IS_64_BIT}, 1) CFLAGS += -DHAVE_ARCH_X86_64_SUPPORT ARCH_INCLUDE = ../../arch/x86/lib/memcpy_64.S ../../arch/x86/lib/memset_64.S LIBUNWIND_LIBS = -lunwind -lunwind-x86_64 diff --git a/tools/perf/config/Makefile.arch b/tools/perf/config/Makefile.arch index 851cd0172a76..ff95a68741d1 100644 --- a/tools/perf/config/Makefile.arch +++ b/tools/perf/config/Makefile.arch @@ -1,7 +1,7 @@ uname_M := $(shell uname -m 2>/dev/null || echo not) -ARCH ?= $(shell echo $(uname_M) | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \ +RAW_ARCH := $(shell echo $(uname_M) | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \ -e s/arm.*/arm/ -e s/sa110/arm/ \ -e s/s390x/s390/ -e s/parisc64/parisc/ \ -e s/ppc.*/powerpc/ -e s/mips.*/mips/ \ @@ -9,23 +9,23 @@ ARCH ?= $(shell echo $(uname_M) | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \ -e s/tile.*/tile/ ) # Additional ARCH settings for x86 -ifeq ($(ARCH),i386) - override ARCH := x86 +ifeq ($(RAW_ARCH),i386) + ARCH ?= x86 endif -ifeq ($(ARCH),x86_64) - override ARCH := x86 - IS_X86_64 := 0 - ifeq (, $(findstring m32,$(CFLAGS))) - IS_X86_64 := $(shell echo __x86_64__ | ${CC} -E -x c - | tail -n 1) - RAW_ARCH := x86_64 +ifeq ($(RAW_ARCH),x86_64) + ARCH ?= x86 + + ifneq (, $(findstring m32,$(CFLAGS))) + RAW_ARCH := x86_32 endif endif -ifeq (${IS_X86_64}, 1) +ARCH ?= $(RAW_ARCH) + +LP64 := $(shell echo __LP64__ | ${CC} ${CFLAGS} -E -x c - | tail -n 1) +ifeq ($(LP64), 1) IS_64_BIT := 1 -else ifeq ($(ARCH),x86) - IS_64_BIT := 0 else - IS_64_BIT := $(shell echo __LP64__ | ${CC} ${CFLAGS} -E -x c - | tail -n 1) + IS_64_BIT := 0 endif diff --git a/tools/perf/perf-sys.h b/tools/perf/perf-sys.h index a3b13d7dc1d4..6ef68165c9db 100644 --- a/tools/perf/perf-sys.h +++ b/tools/perf/perf-sys.h @@ -6,7 +6,6 @@ #include <sys/syscall.h> #include <linux/types.h> #include <linux/perf_event.h> -#include <asm/unistd.h> #if defined(__i386__) #define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") diff --git a/tools/perf/tests/dwarf-unwind.c b/tools/perf/tests/dwarf-unwind.c index ab28cca2cb97..0bf06bec68c7 100644 --- a/tools/perf/tests/dwarf-unwind.c +++ b/tools/perf/tests/dwarf-unwind.c @@ -11,6 +11,9 @@ #include "thread.h" #include "callchain.h" +/* For bsearch. We try to unwind functions in shared object. */ +#include <stdlib.h> + static int mmap_handler(struct perf_tool *tool __maybe_unused, union perf_event *event, struct perf_sample *sample __maybe_unused, @@ -28,7 +31,7 @@ static int init_live_machine(struct machine *machine) mmap_handler, machine, true); } -#define MAX_STACK 6 +#define MAX_STACK 8 static int unwind_entry(struct unwind_entry *entry, void *arg) { @@ -37,6 +40,8 @@ static int unwind_entry(struct unwind_entry *entry, void *arg) static const char *funcs[MAX_STACK] = { "test__arch_unwind_sample", "unwind_thread", + "compare", + "bsearch", "krava_3", "krava_2", "krava_1", @@ -88,10 +93,37 @@ static int unwind_thread(struct thread *thread) return err; } +static int global_unwind_retval = -INT_MAX; + +__attribute__ ((noinline)) +static int compare(void *p1, void *p2) +{ + /* Any possible value should be 'thread' */ + struct thread *thread = *(struct thread **)p1; + + if (global_unwind_retval == -INT_MAX) + global_unwind_retval = unwind_thread(thread); + + return p1 - p2; +} + __attribute__ ((noinline)) static int krava_3(struct thread *thread) { - return unwind_thread(thread); + struct thread *array[2] = {thread, thread}; + void *fp = &bsearch; + /* + * make _bsearch a volatile function pointer to + * prevent potential optimization, which may expand + * bsearch and call compare directly from this function, + * instead of libc shared object. + */ + void *(*volatile _bsearch)(void *, void *, size_t, + size_t, int (*)(void *, void *)); + + _bsearch = fp; + _bsearch(array, &thread, 2, sizeof(struct thread **), compare); + return global_unwind_retval; } __attribute__ ((noinline)) diff --git a/tools/perf/tests/hists_cumulate.c b/tools/perf/tests/hists_cumulate.c index 614d5c4978ab..8d110dec393e 100644 --- a/tools/perf/tests/hists_cumulate.c +++ b/tools/perf/tests/hists_cumulate.c @@ -187,7 +187,7 @@ static int do_test(struct hists *hists, struct result *expected, size_t nr_expec * function since TEST_ASSERT_VAL() returns in case of failure. */ hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); if (verbose > 2) { pr_info("use callchain: %d, cumulate callchain: %d\n", @@ -454,12 +454,12 @@ static int test3(struct perf_evsel *evsel, struct machine *machine) * 30.00% 10.00% perf perf [.] cmd_record * 20.00% 0.00% bash libc [.] malloc * 10.00% 10.00% bash [kernel] [k] page_fault - * 10.00% 10.00% perf [kernel] [k] schedule - * 10.00% 0.00% perf [kernel] [k] sys_perf_event_open + * 10.00% 10.00% bash bash [.] xmalloc * 10.00% 10.00% perf [kernel] [k] page_fault - * 10.00% 10.00% perf libc [.] free * 10.00% 10.00% perf libc [.] malloc - * 10.00% 10.00% bash bash [.] xmalloc + * 10.00% 10.00% perf [kernel] [k] schedule + * 10.00% 10.00% perf libc [.] free + * 10.00% 0.00% perf [kernel] [k] sys_perf_event_open */ struct result expected[] = { { 7000, 2000, "perf", "perf", "main" }, @@ -468,12 +468,12 @@ static int test3(struct perf_evsel *evsel, struct machine *machine) { 3000, 1000, "perf", "perf", "cmd_record" }, { 2000, 0, "bash", "libc", "malloc" }, { 1000, 1000, "bash", "[kernel]", "page_fault" }, - { 1000, 1000, "perf", "[kernel]", "schedule" }, - { 1000, 0, "perf", "[kernel]", "sys_perf_event_open" }, + { 1000, 1000, "bash", "bash", "xmalloc" }, { 1000, 1000, "perf", "[kernel]", "page_fault" }, + { 1000, 1000, "perf", "[kernel]", "schedule" }, { 1000, 1000, "perf", "libc", "free" }, { 1000, 1000, "perf", "libc", "malloc" }, - { 1000, 1000, "bash", "bash", "xmalloc" }, + { 1000, 0, "perf", "[kernel]", "sys_perf_event_open" }, }; symbol_conf.use_callchain = false; @@ -537,10 +537,13 @@ static int test4(struct perf_evsel *evsel, struct machine *machine) * malloc * main * - * 10.00% 10.00% perf [kernel] [k] schedule + * 10.00% 10.00% bash bash [.] xmalloc * | - * --- schedule - * run_command + * --- xmalloc + * malloc + * xmalloc <--- NOTE: there's a cycle + * malloc + * xmalloc * main * * 10.00% 0.00% perf [kernel] [k] sys_perf_event_open @@ -556,6 +559,12 @@ static int test4(struct perf_evsel *evsel, struct machine *machine) * run_command * main * + * 10.00% 10.00% perf [kernel] [k] schedule + * | + * --- schedule + * run_command + * main + * * 10.00% 10.00% perf libc [.] free * | * --- free @@ -570,15 +579,6 @@ static int test4(struct perf_evsel *evsel, struct machine *machine) * run_command * main * - * 10.00% 10.00% bash bash [.] xmalloc - * | - * --- xmalloc - * malloc - * xmalloc <--- NOTE: there's a cycle - * malloc - * xmalloc - * main - * */ struct result expected[] = { { 7000, 2000, "perf", "perf", "main" }, @@ -587,12 +587,12 @@ static int test4(struct perf_evsel *evsel, struct machine *machine) { 3000, 1000, "perf", "perf", "cmd_record" }, { 2000, 0, "bash", "libc", "malloc" }, { 1000, 1000, "bash", "[kernel]", "page_fault" }, - { 1000, 1000, "perf", "[kernel]", "schedule" }, + { 1000, 1000, "bash", "bash", "xmalloc" }, { 1000, 0, "perf", "[kernel]", "sys_perf_event_open" }, { 1000, 1000, "perf", "[kernel]", "page_fault" }, + { 1000, 1000, "perf", "[kernel]", "schedule" }, { 1000, 1000, "perf", "libc", "free" }, { 1000, 1000, "perf", "libc", "malloc" }, - { 1000, 1000, "bash", "bash", "xmalloc" }, }; struct callchain_result expected_callchain[] = { { @@ -622,9 +622,12 @@ static int test4(struct perf_evsel *evsel, struct machine *machine) { "bash", "main" }, }, }, { - 3, { { "[kernel]", "schedule" }, - { "perf", "run_command" }, - { "perf", "main" }, }, + 6, { { "bash", "xmalloc" }, + { "libc", "malloc" }, + { "bash", "xmalloc" }, + { "libc", "malloc" }, + { "bash", "xmalloc" }, + { "bash", "main" }, }, }, { 3, { { "[kernel]", "sys_perf_event_open" }, @@ -638,6 +641,11 @@ static int test4(struct perf_evsel *evsel, struct machine *machine) { "perf", "main" }, }, }, { + 3, { { "[kernel]", "schedule" }, + { "perf", "run_command" }, + { "perf", "main" }, }, + }, + { 4, { { "libc", "free" }, { "perf", "cmd_record" }, { "perf", "run_command" }, @@ -649,14 +657,6 @@ static int test4(struct perf_evsel *evsel, struct machine *machine) { "perf", "run_command" }, { "perf", "main" }, }, }, - { - 6, { { "bash", "xmalloc" }, - { "libc", "malloc" }, - { "bash", "xmalloc" }, - { "libc", "malloc" }, - { "bash", "xmalloc" }, - { "bash", "main" }, }, - }, }; symbol_conf.use_callchain = true; diff --git a/tools/perf/tests/hists_filter.c b/tools/perf/tests/hists_filter.c index 74f257a81265..59e53db7914c 100644 --- a/tools/perf/tests/hists_filter.c +++ b/tools/perf/tests/hists_filter.c @@ -138,7 +138,7 @@ int test__hists_filter(void) struct hists *hists = evsel__hists(evsel); hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); if (verbose > 2) { pr_info("Normal histogram\n"); diff --git a/tools/perf/tests/hists_output.c b/tools/perf/tests/hists_output.c index a748f2be1222..f5547610da02 100644 --- a/tools/perf/tests/hists_output.c +++ b/tools/perf/tests/hists_output.c @@ -152,7 +152,7 @@ static int test1(struct perf_evsel *evsel, struct machine *machine) goto out; hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); if (verbose > 2) { pr_info("[fields = %s, sort = %s]\n", field_order, sort_order); @@ -252,7 +252,7 @@ static int test2(struct perf_evsel *evsel, struct machine *machine) goto out; hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); if (verbose > 2) { pr_info("[fields = %s, sort = %s]\n", field_order, sort_order); @@ -306,7 +306,7 @@ static int test3(struct perf_evsel *evsel, struct machine *machine) goto out; hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); if (verbose > 2) { pr_info("[fields = %s, sort = %s]\n", field_order, sort_order); @@ -384,7 +384,7 @@ static int test4(struct perf_evsel *evsel, struct machine *machine) goto out; hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); if (verbose > 2) { pr_info("[fields = %s, sort = %s]\n", field_order, sort_order); @@ -487,7 +487,7 @@ static int test5(struct perf_evsel *evsel, struct machine *machine) goto out; hists__collapse_resort(hists, NULL); - hists__output_resort(hists); + hists__output_resort(hists, NULL); if (verbose > 2) { pr_info("[fields = %s, sort = %s]\n", field_order, sort_order); diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c index e6bb04b5b09b..788506eef567 100644 --- a/tools/perf/ui/browsers/hists.c +++ b/tools/perf/ui/browsers/hists.c @@ -550,7 +550,7 @@ static int hist_browser__show_callchain(struct hist_browser *browser, bool need_percent; node = rb_first(root); - need_percent = !!rb_next(node); + need_percent = node && rb_next(node); while (node) { struct callchain_node *child = rb_entry(node, struct callchain_node, rb_node); diff --git a/tools/perf/ui/hist.c b/tools/perf/ui/hist.c index dc0d095f318c..482adae3cc44 100644 --- a/tools/perf/ui/hist.c +++ b/tools/perf/ui/hist.c @@ -204,6 +204,9 @@ static int __hpp__sort_acc(struct hist_entry *a, struct hist_entry *b, if (ret) return ret; + if (a->thread != b->thread || !symbol_conf.use_callchain) + return 0; + ret = b->callchain->max_depth - a->callchain->max_depth; } return ret; diff --git a/tools/perf/ui/tui/setup.c b/tools/perf/ui/tui/setup.c index 2f612562978c..3c38f25b1695 100644 --- a/tools/perf/ui/tui/setup.c +++ b/tools/perf/ui/tui/setup.c @@ -1,5 +1,8 @@ #include <signal.h> #include <stdbool.h> +#ifdef HAVE_BACKTRACE_SUPPORT +#include <execinfo.h> +#endif #include "../../util/cache.h" #include "../../util/debug.h" @@ -88,6 +91,25 @@ int ui__getch(int delay_secs) return SLkp_getkey(); } +#ifdef HAVE_BACKTRACE_SUPPORT +static void ui__signal_backtrace(int sig) +{ + void *stackdump[32]; + size_t size; + + ui__exit(false); + psignal(sig, "perf"); + + printf("-------- backtrace --------\n"); + size = backtrace(stackdump, ARRAY_SIZE(stackdump)); + backtrace_symbols_fd(stackdump, size, STDOUT_FILENO); + + exit(0); +} +#else +# define ui__signal_backtrace ui__signal +#endif + static void ui__signal(int sig) { ui__exit(false); @@ -122,8 +144,8 @@ int ui__init(void) ui_browser__init(); tui_progress__init(); - signal(SIGSEGV, ui__signal); - signal(SIGFPE, ui__signal); + signal(SIGSEGV, ui__signal_backtrace); + signal(SIGFPE, ui__signal_backtrace); signal(SIGINT, ui__signal); signal(SIGQUIT, ui__signal); signal(SIGTERM, ui__signal); diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index 0784a9420528..cadbdc90a5cb 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -116,11 +116,6 @@ struct annotation { struct annotated_source *src; }; -struct sannotation { - struct annotation annotation; - struct symbol symbol; -}; - static inline struct sym_hist *annotation__histogram(struct annotation *notes, int idx) { return (((void *)¬es->src->histograms) + @@ -129,8 +124,7 @@ static inline struct sym_hist *annotation__histogram(struct annotation *notes, i static inline struct annotation *symbol__annotation(struct symbol *sym) { - struct sannotation *a = container_of(sym, struct sannotation, symbol); - return &a->annotation; + return (void *)sym - symbol_conf.priv_size; } int addr_map_symbol__inc_samples(struct addr_map_symbol *ams, int evidx); diff --git a/tools/perf/util/cache.h b/tools/perf/util/cache.h index 5cf9e1b5989d..d04d770d90f6 100644 --- a/tools/perf/util/cache.h +++ b/tools/perf/util/cache.h @@ -71,7 +71,9 @@ extern char *perf_path(const char *fmt, ...) __attribute__((format (printf, 1, 2 extern char *perf_pathdup(const char *fmt, ...) __attribute__((format (printf, 1, 2))); +#ifndef __UCLIBC__ /* Matches the libc/libbsd function attribute so we declare this unconditionally: */ extern size_t strlcpy(char *dest, const char *src, size_t size); +#endif #endif /* __PERF_CACHE_H */ diff --git a/tools/perf/util/callchain.c b/tools/perf/util/callchain.c index 64b377e591e4..14e7a123d43b 100644 --- a/tools/perf/util/callchain.c +++ b/tools/perf/util/callchain.c @@ -841,3 +841,33 @@ char *callchain_list__sym_name(struct callchain_list *cl, return bf; } + +static void free_callchain_node(struct callchain_node *node) +{ + struct callchain_list *list, *tmp; + struct callchain_node *child; + struct rb_node *n; + + list_for_each_entry_safe(list, tmp, &node->val, list) { + list_del(&list->list); + free(list); + } + + n = rb_first(&node->rb_root_in); + while (n) { + child = container_of(n, struct callchain_node, rb_node_in); + n = rb_next(n); + rb_erase(&child->rb_node_in, &node->rb_root_in); + + free_callchain_node(child); + free(child); + } +} + +void free_callchain(struct callchain_root *root) +{ + if (!symbol_conf.use_callchain) + return; + + free_callchain_node(&root->node); +} diff --git a/tools/perf/util/callchain.h b/tools/perf/util/callchain.h index dbc08cf5f970..c0ec1acc38e4 100644 --- a/tools/perf/util/callchain.h +++ b/tools/perf/util/callchain.h @@ -198,4 +198,6 @@ static inline int arch_skip_callchain_idx(struct thread *thread __maybe_unused, char *callchain_list__sym_name(struct callchain_list *cl, char *bf, size_t bfsize, bool show_dso); +void free_callchain(struct callchain_root *root); + #endif /* __PERF_CALLCHAIN_H */ diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index 6e88b9e395df..182395546ddc 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -6,6 +6,7 @@ #include "evlist.h" #include "evsel.h" #include "annotate.h" +#include "ui/progress.h" #include <math.h> static bool hists__filter_entry_by_dso(struct hists *hists, @@ -303,7 +304,7 @@ static struct hist_entry *hist_entry__new(struct hist_entry *template, size_t callchain_size = 0; struct hist_entry *he; - if (symbol_conf.use_callchain || symbol_conf.cumulate_callchain) + if (symbol_conf.use_callchain) callchain_size = sizeof(struct callchain_root); he = zalloc(sizeof(*he) + callchain_size); @@ -736,7 +737,7 @@ iter_add_single_cumulative_entry(struct hist_entry_iter *iter, iter->he = he; he_cache[iter->curr++] = he; - callchain_append(he->callchain, &callchain_cursor, sample->period); + hist_entry__append_callchain(he, sample); /* * We need to re-initialize the cursor since callchain_append() @@ -809,7 +810,8 @@ iter_add_next_cumulative_entry(struct hist_entry_iter *iter, iter->he = he; he_cache[iter->curr++] = he; - callchain_append(he->callchain, &cursor, sample->period); + if (symbol_conf.use_callchain) + callchain_append(he->callchain, &cursor, sample->period); return 0; } @@ -945,6 +947,7 @@ void hist_entry__free(struct hist_entry *he) zfree(&he->mem_info); zfree(&he->stat_acc); free_srcline(he->srcline); + free_callchain(he->callchain); free(he); } @@ -987,6 +990,7 @@ static bool hists__collapse_insert_entry(struct hists *hists __maybe_unused, else p = &(*p)->rb_right; } + hists->nr_entries++; rb_link_node(&he->rb_node_in, parent, p); rb_insert_color(&he->rb_node_in, root); @@ -1024,7 +1028,10 @@ void hists__collapse_resort(struct hists *hists, struct ui_progress *prog) if (!sort__need_collapse) return; + hists->nr_entries = 0; + root = hists__get_rotate_entries_in(hists); + next = rb_first(root); while (next) { @@ -1119,7 +1126,7 @@ static void __hists__insert_output_entry(struct rb_root *entries, rb_insert_color(&he->rb_node, entries); } -void hists__output_resort(struct hists *hists) +void hists__output_resort(struct hists *hists, struct ui_progress *prog) { struct rb_root *root; struct rb_node *next; @@ -1148,6 +1155,9 @@ void hists__output_resort(struct hists *hists) if (!n->filtered) hists__calc_col_len(hists, n); + + if (prog) + ui_progress__update(prog, 1); } } diff --git a/tools/perf/util/hist.h b/tools/perf/util/hist.h index d0ef9a19a744..46bd50344f85 100644 --- a/tools/perf/util/hist.h +++ b/tools/perf/util/hist.h @@ -121,7 +121,7 @@ int hist_entry__sort_snprintf(struct hist_entry *he, char *bf, size_t size, struct hists *hists); void hist_entry__free(struct hist_entry *); -void hists__output_resort(struct hists *hists); +void hists__output_resort(struct hists *hists, struct ui_progress *prog); void hists__collapse_resort(struct hists *hists, struct ui_progress *prog); void hists__decay_entries(struct hists *hists, bool zap_user, bool zap_kernel); diff --git a/tools/perf/util/hweight.c b/tools/perf/util/hweight.c deleted file mode 100644 index 5c1d0d099f0d..000000000000 --- a/tools/perf/util/hweight.c +++ /dev/null @@ -1,31 +0,0 @@ -#include <linux/bitops.h> - -/** - * hweightN - returns the hamming weight of a N-bit word - * @x: the word to weigh - * - * The Hamming Weight of a number is the total number of bits set in it. - */ - -unsigned int hweight32(unsigned int w) -{ - unsigned int res = w - ((w >> 1) & 0x55555555); - res = (res & 0x33333333) + ((res >> 2) & 0x33333333); - res = (res + (res >> 4)) & 0x0F0F0F0F; - res = res + (res >> 8); - return (res + (res >> 16)) & 0x000000FF; -} - -unsigned long hweight64(__u64 w) -{ -#if BITS_PER_LONG == 32 - return hweight32((unsigned int)(w >> 32)) + hweight32((unsigned int)w); -#elif BITS_PER_LONG == 64 - __u64 res = w - ((w >> 1) & 0x5555555555555555ul); - res = (res & 0x3333333333333333ul) + ((res >> 2) & 0x3333333333333333ul); - res = (res + (res >> 4)) & 0x0F0F0F0F0F0F0F0Ful; - res = res + (res >> 8); - res = res + (res >> 16); - return (res + (res >> 32)) & 0x00000000000000FFul; -#endif -} diff --git a/tools/perf/util/include/asm/hweight.h b/tools/perf/util/include/asm/hweight.h deleted file mode 100644 index 36cf26d434a5..000000000000 --- a/tools/perf/util/include/asm/hweight.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef PERF_HWEIGHT_H -#define PERF_HWEIGHT_H - -#include <linux/types.h> -unsigned int hweight32(unsigned int w); -unsigned long hweight64(__u64 w); - -#endif /* PERF_HWEIGHT_H */ diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 94de3e48b490..1bca3a9f2b16 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -389,7 +389,6 @@ static struct thread *__machine__findnew_thread(struct machine *machine, if (th != NULL) { rb_link_node(&th->rb_node, parent, p); rb_insert_color(&th->rb_node, &machine->threads); - machine->last_match = th; /* * We have to initialize map_groups separately @@ -400,9 +399,12 @@ static struct thread *__machine__findnew_thread(struct machine *machine, * leader and that would screwed the rb tree. */ if (thread__init_map_groups(th, machine)) { + rb_erase(&th->rb_node, &machine->threads); thread__delete(th); return NULL; } + + machine->last_match = th; } return th; diff --git a/tools/perf/util/probe-event.c b/tools/perf/util/probe-event.c index 28eb1417cb2a..94a717bf007d 100644 --- a/tools/perf/util/probe-event.c +++ b/tools/perf/util/probe-event.c @@ -495,9 +495,11 @@ static int try_to_find_probe_trace_events(struct perf_probe_event *pev, } if (ntevs == 0) { /* No error but failed to find probe point. */ - pr_warning("Probe point '%s' not found.\n", + pr_warning("Probe point '%s' not found in debuginfo.\n", synthesize_perf_probe_point(&pev->point)); - return -ENOENT; + if (need_dwarf) + return -ENOENT; + return 0; } /* Error path : ntevs < 0 */ pr_debug("An error occurred in debuginfo analysis (%d).\n", ntevs); @@ -2050,9 +2052,11 @@ static int write_probe_trace_event(int fd, struct probe_trace_event *tev) pr_debug("Writing event: %s\n", buf); if (!probe_event_dry_run) { ret = write(fd, buf, strlen(buf)); - if (ret <= 0) + if (ret <= 0) { + ret = -errno; pr_warning("Failed to write event: %s\n", strerror_r(errno, sbuf, sizeof(sbuf))); + } } free(buf); return ret; diff --git a/tools/perf/util/probe-finder.c b/tools/perf/util/probe-finder.c index c7918f83b300..b5247d777f0e 100644 --- a/tools/perf/util/probe-finder.c +++ b/tools/perf/util/probe-finder.c @@ -989,8 +989,24 @@ static int debuginfo__find_probes(struct debuginfo *dbg, int ret = 0; #if _ELFUTILS_PREREQ(0, 142) + Elf *elf; + GElf_Ehdr ehdr; + GElf_Shdr shdr; + /* Get the call frame information from this dwarf */ - pf->cfi = dwarf_getcfi_elf(dwarf_getelf(dbg->dbg)); + elf = dwarf_getelf(dbg->dbg); + if (elf == NULL) + return -EINVAL; + + if (gelf_getehdr(elf, &ehdr) == NULL) + return -EINVAL; + + if (elf_section_by_name(elf, &ehdr, &shdr, ".eh_frame", NULL) && + shdr.sh_type == SHT_PROGBITS) { + pf->cfi = dwarf_getcfi_elf(elf); + } else { + pf->cfi = dwarf_getcfi(dbg->dbg); + } #endif off = 0; diff --git a/tools/perf/util/python-ext-sources b/tools/perf/util/python-ext-sources index 16a475a7d492..6c6a6953fa93 100644 --- a/tools/perf/util/python-ext-sources +++ b/tools/perf/util/python-ext-sources @@ -10,7 +10,7 @@ util/ctype.c util/evlist.c util/evsel.c util/cpumap.c -util/hweight.c +../../lib/hweight.c util/thread_map.c util/util.c util/xyarray.c diff --git a/tools/perf/util/unwind-libunwind.c b/tools/perf/util/unwind-libunwind.c index 371219a6daf1..6edf535f65c2 100644 --- a/tools/perf/util/unwind-libunwind.c +++ b/tools/perf/util/unwind-libunwind.c @@ -185,6 +185,28 @@ static u64 elf_section_offset(int fd, const char *name) return offset; } +#ifndef NO_LIBUNWIND_DEBUG_FRAME +static int elf_is_exec(int fd, const char *name) +{ + Elf *elf; + GElf_Ehdr ehdr; + int retval = 0; + + elf = elf_begin(fd, PERF_ELF_C_READ_MMAP, NULL); + if (elf == NULL) + return 0; + if (gelf_getehdr(elf, &ehdr) == NULL) + goto out; + + retval = (ehdr.e_type == ET_EXEC); + +out: + elf_end(elf); + pr_debug("unwind: elf_is_exec(%s): %d\n", name, retval); + return retval; +} +#endif + struct table_entry { u32 start_ip_offset; u32 fde_offset; @@ -322,8 +344,12 @@ find_proc_info(unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi, #ifndef NO_LIBUNWIND_DEBUG_FRAME /* Check the .debug_frame section for unwinding info */ if (!read_unwind_spec_debug_frame(map->dso, ui->machine, &segbase)) { + int fd = dso__data_fd(map->dso, ui->machine); + int is_exec = elf_is_exec(fd, map->dso->name); + unw_word_t base = is_exec ? 0 : map->start; + memset(&di, 0, sizeof(di)); - if (dwarf_find_debug_frame(0, &di, ip, 0, map->dso->name, + if (dwarf_find_debug_frame(0, &di, ip, base, map->dso->name, map->start, map->end)) return dwarf_search_unwind_table(as, ip, &di, pi, need_unwind_info, arg); diff --git a/tools/testing/selftests/exec/execveat.c b/tools/testing/selftests/exec/execveat.c index d273624c93a6..e238c9559caf 100644 --- a/tools/testing/selftests/exec/execveat.c +++ b/tools/testing/selftests/exec/execveat.c @@ -62,7 +62,7 @@ static int _check_execveat_fail(int fd, const char *path, int flags, } static int check_execveat_invoked_rc(int fd, const char *path, int flags, - int expected_rc) + int expected_rc, int expected_rc2) { int status; int rc; @@ -98,9 +98,10 @@ static int check_execveat_invoked_rc(int fd, const char *path, int flags, child, status); return 1; } - if (WEXITSTATUS(status) != expected_rc) { - printf("[FAIL] (child %d exited with %d not %d)\n", - child, WEXITSTATUS(status), expected_rc); + if ((WEXITSTATUS(status) != expected_rc) && + (WEXITSTATUS(status) != expected_rc2)) { + printf("[FAIL] (child %d exited with %d not %d nor %d)\n", + child, WEXITSTATUS(status), expected_rc, expected_rc2); return 1; } printf("[OK]\n"); @@ -109,7 +110,7 @@ static int check_execveat_invoked_rc(int fd, const char *path, int flags, static int check_execveat(int fd, const char *path, int flags) { - return check_execveat_invoked_rc(fd, path, flags, 99); + return check_execveat_invoked_rc(fd, path, flags, 99, 99); } static char *concat(const char *left, const char *right) @@ -192,9 +193,15 @@ static int check_execveat_pathmax(int dot_dfd, const char *src, int is_script) * Execute as a long pathname relative to ".". If this is a script, * the interpreter will launch but fail to open the script because its * name ("/dev/fd/5/xxx....") is bigger than PATH_MAX. + * + * The failure code is usually 127 (POSIX: "If a command is not found, + * the exit status shall be 127."), but some systems give 126 (POSIX: + * "If the command name is found, but it is not an executable utility, + * the exit status shall be 126."), so allow either. */ if (is_script) - fail += check_execveat_invoked_rc(dot_dfd, longpath, 0, 127); + fail += check_execveat_invoked_rc(dot_dfd, longpath, 0, + 127, 126); else fail += check_execveat(dot_dfd, longpath, 0); diff --git a/tools/testing/selftests/mqueue/mq_perf_tests.c b/tools/testing/selftests/mqueue/mq_perf_tests.c index 94dae65eea41..8519e9ee97e3 100644 --- a/tools/testing/selftests/mqueue/mq_perf_tests.c +++ b/tools/testing/selftests/mqueue/mq_perf_tests.c @@ -536,10 +536,9 @@ int main(int argc, char *argv[]) { struct mq_attr attr; char *option, *next_option; - int i, cpu; + int i, cpu, rc; struct sigaction sa; poptContext popt_context; - char rc; void *retval; main_thread = pthread_self(); diff --git a/tools/testing/selftests/vm/Makefile b/tools/testing/selftests/vm/Makefile index 4c4b1f631ecf..077828c889f1 100644 --- a/tools/testing/selftests/vm/Makefile +++ b/tools/testing/selftests/vm/Makefile @@ -7,7 +7,7 @@ BINARIES += transhuge-stress all: $(BINARIES) %: %.c - $(CC) $(CFLAGS) -o $@ $^ + $(CC) $(CFLAGS) -o $@ $^ -lrt run_tests: all @/bin/sh ./run_vmtests || (echo "vmtests: [FAIL]"; exit 1) |