diff options
Diffstat (limited to 'Documentation/arm/pxa')
| -rw-r--r-- | Documentation/arm/pxa/mfp.rst (renamed from Documentation/arm/pxa/mfp.txt) | 110 |
1 files changed, 56 insertions, 54 deletions
diff --git a/Documentation/arm/pxa/mfp.txt b/Documentation/arm/pxa/mfp.rst index 0b7cab978c02..ac34e5d7ee44 100644 --- a/Documentation/arm/pxa/mfp.txt +++ b/Documentation/arm/pxa/mfp.rst @@ -1,4 +1,6 @@ - MFP Configuration for PXA2xx/PXA3xx Processors +============================================== +MFP Configuration for PXA2xx/PXA3xx Processors +============================================== Eric Miao <eric.miao@marvell.com> @@ -6,15 +8,15 @@ MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and later PXA series processors. This document describes the existing MFP API, and how board/platform driver authors could make use of it. - Basic Concept -=============== +Basic Concept +============= Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP mechanism is introduced from PXA3xx to completely move the pin-mux functions out of the GPIO controller. In addition to pin-mux configurations, the MFP also controls the low power state, driving strength, pull-up/down and event detection of each pin. Below is a diagram of internal connections between -the MFP logic and the remaining SoC peripherals: +the MFP logic and the remaining SoC peripherals:: +--------+ | |--(GPIO19)--+ @@ -69,8 +71,8 @@ NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical pad (or ball). - MFP API Usage -=============== +MFP API Usage +============= For board code writers, here are some guidelines: @@ -94,9 +96,9 @@ For board code writers, here are some guidelines: PXA310 supporting some additional ones), thus the difference is actually covered in a single mfp-pxa300.h. -2. prepare an array for the initial pin configurations, e.g.: +2. prepare an array for the initial pin configurations, e.g.:: - static unsigned long mainstone_pin_config[] __initdata = { + static unsigned long mainstone_pin_config[] __initdata = { /* Chip Select */ GPIO15_nCS_1, @@ -116,7 +118,7 @@ For board code writers, here are some guidelines: /* GPIO */ GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, - }; + }; a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(), and written to the actual registers, they are useless and may discard, @@ -143,17 +145,17 @@ For board code writers, here are some guidelines: d) although PXA3xx MFP supports edge detection on each pin, the internal logic will only wakeup the system when those specific bits in ADxER registers are set, which can be well mapped to the - corresponding peripheral, thus set_irq_wake() can be called with + corresponding peripheral, thus set_irq_wake() can be called with the peripheral IRQ to enable the wakeup. - MFP on PXA3xx -=============== +MFP on PXA3xx +============= Every external I/O pad on PXA3xx (excluding those for special purpose) has one MFP logic associated, and is controlled by one MFP register (MFPR). -The MFPR has the following bit definitions (for PXA300/PXA310/PXA320): +The MFPR has the following bit definitions (for PXA300/PXA310/PXA320):: 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ @@ -183,8 +185,8 @@ The MFPR has the following bit definitions (for PXA300/PXA310/PXA320): 0b006 - slow 10mA 0b007 - fast 10mA - MFP Design for PXA2xx/PXA3xx -============================== +MFP Design for PXA2xx/PXA3xx +============================ Due to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified MFP API is introduced to cover both series of processors. @@ -194,11 +196,11 @@ configurations, these definitions are processor and platform independent, and the actual API invoked to convert these definitions into register settings and make them effective there-after. - Files Involved - -------------- +Files Involved +-------------- - arch/arm/mach-pxa/include/mach/mfp.h - + for 1. Unified pin definitions - enum constants for all configurable pins 2. processor-neutral bit definitions for a possible MFP configuration @@ -226,42 +228,42 @@ make them effective there-after. for implementation of the pin configuration to take effect for the actual processor. - Pin Configuration - ----------------- +Pin Configuration +----------------- The following comments are copied from mfp.h (see the actual source code - for most updated info) - - /* - * a possible MFP configuration is represented by a 32-bit integer - * - * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) - * bit 10..12 - Alternate Function Selection - * bit 13..15 - Drive Strength - * bit 16..18 - Low Power Mode State - * bit 19..20 - Low Power Mode Edge Detection - * bit 21..22 - Run Mode Pull State - * - * to facilitate the definition, the following macros are provided - * - * MFP_CFG_DEFAULT - default MFP configuration value, with - * alternate function = 0, - * drive strength = fast 3mA (MFP_DS03X) - * low power mode = default - * edge detection = none - * - * MFP_CFG - default MFPR value with alternate function - * MFP_CFG_DRV - default MFPR value with alternate function and - * pin drive strength - * MFP_CFG_LPM - default MFPR value with alternate function and - * low power mode - * MFP_CFG_X - default MFPR value with alternate function, - * pin drive strength and low power mode - */ - - Examples of pin configurations are: - - #define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) + for most updated info):: + + /* + * a possible MFP configuration is represented by a 32-bit integer + * + * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) + * bit 10..12 - Alternate Function Selection + * bit 13..15 - Drive Strength + * bit 16..18 - Low Power Mode State + * bit 19..20 - Low Power Mode Edge Detection + * bit 21..22 - Run Mode Pull State + * + * to facilitate the definition, the following macros are provided + * + * MFP_CFG_DEFAULT - default MFP configuration value, with + * alternate function = 0, + * drive strength = fast 3mA (MFP_DS03X) + * low power mode = default + * edge detection = none + * + * MFP_CFG - default MFPR value with alternate function + * MFP_CFG_DRV - default MFPR value with alternate function and + * pin drive strength + * MFP_CFG_LPM - default MFPR value with alternate function and + * low power mode + * MFP_CFG_X - default MFPR value with alternate function, + * pin drive strength and low power mode + */ + + Examples of pin configurations are:: + + #define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) which reads GPIO94 can be configured as SSP3_RXD, with alternate function selection of 1, driving strength of 0b101, and a float state in low power @@ -272,8 +274,8 @@ make them effective there-after. do so, simply because this default setting is usually carefully encoded, and is supposed to work in most cases. - Register Settings - ----------------- +Register Settings +----------------- Register settings on PXA3xx for a pin configuration is actually very straight-forward, most bits can be converted directly into MFPR value |