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Diffstat (limited to '')
21 files changed, 1263 insertions, 288 deletions
diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml index f0b3d30fbb76..85c4a979aec4 100644 --- a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml +++ b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A64 Display Engine Bus Device Tree Bindings +title: Allwinner A64 Display Engine Bus maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -31,12 +31,14 @@ properties: maxItems: 1 allwinner,sram: - allOf: - - $ref: /schemas/types.yaml#definitions/phandle-array - - maxItems: 1 description: The SRAM that needs to be claimed to access the display engine bus. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to SRAM + - description: register value for device ranges: true diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml index 80973619342d..bee5f53f837f 100644 --- a/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml +++ b/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/bus/allwinner,sun8i-a23-rsb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A23 RSB Device Tree Bindings +title: Allwinner A23 RSB maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -21,8 +21,10 @@ properties: oneOf: - const: allwinner,sun8i-a23-rsb - items: - - const: allwinner,sun8i-a83t-rsb - - const: allwinner,sun8i-a23-rsb + - enum: + - allwinner,sun8i-a83t-rsb + - allwinner,sun50i-h616-rsb + - const: allwinner,sun8i-a23-rsb reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/bus/arm,integrator-ap-lm.yaml b/Documentation/devicetree/bindings/bus/arm,integrator-ap-lm.yaml new file mode 100644 index 000000000000..47227427c1c0 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/arm,integrator-ap-lm.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/arm,integrator-ap-lm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Integrator/AP Logic Module extension bus + +maintainers: + - Linus Walleij <linusw@kernel.org> + +description: The Integrator/AP is a prototyping platform and as such has a + site for stacking up to four logic modules (LM) designed specifically for + use with this platform. A special system controller register can be read to + determine if a logic module is connected at index 0, 1, 2 or 3. The logic + module connector is described in this binding. The logic modules per se + then have their own specific per-module bindings and they will be described + as subnodes under this logic module extension bus. + +properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + compatible: + items: + - const: arm,integrator-ap-lm + + ranges: true + dma-ranges: true + +patternProperties: + "^bus(@[0-9a-f]*)?$": + description: Nodes on the Logic Module bus represent logic modules + and are named with bus. The first module is at 0xc0000000, the second + at 0xd0000000 and so on until the top of the memory of the system at + 0xffffffff. All information about the memory used by the module is + in ranges and dma-ranges. + type: object + + required: + - compatible + +required: + - compatible + +examples: + - | + bus@c0000000 { + compatible = "arm,integrator-ap-lm"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc0000000 0xc0000000 0x40000000>; + dma-ranges; + + bus@c0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xc0000000 0x10000000>; + /* The Logic Modules sees the Core Module 0 RAM @80000000 */ + dma-ranges = <0x00000000 0x80000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + serial@100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00100000 0x1000>; + interrupts-extended = <&impd1_vic 1>; + }; + + impd1_vic: interrupt-controller@3000000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x03000000 0x1000>; + valid-mask = <0x00000bff>; + interrupts-extended = <&pic 9>; + }; + }; + }; + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/bus/baikal,bt1-apb.yaml b/Documentation/devicetree/bindings/bus/baikal,bt1-apb.yaml new file mode 100644 index 000000000000..37ba3337f944 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/baikal,bt1-apb.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 APB-bus + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: | + Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect + which routes them to the AXI-APB bridge. This interface is a single master + multiple slaves bus in turn serializing IO accesses and routing them to the + addressed APB slave devices. In case of any APB protocol collisions, slave + device not responding on timeout an IRQ is raised with an erroneous address + reported to the APB terminator (APB Errors Handler Block). + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + contains: + const: baikal,bt1-apb + + reg: + items: + - description: APB EHB MMIO registers + - description: APB MMIO region with no any device mapped + + reg-names: + items: + - const: ehb + - const: nodev + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB reference clock + + clock-names: + items: + - const: pclk + + resets: + items: + - description: APB domain reset line + + reset-names: + items: + - const: prst + +unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + + bus@1f059000 { + compatible = "baikal,bt1-apb", "simple-bus"; + reg = <0x1f059000 0x1000>, + <0x1d000000 0x2040000>; + reg-names = "ehb", "nodev"; + #address-cells = <1>; + #size-cells = <1>; + + ranges; + + interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&ccu_sys 1>; + clock-names = "pclk"; + + resets = <&ccu_sys 1>; + reset-names = "prst"; + }; +... diff --git a/Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml b/Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml new file mode 100644 index 000000000000..4ac78b44e45e --- /dev/null +++ b/Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 AXI-bus + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: | + AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all + high-speed peripheral IP-cores with RAM controller and with MIPS P5600 + cores. Traffic arbitration is done by means of DW AXI Interconnect (so + called AXI Main Interconnect) routing IO requests from one block to + another: from CPU to SoC peripherals and between some SoC peripherals + (mostly between peripheral devices and RAM, but also between DMA and + some peripherals). In case of any protocol error, device not responding + an IRQ is raised and a faulty situation is reported to the AXI EHB + (Errors Handler Block) embedded on top of the DW AXI Interconnect and + accessible by means of the Baikal-T1 System Controller. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + contains: + const: baikal,bt1-axi + + reg: + minItems: 1 + items: + - description: Synopsys DesignWare AXI Interconnect QoS registers + - description: AXI EHB MMIO system controller registers + + reg-names: + minItems: 1 + items: + - const: qos + - const: ehb + + '#interconnect-cells': + const: 1 + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the Baikal-T1 System Controller DT node + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Main Interconnect uplink reference clock + + clock-names: + items: + - const: aclk + + resets: + items: + - description: Main Interconnect reset line + + reset-names: + items: + - const: arst + +unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - syscon + - interrupts + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + + bus@1f05a000 { + compatible = "baikal,bt1-axi", "simple-bus"; + reg = <0x1f05a000 0x1000>, + <0x1f04d110 0x8>; + reg-names = "qos", "ehb"; + #address-cells = <1>; + #size-cells = <1>; + #interconnect-cells = <1>; + + syscon = <&syscon>; + + ranges; + + interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&ccu_axi 0>; + clock-names = "aclk"; + + resets = <&ccu_axi 0>; + reset-names = "arst"; + }; +... diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt deleted file mode 100644 index 729def62f0c5..000000000000 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ /dev/null @@ -1,33 +0,0 @@ -Broadcom GISB bus Arbiter controller - -Required properties: - -- compatible: - "brcm,bcm7278-gisb-arb" for V7 28nm chips - "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips - "brcm,bcm7435-gisb-arb" for newer 40nm chips - "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips - "brcm,bcm7038-gisb-arb" for 130nm chips -- reg: specifies the base physical address and size of the registers -- interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller - -Optional properties: - -- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB - masters are valid at the system level -- brcm,gisb-arb-master-names: string list of the litteral name of the GISB - masters. Should match the number of bits set in brcm,gisb-master-mask and - the order in which they appear - -Example: - -gisb-arb@f0400000 { - compatible = "brcm,gisb-arb"; - reg = <0xf0400000 0x800>; - interrupts = <0>, <2>; - interrupt-parent = <&sun_l2_intc>; - - brcm,gisb-arb-master-mask = <0x7>; - brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; -}; diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml new file mode 100644 index 000000000000..b23c3001991e --- /dev/null +++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom GISB bus Arbiter controller + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7445-gisb-arb # for other 28nm chips + - const: brcm,gisb-arb + - items: + - enum: + - brcm,bcm7278-gisb-arb # for V7 28nm chips + - brcm,bcm7435-gisb-arb # for newer 40nm chips + - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips + - brcm,bcm7038-gisb-arb # for 130nm chips + - brcm,gisb-arb # fallback compatible + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + items: + - description: timeout interrupt line + - description: target abort interrupt line + - description: breakpoint interrupt line + + brcm,gisb-arb-master-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + 32-bits wide bitmask used to specify which GISB masters are valid at the + system level + + brcm,gisb-arb-master-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: > + String list of the litteral name of the GISB masters. Should match the + number of bits set in brcm,gisb-master-mask and the order in which they + appear from MSB to LSB. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + gisb-arb@f0400000 { + compatible = "brcm,gisb-arb"; + reg = <0xf0400000 0x800>; + interrupts = <0>, <2>; + interrupt-parent = <&sun_l2_intc>; + brcm,gisb-arb-master-mask = <0x7>; + brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; + }; diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml new file mode 100644 index 000000000000..d42dbb0bbc2e --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Shared Peripherals Bus Interface + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + +description: | + A simple bus enabling access to shared peripherals. + + The "spba-bus" follows the "simple-bus" set of properties, as + specified in the Devicetree Specification. It is an extension of + "simple-bus" because the SDMA controller uses this compatible flag to + determine which peripherals are available to it and the range over which + the SDMA can access. There are no special clocks for the bus, because + the SDMA controller itself has its interrupt and clock assignments. + +select: + properties: + compatible: + contains: + const: fsl,spba-bus + required: + - compatible + +properties: + $nodename: + pattern: "^spba-bus(@[0-9a-f]+)?$" + + compatible: + items: + - const: fsl,spba-bus + - const: simple-bus + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + reg: + maxItems: 1 + + ranges: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - reg + - ranges + +additionalProperties: + type: object + +examples: + - | + spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + }; diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt index 1b1d1c5c21ea..e7f502070d77 100644 --- a/Documentation/devicetree/bindings/bus/imx-weim.txt +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt @@ -48,6 +48,11 @@ Optional properties: devices, the presence of this property indicates that the weim bus should operate in Burst Clock Mode. + - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. + Without this option Burst Clock will output clock + only when necessary. This takes effect only if + "fsl,burst-clk-enable" is set. + Timing property for child nodes. It is mandatory, not optional. - fsl,weim-cs-timing: The timing array, contains timing values for the diff --git a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml new file mode 100644 index 000000000000..5fb4e7bfa4da --- /dev/null +++ b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx Expansion Bus Controller + +description: | + The IXP4xx expansion bus controller handles access to devices on the + memory-mapped expansion bus on the Intel IXP4xx family of system on chips, + including IXP42x, IXP43x, IXP45x and IXP46x. + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +properties: + $nodename: + pattern: '^bus@[0-9a-f]+$' + + compatible: + items: + - enum: + - intel,ixp42x-expansion-bus-controller + - intel,ixp43x-expansion-bus-controller + - intel,ixp45x-expansion-bus-controller + - intel,ixp46x-expansion-bus-controller + - const: syscon + + reg: + description: Control registers for the expansion bus, these are not + inside the memory range handled by the expansion bus. + maxItems: 1 + + native-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: The IXP4xx has a peculiar MMIO access scheme, as it changes + the access pattern for words (swizzling) on the bus depending on whether + the SoC is running in big-endian or little-endian mode. Thus the + registers must always be accessed using native endianness. + + "#address-cells": + description: | + The first cell is the chip select number. + The second cell is the address offset within the bank. + const: 2 + + "#size-cells": + const: 1 + + ranges: true + dma-ranges: true + +patternProperties: + "^.*@[0-7],[0-9a-f]+$": + description: Devices attached to chip selects are represented as + subnodes. + type: object + + properties: + intel,ixp4xx-eb-t1: + description: Address timing, extend address phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + intel,ixp4xx-eb-t2: + description: Setup chip select timing, extend setup phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + intel,ixp4xx-eb-t3: + description: Strobe timing, extend strobe phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + + intel,ixp4xx-eb-t4: + description: Hold timing, extend hold phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + intel,ixp4xx-eb-t5: + description: Recovery timing, extend recovery phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + + intel,ixp4xx-eb-cycle-type: + description: The type of cycles to use on the expansion bus for this + chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + intel,ixp4xx-eb-byte-access-on-halfword: + description: Allow byte read access on half word devices. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-hpi-hrdy-pol-high: + description: Set HPI HRDY polarity to active high when using HPI. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-mux-address-and-data: + description: Multiplex address and data on the data bus. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-ahb-split-transfers: + description: Enable AHB split transfers. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-write-enable: + description: Enable write cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-byte-access: + description: Expansion bus uses only 8 bits. The default is to use + 16 bits. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + +required: + - compatible + - reg + - native-endian + - "#address-cells" + - "#size-cells" + - ranges + - dma-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + bus@50000000 { + compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; + reg = <0xc4000000 0x28>; + native-endian; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x01000000>, + <1 0x0 0x51000000 0x01000000>; + dma-ranges = <0 0x0 0x50000000 0x01000000>, + <1 0x0 0x51000000 0x01000000>; + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + reg = <0 0x00000000 0x1000000>; + intel,ixp4xx-eb-t3 = <3>; + intel,ixp4xx-eb-cycle-type = <0>; + intel,ixp4xx-eb-byte-access-on-halfword = <1>; + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <0>; + }; + serial@1,0 { + compatible = "exar,xr16l2551", "ns8250"; + reg = <1 0x00000000 0x10>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <1843200>; + intel,ixp4xx-eb-t3 = <3>; + intel,ixp4xx-eb-cycle-type = <1>; + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml new file mode 100644 index 000000000000..6a7b26b049f1 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Common Device Memory Map + +description: | + Defines a location of the MIPS Common Device Memory Map registers. + +maintainers: + - James Hogan <jhogan@kernel.org> + +properties: + compatible: + const: mti,mips-cdmm + + reg: + description: | + Base address and size of an unoccupied memory region, which will be + used to map the MIPS CDMM registers block. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cdmm@1bde8000 { + compatible = "mti,mips-cdmm"; + reg = <0x1bde8000 0x8000>; + }; +... diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt deleted file mode 100644 index 3108d03802ee..000000000000 --- a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt +++ /dev/null @@ -1,44 +0,0 @@ -NVIDIA Tegra ACONNECT Bus - -The Tegra ACONNECT bus is an AXI switch which is used to connnect various -components inside the Audio Processing Engine (APE). All CPU accesses to -the APE subsystem go through the ACONNECT via an APB to AXI wrapper. - -Required properties: -- compatible: Must be "nvidia,tegra210-aconnect". -- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE), - and APE interface clock (TEGRA210_CLK_APB2APE). -- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding - 'clocks' entries. -- power-domains: Must contain a phandle that points to the audio powergate - (namely 'aud') for Tegra210. -- #address-cells: The number of cells used to represent physical base addresses - in the aconnect address space. Should be 1. -- #size-cells: The number of cells used to represent the size of an address - range in the aconnect address space. Should be 1. -- ranges: Mapping of the aconnect address space to the CPU address space. - -All devices accessed via the ACONNNECT are described by child-nodes. - -Example: - - aconnect@702c0000 { - compatible = "nvidia,tegra210-aconnect"; - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - clock-names = "ape", "apb2ape"; - power-domains = <&pd_audio>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; - - - child1 { - ... - }; - - child2 { - ... - }; - }; diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml new file mode 100644 index 000000000000..d3ed048c9521 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/nvidia,tegra210-aconnect.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra ACONNECT Bus + +description: | + The Tegra ACONNECT bus is an AXI switch which is used to connnect various + components inside the Audio Processing Engine (APE). All CPU accesses to + the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All + devices accessed via the ACONNNECT are described by child-nodes. + +maintainers: + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + oneOf: + - const: nvidia,tegra210-aconnect + - items: + - enum: + - nvidia,tegra234-aconnect + - nvidia,tegra186-aconnect + - nvidia,tegra194-aconnect + - const: nvidia,tegra210-aconnect + + clocks: + items: + - description: Must contain the entry for APE clock + - description: Must contain the entry for APE interface clock + + clock-names: + items: + - const: ape + - const: apb2ape + + power-domains: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "@[0-9a-f]+$": + type: object + +required: + - compatible + - clocks + - clock-names + - power-domains + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include<dt-bindings/clock/tegra210-car.h> + + aconnect@702c0000 { + compatible = "nvidia,tegra210-aconnect"; + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&pd_audio>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x702c0000 0x702c0000 0x00040000>; + + // Child device nodes follow ... + }; + +... diff --git a/Documentation/devicetree/bindings/bus/palmbus.yaml b/Documentation/devicetree/bindings/bus/palmbus.yaml new file mode 100644 index 000000000000..30fa6526cfc2 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/palmbus.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/palmbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink PalmBus + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + The ralink palmbus controller can be found in all ralink MIPS + SoCs. It provides an external bus for connecting multiple + external devices to the SoC. + +properties: + $nodename: + pattern: "^palmbus(@[0-9a-f]+)?$" + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + compatible: + const: palmbus + + reg: + maxItems: 1 + + ranges: true + +patternProperties: + # All other properties should be child nodes with unit-address and 'reg' + "@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + palmbus@1e000000 { + compatible = "palmbus"; + reg = <0x1e000000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000000 0x0fffff>; + + gpio@600 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "mediatek,mt7621-gpio"; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 95>; + interrupt-controller; + reg = <0x600 0x100>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml new file mode 100644 index 000000000000..8e9e6ff35d7d --- /dev/null +++ b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs + +maintainers: + - Michael Srba <Michael.Srba@seznam.cz> + +description: | + This binding describes the dependencies (clocks, resets, power domains) which + need to be turned on in a sequence before communication over the AHB bus + becomes possible. + + Additionally, the reg property is used to pass to the driver the location of + two sadly undocumented registers which need to be poked as part of the sequence. + + The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart + controllers, a hexagon core, and a clock controller which provides clocks for + the above. + +properties: + compatible: + items: + - const: qcom,msm8998-ssc-block-bus + - const: qcom,ssc-block-bus + + reg: + items: + - description: SSCAON_CONFIG0 registers + - description: SSCAON_CONFIG1 registers + + reg-names: + items: + - const: mpm_sscaon_config0 + - const: mpm_sscaon_config1 + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + clocks: + maxItems: 6 + + clock-names: + items: + - const: xo + - const: aggre2 + - const: gcc_im_sleep + - const: aggre2_north + - const: ssc_xo + - const: ssc_ahbs + + power-domains: + items: + - description: CX power domain + - description: MX power domain + + power-domain-names: + items: + - const: ssc_cx + - const: ssc_mx + + resets: + items: + - description: Main reset + - description: + SSC Branch Control Register reset (associated with the ssc_xo and + ssc_ahbs clocks) + + reset-names: + items: + - const: ssc_reset + - const: ssc_bcr + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: describes how to locate the ssc AXI halt register + items: + - items: + - description: Phandle reference to a syscon representing TCSR + - description: offset for the ssc AXI halt register + +required: + - compatible + - reg + - reg-names + - '#address-cells' + - '#size-cells' + - ranges + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - qcom,halt-regs + +additionalProperties: + type: object + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8998.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <1>; + #size-cells = <1>; + + // devices under this node are physically located in the SSC block, connected to an ssc-internal bus; + ssc_ahb_slave: bus@10ac008 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus"; + reg = <0x10ac008 0x4>, <0x10ac010 0x4>; + reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1"; + + clocks = <&xo>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&gcc GCC_IM_SLEEP>, + <&gcc AGGRE2_SNOC_NORTH_AXI>, + <&gcc SSC_XO>, + <&gcc SSC_CNOC_AHBS_CLK>; + clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs"; + + resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>; + reset-names = "ssc_reset", "ssc_bcr"; + + power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>; + power-domain-names = "ssc_cx", "ssc_mx"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x26000>; + }; + }; diff --git a/Documentation/devicetree/bindings/bus/renesas,bsc.yaml b/Documentation/devicetree/bindings/bus/renesas,bsc.yaml index 7d10b62a52d5..f53a37785413 100644 --- a/Documentation/devicetree/bindings/bus/renesas,bsc.yaml +++ b/Documentation/devicetree/bindings/bus/renesas,bsc.yaml @@ -44,6 +44,8 @@ properties: required: - reg +unevaluatedProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml b/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml index 33326ffdb266..182134d7a6a3 100644 --- a/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml +++ b/Documentation/devicetree/bindings/bus/simple-pm-bus.yaml @@ -61,6 +61,8 @@ anyOf: - required: - power-domains +additionalProperties: true + examples: - | #include <dt-bindings/clock/qcom,gcc-msm8996.h> diff --git a/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml b/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml new file mode 100644 index 000000000000..49df13fc2f89 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier System Bus + +description: | + The UniPhier System Bus is an external bus that connects on-board devices to + the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and + some control signals. It supports up to 8 banks (chip selects). + + Before any access to the bus, the bus controller must be configured; the bus + controller registers provide the control for the translation from the offset + within each bank to the CPU-viewed address. The needed setup includes the + base address, the size of each bank. Optionally, some timing parameters can + be optimized for faster bus access. + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + const: socionext,uniphier-system-bus + + reg: + maxItems: 1 + + "#address-cells": + description: | + The first cell is the bank number (chip select). + The second cell is the address offset within the bank. + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Provide address translation from the System Bus to the parent bus. + + Note: + The address region(s) that can be assigned for the System Bus is + implementation defined. Some SoCs can use 0x00000000-0x0fffffff and + 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff. + There might be additional limitations depending on SoCs and the boot mode. + The address translation is arbitrary as long as the banks are assigned in + the supported address space with the required alignment and they do not + overlap one another. + + For example, it is possible to map: + bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff + It is also possible to map: + bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff + There is no reason to stick to a particular translation mapping, but the + "ranges" property should provide a "reasonable" default that is known to + work. The software should initialize the bus controller according to it. + +patternProperties: + "^.*@[1-5],[1-9a-f][0-9a-f]+$": + description: Devices attached to chip selects + type: object + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, + // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and + // mapped to 0x43f00000 of the parent bus. + // - the UART device is connected at the offset 0x00200000 of CS5 and + // mapped to 0x46200000 of the parent bus. + + system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0x00000000 0x42000000 0x02000000>, + <5 0x00000000 0x46000000 0x01000000>; + + ethernet@1,1f00000 { + compatible = "smsc,lan9115"; + reg = <1 0x01f00000 0x1000>; + interrupts = <0 48 4>; + phy-mode = "mii"; + }; + + serial@5,200000 { + compatible = "ns16550a"; + reg = <5 0x00200000 0x20>; + interrupts = <0 49 4>; + clock-frequency = <12288000>; + }; + }; diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt deleted file mode 100644 index 233eb8294204..000000000000 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ /dev/null @@ -1,138 +0,0 @@ -Texas Instruments sysc interconnect target module wrapper binding - -Texas Instruments SoCs can have a generic interconnect target module -hardware for devices connected to various interconnects such as L3 -interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc -is mostly used for interaction between module and PRCM. It participates -in the OCP Disconnect Protocol but other than that is mostly independent -of the interconnect. - -Each interconnect target module can have one or more devices connected to -it. There is a set of control registers for managing interconnect target -module clocks, idle modes and interconnect level resets for the module. - -These control registers are sprinkled into the unused register address -space of the first child device IP block managed by the interconnect -target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. - -Required standard properties: - -- compatible shall be one of the following generic types: - - "ti,sysc" - "ti,sysc-omap2" - "ti,sysc-omap4" - "ti,sysc-omap4-simple" - - or one of the following derivative types for hardware - needing special workarounds: - - "ti,sysc-omap2-timer" - "ti,sysc-omap4-timer" - "ti,sysc-omap3430-sr" - "ti,sysc-omap3630-sr" - "ti,sysc-omap4-sr" - "ti,sysc-omap3-sham" - "ti,sysc-omap-aes" - "ti,sysc-mcasp" - "ti,sysc-dra7-mcasp" - "ti,sysc-usb-host-fs" - "ti,sysc-dra7-mcan" - -- reg shall have register areas implemented for the interconnect - target module in question such as revision, sysc and syss - -- reg-names shall contain the register names implemented for the - interconnect target module in question such as - "rev, "sysc", and "syss" - -- ranges shall contain the interconnect target module IO range - available for one or more child device IP blocks managed - by the interconnect target module, the ranges may include - multiple ranges such as device L4 range for control and - parent L3 range for DMA access - -Optional properties: - -- ti,sysc-mask shall contain mask of supported register bits for the - SYSCONFIG register as documented in the Technical Reference - Manual (TRM) for the interconnect target module - -- ti,sysc-midle list of master idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register MIDLEMODE bits - -- ti,sysc-sidle list of slave idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register SIDLEMODE bits - -- ti,sysc-delay-us delay needed after OCP softreset before accssing - SYSCONFIG register again - -- ti,syss-mask optional mask of reset done status bits as described in the - TRM for SYSSTATUS registers, typically 1 with some devices - having separate reset done bits for children like OHCI and - EHCI - -- clocks clock specifier for each name in the clock-names as - specified in the binding documentation for ti-clkctrl, - typically available for all interconnect targets on TI SoCs - based on omap4 except if it's read-only register in hwauto - mode as for example omap4 L4_CFG_CLKCTRL - -- clock-names should contain at least "fck", and optionally also "ick" - depending on the SoC and the interconnect target module, - some interconnect target modules also need additional - optional clocks that can be specified as listed in TRM - for the related CLKCTRL register bits 8 to 15 such as - "dbclk" or "clk32k" depending on their role - -- ti,hwmods optional TI interconnect module name to use legacy - hwmod platform data - -- ti,no-reset-on-init interconnect target module should not be reset at init - -- ti,no-idle-on-init interconnect target module should not be idled at init - -- ti,no-idle interconnect target module should not be idled - -Example: Single instance of MUSB controller on omap4 using interconnect ranges -using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): - - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ - compatible = "ti,sysc-omap2"; - ti,hwmods = "usb_otg_hs"; - reg = <0x2b400 0x4>, - <0x2b404 0x4>, - <0x2b408 0x4>; - reg-names = "rev", "sysc", "syss"; - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2b000 0x1000>; - - usb_otg_hs: otg@0 { - compatible = "ti,omap4-musb"; - reg = <0x0 0x7ff>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - usb-phy = <&usb2_phy>; - ... - }; - }; - -Note that other SoCs, such as am335x can have multiple child devices. On am335x -there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA -instance as children of a single interconnect target module. diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.yaml b/Documentation/devicetree/bindings/bus/ti-sysc.yaml new file mode 100644 index 000000000000..fced4082b047 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti-sysc.yaml @@ -0,0 +1,215 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/ti-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments interconnect target module binding + +maintainers: + - Tony Lindgren <tony@atomide.com> + +description: + Texas Instruments SoCs can have a generic interconnect target module + for devices connected to various interconnects such as L3 interconnect + using Arteris NoC, and L4 interconnect using Sonics s3220. This module + is mostly used for interaction between module and Power, Reset and Clock + Manager PRCM. It participates in the OCP Disconnect Protocol, but other + than that it is mostly independent of the interconnect. + + Each interconnect target module can have one or more devices connected to + it. There is a set of control registers for managing the interconnect target + module clocks, idle modes and interconnect level resets. + + The interconnect target module control registers are sprinkled into the + unused register address space of the first child device IP block managed by + the interconnect target module. Typically the register names are REVISION, + SYSCONFIG and SYSSTATUS. + +properties: + $nodename: + pattern: "^target-module(@[0-9a-f]+)?$" + + compatible: + oneOf: + - items: + - enum: + - ti,sysc-omap2 + - ti,sysc-omap4 + - ti,sysc-omap4-simple + - ti,sysc-omap2-timer + - ti,sysc-omap4-timer + - ti,sysc-omap3430-sr + - ti,sysc-omap3630-sr + - ti,sysc-omap4-sr + - ti,sysc-omap3-sham + - ti,sysc-omap-aes + - ti,sysc-mcasp + - ti,sysc-dra7-mcasp + - ti,sysc-usb-host-fs + - ti,sysc-dra7-mcan + - ti,sysc-pruss + - const: ti,sysc + - items: + - const: ti,sysc + + reg: + description: + Interconnect target module control registers consisting of + REVISION, SYSCONFIG and SYSSTATUS registers as defined in the + Technical Reference Manual for the SoC. + minItems: 1 + maxItems: 3 + + reg-names: + description: + Interconnect target module control register names consisting + of "rev", "sysc" and "syss". + oneOf: + - minItems: 1 + items: + - const: rev + - const: sysc + - const: syss + - items: + - const: rev + - const: syss + - enum: [ sysc, syss ] + + power-domains: + description: Target module power domain if available. + maxItems: 1 + + clocks: + description: + Target module clocks consisting of one functional clock, one + interface clock, and up to 8 module specific optional clocks. + Some modules may have only the functional clock, and some have + no configurable clocks. + minItems: 1 + maxItems: 4 + + clock-names: + description: + Target module clock names like "fck", "ick", "optck1", "optck2" + if the clocks are configurable. + oneOf: + - enum: [ ick, fck, sys_clk ] + - items: + - const: fck + - enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ] + - items: + - const: fck + - const: phy-clk + - const: phy-clk-div + - items: + - const: fck + - const: hdmi_clk + - const: sys_clk + - const: tv_clk + - items: + - const: fck + - const: ahclkx + - const: ahclkr + + resets: + description: + Target module reset bit in the RSTCTRL register if wired for the module. + Note that the other reset bits should be mapped for the child device + driver to use. + maxItems: 1 + + reset-names: + description: + Target module reset names in the RSTCTRL register, typically named + "rstctrl" if only one reset bit is wired for the module. + items: + - const: rstctrl + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + dma-ranges: true + + ti,sysc-mask: + description: Mask of supported register bits for the SYSCONFIG register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-midle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,sysc-sidle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,syss-mask: + description: Mask of supported register bits for the SYSSTATUS register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-delay-us: + description: Delay needed after OCP softreset before accessing SYCONFIG + default: 0 + minimum: 0 + maximum: 2 + + ti,no-reset-on-init: + description: Interconnect target module shall not be reset at init + type: boolean + + ti,no-idle-on-init: + description: Interconnect target module shall not be idled at init + type: boolean + + ti,no-idle: + description: Interconnect target module shall not be idled + type: boolean + + ti,hwmods: + description: Interconnect module name to use with legacy hwmod data + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - ranges + +additionalProperties: + type: object + +examples: + - | + #include <dt-bindings/bus/ti-sysc.h> + #include <dt-bindings/clock/omap4.h> + + target-module@2b000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2b000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt b/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt deleted file mode 100644 index 68ef80afff16..000000000000 --- a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt +++ /dev/null @@ -1,66 +0,0 @@ -UniPhier System Bus - -The UniPhier System Bus is an external bus that connects on-board devices to -the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and -some control signals. It supports up to 8 banks (chip selects). - -Before any access to the bus, the bus controller must be configured; the bus -controller registers provide the control for the translation from the offset -within each bank to the CPU-viewed address. The needed setup includes the base -address, the size of each bank. Optionally, some timing parameters can be -optimized for faster bus access. - -Required properties: -- compatible: should be "socionext,uniphier-system-bus". -- reg: offset and length of the register set for the bus controller device. -- #address-cells: should be 2. The first cell is the bank number (chip select). - The second cell is the address offset within the bank. -- #size-cells: should be 1. -- ranges: should provide a proper address translation from the System Bus to - the parent bus. - -Note: -The address region(s) that can be assigned for the System Bus is implementation -defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff, -while other SoCs can only use 0x40000000-0x4fffffff. There might be additional -limitations depending on SoCs and the boot mode. The address translation is -arbitrary as long as the banks are assigned in the supported address space with -the required alignment and they do not overlap one another. -For example, it is possible to map: - bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff -It is also possible to map: - bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff -There is no reason to stick to a particular translation mapping, but the -"ranges" property should provide a "reasonable" default that is known to work. -The software should initialize the bus controller according to it. - -Example: - - system-bus { - compatible = "socionext,uniphier-system-bus"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <1 0x00000000 0x42000000 0x02000000 - 5 0x00000000 0x46000000 0x01000000>; - - ethernet@1,01f00000 { - compatible = "smsc,lan9115"; - reg = <1 0x01f00000 0x1000>; - interrupts = <0 48 4> - phy-mode = "mii"; - }; - - uart@5,00200000 { - compatible = "ns16550a"; - reg = <5 0x00200000 0x20>; - interrupts = <0 49 4> - clock-frequency = <12288000>; - }; - }; - -In this example, - - the Ethernet device is connected at the offset 0x01f00000 of CS1 and - mapped to 0x43f00000 of the parent bus. - - the UART device is connected at the offset 0x00200000 of CS5 and - mapped to 0x46200000 of the parent bus. |