diff options
Diffstat (limited to 'Documentation/devicetree/bindings/mtd')
8 files changed, 234 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/mtd/aspeed-smc.txt b/Documentation/devicetree/bindings/mtd/aspeed-smc.txt new file mode 100644 index 000000000000..49f6528ef547 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/aspeed-smc.txt @@ -0,0 +1,51 @@ +* Aspeed Firmware Memory controller +* Aspeed SPI Flash Memory Controller + +The Firmware Memory Controller in the Aspeed AST2500 SoC supports +three chip selects, two of which are always of SPI type and the third +can be SPI or NOR type flash. These bindings only describe SPI. + +The two SPI flash memory controllers in the AST2500 each support two +chip selects. + +Required properties: + - compatible : Should be one of + "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller + "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller + "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller + "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers + + - reg : the first contains the control register location and length, + the second contains the memory window mapping address and length + - #address-cells : must be 1 corresponding to chip select child binding + - #size-cells : must be 0 corresponding to chip select child binding + +Optional properties: + - interrupts : Should contain the interrupt for the dma device if an + FMC + +The child nodes are the SPI flash modules which must have a compatible +property as specified in bindings/mtd/jedec,spi-nor.txt + +Optionally, the child node can contain properties for SPI mode (may be +ignored): + - spi-max-frequency - max frequency of spi bus + + +Example: +fmc: fmc@1e620000 { + compatible = "aspeed,ast2500-fmc"; + reg = < 0x1e620000 0x94 + 0x20000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <19>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + /* spi-max-frequency = <>; */ + /* m25p,fast-read; */ + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/Documentation/devicetree/bindings/mtd/common.txt b/Documentation/devicetree/bindings/mtd/common.txt new file mode 100644 index 000000000000..fc068b923d7a --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/common.txt @@ -0,0 +1,15 @@ +* Common properties of all MTD devices + +Optional properties: +- label: user-defined MTD device name. Can be used to assign user + friendly names to MTD devices (instead of the flash model or flash + controller based name) in order to ease flash device identification + and/or describe what they are used for. + +Example: + + flash@0 { + label = "System-firmware"; + + /* flash type specific properties */ + }; diff --git a/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt b/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt new file mode 100644 index 000000000000..3fa1b34d69ad --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt @@ -0,0 +1,24 @@ +Flash device on Cortina Systems Gemini SoC + +This flash is regular CFI compatible (Intel or AMD extended) flash chips with +some special bits that can be controlled by the machine's system controller. + +Required properties: +- compatible : must be "cortina,gemini-flash", "cfi-flash"; +- reg : memory address for the flash chip +- syscon : must be a phandle to the system controller +- bank-width : width in bytes of flash interface, should be <2> + +For the rest of the properties, see mtd-physmap.txt. + +The device tree may optionally contain sub-nodes describing partitions of the +address space. See partition.txt for more detail. + +Example: + +flash@30000000 { + compatible = "cortina,gemini-flash", "cfi-flash"; + reg = <0x30000000 0x01000000>; + syscon = <&syscon>; + bank-width = <2>; +}; diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt index 2c91c03e7eb0..3e920ec5c4d3 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt @@ -14,6 +14,8 @@ Required properties: at25df641 at26df081a mr25h256 + mr25h10 + mr25h40 mx25l4005a mx25l1606e mx25l6405d diff --git a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt index fb314f09861b..5ded66ad7aef 100644 --- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt @@ -1,7 +1,13 @@ * Serial NOR flash controller for MTK MT81xx (and similar) Required properties: -- compatible: should be "mediatek,mt8173-nor"; +- compatible: The possible values are: + "mediatek,mt2701-nor" + "mediatek,mt7623-nor" + "mediatek,mt8173-nor" + For mt8173, compatible should be "mediatek,mt8173-nor". + For every other SoC, should contain both the SoC-specific compatible string + and "mediatek,mt8173-nor". - reg: physical base address and length of the controller's register - clocks: the phandle of the clocks needed by the nor controller - clock-names: the names of the clocks diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt new file mode 100644 index 000000000000..56d5c19da41d --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt @@ -0,0 +1,41 @@ +* Oxford Semiconductor OXNAS NAND Controller + +Please refer to nand.txt for generic information regarding MTD NAND bindings. + +Required properties: + - compatible: "oxsemi,ox820-nand" + - reg: Base address and length for NAND mapped memory. + +Optional Properties: + - clocks: phandle to the NAND gate clock if needed. + - resets: phandle to the NAND reset control if needed. + +Example: + +nandc: nand-controller@41000000 { + compatible = "oxsemi,ox820-nand"; + reg = <0x41000000 0x100000>; + clocks = <&stdclk CLK_820_NAND>; + resets = <&reset RESET_NAND>; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "hamming"; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00e00000>; + read-only; + }; + + partition@e00000 { + label = "ubi"; + reg = <0x00e00000 0x07200000>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt b/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt new file mode 100644 index 000000000000..0040eb8895e0 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt @@ -0,0 +1,56 @@ +* Samsung S3C2410 and compatible NAND flash controller + +Required properties: +- compatible : The possible values are: + "samsung,s3c2410-nand" + "samsung,s3c2412-nand" + "samsung,s3c2440-nand" +- reg : register's location and length. +- #address-cells, #size-cells : see nand.txt +- clocks : phandle to the nand controller clock +- clock-names : must contain "nand" + +Optional child nodes: +Child nodes representing the available nand chips. + +Optional child properties: +- nand-ecc-mode : see nand.txt +- nand-on-flash-bbt : see nand.txt + +Each child device node may optionally contain a 'partitions' sub-node, +which further contains sub-nodes describing the flash partition mapping. +See partition.txt for more detail. + +Example: + +nand-controller@4e000000 { + compatible = "samsung,s3c2440-nand"; + reg = <0x4e000000 0x40>; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clocks HCLK_NAND>; + clock-names = "nand"; + + nand { + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x040000>; + }; + + partition@40000 { + label = "kernel"; + reg = <0x040000 0x500000>; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/mtd/tango-nand.txt b/Documentation/devicetree/bindings/mtd/tango-nand.txt new file mode 100644 index 000000000000..cd1bf2ac9055 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/tango-nand.txt @@ -0,0 +1,38 @@ +Sigma Designs Tango4 NAND Flash Controller (NFC) + +Required properties: + +- compatible: "sigma,smp8758-nand" +- reg: address/size of nfc_reg, nfc_mem, and pbus_reg +- dmas: reference to the DMA channel used by the controller +- dma-names: "rxtx" +- clocks: reference to the system clock +- #address-cells: <1> +- #size-cells: <0> + +Children nodes represent the available NAND chips. +See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. + +Example: + + nandc: nand-controller@2c000 { + compatible = "sigma,smp8758-nand"; + reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>; + dmas = <&dma0 3>; + dma-names = "rxtx"; + clocks = <&clkgen SYS_CLK>; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; /* CS0 */ + nand-ecc-strength = <14>; + nand-ecc-step-size = <1024>; + }; + + nand@1 { + reg = <1>; /* CS1 */ + nand-ecc-strength = <14>; + nand-ecc-step-size = <1024>; + }; + }; |