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-rw-r--r--Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml64
1 files changed, 50 insertions, 14 deletions
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index f6ed1a005e7a..c5dbb91ac402 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Samsung SoC series UFS PHY Device Tree Bindings
+title: Samsung SoC series UFS PHY
maintainers:
- Alim Akhtar <alim.akhtar@samsung.com>
@@ -17,6 +17,7 @@ properties:
enum:
- samsung,exynos7-ufs-phy
- samsung,exynosautov9-ufs-phy
+ - tesla,fsd-ufs-phy
reg:
maxItems: 1
@@ -26,23 +27,25 @@ properties:
- const: phy-pma
clocks:
- items:
- - description: PLL reference clock
- - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
- - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
- - description: symbol clock for output symbol ( tx0 symbol clock)
+ minItems: 1
+ maxItems: 4
clock-names:
- items:
- - const: ref_clk
- - const: rx1_symbol_clk
- - const: rx0_symbol_clk
- - const: tx0_symbol_clk
+ minItems: 1
+ maxItems: 4
samsung,pmu-syscon:
- $ref: '/schemas/types.yaml#/definitions/phandle'
- description: phandle for PMU system controller interface, used to
- control pmu registers bits for ufs m-phy
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ items:
+ minItems: 1
+ items:
+ - description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+ - description: offset of the pmu control register
+ description:
+ It can be phandle/offset pair. The second cell which can represent an
+ offset is optional.
required:
- "#phy-cells"
@@ -53,6 +56,39 @@ required:
- clock-names
- samsung,pmu-syscon
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-ufs-phy
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol (rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol (rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol (tx0 symbol clock)
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ else:
+ properties:
+ clocks:
+ items:
+ - description: PLL reference clock
+
+ clock-names:
+ items:
+ - const: ref_clk
+
additionalProperties: false
examples: