diff options
Diffstat (limited to 'Documentation/devicetree/bindings/soc')
| -rw-r--r-- | Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 58 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt | 30 |
2 files changed, 78 insertions, 10 deletions
diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt new file mode 100644 index 000000000000..ddeb5b6a53c1 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -0,0 +1,58 @@ +MediaTek PMIC Wrapper Driver + +This document describes the binding for the MediaTek PMIC wrapper. + +On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface +is not directly visible to the CPU, but only through the PMIC wrapper +inside the SoC. The communication between the SoC and the PMIC can +optionally be encrypted. Also a non standard Dual IO SPI mode can be +used to increase speed. + +IP Pairing + +on MT8135 the pins of some SoC internal peripherals can be on the PMIC. +The signals of these pins are routed over the SPI bus using the pwrap +bridge. In the binding description below the properties needed for bridging +are marked with "IP Pairing". These are optional on SoCs which do not support +IP Pairing + +Required properties in pwrap device node. +- compatible: + "mediatek,mt8135-pwrap" for MT8135 SoCs + "mediatek,mt8173-pwrap" for MT8173 SoCs +- interrupts: IRQ for pwrap in SOC +- reg-names: Must include the following entries: + "pwrap": Main registers base + "pwrap-bridge": bridge base (IP Pairing) +- reg: Must contain an entry for each entry in reg-names. +- reset-names: Must include the following entries: + "pwrap" + "pwrap-bridge" (IP Pairing) +- resets: Must contain an entry for each entry in reset-names. +- clock-names: Must include the following entries: + "spi": SPI bus clock + "wrap": Main module clock +- clocks: Must contain an entry for each entry in clock-names. + +Optional properities: +- pmic: Mediatek PMIC MFD is the child device of pwrap + See the following for child node definitions: + Documentation/devicetree/bindings/mfd/mt6397.txt + +Example: + pwrap: pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "wrap"; + + pmic { + compatible = "mediatek,mt6397"; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt index 4ce24d425bf1..2f5ede39bea2 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt @@ -6,7 +6,8 @@ configuration settings. The mode setting will govern the input/output mode of the 4 GSBI IOs. Required properties: -- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064 +- compatible: Should contain "qcom,gsbi-v1.0.0" +- cell-index: Should contain the GSBI index - reg: Address range for GSBI registers - clocks: required clock - clock-names: must contain "iface" entry @@ -16,6 +17,8 @@ Required properties: Optional properties: - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values. +- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses + dma. Required properties if child node exists: - #address-cells: Must be 1 @@ -39,6 +42,7 @@ Example for APQ8064: gsbi4@16300000 { compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; reg = <0x16300000 0x100>; clocks = <&gcc GSBI4_H_CLK>; clock-names = "iface"; @@ -48,22 +52,24 @@ Example for APQ8064: qcom,mode = <GSBI_PROT_I2C_UART>; qcom,crci = <GSBI_CRCI_QUP>; + syscon-tcsr = <&tcsr>; + /* child nodes go under here */ i2c_qup4: i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16380000 0x1000>; + interrupts = <0 153 0>; - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; + clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; - clock-frequency = <200000>; + clock-frequency = <200000>; - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - }; + }; uart4: serial@16340000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; @@ -76,3 +82,7 @@ Example for APQ8064: }; }; + tcsr: syscon@1a400000 { + compatible = "qcom,apq8064-tcsr", "syscon"; + reg = <0x1a400000 0x100>; + }; |