diff options
Diffstat (limited to 'Documentation/devicetree')
379 files changed, 17043 insertions, 5166 deletions
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index b2a9f9f8430b..96b1dad58253 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards @@ -121,7 +121,7 @@ Required properties (in root node): Required nodes: - soc: some node of the RealView platforms must be the SoC - node that contain the SoC-specific devices, withe the compatible + node that contain the SoC-specific devices, with the compatible string set to one of these tuples: "arm,realview-eb-soc", "simple-bus" "arm,realview-pb1176-soc", "simple-bus" diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 9fbde401a090..e003a553b986 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -10,6 +10,12 @@ PIT Timer required properties: - interrupts: Should contain interrupt for the PIT which is the IRQ line shared across all System Controller members. +PIT64B Timer required properties: +- compatible: Should be "microchip,sam9x60-pit64b" +- reg: Should contain registers location and length +- interrupts: Should contain interrupt for PIT64B timer +- clocks: Should contain the available clock sources for PIT64B timer. + System Timer (ST) required properties: - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" - reg: Should contain registers location and length diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt deleted file mode 100644 index 771f5d20ae18..000000000000 --- a/Documentation/devicetree/bindings/arm/idle-states.txt +++ /dev/null @@ -1,706 +0,0 @@ -========================================== -ARM idle states binding description -========================================== - -========================================== -1 - Introduction -========================================== - -ARM systems contain HW capable of managing power consumption dynamically, -where cores can be put in different low-power states (ranging from simple -wfi to power gating) according to OS PM policies. The CPU states representing -the range of dynamic idle states that a processor can enter at run-time, can be -specified through device tree bindings representing the parameters required -to enter/exit specific idle states on a given processor. - -According to the Server Base System Architecture document (SBSA, [3]), the -power states an ARM CPU can be put into are identified by the following list: - -- Running -- Idle_standby -- Idle_retention -- Sleep -- Off - -The power states described in the SBSA document define the basic CPU states on -top of which ARM platforms implement power management schemes that allow an OS -PM implementation to put the processor in different idle states (which include -states listed above; "off" state is not an idle state since it does not have -wake-up capabilities, hence it is not considered in this document). - -Idle state parameters (e.g. entry latency) are platform specific and need to be -characterized with bindings that provide the required information to OS PM -code so that it can build the required tables and use them at runtime. - -The device tree binding definition for ARM idle states is the subject of this -document. - -=========================================== -2 - idle-states definitions -=========================================== - -Idle states are characterized for a specific system through a set of -timing and energy related properties, that underline the HW behaviour -triggered upon idle states entry and exit. - -The following diagram depicts the CPU execution phases and related timing -properties required to enter and exit an idle state: - -..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__.. - | | | | | - - |<------ entry ------->| - | latency | - |<- exit ->| - | latency | - |<-------- min-residency -------->| - |<------- wakeup-latency ------->| - - Diagram 1: CPU idle state execution phases - -EXEC: Normal CPU execution. - -PREP: Preparation phase before committing the hardware to idle mode - like cache flushing. This is abortable on pending wake-up - event conditions. The abort latency is assumed to be negligible - (i.e. less than the ENTRY + EXIT duration). If aborted, CPU - goes back to EXEC. This phase is optional. If not abortable, - this should be included in the ENTRY phase instead. - -ENTRY: The hardware is committed to idle mode. This period must run - to completion up to IDLE before anything else can happen. - -IDLE: This is the actual energy-saving idle period. This may last - between 0 and infinite time, until a wake-up event occurs. - -EXIT: Period during which the CPU is brought back to operational - mode (EXEC). - -entry-latency: Worst case latency required to enter the idle state. The -exit-latency may be guaranteed only after entry-latency has passed. - -min-residency: Minimum period, including preparation and entry, for a given -idle state to be worthwhile energywise. - -wakeup-latency: Maximum delay between the signaling of a wake-up event and the -CPU being able to execute normal code again. If not specified, this is assumed -to be entry-latency + exit-latency. - -These timing parameters can be used by an OS in different circumstances. - -An idle CPU requires the expected min-residency time to select the most -appropriate idle state based on the expected expiry time of the next IRQ -(i.e. wake-up) that causes the CPU to return to the EXEC phase. - -An operating system scheduler may need to compute the shortest wake-up delay -for CPUs in the system by detecting how long will it take to get a CPU out -of an idle state, e.g.: - -wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0) - -In other words, the scheduler can make its scheduling decision by selecting -(e.g. waking-up) the CPU with the shortest wake-up delay. -The wake-up delay must take into account the entry latency if that period -has not expired. The abortable nature of the PREP period can be ignored -if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than -the worst case since it depends on the CPU operating conditions, i.e. caches -state). - -An OS has to reliably probe the wakeup-latency since some devices can enforce -latency constraint guarantees to work properly, so the OS has to detect the -worst case wake-up latency it can incur if a CPU is allowed to enter an -idle state, and possibly to prevent that to guarantee reliable device -functioning. - -The min-residency time parameter deserves further explanation since it is -expressed in time units but must factor in energy consumption coefficients. - -The energy consumption of a cpu when it enters a power state can be roughly -characterised by the following graph: - - | - | - | - e | - n | /--- - e | /------ - r | /------ - g | /----- - y | /------ - | ---- - | /| - | / | - | / | - | / | - | / | - | / | - |/ | - -----|-------+---------------------------------- - 0| 1 time(ms) - - Graph 1: Energy vs time example - -The graph is split in two parts delimited by time 1ms on the X-axis. -The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope -and denotes the energy costs incurred while entering and leaving the idle -state. -The graph curve in the area delimited by X-axis values = {x | x > 1ms } has -shallower slope and essentially represents the energy consumption of the idle -state. - -min-residency is defined for a given idle state as the minimum expected -residency time for a state (inclusive of preparation and entry) after -which choosing that state become the most energy efficient option. A good -way to visualise this, is by taking the same graph above and comparing some -states energy consumptions plots. - -For sake of simplicity, let's consider a system with two idle states IDLE1, -and IDLE2: - - | - | - | - | /-- IDLE1 - e | /--- - n | /---- - e | /--- - r | /-----/--------- IDLE2 - g | /-------/--------- - y | ------------ /---| - | / /---- | - | / /--- | - | / /---- | - | / /--- | - | --- | - | / | - | / | - |/ | time - ---/----------------------------+------------------------ - |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy - | - IDLE2-min-residency - - Graph 2: idle states min-residency example - -In graph 2 above, that takes into account idle states entry/exit energy -costs, it is clear that if the idle state residency time (i.e. time till next -wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state -choice energywise. - -This is mainly down to the fact that IDLE1 entry/exit energy costs are lower -than IDLE2. - -However, the lower power consumption (i.e. shallower energy curve slope) of -idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy -efficient. - -The time at which IDLE2 becomes more energy efficient than IDLE1 (and other -shallower states in a system with multiple idle states) is defined -IDLE2-min-residency and corresponds to the time when energy consumption of -IDLE1 and IDLE2 states breaks even. - -The definitions provided in this section underpin the idle states -properties specification that is the subject of the following sections. - -=========================================== -3 - idle-states node -=========================================== - -ARM processor idle states are defined within the idle-states node, which is -a direct child of the cpus node [1] and provides a container where the -processor idle states, defined as device tree nodes, are listed. - -- idle-states node - - Usage: Optional - On ARM systems, it is a container of processor idle - states nodes. If the system does not provide CPU - power management capabilities, or the processor just - supports idle_standby, an idle-states node is not - required. - - Description: idle-states node is a container node, where its - subnodes describe the CPU idle states. - - Node name must be "idle-states". - - The idle-states node's parent node must be the cpus node. - - The idle-states node's child nodes can be: - - - one or more state nodes - - Any other configuration is considered invalid. - - An idle-states node defines the following properties: - - - entry-method - Value type: <stringlist> - Usage and definition depend on ARM architecture version. - # On ARM v8 64-bit this property is required and must - be: - - "psci" - # On ARM 32-bit systems this property is optional - -This assumes that the "enable-method" property is set to "psci" in the cpu -node[6] that is responsible for setting up CPU idle management in the OS -implementation. - -The nodes describing the idle states (state) can only be defined -within the idle-states node, any other configuration is considered invalid -and therefore must be ignored. - -=========================================== -4 - state node -=========================================== - -A state node represents an idle state description and must be defined as -follows: - -- state node - - Description: must be child of the idle-states node - - The state node name shall follow standard device tree naming - rules ([5], 2.2.1 "Node names"), in particular state nodes which - are siblings within a single common parent must be given a unique name. - - The idle state entered by executing the wfi instruction (idle_standby - SBSA,[3][4]) is considered standard on all ARM platforms and therefore - must not be listed. - - With the definitions provided above, the following list represents - the valid properties for a state node: - - - compatible - Usage: Required - Value type: <stringlist> - Definition: Must be "arm,idle-state". - - - local-timer-stop - Usage: See definition - Value type: <none> - Definition: if present the CPU local timer control logic is - lost on state entry, otherwise it is retained. - - - entry-latency-us - Usage: Required - Value type: <prop-encoded-array> - Definition: u32 value representing worst case latency in - microseconds required to enter the idle state. - - - exit-latency-us - Usage: Required - Value type: <prop-encoded-array> - Definition: u32 value representing worst case latency - in microseconds required to exit the idle state. - The exit-latency-us duration may be guaranteed - only after entry-latency-us has passed. - - - min-residency-us - Usage: Required - Value type: <prop-encoded-array> - Definition: u32 value representing minimum residency duration - in microseconds, inclusive of preparation and - entry, for this idle state to be considered - worthwhile energy wise (refer to section 2 of - this document for a complete description). - - - wakeup-latency-us: - Usage: Optional - Value type: <prop-encoded-array> - Definition: u32 value representing maximum delay between the - signaling of a wake-up event and the CPU being - able to execute normal code again. If omitted, - this is assumed to be equal to: - - entry-latency-us + exit-latency-us - - It is important to supply this value on systems - where the duration of PREP phase (see diagram 1, - section 2) is non-neglibigle. - In such systems entry-latency-us + exit-latency-us - will exceed wakeup-latency-us by this duration. - - - status: - Usage: Optional - Value type: <string> - Definition: A standard device tree property [5] that indicates - the operational status of an idle-state. - If present, it shall be: - "okay": to indicate that the idle state is - operational. - "disabled": to indicate that the idle state has - been disabled in firmware so it is not - operational. - If the property is not present the idle-state must - be considered operational. - - - idle-state-name: - Usage: Optional - Value type: <string> - Definition: A string used as a descriptive name for the idle - state. - - In addition to the properties listed above, a state node may require - additional properties specific to the entry-method defined in the - idle-states node. Please refer to the entry-method bindings - documentation for properties definitions. - -=========================================== -4 - Examples -=========================================== - -Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU4: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU5: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU6: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU7: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU8: cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU9: cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU10: cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU11: cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU12: cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU13: cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU14: cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU15: cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - idle-states { - entry-method = "psci"; - - CPU_RETENTION_0_0: cpu-retention-0-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <20>; - exit-latency-us = <40>; - min-residency-us = <80>; - }; - - CLUSTER_RETENTION_0: cluster-retention-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <50>; - exit-latency-us = <100>; - min-residency-us = <250>; - wakeup-latency-us = <130>; - }; - - CPU_SLEEP_0_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <250>; - exit-latency-us = <500>; - min-residency-us = <950>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <600>; - exit-latency-us = <1100>; - min-residency-us = <2700>; - wakeup-latency-us = <1500>; - }; - - CPU_RETENTION_1_0: cpu-retention-1-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <20>; - exit-latency-us = <40>; - min-residency-us = <90>; - }; - - CLUSTER_RETENTION_1: cluster-retention-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <50>; - exit-latency-us = <100>; - min-residency-us = <270>; - wakeup-latency-us = <100>; - }; - - CPU_SLEEP_1_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <70>; - exit-latency-us = <100>; - min-residency-us = <300>; - wakeup-latency-us = <150>; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1200>; - min-residency-us = <3500>; - wakeup-latency-us = <1300>; - }; - }; - -}; - -Example 2 (ARM 32-bit, 8-cpu system, two clusters): - -cpus { - #size-cells = <0>; - #address-cells = <1>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - idle-states { - CPU_SLEEP_0_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <200>; - exit-latency-us = <100>; - min-residency-us = <400>; - wakeup-latency-us = <250>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <500>; - exit-latency-us = <1500>; - min-residency-us = <2500>; - wakeup-latency-us = <1700>; - }; - - CPU_SLEEP_1_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <500>; - min-residency-us = <900>; - wakeup-latency-us = <600>; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <800>; - exit-latency-us = <2000>; - min-residency-us = <6500>; - wakeup-latency-us = <2300>; - }; - }; - -}; - -=========================================== -5 - References -=========================================== - -[1] ARM Linux Kernel documentation - CPUs bindings - Documentation/devicetree/bindings/arm/cpus.yaml - -[2] ARM Linux Kernel documentation - PSCI bindings - Documentation/devicetree/bindings/arm/psci.yaml - -[3] ARM Server Base System Architecture (SBSA) - http://infocenter.arm.com/help/index.jsp - -[4] ARM Architecture Reference Manuals - http://infocenter.arm.com/help/index.jsp - -[5] Devicetree Specification - https://www.devicetree.org/specifications/ - -[6] ARM Linux Kernel documentation - Booting AArch64 Linux - Documentation/arm64/booting.rst diff --git a/Documentation/devicetree/bindings/arm/idle-states.yaml b/Documentation/devicetree/bindings/arm/idle-states.yaml new file mode 100644 index 000000000000..ea805c1e6b20 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/idle-states.yaml @@ -0,0 +1,661 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/idle-states.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM idle states binding description + +maintainers: + - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> + +description: |+ + ========================================== + 1 - Introduction + ========================================== + + ARM systems contain HW capable of managing power consumption dynamically, + where cores can be put in different low-power states (ranging from simple wfi + to power gating) according to OS PM policies. The CPU states representing the + range of dynamic idle states that a processor can enter at run-time, can be + specified through device tree bindings representing the parameters required to + enter/exit specific idle states on a given processor. + + According to the Server Base System Architecture document (SBSA, [3]), the + power states an ARM CPU can be put into are identified by the following list: + + - Running + - Idle_standby + - Idle_retention + - Sleep + - Off + + The power states described in the SBSA document define the basic CPU states on + top of which ARM platforms implement power management schemes that allow an OS + PM implementation to put the processor in different idle states (which include + states listed above; "off" state is not an idle state since it does not have + wake-up capabilities, hence it is not considered in this document). + + Idle state parameters (e.g. entry latency) are platform specific and need to + be characterized with bindings that provide the required information to OS PM + code so that it can build the required tables and use them at runtime. + + The device tree binding definition for ARM idle states is the subject of this + document. + + =========================================== + 2 - idle-states definitions + =========================================== + + Idle states are characterized for a specific system through a set of + timing and energy related properties, that underline the HW behaviour + triggered upon idle states entry and exit. + + The following diagram depicts the CPU execution phases and related timing + properties required to enter and exit an idle state: + + ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__.. + | | | | | + + |<------ entry ------->| + | latency | + |<- exit ->| + | latency | + |<-------- min-residency -------->| + |<------- wakeup-latency ------->| + + Diagram 1: CPU idle state execution phases + + EXEC: Normal CPU execution. + + PREP: Preparation phase before committing the hardware to idle mode + like cache flushing. This is abortable on pending wake-up + event conditions. The abort latency is assumed to be negligible + (i.e. less than the ENTRY + EXIT duration). If aborted, CPU + goes back to EXEC. This phase is optional. If not abortable, + this should be included in the ENTRY phase instead. + + ENTRY: The hardware is committed to idle mode. This period must run + to completion up to IDLE before anything else can happen. + + IDLE: This is the actual energy-saving idle period. This may last + between 0 and infinite time, until a wake-up event occurs. + + EXIT: Period during which the CPU is brought back to operational + mode (EXEC). + + entry-latency: Worst case latency required to enter the idle state. The + exit-latency may be guaranteed only after entry-latency has passed. + + min-residency: Minimum period, including preparation and entry, for a given + idle state to be worthwhile energywise. + + wakeup-latency: Maximum delay between the signaling of a wake-up event and the + CPU being able to execute normal code again. If not specified, this is assumed + to be entry-latency + exit-latency. + + These timing parameters can be used by an OS in different circumstances. + + An idle CPU requires the expected min-residency time to select the most + appropriate idle state based on the expected expiry time of the next IRQ + (i.e. wake-up) that causes the CPU to return to the EXEC phase. + + An operating system scheduler may need to compute the shortest wake-up delay + for CPUs in the system by detecting how long will it take to get a CPU out + of an idle state, e.g.: + + wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0) + + In other words, the scheduler can make its scheduling decision by selecting + (e.g. waking-up) the CPU with the shortest wake-up delay. + The wake-up delay must take into account the entry latency if that period + has not expired. The abortable nature of the PREP period can be ignored + if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than + the worst case since it depends on the CPU operating conditions, i.e. caches + state). + + An OS has to reliably probe the wakeup-latency since some devices can enforce + latency constraint guarantees to work properly, so the OS has to detect the + worst case wake-up latency it can incur if a CPU is allowed to enter an + idle state, and possibly to prevent that to guarantee reliable device + functioning. + + The min-residency time parameter deserves further explanation since it is + expressed in time units but must factor in energy consumption coefficients. + + The energy consumption of a cpu when it enters a power state can be roughly + characterised by the following graph: + + | + | + | + e | + n | /--- + e | /------ + r | /------ + g | /----- + y | /------ + | ---- + | /| + | / | + | / | + | / | + | / | + | / | + |/ | + -----|-------+---------------------------------- + 0| 1 time(ms) + + Graph 1: Energy vs time example + + The graph is split in two parts delimited by time 1ms on the X-axis. + The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope + and denotes the energy costs incurred while entering and leaving the idle + state. + The graph curve in the area delimited by X-axis values = {x | x > 1ms } has + shallower slope and essentially represents the energy consumption of the idle + state. + + min-residency is defined for a given idle state as the minimum expected + residency time for a state (inclusive of preparation and entry) after + which choosing that state become the most energy efficient option. A good + way to visualise this, is by taking the same graph above and comparing some + states energy consumptions plots. + + For sake of simplicity, let's consider a system with two idle states IDLE1, + and IDLE2: + + | + | + | + | /-- IDLE1 + e | /--- + n | /---- + e | /--- + r | /-----/--------- IDLE2 + g | /-------/--------- + y | ------------ /---| + | / /---- | + | / /--- | + | / /---- | + | / /--- | + | --- | + | / | + | / | + |/ | time + ---/----------------------------+------------------------ + |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy + | + IDLE2-min-residency + + Graph 2: idle states min-residency example + + In graph 2 above, that takes into account idle states entry/exit energy + costs, it is clear that if the idle state residency time (i.e. time till next + wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state + choice energywise. + + This is mainly down to the fact that IDLE1 entry/exit energy costs are lower + than IDLE2. + + However, the lower power consumption (i.e. shallower energy curve slope) of + idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy + efficient. + + The time at which IDLE2 becomes more energy efficient than IDLE1 (and other + shallower states in a system with multiple idle states) is defined + IDLE2-min-residency and corresponds to the time when energy consumption of + IDLE1 and IDLE2 states breaks even. + + The definitions provided in this section underpin the idle states + properties specification that is the subject of the following sections. + + =========================================== + 3 - idle-states node + =========================================== + + ARM processor idle states are defined within the idle-states node, which is + a direct child of the cpus node [1] and provides a container where the + processor idle states, defined as device tree nodes, are listed. + + On ARM systems, it is a container of processor idle states nodes. If the + system does not provide CPU power management capabilities, or the processor + just supports idle_standby, an idle-states node is not required. + + =========================================== + 4 - References + =========================================== + + [1] ARM Linux Kernel documentation - CPUs bindings + Documentation/devicetree/bindings/arm/cpus.yaml + + [2] ARM Linux Kernel documentation - PSCI bindings + Documentation/devicetree/bindings/arm/psci.yaml + + [3] ARM Server Base System Architecture (SBSA) + http://infocenter.arm.com/help/index.jsp + + [4] ARM Architecture Reference Manuals + http://infocenter.arm.com/help/index.jsp + + [6] ARM Linux Kernel documentation - Booting AArch64 Linux + Documentation/arm64/booting.rst + +properties: + $nodename: + const: idle-states + + entry-method: + description: | + Usage and definition depend on ARM architecture version. + + On ARM v8 64-bit this property is required. + On ARM 32-bit systems this property is optional + + This assumes that the "enable-method" property is set to "psci" in the cpu + node[6] that is responsible for setting up CPU idle management in the OS + implementation. + const: psci + +patternProperties: + "^(cpu|cluster)-": + type: object + description: | + Each state node represents an idle state description and must be defined + as follows. + + The idle state entered by executing the wfi instruction (idle_standby + SBSA,[3][4]) is considered standard on all ARM platforms and therefore + must not be listed. + + In addition to the properties listed above, a state node may require + additional properties specific to the entry-method defined in the + idle-states node. Please refer to the entry-method bindings + documentation for properties definitions. + + properties: + compatible: + const: arm,idle-state + + local-timer-stop: + description: + If present the CPU local timer control logic is + lost on state entry, otherwise it is retained. + type: boolean + + entry-latency-us: + description: + Worst case latency in microseconds required to enter the idle state. + + exit-latency-us: + description: + Worst case latency in microseconds required to exit the idle state. + The exit-latency-us duration may be guaranteed only after + entry-latency-us has passed. + + min-residency-us: + description: + Minimum residency duration in microseconds, inclusive of preparation + and entry, for this idle state to be considered worthwhile energy wise + (refer to section 2 of this document for a complete description). + + wakeup-latency-us: + description: | + Maximum delay between the signaling of a wake-up event and the CPU + being able to execute normal code again. If omitted, this is assumed + to be equal to: + + entry-latency-us + exit-latency-us + + It is important to supply this value on systems where the duration of + PREP phase (see diagram 1, section 2) is non-neglibigle. In such + systems entry-latency-us + exit-latency-us will exceed + wakeup-latency-us by this duration. + + idle-state-name: + $ref: /schemas/types.yaml#definitions/string + description: + A string used as a descriptive name for the idle state. + + required: + - compatible + - entry-latency-us + - exit-latency-us + - min-residency-us + +additionalProperties: false + +examples: + - | + + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@100000000 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100000001 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100000100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100000101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010000 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010001 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + idle-states { + entry-method = "psci"; + + CPU_RETENTION_0_0: cpu-retention-0-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <80>; + }; + + CLUSTER_RETENTION_0: cluster-retention-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <250>; + wakeup-latency-us = <130>; + }; + + CPU_SLEEP_0_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <250>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + + CPU_RETENTION_1_0: cpu-retention-1-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <90>; + }; + + CLUSTER_RETENTION_1: cluster-retention-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <270>; + wakeup-latency-us = <100>; + }; + + CPU_SLEEP_1_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <70>; + exit-latency-us = <100>; + min-residency-us = <300>; + wakeup-latency-us = <150>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1200>; + min-residency-us = <3500>; + wakeup-latency-us = <1300>; + }; + }; + }; + + - | + // Example 2 (ARM 32-bit, 8-cpu system, two clusters): + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + idle-states { + cpu_sleep_0_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <200>; + exit-latency-us = <100>; + min-residency-us = <400>; + wakeup-latency-us = <250>; + }; + + cluster_sleep_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <1500>; + min-residency-us = <2500>; + wakeup-latency-us = <1700>; + }; + + cpu_sleep_1_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <500>; + min-residency-us = <900>; + wakeup-latency-us = <600>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <800>; + exit-latency-us = <2000>; + min-residency-us = <6500>; + wakeup-latency-us = <2300>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt deleted file mode 100644 index 25307aa1eb9b..000000000000 --- a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt +++ /dev/null @@ -1,37 +0,0 @@ -ML-AHB interconnect bindings - -These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects -a Cortex-M subsystem with dedicated memories. -The MCU SRAM and RETRAM memory parts can be accessed through different addresses -(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the -Cortex-M firmware accesses among those ports allows to tune the system -performance. - -[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf -[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping - -Required properties: -- compatible: should be "simple-bus" -- dma-ranges: describes memory addresses translation between the local CPU and - the remote Cortex-M processor. Each memory region, is declared with - 3 parameters: - - param 1: device base address (Cortex-M processor address) - - param 2: physical base address (local CPU address) - - param 3: size of the memory region. - -The Cortex-M remote processor accessed via the mlahb interconnect is described -by a child node. - -Example: -mlahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges = <0x00000000 0x38000000 0x10000>, - <0x10000000 0x10000000 0x60000>, - <0x30000000 0x30000000 0x60000>; - - m4_rproc: m4@10000000 { - ... - }; -}; diff --git a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml new file mode 100644 index 000000000000..68917bb7c7e8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 ML-AHB interconnect bindings + +maintainers: + - Fabien Dessenne <fabien.dessenne@st.com> + - Arnaud Pouliquen <arnaud.pouliquen@st.com> + +description: | + These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects + a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory + parts can be accessed through different addresses (see "RAM aliases" in [1]) + using different buses (see [2]): balancing the Cortex-M firmware accesses + among those ports allows to tune the system performance. + [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf + [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + contains: + enum: + - st,mlahb + + dma-ranges: + description: | + Describe memory addresses translation between the local CPU and the + remote Cortex-M processor. Each memory region, is declared with + 3 parameters: + - param 1: device base address (Cortex-M processor address) + - param 2: physical base address (local CPU address) + - param 3: size of the memory region. + maxItems: 3 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - '#address-cells' + - '#size-cells' + - dma-ranges + +examples: + - | + mlahb: ahb { + compatible = "st,mlahb", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10000000 0x40000>; + ranges; + dma-ranges = <0x00000000 0x38000000 0x10000>, + <0x10000000 0x10000000 0x60000>, + <0x30000000 0x30000000 0x60000>; + + m4_rproc: m4@10000000 { + reg = <0x10000000 0x40000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml new file mode 100644 index 000000000000..0dedf94c8578 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 Platforms System Controller bindings + +maintainers: + - Alexandre Torgue <alexandre.torgue@st.com> + - Christophe Roullier <christophe.roullier@st.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - st,stm32mp157-syscfg + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt deleted file mode 100644 index c92d411fd023..000000000000 --- a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt +++ /dev/null @@ -1,16 +0,0 @@ -STMicroelectronics STM32 Platforms System Controller - -Properties: - - compatible : should contain two values. First value must be : - - " st,stm32mp157-syscfg " - for stm32mp157 based SoCs, - second value must be always "syscon". - - reg : offset and length of the register set. - - clocks: phandle to the syscfg clock - - Example: - syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - clocks = <&rcc SYSCFG>; - }; - diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 8a1e38a1d7ab..cffe8bb0bad1 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -8,7 +8,7 @@ title: Allwinner platforms device tree bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: $nodename: diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml new file mode 100644 index 000000000000..9370e64992dd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner Memory Bus (MBUS) controller + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + The MBUS controller drives the MBUS that other devices in the SoC + will use to perform DMA. It also has a register interface that + allows to monitor and control the bandwidth and priorities for + masters on that bus. + + Each device having to perform their DMA through the MBUS must have + the interconnects and interconnect-names properties set to the MBUS + controller and with "dma-mem" as the interconnect name. + +properties: + "#interconnect-cells": + const: 1 + description: + The content of the cell is the MBUS ID. + + compatible: + enum: + - allwinner,sun5i-a13-mbus + - allwinner,sun8i-h3-mbus + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + dma-ranges: + description: + See section 2.3.9 of the DeviceTree Specification. + +required: + - "#interconnect-cells" + - compatible + - reg + - clocks + - dma-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun5i-ccu.h> + + mbus: dram-controller@1c01000 { + compatible = "allwinner,sun5i-a13-mbus"; + reg = <0x01c01000 0x1000>; + clocks = <&ccu CLK_MBUS>; + dma-ranges = <0x00000000 0x40000000 0x20000000>; + #interconnect-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt deleted file mode 100644 index 2005bb486705..000000000000 --- a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt +++ /dev/null @@ -1,37 +0,0 @@ -Allwinner Memory Bus (MBUS) controller - -The MBUS controller drives the MBUS that other devices in the SoC will -use to perform DMA. It also has a register interface that allows to -monitor and control the bandwidth and priorities for masters on that -bus. - -Required properties: - - compatible: Must be one of: - - allwinner,sun5i-a13-mbus - - allwinner,sun8i-h3-mbus - - reg: Offset and length of the register set for the controller - - clocks: phandle to the clock driving the controller - - dma-ranges: See section 2.3.9 of the DeviceTree Specification - - #interconnect-cells: Must be one, with the argument being the MBUS - port ID - -Each device having to perform their DMA through the MBUS must have the -interconnects and interconnect-names properties set to the MBUS -controller and with "dma-mem" as the interconnect name. - -Example: - -mbus: dram-controller@1c01000 { - compatible = "allwinner,sun5i-a13-mbus"; - reg = <0x01c01000 0x1000>; - clocks = <&ccu CLK_MBUS>; - dma-ranges = <0x00000000 0x40000000 0x20000000>; - #interconnect-cells = <1>; -}; - -fe0: display-frontend@1e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - ... - interconnects = <&mbus 19>; - interconnect-names = "dma-mem"; -}; diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index 55c6fab1b373..77091a277642 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -9,8 +9,6 @@ PHYs. Required properties: - compatible : compatible string, one of: - - "allwinner,sun4i-a10-ahci" - - "allwinner,sun8i-r40-ahci" - "brcm,iproc-ahci" - "hisilicon,hisi-ahci" - "cavium,octeon-7130-ahci" @@ -45,8 +43,6 @@ Required properties when using sub-nodes: - #address-cells : number of cells to encode an address - #size-cells : number of cells representing the size of an address -For allwinner,sun8i-r40-ahci, the reset property must be present. - Sub-nodes required properties: - reg : the port number And at least one of the following properties: @@ -60,14 +56,6 @@ Examples: interrupts = <115>; }; - ahci: sata@1c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <56>; - clocks = <&pll6 0>, <&ahb_gates 25>; - target-supply = <®_ahci_5v>; - }; - With sub-nodes: sata@f7e90000 { compatible = "marvell,berlin2q-achi", "generic-ahci"; diff --git a/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.yaml b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.yaml new file mode 100644 index 000000000000..cb530b46beff --- /dev/null +++ b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/allwinner,sun4i-a10-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 AHCI SATA Controller bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + compatible: + const: allwinner,sun4i-a10-ahci + + reg: + maxItems: 1 + + clocks: + items: + - description: AHCI Bus Clock + - description: AHCI Module Clock + + interrupts: + maxItems: 1 + + target-supply: + description: Regulator for SATA target power + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + ahci: sata@1c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <56>; + clocks = <&pll6 0>, <&ahb_gates 25>; + target-supply = <®_ahci_5v>; + }; diff --git a/Documentation/devicetree/bindings/ata/allwinner,sun8i-r40-ahci.yaml b/Documentation/devicetree/bindings/ata/allwinner,sun8i-r40-ahci.yaml new file mode 100644 index 000000000000..e6b42a113ff1 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/allwinner,sun8i-r40-ahci.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner R40 AHCI SATA Controller bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + compatible: + const: allwinner,sun8i-r40-ahci + + reg: + maxItems: 1 + + clocks: + items: + - description: AHCI Bus Clock + - description: AHCI Module Clock + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: ahci + + ahci-supply: + description: Regulator for the AHCI controller + + phy-supply: + description: Regulator for the SATA PHY power + +required: + - compatible + - reg + - clocks + - interrupts + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/sun8i-r40-ccu.h> + #include <dt-bindings/reset/sun8i-r40-ccu.h> + + ahci: sata@1c18000 { + compatible = "allwinner,sun8i-r40-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; + resets = <&ccu RST_BUS_SATA>; + reset-names = "ahci"; + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo3>; + }; + +... diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt index 7713a413c6a7..b9ae4ce4a0a0 100644 --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt @@ -5,6 +5,7 @@ Each SATA controller should have its own node. Required properties: - compatible : should be one or more of + "brcm,bcm7216-ahci" "brcm,bcm7425-ahci" "brcm,bcm7445-ahci" "brcm,bcm-nsp-ahci" @@ -14,6 +15,12 @@ Required properties: - reg-names : "ahci" and "top-ctrl" - interrupts : interrupt mapping for SATA IRQ +Optional properties: + +- reset: for "brcm,bcm7216-ahci" must be a valid reset phandle + pointing to the RESCAL reset controller provider node. +- reset-names: for "brcm,bcm7216-ahci", must be "rescal". + Also see ahci-platform.txt. Example: diff --git a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt b/Documentation/devicetree/bindings/ata/faraday,ftide010.txt deleted file mode 100644 index a0c64a29104d..000000000000 --- a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Faraday Technology FTIDE010 PATA controller - -This controller is the first Faraday IDE interface block, used in the -StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini -platform. The controller can do PIO modes 0 through 4, Multi-word DMA -(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6. - -On the Gemini platform, this PATA block is accompanied by a PATA to -SATA bridge in order to support SATA. This is why a phandle to that -controller is compulsory on that platform. - -The timing properties are unique per-SoC, not per-board. - -Required properties: -- compatible: should be one of - "cortina,gemini-pata", "faraday,ftide010" - "faraday,ftide010" -- interrupts: interrupt for the block -- reg: registers and size for the block - -Optional properties: -- clocks: a SoC clock running the peripheral. -- clock-names: should be set to "PCLK" for the peripheral clock. - -Required properties for "cortina,gemini-pata" compatible: -- sata: a phande to the Gemini PATA to SATA bridge, see - cortina,gemini-sata-bridge.txt for details. - -Example: - -ata@63000000 { - compatible = "cortina,gemini-pata", "faraday,ftide010"; - reg = <0x63000000 0x100>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - clocks = <&gcc GEMINI_CLK_GATE_IDE>; - clock-names = "PCLK"; - sata = <&sata>; -}; diff --git a/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml b/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml new file mode 100644 index 000000000000..bfc6357476fd --- /dev/null +++ b/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday Technology FTIDE010 PATA controller + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: | + This controller is the first Faraday IDE interface block, used in the + StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini + platform. The controller can do PIO modes 0 through 4, Multi-word DMA + (MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6. + + On the Gemini platform, this PATA block is accompanied by a PATA to + SATA bridge in order to support SATA. This is why a phandle to that + controller is compulsory on that platform. + + The timing properties are unique per-SoC, not per-board. + +properties: + compatible: + oneOf: + - const: faraday,ftide010 + - items: + - const: cortina,gemini-pata + - const: faraday,ftide010 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + + clock-names: + const: PCLK + + sata: + description: + phandle to the Gemini PATA to SATA bridge, if available + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: pata-common.yaml# + + - if: + properties: + compatible: + contains: + const: cortina,gemini-pata + + then: + required: + - sata + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/cortina,gemini-clock.h> + + ide@63000000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63000000 0x100>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GEMINI_CLK_GATE_IDE>; + clock-names = "PCLK"; + sata = <&sata>; + #address-cells = <1>; + #size-cells = <0>; + ide-port@0 { + reg = <0>; + }; + ide-port@1 { + reg = <1>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/ata/pata-common.yaml b/Documentation/devicetree/bindings/ata/pata-common.yaml new file mode 100644 index 000000000000..fc5ebbe7108d --- /dev/null +++ b/Documentation/devicetree/bindings/ata/pata-common.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/pata-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Parallel AT attachment (PATA) controllers + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: | + This document defines device tree properties common to most Parallel + ATA (PATA, also known as IDE) AT attachment storage devices. + It doesn't constitue a device tree binding specification by itself but is + meant to be referenced by device tree bindings. + + The PATA (IDE) controller-specific device tree bindings are responsible for + defining whether each property is required or optional. + +properties: + $nodename: + pattern: "^ide(@.*)?$" + description: + Specifies the host controller node. PATA host controller nodes are named + "ide". + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^ide-port@[0-1]$": + description: | + DT nodes for ports connected on the PATA host. The master drive will have + ID number 0 and the slave drive will have ID number 1. The PATA port + nodes will be named "ide-port". + type: object + + properties: + reg: + minimum: 0 + maximum: 1 + description: + The ID number of the drive port, 0 for the master port and 1 for the + slave port. + +... diff --git a/Documentation/devicetree/bindings/ata/sata-common.yaml b/Documentation/devicetree/bindings/ata/sata-common.yaml new file mode 100644 index 000000000000..6783a4dec6b5 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/sata-common.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/sata-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Serial AT attachment (SATA) controllers + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: | + This document defines device tree properties common to most Serial + AT attachment (SATA) storage devices. It doesn't constitute a device tree + binding specification by itself but is meant to be referenced by device + tree bindings. + + The SATA controller-specific device tree bindings are responsible for + defining whether each property is required or optional. + +properties: + $nodename: + pattern: "^sata(@.*)?$" + description: + Specifies the host controller node. SATA host controller nodes are named + "sata" + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^sata-port@[0-9a-e]$": + description: | + DT nodes for ports connected on the SATA host. The SATA port + nodes will be named "sata-port". + type: object + + properties: + reg: + minimum: 0 + maximum: 14 + description: + The ID number of the drive port SATA can potentially use a port + multiplier making it possible to connect up to 15 disks to a single + SATA port. + +... diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml index d2a872286437..f0b3d30fbb76 100644 --- a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml +++ b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml @@ -8,7 +8,7 @@ title: Allwinner A64 Display Engine Bus Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: $nodename: diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml index be32f087c529..9fe11ceecdba 100644 --- a/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml +++ b/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml @@ -8,7 +8,7 @@ title: Allwinner A23 RSB Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#address-cells": diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml new file mode 100644 index 000000000000..558db4b6ed17 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 AHB Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-ahb-clk + - allwinner,sun6i-a31-ahb1-clk + - allwinner,sun8i-h3-ahb2-clk + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-ahb-clk + + then: + properties: + clocks: + maxItems: 1 + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-ahb1-clk + + then: + properties: + clocks: + maxItems: 4 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-h3-ahb2-clk + + then: + properties: + clocks: + maxItems: 2 + +examples: + - | + ahb@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>; + clock-output-names = "ahb"; + }; + + - | + ahb1@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + - | + ahb2_clk@1c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6d2>; + clock-output-names = "ahb2"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml new file mode 100644 index 000000000000..b1e3d739beb2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 APB0 Bus Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-apb0-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + apb0@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + clock-output-names = "apb0"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml new file mode 100644 index 000000000000..51b7a6d4ea54 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 APB1 Bus Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-apb1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-axi-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-axi-clk.yaml new file mode 100644 index 000000000000..d801158e15de --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-axi-clk.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 AXI Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-axi-clk + - allwinner,sun8i-a23-axi-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + axi@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + - | + axi_clk@1c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml index 64938fdaea55..4d382128b711 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -8,7 +8,7 @@ title: Allwinner Clock Control Unit Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#clock-cells": diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml new file mode 100644 index 000000000000..0dfafba1a168 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-cpu-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 CPU Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-cpu-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + cpu@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-display-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-display-clk.yaml new file mode 100644 index 000000000000..7484a7ab7dea --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-display-clk.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-display-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Display Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + "#reset-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-display-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-gates-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-gates-clk.yaml new file mode 100644 index 000000000000..ed1b2126a81b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-gates-clk.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Bus Gates Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + This additional argument passed to that clock is the offset of + the bit controlling this particular gate in the register. + + compatible: + oneOf: + - const: allwinner,sun4i-a10-gates-clk + - const: allwinner,sun4i-a10-axi-gates-clk + - const: allwinner,sun4i-a10-ahb-gates-clk + - const: allwinner,sun5i-a10s-ahb-gates-clk + - const: allwinner,sun5i-a13-ahb-gates-clk + - const: allwinner,sun7i-a20-ahb-gates-clk + - const: allwinner,sun6i-a31-ahb1-gates-clk + - const: allwinner,sun8i-a23-ahb1-gates-clk + - const: allwinner,sun9i-a80-ahb0-gates-clk + - const: allwinner,sun9i-a80-ahb1-gates-clk + - const: allwinner,sun9i-a80-ahb2-gates-clk + - const: allwinner,sun4i-a10-apb0-gates-clk + - const: allwinner,sun5i-a10s-apb0-gates-clk + - const: allwinner,sun5i-a13-apb0-gates-clk + - const: allwinner,sun7i-a20-apb0-gates-clk + - const: allwinner,sun9i-a80-apb0-gates-clk + - const: allwinner,sun8i-a83t-apb0-gates-clk + - const: allwinner,sun4i-a10-apb1-gates-clk + - const: allwinner,sun5i-a13-apb1-gates-clk + - const: allwinner,sun5i-a10s-apb1-gates-clk + - const: allwinner,sun6i-a31-apb1-gates-clk + - const: allwinner,sun7i-a20-apb1-gates-clk + - const: allwinner,sun8i-a23-apb1-gates-clk + - const: allwinner,sun9i-a80-apb1-gates-clk + - const: allwinner,sun6i-a31-apb2-gates-clk + - const: allwinner,sun8i-a23-apb2-gates-clk + - const: allwinner,sun8i-a83t-bus-gates-clk + - const: allwinner,sun9i-a80-apbs-gates-clk + - const: allwinner,sun4i-a10-dram-gates-clk + + - items: + - const: allwinner,sun5i-a13-dram-gates-clk + - const: allwinner,sun4i-a10-gates-clk + + - items: + - const: allwinner,sun8i-h3-apb0-gates-clk + - const: allwinner,sun4i-a10-gates-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-indices: + minItems: 1 + maxItems: 64 + + clock-output-names: + minItems: 1 + maxItems: 64 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-indices + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-indices = <0>; + clock-output-names = "axi_dram"; + }; + + - | + clk@1c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <3>, + <4>, <5>, <6>, + <7>, <8>, <9>, + <10>, <11>, <12>, + <13>, <14>, <16>, + <17>, <18>, <20>, + <21>, <22>, <23>, + <24>, <25>, <26>, + <32>, <33>, <34>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <45>, + <46>, <47>, + <50>, <52>; + clock-output-names = "ahb_usb0", "ahb_ehci0", + "ahb_ohci0", "ahb_ehci1", + "ahb_ohci1", "ahb_ss", "ahb_dma", + "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_mmc3", "ahb_ms", + "ahb_nand", "ahb_sdram", "ahb_ace", + "ahb_emac", "ahb_ts", "ahb_spi0", + "ahb_spi1", "ahb_spi2", "ahb_spi3", + "ahb_pata", "ahb_sata", "ahb_gps", + "ahb_ve", "ahb_tvd", "ahb_tve0", + "ahb_tve1", "ahb_lcd0", "ahb_lcd1", + "ahb_csi0", "ahb_csi1", "ahb_hdmi", + "ahb_de_be0", "ahb_de_be1", + "ahb_de_fe0", "ahb_de_fe1", + "ahb_mp", "ahb_mali400"; + }; + + + - | + clk@1c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-apb0-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-indices = <0>, <1>, + <2>, <3>, + <5>, <6>, + <7>, <10>; + clock-output-names = "apb0_codec", "apb0_spdif", + "apb0_ac97", "apb0_iis", + "apb0_pio", "apb0_ir0", + "apb0_ir1", "apb0_keypad"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml new file mode 100644 index 000000000000..18f131e262b4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mbus-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 MBUS Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun5i-a13-mbus-clk + - allwinner,sun8i-a23-mbus-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; + + - | + clk@1c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5>; + clock-output-names = "mbus"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml new file mode 100644 index 000000000000..5199285a661a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Module 1 Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + There is three different outputs: the main clock, with the ID 0, + and the output and sample clocks, with the IDs 1 and 2, + respectively. + + compatible: + enum: + - allwinner,sun4i-a10-mmc-clk + - allwinner,sun9i-a80-mmc-clk + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 3 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-mmc-clk + +then: + properties: + clocks: + maxItems: 3 + +else: + properties: + clocks: + maxItems: 2 + +examples: + - | + clk@1c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + - | + clk@6000410 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-clk"; + reg = <0x06000410 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "mmc0", "mmc0_output", + "mmc0_sample"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml new file mode 100644 index 000000000000..3e2abe3e67c1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Module 0 Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +select: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-mod0-clk + - allwinner,sun9i-a80-mod0-clk + + # The PRCM on the A31 and A23 will have the reg property missing, + # since it's set at the upper level node, and will be validated by + # PRCM's schema. Make sure we only validate standalone nodes. + required: + - compatible + - reg + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-mod0-clk + - allwinner,sun9i-a80-mod0-clk + + reg: + maxItems: 1 + + clocks: + # On the A80, the PRCM mod0 clocks have 2 parents. + minItems: 2 + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + - | + clk@8001454 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x08001454 0x4>; + clocks = <&osc32k>, <&osc24M>; + clock-output-names = "r_ir"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml new file mode 100644 index 000000000000..7ddb55c75cff --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Module 1 Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-mod1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun4i-a10-pll2.h> + + clk@1c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "spdif"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml new file mode 100644 index 000000000000..69cfa4a3d562 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Gatable Oscillator Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-osc-clk + + reg: + maxItems: 1 + + clock-frequency: + description: > + Frequency of the main oscillator. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clock-frequency + - clock-output-names + +additionalProperties: false + +examples: + - | + osc24M: clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml new file mode 100644 index 000000000000..e9c4cf834aa7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 CPU PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-pll1-clk + - allwinner,sun6i-a31-pll1-clk + - allwinner,sun8i-a23-pll1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "osc24M"; + }; + + - | + clk@1c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + - | + clk@1c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml new file mode 100644 index 000000000000..4b80a42fb3da --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Video PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-pll3-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml new file mode 100644 index 000000000000..415bd77de53d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 DRAM PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The first output is the DRAM clock output, the second is meant + for peripherals on the SoC. + + compatible: + const: allwinner,sun4i-a10-pll5-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 2 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml new file mode 100644 index 000000000000..ec5652f76027 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Peripheral PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The first output is the SATA clock output, the second is the + regular PLL output, the third is a PLL output at twice the rate. + + compatible: + const: allwinner,sun4i-a10-pll6-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 3 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml new file mode 100644 index 000000000000..0a335c615efd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 TCON Channel 0 Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun4i-a10-tcon-ch0-clk + - allwinner,sun4i-a10-tcon-ch1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-tcon-ch0-clk + +then: + required: + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clk@1c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch0-sclk"; + }; + + - | + clk@1c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch1-sclk"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-usb-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-usb-clk.yaml new file mode 100644 index 000000000000..cd95d25bfe7c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-usb-clk.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-usb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 USB Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun4i-a10-usb-clk + - allwinner,sun5i-a13-usb-clk + - allwinner,sun6i-a31-usb-clk + - allwinner,sun8i-a23-usb-clk + - allwinner,sun8i-h3-usb-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + minItems: 2 + maxItems: 8 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-usb-clk + + then: + properties: + clock-output-names: + maxItems: 3 + + - if: + properties: + compatible: + contains: + const: allwinner,sun5i-a13-usb-clk + + then: + properties: + clock-output-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-usb-clk + + then: + properties: + clock-output-names: + maxItems: 6 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-a23-usb-clk + + then: + properties: + clock-output-names: + maxItems: 5 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-h3-usb-clk + + then: + properties: + clock-output-names: + maxItems: 8 + +examples: + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_phy"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", + "usb_ohci0", "usb_ohci1", + "usb_ohci2"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-a23-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic", + "usb_hsic_12M", "usb_ohci0"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", + "usb_phy2", "usb_phy3", + "usb_ohci0", "usb_ohci1", + "usb_ohci2", "usb_ohci3"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ve-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ve-clk.yaml new file mode 100644 index 000000000000..5dfd0c1c27b4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ve-clk.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ve-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Video Engine Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + "#reset-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-ve-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c2013c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-ve-clk"; + reg = <0x01c2013c 0x4>; + clocks = <&pll4>; + clock-output-names = "ve"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml new file mode 100644 index 000000000000..99add7991c48 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A13 AHB Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun5i-a13-ahb-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + ahb@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>, <&cpu>, <&pll6 1>; + clock-output-names = "ahb"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml new file mode 100644 index 000000000000..5f377205af71 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 Peripheral PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The first output is the regular PLL output, the second is a PLL + output at twice the rate. + + compatible: + const: allwinner,sun6i-a31-pll6-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 2 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml new file mode 100644 index 000000000000..59e5dce1b65a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A20 GMAC TX Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun7i-a20-gmac-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + description: > + The parent clocks shall be fixed rate dummy clocks at 25 MHz and + 125 MHz, respectively. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20164 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c20164 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-out-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-out-clk.yaml new file mode 100644 index 000000000000..c745733bcf04 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-out-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-out-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A20 Output Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun7i-a20-out-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c201f0 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-out-clk"; + reg = <0x01c201f0 0x4>; + clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; + clock-output-names = "clk_out_a"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml new file mode 100644 index 000000000000..3eb2bf65b230 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Bus Gates Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + This additional argument passed to that clock is the offset of + the bit controlling this particular gate in the register. + + compatible: + const: allwinner,sun8i-h3-bus-gates-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-indices: + minItems: 1 + maxItems: 64 + + clock-output-names: + minItems: 1 + maxItems: 64 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-indices + - clock-names + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-gates-clk"; + reg = <0x01c20060 0x14>; + clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; + clock-names = "ahb1", "ahb2", "apb1", "apb2"; + clock-indices = <5>, <6>, <8>, + <9>, <10>, <13>, + <14>, <17>, <18>, + <19>, <20>, + <21>, <23>, + <24>, <25>, + <26>, <27>, + <28>, <29>, + <30>, <31>, <32>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <52>, <53>, + <54>, <64>, + <65>, <69>, <72>, + <76>, <77>, <78>, + <96>, <97>, <98>, + <112>, <113>, + <114>, <115>, + <116>, <128>, <135>; + clock-output-names = "bus_ce", "bus_dma", "bus_mmc0", + "bus_mmc1", "bus_mmc2", "bus_nand", + "bus_sdram", "bus_gmac", "bus_ts", + "bus_hstimer", "bus_spi0", + "bus_spi1", "bus_otg", + "bus_otg_ehci0", "bus_ehci1", + "bus_ehci2", "bus_ehci3", + "bus_otg_ohci0", "bus_ohci1", + "bus_ohci2", "bus_ohci3", "bus_ve", + "bus_lcd0", "bus_lcd1", "bus_deint", + "bus_csi", "bus_tve", "bus_hdmi", + "bus_de", "bus_gpu", "bus_msgbox", + "bus_spinlock", "bus_codec", + "bus_spdif", "bus_pio", "bus_ths", + "bus_i2s0", "bus_i2s1", "bus_i2s2", + "bus_i2c0", "bus_i2c1", "bus_i2c2", + "bus_uart0", "bus_uart1", + "bus_uart2", "bus_uart3", + "bus_scr", "bus_ephy", "bus_dbg"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml new file mode 100644 index 000000000000..d178da90aaec --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 AHB Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-ahb-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@6000060 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-ahb-clk"; + reg = <0x06000060 0x4>; + clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "ahb0"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml new file mode 100644 index 000000000000..0351c79bd221 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 APB0 Bus Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun9i-a80-apb0-clk + - allwinner,sun9i-a80-apb1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@6000070 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-apb0-clk"; + reg = <0x06000070 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "apb0"; + }; + + - | + clk@6000074 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-apb1-clk"; + reg = <0x06000074 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "apb1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml new file mode 100644 index 000000000000..24d5b2f1a314 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-cpus-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 CPUS Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-cpus-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@8001410 { + compatible = "allwinner,sun9i-a80-cpus-clk"; + reg = <0x08001410 0x4>; + #clock-cells = <0>; + clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>; + clock-output-names = "cpus"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-gt-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-gt-clk.yaml new file mode 100644 index 000000000000..07f38def7dc3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-gt-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-gt-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 GT Bus Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-gt-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@0600005c { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-gt-clk"; + reg = <0x0600005c 0x4>; + clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "gt"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml new file mode 100644 index 000000000000..20dc115fa211 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 MMC Configuration Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +description: > + There is one clock/reset output per mmc controller. The number of + outputs is determined by the size of the address block, which is + related to the overall mmc block. + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-mmc-config-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + clock-output-names: + maxItems: 4 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c13000 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-config-clk"; + reg = <0x01c13000 0x10>; + clocks = <&ahb0_gates 8>; + resets = <&ahb0_resets 8>; + clock-output-names = "mmc0_config", "mmc1_config", + "mmc2_config", "mmc3_config"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml new file mode 100644 index 000000000000..b76bab6a30e9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 Peripheral PLL Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-pll4-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@600000c { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-pll4-clk"; + reg = <0x0600000c 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml new file mode 100644 index 000000000000..15218d10e78e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-mod-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 USB Module Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-usb-mod-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 6 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@a08000 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-mod-clk"; + reg = <0x00a08000 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb0_ahb", "usb_ohci0", + "usb1_ahb", "usb_ohci1", + "usb2_ahb", "usb_ohci2"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml new file mode 100644 index 000000000000..2569041684e6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-phy-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 USB PHY Clock Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-usb-phy-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 6 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@a08004 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-phy-clk"; + reg = <0x00a08004 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb_phy0", "usb_hsic1_480M", + "usb_phy1", "usb_hsic2_480M", + "usb_phy2", "usb_hsic_12M"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml new file mode 100644 index 000000000000..4b8669f870ec --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic DDR Clock Controller Device Tree Bindings + +maintainers: + - Martin Blumenstingl <martin.blumenstingl@googlemail.com> + +properties: + compatible: + enum: + - amlogic,meson8-ddr-clkc + - amlogic,meson8b-ddr-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt index 4d94091c1d2d..cc51e4746b3b 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -11,6 +11,11 @@ Required Properties: - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs - #clock-cells: should be 1. - #reset-cells: should be 1. +- clocks: list of clock phandles, one for each entry in clock-names +- clock-names: should contain the following: + * "xtal": the 24MHz system oscillator + * "ddr_pll": the DDR PLL clock + * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) Parent node should have the following properties : - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml new file mode 100644 index 000000000000..c8350030b374 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding + +maintainers: + - Wen He <wen.he_1@nxp.com> + +description: | + NXP LS1028A has a clock domain PXLCLK0 used for the Display output + interface in the display core, as implemented in TSMC CLN28HPM PLL. + which generate and offers pixel clocks to Display. + +properties: + compatible: + const: fsl,ls1028a-plldig + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + fsl,vco-hz: + description: Optional for VCO frequency of the PLL in Hertz. + The VCO frequency of this PLL cannot be changed during runtime + only at startup. Therefore, the output frequencies are very + limited and might not even closely match the requested frequency. + To work around this restriction the user may specify its own + desired VCO frequency for the PLL. + minimum: 650000000 + maximum: 1300000000 + default: 1188000000 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +examples: + # Display PIXEL Clock node: + - | + dpclk: clock-display@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml new file mode 100644 index 000000000000..8fb2060ac47f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/fsl,sai-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale SAI bitclock-as-a-clock binding + +maintainers: + - Michael Walle <michael@walle.cc> + +description: | + It is possible to use the BCLK pin of a SAI module as a generic clock + output. Some SoC are very constrained in their pin multiplexer + configuration. Eg. pins can only be changed groups. For example, on the + LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI, + the second pins are wasted. Using this binding it is possible to use the + clock of the second SAI as a MCLK clock for an audio codec, for example. + + This is a composite of a gated clock and a divider clock. + +properties: + compatible: + const: fsl,vf610-sai-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mclk: clock-mclk@f130080 { + compatible = "fsl,vf610-sai-clock"; + reg = <0x0 0xf130080 0x0 0x80>; + #clock-cells = <0>; + clocks = <&parentclk>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml new file mode 100644 index 000000000000..80278882cf57 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/imx8mp-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Plus Clock Control Module Binding + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: + NXP i.MX8M Plus clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: fsl,imx8mp-ccm + + reg: + maxItems: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + + clock-names: + items: + - const: osc_32k + - const: osc_24m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h + for the full list of i.MX8M Plus clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + # Clock Control Module node: + - | + clk: clock-controller@30380000 { + compatible = "fsl,imx8mp-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, + <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", + "clk_ext2", "clk_ext3", "clk_ext4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt deleted file mode 100644 index d639e18d0b85..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt +++ /dev/null @@ -1,19 +0,0 @@ -Qualcomm Technologies, Inc. Display Clock Controller Binding ------------------------------------------------------------- - -Required properties : - -- compatible : shall contain "qcom,sdm845-dispcc" -- reg : shall contain base register location and length. -- #clock-cells : from common clock binding, shall contain 1. -- #reset-cells : from common reset binding, shall contain 1. -- #power-domain-cells : from generic power domain binding, shall contain 1. - -Example: - dispcc: clock-controller@af00000 { - compatible = "qcom,sdm845-dispcc"; - reg = <0xaf00000 0x100000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml new file mode 100644 index 000000000000..9c58e02a1de1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller Binding + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains. + +properties: + compatible: + enum: + - qcom,sc7180-dispcc + - qcom,sdm845-dispcc + + clocks: + minItems: 1 + maxItems: 2 + items: + - description: Board XO source + - description: GPLL0 source from GCC + + clock-names: + items: + - const: xo + - const: gpll0 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + # Example of DISPCC with clock node properties for SDM845: + - | + clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0xaf00000 0x10000>; + clocks = <&rpmhcc 0>, <&gcc 24>; + clock-names = "xo", "gpll0"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index e73a56fb60ca..cac1150c9292 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -19,8 +19,9 @@ properties: enum: - qcom,gcc-apq8064 - qcom,gcc-apq8084 - - qcom,gcc-ipq8064 - qcom,gcc-ipq4019 + - qcom,gcc-ipq6018 + - qcom,gcc-ipq8064 - qcom,gcc-ipq8074 - qcom,gcc-msm8660 - qcom,gcc-msm8916 @@ -40,20 +41,50 @@ properties: - qcom,gcc-sm8150 clocks: - minItems: 1 - maxItems: 3 - items: - - description: Board XO source - - description: Board active XO source - - description: Sleep clock source + oneOf: + #qcom,gcc-sm8150 + #qcom,gcc-sc7180 + - items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + #qcom,gcc-msm8996 + - items: + - description: XO source + - description: Second XO source + - description: Sleep clock source + #qcom,gcc-msm8998 + - items: + - description: Board XO source + - description: Sleep clock source + - description: USB 3.0 phy pipe clock + - description: UFS phy rx symbol clock for pipe 0 + - description: UFS phy rx symbol clock for pipe 1 + - description: UFS phy tx symbol clock + - description: PCIE phy pipe clock clock-names: - minItems: 1 - maxItems: 3 - items: - - const: bi_tcxo - - const: bi_tcxo_ao - - const: sleep_clk + oneOf: + #qcom,gcc-sm8150 + #qcom,gcc-sc7180 + - items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + #qcom,gcc-msm8996 + - items: + - const: cxo + - const: cxo2 + - const: sleep_clk + #qcom,gcc-msm8998 + - items: + - const: xo + - const: sleep_clk + - const: usb3_pipe + - const: ufs_rx_symbol0 + - const: ufs_rx_symbol1 + - const: ufs_tx_symbol0 + - const: pcie0_pipe '#clock-cells': const: 1 @@ -118,6 +149,7 @@ else: compatible: contains: enum: + - qcom,gcc-msm8998 - qcom,gcc-sm8150 - qcom,gcc-sc7180 then: @@ -179,10 +211,35 @@ examples: clock-controller@100000 { compatible = "qcom,gcc-sc7180"; reg = <0x100000 0x1f0000>; - clocks = <&rpmhcc 0>, <&rpmhcc 1>; - clock-names = "bi_tcxo", "bi_tcxo_ao"; + clocks = <&rpmhcc 0>, <&rpmhcc 1>, <0>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + # Example of MSM8998 GCC: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@100000 { + compatible = "qcom,gcc-msm8998"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + reg = <0x00100000 0xb0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep_clk", + "usb3_pipe", + "ufs_rx_symbol0", + "ufs_rx_symbol1", + "ufs_tx_symbol0", + "pcie0_pipe"; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt deleted file mode 100644 index 269afe8a757e..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ /dev/null @@ -1,24 +0,0 @@ -Qualcomm Graphics Clock & Reset Controller Binding --------------------------------------------------- - -Required properties : -- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc" -- reg : shall contain base register location and length -- #clock-cells : from common clock binding, shall contain 1 -- #reset-cells : from common reset binding, shall contain 1 -- #power-domain-cells : from generic power domain binding, shall contain 1 -- clocks : shall contain the XO clock - shall contain the gpll0 out main clock (msm8998) -- clock-names : shall be "xo" - shall be "gpll0" (msm8998) - -Example: - gpucc: clock-controller@5090000 { - compatible = "qcom,sdm845-gpucc"; - reg = <0x5090000 0x9000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml new file mode 100644 index 000000000000..622845aa643f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm grpahics clock control module which supports the clocks, resets and + power domains. + +properties: + compatible: + enum: + - qcom,msm8998-gpucc + - qcom,sc7180-gpucc + - qcom,sdm845-gpucc + + clocks: + minItems: 1 + maxItems: 3 + items: + - description: Board XO source + - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src) + - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src) + + clock-names: + minItems: 1 + maxItems: 3 + items: + - const: xo + - const: gpll0_main + - const: gpll0_div + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + # Example of GPUCC with clock node properties for SDM845: + - | + clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0x5090000 0x9000>; + clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>; + clock-names = "xo", "gpll0_main", "gpll0_div"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt deleted file mode 100644 index 8b0f7841af8d..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt +++ /dev/null @@ -1,28 +0,0 @@ -Qualcomm Multimedia Clock & Reset Controller Binding ----------------------------------------------------- - -Required properties : -- compatible : shall contain only one of the following: - - "qcom,mmcc-apq8064" - "qcom,mmcc-apq8084" - "qcom,mmcc-msm8660" - "qcom,mmcc-msm8960" - "qcom,mmcc-msm8974" - "qcom,mmcc-msm8996" - -- reg : shall contain base register location and length -- #clock-cells : shall contain 1 -- #reset-cells : shall contain 1 - -Optional properties : -- #power-domain-cells : shall contain 1 - -Example: - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml new file mode 100644 index 000000000000..91101c915904 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,mmcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Multimedia Clock & Reset Controller Binding + +maintainers: + - Jeffrey Hugo <jhugo@codeaurora.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm multimedia clock control module which supports the clocks, resets and + power domains. + +properties: + compatible : + enum: + - qcom,mmcc-apq8064 + - qcom,mmcc-apq8084 + - qcom,mmcc-msm8660 + - qcom,mmcc-msm8960 + - qcom,mmcc-msm8974 + - qcom,mmcc-msm8996 + - qcom,mmcc-msm8998 + + clocks: + items: + - description: Board XO source + - description: Board sleep source + - description: Global PLL 0 clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: DisplayPort phy PLL vco clock + - description: DisplayPort phy PLL link clock + + clock-names: + items: + - const: xo + - const: sleep + - const: gpll0 + - const: dsi0dsi + - const: dsi0byte + - const: dsi1dsi + - const: dsi1byte + - const: hdmipll + - const: dpvco + - const: dplink + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +if: + properties: + compatible: + contains: + const: qcom,mmcc-msm8998 + +then: + required: + - clocks + - clock-names + +examples: + # Example for MMCC for MSM8960: + - | + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt deleted file mode 100644 index 8a8622c65c5a..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt +++ /dev/null @@ -1,18 +0,0 @@ -Qualcomm Video Clock & Reset Controller Binding ------------------------------------------------ - -Required properties : -- compatible : shall contain "qcom,sdm845-videocc" -- reg : shall contain base register location and length -- #clock-cells : from common clock binding, shall contain 1. -- #power-domain-cells : from generic power domain binding, shall contain 1. -- #reset-cells : from common reset binding, shall contain 1. - -Example: - videocc: clock-controller@ab00000 { - compatible = "qcom,sdm845-videocc"; - reg = <0xab00000 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml new file mode 100644 index 000000000000..43cfc893a8d1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller Binding + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm video clock control module which supports the clocks, resets and + power domains. + +properties: + compatible: + enum: + - qcom,sc7180-videocc + - qcom,sdm845-videocc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xo + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + # Example of VIDEOCC with clock node properties for SDM845: + - | + clock-controller@ab00000 { + compatible = "qcom,sdm845-videocc"; + reg = <0xab00000 0x10000>; + clocks = <&rpmhcc 0>; + clock-names = "xo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index c7674d0267a3..f4d153f24a0f 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -19,7 +19,7 @@ Required Properties: - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) - - "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N) + - "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N) - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E) - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt deleted file mode 100644 index fb9495ea582c..000000000000 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt +++ /dev/null @@ -1,60 +0,0 @@ -STMicroelectronics STM32 Peripheral Reset Clock Controller -========================================================== - -The RCC IP is both a reset and a clock controller. - -RCC makes also power management (resume/supend and wakeup interrupt). - -Please also refer to reset.txt for common reset controller binding usage. - -Please also refer to clock-bindings.txt for common clock controller -binding usage. - - -Required properties: -- compatible: "st,stm32mp1-rcc", "syscon" -- reg: should be register base and length as documented in the datasheet -- #clock-cells: 1, device nodes should specify the clock in their - "clocks" property, containing a phandle to the clock device node, - an index specifying the clock to use. -- #reset-cells: Shall be 1 -- interrupts: Should contain a general interrupt line and a interrupt line - to the wake-up of processor (CSTOP). - -Example: - rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>, - <GIC_SPI 145 IRQ_TYPE_NONE>; - }; - -Specifying clocks -================= - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/stm32mp1-clks.h header and can be used in device -tree sources. - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index specifying -which channel to use. -The index is the bit number within the RCC registers bank, starting from RCC -base address. -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. - -For example on STM32MP1, for LTDC reset: - ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset - = 0x180 / 4 * 32 + 0 = 3072 - -The list of valid indices for STM32MP1 is available in: -include/dt-bindings/reset-controller/stm32mp1-resets.h - -This file implements defines like: -#define LTDC_R 3072 diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml new file mode 100644 index 000000000000..b8f91e444d2f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/st,stm32mp1-rcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Reset Clock Controller Binding + +maintainers: + - Gabriel Fernandez <gabriel.fernandez@st.com> + +description: | + The RCC IP is both a reset and a clock controller. + RCC makes also power management (resume/supend and wakeup interrupt). + Please also refer to reset.txt for common reset controller binding usage. + + This binding uses common clock bindings + Documentation/devicetree/bindings/clock/clock-bindings.txt + + Specifying clocks + ================= + + All available clocks are defined as preprocessor macros in + dt-bindings/clock/stm32mp1-clks.h header and can be used in device + tree sources. + + Specifying softreset control of devices + ======================================= + + Device nodes should specify the reset channel required in their "resets" + property, containing a phandle to the reset device node and an index specifying + which channel to use. + The index is the bit number within the RCC registers bank, starting from RCC + base address. + It is calculated as: index = register_offset / 4 * 32 + bit_offset. + Where bit_offset is the bit offset within the register. + + For example on STM32MP1, for LTDC reset: + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset + = 0x180 / 4 * 32 + 0 = 3072 + + The list of valid indices for STM32MP1 is available in: + include/dt-bindings/reset-controller/stm32mp1-resets.h + + This file implements defines like: + #define LTDC_R 3072 + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + items: + - const: st,stm32mp1-rcc + - const: syscon + + reg: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + rcc: rcc@50000000 { + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt deleted file mode 100644 index 1a042e20b115..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ /dev/null @@ -1,225 +0,0 @@ -Device Tree Clock bindings for arch-sunxi - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator - "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 - "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 - "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 - "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10 - "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 - "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock - "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock - "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 - "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80 - "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock - "allwinner,sun4i-a10-axi-clk" - for the AXI clock - "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 - "allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs - "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates - "allwinner,sun4i-a10-ahb-clk" - for the AHB clock - "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 - "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 - "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 - "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 - "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s - "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 - "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 - "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80 - "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 - "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 - "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 - "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 - "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 - "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80 - "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80 - "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock - "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 - "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 - "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80 - "allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T - "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 - "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 - "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s - "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 - "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 - "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 - "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3 - "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 - "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock - "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 - "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 - "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 - "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s - "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 - "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 - "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 - "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 - "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 - "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 - "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T - "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3 - "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 - "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10 - "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 - "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13 - "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 - "allwinner,sun4i-a10-mmc-clk" - for the MMC clock - "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 - "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80 - "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks - "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80 - "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 - "allwinner,sun7i-a20-out-clk" - for the external output clocks - "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 - "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10 - "allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10 - "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 - "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 - "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 - "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 - "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 - "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 - "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 - "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock - "allwinner,sun6i-a31-display-clk" - for the display clocks - -Required properties for all clocks: -- reg : shall be the control register address for the clock. -- clocks : shall be the input parent clock(s) phandle for the clock. For - multiplexed clocks, the list order must match the hardware - programming order. -- #clock-cells : from common clock binding; shall be set to 0 except for - the following compatibles where it shall be set to 1: - "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", - "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk", - "allwinner,*-usb-clk", "allwinner,*-mmc-clk", - "allwinner,*-mmc-config-clk" -- clock-output-names : shall be the corresponding names of the outputs. - If the clock module only has one output, the name shall be the - module name. - -And "allwinner,*-usb-clk" clocks also require: -- reset-cells : shall be set to 1 - -The "allwinner,sun4i-a10-ve-clk" clock also requires: -- reset-cells : shall be set to 0 - -The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: -- #reset-cells : shall be set to 1 -- resets : shall be the reset control phandle for the mmc block. - -For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate -dummy clocks at 25 MHz and 125 MHz, respectively. See example. - -Clock consumers should specify the desired clocks they use with a -"clocks" phandle cell. Consumers that are using a gated clock should -provide an additional ID in their clock property. This ID is the -offset of the bit controlling this particular gate in the register. -For the other clocks with "#clock-cells" = 1, the additional ID shall -refer to the index of the output. - -For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output -is the normal PLL6 output, or "pll6". The second output is rate doubled -PLL6, or "pll6x2". - -The "allwinner,*-mmc-clk" clocks have three different outputs: the -main clock, with the ID 0, and the output and sample clocks, with the -IDs 1 and 2, respectively. - -The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output -per mmc controller. The number of outputs is determined by the size of -the address block, which is related to the overall mmc block. - -For example: - -osc24M: clk@1c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clocks = <&osc24M_fixed>; - clock-output-names = "osc24M"; -}; - -pll1: clk@1c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; -}; - -pll5: clk@1c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; -}; - -pll6: clk@1c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; -}; - -cpu: cpu@1c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>; - clock-output-names = "cpu"; -}; - -mmc0_clk: clk@1c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; -}; - -mii_phy_tx_clk: clk@2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; -}; - -gmac_int_tx_clk: clk@3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; -}; - -gmac_clk: clk@1c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - /* - * The first clock must be fixed at 25MHz; - * the second clock must be fixed at 125MHz - */ - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac"; -}; - -mmc_config_clk: clk@1c13000 { - compatible = "allwinner,sun9i-a80-mmc-config-clk"; - reg = <0x01c13000 0x10>; - clocks = <&ahb0_gates 8>; - clock-names = "ahb"; - resets = <&ahb0_resets 8>; - reset-names = "ahb"; - #clock-cells = <1>; - #reset-cells = <1>; - clock-output-names = "mmc0_config", "mmc1_config", - "mmc2_config", "mmc3_config"; -}; diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt index 48ee6991f2cc..18af6b9409e3 100644 --- a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt +++ b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt @@ -16,18 +16,23 @@ For more information, please see the Linux clock framework binding at Documentation/devicetree/bindings/clock/clock-bindings.txt. Required properties : -- compatible : shall be "ti,clkctrl" +- compatible : shall be "ti,clkctrl" or a clock domain specific name: + "ti,clkctrl-l4-cfg" + "ti,clkctrl-l4-per" + "ti,clkctrl-l4-secure" + "ti,clkctrl-l4-wkup" - #clock-cells : shall contain 2 with the first entry being the instance offset from the clock domain base and the second being the clock index +- reg : clock registers Example: Clock controller node on omap 4430: &cm2 { l4per: cm@1400 { cm_l4per@0 { - cm_l4per_clkctrl: clk@20 { - compatible = "ti,clkctrl"; + cm_l4per_clkctrl: clock@20 { + compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; reg = <0x20 0x1b0>; #clock-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt b/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt index 10f7047755f3..21c002d28b9b 100644 --- a/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt +++ b/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt @@ -43,7 +43,7 @@ Configuration of ATL instances: - aws : Audio word select signal selection }; -For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include +For valid word select signals, see the dt-bindings/clock/ti-dra7-atl.h include file. Examples: @@ -83,7 +83,7 @@ atl: atl@4843c000 { clock-names = "fck"; }; -#include <dt-bindings/clk/ti-dra7-atl.h> +#include <dt-bindings/clock/ti-dra7-atl.h> &atl { diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml new file mode 100644 index 000000000000..f1150cad34a4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal clock controller + +maintainers: + - Michal Simek <michal.simek@xilinx.com> + - Jolly Shah <jolly.shah@xilinx.com> + - Rajan Vaja <rajan.vaja@xilinx.com> + +description: | + The clock controller is a hardware block of Xilinx versal clock tree. It + reads required input clock frequencies from the devicetree and acts as clock + provider for all clock consumers of PS clocks. + +select: false + +properties: + compatible: + const: xlnx,versal-clk + + "#clock-cells": + const: 1 + + clocks: + description: List of clock specifiers which are external input + clocks to the given clock controller. + items: + - description: reference clock + - description: alternate reference clock + - description: alternate reference clock for programmable logic + + clock-names: + items: + - const: ref + - const: alt_ref + - const: pl_alt_ref + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + versal_clk: clock-controller { + #clock-cells = <1>; + compatible = "xlnx,versal-clk"; + clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>; + clock-names = "ref", "alt_ref", "pl_alt_ref"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt index d357987181ee..88578ac1a8a7 100644 --- a/Documentation/devicetree/bindings/connector/usb-connector.txt +++ b/Documentation/devicetree/bindings/connector/usb-connector.txt @@ -1,8 +1,8 @@ USB Connector ============= -USB connector node represents physical USB connector. It should be -a child of USB interface controller. +A USB connector node represents a physical USB connector. It should be +a child of a USB interface controller. Required properties: - compatible: describes type of the connector, must be one of: diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml index 80b3e7350a73..33c7842917f6 100644 --- a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 Security System Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml new file mode 100644 index 000000000000..86057d541065 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Display Engine Backend Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + The display engine backend exposes layers and sprites to the system. + +properties: + compatible: + enum: + - allwinner,sun4i-a10-display-backend + - allwinner,sun5i-a13-display-backend + - allwinner,sun6i-a31-display-backend + - allwinner,sun7i-a20-display-backend + - allwinner,sun8i-a23-display-backend + - allwinner,sun8i-a33-display-backend + - allwinner,sun9i-a80-display-backend + + reg: + minItems: 1 + maxItems: 2 + items: + - description: Display Backend registers + - description: SAT registers + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: be + - const: sat + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 4 + items: + - description: The backend interface clock + - description: The backend module clock + - description: The backend DRAM clock + - description: The SAT clock + + clock-names: + minItems: 3 + maxItems: 4 + items: + - const: ahb + - const: mod + - const: ram + - const: sat + + resets: + minItems: 1 + maxItems: 2 + items: + - description: The Backend reset line + - description: The SAT reset line + + reset-names: + minItems: 1 + maxItems: 2 + items: + - const: be + - const: sat + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnects: + maxItems: 1 + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnect-names: + const: dma-mem + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +if: + properties: + compatible: + contains: + const: allwinner,sun8i-a33-display-backend + +then: + properties: + reg: + minItems: 2 + + reg-names: + minItems: 2 + + clocks: + minItems: 4 + + clock-names: + minItems: 4 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + + required: + - reg-names + - reset-names + +else: + properties: + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + +examples: + - | + /* + * This comes from the clock/sun4i-a10-ccu.h and + * reset/sun4i-a10-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_AHB_DE_BE0 42 + #define CLK_DRAM_DE_BE0 140 + #define CLK_DE_BE0 144 + #define RST_DE_BE0 5 + + display-backend@1e60000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + /* + * This comes from the clock/sun8i-a23-a33-ccu.h and + * reset/sun8i-a23-a33-ccu.h headers, but we can't include them + * since it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_BUS_DE_BE 40 + #define CLK_BUS_SAT 46 + #define CLK_DRAM_DE_BE 84 + #define CLK_DE_BE 85 + #define RST_BUS_DE_BE 21 + #define RST_BUS_SAT 27 + + display-backend@1e60000 { + compatible = "allwinner,sun8i-a33-display-backend"; + reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; + reg-names = "be", "sat"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; + clock-names = "ahb", "mod", + "ram", "sat"; + resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; + reset-names = "be", "sat"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&fe0_out_be0>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml new file mode 100644 index 000000000000..944ff2f1cf93 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Display Engine Pipeline Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + The display engine pipeline (and its entry point, since it can be + either directly the backend or the frontend) is represented as an + extra node. + + The Allwinner A10 Display pipeline is composed of several components + that are going to be documented below: + + For all connections between components up to the TCONs in the + display pipeline, when there are multiple components of the same + type at the same depth, the local endpoint ID must be the same as + the remote component's index. For example, if the remote endpoint is + Frontend 1, then the local endpoint ID must be 1. + + Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0 + [1] -- -- [1] [1] -- -- [1] + \ / \ / + X X + / \ / \ + [0] -- -- [0] [0] -- -- [0] + Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1 + + For a two pipeline system such as the one depicted above, the lines + represent the connections between the components, while the numbers + within the square brackets corresponds to the ID of the local endpoint. + + The same rule also applies to DE 2.0 mixer-TCON connections: + + Mixer 0 [0] ----------- [0] TCON 0 + [1] ---- ---- [1] + \ / + X + / \ + [0] ---- ---- [0] + Mixer 1 [1] ----------- [1] TCON 1 + +properties: + compatible: + enum: + - allwinner,sun4i-a10-display-engine + - allwinner,sun5i-a10s-display-engine + - allwinner,sun5i-a13-display-engine + - allwinner,sun6i-a31-display-engine + - allwinner,sun6i-a31s-display-engine + - allwinner,sun7i-a20-display-engine + - allwinner,sun8i-a23-display-engine + - allwinner,sun8i-a33-display-engine + - allwinner,sun8i-a83t-display-engine + - allwinner,sun8i-h3-display-engine + - allwinner,sun8i-r40-display-engine + - allwinner,sun8i-v3s-display-engine + - allwinner,sun9i-a80-display-engine + - allwinner,sun50i-a64-display-engine + - allwinner,sun50i-h6-display-engine + + allwinner,pipelines: + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle-array + - minItems: 1 + maxItems: 2 + description: | + Available display engine frontends (DE 1.0) or mixers (DE + 2.0/3.0) available. + +required: + - compatible + - allwinner,pipelines + +additionalProperties: false + +if: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-display-engine + - allwinner,sun6i-a31-display-engine + - allwinner,sun6i-a31s-display-engine + - allwinner,sun7i-a20-display-engine + - allwinner,sun8i-a83t-display-engine + - allwinner,sun8i-r40-display-engine + - allwinner,sun9i-a80-display-engine + - allwinner,sun50i-a64-display-engine + +then: + properties: + allwinner,pipelines: + minItems: 2 + +else: + properties: + allwinner,pipelines: + maxItems: 1 + +examples: + - | + de: display-engine { + compatible = "allwinner,sun4i-a10-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml new file mode 100644 index 000000000000..3eb1c2bbf4e7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Display Engine Frontend Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + The display engine frontend does formats conversion, scaling, + deinterlacing and color space conversion. + +properties: + compatible: + enum: + - allwinner,sun4i-a10-display-frontend + - allwinner,sun5i-a13-display-frontend + - allwinner,sun6i-a31-display-frontend + - allwinner,sun7i-a20-display-frontend + - allwinner,sun8i-a23-display-frontend + - allwinner,sun8i-a33-display-frontend + - allwinner,sun9i-a80-display-frontend + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The frontend interface clock + - description: The frontend module clock + - description: The frontend DRAM clock + + clock-names: + items: + - const: ahb + - const: mod + - const: ram + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnects: + maxItems: 1 + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnect-names: + const: dma-mem + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun4i-a10-ccu.h> + #include <dt-bindings/reset/sun4i-a10-ccu.h> + + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml new file mode 100644 index 000000000000..5d4915aed1e2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml @@ -0,0 +1,183 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 HDMI Controller Device Tree Bindings + +description: | + The HDMI Encoder supports the HDMI video and audio outputs, and does + CEC. It is one end of the pipeline. + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + compatible: + oneOf: + - const: allwinner,sun4i-a10-hdmi + - const: allwinner,sun5i-a10s-hdmi + - const: allwinner,sun6i-a31-hdmi + - items: + - const: allwinner,sun7i-a20-hdmi + - const: allwinner,sun5i-a10s-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + oneOf: + - items: + - description: The HDMI interface clock + - description: The HDMI module clock + - description: The first video PLL + - description: The second video PLL + + - items: + - description: The HDMI interface clock + - description: The HDMI module clock + - description: The HDMI DDC clock + - description: The first video PLL + - description: The second video PLL + + clock-names: + oneOf: + - items: + - const: ahb + - const: mod + - const: pll-0 + - const: pll-1 + + - items: + - const: ahb + - const: mod + - const: ddc + - const: pll-0 + - const: pll-1 + + resets: + maxItems: 1 + + dmas: + items: + - description: DDC Transmission DMA Channel + - description: DDC Reception DMA Channel + - description: Audio Transmission DMA Channel + + dma-names: + items: + - const: ddc-tx + - const: ddc-rx + - const: audio-tx + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. Usually an HDMI + connector. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + +if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-hdmi + +then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + + required: + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun4i-a10-ccu.h> + #include <dt-bindings/dma/sun4i-a10.h> + #include <dt-bindings/reset/sun4i-a10-ccu.h> + + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun4i-a10-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml new file mode 100644 index 000000000000..86ad617d2327 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -0,0 +1,676 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Timings Controller (TCON) Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + The TCON acts as a timing controller for RGB, LVDS and TV + interfaces. + +properties: + "#clock-cells": + const: 0 + + compatible: + oneOf: + - const: allwinner,sun4i-a10-tcon + - const: allwinner,sun5i-a13-tcon + - const: allwinner,sun6i-a31-tcon + - const: allwinner,sun6i-a31s-tcon + - const: allwinner,sun7i-a20-tcon + - const: allwinner,sun8i-a23-tcon + - const: allwinner,sun8i-a33-tcon + - const: allwinner,sun8i-a83t-tcon-lcd + - const: allwinner,sun8i-a83t-tcon-tv + - const: allwinner,sun8i-r40-tcon-tv + - const: allwinner,sun8i-v3s-tcon + - const: allwinner,sun9i-a80-tcon-lcd + - const: allwinner,sun9i-a80-tcon-tv + + - items: + - enum: + - allwinner,sun50i-a64-tcon-lcd + - const: allwinner,sun8i-a83t-tcon-lcd + + - items: + - enum: + - allwinner,sun8i-h3-tcon-tv + - allwinner,sun50i-a64-tcon-tv + - allwinner,sun50i-h6-tcon-tv + - const: allwinner,sun8i-a83t-tcon-tv + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + clock-output-names: + allOf: + - $ref: /schemas/types.yaml#/definitions/string-array + - maxItems: 1 + description: + Name of the LCD pixel clock created. + + dmas: + maxItems: 1 + + resets: + anyOf: + - items: + - description: TCON Reset Line + + - items: + - description: TCON Reset Line + - description: TCON LVDS Reset Line + + - items: + - description: TCON Reset Line + - description: TCON eDP Reset Line + + - items: + - description: TCON Reset Line + - description: TCON eDP Reset Line + - description: TCON LVDS Reset Line + + reset-names: + oneOf: + - const: lcd + + - items: + - const: lcd + - const: lvds + + - items: + - const: lcd + - const: edp + + - items: + - const: lcd + - const: edp + - const: lvds + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + patternProperties: + "^endpoint(@[0-9])$": + type: object + + properties: + allwinner,tcon-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + TCON can have 1 or 2 channels, usually with the + first channel being used for the panels interfaces + (RGB, LVDS, etc.), and the second being used for the + outputs that require another controller (TV Encoder, + HDMI, etc.). + + If that property is present, specifies the TCON + channel the endpoint is associated to. If that + property is not present, the endpoint number will be + used as the channel number. + + unevaluatedProperties: true + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-tcon + - allwinner,sun5i-a13-tcon + - allwinner,sun7i-a20-tcon + + then: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: ahb + - const: tcon-ch0 + - const: tcon-ch1 + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun6i-a31-tcon + - allwinner,sun6i-a31s-tcon + + then: + properties: + clocks: + minItems: 4 + + clock-names: + items: + - const: ahb + - const: tcon-ch0 + - const: tcon-ch1 + - const: lvds-alt + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a23-tcon + - allwinner,sun8i-a33-tcon + + then: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: ahb + - const: tcon-ch0 + - const: lvds-alt + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-tcon-lcd + - allwinner,sun8i-v3s-tcon + - allwinner,sun9i-a80-tcon-lcd + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: ahb + - const: tcon-ch0 + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-tcon-tv + - allwinner,sun8i-r40-tcon-tv + - allwinner,sun9i-a80-tcon-tv + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: ahb + - const: tcon-ch1 + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun5i-a13-tcon + - allwinner,sun6i-a31-tcon + - allwinner,sun6i-a31s-tcon + - allwinner,sun7i-a20-tcon + - allwinner,sun8i-a23-tcon + - allwinner,sun8i-a33-tcon + - allwinner,sun8i-v3s-tcon + - allwinner,sun9i-a80-tcon-lcd + - allwinner,sun4i-a10-tcon + - allwinner,sun8i-a83t-tcon-lcd + + then: + required: + - "#clock-cells" + - clock-output-names + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun6i-a31-tcon + - allwinner,sun6i-a31s-tcon + - allwinner,sun8i-a23-tcon + - allwinner,sun8i-a33-tcon + - allwinner,sun8i-a83t-tcon-lcd + + then: + properties: + resets: + minItems: 2 + + reset-names: + items: + - const: lcd + - const: lvds + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun9i-a80-tcon-lcd + + then: + properties: + resets: + minItems: 3 + + reset-names: + items: + - const: lcd + - const: edp + - const: lvds + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun9i-a80-tcon-tv + + then: + properties: + resets: + minItems: 2 + + reset-names: + items: + - const: lcd + - const: edp + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-tcon + - allwinner,sun5i-a13-tcon + - allwinner,sun6i-a31-tcon + - allwinner,sun6i-a31s-tcon + - allwinner,sun7i-a20-tcon + - allwinner,sun8i-a23-tcon + - allwinner,sun8i-a33-tcon + + then: + required: + - dmas + +examples: + - | + #include <dt-bindings/dma/sun4i-a10.h> + + /* + * This comes from the clock/sun4i-a10-ccu.h and + * reset/sun4i-a10-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_AHB_LCD0 56 + #define CLK_TCON0_CH0 149 + #define CLK_TCON0_CH1 155 + #define RST_TCON0 11 + + lcd-controller@1c0c000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&ccu RST_TCON0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + #undef CLK_AHB_LCD0 + #undef CLK_TCON0_CH0 + #undef CLK_TCON0_CH1 + #undef RST_TCON0 + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + /* + * This comes from the clock/sun6i-a31-ccu.h and + * reset/sun6i-a31-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_PLL_MIPI 15 + #define CLK_AHB1_LCD0 47 + #define CLK_LCD0_CH0 127 + #define CLK_LCD0_CH1 129 + #define RST_AHB1_LCD0 27 + #define RST_AHB1_LVDS 41 + + lcd-controller@1c0c000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma 11>; + resets = <&ccu RST_AHB1_LCD0>, <&ccu RST_AHB1_LVDS>; + reset-names = "lcd", "lvds"; + clocks = <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_LCD0_CH0>, + <&ccu CLK_LCD0_CH1>, + <&ccu CLK_PLL_MIPI>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1", + "lvds-alt"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_out_tcon0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + #undef CLK_PLL_MIPI + #undef CLK_AHB1_LCD0 + #undef CLK_LCD0_CH0 + #undef CLK_LCD0_CH1 + #undef RST_AHB1_LCD0 + #undef RST_AHB1_LVDS + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + /* + * This comes from the clock/sun9i-a80-ccu.h and + * reset/sun9i-a80-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_BUS_LCD0 102 + #define CLK_LCD0 58 + #define RST_BUS_LCD0 22 + #define RST_BUS_EDP 24 + #define RST_BUS_LVDS 25 + + lcd-controller@3c00000 { + compatible = "allwinner,sun9i-a80-tcon-lcd"; + reg = <0x03c00000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; + clock-names = "ahb", "tcon-ch0"; + resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "edp", "lvds"; + clock-output-names = "tcon0-pixel-clock"; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + #undef CLK_BUS_TCON0 + #undef CLK_TCON0 + #undef RST_BUS_TCON0 + #undef RST_BUS_EDP + #undef RST_BUS_LVDS + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + /* + * This comes from the clock/sun8i-a83t-ccu.h and + * reset/sun8i-a83t-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_BUS_TCON0 36 + #define CLK_TCON0 85 + #define RST_BUS_TCON0 22 + #define RST_BUS_LVDS 31 + + lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-a83t-tcon-lcd"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + #clock-cells = <0>; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + #undef CLK_BUS_TCON0 + #undef CLK_TCON0 + #undef RST_BUS_TCON0 + #undef RST_BUS_LVDS + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + /* + * This comes from the clock/sun8i-r40-ccu.h and + * reset/sun8i-r40-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + + #define CLK_BUS_TCON_TV0 73 + #define RST_BUS_TCON_TV0 49 + + tcon_tv0: lcd-controller@1c73000 { + compatible = "allwinner,sun8i-r40-tcon-tv"; + reg = <0x01c73000 0x1000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV0>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + #undef CLK_BUS_TCON_TV0 + #undef RST_BUS_TCON_TV0 + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml new file mode 100644 index 000000000000..5d5d39665119 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tv-encoder.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 TV Encoder Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + compatible: + const: allwinner,sun4i-a10-tv-encoder + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + port: + type: object + description: + A port node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoint, usually coming from the + associated TCON. + +required: + - compatible + - reg + - clocks + - resets + - port + +additionalProperties: false + +examples: + - | + tve0: tv-encoder@1c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ahb_gates 34>; + resets = <&tcon_ch0_clk 0>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_tve0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml new file mode 100644 index 000000000000..0c1ce55940e1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 Dynamic Range Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + The DRC (Dynamic Range Controller) allows to dynamically adjust + pixel brightness/contrast based on histogram measurements for LCD + content adaptive backlight control. + +properties: + compatible: + enum: + - allwinner,sun6i-a31-drc + - allwinner,sun6i-a31s-drc + - allwinner,sun8i-a23-drc + - allwinner,sun8i-a33-drc + - allwinner,sun9i-a80-drc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The DRC interface clock + - description: The DRC module clock + - description: The DRC DRAM clock + + clock-names: + items: + - const: ahb + - const: mod + - const: ram + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + #include <dt-bindings/clock/sun6i-a31-ccu.h> + #include <dt-bindings/reset/sun6i-a31-ccu.h> + + drc0: drc@1e70000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e70000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_DRAM_DRC0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + reg = <0>; + + drc0_in_be0: endpoint { + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + + drc0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_drc0>; + }; + }; + }; + }; + + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml index dafc0980c4fa..9e90c2b00960 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml @@ -8,14 +8,16 @@ title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#address-cells": true "#size-cells": true compatible: - const: allwinner,sun6i-a31-mipi-dsi + enum: + - allwinner,sun6i-a31-mipi-dsi + - allwinner,sun50i-a64-mipi-dsi reg: maxItems: 1 @@ -24,6 +26,8 @@ properties: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 items: - description: Bus Clock - description: Module Clock @@ -63,13 +67,38 @@ required: - reg - interrupts - clocks - - clock-names - phys - phy-names - resets - vcc-dsi-supply - port +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-mipi-dsi + + then: + properties: + clocks: + minItems: 2 + + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-a64-mipi-dsi + + then: + properties: + clocks: + minItems: 1 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml new file mode 100644 index 000000000000..1dee641e3ea1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-de2-mixer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner Display Engine 2.0 Mixer Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + compatible: + enum: + - allwinner,sun8i-a83t-de2-mixer-0 + - allwinner,sun8i-a83t-de2-mixer-1 + - allwinner,sun8i-h3-de2-mixer-0 + - allwinner,sun8i-r40-de2-mixer-0 + - allwinner,sun8i-r40-de2-mixer-1 + - allwinner,sun8i-v3s-de2-mixer + - allwinner,sun50i-a64-de2-mixer-0 + - allwinner,sun50i-a64-de2-mixer-1 + - allwinner,sun50i-h6-de3-mixer-0 + + reg: + maxItems: 1 + + clocks: + items: + - description: The mixer interface clock + - description: The mixer module clock + + clock-names: + items: + - const: bus + - const: mod + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun8i-de2.h> + #include <dt-bindings/reset/sun8i-de2.h> + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-a83t-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + + mixer0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_mixer0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml new file mode 100644 index 000000000000..4d6795690ac3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml @@ -0,0 +1,273 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller + IP with Allwinner\'s own PHY IP. It supports audio and video outputs + and CEC. + + These DT bindings follow the Synopsys DWC HDMI TX bindings defined + in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with + the following device-specific properties. + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 0 + + compatible: + oneOf: + - const: allwinner,sun8i-a83t-dw-hdmi + - const: allwinner,sun50i-h6-dw-hdmi + + - items: + - enum: + - allwinner,sun8i-h3-dw-hdmi + - allwinner,sun8i-r40-dw-hdmi + - allwinner,sun50i-a64-dw-hdmi + - const: allwinner,sun8i-a83t-dw-hdmi + + reg: + maxItems: 1 + + reg-io-width: + const: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 6 + items: + - description: Bus Clock + - description: Register Clock + - description: TMDS Clock + - description: HDMI CEC Clock + - description: HDCP Clock + - description: HDCP Bus Clock + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: iahb + - const: isfr + - const: tmds + - const: cec + - const: hdcp + - const: hdcp-bus + + resets: + minItems: 1 + maxItems: 2 + items: + - description: HDMI Controller Reset + - description: HDCP Reset + + reset-names: + minItems: 1 + maxItems: 2 + items: + - const: ctrl + - const: hdcp + + phys: + maxItems: 1 + description: + Phandle to the DWC HDMI PHY. + + phy-names: + const: phy + + hvcc-supply: + description: + The VCC power supply of the controller + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. Usually the associated + TCON. + + port@1: + type: object + description: | + Output endpoints of the controller. Usually an HDMI + connector. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - reg-io-width + - interrupts + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-h6-dw-hdmi + +then: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + /* + * This comes from the clock/sun8i-a83t-ccu.h and + * reset/sun8i-a83t-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + #define CLK_BUS_HDMI 39 + #define CLK_HDMI 93 + #define CLK_HDMI_SLOW 94 + #define RST_BUS_HDMI1 26 + + hdmi@1ee0000 { + compatible = "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "phy"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + /* Cleanup after ourselves */ + #undef CLK_BUS_HDMI + #undef CLK_HDMI + #undef CLK_HDMI_SLOW + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + /* + * This comes from the clock/sun50i-h6-ccu.h and + * reset/sun50i-h6-ccu.h headers, but we can't include them since + * it would trigger a bunch of warnings for redefinitions of + * symbols with the other example. + */ + #define CLK_BUS_HDMI 126 + #define CLK_BUS_HDCP 137 + #define CLK_HDMI 123 + #define CLK_HDMI_SLOW 124 + #define CLK_HDMI_CEC 125 + #define CLK_HDCP 136 + #define RST_BUS_HDMI_SUB 57 + #define RST_BUS_HDCP 62 + + hdmi@6000000 { + compatible = "allwinner,sun50i-h6-dw-hdmi"; + reg = <0x06000000 0x10000>; + reg-io-width = <1>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, + <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; + clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", + "hdcp-bus"; + resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; + reset-names = "ctrl", "hdcp"; + phys = <&hdmi_phy>; + phy-names = "phy"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&tcon_top_hdmi_out_hdmi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml new file mode 100644 index 000000000000..501cec16168c --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A83t HDMI PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - allwinner,sun8i-a83t-hdmi-phy + - allwinner,sun8i-h3-hdmi-phy + - allwinner,sun8i-r40-hdmi-phy + - allwinner,sun50i-a64-hdmi-phy + - allwinner,sun50i-h6-hdmi-phy + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Bus Clock + - description: Module Clock + - description: Parent of the PHY clock + - description: Second possible parent of the PHY clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: bus + - const: mod + - const: pll-0 + - const: pll-1 + + resets: + maxItems: 1 + + reset-names: + const: phy + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-r40-hdmi-phy + +then: + properties: + clocks: + minItems: 4 + + clock-names: + minItems: 4 + +else: + if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-h3-hdmi-phy + - allwinner,sun50i-a64-hdmi-phy + + then: + properties: + clocks: + minItems: 3 + + clock-names: + minItems: 3 + + else: + properties: + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun8i-a83t-ccu.h> + #include <dt-bindings/reset/sun8i-a83t-ccu.h> + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-a83t-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml new file mode 100644 index 000000000000..b98ca609824b --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml @@ -0,0 +1,382 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner R40 TCON TOP Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + TCON TOPs main purpose is to configure whole display pipeline. It + determines relationships between mixers and TCONs, selects source + TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV + encoder clock source and contains additional TV TCON and DSI gates. + + It allows display pipeline to be configured in very different ways: + + / LCD0/LVDS0 + / [0] TCON-LCD0 + | \ MIPI DSI + mixer0 | + \ / [1] TCON-LCD1 - LCD1/LVDS1 + TCON-TOP + / \ [2] TCON-TV0 [0] - TVE0/RGB + mixer1 | \ + | TCON-TOP - HDMI + | / + \ [3] TCON-TV1 [1] - TVE1/RGB + + Note that both TCON TOP references same physical unit. Both mixers + can be connected to any TCON. Not all TCON TOP variants support all + features. + +properties: + "#clock-cells": + const: 1 + + compatible: + enum: + - allwinner,sun8i-r40-tcon-top + - allwinner,sun50i-h6-tcon-top + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 6 + items: + - description: The TCON TOP interface clock + - description: The TCON TOP TV0 clock + - description: The TCON TOP TVE0 clock + - description: The TCON TOP TV1 clock + - description: The TCON TOP TVE1 clock + - description: The TCON TOP MIPI DSI clock + + clock-names: + minItems: 2 + maxItems: 6 + items: + - const: bus + - const: tcon-tv0 + - const: tve0 + - const: tcon-tv1 + - const: tve1 + - const: dsi + + clock-output-names: + minItems: 1 + maxItems: 3 + description: > + The first item is the name of the clock created for the TV0 + channel, the second item is the name of the TCON TV1 channel + clock and the third one is the name of the DSI channel clock. + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + All ports should have only one endpoint connected to + remote endpoint. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoint for Mixer 0 mux. + + port@1: + type: object + description: | + Output endpoint for Mixer 0 mux + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: true + + patternProperties: + "^endpoint@[0-9]$": + type: object + + properties: + reg: + description: | + ID of the target TCON + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + + additionalProperties: false + + port@2: + type: object + description: | + Input endpoint for Mixer 1 mux. + + port@3: + type: object + description: | + Output endpoint for Mixer 1 mux + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: true + + patternProperties: + "^endpoint@[0-9]$": + type: object + + properties: + reg: + description: | + ID of the target TCON + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + + additionalProperties: false + + port@4: + type: object + description: | + Input endpoint for HDMI mux. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: true + + patternProperties: + "^endpoint@[0-9]$": + type: object + + properties: + reg: + description: | + ID of the target TCON + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + + additionalProperties: false + + port@5: + type: object + description: | + Output endpoint for HDMI mux + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + - port@4 + - port@5 + + additionalProperties: false + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - resets + - ports + +additionalProperties: false + +if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-tcon-top + +then: + properties: + clocks: + maxItems: 2 + + clock-output-names: + maxItems: 1 + +else: + properties: + clocks: + minItems: 6 + + clock-output-names: + minItems: 3 + + ports: + required: + - port@2 + - port@3 + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + #include <dt-bindings/clock/sun8i-r40-ccu.h> + #include <dt-bindings/reset/sun8i-r40-ccu.h> + + tcon_top: tcon-top@1c70000 { + compatible = "allwinner,sun8i-r40-tcon-top"; + reg = <0x01c70000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_TOP>, + <&ccu CLK_TCON_TV0>, + <&ccu CLK_TVE0>, + <&ccu CLK_TCON_TV1>, + <&ccu CLK_TVE1>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", + "tcon-tv0", + "tve0", + "tcon-tv1", + "tve1", + "dsi"; + clock-output-names = "tcon-top-tv0", + "tcon-top-tv1", + "tcon-top-dsi"; + resets = <&ccu RST_BUS_TCON_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + reg = <0>; + + tcon_top_mixer0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon_top>; + }; + }; + + tcon_top_mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon_top>; + }; + }; + + tcon_top_mixer1_out: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_tv0_out_tcon_top>; + }; + + tcon_top_hdmi_in_tcon_tv1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_tv1_out_tcon_top>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_tcon_top>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml b/Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml new file mode 100644 index 000000000000..96de41d32b3e --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 Detail Enhancement Unit Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC, + can sharpen the display content in both luma and chroma channels. + +properties: + compatible: + const: allwinner,sun9i-a80-deu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The DEU interface clock + - description: The DEU module clock + - description: The DEU DRAM clock + + clock-names: + items: + - const: ahb + - const: mod + - const: ram + + resets: + maxItems: 1 + + ports: + type: object + description: | + A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + Input endpoints of the controller. + + port@1: + type: object + description: | + Output endpoints of the controller. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + #include <dt-bindings/clock/sun9i-a80-de.h> + #include <dt-bindings/reset/sun9i-a80-de.h> + + deu0: deu@3300000 { + compatible = "allwinner,sun9i-a80-deu"; + reg = <0x03300000 0x40000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&de_clocks CLK_BUS_DEU0>, + <&de_clocks CLK_IEP_DEU0>, + <&de_clocks CLK_DRAM_DEU0>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DEU0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + deu0_in: port@0 { + reg = <0>; + + deu0_in_fe0: endpoint { + remote-endpoint = <&fe0_out_deu0>; + }; + }; + + deu0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deu0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_deu0>; + }; + + deu0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_deu0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml new file mode 100644 index 000000000000..8f373029f5d2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/lvds-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Transparent LVDS encoders and decoders + +maintainers: + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + +description: | + This binding supports transparent LVDS encoders and decoders that don't + require any configuration. + + LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple + incompatible data link layers have been used over time to transmit image data + to LVDS panels. This binding targets devices compatible with the following + specifications only. + + [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February + 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) + [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National + Semiconductor + [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video + Electronics Standards Association (VESA) + + Those devices have been marketed under the FPD-Link and FlatLink brand names + among others. + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer + - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer + - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter + - const: lvds-encoder # Generic LVDS encoder compatible fallback + - items: + - enum: + - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver + - const: lvds-decoder # Generic LVDS decoders compatible fallback + - enum: + - thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer + + ports: + type: object + description: | + This device has two video ports. Their connections are modeled using the + OF graph bindings specified in Documentation/devicetree/bindings/graph.txt + properties: + port@0: + type: object + description: | + For LVDS encoders, port 0 is the parallel input + For LVDS decoders, port 0 is the LVDS input + + port@1: + type: object + description: | + For LVDS encoders, port 1 is the LVDS output + For LVDS decoders, port 1 is the parallel output + + required: + - port@0 + - port@1 + + powerdown-gpios: + description: + The GPIO used to control the power down line of this device. + maxItems: 1 + +required: + - compatible + - ports + +examples: + - | + lvds-encoder { + compatible = "ti,ds90c185", "lvds-encoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_enc_in: endpoint { + remote-endpoint = <&display_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + + lvds_enc_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; + }; + + - | + lvds-decoder { + compatible = "ti,ds90cf384a", "lvds-decoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_dec_in: endpoint { + remote-endpoint = <&display_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + + lvds_dec_out: endpoint { + remote-endpoint = <&rgb_panel_in>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt deleted file mode 100644 index 60091db5dfa5..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt +++ /dev/null @@ -1,66 +0,0 @@ -Parallel to LVDS Encoder ------------------------- - -This binding supports the parallel to LVDS encoders that don't require any -configuration. - -LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple -incompatible data link layers have been used over time to transmit image data -to LVDS panels. This binding targets devices compatible with the following -specifications only. - -[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February -1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) -[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National -Semiconductor -[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video -Electronics Standards Association (VESA) - -Those devices have been marketed under the FPD-Link and FlatLink brand names -among others. - - -Required properties: - -- compatible: Must be "lvds-encoder" - - Any encoder compatible with this generic binding, but with additional - properties not listed here, must list a device specific compatible first - followed by this generic compatible. - -Required nodes: - -This device has two video ports. Their connections are modeled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for parallel input -- Video port 1 for LVDS output - - -Example -------- - -lvds-encoder { - compatible = "lvds-encoder"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_enc_in: endpoint { - remote-endpoint = <&display_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - - lvds_enc_out: endpoint { - remote-endpoint = <&lvds_panel_in>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt deleted file mode 100644 index fee3c88e1a17..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt +++ /dev/null @@ -1,50 +0,0 @@ -THine Electronics THC63LVDM83D LVDS serializer ----------------------------------------------- - -The THC63LVDM83D is an LVDS serializer designed to support pixel data -transmission between a host and a flat panel. - -Required properties: - -- compatible: Should be "thine,thc63lvdm83d" - -Optional properties: - -- powerdown-gpios: Power down control GPIO (the /PWDN pin, active low). - -Required nodes: - -The THC63LVDM83D has two video ports. Their connections are modeled using the -OFgraph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for CMOS/TTL input -- Video port 1 for LVDS output - - -Example -------- - - lvds_enc: encoder@0 { - compatible = "thine,thc63lvdm83d"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_enc_in: endpoint@0 { - remote-endpoint = <&rgb_out>; - }; - }; - - port@1 { - reg = <1>; - - lvds_enc_out: endpoint@0 { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt b/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt deleted file mode 100644 index e575f996959a..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt +++ /dev/null @@ -1,55 +0,0 @@ -Texas Instruments FPD-Link (LVDS) Serializer --------------------------------------------- - -The DS90C185 and DS90C187 are low-power serializers for portable -battery-powered applications that reduces the size of the RGB -interface between the host GPU and the display. - -Required properties: - -- compatible: Should be - "ti,ds90c185", "lvds-encoder" for the TI DS90C185 FPD-Link Serializer - "ti,ds90c187", "lvds-encoder" for the TI DS90C187 FPD-Link Serializer - -Optional properties: - -- powerdown-gpios: Power down control GPIO (the PDB pin, active-low) - -Required nodes: - -The devices have two video ports. Their connections are modeled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for parallel input -- Video port 1 for LVDS output - - -Example -------- - -lvds-encoder { - compatible = "ti,ds90c185", "lvds-encoder"; - - powerdown-gpios = <&gpio 17 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_enc_in: endpoint { - remote-endpoint = <&lcdc_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - - lvds_enc_out: endpoint { - remote-endpoint = <&lvds_panel_in>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/dsi-controller.yaml b/Documentation/devicetree/bindings/display/dsi-controller.yaml new file mode 100644 index 000000000000..fd986c36c737 --- /dev/null +++ b/Documentation/devicetree/bindings/display/dsi-controller.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/dsi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for DSI Display Panels + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: | + This document defines device tree properties common to DSI, Display + Serial Interface controllers and attached panels. It doesn't constitute + a device tree binding specification by itself but is meant to be referenced + by device tree bindings. + + When referenced from panel device tree bindings the properties defined in + this document are defined as follows. The panel device tree bindings are + responsible for defining whether each property is required or optional. + + Notice: this binding concerns DSI panels connected directly to a master + without any intermediate port graph to the panel. Each DSI master + can control one to four virtual channels to one panel. Each virtual + channel should have a node "panel" for their virtual channel with their + reg-property set to the virtual channel number, usually there is just + one virtual channel, number 0. + +properties: + $nodename: + pattern: "^dsi-controller(@.*)?$" + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^panel@[0-3]$": + description: Panels connected to the DSI link + type: object + + properties: + reg: + minimum: 0 + maximum: 3 + description: + The virtual channel number of a DSI peripheral. Must be in the range + from 0 to 3, as DSI uses a 2-bit addressing scheme. Some DSI + peripherals respond to more than a single virtual channel. In that + case the reg property can take multiple entries, one for each virtual + channel that the peripheral responds to. + + clock-master: + type: boolean + description: + Should be enabled if the host is being used in conjunction with + another DSI host to drive the same peripheral. Hardware supporting + such a configuration generally requires the data on both the busses + to be driven by the same clock. Only the DSI host instance + controlling this clock should contain this property. + + enforce-video-mode: + type: boolean + description: + The best option is usually to run a panel in command mode, as this + gives better control over the panel hardware. However for different + reasons like broken hardware, missing features or testing, it may be + useful to be able to force a command mode-capable panel into video + mode. + + required: + - reg + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + dsi-controller@a0351000 { + reg = <0xa0351000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "sony,acx424akp"; + reg = <0>; + vddi-supply = <&ab8500_ldo_aux1_reg>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/ingenic,lcd.txt b/Documentation/devicetree/bindings/display/ingenic,lcd.txt index 7b536c8c6dde..01e3261defb6 100644 --- a/Documentation/devicetree/bindings/display/ingenic,lcd.txt +++ b/Documentation/devicetree/bindings/display/ingenic,lcd.txt @@ -4,6 +4,7 @@ Required properties: - compatible: one of: * ingenic,jz4740-lcd * ingenic,jz4725b-lcd + * ingenic,jz4770-lcd - reg: LCD registers location and length - clocks: LCD pixclock and device clock specifiers. The device clock is only required on the JZ4740. diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index a61dd40f3792..551ae26f60da 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC. MDSS: Required properties: -- compatible: "qcom,sdm845-mdss" +- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" - reg: physical base address and length of contoller's registers. - reg-names: register region names. The following region is required: * "mdss" @@ -41,7 +41,7 @@ Optional properties: MDP: Required properties: -- compatible: "qcom,sdm845-dpu" +- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" - reg: physical base address and length of controller's registers. - reg-names : register region names. The following region is required: * "mdp" diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 2b8fd26c43b0..7edc298a15f2 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -23,13 +23,18 @@ Required properties: - iommus: optional phandle to an adreno iommu instance - operating-points-v2: optional phandle to the OPP operating points - interconnects: optional phandle to an interconnect provider. See - ../interconnect/interconnect.txt for details. + ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms + will have two paths; all others will have one path. +- interconnect-names: The names of the interconnect paths that correspond to the + interconnects property. Values must be gfx-mem and ocmem. - qcom,gmu: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. Applicable targets: - qcom,adreno-630.2 - zap-shader: For a5xx and a6xx devices this node contains a memory-region that points to reserved memory to store the zap shader that can be used to help bring the GPU out of secure mode. +- firmware-name: optional property of the 'zap-shader' node, listing the + relative path of the device specific zap firmware. Example 3xx/4xx/a5xx: @@ -76,11 +81,13 @@ Example a6xx (with GMU): operating-points-v2 = <&gpu_opp_table>; interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; + interconnect-names = "gfx-mem"; qcom,gmu = <&gmu>; zap-shader { memory-region = <&zap_shader_region>; + firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn" }; }; }; diff --git a/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml b/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml deleted file mode 100644 index c6e33e7f36d0..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml +++ /dev/null @@ -1,42 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/panel/ampire,am-480272h3tmqw-t01h.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel - -maintainers: - - Yannick Fertre <yannick.fertre@st.com> - - Thierry Reding <treding@nvidia.com> - -allOf: - - $ref: panel-common.yaml# - -properties: - compatible: - const: ampire,am-480272h3tmqw-t01h - - power-supply: true - enable-gpios: true - backlight: true - port: true - -required: - - compatible - -additionalProperties: false - -examples: - - | - panel_rgb: panel { - compatible = "ampire,am-480272h3tmqw-t01h"; - enable-gpios = <&gpioa 8 1>; - port { - panel_in_rgb: endpoint { - remote-endpoint = <&controller_out_rgb>; - }; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt b/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt deleted file mode 100644 index 83e2cae1cc1b..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt +++ /dev/null @@ -1,7 +0,0 @@ -Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "ampire,am800480r3tmqwa1h" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt b/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt deleted file mode 100644 index 3dab52f92c26..000000000000 --- a/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt +++ /dev/null @@ -1,12 +0,0 @@ -GiantPlus 3.0" (320x240 pixels) 24-bit TFT LCD panel - -Required properties: -- compatible: should be "giantplus,gpm940b0" -- power-supply: as specified in the base binding - -Optional properties: -- backlight: as specified in the base binding -- enable-gpios: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml b/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml new file mode 100644 index 000000000000..4ebcea7d0c63 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/leadtek,ltk500hd1829.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Leadtek LTK500HD1829 5.0in 720x1280 DSI panel + +maintainers: + - Heiko Stuebner <heiko.stuebner@theobroma-systems.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: leadtek,ltk500hd1829 + reg: true + backlight: true + reset-gpios: true + iovcc-supply: + description: regulator that supplies the iovcc voltage + vcc-supply: + description: regulator that supplies the vcc voltage + +required: + - compatible + - reg + - backlight + - iovcc-supply + - vcc-supply + +additionalProperties: false + +examples: + - | + dsi@ff450000 { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "leadtek,ltk500hd1829"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + vcc-supply = <&vcc_2v8>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/logicpd,type28.yaml b/Documentation/devicetree/bindings/display/panel/logicpd,type28.yaml new file mode 100644 index 000000000000..2834287b8d88 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/logicpd,type28.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/logicpd,type28.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Logic PD Type 28 4.3" WQVGA TFT LCD panel + +maintainers: + - Adam Ford <aford173@gmail.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: logicpd,type28 + + power-supply: true + enable-gpios: true + backlight: true + port: true + +required: + - compatible + +additionalProperties: false + +examples: + - | + lcd0: display { + compatible = "logicpd,type28"; + enable-gpios = <&gpio5 27 0>; + backlight = <&backlight>; + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml new file mode 100644 index 000000000000..8fe60ee2531c --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/panel-simple.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple panels with one power supply + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Sam Ravnborg <sam@ravnborg.org> + +description: | + This binding file is a collection of the simple (dumb) panels that + requires only a single power-supply. + There are optionally a backlight and an enable GPIO. + The panel may use an OF graph binding for the association to the display, + or it may be a direct child node of the display. + + If the panel is more advanced a dedicated binding file is required. + +allOf: + - $ref: panel-common.yaml# + +properties: + + compatible: + enum: + # compatible must be listed in alphabetical order, ordered by compatible. + # The description in the comment is mandatory for each compatible. + + # Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel + - ampire,am-480272h3tmqw-t01h + # Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel + - ampire,am800480r3tmqwa1h + # AUO B116XAK01 eDP TFT LCD panel + - auo,b116xa01 + # BOE NV140FHM-N49 14.0" FHD a-Si FT panel + - boe,nv140fhmn49 + # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel + - giantplus,gpm940b0 + # Satoz SAT050AT40H12R2 5.0" WVGA TFT LCD panel + - satoz,sat050at40h12r2 + # Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel + - sharp,ls020b1dd01d + + backlight: true + enable-gpios: true + port: true + power-supply: true + +additionalProperties: false + +required: + - compatible + - power-supply + +examples: + - | + panel_rgb: panel-rgb { + compatible = "ampire,am-480272h3tmqw-t01h"; + power-supply = <&vcc_lcd_reg>; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/panel/ronbo,rb070d30.yaml b/Documentation/devicetree/bindings/display/panel/ronbo,rb070d30.yaml index 0e7987f1cdb7..d67617f6f74a 100644 --- a/Documentation/devicetree/bindings/display/panel/ronbo,rb070d30.yaml +++ b/Documentation/devicetree/bindings/display/panel/ronbo,rb070d30.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Ronbo RB070D30 DSI Display Panel maintainers: - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt b/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt deleted file mode 100644 index e45edbc565a3..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt +++ /dev/null @@ -1,12 +0,0 @@ -Sharp 2.0" (240x160 pixels) 16-bit TFT LCD panel - -Required properties: -- compatible: should be "sharp,ls020b1dd01d" -- power-supply: as specified in the base binding - -Optional properties: -- backlight: as specified in the base binding -- enable-gpios: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml b/Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml new file mode 100644 index 000000000000..185dcc8fd1f9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sony,acx424akp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony ACX424AKP 4" 480x864 AMOLED panel + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sony,acx424akp + reg: true + reset-gpios: true + vddi-supply: + description: regulator that supplies the vddi voltage + enforce-video-mode: true + +required: + - compatible + - reg + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi-controller@a0351000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0351000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sony,acx424akp"; + reg = <0>; + vddi-supply = <&foo>; + reset-gpios = <&foo_gpio 0 GPIO_ACTIVE_LOW>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml b/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml new file mode 100644 index 000000000000..186e5e1c8fa3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/xinpeng,xpp055c272.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xinpeng XPP055C272 5.5in 720x1280 DSI panel + +maintainers: + - Heiko Stuebner <heiko.stuebner@theobroma-systems.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: xinpeng,xpp055c272 + reg: true + backlight: true + reset-gpios: true + iovcc-supply: + description: regulator that supplies the iovcc voltage + vci-supply: + description: regulator that supplies the vci voltage + +required: + - compatible + - reg + - backlight + - iovcc-supply + - vci-supply + +additionalProperties: false + +examples: + - | + dsi@ff450000 { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "xinpeng,xpp055c272"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + vci-supply = <&vcc3v3_lcd>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/renesas,cmm.yaml b/Documentation/devicetree/bindings/display/renesas,cmm.yaml new file mode 100644 index 000000000000..a57037b9e9ba --- /dev/null +++ b/Documentation/devicetree/bindings/display/renesas,cmm.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,cmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Color Management Module (CMM) + +maintainers: + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> + - Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> + - Jacopo Mondi <jacopo+renesas@jmondi.org> + +description: |+ + Renesas R-Car color management module connected to R-Car DU video channels. + It provides image enhancement functions such as 1-D look-up tables (LUT), + 3-D look-up tables (CLU), 1D-histogram generation (HGO), and color + space conversion (CSC). + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r8a7795-cmm + - renesas,r8a7796-cmm + - renesas,r8a77965-cmm + - renesas,r8a77990-cmm + - renesas,r8a77995-cmm + - const: renesas,rcar-gen3-cmm + - items: + - const: renesas,rcar-gen2-cmm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7796-cpg-mssr.h> + #include <dt-bindings/power/r8a7796-sysc.h> + + cmm0: cmm@fea40000 { + compatible = "renesas,r8a7796-cmm", + "renesas,rcar-gen3-cmm"; + reg = <0 0xfea40000 0 0x1000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 711>; + resets = <&cpg 711>; + }; diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt index 17cb2771364b..eb4ae41fe41f 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ b/Documentation/devicetree/bindings/display/renesas,du.txt @@ -41,10 +41,14 @@ Required Properties: supplied they must be named "dclkin.x" with "x" being the input clock numerical index. - - vsps: A list of phandle and channel index tuples to the VSPs that handle - the memory interfaces for the DU channels. The phandle identifies the VSP - instance that serves the DU channel, and the channel index identifies the - LIF instance in that VSP. + - renesas,cmms: A list of phandles to the CMM instances present in the SoC, + one for each available DU channel. The property shall not be specified for + SoCs that do not provide any CMM (such as V3M and V3H). + + - renesas,vsps: A list of phandle and channel index tuples to the VSPs that + handle the memory interfaces for the DU channels. The phandle identifies the + VSP instance that serves the DU channel, and the channel index identifies + the LIF instance in that VSP. Required nodes: @@ -92,7 +96,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; clock-names = "du.0", "du.1", "du.2", "du.3"; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; + renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; ports { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index ce4c1fc9116c..151be3bba06f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -4,13 +4,16 @@ Rockchip specific extensions to the Synopsys Designware MIPI DSI Required properties: - #address-cells: Should be <1>. - #size-cells: Should be <0>. -- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi". - "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi". +- compatible: one of + "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi" + "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi" + "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi" - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). - clocks, clock-names: Phandles to the controller's pll reference - clock(ref) and APB clock(pclk). For RK3399, a phy config clock - (phy_cfg) and a grf clock(grf) are required. As described in [1]. + clock(ref) when using an internal dphy and APB clock(pclk). + For RK3399, a phy config clock (phy_cfg) and a grf clock(grf) + are required. As described in [1]. - rockchip,grf: this soc should set GRF regs to mux vopl/vopb. - ports: contain a port node with endpoint definitions as defined in [2]. For vopb,set the reg = <0> and set the reg = <1> for vopl. @@ -18,6 +21,8 @@ Required properties: - video port 1 for either a panel or subsequent encoder Optional properties: +- phys: from general PHY binding: the phandle for the PHY device. +- phy-names: Should be "dphy" if phys references an external phy. - power-domains: a phandle to mipi dsi power domain node. - resets: list of phandle + reset specifier pairs, as described in [3]. - reset-names: string reset name, must be "apb". diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt index 7849ff039229..aaf8c44cf90f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt @@ -4,6 +4,7 @@ Rockchip RK3288 LVDS interface Required properties: - compatible: matching the soc type, one of - "rockchip,rk3288-lvds"; + - "rockchip,px30-lvds"; - reg: physical base address of the controller and length of memory mapped region. @@ -18,6 +19,9 @@ Required properties: - rockchip,grf: phandle to the general register files syscon - rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface +- phys: LVDS/DSI DPHY (px30 only) +- phy-names: name of the PHY, must be "dphy" (px30 only) + Optional properties: - pinctrl-names: must contain a "lcdc" entry. - pinctrl-0: pin control group to be used for this controller. diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt deleted file mode 100644 index 31ab72cba3d4..000000000000 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ /dev/null @@ -1,637 +0,0 @@ -Allwinner A10 Display Pipeline -============================== - -The Allwinner A10 Display pipeline is composed of several components -that are going to be documented below: - -For all connections between components up to the TCONs in the display -pipeline, when there are multiple components of the same type at the -same depth, the local endpoint ID must be the same as the remote -component's index. For example, if the remote endpoint is Frontend 1, -then the local endpoint ID must be 1. - - Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0 - [1] -- -- [1] [1] -- -- [1] - \ / \ / - X X - / \ / \ - [0] -- -- [0] [0] -- -- [0] - Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1 - -For a two pipeline system such as the one depicted above, the lines -represent the connections between the components, while the numbers -within the square brackets corresponds to the ID of the local endpoint. - -The same rule also applies to DE 2.0 mixer-TCON connections: - - Mixer 0 [0] ----------- [0] TCON 0 - [1] ---- ---- [1] - \ / - X - / \ - [0] ---- ---- [0] - Mixer 1 [1] ----------- [1] TCON 1 - -HDMI Encoder ------------- - -The HDMI Encoder supports the HDMI video and audio outputs, and does -CEC. It is one end of the pipeline. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-hdmi - * allwinner,sun5i-a10s-hdmi - * allwinner,sun6i-a31-hdmi - - reg: base address and size of memory-mapped region - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the HDMI encoder - * ahb: the HDMI interface clock - * mod: the HDMI module clock - * ddc: the HDMI ddc clock (A31 only) - * pll-0: the first video PLL - * pll-1: the second video PLL - - clock-names: the clock names mentioned above - - resets: phandle to the reset control for the HDMI encoder (A31 only) - - dmas: phandles to the DMA channels used by the HDMI encoder - * ddc-tx: The channel for DDC transmission - * ddc-rx: The channel for DDC reception - * audio-tx: The channel used for audio transmission - - dma-names: the channel names mentioned above - - - ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint. The second should be the - output, usually to an HDMI connector. - -DWC HDMI TX Encoder -------------------- - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with Allwinner's own PHY IP. It supports audio and video outputs and CEC. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - -Required properties: - - - compatible: value must be one of: - * "allwinner,sun8i-a83t-dw-hdmi" - * "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi" - * "allwinner,sun50i-h6-dw-hdmi" - - reg: base address and size of memory-mapped region - - reg-io-width: See dw_hdmi.txt. Shall be 1. - - interrupts: HDMI interrupt number - - clocks: phandles to the clocks feeding the HDMI encoder - * iahb: the HDMI bus clock - * isfr: the HDMI register clock - * tmds: TMDS clock - * cec: HDMI CEC clock (H6 only) - * hdcp: HDCP clock (H6 only) - * hdcp-bus: HDCP bus clock (H6 only) - - clock-names: the clock names mentioned above - - resets: - * ctrl: HDMI controller reset - * hdcp: HDCP reset (H6 only) - - reset-names: reset names mentioned above - - phys: phandle to the DWC HDMI PHY - - phy-names: must be "phy" - - - ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint. The second should be the - output, usually to an HDMI connector. - -Optional properties: - - hvcc-supply: the VCC power supply of the controller - -DWC HDMI PHY ------------- - -Required properties: - - compatible: value must be one of: - * allwinner,sun8i-a83t-hdmi-phy - * allwinner,sun8i-h3-hdmi-phy - * allwinner,sun8i-r40-hdmi-phy - * allwinner,sun50i-a64-hdmi-phy - * allwinner,sun50i-h6-hdmi-phy - - reg: base address and size of memory-mapped region - - clocks: phandles to the clocks feeding the HDMI PHY - * bus: the HDMI PHY interface clock - * mod: the HDMI PHY module clock - - clock-names: the clock names mentioned above - - resets: phandle to the reset controller driving the PHY - - reset-names: must be "phy" - -H3, A64 and R40 HDMI PHY require additional clocks: - - pll-0: parent of phy clock - - pll-1: second possible phy clock parent (A64/R40 only) - -TV Encoder ----------- - -The TV Encoder supports the composite and VGA output. It is one end of -the pipeline. - -Required properties: - - compatible: value should be "allwinner,sun4i-a10-tv-encoder". - - reg: base address and size of memory-mapped region - - clocks: the clocks driving the TV encoder - - resets: phandle to the reset controller driving the encoder - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint. - -TCON ----- - -The TCON acts as a timing controller for RGB, LVDS and TV interfaces. - -Required properties: - - compatible: value must be either: - * allwinner,sun4i-a10-tcon - * allwinner,sun5i-a13-tcon - * allwinner,sun6i-a31-tcon - * allwinner,sun6i-a31s-tcon - * allwinner,sun7i-a20-tcon - * allwinner,sun8i-a23-tcon - * allwinner,sun8i-a33-tcon - * allwinner,sun8i-a83t-tcon-lcd - * allwinner,sun8i-a83t-tcon-tv - * allwinner,sun8i-r40-tcon-tv - * allwinner,sun8i-v3s-tcon - * allwinner,sun9i-a80-tcon-lcd - * allwinner,sun9i-a80-tcon-tv - * "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd" - * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv" - * allwinner,sun50i-h6-tcon-tv, allwinner,sun8i-r40-tcon-tv - - reg: base address and size of memory-mapped region - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the TCON. - - 'ahb': the interface clocks - - 'tcon-ch0': The clock driving the TCON channel 0, if supported - - resets: phandles to the reset controllers driving the encoder - - "lcd": the reset line for the TCON - - "edp": the reset line for the eDP block (A80 only) - - - clock-names: the clock names mentioned above - - reset-names: the reset names mentioned above - - clock-output-names: Name of the pixel clock created, if TCON supports - channel 0. - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint, the second one the output - - The output may have multiple endpoints. TCON can have 1 or 2 channels, - usually with the first channel being used for the panels interfaces - (RGB, LVDS, etc.), and the second being used for the outputs that - require another controller (TV Encoder, HDMI, etc.). The endpoints - will take an extra property, allwinner,tcon-channel, to specify the - channel the endpoint is associated to. If that property is not - present, the endpoint number will be used as the channel number. - -For TCONs with channel 0, there is one more clock required: - - 'tcon-ch0': The clock driving the TCON channel 0 -For TCONs with channel 1, there is one more clock required: - - 'tcon-ch1': The clock driving the TCON channel 1 - -When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found -in A13, H3, H5 and V3s SoCs), you need one more reset line: - - 'lvds': The reset line driving the LVDS logic - -And on the A23, A31, A31s and A33, you need one more clock line: - - 'lvds-alt': An alternative clock source, separate from the TCON channel 0 - clock, that can be used to drive the LVDS clock - -TCON TOP --------- - -TCON TOPs main purpose is to configure whole display pipeline. It determines -relationships between mixers and TCONs, selects source TCON for HDMI, muxes -LCD and TV encoder GPIO output, selects TV encoder clock source and contains -additional TV TCON and DSI gates. - -It allows display pipeline to be configured in very different ways: - - / LCD0/LVDS0 - / [0] TCON-LCD0 - | \ MIPI DSI - mixer0 | - \ / [1] TCON-LCD1 - LCD1/LVDS1 - TCON-TOP - / \ [2] TCON-TV0 [0] - TVE0/RGB - mixer1 | \ - | TCON-TOP - HDMI - | / - \ [3] TCON-TV1 [1] - TVE1/RGB - -Note that both TCON TOP references same physical unit. Both mixers can be -connected to any TCON. Not all TCON TOP variants support all features. - -Required properties: - - compatible: value must be one of: - * allwinner,sun8i-r40-tcon-top - * allwinner,sun50i-h6-tcon-top - - reg: base address and size of the memory-mapped region. - - clocks: phandle to the clocks feeding the TCON TOP - * bus: TCON TOP interface clock - * tcon-tv0: TCON TV0 clock - * tve0: TVE0 clock (R40 only) - * tcon-tv1: TCON TV1 clock (R40 only) - * tve1: TVE0 clock (R40 only) - * dsi: MIPI DSI clock (R40 only) - - clock-names: clock name mentioned above - - resets: phandle to the reset line driving the TCON TOP - - #clock-cells : must contain 1 - - clock-output-names: Names of clocks created for TCON TV0 channel clock, - TCON TV1 channel clock (R40 only) and DSI channel clock (R40 only), in - that order. - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should - be defined: - * port 0 is input for mixer0 mux - * port 1 is output for mixer0 mux - * port 2 is input for mixer1 mux - * port 3 is output for mixer1 mux - * port 4 is input for HDMI mux - * port 5 is output for HDMI mux - All output endpoints for mixer muxes and input endpoints for HDMI mux should - have reg property with the id of the target TCON, as shown in above graph - (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one - endpoint connected to remote endpoint. - -DRC ---- - -The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs -(A31, A23, A33, A80), allows to dynamically adjust pixel -brightness/contrast based on histogram measurements for LCD content -adaptive backlight control. - - -Required properties: - - compatible: value must be one of: - * allwinner,sun6i-a31-drc - * allwinner,sun6i-a31s-drc - * allwinner,sun8i-a23-drc - * allwinner,sun8i-a33-drc - * allwinner,sun9i-a80-drc - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the DRC - * ahb: the DRC interface clock - * mod: the DRC module clock - * ram: the DRC DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset line driving the DRC - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the outputs - -Display Engine Backend ----------------------- - -The display engine backend exposes layers and sprites to the -system. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-display-backend - * allwinner,sun5i-a13-display-backend - * allwinner,sun6i-a31-display-backend - * allwinner,sun7i-a20-display-backend - * allwinner,sun8i-a23-display-backend - * allwinner,sun8i-a33-display-backend - * allwinner,sun9i-a80-display-backend - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the frontend and backend - * ahb: the backend interface clock - * mod: the backend module clock - * ram: the backend DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset controllers driving the backend - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the output - -On the A33, some additional properties are required: - - reg needs to have an additional region corresponding to the SAT - - reg-names need to be set, with "be" and "sat" - - clocks and clock-names need to have a phandle to the SAT bus - clocks, whose name will be "sat" - - resets and reset-names need to have a phandle to the SAT bus - resets, whose name will be "sat" - -DEU ---- - -The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC, -can sharpen the display content in both luma and chroma channels. - -Required properties: - - compatible: value must be one of: - * allwinner,sun9i-a80-deu - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the DEU - * ahb: the DEU interface clock - * mod: the DEU module clock - * ram: the DEU DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset line driving the DEU - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the outputs - -Display Engine Frontend ------------------------ - -The display engine frontend does formats conversion, scaling, -deinterlacing and color space conversion. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-display-frontend - * allwinner,sun5i-a13-display-frontend - * allwinner,sun6i-a31-display-frontend - * allwinner,sun7i-a20-display-frontend - * allwinner,sun8i-a23-display-frontend - * allwinner,sun8i-a33-display-frontend - * allwinner,sun9i-a80-display-frontend - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the frontend and backend - * ahb: the backend interface clock - * mod: the backend module clock - * ram: the backend DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset controllers driving the backend - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the outputs - -Display Engine 2.0 Mixer ------------------------- - -The DE2 mixer have many functionalities, currently only layer blending is -supported. - -Required properties: - - compatible: value must be one of: - * allwinner,sun8i-a83t-de2-mixer-0 - * allwinner,sun8i-a83t-de2-mixer-1 - * allwinner,sun8i-h3-de2-mixer-0 - * allwinner,sun8i-r40-de2-mixer-0 - * allwinner,sun8i-r40-de2-mixer-1 - * allwinner,sun8i-v3s-de2-mixer - * allwinner,sun50i-a64-de2-mixer-0 - * allwinner,sun50i-a64-de2-mixer-1 - * allwinner,sun50i-h6-de3-mixer-0 - - reg: base address and size of the memory-mapped region. - - clocks: phandles to the clocks feeding the mixer - * bus: the mixer interface clock - * mod: the mixer module clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset controllers driving the mixer - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the output - - -Display Engine Pipeline ------------------------ - -The display engine pipeline (and its entry point, since it can be -either directly the backend or the frontend) is represented as an -extra node. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-display-engine - * allwinner,sun5i-a10s-display-engine - * allwinner,sun5i-a13-display-engine - * allwinner,sun6i-a31-display-engine - * allwinner,sun6i-a31s-display-engine - * allwinner,sun7i-a20-display-engine - * allwinner,sun8i-a23-display-engine - * allwinner,sun8i-a33-display-engine - * allwinner,sun8i-a83t-display-engine - * allwinner,sun8i-h3-display-engine - * allwinner,sun8i-r40-display-engine - * allwinner,sun8i-v3s-display-engine - * allwinner,sun9i-a80-display-engine - * allwinner,sun50i-a64-display-engine - * allwinner,sun50i-h6-display-engine - - - allwinner,pipelines: list of phandle to the display engine - frontends (DE 1.0) or mixers (DE 2.0/3.0) available. - -Example: - -panel: panel { - compatible = "olimex,lcd-olinuxino-43-ts"; - #address-cells = <1>; - #size-cells = <0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint { - remote-endpoint = <&tcon0_out_panel>; - }; - }; -}; - -connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; -}; - -hdmi: hdmi@1c16000 { - compatible = "allwinner,sun5i-a10s-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = <58>; - clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_hdmi>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - }; -}; - -tve0: tv-encoder@1c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ahb_gates 34>; - resets = <&tcon_ch0_clk 0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tve0_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_tve0>; - }; - }; -}; - -tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&tcon_ch0_clk 1>; - reset-names = "lcd"; - clocks = <&ahb_gates 36>, - <&tcon_ch0_clk>, - <&tcon_ch1_clk>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - }; - }; - }; -}; - -fe0: display-frontend@1e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ahb_gates 46>, <&de_fe_clk>, - <&dram_gates 25>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_fe_clk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint { - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; -}; - -be0: display-backend@1e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = <47>; - clocks = <&ahb_gates 44>, <&de_be_clk>, - <&dram_gates 26>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_be_clk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; -}; - -display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; -}; diff --git a/Documentation/devicetree/bindings/display/tilcdc/tfp410.txt b/Documentation/devicetree/bindings/display/tilcdc/tfp410.txt deleted file mode 100644 index a58ae7756fc6..000000000000 --- a/Documentation/devicetree/bindings/display/tilcdc/tfp410.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device-Tree bindings for tilcdc DRM TFP410 output driver - -Required properties: - - compatible: value should be "ti,tilcdc,tfp410". - - i2c: the phandle for the i2c device to use for DDC - -Recommended properties: - - pinctrl-names, pinctrl-0: the pincontrol settings to configure - muxing properly for pins that connect to TFP410 device - - powerdn-gpio: the powerdown GPIO, pulled low to power down the - TFP410 device (for DPMS_OFF) - -Example: - - dvicape { - compatible = "ti,tilcdc,tfp410"; - i2c = <&i2c2>; - pinctrl-names = "default"; - pinctrl-0 = <&bone_dvi_cape_dvi_00A1_pins>; - powerdn-gpio = <&gpio2 31 0>; - }; diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml index 15abc0f9429f..83808199657b 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 DMA Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> allOf: - $ref: "dma-controller.yaml#" diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index 387d599522c7..9e53472be194 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -8,7 +8,7 @@ title: Allwinner A64 DMA Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> allOf: - $ref: "dma-controller.yaml#" diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml index 740b7f9b535b..c1676b96daac 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml @@ -8,7 +8,7 @@ title: Allwinner A31 DMA Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> allOf: - $ref: "dma-controller.yaml#" diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt index 29dd3ccb1235..e77b08ebcd06 100644 --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-edma.txt @@ -10,6 +10,7 @@ Required properties: - compatible : - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp + - "fsl,fsl,ls1028a-edma" for eDMA used similar to that on Vybrid vf610 SoC - reg : Specifies base physical address(s) and size of the eDMA registers. The 1st region is eDMA control register's address and size. The 2nd and the 3rd regions are programmable channel multiplexing diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index 9d8bbac27d8b..c9e97409e853 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt @@ -10,6 +10,9 @@ Required properties: "fsl,imx6q-sdma" "fsl,imx7d-sdma" "fsl,imx8mq-sdma" + "fsl,imx8mm-sdma" + "fsl,imx8mn-sdma" + "fsl,imx8mp-sdma" The -to variants should be preferred since they allow to determine the correct ROM script addresses needed for the driver to work without additional firmware. diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt index ec89782d9498..3459e77be294 100644 --- a/Documentation/devicetree/bindings/dma/jz4780-dma.txt +++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt @@ -1,4 +1,4 @@ -* Ingenic JZ4780 DMA Controller +* Ingenic XBurst DMA Controller Required properties: @@ -8,10 +8,12 @@ Required properties: * ingenic,jz4770-dma * ingenic,jz4780-dma * ingenic,x1000-dma + * ingenic,x1830-dma - reg: Should contain the DMA channel registers location and length, followed by the DMA controller registers location and length. - interrupts: Should contain the interrupt specifier of the DMA controller. -- clocks: Should contain a clock specifier for the JZ4780/X1000 PDMA clock. +- clocks: Should contain a clock specifier for the JZ4780/X1000/X1830 PDMA + clock. - #dma-cells: Must be <2>. Number of integer cells in the dmas property of DMA clients (see below). diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index 5551e929fd99..b7f81c63be8b 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -30,6 +30,7 @@ Required Properties: - "renesas,dmac-r8a7794" (R-Car E2) - "renesas,dmac-r8a7795" (R-Car H3) - "renesas,dmac-r8a7796" (R-Car M3-W) + - "renesas,dmac-r8a77961" (R-Car M3-W+) - "renesas,dmac-r8a77965" (R-Car M3-N) - "renesas,dmac-r8a77970" (R-Car V3M) - "renesas,dmac-r8a77980" (R-Car V3H) diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml new file mode 100644 index 000000000000..0c0ac11ad55f --- /dev/null +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DMA Controller bindings + +description: | + The STM32 DMA is a general-purpose direct memory access controller capable of + supporting 8 independent DMA channels. Each channel can have up to 8 requests. + DMA clients connected to the STM32 DMA controller must use the format + described in the dma.txt file, using a four-cell specifier for each + channel: a phandle to the DMA controller plus the following four integer cells: + 1. The channel id + 2. The request line number + 3. A 32bit mask specifying the DMA channel configuration which are device + dependent: + -bit 9: Peripheral Increment Address + 0x0: no address increment between transfers + 0x1: increment address between transfers + -bit 10: Memory Increment Address + 0x0: no address increment between transfers + 0x1: increment address between transfers + -bit 15: Peripheral Increment Offset Size + 0x0: offset size is linked to the peripheral bus width + 0x1: offset size is fixed to 4 (32-bit alignment) + -bit 16-17: Priority level + 0x0: low + 0x1: medium + 0x2: high + 0x3: very high + 4. A 32bit bitfield value specifying DMA features which are device dependent: + -bit 0-1: DMA FIFO threshold selection + 0x0: 1/4 full FIFO + 0x1: 1/2 full FIFO + 0x2: 3/4 full FIFO + 0x3: full FIFO + +maintainers: + - Amelie Delaunay <amelie.delaunay@st.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + "#dma-cells": + const: 4 + + compatible: + const: st,stm32-dma + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 8 + description: Should contain all of the per-channel DMA + interrupts in ascending order with respect to the + DMA channel index. + + resets: + maxItems: 1 + + st,mem2mem: + $ref: /schemas/types.yaml#/definitions/flag + description: if defined, it indicates that the controller + supports memory-to-memory transfer + +required: + - compatible + - reg + - clocks + - interrupts + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + dma-controller@40026400 { + compatible = "st,stm32-dma"; + reg = <0x40026400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&clk_hclk>; + #dma-cells = <4>; + st,mem2mem; + resets = <&rcc 150>; + dma-requests = <8>; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml new file mode 100644 index 000000000000..915bc4af9568 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/st,stm32-dmamux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DMA MUX (DMA request router) bindings + +maintainers: + - Amelie Delaunay <amelie.delaunay@st.com> + +allOf: + - $ref: "dma-router.yaml#" + +properties: + "#dma-cells": + const: 3 + + compatible: + const: st,stm32h7-dmamux + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - dma-masters + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + dma-router@40020800 { + compatible = "st,stm32h7-dmamux"; + reg = <0x40020800 0x3c>; + #dma-cells = <3>; + dma-requests = <128>; + dma-channels = <16>; + dma-masters = <&dma1 &dma2>; + clocks = <&timer_clk>; + }; + +... + diff --git a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml new file mode 100644 index 000000000000..c66543d0c267 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 MDMA Controller bindings + +description: | + The STM32 MDMA is a general-purpose direct memory access controller capable of + supporting 64 independent DMA channels with 256 HW requests. + DMA clients connected to the STM32 MDMA controller must use the format + described in the dma.txt file, using a five-cell specifier for each channel: + a phandle to the MDMA controller plus the following five integer cells: + 1. The request line number + 2. The priority level + 0x0: Low + 0x1: Medium + 0x2: High + 0x3: Very high + 3. A 32bit mask specifying the DMA channel configuration + -bit 0-1: Source increment mode + 0x0: Source address pointer is fixed + 0x2: Source address pointer is incremented after each data transfer + 0x3: Source address pointer is decremented after each data transfer + -bit 2-3: Destination increment mode + 0x0: Destination address pointer is fixed + 0x2: Destination address pointer is incremented after each data transfer + 0x3: Destination address pointer is decremented after each data transfer + -bit 8-9: Source increment offset size + 0x0: byte (8bit) + 0x1: half-word (16bit) + 0x2: word (32bit) + 0x3: double-word (64bit) + -bit 10-11: Destination increment offset size + 0x0: byte (8bit) + 0x1: half-word (16bit) + 0x2: word (32bit) + 0x3: double-word (64bit) + -bit 25-18: The number of bytes to be transferred in a single transfer + (min = 1 byte, max = 128 bytes) + -bit 29:28: Trigger Mode + 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) + 0x1: Each MDMA request triggers a block transfer (max 64K bytes) + 0x2: Each MDMA request triggers a repeated block transfer + 0x3: Each MDMA request triggers a linked list transfer + 4. A 32bit value specifying the register to be used to acknowledge the request + if no HW ack signal is used by the MDMA client + 5. A 32bit mask specifying the value to be written to acknowledge the request + if no HW ack signal is used by the MDMA client + +maintainers: + - Amelie Delaunay <amelie.delaunay@st.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + "#dma-cells": + const: 5 + + compatible: + const: st,stm32h7-mdma + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + st,ahb-addr-masks: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Array of u32 mask to list memory devices addressed via AHB bus. + +required: + - compatible + - reg + - clocks + - interrupts + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + dma-controller@52000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x52000000 0x1000>; + interrupts = <122>; + clocks = <&timer_clk>; + resets = <&rcc 992>; + #dma-cells = <5>; + dma-channels = <16>; + dma-requests = <32>; + st,ahb-addr-masks = <0x20000000>, <0x00000000>; + }; + +... + diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt deleted file mode 100644 index c5f519097204..000000000000 --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt +++ /dev/null @@ -1,83 +0,0 @@ -* STMicroelectronics STM32 DMA controller - -The STM32 DMA is a general-purpose direct memory access controller capable of -supporting 8 independent DMA channels. Each channel can have up to 8 requests. - -Required properties: -- compatible: Should be "st,stm32-dma" -- reg: Should contain DMA registers location and length. This should include - all of the per-channel registers. -- interrupts: Should contain all of the per-channel DMA interrupts in - ascending order with respect to the DMA channel index. -- clocks: Should contain the input clock of the DMA instance. -- #dma-cells : Must be <4>. See DMA client paragraph for more details. - -Optional properties: -- dma-requests : Number of DMA requests supported. -- resets: Reference to a reset controller asserting the DMA controller -- st,mem2mem: boolean; if defined, it indicates that the controller supports - memory-to-memory transfer - -Example: - - dma2: dma-controller@40026400 { - compatible = "st,stm32-dma"; - reg = <0x40026400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&clk_hclk>; - #dma-cells = <4>; - st,mem2mem; - resets = <&rcc 150>; - dma-requests = <8>; - }; - -* DMA client - -DMA clients connected to the STM32 DMA controller must use the format -described in the dma.txt file, using a four-cell specifier for each -channel: a phandle to the DMA controller plus the following four integer cells: - -1. The channel id -2. The request line number -3. A 32bit mask specifying the DMA channel configuration which are device - dependent: - -bit 9: Peripheral Increment Address - 0x0: no address increment between transfers - 0x1: increment address between transfers - -bit 10: Memory Increment Address - 0x0: no address increment between transfers - 0x1: increment address between transfers - -bit 15: Peripheral Increment Offset Size - 0x0: offset size is linked to the peripheral bus width - 0x1: offset size is fixed to 4 (32-bit alignment) - -bit 16-17: Priority level - 0x0: low - 0x1: medium - 0x2: high - 0x3: very high -4. A 32bit bitfield value specifying DMA features which are device dependent: - -bit 0-1: DMA FIFO threshold selection - 0x0: 1/4 full FIFO - 0x1: 1/2 full FIFO - 0x2: 3/4 full FIFO - 0x3: full FIFO - - -Example: - - usart1: serial@40011000 { - compatible = "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&clk_pclk2>; - dmas = <&dma2 2 4 0x10400 0x3>, - <&dma2 7 5 0x10200 0x3>; - dma-names = "rx", "tx"; - }; diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt deleted file mode 100644 index 1b893b235507..000000000000 --- a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt +++ /dev/null @@ -1,84 +0,0 @@ -STM32 DMA MUX (DMA request router) - -Required properties: -- compatible: "st,stm32h7-dmamux" -- reg: Memory map for accessing module -- #dma-cells: Should be set to <3>. - First parameter is request line number. - Second is DMA channel configuration - Third is Fifo threshold - For more details about the three cells, please see - stm32-dma.txt documentation binding file -- dma-masters: Phandle pointing to the DMA controllers. - Several controllers are allowed. Only "st,stm32-dma" DMA - compatible are supported. - -Optional properties: -- dma-channels : Number of DMA requests supported. -- dma-requests : Number of DMAMUX requests supported. -- resets: Reference to a reset controller asserting the DMA controller -- clocks: Input clock of the DMAMUX instance. - -Example: - -/* DMA controller 1 */ -dma1: dma-controller@40020000 { - compatible = "st,stm32-dma"; - reg = <0x40020000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&timer_clk>; - #dma-cells = <4>; - st,mem2mem; - resets = <&rcc 150>; - dma-channels = <8>; - dma-requests = <8>; -}; - -/* DMA controller 1 */ -dma2: dma@40020400 { - compatible = "st,stm32-dma"; - reg = <0x40020400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&timer_clk>; - #dma-cells = <4>; - st,mem2mem; - resets = <&rcc 150>; - dma-channels = <8>; - dma-requests = <8>; -}; - -/* DMA mux */ -dmamux1: dma-router@40020800 { - compatible = "st,stm32h7-dmamux"; - reg = <0x40020800 0x3c>; - #dma-cells = <3>; - dma-requests = <128>; - dma-channels = <16>; - dma-masters = <&dma1 &dma2>; - clocks = <&timer_clk>; -}; - -/* DMA client */ -usart1: serial@40011000 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&timer_clk>; - dmas = <&dmamux1 41 0x414 0>, - <&dmamux1 42 0x414 0>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt deleted file mode 100644 index d18772d6bc65..000000000000 --- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt +++ /dev/null @@ -1,94 +0,0 @@ -* STMicroelectronics STM32 MDMA controller - -The STM32 MDMA is a general-purpose direct memory access controller capable of -supporting 64 independent DMA channels with 256 HW requests. - -Required properties: -- compatible: Should be "st,stm32h7-mdma" -- reg: Should contain MDMA registers location and length. This should include - all of the per-channel registers. -- interrupts: Should contain the MDMA interrupt. -- clocks: Should contain the input clock of the DMA instance. -- resets: Reference to a reset controller asserting the DMA controller. -- #dma-cells : Must be <5>. See DMA client paragraph for more details. - -Optional properties: -- dma-channels: Number of DMA channels supported by the controller. -- dma-requests: Number of DMA request signals supported by the controller. -- st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via - AHB bus. - -Example: - - mdma1: dma@52000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x52000000 0x1000>; - interrupts = <122>; - clocks = <&timer_clk>; - resets = <&rcc 992>; - #dma-cells = <5>; - dma-channels = <16>; - dma-requests = <32>; - st,ahb-addr-masks = <0x20000000>, <0x00000000>; - }; - -* DMA client - -DMA clients connected to the STM32 MDMA controller must use the format -described in the dma.txt file, using a five-cell specifier for each channel: -a phandle to the MDMA controller plus the following five integer cells: - -1. The request line number -2. The priority level - 0x00: Low - 0x01: Medium - 0x10: High - 0x11: Very high -3. A 32bit mask specifying the DMA channel configuration - -bit 0-1: Source increment mode - 0x00: Source address pointer is fixed - 0x10: Source address pointer is incremented after each data transfer - 0x11: Source address pointer is decremented after each data transfer - -bit 2-3: Destination increment mode - 0x00: Destination address pointer is fixed - 0x10: Destination address pointer is incremented after each data - transfer - 0x11: Destination address pointer is decremented after each data - transfer - -bit 8-9: Source increment offset size - 0x00: byte (8bit) - 0x01: half-word (16bit) - 0x10: word (32bit) - 0x11: double-word (64bit) - -bit 10-11: Destination increment offset size - 0x00: byte (8bit) - 0x01: half-word (16bit) - 0x10: word (32bit) - 0x11: double-word (64bit) --bit 25-18: The number of bytes to be transferred in a single transfer - (min = 1 byte, max = 128 bytes) --bit 29:28: Trigger Mode - 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) - 0x01: Each MDMA request triggers a block transfer (max 64K bytes) - 0x10: Each MDMA request triggers a repeated block transfer - 0x11: Each MDMA request triggers a linked list transfer -4. A 32bit value specifying the register to be used to acknowledge the request - if no HW ack signal is used by the MDMA client -5. A 32bit mask specifying the value to be written to acknowledge the request - if no HW ack signal is used by the MDMA client - -Example: - - i2c4: i2c@5c002000 { - compatible = "st,stm32f7-i2c"; - reg = <0x5c002000 0x400>; - interrupts = <95>, - <96>; - clocks = <&timer_clk>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, - <&mdma1 37 0x0 0x40002 0x0 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; diff --git a/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml new file mode 100644 index 000000000000..8b5c346f23f6 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings + +maintainers: + - Peter Ujfalusi <peter.ujfalusi@ti.com> + +description: | + The UDMA-P is intended to perform similar (but significantly upgraded) + functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P + module supports the transmission and reception of various packet types. + The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA + data structure compliant packets to/from smaller data blocks that are natively + compatible with the specific requirements of each connected peripheral. + Multiple Tx and Rx channels are provided within the DMA which allow multiple + segmentation or reassembly operations to be ongoing. The DMA controller + maintains state information for each of the channels which allows packet + segmentation and reassembly operations to be time division multiplexed between + channels in order to share the underlying DMA hardware. An external DMA + scheduler is used to control the ordering and rate at which this multiplexing + occurs for Transmit operations. The ordering and rate of Receive operations + is indirectly controlled by the order in which blocks are pushed into the DMA + on the Rx PSI-L interface. + + The UDMA-P also supports acting as both a UTC and UDMA-C for its internal + channels. Channels in the UDMA-P can be configured to be either Packet-Based + or Third-Party channels on a channel by channel basis. + + All transfers within NAVSS is done between PSI-L source and destination + threads. + The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or + legacy, non PSI-L native peripherals. In the later case a special, small PDMA + is tasked to act as a bridge between the PSI-L fabric and the legacy + peripheral. + + PDMAs can be configured via UDMAP peer registers to match with the + configuration of the legacy peripheral. + +allOf: + - $ref: "../dma-controller.yaml#" + +properties: + "#dma-cells": + const: 1 + description: | + The cell is the PSI-L thread ID of the remote (to UDMAP) end. + Valid ranges for thread ID depends on the data movement direction: + for source thread IDs (rx): 0 - 0x7fff + for destination thread IDs (tx): 0x8000 - 0xffff + + Please refer to the device documentation for the PSI-L thread map and also + the PSI-L peripheral chapter for the correct thread ID. + + compatible: + enum: + - ti,am654-navss-main-udmap + - ti,am654-navss-mcu-udmap + - ti,j721e-navss-main-udmap + - ti,j721e-navss-mcu-udmap + + reg: + maxItems: 3 + + reg-names: + items: + - const: gcfg + - const: rchanrt + - const: tchanrt + + msi-parent: true + + ti,sci: + description: phandle to TI-SCI compatible System controller node + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + ti,sci-dev-id: + description: TI-SCI device id of UDMAP + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + + ti,ringacc: + description: phandle to the ring accelerator node + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + ti,sci-rm-range-tchan: + description: | + Array of UDMA tchan resource subtypes for resource allocation for this + host + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + # Should be enough + maxItems: 255 + + ti,sci-rm-range-rchan: + description: | + Array of UDMA rchan resource subtypes for resource allocation for this + host + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + # Should be enough + maxItems: 255 + + ti,sci-rm-range-rflow: + description: | + Array of UDMA rflow resource subtypes for resource allocation for this + host + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + # Should be enough + maxItems: 255 + +required: + - compatible + - "#dma-cells" + - reg + - reg-names + - msi-parent + - ti,sci + - ti,sci-dev-id + - ti,ringacc + - ti,sci-rm-range-tchan + - ti,sci-rm-range-rchan + - ti,sci-rm-range-rflow + +examples: + - |+ + cbass_main { + #address-cells = <2>; + #size-cells = <2>; + + cbass_main_navss: navss@30800000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + dma-ranges; + ranges; + + ti,sci-dev-id = <118>; + + main_udmap: dma-controller@31150000 { + compatible = "ti,am654-navss-main-udmap"; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + #dma-cells = <1>; + + ti,ringacc = <&ringacc>; + + msi-parent = <&inta_main_udmass>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <188>; + + ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ + <0x2>; /* TX_CHAN */ + ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */ + <0x5>; /* RX_CHAN */ + ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */ + }; + }; + + mcasp0: mcasp@02B00000 { + dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; + dma-names = "tx", "rx"; + }; + + crypto: crypto@4E00000 { + compatible = "ti,sa2ul-crypto"; + + dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; + dma-names = "tx", "rx1", "rx2"; + }; + }; diff --git a/Documentation/devicetree/bindings/gpio/qcom,wcd934x-gpio.yaml b/Documentation/devicetree/bindings/gpio/qcom,wcd934x-gpio.yaml new file mode 100644 index 000000000000..32a566ec3558 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/qcom,wcd934x-gpio.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/qcom,wcd934x-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: WCD9340/WCD9341 GPIO controller + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + Qualcomm Technologies Inc WCD9340/WCD9341 Audio Codec has integrated + gpio controller to control 5 gpios on the chip. + +properties: + compatible: + enum: + - qcom,wcd9340-gpio + - qcom,wcd9341-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + wcdgpio: gpio@42 { + compatible = "qcom,wcd9340-gpio"; + reg = <0x042 0x2>; + gpio-controller; + #gpio-cells = <2>; + }; + +... diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt index 41e5fed0f842..10dce84b1545 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt @@ -18,7 +18,8 @@ Required Properties: - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller. - - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller. + - "renesas,gpio-r8a7796": for R8A77960 (R-Car M3-W) compatible GPIO controller. + - "renesas,gpio-r8a77961": for R8A77961 (R-Car M3-W+) compatible GPIO controller. - "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO controller. - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller. - "renesas,gpio-r8a77980": for R8A77980 (R-Car V3H) compatible GPIO controller. diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml new file mode 100644 index 000000000000..418e8381e07c --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive GPIO controller + +maintainers: + - Yash Shah <yash.shah@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> + +properties: + compatible: + items: + - const: sifive,fu540-c000-gpio + - const: sifive,gpio0 + + reg: + maxItems: 1 + + interrupts: + description: + interrupt mapping one per GPIO. Maximum 16 GPIOs. + minItems: 1 + maxItems: 16 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + clocks: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - clocks + - "#gpio-cells" + - gpio-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sifive-fu540-prci.h> + gpio@10060000 { + compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; + interrupt-parent = <&plic>; + interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + reg = <0x0 0x10060000 0x0 0x1000>; + clocks = <&tlclk PRCI_CLK_TLCLK>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + +... diff --git a/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml b/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml new file mode 100644 index 000000000000..d102888c1be7 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Bootlin +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Xylon LogiCVC GPIO controller + +maintainers: + - Paul Kocialkowski <paul.kocialkowski@bootlin.com> + +description: | + The LogiCVC GPIO describes the GPIO block included in the LogiCVC display + controller. These are meant to be used for controlling display-related + signals. + + The controller exposes GPIOs from the display and power control registers, + which are mapped by the driver as follows: + - GPIO[4:0] (display control) mapped to index 0-4 + - EN_BLIGHT (power control) mapped to index 5 + - EN_VDD (power control) mapped to index 6 + - EN_VEE (power control) mapped to index 7 + - V_EN (power control) mapped to index 8 + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + enum: + - xylon,logicvc-3.02.a-gpio + + reg: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + + gpio-line-names: + minItems: 1 + maxItems: 9 + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + +examples: + - | + logicvc: logicvc@43c00000 { + compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd"; + reg = <0x43c00000 0x6000>; + + #address-cells = <1>; + #size-cells = <1>; + + logicvc_gpio: gpio@40 { + compatible = "xylon,logicvc-3.02.a-gpio"; + reg = <0x40 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", + "EN_BLIGHT", "EN_VDD", "EN_VEE", "V_EN"; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml new file mode 100644 index 000000000000..2a9822075b36 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,adm1177.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor + +maintainers: + - Michael Hennerich <michael.hennerich@analog.com> + - Beniamin Bia <beniamin.bia@analog.com> + +description: | + Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor + https://www.analog.com/media/en/technical-documentation/data-sheets/ADM1177.pdf + +properties: + compatible: + enum: + - adi,adm1177 + + reg: + maxItems: 1 + + avcc-supply: + description: + Phandle to the Avcc power supply + + shunt-resistor-micro-ohms: + description: + The value of curent sense resistor in microohms. If not provided, + the current reading and overcurrent alert is disabled. + + adi,shutdown-threshold-microamp: + description: + Specifies the current level at which an over current alert occurs. + If not provided, the overcurrent alert is configured to max ADC range + based on shunt-resistor-micro-ohms. + + adi,vrange-high-enable: + description: + Specifies which internal voltage divider to be used. A 1 selects + a 7:2 voltage divider while a 0 selects a 14:1 voltage divider. + type: boolean + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + pwmon@5a { + compatible = "adi,adm1177"; + reg = <0x5a>; + shunt-resistor-micro-ohms = <50000>; /* 50 mOhm */ + adi,shutdown-threshold-microamp = <1059000>; /* 1.059 A */ + adi,vrange-high-enable; + }; + }; +... diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml new file mode 100644 index 000000000000..5d42e1304202 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/hwmon/pmbus/ti,ucd90320.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UCD90320 power sequencer + +maintainers: + - Jim Wright <wrightj@linux.vnet.ibm.com> + +description: | + The UCD90320 is a 32-rail PMBus/I2C addressable power-supply sequencer and + monitor. The 24 integrated ADC channels (AMONx) monitor the power supply + voltage, current, and temperature. Of the 84 GPIO pins, 8 can be used as + digital monitors (DMONx), 32 to enable the power supply (ENx), 24 for + margining (MARx), 16 for logical GPO, and 32 GPIs for cascading, and system + function. + + http://focus.ti.com/lit/ds/symlink/ucd90320.pdf + +properties: + compatible: + enum: + - ti,ucd90320 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ucd90320@11 { + compatible = "ti,ucd90320"; + reg = <0x11>; + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/allwinner,sun6i-a31-p2wi.yaml b/Documentation/devicetree/bindings/i2c/allwinner,sun6i-a31-p2wi.yaml index 9346ef6ba61b..6097e8ac46c1 100644 --- a/Documentation/devicetree/bindings/i2c/allwinner,sun6i-a31-p2wi.yaml +++ b/Documentation/devicetree/bindings/i2c/allwinner,sun6i-a31-p2wi.yaml @@ -8,7 +8,7 @@ title: Allwinner A31 P2WI (Push/Pull 2 Wires Interface) Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt index 2210f4359c45..8347b1e7c080 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt @@ -18,8 +18,10 @@ Optional properties: - dma-names: should contain "tx" and "rx". - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO capable I2C controllers. -- i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c" - and "atmel,sama5d2-i2c". +- i2c-sda-hold-time-ns: TWD hold time, only available for: + "atmel,sama5d4-i2c", + "atmel,sama5d2-i2c", + "microchip,sam9x60-i2c". - Child nodes conforming to i2c bus binding Examples : diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt index b245363d6d60..f0c072ff9eca 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt @@ -4,6 +4,7 @@ Required properties: - compatible : - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc - "fsl,imx8qxp-lpi2c" for LPI2C compatible with the one integrated on i.MX8QXP soc + - "fsl,imx8qm-lpi2c" for LPI2C compatible with the one integrated on i.MX8QM soc - reg : address and length of the lpi2c master registers - interrupts : lpi2c interrupt - clocks : lpi2c clock specifier diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml new file mode 100644 index 000000000000..4147f02b5e3c --- /dev/null +++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/accel/adi,adis16240.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADIS16240 Programmable Impact Sensor and Recorder driver + +maintainers: + - Alexandru Ardelean <alexandru.ardelean@analog.com> + +description: | + ADIS16240 Programmable Impact Sensor and Recorder driver that supports + SPI interface. + https://www.analog.com/en/products/adis16240.html + +properties: + compatible: + enum: + - adi,adis16240 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + spi0 { + #address-cells = <1>; + #size-cells = <0>; + + /* Example for a SPI device node */ + accelerometer@0 { + compatible = "adi,adis16240"; + reg = <0>; + spi-max-frequency = <2500000>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/accel/bma180.txt b/Documentation/devicetree/bindings/iio/accel/bma180.txt index 3b25b4c4d446..f53237270b32 100644 --- a/Documentation/devicetree/bindings/iio/accel/bma180.txt +++ b/Documentation/devicetree/bindings/iio/accel/bma180.txt @@ -1,11 +1,14 @@ -* Bosch BMA180 / BMA250 triaxial acceleration sensor +* Bosch BMA180 / BMA25x triaxial acceleration sensor http://omapworld.com/BMA180_111_1002839.pdf http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-ds002-05.pdf Required properties: - - compatible : should be "bosch,bma180" or "bosch,bma250" + - compatible : should be one of: + "bosch,bma180" + "bosch,bma250" + "bosch,bma254" - reg : the I2C address of the sensor Optional properties: diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml new file mode 100644 index 000000000000..c1c6d6f223cf --- /dev/null +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/accel/bosch,bma400.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bosch BMA400 triaxial acceleration sensor + +maintainers: + - Dan Robertson <dan@dlrobertson.com> + +description: | + Acceleration and temperature iio sensors with an i2c interface + + Specifications about the sensor can be found at: + https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMA400-DS000.pdf + +properties: + compatible: + enum: + - bosch,bma400 + + reg: + maxItems: 1 + + vdd-supply: + description: phandle to the regulator that provides power to the accelerometer + + vddio-supply: + description: phandle to the regulator that provides power to the sensor's IO + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + accelerometer@14 { + compatible = "bosch,bma400"; + reg = <0x14>; + vdd-supply = <&vdd>; + vddio-supply = <&vddio>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.txt b/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.txt index eb76a02e2a82..ce950e162d5d 100644 --- a/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.txt +++ b/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.txt @@ -9,9 +9,16 @@ Required properties: "kionix,kxtf9" - reg: i2c slave address +Optional properties: + + - mount-matrix: an optional 3x3 mounting rotation matrix + Example: kxtf9@f { compatible = "kionix,kxtf9"; reg = <0x0F>; + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "1"; }; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml new file mode 100644 index 000000000000..31ffa275f5fa --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7091r5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD7091R5 4-Channel 12-Bit ADC + +maintainers: + - Beniamin Bia <beniamin.bia@analog.com> + +description: | + Analog Devices AD7091R5 4-Channel 12-Bit ADC + https://www.analog.com/media/en/technical-documentation/data-sheets/ad7091r-5.pdf + +properties: + compatible: + enum: + - adi,ad7091r5 + + reg: + maxItems: 1 + + vref-supply: + description: + Phandle to the vref power supply + + interrupts: + maxItems: 1 + + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@2f { + compatible = "adi,ad7091r5"; + reg = <0x2f>; + + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml index b68be3aaf587..e1f6d64bdccd 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/iio/adc/adi,ad7292.yaml# @@ -53,7 +53,8 @@ patternProperties: description: | The channel number. It can have up to 8 channels numbered from 0 to 7. items: - maximum: 7 + - minimum: 0 + maximum: 7 diff-channels: description: see Documentation/devicetree/bindings/iio/adc/adc.txt diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 6eb33207a167..5117ad68a584 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -82,7 +82,7 @@ properties: Must be the device tree identifier of the over-sampling mode pins. As the line is active high, it should be marked GPIO_ACTIVE_HIGH. - maxItems: 1 + maxItems: 3 adi,sw-mode: description: @@ -125,9 +125,9 @@ examples: adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH - &gpio 23 GPIO_ACTIVE_HIGH - &gpio 26 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>, + <&gpio 23 GPIO_ACTIVE_HIGH>, + <&gpio 26 GPIO_ACTIVE_HIGH>; standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>; adi,sw-mode; }; diff --git a/Documentation/devicetree/bindings/iio/adc/allwinner,sun8i-a33-ths.yaml b/Documentation/devicetree/bindings/iio/adc/allwinner,sun8i-a33-ths.yaml index d74962c0f5ae..15c514b83583 100644 --- a/Documentation/devicetree/bindings/iio/adc/allwinner,sun8i-a33-ths.yaml +++ b/Documentation/devicetree/bindings/iio/adc/allwinner,sun8i-a33-ths.yaml @@ -8,7 +8,7 @@ title: Allwinner A33 Thermal Sensor Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#io-channel-cells": diff --git a/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml b/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml new file mode 100644 index 000000000000..59009997dca0 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/lltc,ltc2496.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Linear Technology / Analog Devices LTC2496 ADC + +maintainers: + - Lars-Peter Clausen <lars@metafoo.de> + - Michael Hennerich <Michael.Hennerich@analog.com> + - Stefan Popa <stefan.popa@analog.com> + +properties: + compatible: + enum: + - lltc,ltc2496 + + vref-supply: + description: phandle to an external regulator providing the reference voltage + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + reg: + description: spi chipselect number according to the usual spi bindings + + spi-max-frequency: + description: maximal spi bus frequency supported + +required: + - compatible + - vref-supply + - reg + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "lltc,ltc2496"; + reg = <0>; + vref-supply = <<c2496_reg>; + spi-max-frequency = <2000000>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt deleted file mode 100644 index 59b92cd32552..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt +++ /dev/null @@ -1,13 +0,0 @@ -Device-Tree bindings for sigma delta modulator - -Required properties: -- compatible: should be "ads1201", "sd-modulator". "sd-modulator" can be use - as a generic SD modulator if modulator not specified in compatible list. -- #io-channel-cells = <0>: See the IIO bindings section "IIO consumers". - -Example node: - - ads1202: adc { - compatible = "sd-modulator"; - #io-channel-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml new file mode 100644 index 000000000000..a390343d0c2a --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/sigma-delta-modulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device-Tree bindings for sigma delta modulator + +maintainers: + - Arnaud Pouliquen <arnaud.pouliquen@st.com> + +properties: + compatible: + description: | + "sd-modulator" can be used as a generic SD modulator, + if the modulator is not specified in the compatible list. + enum: + - sd-modulator + - ads1201 + + '#io-channel-cells': + const: 0 + +required: + - compatible + - '#io-channel-cells' + +additionalProperties: false + +examples: + - | + ads1202: adc { + compatible = "sd-modulator"; + #io-channel-cells = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt deleted file mode 100644 index 75ba25d062e1..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt +++ /dev/null @@ -1,135 +0,0 @@ -STMicroelectronics STM32 DFSDM ADC device driver - - -STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to -interface external sigma delta modulators to STM32 micro controllers. -It is mainly targeted for: -- Sigma delta modulators (motor control, metering...) -- PDM microphones (audio digital microphone) - -It features up to 8 serial digital interfaces (SPI or Manchester) and -up to 4 filters on stm32h7 or 6 filters on stm32mp1. - -Each child node match with a filter instance. - -Contents of a STM32 DFSDM root node: ------------------------------------- -Required properties: -- compatible: Should be one of: - "st,stm32h7-dfsdm" - "st,stm32mp1-dfsdm" -- reg: Offset and length of the DFSDM block register set. -- clocks: IP and serial interfaces clocking. Should be set according - to rcc clock ID and "clock-names". -- clock-names: Input clock name "dfsdm" must be defined, - "audio" is optional. If defined CLKOUT is based on the audio - clock, else "dfsdm" is used. -- #interrupt-cells = <1>; -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- spi-max-frequency: Requested only for SPI master mode. - SPI clock OUT frequency (Hz). This clock must be set according - to "clock" property. Frequency must be a multiple of the rcc - clock frequency. If not, SPI CLKOUT frequency will not be - accurate. -- pinctrl-names: Set to "default". -- pinctrl-0: List of phandles pointing to pin configuration - nodes to set pins in mode of operation for dfsdm - on external pin. - -Contents of a STM32 DFSDM child nodes: --------------------------------------- - -Required properties: -- compatible: Must be: - "st,stm32-dfsdm-adc" for sigma delta ADCs - "st,stm32-dfsdm-dmic" for audio digital microphone. -- reg: Specifies the DFSDM filter instance used. - Valid values are from 0 to 3 on stm32h7, 0 to 5 on stm32mp1. -- interrupts: IRQ lines connected to each DFSDM filter instance. -- st,adc-channels: List of single-ended channels muxed for this ADC. - valid values: - "st,stm32h7-dfsdm" compatibility: 0 to 7. -- st,adc-channel-names: List of single-ended channel names. -- st,filter-order: SinC filter order from 0 to 5. - 0: FastSinC - [1-5]: order 1 to 5. - For audio purpose it is recommended to use order 3 to 5. -- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers". - -Required properties for "st,stm32-dfsdm-adc" compatibility: -- io-channels: From common IIO binding. Used to pipe external sigma delta - modulator or internal ADC output to DFSDM channel. - This is not required for "st,stm32-dfsdm-pdm" compatibility as - PDM microphone is binded in Audio DT node. - -Required properties for "st,stm32-dfsdm-pdm" compatibility: -- #sound-dai-cells: Must be set to 0. -- dma: DMA controller phandle and DMA request line associated to the - filter instance (specified by the field "reg") -- dma-names: Must be "rx" - -Optional properties: -- st,adc-channel-types: Single-ended channel input type. - - "SPI_R": SPI with data on rising edge (default) - - "SPI_F": SPI with data on falling edge - - "MANCH_R": manchester codec, rising edge = logic 0, falling edge = logic 1 - - "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0 -- st,adc-channel-clk-src: Conversion clock source. - - "CLKIN": external SPI clock (CLKIN x) - - "CLKOUT": internal SPI clock (CLKOUT) (default) - - "CLKOUT_F": internal SPI clock divided by 2 (falling edge). - - "CLKOUT_R": internal SPI clock divided by 2 (rising edge). - -- st,adc-alt-channel: Must be defined if two sigma delta modulator are - connected on same SPI input. - If not set, channel n is connected to SPI input n. - If set, channel n is connected to SPI input n + 1. - -- st,filter0-sync: Set to 1 to synchronize with DFSDM filter instance 0. - Used for multi microphones synchronization. - -Example of a sigma delta adc connected on DFSDM SPI port 0 -and a pdm microphone connected on DFSDM SPI port 1: - - ads1202: simple_sd_adc@0 { - compatible = "ads1202"; - #io-channel-cells = <1>; - }; - - dfsdm: dfsdm@40017000 { - compatible = "st,stm32h7-dfsdm"; - reg = <0x40017000 0x400>; - clocks = <&rcc DFSDM1_CK>; - clock-names = "dfsdm"; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dfsdm_adc0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <0>; - interrupts = <110>; - st,adc-channels = <0>; - st,adc-channel-names = "sd_adc0"; - st,adc-channel-types = "SPI_F"; - st,adc-channel-clk-src = "CLKOUT"; - io-channels = <&ads1202 0>; - st,filter-order = <3>; - }; - dfsdm_pdm1: filter@1 { - compatible = "st,stm32-dfsdm-dmic"; - reg = <1>; - interrupts = <111>; - dmas = <&dmamux1 102 0x400 0x00>; - dma-names = "rx"; - st,adc-channels = <1>; - st,adc-channel-names = "dmic1"; - st,adc-channel-types = "SPI_R"; - st,adc-channel-clk-src = "CLKOUT"; - st,filter-order = <5>; - }; - } diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml new file mode 100644 index 000000000000..c91407081aa5 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -0,0 +1,332 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/st,stm32-dfsdm-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DFSDM ADC device driver + +maintainers: + - Fabrice Gasnier <fabrice.gasnier@st.com> + - Olivier Moysan <olivier.moysan@st.com> + +description: | + STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to + interface external sigma delta modulators to STM32 micro controllers. + It is mainly targeted for: + - Sigma delta modulators (motor control, metering...) + - PDM microphones (audio digital microphone) + + It features up to 8 serial digital interfaces (SPI or Manchester) and + up to 4 filters on stm32h7 or 6 filters on stm32mp1. + + Each child node matches with a filter instance. + +properties: + compatible: + enum: + - st,stm32h7-dfsdm + - st,stm32mp1-dfsdm + + reg: + maxItems: 1 + + clocks: + items: + - description: + Internal clock used for DFSDM digital processing and control blocks. + dfsdm clock can also feed CLKOUT, when CLKOUT is used. + - description: audio clock can be used as an alternate to feed CLKOUT. + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: dfsdm + - const: audio + minItems: 1 + maxItems: 2 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + spi-max-frequency: + description: + SPI clock OUT frequency (Hz). Requested only for SPI master mode. + This clock must be set according to the "clock" property. + Frequency must be a multiple of the rcc clock frequency. + If not, SPI CLKOUT frequency will not be accurate. + maximum: 20000000 + +required: + - compatible + - reg + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + +patternProperties: + "^filter@[0-9]+$": + type: object + description: child node + + properties: + compatible: + enum: + - st,stm32-dfsdm-adc + - st,stm32-dfsdm-dmic + + reg: + description: Specifies the DFSDM filter instance used. + maxItems: 1 + + interrupts: + maxItems: 1 + + st,adc-channels: + description: | + List of single-ended channels muxed for this ADC. + On stm32h7 and stm32mp1: + - For st,stm32-dfsdm-adc: up to 8 channels numbered from 0 to 7. + - For st,stm32-dfsdm-dmic: 1 channel numbered from 0 to 7. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minimum: 0 + maximum: 7 + + st,adc-channel-names: + description: List of single-ended channel names. + allOf: + - $ref: /schemas/types.yaml#/definitions/string-array + + st,filter-order: + description: | + SinC filter order from 0 to 5. + - 0: FastSinC + - [1-5]: order 1 to 5. + For audio purpose it is recommended to use order 3 to 5. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - items: + minimum: 0 + maximum: 5 + + "#io-channel-cells": + const: 1 + + st,adc-channel-types: + description: | + Single-ended channel input type. + - "SPI_R": SPI with data on rising edge (default) + - "SPI_F": SPI with data on falling edge + - "MANCH_R": manchester codec, rising edge = logic 0, falling edge = logic 1 + - "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0 + items: + enum: [ SPI_R, SPI_F, MANCH_R, MANCH_F ] + allOf: + - $ref: /schemas/types.yaml#/definitions/non-unique-string-array + + st,adc-channel-clk-src: + description: | + Conversion clock source. + - "CLKIN": external SPI clock (CLKIN x) + - "CLKOUT": internal SPI clock (CLKOUT) (default) + - "CLKOUT_F": internal SPI clock divided by 2 (falling edge). + - "CLKOUT_R": internal SPI clock divided by 2 (rising edge). + items: + enum: [ CLKIN, CLKOUT, CLKOUT_F, CLKOUT_R ] + allOf: + - $ref: /schemas/types.yaml#/definitions/non-unique-string-array + + st,adc-alt-channel: + description: + Must be defined if two sigma delta modulators are + connected on same SPI input. + If not set, channel n is connected to SPI input n. + If set, channel n is connected to SPI input n + 1. + type: boolean + + st,filter0-sync: + description: + Set to 1 to synchronize with DFSDM filter instance 0. + Used for multi microphones synchronization. + type: boolean + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rx + + required: + - compatible + - reg + - interrupts + - st,adc-channels + - st,adc-channel-names + - st,filter-order + - "#io-channel-cells" + + allOf: + - if: + properties: + compatible: + contains: + const: st,stm32-dfsdm-adc + + - then: + properties: + st,adc-channels: + minItems: 1 + maxItems: 8 + + st,adc-channel-names: + minItems: 1 + maxItems: 8 + + st,adc-channel-types: + minItems: 1 + maxItems: 8 + + st,adc-channel-clk-src: + minItems: 1 + maxItems: 8 + + io-channels: + description: + From common IIO binding. Used to pipe external sigma delta + modulator or internal ADC output to DFSDM channel. + This is not required for "st,stm32-dfsdm-pdm" compatibility as + PDM microphone is binded in Audio DT node. + + required: + - io-channels + + - if: + properties: + compatible: + contains: + const: st,stm32-dfsdm-dmic + + - then: + properties: + st,adc-channels: + maxItems: 1 + + st,adc-channel-names: + maxItems: 1 + + st,adc-channel-types: + maxItems: 1 + + st,adc-channel-clk-src: + maxItems: 1 + + required: + - dmas + - dma-names + + patternProperties: + "^dfsdm-dai+$": + type: object + description: child node + + properties: + "#sound-dai-cells": + const: 0 + + io-channels: + description: + From common IIO binding. Used to pipe external sigma delta + modulator or internal ADC output to DFSDM channel. + + required: + - "#sound-dai-cells" + - io-channels + +allOf: + - if: + properties: + compatible: + contains: + const: st,stm32h7-dfsdm + + - then: + patternProperties: + "^filter@[0-9]+$": + properties: + reg: + items: + minimum: 0 + maximum: 3 + + - if: + properties: + compatible: + contains: + const: st,stm32mp1-dfsdm + + - then: + patternProperties: + "^filter@[0-9]+$": + properties: + reg: + items: + minimum: 0 + maximum: 5 + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>; + clock-names = "dfsdm", "audio"; + #address-cells = <1>; + #size-cells = <0>; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-dmic"; + reg = <0>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + #io-channel-cells = <1>; + st,adc-channels = <1>; + st,adc-channel-names = "dmic0"; + st,adc-channel-types = "SPI_R"; + st,adc-channel-clk-src = "CLKOUT"; + st,filter-order = <5>; + + asoc_pdm0: dfsdm-dai { + compatible = "st,stm32h7-dfsdm-dai"; + #sound-dai-cells = <0>; + io-channels = <&dfsdm0 0>; + }; + }; + + dfsdm_pdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + reg = <1>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + #io-channel-cells = <1>; + st,adc-channels = <2 3>; + st,adc-channel-names = "in2", "in3"; + st,adc-channel-types = "SPI_R", "SPI_R"; + st,adc-channel-clk-src = "CLKOUT_F", "CLKOUT_F"; + io-channels = <&sd_adc2 &sd_adc3>; + st,filter-order = <1>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16480.txt b/Documentation/devicetree/bindings/iio/imu/adi,adis16480.txt index ed7783f45233..cd903a1d880d 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16480.txt +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16480.txt @@ -8,6 +8,7 @@ Required properties for the ADIS16480: * "adi,adis16480" * "adi,adis16485" * "adi,adis16488" + * "adi,adis16490" * "adi,adis16495-1" * "adi,adis16495-2" * "adi,adis16495-3" diff --git a/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml new file mode 100644 index 000000000000..9f5ca9c42025 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/pressure/asc,dlhl60d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: All Sensors DLH series low voltage digital pressure sensors + +maintainers: + - Tomislav Denis <tomislav.denis@avl.com> + +description: | + Bindings for the All Sensors DLH series pressure sensors. + + Specifications about the sensors can be found at: + http://www.allsensors.com/cad/DS-0355_Rev_B.PDF + +properties: + compatible: + enum: + - asc,dlhl60d + - asc,dlhl60g + + reg: + description: I2C device address + maxItems: 1 + + interrupts: + description: interrupt mapping for EOC(data ready) pin + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + pressure@29 { + compatible = "asc,dlhl60d"; + reg = <0x29>; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_EDGE_RISING>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml b/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml new file mode 100644 index 000000000000..a079c9921af6 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/proximity/parallax-ping.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Parallax PING))) and LaserPING range finder + +maintainers: + - Andreas Klinger <ak@it-klinger.de> + +description: | + Bit-banging driver using one GPIO: + - ping-gpios is raised by the driver to start measurement + - direction of ping-gpio is then switched into input with an interrupt + for receiving distance value as PWM signal + + Specifications about the devices can be found at: + http://parallax.com/sites/default/files/downloads/28041-LaserPING-2m-Rangefinder-Guide.pdf + http://parallax.com/sites/default/files/downloads/28015-PING-Documentation-v1.6.pdf + +properties: + compatible: + enum: + - parallax,ping + - parallax,laserping + + ping-gpios: + description: + Definition of the GPIO for the triggering and echo (output and input) + This GPIO is set for about 5 us by the driver to tell the device it + should initiate the measurement cycle. Afterwards the GPIO is switched + to input direction with an interrupt. The device sets it and the + length of the input signal corresponds to the measured distance. + It needs to be an GPIO which is able to deliver an interrupt because + the time between two interrupts is measured in the driver. + See Documentation/devicetree/bindings/gpio/gpio.txt for information + on how to specify a consumer gpio. + maxItems: 1 + +required: + - compatible + - ping-gpios + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + proximity { + compatible = "parallax,laserping"; + ping-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt b/Documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt index 28bc5c4d965b..bb85cd0e039c 100644 --- a/Documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt +++ b/Documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt @@ -5,7 +5,10 @@ Maxim thermocouple support Required properties: - - compatible: must be "maxim,max31855" or "maxim,max6675" + - compatible: must be "maxim,max6675" or one of the following: + "maxim,max31855k", "maxim,max31855j", "maxim,max31855n", + "maxim,max31855s", "maxim,max31855t", "maxim,max31855e", + "maxim,max31855r"; the generic "max,max31855" is deprecated. - reg: SPI chip select number for the device - spi-max-frequency: must be 4300000 - spi-cpha: must be defined for max6675 to enable SPI mode 1 @@ -15,7 +18,7 @@ Required properties: Example: max31855@0 { - compatible = "maxim,max31855"; + compatible = "maxim,max31855k"; reg = <0>; spi-max-frequency = <4300000>; }; diff --git a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index b3bd8ef7fbd6..5b3b71c9c018 100644 --- a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 LRADC Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt index 0f6950073d6f..0e57315e9cbd 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt @@ -36,6 +36,8 @@ Optional properties: - pinctrl-0: a phandle pointing to the pin settings for the control gpios + - wakeup-source: If present the device will act as wakeup-source + - threshold: allows setting the "click"-threshold in the range from 0 to 80. diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.txt b/Documentation/devicetree/bindings/input/touchscreen/goodix.txt deleted file mode 100644 index fc03ea4cf5ab..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.txt +++ /dev/null @@ -1,50 +0,0 @@ -Device tree bindings for Goodix GT9xx series touchscreen controller - -Required properties: - - - compatible : Should be "goodix,gt1151" - or "goodix,gt5663" - or "goodix,gt5688" - or "goodix,gt911" - or "goodix,gt9110" - or "goodix,gt912" - or "goodix,gt927" - or "goodix,gt9271" - or "goodix,gt928" - or "goodix,gt967" - - reg : I2C address of the chip. Should be 0x5d or 0x14 - - interrupts : Interrupt to which the chip is connected - -Optional properties: - - - irq-gpios : GPIO pin used for IRQ. The driver uses the - interrupt gpio pin as output to reset the device. - - reset-gpios : GPIO pin used for reset - - AVDD28-supply : Analog power supply regulator on AVDD28 pin - - VDDIO-supply : GPIO power supply regulator on VDDIO pin - - touchscreen-inverted-x - - touchscreen-inverted-y - - touchscreen-size-x - - touchscreen-size-y - - touchscreen-swapped-x-y - -The touchscreen-* properties are documented in touchscreen.txt in this -directory. - -Example: - - i2c@00000000 { - /* ... */ - - gt928@5d { - compatible = "goodix,gt928"; - reg = <0x5d>; - interrupt-parent = <&gpio>; - interrupts = <0 0>; - - irq-gpios = <&gpio1 0 0>; - reset-gpios = <&gpio1 1 0>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml new file mode 100644 index 000000000000..d7c3262b2494 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/goodix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Goodix GT9xx series touchscreen controller Bindings + +maintainers: + - Dmitry Torokhov <dmitry.torokhov@gmail.com> + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - goodix,gt1151 + - goodix,gt5663 + - goodix,gt5688 + - goodix,gt911 + - goodix,gt9110 + - goodix,gt912 + - goodix,gt927 + - goodix,gt9271 + - goodix,gt928 + - goodix,gt967 + + reg: + enum: [ 0x5d, 0x14 ] + + interrupts: + maxItems: 1 + + irq-gpios: + description: GPIO pin used for IRQ. + The driver uses the interrupt gpio pin as + output to reset the device. + maxItems: 1 + + reset-gpios: + maxItems: 1 + + AVDD28-supply: + description: Analog power supply regulator on AVDD28 pin + + VDDIO-supply: + description: GPIO power supply regulator on VDDIO pin + + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-swapped-x-y: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + +examples: +- | + i2c@00000000 { + #address-cells = <1>; + #size-cells = <0>; + gt928@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + interrupt-parent = <&gpio>; + interrupts = <0 0>; + irq-gpios = <&gpio1 0 0>; + reset-gpios = <&gpio1 1 0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt index 8641a2d70851..e1adb902d503 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt @@ -1,39 +1 @@ -General Touchscreen Properties: - -Optional properties for Touchscreens: - - touchscreen-min-x : minimum x coordinate reported (0 if not set) - - touchscreen-min-y : minimum y coordinate reported (0 if not set) - - touchscreen-size-x : horizontal resolution of touchscreen - (maximum x coordinate reported + 1) - - touchscreen-size-y : vertical resolution of touchscreen - (maximum y coordinate reported + 1) - - touchscreen-max-pressure : maximum reported pressure (arbitrary range - dependent on the controller) - - touchscreen-min-pressure : minimum pressure on the touchscreen to be - achieved in order for the touchscreen - driver to report a touch event. - - touchscreen-fuzz-x : horizontal noise value of the absolute input - device (in pixels) - - touchscreen-fuzz-y : vertical noise value of the absolute input - device (in pixels) - - touchscreen-fuzz-pressure : pressure noise value of the absolute input - device (arbitrary range dependent on the - controller) - - touchscreen-average-samples : Number of data samples which are averaged - for each read (valid values dependent on the - controller) - - touchscreen-inverted-x : X axis is inverted (boolean) - - touchscreen-inverted-y : Y axis is inverted (boolean) - - touchscreen-swapped-x-y : X and Y axis are swapped (boolean) - Swapping is done after inverting the axis - - touchscreen-x-mm : horizontal length in mm of the touchscreen - - touchscreen-y-mm : vertical length in mm of the touchscreen - -Deprecated properties for Touchscreens: - - x-size : deprecated name for touchscreen-size-x - - y-size : deprecated name for touchscreen-size-y - - moving-threshold : deprecated name for a combination of - touchscreen-fuzz-x and touchscreen-fuzz-y - - contact-threshold : deprecated name for touchscreen-fuzz-pressure - - x-invert : deprecated name for touchscreen-inverted-x - - y-invert : deprecated name for touchscreen-inverted-y +See touchscreen.yaml diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml new file mode 100644 index 000000000000..d7dac16a3960 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/touchscreen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common touchscreen Bindings + +maintainers: + - Dmitry Torokhov <dmitry.torokhov@gmail.com> + +properties: + touchscreen-min-x: + description: minimum x coordinate reported + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + touchscreen-min-y: + description: minimum y coordinate reported + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + touchscreen-size-x: + description: horizontal resolution of touchscreen (maximum x coordinate reported + 1) + $ref: /schemas/types.yaml#/definitions/uint32 + + touchscreen-size-y: + description: vertical resolution of touchscreen (maximum y coordinate reported + 1) + $ref: /schemas/types.yaml#/definitions/uint32 + + touchscreen-max-pressure: + description: maximum reported pressure (arbitrary range dependent on the controller) + $ref: /schemas/types.yaml#/definitions/uint32 + + touchscreen-min-pressure: + description: minimum pressure on the touchscreen to be achieved in order for the + touchscreen driver to report a touch event. + $ref: /schemas/types.yaml#/definitions/uint32 + + touchscreen-fuzz-x: + description: horizontal noise value of the absolute input device (in pixels) + $ref: /schemas/types.yaml#/definitions/uint32 + + touchscreen-fuzz-y: + description: vertical noise value of the absolute input device (in pixels) + $ref: /schemas/types.yaml#/definitions/uint32 + + touchscreen-fuzz-pressure: + description: pressure noise value of the absolute input device (arbitrary range + dependent on the controller) + $ref: /schemas/types.yaml#/definitions/uint32 + + touchscreen-average-samples: + description: Number of data samples which are averaged for each read (valid values + dependent on the controller) + $ref: /schemas/types.yaml#/definitions/uint32 + + touchscreen-inverted-x: + description: X axis is inverted + type: boolean + + touchscreen-inverted-y: + description: Y axis is inverted + type: boolean + + touchscreen-swapped-x-y: + description: X and Y axis are swapped + Swapping is done after inverting the axis + type: boolean + + touchscreen-x-mm: + description: horizontal length in mm of the touchscreen + $ref: /schemas/types.yaml#/definitions/uint32 + + touchscreen-y-mm: + description: vertical length in mm of the touchscreen + $ref: /schemas/types.yaml#/definitions/uint32 + +dependencies: + touchscreen-size-x: [ touchscreen-size-y ] + touchscreen-size-y: [ touchscreen-size-x ] + touchscreen-x-mm: [ touchscreen-y-mm ] + touchscreen-y-mm: [ touchscreen-x-mm ] diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8916.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8916.yaml new file mode 100644 index 000000000000..4107e60cab12 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8916.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,msm8916.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8916 Network-On-Chip interconnect + +maintainers: + - Georgi Djakov <georgi.djakov@linaro.org> + +description: | + The Qualcomm MSM8916 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + compatible: + enum: + - qcom,msm8916-bimc + - qcom,msm8916-pcnoc + - qcom,msm8916-snoc + + reg: + maxItems: 1 + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: bus + - const: bus_a + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + +required: + - compatible + - reg + - '#interconnect-cells' + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + + bimc: interconnect@400000 { + compatible = "qcom,msm8916-bimc"; + reg = <0x00400000 0x62000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + pcnoc: interconnect@500000 { + compatible = "qcom,msm8916-pcnoc"; + reg = <0x00500000 0x11000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + + snoc: interconnect@580000 { + compatible = "qcom,msm8916-snoc"; + reg = <0x00580000 0x14000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml index 23a202d24e43..953d875b5e74 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 Interrupt Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> allOf: - $ref: /schemas/interrupt-controller.yaml# diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index 8cd08cfb25be..cf09055da78b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -8,7 +8,7 @@ title: Allwinner A20 Non-Maskable Interrupt Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> allOf: - $ref: /schemas/interrupt-controller.yaml# diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index 684bb1cd75ec..23b18b92c558 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -17,6 +17,7 @@ Required properties: "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3) + "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L) - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt new file mode 100644 index 000000000000..251ed44171db --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt @@ -0,0 +1,23 @@ +Aspeed AST25XX and AST26XX SCU Interrupt Controller + +Required Properties: + - #interrupt-cells : must be 1 + - compatible : must be "aspeed,ast2500-scu-ic", + "aspeed,ast2600-scu-ic0" or + "aspeed,ast2600-scu-ic1" + - interrupts : interrupt from the parent controller + - interrupt-controller : indicates that the controller receives and + fires new interrupts for child busses + +Example: + + syscon@1e6e2000 { + ranges = <0 0x1e6e2000 0x1a8>; + + scu_ic: interrupt-controller@18 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-scu-ic"; + interrupts = <21>; + interrupt-controller; + }; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.yaml new file mode 100644 index 000000000000..43c6effbb5bd --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale INTMUX interrupt multiplexer + +maintainers: + - Joakim Zhang <qiangqing.zhang@nxp.com> + +properties: + compatible: + const: fsl,imx-intmux + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 8 + description: | + Should contain the parent interrupt lines (up to 8) used to multiplex + the input interrupts. + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: | + The 1st cell is hw interrupt number, the 2nd cell is channel index. + + clocks: + description: ipg clock. + + clock-names: + const: ipg + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + interrupt-controller@37400000 { + compatible = "fsl,imx-intmux"; + reg = <0x37400000 0x1000>; + interrupts = <0 16 4>, + <0 17 4>, + <0 18 4>, + <0 19 4>, + <0 20 4>, + <0 21 4>, + <0 22 4>, + <0 23 4>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk>; + clock-names = "ipg"; + }; diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt index 9fa6f9795d50..26d770ef3601 100644 --- a/Documentation/devicetree/bindings/leds/common.txt +++ b/Documentation/devicetree/bindings/leds/common.txt @@ -1,173 +1 @@ -* Common leds properties. - -LED and flash LED devices provide the same basic functionality as current -regulators, but extended with LED and flash LED specific features like -blinking patterns, flash timeout, flash faults and external flash strobe mode. - -Many LED devices expose more than one current output that can be connected -to one or more discrete LED component. Since the arrangement of connections -can influence the way of the LED device initialization, the LED components -have to be tightly coupled with the LED device binding. They are represented -by child nodes of the parent LED device binding. - - -Optional properties for child nodes: -- led-sources : List of device current outputs the LED is connected to. The - outputs are identified by the numbers that must be defined - in the LED device binding documentation. - -- function: LED functon. Use one of the LED_FUNCTION_* prefixed definitions - from the header include/dt-bindings/leds/common.h. - If there is no matching LED_FUNCTION available, add a new one. - -- color : Color of the LED. Use one of the LED_COLOR_ID_* prefixed definitions - from the header include/dt-bindings/leds/common.h. - If there is no matching LED_COLOR_ID available, add a new one. - -- function-enumerator: Integer to be used when more than one instance - of the same function is needed, differing only with - an ordinal number. - -- label : The label for this LED. If omitted, the label is taken from the node - name (excluding the unit address). It has to uniquely identify - a device, i.e. no other LED class device can be assigned the same - label. This property is deprecated - use 'function' and 'color' - properties instead. function-enumerator has no effect when this - property is present. - -- default-state : The initial state of the LED. Valid values are "on", "off", - and "keep". If the LED is already on or off and the default-state property is - set the to same value, then no glitch should be produced where the LED - momentarily turns off (or on). The "keep" setting will keep the LED at - whatever its current state is, without producing a glitch. The default is - off if this property is not present. - -- linux,default-trigger : This parameter, if present, is a - string defining the trigger assigned to the LED. Current triggers are: - "backlight" - LED will act as a back-light, controlled by the framebuffer - system - "default-on" - LED will turn on (but for leds-gpio see "default-state" - property in Documentation/devicetree/bindings/leds/leds-gpio.txt) - "heartbeat" - LED "double" flashes at a load average based rate - "disk-activity" - LED indicates disk activity - "ide-disk" - LED indicates IDE disk activity (deprecated), - in new implementations use "disk-activity" - "timer" - LED flashes at a fixed, configurable rate - "pattern" - LED alters the brightness for the specified duration with one - software timer (requires "led-pattern" property) - -- led-pattern : Array of integers with default pattern for certain triggers. - Each trigger may parse this property differently: - - one-shot : two numbers specifying delay on and delay off (in ms), - - timer : two numbers specifying delay on and delay off (in ms), - - pattern : the pattern is given by a series of tuples, of - brightness and duration (in ms). The exact format is - described in: - Documentation/devicetree/bindings/leds/leds-trigger-pattern.txt - - -- led-max-microamp : Maximum LED supply current in microamperes. This property - can be made mandatory for the board configurations - introducing a risk of hardware damage in case an excessive - current is set. - For flash LED controllers with configurable current this - property is mandatory for the LEDs in the non-flash modes - (e.g. torch or indicator). - -- panic-indicator : This property specifies that the LED should be used, - if at all possible, as a panic indicator. - -- trigger-sources : List of devices which should be used as a source triggering - this LED activity. Some LEDs can be related to a specific - device and should somehow indicate its state. E.g. USB 2.0 - LED may react to device(s) in a USB 2.0 port(s). - Another common example is switch or router with multiple - Ethernet ports each of them having its own LED assigned - (assuming they are not hardwired). In such cases this - property should contain phandle(s) of related source - device(s). - In many cases LED can be related to more than one device - (e.g. one USB LED vs. multiple USB ports). Each source - should be represented by a node in the device tree and be - referenced by a phandle and a set of phandle arguments. A - length of arguments should be specified by the - #trigger-source-cells property in the source node. - -Required properties for flash LED child nodes: -- flash-max-microamp : Maximum flash LED supply current in microamperes. -- flash-max-timeout-us : Maximum timeout in microseconds after which the flash - LED is turned off. - -For controllers that have no configurable current the flash-max-microamp -property can be omitted. -For controllers that have no configurable timeout the flash-max-timeout-us -property can be omitted. - -* Trigger source providers - -Each trigger source should be represented by a device tree node. It may be e.g. -a USB port or an Ethernet device. - -Required properties for trigger source: -- #trigger-source-cells : Number of cells in a source trigger. Typically 0 for - nodes of simple trigger sources (e.g. a specific USB - port). - -* Examples - -#include <dt-bindings/leds/common.h> - -led-controller@0 { - compatible = "gpio-leds"; - - led0 { - function = LED_FUNCTION_STATUS; - linux,default-trigger = "heartbeat"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - led1 { - function = LED_FUNCTION_USB; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>; - }; -}; - -led-controller@0 { - compatible = "maxim,max77693-led"; - - led { - function = LED_FUNCTION_FLASH; - color = <LED_COLOR_ID_WHITE>; - led-sources = <0>, <1>; - led-max-microamp = <50000>; - flash-max-microamp = <320000>; - flash-max-timeout-us = <500000>; - }; -}; - -led-controller@30 { - compatible = "panasonic,an30259a"; - reg = <0x30>; - #address-cells = <1>; - #size-cells = <0>; - - led@1 { - reg = <1>; - linux,default-trigger = "heartbeat"; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - }; - - led@2 { - reg = <2>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - }; - - led@3 { - reg = <3>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - }; -}; +This file has moved to ./common.yaml. diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml new file mode 100644 index 000000000000..d97d099b87e5 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common leds properties + +maintainers: + - Jacek Anaszewski <jacek.anaszewski@gmail.com> + - Pavel Machek <pavel@ucw.cz> + +description: + LED and flash LED devices provide the same basic functionality as current + regulators, but extended with LED and flash LED specific features like + blinking patterns, flash timeout, flash faults and external flash strobe mode. + + Many LED devices expose more than one current output that can be connected + to one or more discrete LED component. Since the arrangement of connections + can influence the way of the LED device initialization, the LED components + have to be tightly coupled with the LED device binding. They are represented + by child nodes of the parent LED device binding. + +properties: + led-sources: + description: + List of device current outputs the LED is connected to. The outputs are + identified by the numbers that must be defined in the LED device binding + documentation. + $ref: /schemas/types.yaml#definitions/uint32-array + + function: + description: + LED function. Use one of the LED_FUNCTION_* prefixed definitions + from the header include/dt-bindings/leds/common.h. If there is no + matching LED_FUNCTION available, add a new one. + $ref: /schemas/types.yaml#definitions/string + + color: + description: + Color of the LED. Use one of the LED_COLOR_ID_* prefixed definitions from + the header include/dt-bindings/leds/common.h. If there is no matching + LED_COLOR_ID available, add a new one. + allOf: + - $ref: /schemas/types.yaml#definitions/uint32 + minimum: 0 + maximum: 8 + + function-enumerator: + description: + Integer to be used when more than one instance of the same function is + needed, differing only with an ordinal number. + $ref: /schemas/types.yaml#definitions/uint32 + + label: + description: + The label for this LED. If omitted, the label is taken from the node name + (excluding the unit address). It has to uniquely identify a device, i.e. + no other LED class device can be assigned the same label. This property is + deprecated - use 'function' and 'color' properties instead. + function-enumerator has no effect when this property is present. + + default-state: + description: + The initial state of the LED. If the LED is already on or off and the + default-state property is set the to same value, then no glitch should be + produced where the LED momentarily turns off (or on). The "keep" setting + will keep the LED at whatever its current state is, without producing a + glitch. + allOf: + - $ref: /schemas/types.yaml#definitions/string + enum: + - on + - off + - keep + default: off + + linux,default-trigger: + description: + This parameter, if present, is a string defining the trigger assigned to + the LED. + allOf: + - $ref: /schemas/types.yaml#definitions/string + enum: + # LED will act as a back-light, controlled by the framebuffer system + - backlight + # LED will turn on (but for leds-gpio see "default-state" property in + # Documentation/devicetree/bindings/leds/leds-gpio.txt) + - default-on + # LED "double" flashes at a load average based rate + - heartbeat + # LED indicates disk activity + - disk-activity + # LED indicates IDE disk activity (deprecated), in new implementations + # use "disk-activity" + - ide-disk + # LED flashes at a fixed, configurable rate + - timer + # LED alters the brightness for the specified duration with one software + # timer (requires "led-pattern" property) + - pattern + + led-pattern: + description: | + Array of integers with default pattern for certain triggers. + + Each trigger may parse this property differently: + - one-shot : two numbers specifying delay on and delay off (in ms), + - timer : two numbers specifying delay on and delay off (in ms), + - pattern : the pattern is given by a series of tuples, of + brightness and duration (in ms). The exact format is + described in: + Documentation/devicetree/bindings/leds/leds-trigger-pattern.txt + allOf: + - $ref: /schemas/types.yaml#definitions/uint32-matrix + items: + minItems: 2 + maxItems: 2 + + led-max-microamp: + description: + Maximum LED supply current in microamperes. This property can be made + mandatory for the board configurations introducing a risk of hardware + damage in case an excessive current is set. + For flash LED controllers with configurable current this property is + mandatory for the LEDs in the non-flash modes (e.g. torch or indicator). + + panic-indicator: + description: + This property specifies that the LED should be used, if at all possible, + as a panic indicator. + type: boolean + + trigger-sources: + description: | + List of devices which should be used as a source triggering this LED + activity. Some LEDs can be related to a specific device and should somehow + indicate its state. E.g. USB 2.0 LED may react to device(s) in a USB 2.0 + port(s). + Another common example is switch or router with multiple Ethernet ports + each of them having its own LED assigned (assuming they are not + hardwired). In such cases this property should contain phandle(s) of + related source device(s). + In many cases LED can be related to more than one device (e.g. one USB LED + vs. multiple USB ports). Each source should be represented by a node in + the device tree and be referenced by a phandle and a set of phandle + arguments. A length of arguments should be specified by the + #trigger-source-cells property in the source node. + $ref: /schemas/types.yaml#definitions/phandle-array + + # Required properties for flash LED child nodes: + flash-max-microamp: + description: + Maximum flash LED supply current in microamperes. Required for flash LED + nodes with configurable current. + + flash-max-timeout-us: + description: + Maximum timeout in microseconds after which the flash LED is turned off. + Required for flash LED nodes with configurable timeout. + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/leds/common.h> + + led-controller { + compatible = "gpio-leds"; + + led0 { + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + led1 { + function = LED_FUNCTION_USB; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + }; + }; + + led-controller@0 { + compatible = "maxim,max77693-led"; + reg = <0 0x100>; + + led { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + led-sources = <0>, <1>; + led-max-microamp = <50000>; + flash-max-microamp = <320000>; + flash-max-timeout-us = <500000>; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@30 { + compatible = "panasonic,an30259a"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt b/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt index 21882c8d4b0c..83ff1b4d70a6 100644 --- a/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt +++ b/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt @@ -8,7 +8,7 @@ Required properties: - compatible: should be "ir-spi-led". Optional properties: - - duty-cycle: 8 bit balue that represents the percentage of one period + - duty-cycle: 8 bit value that represents the percentage of one period in which the signal is active. It can be 50, 60, 70, 75, 80 or 90. - led-active-low: boolean value that specifies whether the output is negated with a NOT gate. diff --git a/Documentation/devicetree/bindings/leds/leds-gpio.txt b/Documentation/devicetree/bindings/leds/leds-gpio.txt deleted file mode 100644 index d21281b63d38..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-gpio.txt +++ /dev/null @@ -1,75 +0,0 @@ -LEDs connected to GPIO lines - -Required properties: -- compatible : should be "gpio-leds". - -Each LED is represented as a sub-node of the gpio-leds device. Each -node's name represents the name of the corresponding LED. - -LED sub-node properties: -- gpios : Should specify the LED's GPIO, see "gpios property" in - Documentation/devicetree/bindings/gpio/gpio.txt. Active low LEDs should be - indicated using flags in the GPIO specifier. -- function : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- color : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- label : (optional) - see Documentation/devicetree/bindings/leds/common.txt (deprecated) -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- default-state: (optional) The initial state of the LED. - see Documentation/devicetree/bindings/leds/common.txt -- retain-state-suspended: (optional) The suspend state can be retained.Such - as charge-led gpio. -- retain-state-shutdown: (optional) Retain the state of the LED on shutdown. - Useful in BMC systems, for example when the BMC is rebooted while the host - remains up. -- panic-indicator : (optional) - see Documentation/devicetree/bindings/leds/common.txt - -Examples: - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> - -leds { - compatible = "gpio-leds"; - led0 { - gpios = <&mcu_pio 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - function = LED_FUNCTION_DISK; - }; - - led1 { - gpios = <&mcu_pio 1 GPIO_ACTIVE_HIGH>; - /* Keep LED on if BIOS detected hardware fault */ - default-state = "keep"; - function = LED_FUNCTION_FAULT; - }; -}; - -run-control { - compatible = "gpio-leds"; - led0 { - gpios = <&mpc8572 6 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_RED>; - default-state = "off"; - }; - led1 { - gpios = <&mpc8572 7 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_GREEN>; - default-state = "on"; - }; -}; - -leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "max8903-charger-charging"; - retain-state-suspended; - function = LED_FUNCTION_CHARGE; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-gpio.yaml b/Documentation/devicetree/bindings/leds/leds-gpio.yaml new file mode 100644 index 000000000000..0e75b185dd19 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-gpio.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LEDs connected to GPIO lines + +maintainers: + - Jacek Anaszewski <jacek.anaszewski@gmail.com> + - Pavel Machek <pavel@ucw.cz> + +description: + Each LED is represented as a sub-node of the gpio-leds device. Each + node's name represents the name of the corresponding LED. + +properties: + compatible: + const: gpio-leds + +patternProperties: + # The first form is preferred, but fall back to just 'led' anywhere in the + # node name to at least catch some child nodes. + "(^led-[0-9a-f]$|led)": + type: object + + allOf: + - $ref: common.yaml# + + properties: + gpios: + maxItems: 1 + + retain-state-suspended: + description: + The suspend state can be retained.Such as charge-led gpio. + type: boolean + + retain-state-shutdown: + description: + Retain the state of the LED on shutdown. Useful in BMC systems, for + example when the BMC is rebooted while the host remains up. + type: boolean + + required: + - gpios + +additionalProperties: false + +examples: + - | + + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/leds/common.h> + + leds { + compatible = "gpio-leds"; + led-0 { + gpios = <&mcu_pio 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + function = LED_FUNCTION_DISK; + }; + + led-1 { + gpios = <&mcu_pio 1 GPIO_ACTIVE_HIGH>; + /* Keep LED on if BIOS detected hardware fault */ + default-state = "keep"; + function = LED_FUNCTION_FAULT; + }; + }; + + run-control { + compatible = "gpio-leds"; + led-0 { + gpios = <&mpc8572 6 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + default-state = "off"; + }; + led-1 { + gpios = <&mpc8572 7 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/leds/leds-lm3692x.txt b/Documentation/devicetree/bindings/leds/leds-lm3692x.txt index 4c2d923f8758..501468aa4d38 100644 --- a/Documentation/devicetree/bindings/leds/leds-lm3692x.txt +++ b/Documentation/devicetree/bindings/leds/leds-lm3692x.txt @@ -18,6 +18,10 @@ Required properties: Optional properties: - enable-gpios : gpio pin to enable/disable the device. - vled-supply : LED supply + - ti,ovp-microvolt: Overvoltage protection in + micro-volt, can be 17000000, 21000000, 25000000 or + 29000000. If ti,ovp-microvolt is not specified it + defaults to 29000000. Required child properties: - reg : 0 - Will enable all LED sync paths @@ -31,6 +35,8 @@ Optional child properties: - label : see Documentation/devicetree/bindings/leds/common.txt (deprecated) - linux,default-trigger : see Documentation/devicetree/bindings/leds/common.txt + - led-max-microamp : + see Documentation/devicetree/bindings/leds/common.txt Example: @@ -44,12 +50,14 @@ led-controller@36 { enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; vled-supply = <&vbatt>; + ti,ovp-microvolt = <29000000>; led@0 { reg = <0>; function = LED_FUNCTION_BACKLIGHT; color = <LED_COLOR_ID_WHITE>; linux,default-trigger = "backlight"; + led-max-microamp = <20000>; }; } diff --git a/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml new file mode 100644 index 000000000000..b50f4bcc98f1 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/rohm,bd71828-leds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD71828 Power Management Integrated Circuit LED driver + +maintainers: + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + +description: | + This module is part of the ROHM BD71828 MFD device. For more details + see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml. + + The LED controller is represented as a sub-node of the PMIC node on the device + tree. + + The device has two LED outputs referred as GRNLED and AMBLED in data-sheet. + +select: false + +properties: + compatible: + const: rohm,bd71828-leds + +patternProperties: + "^led-[1-2]$": + type: object + description: + Properties for a single LED. + properties: + #allOf: + #- $ref: "common.yaml#" + rohm,led-compatible: + description: LED identification string + allOf: + - $ref: "/schemas/types.yaml#/definitions/string" + - enum: + - bd71828-ambled + - bd71828-grnled + function: + description: + Purpose of LED as defined in dt-bindings/leds/common.h + $ref: "/schemas/types.yaml#/definitions/string" + color: + description: + LED colour as defined in dt-bindings/leds/common.h + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible diff --git a/Documentation/devicetree/bindings/leds/trigger-source.yaml b/Documentation/devicetree/bindings/leds/trigger-source.yaml new file mode 100644 index 000000000000..0618003e40bd --- /dev/null +++ b/Documentation/devicetree/bindings/leds/trigger-source.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/trigger-source.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trigger source providers + +maintainers: + - Jacek Anaszewski <jacek.anaszewski@gmail.com> + - Pavel Machek <pavel@ucw.cz> + +description: + Each trigger source provider should be represented by a device tree node. It + may be e.g. a USB port or an Ethernet device. + +properties: + '#trigger-source-cells': + description: + Number of cells in a source trigger. Typically 0 for nodes of simple + trigger sources (e.g. a specific USB port). + enum: [ 0, 1 ] + +... diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index 0278482af65c..beec612dbe6a 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -21,10 +21,11 @@ platforms. Usage: required Value type: <prop-encoded-array> Definition: must specify the base address and size of the global block + - clocks: - Usage: required if #clocks-cells property is present - Value type: <phandle> - Definition: phandle to the input PLL, which feeds the APCS mux/divider + Usage: required if #clock-names property is present + Value type: <phandle array> + Definition: phandles to the two parent clocks of the clock driver. - #mbox-cells: Usage: required @@ -36,6 +37,12 @@ platforms. Value type: <u32> Definition: as described in clock.txt, must be 0 +- clock-names: + Usage: required if the platform data based clock driver needs to + retrieve the parent clock names from device tree. + This will requires two mandatory clocks to be defined. + Value type: <string-array> + Definition: must be "pll" and "aux" = EXAMPLE The following example describes the APCS HMSS found in MSM8996 and part of the @@ -68,3 +75,14 @@ Below is another example of the APCS binding on MSM8916 platforms: clocks = <&a53pll>; #clock-cells = <0>; }; + +Below is another example of the APCS binding on QCS404 platforms: + + apcs_glb: mailbox@b011000 { + compatible = "qcom,qcs404-apcs-apps-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; + clock-names = "pll", "aux"; + #clock-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml index d3e423fcb6c2..9af873b43acd 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> description: |- The Allwinner A10 and later has a CMOS Sensor Interface to retrieve @@ -16,7 +16,15 @@ description: |- properties: compatible: - const: allwinner,sun7i-a20-csi0 + oneOf: + - const: allwinner,sun4i-a10-csi1 + - const: allwinner,sun7i-a20-csi0 + - items: + - const: allwinner,sun7i-a20-csi1 + - const: allwinner,sun4i-a10-csi1 + - items: + - const: allwinner,sun8i-r40-csi0 + - const: allwinner,sun7i-a20-csi0 reg: maxItems: 1 @@ -25,12 +33,16 @@ properties: maxItems: 1 clocks: + minItems: 2 + maxItems: 3 items: - description: The CSI interface clock - description: The CSI ISP clock - description: The CSI DRAM clock clock-names: + minItems: 2 + maxItems: 3 items: - const: bus - const: isp diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml index dea36d68cdbe..7838804700d6 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 Infrared Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> allOf: - $ref: "rc.yaml#" diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml new file mode 100644 index 000000000000..526593c8c614 --- /dev/null +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Video Engine Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + compatible: + enum: + - allwinner,sun4i-a10-video-engine + - allwinner,sun5i-a13-video-engine + - allwinner,sun7i-a20-video-engine + - allwinner,sun8i-a33-video-engine + - allwinner,sun8i-h3-video-engine + - allwinner,sun50i-a64-video-engine + - allwinner,sun50i-h5-video-engine + - allwinner,sun50i-h6-video-engine + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + - description: RAM Clock + + clock-names: + items: + - const: ahb + - const: mod + - const: ram + + resets: + maxItems: 1 + + allwinner,sram: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Phandle to the device SRAM + + memory-region: + description: + CMA pool to use for buffers allocation instead of the default + CMA pool. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - allwinner,sram + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/sun7i-a20-ccu.h> + #include <dt-bindings/reset/sun4i-a10-ccu.h> + + video-codec@1c0e000 { + compatible = "allwinner,sun7i-a20-video-engine"; + reg = <0x01c0e000 0x1000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_VE>; + allwinner,sram = <&ve_sram 1>; + }; + +... diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml new file mode 100644 index 000000000000..1fd9b5532a21 --- /dev/null +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 CMOS Sensor Interface (CSI) Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + compatible: + enum: + - allwinner,sun6i-a31-csi + - allwinner,sun8i-a83t-csi + - allwinner,sun8i-h3-csi + - allwinner,sun8i-v3s-csi + - allwinner,sun50i-a64-csi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + - description: DRAM Clock + + clock-names: + items: + - const: bus + - const: mod + - const: ram + + resets: + maxItems: 1 + + # See ./video-interfaces.txt for details + port: + type: object + + properties: + endpoint: + type: object + + properties: + remote-endpoint: true + + bus-width: + enum: [ 8, 10, 12, 16 ] + + pclk-sample: true + hsync-active: true + vsync-active: true + + required: + - bus-width + - remote-endpoint + + required: + - endpoint + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/sun8i-v3s-ccu.h> + #include <dt-bindings/reset/sun8i-v3s-ccu.h> + + csi1: csi@1cb4000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb4000 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", + "mod", + "ram"; + resets = <&ccu RST_BUS_CSI>; + + port { + /* Parallel bus endpoint */ + csi1_ep: endpoint { + remote-endpoint = <&adv7611_ep>; + bus-width = <16>; + + /* + * If hsync-active/vsync-active are missing, + * embedded BT.656 sync is used. + */ + hsync-active = <0>; /* Active low */ + vsync-active = <0>; /* Active low */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml new file mode 100644 index 000000000000..335717e15970 --- /dev/null +++ b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/amlogic,gx-vdec.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Video Decoder + +maintainers: + - Neil Armstrong <narmstrong@baylibre.com> + - Maxime Jourdan <mjourdan@baylibre.com> + +description: | + The video decoding IP lies within the DOS memory region, + except for the hardware bitstream parser that makes use of an undocumented + region. + + It makes use of the following blocks: + - ESPARSER is a bitstream parser that outputs to a VIFIFO. Further VDEC blocks + then feed from this VIFIFO. + - VDEC_1 can decode MPEG-1, MPEG-2, MPEG-4 part 2, MJPEG, H.263, H.264, VC-1. + - VDEC_HEVC can decode HEVC and VP9. + + Both VDEC_1 and VDEC_HEVC share the "vdec" IRQ and as such cannot run + concurrently. + +properties: + compatible: + oneOf: + - items: + - enum: + - amlogic,gxbb-vdec # GXBB (S905) + - amlogic,gxl-vdec # GXL (S905X, S905D) + - amlogic,gxm-vdec # GXM (S912) + - const: amlogic,gx-vdec + - enum: + - amlogic,g12a-vdec # G12A (S905X2, S905D2) + - amlogic,sm1-vdec # SM1 (S905X3, S905D3) + + interrupts: + minItems: 2 + + interrupt-names: + items: + - const: vdec + - const: esparser + + reg: + minItems: 2 + + reg-names: + items: + - const: dos + - const: esparser + + resets: + maxItems: 1 + + reset-names: + items: + - const: esparser + + clocks: + minItems: 4 + maxItems: 5 + + clock-names: + minItems: 4 + maxItems: 5 + items: + - const: dos_parser + - const: dos + - const: vdec_1 + - const: vdec_hevc + - const: vdec_hevcf + + amlogic,ao-sysctrl: + description: should point to the AOBUS sysctrl node + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + amlogic,canvas: + description: should point to a canvas provider node + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + +allOf: + - if: + properties: + compatible: + contains: + enum: + - amlogic,gx-vdec + + then: + properties: + clock-names: + maxItems: 4 + + - if: + properties: + compatible: + contains: + enum: + - amlogic,g12a-vdec + - amlogic,sm1-vdec + + then: + properties: + clock-names: + minItems: 5 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - amlogic,ao-sysctrl + - amlogic,canvas + +examples: + - | + vdec: video-decoder@c8820000 { + compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec"; + reg = <0xc8820000 0x10000>, <0xc110a580 0xe4>; + reg-names = "dos", "esparser"; + interrupts = <44>, <32>; + interrupt-names = "vdec", "esparser"; + clocks = <&clk_dos_parser> ,<&clk_dos>, <&clk_vdec_1>, <&clk_vdec_hevc>; + clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; + resets = <&reset_parser>; + reset-names = "esparser"; + amlogic,ao-sysctrl = <&sysctrl_AO>; + amlogic,canvas = <&canvas>; + }; diff --git a/Documentation/devicetree/bindings/media/amlogic,vdec.txt b/Documentation/devicetree/bindings/media/amlogic,vdec.txt deleted file mode 100644 index 9b6aace86ca7..000000000000 --- a/Documentation/devicetree/bindings/media/amlogic,vdec.txt +++ /dev/null @@ -1,72 +0,0 @@ -Amlogic Video Decoder -================================ - -The video decoding IP lies within the DOS memory region, -except for the hardware bitstream parser that makes use of an undocumented -region. - -It makes use of the following blocks: - -- ESPARSER is a bitstream parser that outputs to a VIFIFO. Further VDEC blocks -then feed from this VIFIFO. -- VDEC_1 can decode MPEG-1, MPEG-2, MPEG-4 part 2, MJPEG, H.263, H.264, VC-1. -- VDEC_HEVC can decode HEVC and VP9. - -Both VDEC_1 and VDEC_HEVC share the "vdec" IRQ and as such cannot run -concurrently. - -Device Tree Bindings: ---------------------- - -VDEC: Video Decoder --------------------------- - -Required properties: -- compatible: value should be different for each SoC family as : - - GXBB (S905) : "amlogic,gxbb-vdec" - - GXL (S905X, S905D) : "amlogic,gxl-vdec" - - GXM (S912) : "amlogic,gxm-vdec" - followed by the common "amlogic,gx-vdec" -- reg: base address and size of he following memory-mapped regions : - - dos - - esparser -- reg-names: should contain the names of the previous memory regions -- interrupts: should contain the following IRQs: - - vdec - - esparser -- interrupt-names: should contain the names of the previous interrupts -- amlogic,ao-sysctrl: should point to the AOBUS sysctrl node -- amlogic,canvas: should point to a canvas provider node -- clocks: should contain the following clocks : - - dos_parser - - dos - - vdec_1 - - vdec_hevc -- clock-names: should contain the names of the previous clocks -- resets: should contain the parser reset -- reset-names: should be "esparser" - -Example: - -vdec: video-codec@c8820000 { - compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec"; - reg = <0x0 0xc8820000 0x0 0x10000>, - <0x0 0xc110a580 0x0 0xe4>; - reg-names = "dos", "esparser"; - - interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&sysctrl_AO>; - amlogic,canvas = <&canvas>; - - clocks = <&clkc CLKID_DOS_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>; - clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; - - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; -}; diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt deleted file mode 100644 index 20c82fb0c343..000000000000 --- a/Documentation/devicetree/bindings/media/cedrus.txt +++ /dev/null @@ -1,57 +0,0 @@ -Device-tree bindings for the VPU found in Allwinner SoCs, referred to as the -Video Engine (VE) in Allwinner literature. - -The VPU can only access the first 256 MiB of DRAM, that are DMA-mapped starting -from the DRAM base. This requires specific memory allocation and handling. - -Required properties: -- compatible : must be one of the following compatibles: - - "allwinner,sun4i-a10-video-engine" - - "allwinner,sun5i-a13-video-engine" - - "allwinner,sun7i-a20-video-engine" - - "allwinner,sun8i-a33-video-engine" - - "allwinner,sun8i-h3-video-engine" - - "allwinner,sun50i-a64-video-engine" - - "allwinner,sun50i-h5-video-engine" - - "allwinner,sun50i-h6-video-engine" -- reg : register base and length of VE; -- clocks : list of clock specifiers, corresponding to entries in - the clock-names property; -- clock-names : should contain "ahb", "mod" and "ram" entries; -- resets : phandle for reset; -- interrupts : VE interrupt number; -- allwinner,sram : SRAM region to use with the VE. - -Optional properties: -- memory-region : CMA pool to use for buffers allocation instead of the - default CMA pool. - -Example: - -reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; - reusable; - linux,cma-default; - }; -}; - -video-codec@1c0e000 { - compatible = "allwinner,sun7i-a20-video-engine"; - reg = <0x01c0e000 0x1000>; - - clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - - resets = <&ccu RST_VE>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - allwinner,sram = <&ve_sram 1>; -}; diff --git a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt b/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt index 38941db23dd2..ce9a22689e53 100644 --- a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt +++ b/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt @@ -1,4 +1,4 @@ -Samsung S5P/EXYNOS SoC series JPEG codec +Samsung S5P/Exynos SoC series JPEG codec Required properties: diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt b/Documentation/devicetree/bindings/media/exynos5-gsc.txt index bc963a6d305a..1872688fa408 100644 --- a/Documentation/devicetree/bindings/media/exynos5-gsc.txt +++ b/Documentation/devicetree/bindings/media/exynos5-gsc.txt @@ -1,6 +1,6 @@ * Samsung Exynos5 G-Scaler device -G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs. +G-Scaler is used for scaling and color space conversion on Exynos5 SoCs. Required properties: - compatible: should be one of diff --git a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt index 13ebc0fac9ea..ca4cf774662e 100644 --- a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt +++ b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt @@ -1,7 +1,8 @@ Device-Tree bindings for hix5hd2 ir IP Required properties: - - compatible: Should contain "hisilicon,hix5hd2-ir". + - compatible: Should contain "hisilicon,hix5hd2-ir", or: + - "hisilicon,hi3796cv300-ir" for Hi3796CV300 IR device. - reg: Base physical address of the controller and length of memory mapped region. - interrupts: interrupt-specifier for the sole interrupt generated by diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.txt b/Documentation/devicetree/bindings/media/renesas,ceu.txt deleted file mode 100644 index 3e2a2652eb19..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,ceu.txt +++ /dev/null @@ -1,86 +0,0 @@ -Renesas Capture Engine Unit (CEU) ----------------------------------------------- - -The Capture Engine Unit is the image capture interface found in the Renesas -SH Mobile, R-Mobile and RZ SoCs. - -The interface supports a single parallel input with data bus width of 8 or 16 -bits. - -Required properties: -- compatible: Shall be one of the following values: - "renesas,r7s72100-ceu" for CEU units found in RZ/A1H and RZ/A1M SoCs - "renesas,r8a7740-ceu" for CEU units found in R-Mobile A1 R8A7740 SoCs -- reg: Registers address base and size. -- interrupts: The interrupt specifier. - -The CEU supports a single parallel input and should contain a single 'port' -subnode with a single 'endpoint'. Connection to input devices are modeled -according to the video interfaces OF bindings specified in: -[1] Documentation/devicetree/bindings/media/video-interfaces.txt - -Optional endpoint properties applicable to parallel input bus described in -the above mentioned "video-interfaces.txt" file are supported. - -- hsync-active: See [1] for description. If property is not present, - default is active high. -- vsync-active: See [1] for description. If property is not present, - default is active high. -- bus-width: See [1] for description. Accepted values are '8' and '16'. - If property is not present, default is '8'. -- field-even-active: See [1] for description. If property is not present, - an even field is identified by a logic 0 (active-low signal). - -Example: - -The example describes the connection between the Capture Engine Unit and an -OV7670 image sensor connected to i2c1 interface. - -ceu: ceu@e8210000 { - reg = <0xe8210000 0x209c>; - compatible = "renesas,r7s72100-ceu"; - interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&vio_pins>; - - status = "okay"; - - port { - ceu_in: endpoint { - remote-endpoint = <&ov7670_out>; - - hsync-active = <1>; - vsync-active = <0>; - }; - }; -}; - -i2c1: i2c@fcfee400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - - clock-frequency = <100000>; - - ov7670: camera@21 { - compatible = "ovti,ov7670"; - reg = <0x21>; - - pinctrl-names = "default"; - pinctrl-0 = <&vio_pins>; - - reset-gpios = <&port3 11 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&port3 12 GPIO_ACTIVE_HIGH>; - - port { - ov7670_out: endpoint { - remote-endpoint = <&ceu_in>; - - hsync-active = <1>; - vsync-active = <0>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.yaml b/Documentation/devicetree/bindings/media/renesas,ceu.yaml new file mode 100644 index 000000000000..8e9251a0f9ef --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,ceu.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/renesas,ceu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Capture Engine Unit (CEU) Bindings + +maintainers: + - Jacopo Mondi <jacopo+renesas@jmondi.org> + - linux-renesas-soc@vger.kernel.org + +description: |+ + The Capture Engine Unit is the image capture interface found in the Renesas SH + Mobile, R-Mobile and RZ SoCs. The interface supports a single parallel input + with data bus width of 8 or 16 bits. + +properties: + compatible: + enum: + - renesas,r7s72100-ceu + - renesas,r8a7740-ceu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + port: + type: object + additionalProperties: false + + properties: + endpoint: + type: object + additionalProperties: false + + # Properties described in + # Documentation/devicetree/bindings/media/video-interfaces.txt + properties: + remote-endpoint: true + hsync-active: true + vsync-active: true + field-even-active: false + bus-width: + enum: [8, 16] + default: 8 + + required: + - remote-endpoint + + required: + - endpoint + +required: + - compatible + - reg + - interrupts + - port + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + ceu: ceu@e8210000 { + reg = <0xe8210000 0x209c>; + compatible = "renesas,r7s72100-ceu"; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + + port { + ceu_in: endpoint { + remote-endpoint = <&ov7670_out>; + hsync-active = <1>; + vsync-active = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/renesas,csi2.txt b/Documentation/devicetree/bindings/media/renesas,csi2.txt deleted file mode 100644 index 2da6f60b2b56..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,csi2.txt +++ /dev/null @@ -1,107 +0,0 @@ -Renesas R-Car MIPI CSI-2 ------------------------- - -The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the -Renesas R-Car and RZ/G2 family of devices. It is used in conjunction with the -R-Car VIN module, which provides the video capture capabilities. - -Mandatory properties --------------------- - - compatible: Must be one or more of the following - - "renesas,r8a774a1-csi2" for the R8A774A1 device. - - "renesas,r8a774b1-csi2" for the R8A774B1 device. - - "renesas,r8a774c0-csi2" for the R8A774C0 device. - - "renesas,r8a7795-csi2" for the R8A7795 device. - - "renesas,r8a7796-csi2" for the R8A7796 device. - - "renesas,r8a77965-csi2" for the R8A77965 device. - - "renesas,r8a77970-csi2" for the R8A77970 device. - - "renesas,r8a77980-csi2" for the R8A77980 device. - - "renesas,r8a77990-csi2" for the R8A77990 device. - - - reg: the register base and size for the device registers - - interrupts: the interrupt for the device - - clocks: A phandle + clock specifier for the module clock - - resets: A phandle + reset specifier for the module reset - -The device node shall contain two 'port' child nodes according to the -bindings defined in Documentation/devicetree/bindings/media/ -video-interfaces.txt. port@0 shall connect to the CSI-2 source. port@1 -shall connect to all the R-Car VIN modules that have a hardware -connection to the CSI-2 receiver. - -- port@0- Video source (mandatory) - - endpoint@0 - sub-node describing the endpoint that is the video source - -- port@1 - VIN instances (optional) - - One endpoint sub-node for every R-Car VIN instance which is connected - to the R-Car CSI-2 receiver. - -Example: - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7796-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 714>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - - csi20_in: endpoint@0 { - reg = <0>; - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&adv7482_txb>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/renesas,csi2.yaml b/Documentation/devicetree/bindings/media/renesas,csi2.yaml new file mode 100644 index 000000000000..408442a0c389 --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,csi2.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (C) 2020 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/renesas,csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car MIPI CSI-2 receiver + +maintainers: + - Niklas Söderlund <niklas.soderlund@ragnatech.se> + +description: + The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the + Renesas R-Car and RZ/G2 family of devices. It is used in conjunction with the + R-Car VIN module, which provides the video capture capabilities. + +properties: + compatible: + items: + - enum: + - renesas,r8a774a1-csi2 # RZ/G2M + - renesas,r8a774b1-csi2 # RZ/G2N + - renesas,r8a774c0-csi2 # RZ/G2E + - renesas,r8a7795-csi2 # R-Car H3 + - renesas,r8a7796-csi2 # R-Car M3-W + - renesas,r8a77965-csi2 # R-Car M3-N + - renesas,r8a77970-csi2 # R-Car V3M + - renesas,r8a77980-csi2 # R-Car V3H + - renesas,r8a77990-csi2 # R-Car E3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + ports: + type: object + description: + A node containing input and output port nodes with endpoint definitions + as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + port@0: + type: object + description: + Input port node, single endpoint describing the CSI-2 transmitter. + + properties: + reg: + const: 0 + + endpoint: + type: object + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + maxItems: 1 + + remote-endpoint: true + + required: + - clock-lanes + - data-lanes + - remote-endpoint + + additionalProperties: false + + additionalProperties: false + + port@1: + type: object + description: + Output port node, multiple endpoints describing all the R-Car VIN + modules connected the CSI-2 receiver. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + const: 1 + + patternProperties: + "^endpoint@[0-9a-f]$": + type: object + + properties: + reg: + maxItems: 1 + + remote-endpoint: true + + required: + - reg + - remote-endpoint + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - resets + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7796-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7796-sysc.h> + + csi20: csi2@fea80000 { + compatible = "renesas,r8a7796-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 714>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi20_in: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&adv7482_txb>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/renesas,vin.txt b/Documentation/devicetree/bindings/media/renesas,vin.txt index e30b0d4eefdd..5eefd62ac5c5 100644 --- a/Documentation/devicetree/bindings/media/renesas,vin.txt +++ b/Documentation/devicetree/bindings/media/renesas,vin.txt @@ -13,6 +13,7 @@ on Gen3 and RZ/G2 platforms to a CSI-2 receiver. - "renesas,vin-r8a7743" for the R8A7743 device - "renesas,vin-r8a7744" for the R8A7744 device - "renesas,vin-r8a7745" for the R8A7745 device + - "renesas,vin-r8a77470" for the R8A77470 device - "renesas,vin-r8a774a1" for the R8A774A1 device - "renesas,vin-r8a774b1" for the R8A774B1 device - "renesas,vin-r8a774c0" for the R8A774C0 device @@ -41,9 +42,6 @@ on Gen3 and RZ/G2 platforms to a CSI-2 receiver. - interrupts: the interrupt for the device - clocks: Reference to the parent clock -Additionally, an alias named vinX will need to be created to specify -which video input device this is. - The per-board settings for Gen2 and RZ/G1 platforms: - port - sub-node describing a single endpoint connected to the VIN diff --git a/Documentation/devicetree/bindings/media/samsung-fimc.txt b/Documentation/devicetree/bindings/media/samsung-fimc.txt index 48c599dacbdf..f91b9dc80eb3 100644 --- a/Documentation/devicetree/bindings/media/samsung-fimc.txt +++ b/Documentation/devicetree/bindings/media/samsung-fimc.txt @@ -1,4 +1,4 @@ -Samsung S5P/EXYNOS SoC Camera Subsystem (FIMC) +Samsung S5P/Exynos SoC Camera Subsystem (FIMC) ---------------------------------------------- The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices diff --git a/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt b/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt index be45f0b1a449..a4149c9434ea 100644 --- a/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt +++ b/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt @@ -1,4 +1,4 @@ -Samsung S5P/EXYNOS SoC series MIPI CSI-2 receiver (MIPI CSIS) +Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS) ------------------------------------------------------------- Required properties: diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt deleted file mode 100644 index a2e3e56f0257..000000000000 --- a/Documentation/devicetree/bindings/media/sun6i-csi.txt +++ /dev/null @@ -1,61 +0,0 @@ -Allwinner V3s Camera Sensor Interface -------------------------------------- - -Allwinner V3s SoC features a CSI module(CSI1) with parallel interface. - -Required properties: - - compatible: value must be one of: - * "allwinner,sun6i-a31-csi" - * "allwinner,sun8i-a83t-csi" - * "allwinner,sun8i-h3-csi" - * "allwinner,sun8i-v3s-csi" - * "allwinner,sun50i-a64-csi" - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the CSI - * bus: the CSI interface clock - * mod: the CSI module clock - * ram: the CSI DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset line driving the CSI - -The CSI node should contain one 'port' child node with one child 'endpoint' -node, according to the bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Endpoint node properties for CSI ---------------------------------- -See the video-interfaces.txt for a detailed description of these properties. -- remote-endpoint : (required) a phandle to the bus receiver's endpoint - node -- bus-width: : (required) must be 8, 10, 12 or 16 -- pclk-sample : (optional) (default: sample on falling edge) -- hsync-active : (required; parallel-only) -- vsync-active : (required; parallel-only) - -Example: - -csi1: csi@1cb4000 { - compatible = "allwinner,sun8i-v3s-csi"; - reg = <0x01cb4000 0x1000>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI1_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - - port { - /* Parallel bus endpoint */ - csi1_ep: endpoint { - remote-endpoint = <&adv7611_ep>; - bus-width = <16>; - - /* If hsync-active/vsync-active are missing, - embedded BT.656 sync is used */ - hsync-active = <0>; /* Active low */ - vsync-active = <0>; /* Active low */ - pclk-sample = <1>; /* Rising */ - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/ti,cal.yaml b/Documentation/devicetree/bindings/media/ti,cal.yaml new file mode 100644 index 000000000000..1ea784179536 --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,cal.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,cal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) Device Tree Bindings + +maintainers: + - Benoit Parrot <bparrot@ti.com> + +description: |- + The Camera Adaptation Layer (CAL) is a key component for image capture + applications. The capture module provides the system interface and the + processing capability to connect CSI2 image-sensor modules to the + DRA72x device. + + CAL supports 2 camera port nodes on MIPI bus. Each CSI2 camera port nodes + should contain a 'port' child node with child 'endpoint' node. Please + refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + +properties: + compatible: + enum: + # for DRA72 controllers + - ti,dra72-cal + # for DRA72 controllers pre ES2.0 + - ti,dra72-pre-es2-cal + # for DRA76 controllers + - ti,dra76-cal + # for AM654 controllers + - ti,am654-cal + + reg: + minItems: 2 + items: + - description: The CAL main register region + - description: The RX Core0 (DPHY0) register region + - description: The RX Core1 (DPHY1) register region + + reg-names: + minItems: 2 + items: + - const: cal_top + - const: cal_rx_core0 + - const: cal_rx_core1 + + interrupts: + maxItems: 1 + + ti,camerrx-control: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + phandle to the device control module and offset to the + control_camerarx_core register + + clocks: + maxItems: 1 + + clock-names: + const: fck + + power-domains: + description: + List of phandle and PM domain specifier as documented in + Documentation/devicetree/bindings/power/power_domain.txt + maxItems: 1 + + # See ./video-interfaces.txt for details + ports: + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + additionalProperties: false + + properties: + reg: + const: 0 + description: CSI2 Port #0 + + patternProperties: + endpoint: + type: object + additionalProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + remote-endpoint: true + + required: + - reg + + port@1: + type: object + additionalProperties: false + + properties: + reg: + const: 1 + description: CSI2 Port #1 + + patternProperties: + endpoint: + type: object + additionalProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + remote-endpoint: true + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - port@0 + +required: + - compatible + - reg + - reg-names + - interrupts + - ti,camerrx-control + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + cal: cal@4845b000 { + compatible = "ti,dra72-cal"; + reg = <0x4845B000 0x400>, + <0x4845B800 0x40>, + <0x4845B900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + ti,camerrx-control = <&scm_conf 0xE94>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + csi2_phy0: endpoint { + remote-endpoint = <&csi2_cam0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + i2c5: i2c@4807c000 { + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + camera-sensor@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2_phy0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/ti-cal.txt b/Documentation/devicetree/bindings/media/ti-cal.txt deleted file mode 100644 index ae9b52f37576..000000000000 --- a/Documentation/devicetree/bindings/media/ti-cal.txt +++ /dev/null @@ -1,72 +0,0 @@ -Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) ------------------------------------------------------- - -The Camera Adaptation Layer (CAL) is a key component for image capture -applications. The capture module provides the system interface and the -processing capability to connect CSI2 image-sensor modules to the -DRA72x device. - -Required properties: -- compatible: must be "ti,dra72-cal" -- reg: CAL Top level, Receiver Core #0, Receiver Core #1 and Camera RX - control address space -- reg-names: cal_top, cal_rx_core0, cal_rx_core1, and camerrx_control - registers -- interrupts: should contain IRQ line for the CAL; - -CAL supports 2 camera port nodes on MIPI bus. Each CSI2 camera port nodes -should contain a 'port' child node with child 'endpoint' node. Please -refer to the bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - cal: cal@4845b000 { - compatible = "ti,dra72-cal"; - ti,hwmods = "cal"; - reg = <0x4845B000 0x400>, - <0x4845B800 0x40>, - <0x4845B900 0x40>, - <0x4A002e94 0x4>; - reg-names = "cal_top", - "cal_rx_core0", - "cal_rx_core1", - "camerrx_control"; - interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi2_0: port@0 { - reg = <0>; - endpoint { - slave-mode; - remote-endpoint = <&ar0330_1>; - }; - }; - csi2_1: port@1 { - reg = <1>; - }; - }; - }; - - i2c5: i2c@4807c000 { - ar0330@10 { - compatible = "ti,ar0330"; - reg = <0x10>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ar0330_1: endpoint { - reg = <0>; - clock-lanes = <1>; - data-lanes = <0 2 3 4>; - remote-endpoint = <&csi2_0>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml new file mode 100644 index 000000000000..c9e6c22cb5be --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX8M DDR Controller + +maintainers: + - Leonard Crestez <leonard.crestez@nxp.com> + +description: + The DDRC block is integrated in i.MX8M for interfacing with DDR based + memories. + + It supports switching between different frequencies at runtime but during + this process RAM itself becomes briefly inaccessible so actual frequency + switching is implemented by TF-A code which runs from a SRAM area. + + The Linux driver for the DDRC doesn't even map registers (they're included + for the sake of "describing hardware"), it mostly just exposes firmware + capabilities through standard Linux mechanism like devfreq and OPP tables. + +properties: + compatible: + items: + - enum: + - fsl,imx8mn-ddrc + - fsl,imx8mm-ddrc + - fsl,imx8mq-ddrc + - const: fsl,imx8m-ddrc + + reg: + maxItems: 1 + description: + Base address and size of DDRC CTL area. + This is not currently mapped by the imx8m-ddrc driver. + + clocks: + maxItems: 4 + + clock-names: + items: + - const: core + - const: pll + - const: alt + - const: apb + + operating-points-v2: true + opp-table: true + +required: + - reg + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + operating-points-v2 = <&ddrc_opp_table>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 30d9fb193d7f..22a94b6fdbde 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -60,7 +60,8 @@ patternProperties: maximum: 1066000000 nvidia,emem-configuration: - $ref: /schemas/types.yaml#/definitions/uint32-array + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array description: | Values to be written to the EMEM register block. See section "15.6.1 MC Registers" in the TRM. diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index 7fe0ca14e324..e4135bac6957 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -56,7 +56,8 @@ patternProperties: maximum: 900000000 nvidia,emc-auto-cal-interval: - $ref: /schemas/types.yaml#/definitions/uint32 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 description: Pad calibration interval in microseconds. minimum: 0 @@ -78,7 +79,8 @@ patternProperties: Mode Register 0. nvidia,emc-zcal-cnt-long: - $ref: /schemas/types.yaml#/definitions/uint32 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 description: Number of EMC clocks to wait before issuing any commands after sending ZCAL_MRW_CMD. @@ -96,7 +98,8 @@ patternProperties: FBIO "read" FIFO periodic resetting enabled. nvidia,emc-configuration: - $ref: /schemas/types.yaml#/definitions/uint32-array + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array description: EMC timing characterization data. These are the registers (see section "18.13.2 EMC Registers" in the TRM) whose values diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml index 84fd57bcf0dc..4b9196c83291 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -77,7 +77,8 @@ patternProperties: maximum: 900000000 nvidia,emem-configuration: - $ref: /schemas/types.yaml#/definitions/uint32-array + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array description: | Values to be written to the EMEM register block. See section "18.13.1 MC Registers" in the TRM. diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt index b6bc30d7777e..5c6eabeed341 100644 --- a/Documentation/devicetree/bindings/mfd/ab8500.txt +++ b/Documentation/devicetree/bindings/mfd/ab8500.txt @@ -1,7 +1,7 @@ * AB8500 Multi-Functional Device (MFD) Required parent device properties: -- compatible : contains "stericsson,ab8500"; +- compatible : contains "stericsson,ab8500" or "stericsson,ab8505"; - interrupts : contains the IRQ line for the AB8500 - interrupt-controller : describes the AB8500 as an Interrupt Controller (has its own domain) - #interrupt-cells : should be 2, for 2-cell format @@ -49,11 +49,13 @@ ab8500-charger : : vddadc : Charger interface : CH_WD_EXP : : Charger watchdog detected ab8500-gpadc : HW_CONV_END : vddadc : Analogue to Digital Converter SW_CONV_END : : -ab8500-gpio : : : GPIO Controller +ab8500-gpio : : : GPIO Controller (AB8500) +ab8505-gpio : : : GPIO Controller (AB8505) ab8500-ponkey : ONKEY_DBF : : Power-on Key ONKEY_DBR : : ab8500-pwm : : : Pulse Width Modulator -ab8500-regulator : : : Regulators +ab8500-regulator : : : Regulators (AB8500) +ab8505-regulator : : : Regulators (AB8505) ab8500-rtc : 60S : : Real Time Clock : ALARM : : ab8500-sysctrl : : : System Control diff --git a/Documentation/devicetree/bindings/mfd/allwinner,sun4i-a10-ts.yaml b/Documentation/devicetree/bindings/mfd/allwinner,sun4i-a10-ts.yaml index 4b1a09acb98b..39afacc447b2 100644 --- a/Documentation/devicetree/bindings/mfd/allwinner,sun4i-a10-ts.yaml +++ b/Documentation/devicetree/bindings/mfd/allwinner,sun4i-a10-ts.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 Resistive Touchscreen Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#thermal-sensor-cells": diff --git a/Documentation/devicetree/bindings/mfd/allwinner,sun6i-a31-prcm.yaml b/Documentation/devicetree/bindings/mfd/allwinner,sun6i-a31-prcm.yaml new file mode 100644 index 000000000000..d131759ccaf3 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/allwinner,sun6i-a31-prcm.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 PRCM Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + compatible: + const: allwinner,sun6i-a31-prcm + + reg: + maxItems: 1 + +patternProperties: + "^.*_(clk|rst)$": + type: object + + properties: + compatible: + enum: + - allwinner,sun4i-a10-mod0-clk + - allwinner,sun6i-a31-apb0-clk + - allwinner,sun6i-a31-apb0-gates-clk + - allwinner,sun6i-a31-ar100-clk + - allwinner,sun6i-a31-clock-reset + - fixed-factor-clock + + allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-apb0-clk + + then: + properties: + "#clock-cells": + const: 0 + + # Already checked in the main schema + compatible: true + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + phandle: true + + required: + - "#clock-cells" + - compatible + - clocks + - clock-output-names + + additionalProperties: false + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-apb0-gates-clk + + then: + properties: + "#clock-cells": + const: 1 + description: > + This additional argument passed to that clock is the + offset of the bit controlling this particular gate in + the register. + + # Already checked in the main schema + compatible: true + + clocks: + maxItems: 1 + + clock-output-names: + minItems: 1 + maxItems: 32 + + phandle: true + + required: + - "#clock-cells" + - compatible + - clocks + - clock-output-names + + additionalProperties: false + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-ar100-clk + + then: + properties: + "#clock-cells": + const: 0 + + # Already checked in the main schema + compatible: true + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming + order. + + clock-output-names: + maxItems: 1 + + phandle: true + + required: + - "#clock-cells" + - compatible + - clocks + - clock-output-names + + additionalProperties: false + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-clock-reset + + then: + properties: + "#reset-cells": + const: 1 + + # Already checked in the main schema + compatible: true + + phandle: true + + required: + - "#reset-cells" + - compatible + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun6i-a31-ccu.h> + + prcm@1f01400 { + compatible = "allwinner,sun6i-a31-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "allwinner,sun6i-a31-ar100-clk"; + #clock-cells = <0>; + clocks = <&rtc 0>, <&osc24M>, + <&ccu CLK_PLL_PERIPH>, + <&ccu CLK_PLL_PERIPH>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun6i-a31-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun6i-a31-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_ir", + "apb0_timer", "apb0_p2wi", + "apb0_uart", "apb0_1wire", + "apb0_i2c"; + }; + + ir_clk: ir_clk { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + clocks = <&rtc 0>, <&osc24M>; + clock-output-names = "ir"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mfd/allwinner,sun8i-a23-prcm.yaml b/Documentation/devicetree/bindings/mfd/allwinner,sun8i-a23-prcm.yaml new file mode 100644 index 000000000000..aa5e683b236c --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/allwinner,sun8i-a23-prcm.yaml @@ -0,0 +1,200 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A23 PRCM Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + compatible: + const: allwinner,sun8i-a23-prcm + + reg: + maxItems: 1 + +patternProperties: + "^.*(clk|rst|codec).*$": + type: object + + properties: + compatible: + enum: + - fixed-factor-clock + - allwinner,sun8i-a23-apb0-clk + - allwinner,sun8i-a23-apb0-gates-clk + - allwinner,sun6i-a31-clock-reset + - allwinner,sun8i-a23-codec-analog + + required: + - compatible + + allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-a23-apb0-clk + + then: + properties: + "#clock-cells": + const: 0 + + # Already checked in the main schema + compatible: true + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + phandle: true + + required: + - "#clock-cells" + - compatible + - clocks + - clock-output-names + + additionalProperties: false + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-a23-apb0-gates-clk + + then: + properties: + "#clock-cells": + const: 1 + description: > + This additional argument passed to that clock is the + offset of the bit controlling this particular gate in + the register. + + # Already checked in the main schema + compatible: true + + clocks: + maxItems: 1 + + clock-output-names: + minItems: 1 + maxItems: 32 + + phandle: true + + required: + - "#clock-cells" + - compatible + - clocks + - clock-output-names + + additionalProperties: false + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-clock-reset + + then: + properties: + "#reset-cells": + const: 1 + + # Already checked in the main schema + compatible: true + + phandle: true + + required: + - "#reset-cells" + - compatible + + additionalProperties: false + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-a23-codec-analog + + then: + properties: + # Already checked in the main schema + compatible: true + + phandle: true + + required: + - compatible + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + prcm@1f01400 { + compatible = "allwinner,sun8i-a23-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun8i-a23-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun8i-a23-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_timer", + "apb0_rsb", "apb0_uart", + "apb0_i2c"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + + codec_analog: codec-analog { + compatible = "allwinner,sun8i-a23-codec-analog"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt index 699fd3c9ace8..a09133066aff 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-usart.txt @@ -1,10 +1,13 @@ * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) Required properties for USART: -- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu" - The compatible <chip> indicated will be the first SoC to support an - additional mode or an USART new feature. - For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart" +- compatible: Should be one of the following: + - "atmel,at91rm9200-usart" + - "atmel,at91sam9260-usart" + - "microchip,sam9x60-usart" + - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart" + - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart" + - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart" - reg: Should contain registers location and length - interrupts: Should contain interrupt - clock-names: tuple listing input clock names. diff --git a/Documentation/devicetree/bindings/mfd/da9062.txt b/Documentation/devicetree/bindings/mfd/da9062.txt index bc4b59de6a55..857af982c88f 100644 --- a/Documentation/devicetree/bindings/mfd/da9062.txt +++ b/Documentation/devicetree/bindings/mfd/da9062.txt @@ -13,6 +13,7 @@ da9062-rtc : : Real-Time Clock da9062-onkey : : On Key da9062-watchdog : : Watchdog Timer da9062-thermal : : Thermal +da9062-gpio : : GPIOs The DA9061 PMIC consists of: @@ -38,6 +39,15 @@ Required properties: See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for further information on IRQ bindings. +Optional properties: + +- gpio-controller : Marks the device as a gpio controller. +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify the gpio polarity. + +See Documentation/devicetree/bindings/gpio/gpio.txt for further information on +GPIO bindings. + Sub-nodes: - regulators : This node defines the settings for the LDOs and BUCKs. diff --git a/Documentation/devicetree/bindings/mfd/max14577.txt b/Documentation/devicetree/bindings/mfd/max14577.txt index fc6f0f4e8beb..92070b346756 100644 --- a/Documentation/devicetree/bindings/mfd/max14577.txt +++ b/Documentation/devicetree/bindings/mfd/max14577.txt @@ -5,6 +5,8 @@ Battery Charger and SFOUT LDO output for powering USB devices. It is interfaced to host controller using I2C. MAX77836 additionally contains PMIC (with two LDO regulators) and Fuel Gauge. +For the description of Fuel Gauge low SOC alert interrupt see: +../power/supply/max17040_battery.txt Required properties: diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml new file mode 100644 index 000000000000..4fbb9e734284 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rohm,bd71828-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD71828 Power Management Integrated Circuit bindings + +maintainers: + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + +description: | + BD71828GW is a single-chip power management IC for battery-powered portable + devices. The IC integrates 7 buck converters, 7 LDOs, and a 1500 mA + single-cell linear charger. Also included is a Coulomb counter, a real-time + clock (RTC), and a 32.768 kHz clock gate. + +properties: + compatible: + const: rohm,bd71828 + + reg: + description: + I2C slave address. + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + The first cell is the pin number and the second cell is used to specify + flags. See ../gpio/gpio.txt for more information. + + clocks: + maxItems: 1 + + "#clock-cells": + const: 0 + + rohm,charger-sense-resistor-ohms: + minimum: 10000000 + maximum: 50000000 + description: | + BD71827 and BD71828 have SAR ADC for measuring charging currents. + External sense resistor (RSENSE in data sheet) should be used. If some + other but 30MOhm resistor is used the resistance value should be given + here in Ohms. + + regulators: + $ref: ../regulator/rohm,bd71828-regulator.yaml + description: + List of child nodes that specify the regulators. + + leds: + $ref: ../leds/rohm,bd71828-leds.yaml + + gpio-reserved-ranges: + description: | + Usage of BD71828 GPIO pins can be changed via OTP. This property can be + used to mark the pins which should not be configured for GPIO. Please see + the ../gpio/gpio.txt for more information. + +required: + - compatible + - reg + - interrupts + - clocks + - "#clock-cells" + - regulators + - gpio-controller + - "#gpio-cells" + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/leds/common.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + pmic: pmic@4b { + compatible = "rohm,bd71828"; + reg = <0x4b>; + + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + clocks = <&osc 0>; + #clock-cells = <0>; + clock-output-names = "bd71828-32k-out"; + + gpio-controller; + #gpio-cells = <2>; + gpio-reserved-ranges = <0 1>, <2 1>; + + rohm,charger-sense-resistor-ohms = <10000000>; + + regulators { + buck1: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <2500>; + }; + buck2: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <2500>; + }; + buck3: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2000000>; + }; + buck4: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + }; + buck5: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + buck6: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <2500>; + }; + buck7: BUCK7 { + regulator-name = "buck7"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <2500>; + }; + ldo1: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + ldo2: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + ldo3: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + ldo4: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + ldo5: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + ldo6: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + ldo7_reg: LDO7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + }; + + leds { + compatible = "rohm,bd71828-leds"; + + led-1 { + rohm,led-compatible = "bd71828-grnled"; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; + }; + led-2 { + rohm,led-compatible = "bd71828-ambled"; + function = LED_FUNCTION_CHARGING; + color = <LED_COLOR_ID_AMBER>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt deleted file mode 100644 index daa091c2e67b..000000000000 --- a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt +++ /dev/null @@ -1,59 +0,0 @@ -* Allwinner PRCM (Power/Reset/Clock Management) Multi-Functional Device - -PRCM is an MFD device exposing several Power Management related devices -(like clks and reset controllers). - -Required properties: - - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm" - - reg: The PRCM registers range - -The prcm node may contain several subdevices definitions: - - see Documentation/devicetree/bindings/clock/sunxi.txt for clock devices - - see Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt for reset - controller devices - - -Example: - - prcm: prcm@1f01400 { - compatible = "allwinner,sun6i-a31-prcm"; - reg = <0x01f01400 0x200>; - - /* Put subdevices here */ - ar100: ar100_clk { - compatible = "allwinner,sun6i-a31-ar100-clk"; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&ar100_div>; - clock-output-names = "ahb0"; - }; - - apb0: apb0_clk { - compatible = "allwinner,sun6i-a31-apb0-clk"; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: apb0_gates_clk { - compatible = "allwinner,sun6i-a31-apb0-gates-clk"; - #clock-cells = <1>; - clocks = <&apb0>; - clock-output-names = "apb0_pio", "apb0_ir", - "apb0_timer01", "apb0_p2wi", - "apb0_uart", "apb0_1wire", - "apb0_i2c"; - }; - - apb0_rst: apb0_rst { - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/tps6105x.txt b/Documentation/devicetree/bindings/mfd/tps6105x.txt index 93602c7a19c8..dc448a9d5b4d 100644 --- a/Documentation/devicetree/bindings/mfd/tps6105x.txt +++ b/Documentation/devicetree/bindings/mfd/tps6105x.txt @@ -7,11 +7,56 @@ Required properties: - compatible: "ti,tps61050" or "ti,tps61052" - reg: Specifies the I2C slave address -Example: +Optional sub-node: + +This subnode selects the chip's operational mode. +There can be at most one single available subnode. + +- regulator: presence of this sub-node puts the chip in regulator mode. + see ../regulator/regulator.yaml + +- led: presence of this sub-node puts the chip in led mode. + Optional properties: + - function : see ../leds/common.txt + - color : see ../leds/common.txt + - label : see ../leds/common.txt + (deprecated) + +Example (GPIO operation only): + +i2c0 { + tps61052@33 { + compatible = "ti,tps61052"; + reg = <0x33>; + }; +}; + +Example (GPIO + regulator operation): i2c0 { tps61052@33 { compatible = "ti,tps61052"; reg = <0x33>; + + regulator { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; + +Example (GPIO + led operation): + +#include <dt-bindings/leds/common.h> + +i2c0 { + tps61052@33 { + compatible = "ti,tps61052"; + reg = <0x33>; + + led { + color = <LED_COLOR_ID_WHITE>; + }; }; }; diff --git a/Documentation/devicetree/bindings/mfd/xylon,logicvc.yaml b/Documentation/devicetree/bindings/mfd/xylon,logicvc.yaml new file mode 100644 index 000000000000..abc9937506e0 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/xylon,logicvc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Bootlin +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mfd/xylon,logicvc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Xylon LogiCVC multi-function device + +maintainers: + - Paul Kocialkowski <paul.kocialkowski@bootlin.com> + +description: | + The LogiCVC is a display controller that also contains a GPIO controller. + As a result, a multi-function device is exposed as parent of the display + and GPIO blocks. + +properties: + compatible: + items: + - enum: + - xylon,logicvc-3.02.a + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +select: + properties: + compatible: + contains: + enum: + - xylon,logicvc-3.02.a + + required: + - compatible + +required: + - compatible + - reg + +examples: + - | + logicvc: logicvc@43c00000 { + compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd"; + reg = <0x43c00000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml new file mode 100644 index 000000000000..78dcf6ef3883 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic XBurst based Platforms Device Tree Bindings + +maintainers: + - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> +description: | + Devices with a Ingenic XBurst CPU shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Qi Hardware Ben NanoNote + items: + - const: qi,lb60 + + - description: Game Consoles Worldwide GCW Zero + items: + - const: gcw,zero + + - description: MIPS Creator CI20 + items: + - const: img,ci20 + + - description: YSH & ATIL General Board CU Neo + items: + - const: yna,cu1000-neo +... diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 64bca41031d5..e82c9a07b6fb 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -11,7 +11,7 @@ allOf: maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#address-cells": true diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt index 733b64a4d8eb..ae2074184528 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt @@ -11,28 +11,43 @@ Required properties: - compatible: should be one of the following - "brcm,bcm7425-sdhci" - "brcm,bcm7445-sdhci" + - "brcm,bcm7216-sdhci" Refer to clocks/clock-bindings.txt for generic clock consumer properties. Example: - sdhci@f03e0100 { - compatible = "brcm,bcm7425-sdhci"; - reg = <0xf03e0000 0x100>; - interrupts = <0x0 0x26 0x0>; - sdhci,auto-cmd12; - clocks = <&sw_sdio>; + sdhci@84b0000 { sd-uhs-sdr50; sd-uhs-ddr50; + sd-uhs-sdr104; + sdhci,auto-cmd12; + compatible = "brcm,bcm7216-sdhci", + "brcm,bcm7445-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x84b0000 0x260 0x84b0300 0x200>; + reg-names = "host", "cfg"; + interrupts = <0x0 0x26 0x4>; + interrupt-names = "sdio0_0"; + clocks = <&scmi_clk 245>; + clock-names = "sw_sdio"; }; - sdhci@f03e0300 { + sdhci@84b1000 { + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + supports-cqe; non-removable; bus-width = <0x8>; - compatible = "brcm,bcm7425-sdhci"; - reg = <0xf03e0200 0x100>; - interrupts = <0x0 0x27 0x0>; - sdhci,auto-cmd12; - clocks = <sw_sdio>; - mmc-hs200-1_8v; + compatible = "brcm,bcm7216-sdhci", + "brcm,bcm7445-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x84b1000 0x260 0x84b1300 0x200>; + reg-names = "host", "cfg"; + interrupts = <0x0 0x27 0x4>; + interrupt-names = "sdio1_0"; + clocks = <&scmi_clk 245>; + clock-names = "sw_sdio"; }; diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 2fb466ca2a9d..0f97d711444e 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -21,6 +21,8 @@ Required properties: "fsl,imx8mq-usdhc" "fsl,imx8mm-usdhc" "fsl,imx8mn-usdhc" + "fsl,imx8mp-usdhc" + "fsl,imx8qm-usdhc" "fsl,imx8qxp-usdhc" Optional properties: diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index b130450c3b34..3c0df4016a12 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -96,11 +96,10 @@ properties: description: When set, no physical write-protect line is present. This property should only be specified when the controller has a - dedicated write-protect detection logic. If a GPIO is always - used for the write-protect detection. If a GPIO is always used + dedicated write-protect detection logic. If a GPIO is always used for the write-protect detection logic, it is sufficient to not specify the wp-gpios property in the absence of a write-protect - line. + line. Not used in combination with eMMC or SDIO. wp-gpios: description: diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt b/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt index bc08fc43a9be..e6cc47844207 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt @@ -23,7 +23,8 @@ Required properties: "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC - "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC + "renesas,sdhi-r8a7796" - SDHI IP on R8A77960 SoC + "renesas,sdhi-r8a77961" - SDHI IP on R8A77961 SoC "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC "renesas,sdhi-r8a77970" - SDHI IP on R8A77970 SoC "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt deleted file mode 100644 index 6f629b12bd69..000000000000 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Rockchip specific extensions to the Synopsys Designware Mobile - Storage Host Controller - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Rockchip specific -extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be - - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following, - before RK3288 - - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 - - "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108 - - "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip PX30 - - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036 - - "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322x - - "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328 - - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368 - - "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399 - -Optional Properties: -* clocks: from common clock binding: if ciu-drive and ciu-sample are - specified in clock-names, should contain handles to these clocks. - -* clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt - two more clocks "ciu-drive" and "ciu-sample" are supported. They are used - to control the clock phases, "ciu-sample" is required for tuning high- - speed modes. - -* rockchip,default-sample-phase: The default phase to set ciu-sample at - probing, low speeds or in case where all phases work at tuning time. - If not specified 0 deg will be used. - -* rockchip,desired-num-phases: The desired number of times that the host - execute tuning when needed. If not specified, the host will do tuning - for 360 times, namely tuning for each degree. - -Example: - - rkdwmmc0@12200000 { - compatible = "rockchip,rk3288-dw-mshc"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml new file mode 100644 index 000000000000..89c3edd6a728 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip designware mobile storage host controller device tree bindings + +description: + Rockchip uses the Synopsys designware mobile storage host controller + to interface a SoC with storage medium such as eMMC or SD/MMC cards. + This file documents the combined properties for the core Synopsys dw mshc + controller that are not already included in the synopsys-dw-mshc-common.yaml + file and the Rockchip specific extensions. + +allOf: + - $ref: "synopsys-dw-mshc-common.yaml#" + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +# Everything else is described in the common file +properties: + compatible: + oneOf: + # for Rockchip RK2928 and before RK3288 + - const: rockchip,rk2928-dw-mshc + # for Rockchip RK3288 + - const: rockchip,rk3288-dw-mshc + - items: + - enum: + # for Rockchip PX30 + - rockchip,px30-dw-mshc + # for Rockchip RK3036 + - rockchip,rk3036-dw-mshc + # for Rockchip RK322x + - rockchip,rk3228-dw-mshc + # for Rockchip RK3308 + - rockchip,rk3308-dw-mshc + # for Rockchip RK3328 + - rockchip,rk3328-dw-mshc + # for Rockchip RK3368 + - rockchip,rk3368-dw-mshc + # for Rockchip RK3399 + - rockchip,rk3399-dw-mshc + # for Rockchip RV1108 + - rockchip,rv1108-dw-mshc + - const: rockchip,rk3288-dw-mshc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 4 + description: + Handle to "biu" and "ciu" clocks for the bus interface unit clock and + the card interface unit clock. If "ciu-drive" and "ciu-sample" are + specified in clock-names, it should also contain + handles to these clocks. + + clock-names: + minItems: 2 + items: + - const: biu + - const: ciu + - const: ciu-drive + - const: ciu-sample + description: + Apart from the clock-names "biu" and "ciu" two more clocks + "ciu-drive" and "ciu-sample" are supported. They are used + to control the clock phases, "ciu-sample" is required for tuning + high speed modes. + + rockchip,default-sample-phase: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 360 + default: 0 + description: + The default phase to set "ciu-sample" at probing, + low speeds or in case where all phases work at tuning time. + If not specified 0 deg will be used. + + rockchip,desired-num-phases: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 360 + default: 360 + description: + The desired number of times that the host execute tuning when needed. + If not specified, the host will do tuning for 360 times, + namely tuning for each degree. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/rk3288-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + sdmmc: mmc@ff0c0000 { + compatible = "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0c0000 0x0 0x4000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + resets = <&cru SRST_MMC0>; + reset-names = "reset"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + }; + +... diff --git a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt b/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt index 503c6dbac1b2..69edfd4d3922 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt @@ -5,11 +5,16 @@ Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the sdhci-of-at91 driver. Required properties: -- compatible: Must be "atmel,sama5d2-sdhci". +- compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci". - clocks: Phandlers to the clocks. -- clock-names: Must be "hclock", "multclk", "baseclk"; +- clock-names: Must be "hclock", "multclk", "baseclk" for + "atmel,sama5d2-sdhci". + Must be "hclock", "multclk" for "microchip,sam9x60-sdhci". Optional properties: +- assigned-clocks: The same with "multclk". +- assigned-clock-rates The rate of "multclk" in order to not rely on the + gck configuration set by previous components. - microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is inverted. The default polarity for this signal is described in the datasheet. For instance on SAMA5D2, the pin is usually tied to the GND with a resistor @@ -17,10 +22,12 @@ Optional properties: Example: -sdmmc0: sdio-host@a0000000 { +mmc0: sdio-host@a0000000 { compatible = "atmel,sama5d2-sdhci"; reg = <0xa0000000 0x300>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; clock-names = "hclock", "multclk", "baseclk"; + assigned-clocks = <&sdmmc0_gclk>; + assigned-clock-rates = <480000000>; }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index da4edb146a98..7ee639b1af03 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -19,6 +19,7 @@ Required properties: "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4" "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5" + "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; NOTE that some old device tree files may be floating around that only have the string "qcom,sdhci-msm-v4" without the SoC compatible string but doing that should be considered a deprecated practice. diff --git a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt index 72c4dec7e1db..aeb615ef672a 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt @@ -7,6 +7,8 @@ For UHS devices which require tuning, the device tree should have a "cpu_thermal Required properties: - compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers Should be "ti,k2g-sdhci" for K2G + Should be "ti,am335-sdhci" for am335x controllers + Should be "ti,am437-sdhci" for am437x controllers - ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1 (Not required for K2G). - pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50", @@ -15,6 +17,13 @@ Required properties: "hs200_1_8v", - pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt +Optional properties: +- dmas: List of DMA specifiers with the controller specific format as described + in the generic DMA client binding. A tx and rx specifier is required. +- dma-names: List of DMA request names. These strings correspond 1:1 with the + DMA specifiers listed in dmas. The string naming is to be "tx" + and "rx" for TX and RX DMA requests, respectively. + Example: mmc1: mmc@4809c000 { compatible = "ti,dra7-sdhci"; @@ -22,4 +31,6 @@ Example: ti,hwmods = "mmc1"; bus-width = <4>; vmmc-supply = <&vmmc>; /* phandle to regulator node */ + dmas = <&sdma 61 &sdma 62>; + dma-names = "tx", "rx"; }; diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml new file mode 100644 index 000000000000..890d47a87ac5 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys Designware Mobile Storage Host Controller Common Properties + +allOf: + - $ref: "mmc-controller.yaml#" + +maintainers: + - Ulf Hansson <ulf.hansson@linaro.org> + +# Everything else is described in the common file +properties: + resets: + maxItems: 1 + + reset-names: + const: reset + + clock-frequency: + description: + Should be the frequency (in Hz) of the ciu clock. If this + is specified and the ciu clock is specified then we'll try to set the ciu + clock to this at probe time. + + fifo-depth: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum size of the tx/rx fifo's. If this property is not + specified, the default value of the fifo size is determined from the + controller registers. + + card-detect-delay: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - default: 0 + description: + Delay in milli-seconds before detecting card after card + insert event. The default value is 0. + + data-addr: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + description: + Override fifo address with value provided by DT. The default FIFO reg + offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) + by driver. If the controller does not follow this rule, please use + this property to set fifo address in device tree. + + fifo-watermark-aligned: + allOf: + - $ref: /schemas/types.yaml#/definitions/flag + description: + Data done irq is expected if data length is less than + watermark in PIO mode. But fifo watermark is requested to be aligned + with data length in some SoC so that TX/RX irq can be generated with + data done irq. Add this watermark quirk to mark this requirement and + force fifo watermark setting accordingly. + + dmas: + maxItems: 1 + + dma-names: + const: rx-tx diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt deleted file mode 100644 index 7e5e427a22ce..000000000000 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ /dev/null @@ -1,141 +0,0 @@ -* Synopsys Designware Mobile Storage Host Controller - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core mmc properties described by mmc.txt and the -properties used by the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be - - snps,dw-mshc: for controllers compliant with synopsys dw-mshc. -* #address-cells: should be 1. -* #size-cells: should be 0. - -# Slots (DEPRECATED): The slot specific information are contained within - child-nodes with each child-node representing a supported slot. There should - be atleast one child node representing a card slot. The name of the child node - representing the slot is recommended to be slot@n where n is the unique number - of the slot connected to the controller. The following are optional properties - which can be included in the slot child node. - - * reg: specifies the physical slot number. The valid values of this - property is 0 to (num-slots -1), where num-slots is the value - specified by the num-slots property. - - * bus-width: as documented in mmc core bindings. - - * wp-gpios: specifies the write protect gpio line. The format of the - gpio specifier depends on the gpio controller. If a GPIO is not used - for write-protect, this property is optional. - - * disable-wp: If the wp-gpios property isn't present then (by default) - we'd assume that the write protect is hooked up directly to the - controller's special purpose write protect line (accessible via - the WRTPRT register). However, it's possible that we simply don't - want write protect. In that case specify 'disable-wp'. - NOTE: This property is not required for slots known to always - connect to eMMC or SDIO cards. - -Optional properties: - -* resets: phandle + reset specifier pair, intended to represent hardware - reset signal present internally in some host controller IC designs. - See Documentation/devicetree/bindings/reset/reset.txt for details. - -* reset-names: request name for using "resets" property. Must be "reset". - (It will be used together with "resets" property.) - -* clocks: from common clock binding: handle to biu and ciu clocks for the - bus interface unit clock and the card interface unit clock. - -* clock-names: from common clock binding: Shall be "biu" and "ciu". - If the biu clock is missing we'll simply skip enabling it. If the - ciu clock is missing we'll just assume that the clock is running at - clock-frequency. It is an error to omit both the ciu clock and the - clock-frequency. - -* clock-frequency: should be the frequency (in Hz) of the ciu clock. If this - is specified and the ciu clock is specified then we'll try to set the ciu - clock to this at probe time. - -* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not - specified, the default value of the fifo size is determined from the - controller registers. - -* card-detect-delay: Delay in milli-seconds before detecting card after card - insert event. The default value is 0. - -* data-addr: Override fifo address with value provided by DT. The default FIFO reg - offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by - driver. If the controller does not follow this rule, please use this property - to set fifo address in device tree. - -* fifo-watermark-aligned: Data done irq is expected if data length is less than - watermark in PIO mode. But fifo watermark is requested to be aligned with data - length in some SoC so that TX/RX irq can be generated with data done irq. Add this - watermark quirk to mark this requirement and force fifo watermark setting - accordingly. - -* vmmc-supply: The phandle to the regulator to use for vmmc. If this is - specified we'll defer probe until we can find this regulator. - -* dmas: List of DMA specifiers with the controller specific format as described - in the generic DMA client binding. Refer to dma.txt for details. - -* dma-names: request names for generic DMA client binding. Must be "rx-tx". - Refer to dma.txt for details. - -Aliases: - -- All the MSHC controller nodes should be represented in the aliases node using - the following format 'mshc{n}' where n is a unique number for the alias. - -Example: - -The MSHC controller node can be split into two portions, SoC specific and -board specific portions as listed below. - - dwmmc0@12200000 { - compatible = "snps,dw-mshc"; - clocks = <&clock 351>, <&clock 132>; - clock-names = "biu", "ciu"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - data-addr = <0x200>; - fifo-watermark-aligned; - resets = <&rst 20>; - reset-names = "reset"; - }; - -[board specific internal DMA resources] - - dwmmc0@12200000 { - clock-frequency = <400000000>; - clock-freq-min-max = <400000 200000000>; - broken-cd; - fifo-depth = <0x80>; - card-detect-delay = <200>; - vmmc-supply = <&buck8>; - bus-width = <8>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - -[board specific generic DMA request binding] - - dwmmc0@12200000 { - clock-frequency = <400000000>; - clock-freq-min-max = <400000 200000000>; - broken-cd; - fifo-depth = <0x80>; - card-detect-delay = <200>; - vmmc-supply = <&buck8>; - bus-width = <8>; - cap-mmc-highspeed; - cap-sd-highspeed; - dmas = <&pdma 12>; - dma-names = "rx-tx"; - }; diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml new file mode 100644 index 000000000000..05f9f36dcb75 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys Designware Mobile Storage Host Controller Binding + +allOf: + - $ref: "synopsys-dw-mshc-common.yaml#" + +maintainers: + - Ulf Hansson <ulf.hansson@linaro.org> + +# Everything else is described in the common file +properties: + compatible: + const: snps,dw-mshc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + description: + Handle to "biu" and "ciu" clocks for the + bus interface unit clock and the card interface unit clock. + + clock-names: + items: + - const: biu + - const: ciu + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + mmc@12200000 { + compatible = "snps,dw-mshc"; + reg = <0x12200000 0x1000>; + interrupts = <0 75 0>; + clocks = <&clock 351>, <&clock 132>; + clock-names = "biu", "ciu"; + dmas = <&pdma 12>; + dma-names = "rx-tx"; + resets = <&rst 20>; + reset-names = "reset"; + vmmc-supply = <&buck8>; + #address-cells = <1>; + #size-cells = <0>; + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + clock-freq-min-max = <400000 200000000>; + clock-frequency = <400000000>; + data-addr = <0x200>; + fifo-depth = <0x80>; + fifo-watermark-aligned; + }; diff --git a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml index b5b3cf5b1ac2..5d3fa412aabd 100644 --- a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml @@ -11,7 +11,7 @@ allOf: maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#address-cells": true diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt index b32aed1db46d..98916a84bbf6 100644 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt @@ -14,6 +14,11 @@ Required properties: interface clock, and the ECC circuit clock. - clock-names: should contain "nand", "nand_x", "ecc" +Optional properties: + - resets: may contain phandles to the controller core reset, the register + reset + - reset-names: may contain "nand", "reg" + Sub-nodes: Sub-nodes represent available NAND chips. @@ -46,6 +51,8 @@ nand: nand@ff900000 { reg-names = "nand_data", "denali_reg"; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&nand_rst>, <&nand_reg_rst>; + reset-names = "nand", "reg"; interrupts = <0 144 4>; nand@0 { diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml index ae4796ec50a0..8d8560a67abf 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml @@ -11,7 +11,7 @@ allOf: maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-mdio.yaml b/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-mdio.yaml index e5562c525ed9..767193ec1d32 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-mdio.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-mdio.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 MDIO Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> allOf: - $ref: "mdio.yaml#" diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml index f683b7104e3e..703d0d886884 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml @@ -11,7 +11,7 @@ allOf: maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 11654d4b80fb..db36b4d86484 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -8,7 +8,7 @@ title: Allwinner A83t EMAC Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt index f16b99571af1..dd258674633c 100644 --- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt @@ -11,6 +11,7 @@ Required properties: - compatible: should contain one of the following: * "brcm,bcm20702a1" + * "brcm,bcm4329-bt" * "brcm,bcm4330-bt" * "brcm,bcm43438-bt" * "brcm,bcm4345c5" @@ -22,7 +23,9 @@ Optional properties: - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt - shutdown-gpios: GPIO specifier, used to enable the BT module - device-wakeup-gpios: GPIO specifier, used to wakeup the controller - - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor + - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor. + deprecated, replaced by interrupts and + "host-wakeup" interrupt-names - clocks: 1 or 2 clocks as defined in clock-names below, in that order - clock-names: names for clock inputs, matching the clocks given - "extclk": deprecated, replaced by "txco" @@ -30,7 +33,14 @@ Optional properties: - "lpo": external low power 32.768 kHz clock - vbat-supply: phandle to regulator supply for VBAT - vddio-supply: phandle to regulator supply for VDDIO - + - brcm,bt-pcm-int-params: configure PCM parameters via a 5-byte array + - sco-routing: 0 = PCM, 1 = Transport, 2 = Codec, 3 = I2S + - pcm-interface-rate: 128KBps, 256KBps, 512KBps, 1024KBps, 2048KBps + - pcm-frame-type: short, long + - pcm-sync-mode: slave, master + - pcm-clock-mode: slave, master + - interrupts: must be one, used to wakeup the host processor + - interrupt-names: must be "host-wakeup" Example: @@ -41,5 +51,6 @@ Example: bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <921600>; + brcm,bt-pcm-int-params = [01 02 00 01 01]; }; }; diff --git a/Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml b/Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml index 770af7c46114..a95960ee3feb 100644 --- a/Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml +++ b/Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 CAN Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/net/can/tcan4x5x.txt b/Documentation/devicetree/bindings/net/can/tcan4x5x.txt index 27e1b4cebfbd..6bdcc3f84bd3 100644 --- a/Documentation/devicetree/bindings/net/can/tcan4x5x.txt +++ b/Documentation/devicetree/bindings/net/can/tcan4x5x.txt @@ -10,7 +10,6 @@ Required properties: - #size-cells: 0 - spi-max-frequency: Maximum frequency of the SPI bus the chip can operate at should be less than or equal to 18 MHz. - - device-wake-gpios: Wake up GPIO to wake up the TCAN device. - interrupt-parent: the phandle to the interrupt controller which provides the interrupt. - interrupts: interrupt specification for data-ready. @@ -23,6 +22,7 @@ Optional properties: reset. - device-state-gpios: Input GPIO that indicates if the device is in a sleep state or if the device is active. + - device-wake-gpios: Wake up GPIO to wake up the TCAN device. Example: tcan4x5x: tcan4x5x@0 { @@ -36,5 +36,5 @@ tcan4x5x: tcan4x5x@0 { interrupts = <14 GPIO_ACTIVE_LOW>; device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; }; diff --git a/Documentation/devicetree/bindings/net/dsa/ar9331.txt b/Documentation/devicetree/bindings/net/dsa/ar9331.txt new file mode 100644 index 000000000000..320607cbbb17 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/ar9331.txt @@ -0,0 +1,148 @@ +Atheros AR9331 built-in switch +============================= + +It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal +MDIO bus. All PHYs are built-in as well. + +Required properties: + + - compatible: should be: "qca,ar9331-switch" + - reg: Address on the MII bus for the switch. + - resets : Must contain an entry for each entry in reset-names. + - reset-names : Must include the following entries: "switch" + - interrupt-parent: Phandle to the parent interrupt controller + - interrupts: IRQ line for the switch + - interrupt-controller: Indicates the switch is itself an interrupt + controller. This is used for the PHY interrupts. + - #interrupt-cells: must be 1 + - mdio: Container of PHY and devices on the switches MDIO bus. + +See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional +required and optional properties. +Examples: + +eth0: ethernet@19000000 { + compatible = "qca,ar9330-eth"; + reg = <0x19000000 0x200>; + interrupts = <4>; + + resets = <&rst 9>, <&rst 22>; + reset-names = "mac", "mdio"; + clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; + clock-names = "eth", "mdio"; + + phy-mode = "mii"; + phy-handle = <&phy_port4>; +}; + +eth1: ethernet@1a000000 { + compatible = "qca,ar9330-eth"; + reg = <0x1a000000 0x200>; + interrupts = <5>; + resets = <&rst 13>, <&rst 23>; + reset-names = "mac", "mdio"; + clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; + clock-names = "eth", "mdio"; + + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch10: switch@10 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qca,ar9331-switch"; + reg = <0x10>; + resets = <&rst 8>; + reset-names = "switch"; + + interrupt-parent = <&miscintc>; + interrupts = <12>; + + interrupt-controller; + #interrupt-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + switch_port0: port@0 { + reg = <0x0>; + label = "cpu"; + ethernet = <ð1>; + + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + switch_port1: port@1 { + reg = <0x1>; + phy-handle = <&phy_port0>; + phy-mode = "internal"; + }; + + switch_port2: port@2 { + reg = <0x2>; + phy-handle = <&phy_port1>; + phy-mode = "internal"; + }; + + switch_port3: port@3 { + reg = <0x3>; + phy-handle = <&phy_port2>; + phy-mode = "internal"; + }; + + switch_port4: port@4 { + reg = <0x4>; + phy-handle = <&phy_port3>; + phy-mode = "internal"; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&switch10>; + + phy_port0: phy@0 { + reg = <0x0>; + interrupts = <0>; + }; + + phy_port1: phy@1 { + reg = <0x1>; + interrupts = <0>; + }; + + phy_port2: phy@2 { + reg = <0x2>; + interrupts = <0>; + }; + + phy_port3: phy@3 { + reg = <0x3>; + interrupts = <0>; + }; + + phy_port4: phy@4 { + reg = <0x4>; + interrupts = <0>; + }; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt b/Documentation/devicetree/bindings/net/fsl-fman.txt index 299c0dcd67db..250f8d8cdce4 100644 --- a/Documentation/devicetree/bindings/net/fsl-fman.txt +++ b/Documentation/devicetree/bindings/net/fsl-fman.txt @@ -403,6 +403,19 @@ PROPERTIES The settings and programming routines for internal/external MDIO are different. Must be included for internal MDIO. +- fsl,erratum-a011043 + Usage: optional + Value type: <boolean> + Definition: Indicates the presence of the A011043 erratum + describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely + set when reading internal PCS registers. MDIO reads to + internal PCS registers may result in having the + MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and + read data (MDIO_DATA[MDIO_DATA]) is correct. + Software may get false read error when reading internal + PCS registers through MDIO. As a workaround, all internal + MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit. + For internal PHY device on internal mdio bus, a PHY node should be created. See the definition of the PHY node in booting-without-of.txt for an example of how to define a PHY (Internal PHY has no interrupt line). diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt index 8a08621a5b54..afbcaebf062e 100644 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt @@ -14,7 +14,7 @@ Required properties: Should be "macirq" for the main MAC IRQ - clocks: Must contain a phandle for each entry in clock-names. - clock-names: The name of the clock listed in the clocks property. These are - "axi", "apb", "mac_main", "ptp_ref" for MT2712 SoC + "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC. - mac-address: See ethernet.txt in the same directory - phy-mode: See ethernet.txt in the same directory - mediatek,pericfg: A phandle to the syscon node that control ethernet @@ -23,8 +23,10 @@ Required properties: Optional properties: - mediatek,tx-delay-ps: TX clock delay macro value. Default is 0. It should be defined for RGMII/MII interface. + It should be defined for RMII interface when the reference clock is from MT2712 SoC. - mediatek,rx-delay-ps: RX clock delay macro value. Default is 0. - It should be defined for RGMII/MII/RMII interface. + It should be defined for RGMII/MII interface. + It should be defined for RMII interface. Both delay properties need to be a multiple of 170 for RGMII interface, or will round down. Range 0~31*170. Both delay properties need to be a multiple of 550 for MII/RMII interface, @@ -34,13 +36,20 @@ or will round down. Range 0~31*550. reference clock, which is from external PHYs, is connected to RXC pin on MT2712 SoC. Otherwise, is connected to TXC pin. +- mediatek,rmii-clk-from-mac: boolean property, if present indicates that + MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only. - mediatek,txc-inverse: boolean property, if present indicates that 1. tx clock will be inversed in MII/RGMII case, 2. tx clock inside MAC will be inversed relative to reference clock which is from external PHYs in RMII case, and it rarely happen. + 3. the reference clock, which outputs to TXC pin will be inversed in RMII case + when the reference clock is from MT2712 SoC. - mediatek,rxc-inverse: boolean property, if present indicates that 1. rx clock will be inversed in MII/RGMII case. - 2. reference clock will be inversed when arrived at MAC in RMII case. + 2. reference clock will be inversed when arrived at MAC in RMII case, when + the reference clock is from external PHYs. + 3. the inside clock, which be sent to MAC, will be inversed in RMII case when + the reference clock is from MT2712 SoC. - assigned-clocks: mac_main and ptp_ref clocks - assigned-clock-parents: parent clocks of the assigned clocks @@ -50,29 +59,33 @@ Example: reg = <0 0x1101c000 0 0x1300>; interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "macirq"; - phy-mode ="rgmii"; + phy-mode ="rgmii-rxid"; mac-address = [00 55 7b b5 7d f7]; clock-names = "axi", "apb", "mac_main", "ptp_ref", - "ptp_top"; + "rmii_internal"; clocks = <&pericfg CLK_PERI_GMAC>, <&pericfg CLK_PERI_GMAC_PCLK>, <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, - <&topckgen CLK_TOP_APLL1_D3>; + <&topckgen CLK_TOP_APLL1_D3>, + <&topckgen CLK_TOP_ETHERPLL_50M>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; mediatek,pericfg = <&pericfg>; mediatek,tx-delay-ps = <1530>; mediatek,rx-delay-ps = <1530>; mediatek,rmii-rxc; mediatek,txc-inverse; mediatek,rxc-inverse; - snps,txpbl = <32>; - snps,rxpbl = <32>; + snps,txpbl = <1>; + snps,rxpbl = <1>; snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; snps,reset-active-low; }; diff --git a/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt b/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt index 68b67d9db63a..999aceadb985 100644 --- a/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt @@ -11,6 +11,7 @@ Required properties: - compatible: should contain one of the following: * "qcom,qca6174-bt" * "qcom,wcn3990-bt" + * "qcom,wcn3991-bt" * "qcom,wcn3998-bt" Optional properties for compatible string qcom,qca6174-bt: diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt index 5df4aa7f6811..87dad2dd8ca0 100644 --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt @@ -21,7 +21,8 @@ Required properties: - "renesas,etheravb-r8a774b1" for the R8A774B1 SoC. - "renesas,etheravb-r8a774c0" for the R8A774C0 SoC. - "renesas,etheravb-r8a7795" for the R8A7795 SoC. - - "renesas,etheravb-r8a7796" for the R8A7796 SoC. + - "renesas,etheravb-r8a7796" for the R8A77960 SoC. + - "renesas,etheravb-r8a77961" for the R8A77961 SoC. - "renesas,etheravb-r8a77965" for the R8A77965 SoC. - "renesas,etheravb-r8a77970" for the R8A77970 SoC. - "renesas,etheravb-r8a77980" for the R8A77980 SoC. @@ -37,8 +38,8 @@ Required properties: - reg: Offset and length of (1) the register block and (2) the stream buffer. The region for the register block is mandatory. The region for the stream buffer is optional, as it is only present on - R-Car Gen2 and RZ/G1 SoCs, and on R-Car H3 (R8A7795), M3-W (R8A7796), - and M3-N (R8A77965). + R-Car Gen2 and RZ/G1 SoCs, and on R-Car H3 (R8A7795), M3-W (R8A77960), + M3-W+ (R8A77961), and M3-N (R8A77965). - interrupts: A list of interrupt-specifiers, one for each entry in interrupt-names. If interrupt-names is not present, an interrupt specifier diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 4845e29411e4..e08cd4c4d568 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -347,6 +347,7 @@ allOf: - st,spear600-gmac then: + properties: snps,tso: $ref: /schemas/types.yaml#definitions/flag description: diff --git a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml index 81ae8cafabc1..ac8c76369a86 100644 --- a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml +++ b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml# @@ -44,7 +44,6 @@ properties: description: CPSW functional clock clock-names: - maxItems: 1 items: - const: fck @@ -70,7 +69,6 @@ properties: Phandle to the system control device node which provides access to efuse IO range with MAC addresses - ethernet-ports: type: object properties: @@ -82,8 +80,6 @@ properties: patternProperties: "^port@[0-9]+$": type: object - minItems: 1 - maxItems: 2 description: CPSW external ports allOf: @@ -91,23 +87,20 @@ properties: properties: reg: - maxItems: 1 - enum: [1, 2] + items: + - enum: [1, 2] description: CPSW port number phys: - $ref: /schemas/types.yaml#definitions/phandle-array maxItems: 1 description: phandle on phy-gmii-sel PHY label: - $ref: /schemas/types.yaml#/definitions/string-array - maxItems: 1 description: label associated with this port ti,dual-emac-pvid: - $ref: /schemas/types.yaml#/definitions/uint32 - maxItems: 1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 1024 description: @@ -136,7 +129,6 @@ properties: description: CPTS reference clock clock-names: - maxItems: 1 items: - const: cpts @@ -201,7 +193,7 @@ examples: phys = <&phy_gmii_sel 1>; phy-handle = <ðphy0_sw>; phy-mode = "rgmii"; - ti,dual_emac_pvid = <1>; + ti,dual-emac-pvid = <1>; }; cpsw_port2: port@2 { @@ -211,7 +203,7 @@ examples: phys = <&phy_gmii_sel 2>; phy-handle = <ðphy1_sw>; phy-mode = "rgmii"; - ti,dual_emac_pvid = <2>; + ti,dual-emac-pvid = <2>; }; }; diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt index 388ff48f53ae..44e2a4fab29e 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83867.txt +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt @@ -8,8 +8,6 @@ Required properties: - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h for applicable values. Required only if interface type is PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID - - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h - for applicable values Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays will be left at their default values, as set by the PHY's pin strapping. @@ -42,6 +40,14 @@ Optional property: Some MACs work with differential SGMII clock. See data manual for details. + - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h + for applicable values (deprecated) + + -tx-fifo-depth - As defined in the ethernet-controller.yaml. Values for + the depth can be found in dt-bindings/net/ti-dp83867.h + -rx-fifo-depth - As defined in the ethernet-controller.yaml. Values for + the depth can be found in dt-bindings/net/ti-dp83867.h + Note: ti,min-output-impedance and ti,max-output-impedance are mutually exclusive. When both properties are present ti,max-output-impedance takes precedence. @@ -55,7 +61,7 @@ Example: reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; Datasheet can be found: diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt index 017128394a3e..616c87746d6f 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt @@ -50,7 +50,7 @@ Optional properties: entry in clock-names. - clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref", "wifi_wcss_rtc" for "qcom,ipq4019-wifi" compatible target and - "cxo_ref_clk_pin" for "qcom,wcn3990-wifi" + "cxo_ref_clk_pin" and optionally "qdss" for "qcom,wcn3990-wifi" compatible target. - qcom,msi_addr: MSI interrupt address. - qcom,msi_base: Base value to add before writing MSI data into @@ -88,6 +88,9 @@ Optional properties: of the host capability QMI request - qcom,xo-cal-data: xo cal offset to be configured in xo trim register. +- qcom,msa-fixed-perm: Boolean context flag to disable SCM call for statically + mapped msa region. + Example (to supply PCI based wifi block details): In this example, the node is defined as child node of the PCI controller. @@ -185,4 +188,5 @@ wifi@18000000 { vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; memory-region = <&wifi_msa_mem>; iommus = <&apps_smmu 0x0040 0x1>; + qcom,msa-fixed-perm; }; diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml new file mode 100644 index 000000000000..a1717db36dba --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml @@ -0,0 +1,273 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/qcom,ath11k.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies ath11k wireless devices Generic Binding + +maintainers: + - Kalle Valo <kvalo@codeaurora.org> + +description: | + These are dt entries for Qualcomm Technologies, Inc. IEEE 802.11ax + devices, for example like AHB based IPQ8074. + +properties: + compatible: + const: qcom,ipq8074-wifi + + reg: + maxItems: 1 + + interrupts: + items: + - description: misc-pulse1 interrupt events + - description: misc-latch interrupt events + - description: sw exception interrupt events + - description: watchdog interrupt events + - description: interrupt event for ring CE0 + - description: interrupt event for ring CE1 + - description: interrupt event for ring CE2 + - description: interrupt event for ring CE3 + - description: interrupt event for ring CE4 + - description: interrupt event for ring CE5 + - description: interrupt event for ring CE6 + - description: interrupt event for ring CE7 + - description: interrupt event for ring CE8 + - description: interrupt event for ring CE9 + - description: interrupt event for ring CE10 + - description: interrupt event for ring CE11 + - description: interrupt event for ring host2wbm-desc-feed + - description: interrupt event for ring host2reo-re-injection + - description: interrupt event for ring host2reo-command + - description: interrupt event for ring host2rxdma-monitor-ring3 + - description: interrupt event for ring host2rxdma-monitor-ring2 + - description: interrupt event for ring host2rxdma-monitor-ring1 + - description: interrupt event for ring reo2ost-exception + - description: interrupt event for ring wbm2host-rx-release + - description: interrupt event for ring reo2host-status + - description: interrupt event for ring reo2host-destination-ring4 + - description: interrupt event for ring reo2host-destination-ring3 + - description: interrupt event for ring reo2host-destination-ring2 + - description: interrupt event for ring reo2host-destination-ring1 + - description: interrupt event for ring rxdma2host-monitor-destination-mac3 + - description: interrupt event for ring rxdma2host-monitor-destination-mac2 + - description: interrupt event for ring rxdma2host-monitor-destination-mac1 + - description: interrupt event for ring ppdu-end-interrupts-mac3 + - description: interrupt event for ring ppdu-end-interrupts-mac2 + - description: interrupt event for ring ppdu-end-interrupts-mac1 + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3 + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2 + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac3 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac2 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac1 + - description: interrupt event for ring rxdma2host-destination-ring-mac3 + - description: interrupt event for ring rxdma2host-destination-ring-mac2 + - description: interrupt event for ring rxdma2host-destination-ring-mac1 + - description: interrupt event for ring host2tcl-input-ring4 + - description: interrupt event for ring host2tcl-input-ring3 + - description: interrupt event for ring host2tcl-input-ring2 + - description: interrupt event for ring host2tcl-input-ring1 + - description: interrupt event for ring wbm2host-tx-completions-ring3 + - description: interrupt event for ring wbm2host-tx-completions-ring2 + - description: interrupt event for ring wbm2host-tx-completions-ring1 + - description: interrupt event for ring tcl2host-status-ring + + + interrupt-names: + items: + - const: misc-pulse1 + - const: misc-latch + - const: sw-exception + - const: watchdog + - const: ce0 + - const: ce1 + - const: ce2 + - const: ce3 + - const: ce4 + - const: ce5 + - const: ce6 + - const: ce7 + - const: ce8 + - const: ce9 + - const: ce10 + - const: ce11 + - const: host2wbm-desc-feed + - const: host2reo-re-injection + - const: host2reo-command + - const: host2rxdma-monitor-ring3 + - const: host2rxdma-monitor-ring2 + - const: host2rxdma-monitor-ring1 + - const: reo2ost-exception + - const: wbm2host-rx-release + - const: reo2host-status + - const: reo2host-destination-ring4 + - const: reo2host-destination-ring3 + - const: reo2host-destination-ring2 + - const: reo2host-destination-ring1 + - const: rxdma2host-monitor-destination-mac3 + - const: rxdma2host-monitor-destination-mac2 + - const: rxdma2host-monitor-destination-mac1 + - const: ppdu-end-interrupts-mac3 + - const: ppdu-end-interrupts-mac2 + - const: ppdu-end-interrupts-mac1 + - const: rxdma2host-monitor-status-ring-mac3 + - const: rxdma2host-monitor-status-ring-mac2 + - const: rxdma2host-monitor-status-ring-mac1 + - const: host2rxdma-host-buf-ring-mac3 + - const: host2rxdma-host-buf-ring-mac2 + - const: host2rxdma-host-buf-ring-mac1 + - const: rxdma2host-destination-ring-mac3 + - const: rxdma2host-destination-ring-mac2 + - const: rxdma2host-destination-ring-mac1 + - const: host2tcl-input-ring4 + - const: host2tcl-input-ring3 + - const: host2tcl-input-ring2 + - const: host2tcl-input-ring1 + - const: wbm2host-tx-completions-ring3 + - const: wbm2host-tx-completions-ring2 + - const: wbm2host-tx-completions-ring1 + - const: tcl2host-status-ring + + qcom,rproc: + $ref: /schemas/types.yaml#definitions/phandle + description: + DT entry of q6v5-wcss remoteproc driver. + Phandle to a node that can contain the following properties + * compatible + * reg + * reg-names + +required: + - compatible + - reg + - interrupts + - interrupt-names + - qcom,rproc + +additionalProperties: false + +examples: + - | + + q6v5_wcss: q6v5_wcss@CD00000 { + compatible = "qcom,ipq8074-wcss-pil"; + reg = <0xCD00000 0x4040>, + <0x4AB000 0x20>; + reg-names = "qdsp6", + "rmb"; + }; + + wifi0: wifi@c000000 { + compatible = "qcom,ipq8074-wifi"; + reg = <0xc000000 0x2000000>; + interrupts = <0 320 1>, + <0 319 1>, + <0 318 1>, + <0 317 1>, + <0 316 1>, + <0 315 1>, + <0 314 1>, + <0 311 1>, + <0 310 1>, + <0 411 1>, + <0 410 1>, + <0 40 1>, + <0 39 1>, + <0 302 1>, + <0 301 1>, + <0 37 1>, + <0 36 1>, + <0 296 1>, + <0 295 1>, + <0 294 1>, + <0 293 1>, + <0 292 1>, + <0 291 1>, + <0 290 1>, + <0 289 1>, + <0 288 1>, + <0 239 1>, + <0 236 1>, + <0 235 1>, + <0 234 1>, + <0 233 1>, + <0 232 1>, + <0 231 1>, + <0 230 1>, + <0 229 1>, + <0 228 1>, + <0 224 1>, + <0 223 1>, + <0 203 1>, + <0 183 1>, + <0 180 1>, + <0 179 1>, + <0 178 1>, + <0 177 1>, + <0 176 1>, + <0 163 1>, + <0 162 1>, + <0 160 1>, + <0 159 1>, + <0 158 1>, + <0 157 1>, + <0 156 1>; + interrupt-names = "misc-pulse1", + "misc-latch", + "sw-exception", + "watchdog", + "ce0", + "ce1", + "ce2", + "ce3", + "ce4", + "ce5", + "ce6", + "ce7", + "ce8", + "ce9", + "ce10", + "ce11", + "host2wbm-desc-feed", + "host2reo-re-injection", + "host2reo-command", + "host2rxdma-monitor-ring3", + "host2rxdma-monitor-ring2", + "host2rxdma-monitor-ring1", + "reo2ost-exception", + "wbm2host-rx-release", + "reo2host-status", + "reo2host-destination-ring4", + "reo2host-destination-ring3", + "reo2host-destination-ring2", + "reo2host-destination-ring1", + "rxdma2host-monitor-destination-mac3", + "rxdma2host-monitor-destination-mac2", + "rxdma2host-monitor-destination-mac1", + "ppdu-end-interrupts-mac3", + "ppdu-end-interrupts-mac2", + "ppdu-end-interrupts-mac1", + "rxdma2host-monitor-status-ring-mac3", + "rxdma2host-monitor-status-ring-mac2", + "rxdma2host-monitor-status-ring-mac1", + "host2rxdma-host-buf-ring-mac3", + "host2rxdma-host-buf-ring-mac2", + "host2rxdma-host-buf-ring-mac1", + "rxdma2host-destination-ring-mac3", + "rxdma2host-destination-ring-mac2", + "rxdma2host-destination-ring-mac1", + "host2tcl-input-ring4", + "host2tcl-input-ring3", + "host2tcl-input-ring2", + "host2tcl-input-ring1", + "wbm2host-tx-completions-ring3", + "wbm2host-tx-completions-ring2", + "wbm2host-tx-completions-ring1", + "tcl2host-status-ring"; + qcom,rproc = <&q6v5_wcss>; + }; diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml index 659b02002a35..daf1321d76ad 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 Security ID Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> allOf: - $ref: "nvmem.yaml#" diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt index 904dadf3d07b..6e346d5cddcf 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt @@ -2,7 +2,7 @@ Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings This binding represents the on-chip eFuse OTP controller found on i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL, -i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM and i.MX8MN SoCs. +i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs. Required properties: - compatible: should be one of @@ -17,6 +17,7 @@ Required properties: "fsl,imx8mq-ocotp" (i.MX8MQ), "fsl,imx8mm-ocotp" (i.MX8MM), "fsl,imx8mn-ocotp" (i.MX8MN), + "fsl,imx8mp-ocotp" (i.MX8MP), followed by "syscon". - #address-cells : Should be 1 - #size-cells : Should be 1 diff --git a/Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml b/Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml new file mode 100644 index 000000000000..7bbd4e62044e --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/qcom,spmi-sdam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SPMI SDAM DT bindings + +maintainers: + - Shyam Kumar Thella <sthella@codeaurora.org> + +description: | + The SDAM provides scratch register space for the PMIC clients. This + memory can be used by software to store information or communicate + to/from the PBUS. + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - qcom,spmi-sdam + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +required: + - compatible + - reg + - ranges + +patternProperties: + "^.*@[0-9a-f]+$": + type: object + + properties: + reg: + maxItems: 1 + description: + Offset and size in bytes within the storage device. + + bits: + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 + items: + items: + - minimum: 0 + maximum: 7 + description: + Offset in bit within the address range specified by reg. + - minimum: 1 + description: + Size in bit within the address range specified by reg. + + required: + - reg + + additionalProperties: false + +examples: + - | + sdam_1: nvram@b000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,spmi-sdam"; + reg = <0xb000 0x100>; + ranges = <0 0xb000 0x100>; + + /* Data cells */ + restart_reason: restart@50 { + reg = <0x50 0x1>; + bits = <6 2>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.txt b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.txt deleted file mode 100644 index 142a51d5a9be..000000000000 --- a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.txt +++ /dev/null @@ -1,31 +0,0 @@ -STMicroelectronics STM32 Factory-programmed data device tree bindings - -This represents STM32 Factory-programmed read only non-volatile area: locked -flash, OTP, read-only HW regs... This contains various information such as: -analog calibration data for temperature sensor (e.g. TS_CAL1, TS_CAL2), -internal vref (VREFIN_CAL), unique device ID... - -Required properties: -- compatible: Should be one of: - "st,stm32f4-otp" - "st,stm32mp15-bsec" -- reg: Offset and length of factory-programmed area. -- #address-cells: Should be '<1>'. -- #size-cells: Should be '<1>'. - -Optional Data cells: -- Must be child nodes as described in nvmem.txt. - -Example on stm32f4: - romem: nvmem@1fff7800 { - compatible = "st,stm32f4-otp"; - reg = <0x1fff7800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells: ts_cal1 at 0x1fff7a2c */ - ts_cal1: calib@22c { - reg = <0x22c 0x2>; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml new file mode 100644 index 000000000000..d84deb4774a4 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Factory-programmed data bindings + +description: | + This represents STM32 Factory-programmed read only non-volatile area: locked + flash, OTP, read-only HW regs... This contains various information such as: + analog calibration data for temperature sensor (e.g. TS_CAL1, TS_CAL2), + internal vref (VREFIN_CAL), unique device ID... + +maintainers: + - Fabrice Gasnier <fabrice.gasnier@st.com> + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - st,stm32f4-otp + - st,stm32mp15-bsec + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + +examples: + - | + efuse@1fff7800 { + compatible = "st,stm32f4-otp"; + reg = <0x1fff7800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + calib@22c { + reg = <0x22c 0x2>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml new file mode 100644 index 000000000000..aef87a33a7c9 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner H6 CPU OPP Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + For some SoCs, the CPU frequency subset and voltage value of each + OPP varies based on the silicon variant in use. Allwinner Process + Voltage Scaling Tables defines the voltage and frequency value based + on the speedbin blown in the efuse combination. The + sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to + provide the OPP framework with required information. + +properties: + compatible: + const: allwinner,sun50i-h6-operating-points + + nvmem-cells: + description: | + A phandle pointing to a nvmem-cells node representing the efuse + registers that has information about the speedbin that is used + to select the right frequency/voltage value pair. Please refer + the for nvmem-cells bindings + Documentation/devicetree/bindings/nvmem/nvmem.txt and also + examples below. + +required: + - compatible + - nvmem-cells + +patternProperties: + "opp-[0-9]+": + type: object + + properties: + opp-hz: true + + patternProperties: + "opp-microvolt-.*": true + + required: + - opp-hz + - opp-microvolt-speed0 + - opp-microvolt-speed1 + - opp-microvolt-speed2 + + unevaluatedProperties: false + +unevaluatedProperties: false + +examples: + - | + cpu_opp_table: opp-table { + compatible = "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-480000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <480000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <800000>; + }; + + opp-720000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <720000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <800000>; + }; + + opp-816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <800000>; + }; + + opp-888000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <888000000>; + + opp-microvolt-speed0 = <940000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <800000>; + }; + + opp-1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <1060000>; + opp-microvolt-speed1 = <880000>; + opp-microvolt-speed2 = <840000>; + }; + + opp-1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <940000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-1488000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1488000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <1000000>; + opp-microvolt-speed2 = <960000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt deleted file mode 100644 index 7deae57a587b..000000000000 --- a/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt +++ /dev/null @@ -1,167 +0,0 @@ -Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings -=================================== - -For some SoCs, the CPU frequency subset and voltage value of each OPP -varies based on the silicon variant in use. Allwinner Process Voltage -Scaling Tables defines the voltage and frequency value based on the -speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver -reads the efuse value from the SoC to provide the OPP framework with -required information. - -Required properties: --------------------- -In 'cpus' nodes: -- operating-points-v2: Phandle to the operating-points-v2 table to use. - -In 'operating-points-v2' table: -- compatible: Should be - - 'allwinner,sun50i-h6-operating-points'. -- nvmem-cells: A phandle pointing to a nvmem-cells node representing the - efuse registers that has information about the speedbin - that is used to select the right frequency/voltage value - pair. Please refer the for nvmem-cells bindings - Documentation/devicetree/bindings/nvmem/nvmem.txt and - also examples below. - -In every OPP node: -- opp-microvolt-<name>: Voltage in micro Volts. - At runtime, the platform can pick a <name> and - matching opp-microvolt-<name> property. - [See: opp.txt] - HW: <name>: - sun50i-h6 speed0 speed1 speed2 - -Example 1: ---------- - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - }; - }; - - cpu_opp_table: opp_table { - compatible = "allwinner,sun50i-h6-operating-points"; - nvmem-cells = <&speedbin_efuse>; - opp-shared; - - opp@480000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <480000000>; - - opp-microvolt-speed0 = <880000>; - opp-microvolt-speed1 = <820000>; - opp-microvolt-speed2 = <800000>; - }; - - opp@720000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <720000000>; - - opp-microvolt-speed0 = <880000>; - opp-microvolt-speed1 = <820000>; - opp-microvolt-speed2 = <800000>; - }; - - opp@816000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <816000000>; - - opp-microvolt-speed0 = <880000>; - opp-microvolt-speed1 = <820000>; - opp-microvolt-speed2 = <800000>; - }; - - opp@888000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <888000000>; - - opp-microvolt-speed0 = <940000>; - opp-microvolt-speed1 = <820000>; - opp-microvolt-speed2 = <800000>; - }; - - opp@1080000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <1080000000>; - - opp-microvolt-speed0 = <1060000>; - opp-microvolt-speed1 = <880000>; - opp-microvolt-speed2 = <840000>; - }; - - opp@1320000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <1320000000>; - - opp-microvolt-speed0 = <1160000>; - opp-microvolt-speed1 = <940000>; - opp-microvolt-speed2 = <900000>; - }; - - opp@1488000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <1488000000>; - - opp-microvolt-speed0 = <1160000>; - opp-microvolt-speed1 = <1000000>; - opp-microvolt-speed2 = <960000>; - }; - }; -.... -soc { -.... - sid: sid@3006000 { - compatible = "allwinner,sun50i-h6-sid"; - reg = <0x03006000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - .... - speedbin_efuse: speed@1c { - reg = <0x1c 4>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt b/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt deleted file mode 100644 index f7514c170a32..000000000000 --- a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt +++ /dev/null @@ -1,10 +0,0 @@ -* ARM Juno R1 PCIe interface - -This PCIe host controller is based on PLDA XpressRICH3-AXI IP -and thus inherits all the common properties defined in plda,xpressrich3-axi.txt -as well as the base properties defined in host-generic-pci.txt. - -Required properties: - - compatible: "arm,juno-r1-pcie" - - dma-coherent: The host controller bridges the AXI transactions into PCIe bus - in a manner that makes the DMA operations to appear coherent to the CPUs. diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml new file mode 100644 index 000000000000..77d3e81a437b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Brcmstb PCIe Host Controller Device Tree Bindings + +maintainers: + - Nicolas Saenz Julienne <nsaenzjulienne@suse.de> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: brcm,bcm2711-pcie # The Raspberry Pi 4 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: PCIe host controller + - description: builtin MSI controller + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + - const: pcie + - const: msi + + ranges: + maxItems: 1 + + dma-ranges: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: sw_pcie + + msi-controller: + description: Identifies the node as an MSI controller. + + msi-parent: + description: MSI controller the device is capable of using. + + brcm,enable-ssc: + description: Indicates usage of spread-spectrum clocking. + type: boolean + +required: + - reg + - dma-ranges + - "#interrupt-cells" + - interrupts + - interrupt-names + - interrupt-map-mask + - interrupt-map + - msi-controller + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + scb { + #address-cells = <2>; + #size-cells = <1>; + pcie0: pcie@7d500000 { + compatible = "brcm,bcm2711-pcie"; + reg = <0x0 0x7d500000 0x9310>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&pcie0>; + msi-controller; + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + brcm,enable-ssc; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted file mode 100644 index 515b2f9542e5..000000000000 --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Synopsys DesignWare PCIe root complex in ECAM shift mode - -In some cases, firmware may already have configured the Synopsys DesignWare -PCIe controller in RC mode with static ATU window mappings that cover all -config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. -In this case, there is no need for the OS to perform any low level setup -of clocks, PHYs or device registers, nor is there any reason for the driver -to reconfigure ATU windows for config and/or IO space accesses at runtime. - -In cases where the IP was synthesized with a minimum ATU window size of -64 KB, it cannot be supported by the generic ECAM driver, because it -requires special config space accessors that filter accesses to device #1 -and beyond on the first bus. - -Required properties: -- compatible: "marvell,armada8k-pcie-ecam" or - "socionext,synquacer-pcie-ecam" or - "snps,dw-pcie-ecam" (must be preceded by a more specific match) - -Please refer to the binding document of "pci-host-ecam-generic" in the -file host-generic-pci.txt for a description of the remaining required -and optional properties. - -Example: - - pcie1: pcie@7f000000 { - compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; - device_type = "pci"; - reg = <0x0 0x7f000000 0x0 0xf00000>; - bus-range = <0x0 0xe>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>, - <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>, - <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; - - #interrupt-cells = <0x1>; - interrupt-map-mask = <0x0 0x0 0x0 0x0>; - interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>; - msi-map = <0x0 &its 0x0 0x10000>; - dma-coherent; - }; diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index 0dcb87d6554f..d6796ef54ea1 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -41,45 +41,3 @@ Hip05 Example (note that Hip06 is the same except compatible): 0x0 0 0 3 &mbigen_pcie 3 12 0x0 0 0 4 &mbigen_pcie 4 13>; }; - -HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description. - -Some BIOSes place the host controller in a mode where it is ECAM -compliant for all devices other than the root complex. In such cases, -the host controller should be described as below. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "hisilicon,hip06-pcie-ecam", or - "hisilicon,hip07-pcie-ecam" - -- reg : Two entries: First the ECAM configuration space for any - other bus underneath the root bus. Second, the base - and size of the HiSilicon host bridge registers include - the RC's own config space. - -Example: - pcie0: pcie@a0090000 { - compatible = "hisilicon,hip06-pcie-ecam"; - reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */ - <0 0xa0090000 0 0x10000>; /* host bridge registers */ - bus-range = <0 31>; - msi-map = <0x0000 &its_dsa 0x0000 0x2000>; - msi-map-mask = <0xffff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000 - 0x01000000 0 0 0 0xb7ff0000 0 0x10000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 - 0x0 0 0 2 &mbigen_pcie0 650 4 - 0x0 0 0 3 &mbigen_pcie0 650 4 - 0x0 0 0 4 &mbigen_pcie0 650 4>; - }; diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt deleted file mode 100644 index 614b594f4e72..000000000000 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt +++ /dev/null @@ -1,101 +0,0 @@ -* Generic PCI host controller - -Firmware-initialised PCI host controllers and PCI emulations, such as the -virtio-pci implementations found in kvmtool and other para-virtualised -systems, do not require driver support for complexities such as regulator -and clock management. In fact, the controller may not even require the -configuration of a control interface by the operating system, instead -presenting a set of fixed windows describing a subset of IO, Memory and -Configuration Spaces. - -Such a controller can be described purely in terms of the standardized device -tree bindings communicated in pci.txt: - - -Properties of the host controller node: - -- compatible : Must be "pci-host-cam-generic" or "pci-host-ecam-generic" - depending on the layout of configuration space (CAM vs - ECAM respectively). - -- device_type : Must be "pci". - -- ranges : As described in IEEE Std 1275-1994, but must provide - at least a definition of non-prefetchable memory. One - or both of prefetchable Memory and IO Space may also - be provided. - -- bus-range : Optional property (also described in IEEE Std 1275-1994) - to indicate the range of bus numbers for this controller. - If absent, defaults to <0 255> (i.e. all buses). - -- #address-cells : Must be 3. - -- #size-cells : Must be 2. - -- reg : The Configuration Space base address and size, as accessed - from the parent bus. The base address corresponds to - the first bus in the "bus-range" property. If no - "bus-range" is specified, this will be bus 0 (the default). - -Properties of the /chosen node: - -- linux,pci-probe-only - : Optional property which takes a single-cell argument. - If '0', then Linux will assign devices in its usual manner, - otherwise it will not try to assign devices and instead use - them as they are configured already. - -Configuration Space is assumed to be memory-mapped (as opposed to being -accessed via an ioport) and laid out with a direct correspondence to the -geography of a PCI bus address by concatenating the various components to -form an offset. - -For CAM, this 24-bit offset is: - - cfg_offset(bus, device, function, register) = - bus << 16 | device << 11 | function << 8 | register - -While ECAM extends this by 4 bits to accommodate 4k of function space: - - cfg_offset(bus, device, function, register) = - bus << 20 | device << 15 | function << 12 | register - -Interrupt mapping is exactly as described in `Open Firmware Recommended -Practice: Interrupt Mapping' and requires the following properties: - -- #interrupt-cells : Must be 1 - -- interrupt-map : <see aforementioned specification> - -- interrupt-map-mask : <see aforementioned specification> - - -Example: - -pci { - compatible = "pci-host-cam-generic" - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0x1>; - - // CPU_PHYSICAL(2) SIZE(2) - reg = <0x0 0x40000000 0x0 0x1000000>; - - // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) - ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>, - <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>; - - - #interrupt-cells = <0x1>; - - // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3) - interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1 - 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1 - 0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1 - 0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>; - - // PCI_DEVICE(3) INT#(1) - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; -} diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file mode 100644 index 000000000000..47353d0cd394 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/host-generic-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic PCI host controller + +maintainers: + - Will Deacon <will@kernel.org> + +description: | + Firmware-initialised PCI host controllers and PCI emulations, such as the + virtio-pci implementations found in kvmtool and other para-virtualised + systems, do not require driver support for complexities such as regulator + and clock management. In fact, the controller may not even require the + configuration of a control interface by the operating system, instead + presenting a set of fixed windows describing a subset of IO, Memory and + Configuration Spaces. + + Configuration Space is assumed to be memory-mapped (as opposed to being + accessed via an ioport) and laid out with a direct correspondence to the + geography of a PCI bus address by concatenating the various components to + form an offset. + + For CAM, this 24-bit offset is: + + cfg_offset(bus, device, function, register) = + bus << 16 | device << 11 | function << 8 | register + + While ECAM extends this by 4 bits to accommodate 4k of function space: + + cfg_offset(bus, device, function, register) = + bus << 20 | device << 15 | function << 12 | register + +properties: + compatible: + description: Depends on the layout of configuration space (CAM vs ECAM + respectively). May also have more specific compatibles. + oneOf: + - description: + PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP + items: + - const: arm,juno-r1-pcie + - const: plda,xpressrich3-axi + - const: pci-host-ecam-generic + - description: | + ThunderX PCI host controller for pass-1.x silicon + + Firmware-initialized PCI host controller to on-chip devices found on + some Cavium ThunderX processors. These devices have ECAM-based config + access, but the BARs are all at fixed addresses. We handle the fixed + addresses by synthesizing Enhanced Allocation (EA) capabilities for + these devices. + const: cavium,pci-host-thunder-ecam + - description: + Cavium ThunderX PEM firmware-initialized PCIe host controller + const: cavium,pci-host-thunder-pem + - description: + HiSilicon Hip06/Hip07 PCIe host bridge in almost-ECAM mode. Some + firmware places the host controller in a mode where it is ECAM + compliant for all devices other than the root complex. + enum: + - hisilicon,hip06-pcie-ecam + - hisilicon,hip07-pcie-ecam + - description: | + In some cases, firmware may already have configured the Synopsys + DesignWare PCIe controller in RC mode with static ATU window mappings + that cover all config, MMIO and I/O spaces in a [mostly] ECAM + compatible fashion. In this case, there is no need for the OS to + perform any low level setup of clocks, PHYs or device registers, nor + is there any reason for the driver to reconfigure ATU windows for + config and/or IO space accesses at runtime. + + In cases where the IP was synthesized with a minimum ATU window size + of 64 KB, it cannot be supported by the generic ECAM driver, because + it requires special config space accessors that filter accesses to + device #1 and beyond on the first bus. + items: + - enum: + - marvell,armada8k-pcie-ecam + - socionext,synquacer-pcie-ecam + - const: snps,dw-pcie-ecam + - description: + CAM or ECAM compliant PCI host controllers without any quirks + enum: + - pci-host-cam-generic + - pci-host-ecam-generic + + reg: + description: + The Configuration Space base address and size, as accessed from the parent + bus. The base address corresponds to the first bus in the "bus-range" + property. If no "bus-range" is specified, this will be bus 0 (the + default). Some host controllers have a 2nd non-compliant address range, + so 2 entries are allowed. + minItems: 1 + maxItems: 2 + + ranges: + description: + As described in IEEE Std 1275-1994, but must provide at least a + definition of non-prefetchable memory. One or both of prefetchable Memory + and IO Space may also be provided. + minItems: 1 + maxItems: 3 + + dma-coherent: true + +required: + - compatible + - reg + - ranges + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + const: arm,juno-r1-pcie + then: + required: + - dma-coherent + + - if: + properties: + compatible: + not: + contains: + enum: + - cavium,pci-host-thunder-pem + - hisilicon,hip06-pcie-ecam + - hisilicon,hip07-pcie-ecam + then: + properties: + reg: + maxItems: 1 + +examples: + - | + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie@40000000 { + compatible = "pci-host-cam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x1>; + + // CPU_PHYSICAL(2) SIZE(2) + reg = <0x0 0x40000000 0x0 0x1000000>; + + // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) + ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>, + <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>; + + #interrupt-cells = <0x1>; + + // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3) + interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>, + < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>, + <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>, + <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>; + + // PCI_DEVICE(3) INT#(1) + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml new file mode 100644 index 000000000000..db605d8a387d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe RC controller on Intel Gateway SoCs + +maintainers: + - Dilip Kota <eswara.kota@linux.intel.com> + +properties: + compatible: + items: + - const: intel,lgm-pcie + - const: snps,dw-pcie + + device_type: + const: pci + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + reg: + items: + - description: Controller control and status registers. + - description: PCIe configuration registers. + - description: Controller application registers. + + reg-names: + items: + - const: dbi + - const: config + - const: app + + ranges: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie + + reset-gpios: + maxItems: 1 + + linux,pci-domain: true + + num-lanes: + maximum: 2 + description: Number of lanes to use for this port. + + '#interrupt-cells': + const: 1 + + interrupt-map-mask: + description: Standard PCI IRQ mapping properties. + + interrupt-map: + description: Standard PCI IRQ mapping properties. + + max-link-speed: + description: Specify PCI Gen for link capability. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 1, 2, 3, 4 ] + - default: 1 + + bus-range: + description: Range of bus numbers associated with this controller. + + reset-assert-ms: + description: | + Delay after asserting reset to the PCIe device. + maximum: 500 + default: 100 + +required: + - compatible + - device_type + - "#address-cells" + - "#size-cells" + - reg + - reg-names + - ranges + - resets + - clocks + - phys + - phy-names + - reset-gpios + - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/intel,lgm-clk.h> + pcie10: pcie@d0e00000 { + compatible = "intel,lgm-pcie", "snps,dw-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0xd0e00000 0x1000>, + <0xd2000000 0x800000>, + <0xd0a41000 0x1000>; + reg-names = "dbi", "config", "app"; + linux,pci-domain = <0>; + max-link-speed = <4>; + bus-range = <0x00 0x08>; + interrupt-parent = <&ioapic1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &ioapic1 27 1>, + <0 0 0 2 &ioapic1 28 1>, + <0 0 0 3 &ioapic1 29 1>, + <0 0 0 4 &ioapic1 30 1>; + ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>; + resets = <&rcu0 0x50 0>; + clocks = <&cgu0 LGM_GCLK_PCIE10>; + phys = <&cb0phy0>; + phy-names = "pcie"; + reset-assert-ms = <500>; + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + num-lanes = <2>; + }; diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt b/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt deleted file mode 100644 index f478874b79ce..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt +++ /dev/null @@ -1,30 +0,0 @@ -* ThunderX PCI host controller for pass-1.x silicon - -Firmware-initialized PCI host controller to on-chip devices found on -some Cavium ThunderX processors. These devices have ECAM-based config -access, but the BARs are all at fixed addresses. We handle the fixed -addresses by synthesizing Enhanced Allocation (EA) capabilities for -these devices. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "cavium,pci-host-thunder-ecam" - -Example: - - pcie@84b000000000 { - compatible = "cavium,pci-host-thunder-ecam"; - device_type = "pci"; - msi-parent = <&its>; - msi-map = <0 &its 0x30000 0x10000>; - bus-range = <0 31>; - #size-cells = <2>; - #address-cells = <3>; - #stream-id-cells = <1>; - reg = <0x84b0 0x00000000 0 0x02000000>; /* Configuration space */ - ranges = <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; /* mem ranges */ - }; diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt b/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt deleted file mode 100644 index f131faea3b7c..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt +++ /dev/null @@ -1,43 +0,0 @@ -* ThunderX PEM PCIe host controller - -Firmware-initialized PCI host controller found on some Cavium -ThunderX processors. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "cavium,pci-host-thunder-pem" - -- reg : Two entries: First the configuration space for down - stream devices base address and size, as accessed - from the parent bus. Second, the register bank of - the PEM device PCIe bridge. - -Example: - - pci@87e0,c2000000 { - compatible = "cavium,pci-host-thunder-pem"; - device_type = "pci"; - msi-parent = <&its>; - msi-map = <0 &its 0x10000 0x10000>; - bus-range = <0x8f 0xc7>; - #size-cells = <2>; - #address-cells = <3>; - - reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ - <0x87e0 0xc2000000 0x0 0x00010000>; /* PEM space */ - ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ - <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ - <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ - <0x03000000 0x87e0 0xc2f00000 0x87e0 0xc2000000 0x00 0x00100000>; /* mem64 PEM BAR4 */ - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */ - <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */ - <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */ - <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */ - }; diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt deleted file mode 100644 index f3f75bfb42bc..000000000000 --- a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt +++ /dev/null @@ -1,12 +0,0 @@ -* PLDA XpressRICH3-AXI host controller - -The PLDA XpressRICH3-AXI host controller can be configured in a manner that -makes it compliant with the SBSA[1] standard published by ARM Ltd. For those -scenarios, the host-generic-pci.txt bindings apply with the following additions -to the compatible property: - -Required properties: - - compatible: should contain "plda,xpressrich3-axi" to identify the IP used. - - -[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/ diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index ada80b01bf0c..981b4de12807 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -11,6 +11,7 @@ - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 + - "qcom,pcie-sdm845" for sdm845 - reg: Usage: required @@ -126,6 +127,18 @@ - "master_bus" AXI Master clock - "slave_bus" AXI Slave clock +-clock-names: + Usage: required for sdm845 + Value type: <stringlist> + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "pipe" PIPE clock + - resets: Usage: required Value type: <prop-encoded-array> @@ -188,6 +201,12 @@ - "pwr" PWR reset - "ahb" AHB reset +- reset-names: + Usage: required for sdm845 + Value type: <stringlist> + Definition: Should contain the following entries + - "pci" PCIe core reset + - power-domains: Usage: required for apq8084 and msm8996/apq8096 Value type: <prop-encoded-array> diff --git a/Documentation/devicetree/bindings/pci/versatile.txt b/Documentation/devicetree/bindings/pci/versatile.txt deleted file mode 100644 index 0a702b13d2ac..000000000000 --- a/Documentation/devicetree/bindings/pci/versatile.txt +++ /dev/null @@ -1,59 +0,0 @@ -* ARM Versatile Platform Baseboard PCI interface - -PCI host controller found on the ARM Versatile PB board's FPGA. - -Required properties: -- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI - controller. -- reg: base addresses and lengths of the PCI controller. There must be 3 - entries: - - Versatile-specific registers - - Self Config space - - Config space -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- bus-range: set to <0 0xff> -- ranges: ranges for the PCI memory and I/O regions -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI properties to define - the mapping of the PCI interface to interrupt numbers. - -Example: - -pci-controller@10001000 { - compatible = "arm,versatile-pci"; - device_type = "pci"; - reg = <0x10001000 0x1000 - 0x41000000 0x10000 - 0x42000000 0x100000>; - bus-range = <0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ - 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ - 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ - - interrupt-map-mask = <0x1800 0 0 7>; - interrupt-map = <0x1800 0 0 1 &sic 28 - 0x1800 0 0 2 &sic 29 - 0x1800 0 0 3 &sic 30 - 0x1800 0 0 4 &sic 27 - - 0x1000 0 0 1 &sic 27 - 0x1000 0 0 2 &sic 28 - 0x1000 0 0 3 &sic 29 - 0x1000 0 0 4 &sic 30 - - 0x0800 0 0 1 &sic 30 - 0x0800 0 0 2 &sic 27 - 0x0800 0 0 3 &sic 28 - 0x0800 0 0 4 &sic 29 - - 0x0000 0 0 1 &sic 29 - 0x0000 0 0 2 &sic 30 - 0x0000 0 0 3 &sic 27 - 0x0000 0 0 4 &sic 28>; -}; diff --git a/Documentation/devicetree/bindings/pci/versatile.yaml b/Documentation/devicetree/bindings/pci/versatile.yaml new file mode 100644 index 000000000000..07a48c27db1f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/versatile.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/versatile.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Platform Baseboard PCI interface + +maintainers: + - Rob Herring <robh@kernel.org> + +description: |+ + PCI host controller found on the ARM Versatile PB board's FPGA. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: arm,versatile-pci + + reg: + items: + - description: Versatile-specific registers + - description: Self Config space + - description: Config space + + ranges: + maxItems: 3 + + "#interrupt-cells": true + + interrupt-map: + maxItems: 16 + + interrupt-map-mask: + items: + - const: 0x1800 + - const: 0 + - const: 0 + - const: 7 + +required: + - compatible + - reg + - ranges + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + +examples: + - | + pci@10001000 { + compatible = "arm,versatile-pci"; + device_type = "pci"; + reg = <0x10001000 0x1000>, + <0x41000000 0x10000>, + <0x42000000 0x100000>; + bus-range = <0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + ranges = + <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */ + <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */ + <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ + + interrupt-map-mask = <0x1800 0 0 7>; + interrupt-map = <0x1800 0 0 1 &sic 28>, + <0x1800 0 0 2 &sic 29>, + <0x1800 0 0 3 &sic 30>, + <0x1800 0 0 4 &sic 27>, + + <0x1000 0 0 1 &sic 27>, + <0x1000 0 0 2 &sic 28>, + <0x1000 0 0 3 &sic 29>, + <0x1000 0 0 4 &sic 30>, + + <0x0800 0 0 1 &sic 30>, + <0x0800 0 0 2 &sic 27>, + <0x0800 0 0 3 &sic 28>, + <0x0800 0 0 4 &sic 29>, + + <0x0000 0 0 1 &sic 29>, + <0x0000 0 0 2 &sic 30>, + <0x0000 0 0 3 &sic 27>, + <0x0000 0 0 4 &sic 28>; + }; + + +... diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun4i-a10-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun4i-a10-usb-phy.yaml new file mode 100644 index 000000000000..020ef9e4c411 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun4i-a10-usb-phy.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + enum: + - allwinner,sun4i-a10-usb-phy + - allwinner,sun7i-a20-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU1 registers + - description: PHY PMU2 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu1 + - const: pmu2 + + clocks: + maxItems: 1 + description: USB PHY bus clock + + clock-names: + const: usb_phy + + resets: + items: + - description: USB OTG reset + - description: USB Host 1 Controller reset + - description: USB Host 2 Controller reset + + reset-names: + items: + - const: usb0_reset + - const: usb1_reset + - const: usb2_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + + usb1_vbus-supply: + description: Regulator controlling USB1 Host controller + + usb2_vbus-supply: + description: Regulator controlling USB2 Host controller + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun4i-a10-ccu.h> + #include <dt-bindings/reset/sun4i-a10-ccu.h> + + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-phy"; + reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; + reg-names = "phy_ctrl", "pmu1", "pmu2"; + clocks = <&ccu CLK_USB_PHY>; + clock-names = "usb_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; + usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; + usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml new file mode 100644 index 000000000000..fd6e126fcf18 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A64 USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,sun50i-a64-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU0 registers + - description: PHY PMU1 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu0 + - const: pmu1 + + clocks: + items: + - description: USB OTG PHY bus clock + - description: USB Host 0 PHY bus clock + + clock-names: + items: + - const: usb0_phy + - const: usb1_phy + + resets: + items: + - description: USB OTG reset + - description: USB Host 1 Controller reset + + reset-names: + items: + - const: usb0_reset + - const: usb1_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + + usb1_vbus-supply: + description: Regulator controlling USB1 Host controller + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun50i-a64-ccu.h> + #include <dt-bindings/reset/sun50i-a64-ccu.h> + + phy@1c19400 { + #phy-cells = <1>; + compatible = "allwinner,sun50i-a64-usb-phy"; + reg = <0x01c19400 0x14>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb-phy.yaml new file mode 100644 index 000000000000..7670411002c9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb-phy.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner H6 USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,sun50i-h6-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU0 registers + - description: PHY PMU3 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu0 + - const: pmu3 + + clocks: + items: + - description: USB OTG PHY bus clock + - description: USB Host PHY bus clock + + clock-names: + items: + - const: usb0_phy + - const: usb3_phy + + resets: + items: + - description: USB OTG reset + - description: USB Host Controller reset + + reset-names: + items: + - const: usb0_reset + - const: usb3_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + + usb3_vbus-supply: + description: Regulator controlling USB3 Host controller + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun50i-h6-ccu.h> + #include <dt-bindings/reset/sun50i-h6-ccu.h> + + phy@5100400 { + #phy-cells = <1>; + compatible = "allwinner,sun50i-h6-usb-phy"; + reg = <0x05100400 0x24>, + <0x05101800 0x4>, + <0x05311800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu3"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY3>; + clock-names = "usb0_phy", + "usb3_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY3>; + reset-names = "usb0_reset", + "usb3_reset"; + usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */ + usb0_vbus-supply = <®_vcc5v>; + usb3_vbus-supply = <®_vcc5v>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun5i-a13-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun5i-a13-usb-phy.yaml new file mode 100644 index 000000000000..9b319381d1ad --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun5i-a13-usb-phy.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A13 USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,sun5i-a13-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU1 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu1 + + clocks: + maxItems: 1 + description: USB OTG PHY bus clock + + clock-names: + const: usb_phy + + resets: + items: + - description: USB OTG reset + - description: USB Host 1 Controller reset + + reset-names: + items: + - const: usb0_reset + - const: usb1_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + + usb1_vbus-supply: + description: Regulator controlling USB1 Host controller + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun5i-ccu.h> + #include <dt-bindings/reset/sun5i-ccu.h> + + phy@1c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10>, <0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb_phy"; + resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", "usb1_reset"; + usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml index fa46670de299..d0b541a461f3 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml @@ -8,14 +8,18 @@ title: Allwinner A31 MIPI D-PHY Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#phy-cells": const: 0 compatible: - const: allwinner,sun6i-a31-mipi-dphy + oneOf: + - const: allwinner,sun6i-a31-mipi-dphy + - items: + - const: allwinner,sun50i-a64-mipi-dphy + - const: allwinner,sun6i-a31-mipi-dphy reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-usb-phy.yaml new file mode 100644 index 000000000000..b0ed01bbf3db --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-usb-phy.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,sun6i-a31-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU1 registers + - description: PHY PMU2 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu1 + - const: pmu2 + + clocks: + items: + - description: USB OTG PHY bus clock + - description: USB Host 0 PHY bus clock + - description: USB Host 1 PHY bus clock + + clock-names: + items: + - const: usb0_phy + - const: usb1_phy + - const: usb2_phy + + resets: + items: + - description: USB OTG reset + - description: USB Host 1 Controller reset + - description: USB Host 2 Controller reset + + reset-names: + items: + - const: usb0_reset + - const: usb1_reset + - const: usb2_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + + usb1_vbus-supply: + description: Regulator controlling USB1 Host controller + + usb2_vbus-supply: + description: Regulator controlling USB2 Host controller + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun6i-a31-ccu.h> + #include <dt-bindings/reset/sun6i-a31-ccu.h> + + phy@1c19400 { + #phy-cells = <1>; + compatible = "allwinner,sun6i-a31-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>; + reg-names = "phy_ctrl", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-a23-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-a23-usb-phy.yaml new file mode 100644 index 000000000000..b0674406f8aa --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-a23-usb-phy.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A23 USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + enum: + - allwinner,sun8i-a23-usb-phy + - allwinner,sun8i-a33-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU1 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu1 + + clocks: + items: + - description: USB OTG PHY bus clock + - description: USB Host 0 PHY bus clock + + clock-names: + items: + - const: usb0_phy + - const: usb1_phy + + resets: + items: + - description: USB OTG reset + - description: USB Host 1 Controller reset + + reset-names: + items: + - const: usb0_reset + - const: usb1_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + + usb1_vbus-supply: + description: Regulator controlling USB1 Host controller + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> + #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> + + phy@1c19400 { + #phy-cells = <1>; + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-a83t-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-a83t-usb-phy.yaml new file mode 100644 index 000000000000..48dc9c834a9b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-a83t-usb-phy.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A83t USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,sun8i-a83t-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU1 registers + - description: PHY PMU2 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu1 + - const: pmu2 + + clocks: + items: + - description: USB OTG PHY bus clock + - description: USB Host 0 PHY bus clock + - description: USB Host 1 PHY bus clock + - description: USB HSIC 12MHz clock + + clock-names: + items: + - const: usb0_phy + - const: usb1_phy + - const: usb2_phy + - const: usb2_hsic_12M + + resets: + items: + - description: USB OTG reset + - description: USB Host 1 Controller reset + - description: USB Host 2 Controller reset + + reset-names: + items: + - const: usb0_reset + - const: usb1_reset + - const: usb2_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + + usb1_vbus-supply: + description: Regulator controlling USB1 Host controller + + usb2_vbus-supply: + description: Regulator controlling USB2 Host controller + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun8i-a83t-ccu.h> + #include <dt-bindings/reset/sun8i-a83t-ccu.h> + + phy@1c19400 { + #phy-cells = <1>; + compatible = "allwinner,sun8i-a83t-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x14>, + <0x01c1b800 0x14>; + reg-names = "phy_ctrl", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_HSIC>, + <&ccu CLK_USB_HSIC_12M>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb2_hsic_12M"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_HSIC>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml new file mode 100644 index 000000000000..60c344585276 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner H3 USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,sun8i-h3-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU0 registers + - description: PHY PMU1 registers + - description: PHY PMU2 registers + - description: PHY PMU3 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu0 + - const: pmu1 + - const: pmu2 + - const: pmu3 + + clocks: + items: + - description: USB OTG PHY bus clock + - description: USB Host 0 PHY bus clock + - description: USB Host 1 PHY bus clock + - description: USB Host 2 PHY bus clock + + clock-names: + items: + - const: usb0_phy + - const: usb1_phy + - const: usb2_phy + - const: usb3_phy + + resets: + items: + - description: USB OTG reset + - description: USB Host 1 Controller reset + - description: USB Host 2 Controller reset + - description: USB Host 3 Controller reset + + reset-names: + items: + - const: usb0_reset + - const: usb1_reset + - const: usb2_reset + - const: usb3_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + + usb1_vbus-supply: + description: Regulator controlling USB1 Host controller + + usb2_vbus-supply: + description: Regulator controlling USB2 Host controller + + usb3_vbus-supply: + description: Regulator controlling USB3 Host controller + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun8i-h3-ccu.h> + #include <dt-bindings/reset/sun8i-h3-ccu.h> + + phy@1c19400 { + #phy-cells = <1>; + compatible = "allwinner,sun8i-h3-usb-phy"; + reg = <0x01c19400 0x2c>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>, + <0x01c1c800 0x4>, + <0x01c1d800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>, + <&ccu CLK_USB_PHY3>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>, + <&ccu RST_USB_PHY3>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + usb3_vbus-supply = <®_usb3_vbus>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-r40-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-r40-usb-phy.yaml new file mode 100644 index 000000000000..a2bb36790fbd --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-r40-usb-phy.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner R40 USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,sun8i-r40-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU0 registers + - description: PHY PMU1 registers + - description: PHY PMU2 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu0 + - const: pmu1 + - const: pmu2 + + clocks: + items: + - description: USB OTG PHY bus clock + - description: USB Host 0 PHY bus clock + - description: USB Host 1 PHY bus clock + + clock-names: + items: + - const: usb0_phy + - const: usb1_phy + - const: usb2_phy + + resets: + items: + - description: USB OTG reset + - description: USB Host 1 Controller reset + - description: USB Host 2 Controller reset + + reset-names: + items: + - const: usb0_reset + - const: usb1_reset + - const: usb2_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + + usb1_vbus-supply: + description: Regulator controlling USB1 Host controller + + usb2_vbus-supply: + description: Regulator controlling USB2 Host controller + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun8i-r40-ccu.h> + #include <dt-bindings/reset/sun8i-r40-ccu.h> + + phy@1c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-v3s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-v3s-usb-phy.yaml new file mode 100644 index 000000000000..eadfd0c9493c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-v3s-usb-phy.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner V3s USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,sun8i-v3s-usb-phy + + reg: + items: + - description: PHY Control registers + - description: PHY PMU0 registers + + reg-names: + items: + - const: phy_ctrl + - const: pmu0 + + clocks: + maxItems: 1 + description: USB OTG PHY bus clock + + clock-names: + const: usb0_phy + + resets: + maxItems: 1 + description: USB OTG reset + + reset-names: + const: usb0_reset + + usb0_id_det-gpios: + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/sun8i-v3s-ccu.h> + #include <dt-bindings/reset/sun8i-v3s-ccu.h> + + phy@1c19400 { + #phy-cells = <1>; + compatible = "allwinner,sun8i-v3s-usb-phy"; + reg = <0x01c19400 0x2c>, + <0x01c1a800 0x4>; + reg-names = "phy_ctrl", + "pmu0"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun9i-a80-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun9i-a80-usb-phy.yaml new file mode 100644 index 000000000000..ded7d6f0a119 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,sun9i-a80-usb-phy.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-usb-phy + + reg: + maxItems: 1 + + clocks: + anyOf: + - description: Main PHY Clock + + - items: + - description: Main PHY clock + - description: HSIC 12MHz clock + - description: HSIC 480MHz clock + + clock-names: + oneOf: + - const: phy + + - items: + - const: phy + - const: hsic_12M + - const: hsic_480M + + resets: + anyOf: + - description: Normal USB PHY reset + + - items: + - description: Normal USB PHY reset + - description: HSIC Reset + + reset-names: + oneOf: + - const: phy + + - items: + - const: phy + - const: hsic + + phy_type: + const: hsic + description: + When absent, the PHY type will be assumed to be normal USB. + + phy-supply: + description: + Regulator that powers VBUS + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +if: + properties: + phy_type: + const: hsic + + required: + - phy_type + +then: + properties: + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + +examples: + - | + #include <dt-bindings/clock/sun9i-a80-usb.h> + #include <dt-bindings/reset/sun9i-a80-usb.h> + + usbphy1: phy@a00800 { + compatible = "allwinner,sun9i-a80-usb-phy"; + reg = <0x00a00800 0x4>; + clocks = <&usb_clocks CLK_USB0_PHY>; + clock-names = "phy"; + resets = <&usb_clocks RST_USB0_PHY>; + reset-names = "phy"; + phy-supply = <®_usb1_vbus>; + #phy-cells = <0>; + }; + + - | + #include <dt-bindings/clock/sun9i-a80-usb.h> + #include <dt-bindings/reset/sun9i-a80-usb.h> + + usbphy3: phy@a02800 { + compatible = "allwinner,sun9i-a80-usb-phy"; + reg = <0x00a02800 0x4>; + clocks = <&usb_clocks CLK_USB2_PHY>, + <&usb_clocks CLK_USB_HSIC>, + <&usb_clocks CLK_USB2_HSIC>; + clock-names = "phy", + "hsic_12M", + "hsic_480M"; + resets = <&usb_clocks RST_USB2_PHY>, + <&usb_clocks RST_USB2_HSIC>; + reset-names = "phy", + "hsic"; + phy_type = "hsic"; + phy-supply = <®_usb3_vbus>; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt index 24a0d06acd1d..698aacbdcfc4 100644 --- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt @@ -1,30 +1,49 @@ Broadcom STB USB PHY Required properties: - - compatible: brcm,brcmstb-usb-phy - - reg: two offset and length pairs. - The first pair specifies a manditory set of memory mapped - registers used for general control of the PHY. - The second pair specifies optional registers used by some of - the SoCs that support USB 3.x - - #phy-cells: Shall be 1 as it expects one argument for setting - the type of the PHY. Possible values are: - - PHY_TYPE_USB2 for USB1.1/2.0 PHY - - PHY_TYPE_USB3 for USB3.x PHY +- compatible: should be one of + "brcm,brcmstb-usb-phy" + "brcm,bcm7216-usb-phy" + "brcm,bcm7211-usb-phy" + +- reg and reg-names properties requirements are specific to the + compatible string. + "brcm,brcmstb-usb-phy": + - reg: 1 or 2 offset and length pairs. One for the base CTRL registers + and an optional pair for systems with USB 3.x support + - reg-names: not specified + "brcm,bcm7216-usb-phy": + - reg: 3 offset and length pairs for CTRL, XHCI_EC and XHCI_GBL + registers + - reg-names: "ctrl", "xhci_ec", "xhci_gbl" + "brcm,bcm7211-usb-phy": + - reg: 5 offset and length pairs for CTRL, XHCI_EC, XHCI_GBL, + USB_PHY and USB_MDIO registers and an optional pair + for the BDC registers + - reg-names: "ctrl", "xhci_ec", "xhci_gbl", "usb_phy", "usb_mdio", "bdc_ec" + +- #phy-cells: Shall be 1 as it expects one argument for setting + the type of the PHY. Possible values are: + - PHY_TYPE_USB2 for USB1.1/2.0 PHY + - PHY_TYPE_USB3 for USB3.x PHY Optional Properties: - clocks : clock phandles. - clock-names: String, clock name. +- interrupts: wakeup interrupt +- interrupt-names: "wakeup" - brcm,ipp: Boolean, Invert Port Power. Possible values are: 0 (Don't invert), 1 (Invert) - brcm,ioc: Boolean, Invert Over Current detection. Possible values are: 0 (Don't invert), 1 (Invert) -NOTE: one or both of the following two properties must be set -- brcm,has-xhci: Boolean indicating the phy has an XHCI phy. -- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy. - dr_mode: String, PHY Device mode. Possible values are: "host", "peripheral ", "drd" or "typec-pd" If this property is not defined, the phy will default to "host" mode. +- brcm,syscon-piarbctl: phandle to syscon for handling config registers +NOTE: one or both of the following two properties must be set +- brcm,has-xhci: Boolean indicating the phy has an XHCI phy. +- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy. + Example: @@ -41,3 +60,27 @@ usbphy_0: usb-phy@f0470200 { clocks = <&usb20>, <&usb30>; clock-names = "sw_usb", "sw_usb3"; }; + +usb-phy@29f0200 { + reg = <0x29f0200 0x200>, + <0x29c0880 0x30>, + <0x29cc100 0x534>, + <0x2808000 0x24>, + <0x2980080 0x8>; + reg-names = "ctrl", + "xhci_ec", + "xhci_gbl", + "usb_phy", + "usb_mdio"; + brcm,ioc = <0x0>; + brcm,ipp = <0x0>; + compatible = "brcm,bcm7211-usb-phy"; + interrupts = <0x30>; + interrupt-parent = <&vpu_intr1_nosec_intc>; + interrupt-names = "wake"; + #phy-cells = <0x1>; + brcm,has-xhci; + syscon-piarbctl = <&syscon_piarbctl>; + clocks = <&scmi_clk 256>; + clock-names = "sw_usb"; +}; diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt index b640845fec67..c03ad2198410 100644 --- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt +++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt @@ -2,6 +2,7 @@ Required properties: - compatible: should be one or more of + "brcm,bcm7216-sata-phy" "brcm,bcm7425-sata-phy" "brcm,bcm7445-sata-phy" "brcm,iproc-ns2-sata-phy" diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml new file mode 100644 index 000000000000..ff7959c21af0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings + +maintainers: + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> + +description: |+ + Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon + node is used to reference the base address of eMMC phy registers. + + The eMMC PHY node should be the child of a syscon node with the + required property: + + - compatible: Should be one of the following: + "intel,lgm-syscon", "syscon" + - reg: + maxItems: 1 + +properties: + compatible: + const: intel,lgm-emmc-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - "#phy-cells" + - compatible + - reg + - clocks + +examples: + - | + sysconf: chiptop@e0200000 { + compatible = "intel,lgm-syscon", "syscon"; + reg = <0xe0200000 0x100>; + + emmc-phy: emmc-phy@a8 { + compatible = "intel,lgm-emmc-phy"; + reg = <0x00a8 0x10>; + clocks = <&emmc>; + #phy-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt index 6e1b47bfce43..03f5939d3d19 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt @@ -2,21 +2,24 @@ Cadence Sierra PHY ----------------------- Required properties: -- compatible: cdns,sierra-phy-t0 -- clocks: Must contain an entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must be "phy_clk" +- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform + Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC. - resets: Must contain an entry for each in reset-names. See ../reset/reset.txt for details. - reset-names: Must include "sierra_reset" and "sierra_apb". "sierra_reset" must control the reset line to the PHY. "sierra_apb" must control the reset line to the APB PHY - interface. + interface ("sierra_apb" is optional). - reg: register range for the PHY. - #address-cells: Must be 1 - #size-cells: Must be 0 Optional properties: +- clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must contain "cmn_refclk_dig_div" and + "cmn_refclk1_dig_div" for configuring the frequency of + the clock to the lanes. "phy_clk" is deprecated. - cdns,autoconf: A boolean property whose presence indicates that the PHY registers will be configured by hardware. If not present, all sub-node optional properties must be diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml index bb0da87bcd84..72aca81e8959 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -13,9 +13,6 @@ properties: "#phy-cells": const: 0 - "#clock-cells": - const: 0 - compatible: enum: - rockchip,px30-dsi-dphy @@ -49,7 +46,6 @@ properties: required: - "#phy-cells" - - "#clock-cells" - compatible - reg - clocks @@ -62,11 +58,10 @@ additionalProperties: false examples: - | dsi_dphy: phy@ff2e0000 { - compatible = "rockchip,px30-video-phy"; + compatible = "rockchip,px30-dsi-dphy"; reg = <0x0 0xff2e0000 0x0 0x10000>; clocks = <&pmucru 13>, <&cru 12>; clock-names = "ref", "pclk"; - #clock-cells = <0>; resets = <&cru 12>; reset-names = "apb"; #phy-cells = <0>; diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index 1c40ccd40ce4..7510830a79bd 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -1,4 +1,4 @@ -Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY +Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY ------------------------------------------------- Required properties: @@ -27,7 +27,7 @@ the PHY specifier identifies the PHY and its meaning is as follows: supports additional fifth PHY: 4 - MIPI CSIS 2. -Samsung EXYNOS SoC series Display Port PHY +Samsung Exynos SoC series Display Port PHY ------------------------------------------------- Required properties: @@ -38,7 +38,7 @@ Required properties: control pmu registers for power isolation. - #phy-cells : from the generic PHY bindings, must be 0; -Samsung S5P/EXYNOS SoC series USB PHY +Samsung S5P/Exynos SoC series USB PHY ------------------------------------------------- Required properties: diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt deleted file mode 100644 index f2e120af17f0..000000000000 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ /dev/null @@ -1,68 +0,0 @@ -Allwinner sun4i USB PHY ------------------------ - -Required properties: -- compatible : should be one of - * allwinner,sun4i-a10-usb-phy - * allwinner,sun5i-a13-usb-phy - * allwinner,sun6i-a31-usb-phy - * allwinner,sun7i-a20-usb-phy - * allwinner,sun8i-a23-usb-phy - * allwinner,sun8i-a33-usb-phy - * allwinner,sun8i-a83t-usb-phy - * allwinner,sun8i-h3-usb-phy - * allwinner,sun8i-r40-usb-phy - * allwinner,sun8i-v3s-usb-phy - * allwinner,sun50i-a64-usb-phy - * allwinner,sun50i-h6-usb-phy -- reg : a list of offset + length pairs -- reg-names : - * "phy_ctrl" - * "pmu0" for H3, V3s, A64 or H6 - * "pmu1" - * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3 - * "pmu3" for sun8i-h3 or sun50i-h6 -- #phy-cells : from the generic phy bindings, must be 1 -- clocks : phandle + clock specifier for the phy clocks -- clock-names : - * "usb_phy" for sun4i, sun5i or sun7i - * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i - * "usb0_phy", "usb1_phy" for sun8i - * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t - * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3 - * "usb0_phy" and "usb3_phy" for sun50i-h6 -- resets : a list of phandle + reset specifier pairs -- reset-names : - * "usb0_reset" - * "usb1_reset" - * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3 - * "usb3_reset" for sun8i-h3 and sun50i-h6 - -Optional properties: -- usb0_id_det-gpios : gpio phandle for reading the otg id pin value -- usb0_vbus_det-gpios : gpio phandle for detecting the presence of usb0 vbus -- usb0_vbus_power-supply: power-supply phandle for usb0 vbus presence detect -- usb0_vbus-supply : regulator phandle for controller usb0 vbus -- usb1_vbus-supply : regulator phandle for controller usb1 vbus -- usb2_vbus-supply : regulator phandle for controller usb2 vbus -- usb3_vbus-supply : regulator phandle for controller usb3 vbus - -Example: - usbphy: phy@01c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-phy"; - /* phy base regs, phy1 pmu reg, phy2 pmu reg */ - reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; - reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; - clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; - reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ - usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - }; diff --git a/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt deleted file mode 100644 index 64f7109aea1f..000000000000 --- a/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt +++ /dev/null @@ -1,37 +0,0 @@ -Allwinner sun9i USB PHY ------------------------ - -Required properties: -- compatible : should be one of - * allwinner,sun9i-a80-usb-phy -- reg : a list of offset + length pairs -- #phy-cells : from the generic phy bindings, must be 0 -- phy_type : "hsic" for HSIC usage; - other values or absence of this property indicates normal USB -- clocks : phandle + clock specifier for the phy clocks -- clock-names : depending on the "phy_type" property, - * "phy" for normal USB - * "hsic_480M", "hsic_12M" for HSIC -- resets : a list of phandle + reset specifier pairs -- reset-names : depending on the "phy_type" property, - * "phy" for normal USB - * "hsic" for HSIC - -Optional Properties: -- phy-supply : from the generic phy bindings, a phandle to a regulator that - provides power to VBUS. - -It is recommended to list all clocks and resets available. -The driver will only use those matching the phy_type. - -Example: - usbphy1: phy@a01800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a01800 0x4>; - clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, - <&usb_phy_clk 3>; - clock-names = "hsic_480M", "hsic_12M", "phy"; - resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; - reset-names = "hsic", "phy"; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml new file mode 100644 index 000000000000..452cee1aed32 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E WIZ (SERDES Wrapper) + +maintainers: + - Kishon Vijay Abraham I <kishon@ti.com> + +properties: + compatible: + enum: + - ti,j721e-wiz-16g + - ti,j721e-wiz-10g + + power-domains: + maxItems: 1 + + clocks: + maxItems: 3 + description: clock-specifier to represent input to the WIZ + + clock-names: + items: + - const: fck + - const: core_ref_clk + - const: ext_ref_clk + + num-lanes: + minimum: 1 + maximum: 4 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#reset-cells": + const: 1 + + ranges: true + + assigned-clocks: + maxItems: 2 + + assigned-clock-parents: + maxItems: 2 + + typec-dir-gpios: + maxItems: 1 + description: + GPIO to signal Type-C cable orientation for lane swap. + If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to + achieve the funtionality of an external type-C plug flip mux. + + typec-dir-debounce-ms: + minimum: 100 + maximum: 1000 + default: 100 + description: + Number of milliseconds to wait before sampling typec-dir-gpio. + If not specified, the default debounce of 100ms will be used. + Type-C spec states minimum CC pin debounce of 100 ms and maximum + of 200 ms. However, some solutions might need more than 200 ms. + +patternProperties: + "^pll[0|1]-refclk$": + type: object + description: | + WIZ node should have subnodes for each of the PLLs present in + the SERDES. + properties: + clocks: + maxItems: 2 + description: Phandle to clock nodes representing the two inputs to PLL. + + "#clock-cells": + const: 0 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + required: + - clocks + - "#clock-cells" + - assigned-clocks + - assigned-clock-parents + + "^cmn-refclk1?-dig-div$": + type: object + description: + WIZ node should have subnodes for each of the PMA common refclock + provided by the SERDES. + properties: + clocks: + maxItems: 1 + description: Phandle to the clock node representing the input to the + divider clock. + + "#clock-cells": + const: 0 + + required: + - clocks + - "#clock-cells" + + "^refclk-dig$": + type: object + description: | + WIZ node should have subnode for refclk_dig to select the reference + clock source for the reference clock used in the PHY and PMA digital + logic. + properties: + clocks: + maxItems: 4 + description: Phandle to four clock nodes representing the inputs to + refclk_dig + + "#clock-cells": + const: 0 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + required: + - clocks + - "#clock-cells" + - assigned-clocks + - assigned-clock-parents + + "^serdes@[0-9a-f]+$": + type: object + description: | + WIZ node should have '1' subnode for the SERDES. It could be either + Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the + bindings specified in + Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt + Torrent SERDES should follow the bindings specified in + Documentation/devicetree/bindings/phy/phy-cadence-dp.txt + +required: + - compatible + - power-domains + - clocks + - clock-names + - num-lanes + - "#address-cells" + - "#size-cells" + - "#reset-cells" + - ranges + +examples: + - | + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + wiz@5000000 { + compatible = "ti,j721e-wiz-16g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; + assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; + num-lanes = <2>; + #reset-cells = <1>; + ranges = <0x5000000 0x5000000 0x10000>; + + pll0-refclk { + clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_pll0_refclk>; + assigned-clock-parents = <&k3_clks 293 13>; + }; + + pll1-refclk { + clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&k3_clks 293 0>; + }; + + cmn-refclk-dig-div { + clocks = <&wiz1_refclk_dig>; + #clock-cells = <0>; + }; + + cmn-refclk1-dig-div { + clocks = <&wiz1_pll1_refclk>; + #clock-cells = <0>; + }; + + refclk-dig { + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&k3_clks 292 11>; + }; + + serdes@5000000 { + compatible = "cdns,ti,sierra-phy-t0"; + reg-names = "serdes"; + reg = <0x5000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&serdes_wiz0 0>; + reset-names = "sierra_reset"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index cd0503b6fe36..bfefd09d8c1e 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 Pin Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#gpio-cells": diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index 064b7dfc4252..3749fa233e87 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -54,8 +54,9 @@ patternProperties: TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, - UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, - WDTRST3, WDTRST4, ] + UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP, + USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, + WDTRST4, ] groups: allOf: - $ref: "/schemas/types.yaml#/definitions/string" @@ -85,8 +86,8 @@ patternProperties: TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0, - UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB, - VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ] + UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, USBA, + USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ] required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml new file mode 100644 index 000000000000..2e31e120395e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8MP IOMUX Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imx8mp-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mp-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart2: uart2grp { + fsl,pins = < + 0x228 0x488 0x5F0 0x0 0x6 0x49 + 0x228 0x488 0x000 0x0 0x0 0x49 + >; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt index 0014d9899797..d9b2100c98e8 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt @@ -10,9 +10,9 @@ GPIO port configuration registers and it is typical to refer to pins using the naming scheme "PxN" where x is a character identifying the GPIO port with which the pin is associated and N is an integer from 0 to 31 identifying the pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and -PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO -ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 -contains 6 GPIO ports, PA to PF, for a total of 192 pins. +PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830 +contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the +jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins. Required properties: @@ -28,6 +28,7 @@ Required properties: - "ingenic,x1000-pinctrl" - "ingenic,x1000e-pinctrl" - "ingenic,x1500-pinctrl" + - "ingenic,x1830-pinctrl" - reg: Address range of the pinctrl registers. @@ -40,6 +41,7 @@ Required properties for sub-nodes (GPIO chips): - "ingenic,jz4770-gpio" - "ingenic,jz4780-gpio" - "ingenic,x1000-gpio" + - "ingenic,x1830-gpio" - reg: The GPIO bank number. - interrupt-controller: Marks the device node as an interrupt controller. - interrupts: Interrupt specifier for the controllers interrupt. diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml new file mode 100644 index 000000000000..cd2b436350ef --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain SoC pinmux & GPIO controller binding + +maintainers: + - Rahul Tanwar <rahul.tanwar@linux.intel.com> + +description: | + Pinmux & GPIO controller controls pin multiplexing & configuration including + GPIO function selection & GPIO attributes configuration. + +properties: + compatible: + const: intel,lgm-io + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + function: true + groups: true + pins: true + pinmux: true + bias-pull-up: true + bias-pull-down: true + drive-strength: true + slew-rate: true + drive-open-drain: true + output-enable: true + + required: + - function + - groups + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl: pinctrl@e2880000 { + compatible = "intel,lgm-io"; + reg = <0xe2880000 0x100000>; + + uart0-pins { + pins = <64>, /* UART_RX0 */ + <65>; /* UART_TX0 */ + function = "CONSOLE_UART0"; + pinmux = <1>, + <1>; + groups = "CONSOLE_UART0"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml deleted file mode 100644 index 240d429f773b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml +++ /dev/null @@ -1,116 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel Lightning Mountain SoC pinmux & GPIO controller binding - -maintainers: - - Rahul Tanwar <rahul.tanwar@linux.intel.com> - -description: | - Pinmux & GPIO controller controls pin multiplexing & configuration including - GPIO function selection & GPIO attributes configuration. - - Please refer to [1] for details of the common pinctrl bindings used by the - client devices. - - [1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -properties: - compatible: - const: intel,lgm-io - - reg: - maxItems: 1 - -# Client device subnode's properties -patternProperties: - '-pins$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - - properties: - function: - $ref: /schemas/types.yaml#/definitions/string - description: - A string containing the name of the function to mux to the group. - - groups: - $ref: /schemas/types.yaml#/definitions/string-array - description: - An array of strings identifying the list of groups. - - pins: - $ref: /schemas/types.yaml#/definitions/uint32-array - description: - List of pins to select with this function. - - pinmux: - description: The applicable mux group. - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32-array" - - bias-pull-up: - type: boolean - - bias-pull-down: - type: boolean - - drive-strength: - description: | - Selects the drive strength for the specified pins in mA. - 0: 2 mA - 1: 4 mA - 2: 8 mA - 3: 12 mA - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1, 2, 3] - - slew-rate: - type: boolean - description: | - Sets slew rate for specified pins. - 0: slow slew - 1: fast slew - - drive-open-drain: - type: boolean - - output-enable: - type: boolean - - required: - - function - - groups - - additionalProperties: false - -required: - - compatible - - reg - -additionalProperties: false - -examples: - # Pinmux controller node - - | - pinctrl: pinctrl@e2880000 { - compatible = "intel,lgm-pinctrl"; - reg = <0xe2880000 0x100000>; - - uart0-pins { - pins = <64>, /* UART_RX0 */ - <65>; /* UART_TX0 */ - function = "CONSOLE_UART0"; - pinmux = <1>, - <1>; - groups = "CONSOLE_UART0"; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml b/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml index 777623a57fd5..732d9075560b 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml @@ -114,7 +114,7 @@ properties: specific binding for the hardware defines whether the entries are integers or strings, and their meaning. - group: + groups: $ref: /schemas/types.yaml#/definitions/string-array description: the group to apply the properties to, if the driver supports diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt index b5767ee82ee6..6ffeac9801df 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt @@ -125,8 +125,9 @@ to specify in a pin configuration subnode: mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs, - qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, - qup10, qup11, qup12, qup13, qup14, qup15, sdc1_tb, + qspi_data, qup00, qup01, qup02_i2c, qup02_uart, qup03, + qup04_i2c, qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, + qup12, qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt new file mode 100644 index 000000000000..ab0d5ebbad4e --- /dev/null +++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt @@ -0,0 +1,130 @@ +QCOM CPR (Core Power Reduction) + +CPR (Core Power Reduction) is a technology to reduce core power on a CPU +or other device. Each OPP of a device corresponds to a "corner" that has +a range of valid voltages for a particular frequency. While the device is +running at a particular frequency, CPR monitors dynamic factors such as +temperature, etc. and suggests adjustments to the voltage to save power +and meet silicon characteristic requirements. + +- compatible: + Usage: required + Value type: <string> + Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404 + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: base address and size of the rbcpr register region + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the CPR interrupt + +- clocks: + Usage: required + Value type: <prop-encoded-array> + Definition: phandle to the reference clock + +- clock-names: + Usage: required + Value type: <stringlist> + Definition: must be "ref" + +- vdd-apc-supply: + Usage: required + Value type: <phandle> + Definition: phandle to the vdd-apc-supply regulator + +- #power-domain-cells: + Usage: required + Value type: <u32> + Definition: should be 0 + +- operating-points-v2: + Usage: required + Value type: <phandle> + Definition: A phandle to the OPP table containing the + performance states supported by the CPR + power domain + +- acc-syscon: + Usage: optional + Value type: <phandle> + Definition: phandle to syscon for writing ACC settings + +- nvmem-cells: + Usage: required + Value type: <phandle> + Definition: phandle to nvmem cells containing the data + that makes up a fuse corner, for each fuse corner. + As well as the CPR fuse revision. + +- nvmem-cell-names: + Usage: required + Value type: <stringlist> + Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2", + "cpr_quotient_offset3", "cpr_init_voltage1", + "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1", + "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1", + "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision" + for qcs404. + +Example: + + cpr_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + }; + cpr_opp2: opp2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + }; + cpr_opp3: opp3 { + opp-level = <3>; + qcom,opp-fuse-level = <3>; + }; + }; + + power-controller@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; + clocks = <&xo_board>; + clock-names = "ref"; + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + acc-syscon = <&tcsr>; + + nvmem-cells = <&cpr_efuse_quot_offset1>, + <&cpr_efuse_quot_offset2>, + <&cpr_efuse_quot_offset3>, + <&cpr_efuse_init_voltage1>, + <&cpr_efuse_init_voltage2>, + <&cpr_efuse_init_voltage3>, + <&cpr_efuse_quot1>, + <&cpr_efuse_quot2>, + <&cpr_efuse_quot3>, + <&cpr_efuse_ring1>, + <&cpr_efuse_ring2>, + <&cpr_efuse_ring3>, + <&cpr_efuse_revision>; + nvmem-cell-names = "cpr_quotient_offset1", + "cpr_quotient_offset2", + "cpr_quotient_offset3", + "cpr_init_voltage1", + "cpr_init_voltage2", + "cpr_init_voltage3", + "cpr_quotient1", + "cpr_quotient2", + "cpr_quotient3", + "cpr_ring_osc1", + "cpr_ring_osc2", + "cpr_ring_osc3", + "cpr_fuse_revision"; + }; diff --git a/Documentation/devicetree/bindings/power/supply/battery.txt b/Documentation/devicetree/bindings/power/supply/battery.txt index 5c913d4cf36c..3049cf88bdcf 100644 --- a/Documentation/devicetree/bindings/power/supply/battery.txt +++ b/Documentation/devicetree/bindings/power/supply/battery.txt @@ -35,6 +35,10 @@ Optional Properties: for each of the battery capacity lookup table. The first temperature value specifies the OCV table 0, and the second temperature value specifies the OCV table 1, and so on. + - resistance-temp-table: An array providing the temperature in degree Celsius + and corresponding battery internal resistance percent, which is used to look + up the resistance percent according to current temperature to get a accurate + batterty internal resistance in different temperatures. Battery properties are named, where possible, for the corresponding elements in enum power_supply_property, defined in @@ -61,6 +65,7 @@ Example: ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, ...; ocv-capacity-table-1 = <4200000 100>, <4185000 95>, <4113000 90>, ...; ocv-capacity-table-2 = <4250000 100>, <4200000 95>, <4185000 90>, ...; + resistance-temp-table = <20 100>, <10 90>, <0 80>, <(-10) 60>; }; charger: charger@11 { diff --git a/Documentation/devicetree/bindings/power/supply/bq25890.txt b/Documentation/devicetree/bindings/power/supply/bq25890.txt index dc0568933359..dc9c8f76e06c 100644 --- a/Documentation/devicetree/bindings/power/supply/bq25890.txt +++ b/Documentation/devicetree/bindings/power/supply/bq25890.txt @@ -1,11 +1,14 @@ Binding for TI bq25890 Li-Ion Charger -This driver will support the bq25896 and the bq25890. There are other ICs -in the same family but those have not been tested. +This driver will support the bq25892, the bq25896 and the bq25890. There are +other ICs in the same family but those have not been tested. Required properties: - compatible: Should contain one of the following: * "ti,bq25890" + * "ti,bq25892" + * "ti,bq25895" + * "ti,bq25896" - reg: integer, i2c address of the device. - ti,battery-regulation-voltage: integer, maximum charging voltage (in uV); - ti,charge-current: integer, maximum charging current (in uA); diff --git a/Documentation/devicetree/bindings/power/supply/max17040_battery.txt b/Documentation/devicetree/bindings/power/supply/max17040_battery.txt new file mode 100644 index 000000000000..4e0186b8380f --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/max17040_battery.txt @@ -0,0 +1,33 @@ +max17040_battery +~~~~~~~~~~~~~~~~ + +Required properties : + - compatible : "maxim,max17040" or "maxim,max77836-battery" + - reg: i2c slave address + +Optional properties : +- maxim,alert-low-soc-level : The alert threshold that sets the state of + charge level (%) where an interrupt is + generated. Can be configured from 1 up to 32 + (%). If skipped the power up default value of + 4 (%) will be used. +- interrupts : Interrupt line see Documentation/devicetree/ + bindings/interrupt-controller/interrupts.txt +- wakeup-source : This device has wakeup capabilities. Use this + property to use alert low SOC level interrupt + as wake up source. + +Optional properties support interrupt functionality for alert low state of +charge level, present in some ICs in the same family, and should be used with +compatible "maxim,max77836-battery". + +Example: + + battery-fuel-gauge@36 { + compatible = "maxim,max77836-battery"; + reg = <0x36>; + maxim,alert-low-soc-level = <10>; + interrupt-parent = <&gpio7>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; diff --git a/Documentation/devicetree/bindings/power/supply/max17042_battery.txt b/Documentation/devicetree/bindings/power/supply/max17042_battery.txt index 3f3894aaeebc..f34c5daae9af 100644 --- a/Documentation/devicetree/bindings/power/supply/max17042_battery.txt +++ b/Documentation/devicetree/bindings/power/supply/max17042_battery.txt @@ -2,7 +2,11 @@ max17042_battery ~~~~~~~~~~~~~~~~ Required properties : - - compatible : "maxim,max17042" + - compatible : one of the following + * "maxim,max17042" + * "maxim,max17047" + * "maxim,max17050" + * "maxim,max17055" Optional properties : - maxim,rsns-microohm : Resistance of rsns resistor in micro Ohms diff --git a/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt b/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt index 0a5705b8b592..b6359b590383 100644 --- a/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt +++ b/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt @@ -13,6 +13,8 @@ Required properties: - io-channel-names: Should be "bat-temp" or "charge-vol". - nvmem-cells: A phandle to the calibration cells provided by eFuse device. - nvmem-cell-names: Should be "fgu_calib". +- sprd,calib-resistance-micro-ohms: Specify the real resistance of coulomb counter + chip in micro Ohms. - monitored-battery: Phandle of battery characteristics devicetree node. See Documentation/devicetree/bindings/power/supply/battery.txt @@ -52,5 +54,6 @@ Example: nvmem-cells = <&fgu_calib>; nvmem-cell-names = "fgu_calib"; monitored-battery = <&bat>; + sprd,calib-resistance-micro-ohms = <21500>; }; }; diff --git a/Documentation/devicetree/bindings/ptp/ptp-ines.txt b/Documentation/devicetree/bindings/ptp/ptp-ines.txt new file mode 100644 index 000000000000..4c242bd1ce9c --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/ptp-ines.txt @@ -0,0 +1,35 @@ +ZHAW InES PTP time stamping IP core + +The IP core needs two different kinds of nodes. The control node +lives somewhere in the memory map and specifies the address of the +control registers. There can be up to three port handles placed as +attributes of PHY nodes. These associate a particular MII bus with a +port index within the IP core. + +Required properties of the control node: + +- compatible: "ines,ptp-ctrl" +- reg: physical address and size of the register bank + +Required format of the port handle within the PHY node: + +- timestamper: provides control node reference and + the port channel within the IP core + +Example: + + tstamper: timestamper@60000000 { + compatible = "ines,ptp-ctrl"; + reg = <0x60000000 0x80>; + }; + + ethernet@80000000 { + ... + mdio { + ... + ethernet-phy@3 { + ... + timestamper = <&tstamper 0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/ptp/timestamper.txt b/Documentation/devicetree/bindings/ptp/timestamper.txt new file mode 100644 index 000000000000..fc550ce4d4ea --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/timestamper.txt @@ -0,0 +1,42 @@ +Time stamps from MII bus snooping devices + +This binding supports non-PHY devices that snoop the MII bus and +provide time stamps. In contrast to PHY time stamping drivers (which +can simply attach their interface directly to the PHY instance), stand +alone MII time stamping drivers use this binding to specify the +connection between the snooping device and a given network interface. + +Non-PHY MII time stamping drivers typically talk to the control +interface over another bus like I2C, SPI, UART, or via a memory mapped +peripheral. This controller device is associated with one or more +time stamping channels, each of which snoops on a MII bus. + +The "timestamper" property lives in a phy node and links a time +stamping channel from the controller device to that phy's MII bus. + +Example: + + tstamper: timestamper@10000000 { + compatible = "ines,ptp-ctrl"; + reg = <0x10000000 0x80>; + }; + + ethernet@20000000 { + mdio { + ethernet-phy@1 { + timestamper = <&tstamper 0>; + }; + }; + }; + + ethernet@30000000 { + mdio { + ethernet-phy@2 { + timestamper = <&tstamper 1>; + }; + }; + }; + +In this example, time stamps from the MII bus attached to phy@1 will +appear on time stamp channel 0 (zero), and those from phy@2 appear on +channel 1. diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 0ac52f83a58c..4a21fe77ee1d 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 PWM Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#pwm-cells": diff --git a/Documentation/devicetree/bindings/regulator/mp8859.txt b/Documentation/devicetree/bindings/regulator/mp8859.txt new file mode 100644 index 000000000000..74ad69730989 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mp8859.txt @@ -0,0 +1,22 @@ +Monolithic Power Systems MP8859 voltage regulator + +Required properties: +- compatible: "mps,mp8859"; +- reg: I2C slave address. + +Optional subnode for regulator: "mp8859_dcdc", using common regulator +bindings given in <Documentation/devicetree/bindings/regulator/regulator.txt>. + +Example: + + mp8859: regulator@66 { + compatible = "mps,mp8859"; + reg = <0x66>; + dc_12v: mp8859_dcdc { + regulator-name = "dc_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/mps,mpq7920.yaml b/Documentation/devicetree/bindings/regulator/mps,mpq7920.yaml new file mode 100644 index 000000000000..a682af0dc67e --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mps,mpq7920.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mps,mpq7920.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Monolithic Power System MPQ7920 PMIC + +maintainers: + - Saravanan Sekar <sravanhome@gmail.com> + +properties: + $nodename: + pattern: "pmic@[0-9a-f]{1,2}" + compatible: + enum: + - mps,mpq7920 + + reg: + maxItems: 1 + + regulators: + type: object + allOf: + - $ref: regulator.yaml# + description: | + list of regulators provided by this controller, must be named + after their hardware counterparts BUCK[1-4], one LDORTC, and LDO[2-5] + + properties: + mps,switch-freq: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint8" + enum: [ 0, 1, 2, 3 ] + default: 2 + description: | + switching frequency must be one of following corresponding value + 1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz + + patternProperties: + "^ldo[1-4]$": + type: object + allOf: + - $ref: regulator.yaml# + + "^ldortc$": + type: object + allOf: + - $ref: regulator.yaml# + + "^buck[1-4]$": + type: object + allOf: + - $ref: regulator.yaml# + + properties: + mps,buck-softstart: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint8" + enum: [ 0, 1, 2, 3 ] + description: | + defines the soft start time of this buck, must be one of the following + corresponding values 150us, 300us, 610us, 920us + + mps,buck-phase-delay: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint8" + enum: [ 0, 1, 2, 3 ] + description: | + defines the phase delay of this buck, must be one of the following + corresponding values 0deg, 90deg, 180deg, 270deg + + mps,buck-ovp-disable: + type: boolean + description: | + disables over voltage protection of this buck + + additionalProperties: false + additionalProperties: false + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@69 { + compatible = "mps,mpq7920"; + reg = <0x69>; + + regulators { + mps,switch-freq = /bits/ 8 <1>; + + buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <3587500>; + regulator-min-microamp = <460000>; + regulator-max-microamp = <7600000>; + regulator-boot-on; + mps,buck-ovp-disable; + mps,buck-phase-delay = /bits/ 8 <2>; + mps,buck-softstart = /bits/ 8 <1>; + }; + + ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <3587500>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml new file mode 100644 index 000000000000..71ce032b8cf8 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/rohm,bd71828-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD71828 Power Management Integrated Circuit regulators + +maintainers: + - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + +description: | + This module is part of the ROHM BD71828 MFD device. For more details + see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml. + + The regulator controller is represented as a sub-node of the PMIC node + on the device tree. + + Regulator nodes should be named to BUCK_<number> and LDO_<number>. + The valid names for BD71828 regulator nodes are + BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6, BUCK7 + LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7 + +patternProperties: + "^LDO[1-7]$": + type: object + allOf: + - $ref: regulator.yaml# + description: + Properties for single LDO regulator. + + properties: + regulator-name: + pattern: "^ldo[1-7]$" + description: + should be "ldo1", ..., "ldo7" + + "^BUCK[1-7]$": + type: object + allOf: + - $ref: regulator.yaml# + description: + Properties for single BUCK regulator. + + properties: + regulator-name: + pattern: "^buck[1-7]$" + description: + should be "buck1", ..., "buck7" + + rohm,dvs-run-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 3300000 + description: + PMIC default "RUN" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + rohm,dvs-idle-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 3300000 + description: + PMIC default "IDLE" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + rohm,dvs-suspend-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 3300000 + description: + PMIC default "SUSPEND" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + rohm,dvs-lpsr-voltage: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 3300000 + description: + PMIC default "LPSR" state voltage in uV. See below table for + bucks which support this. 0 means disabled. + + # Supported default DVS states: + # buck | run | idle | suspend | lpsr + #-------------------------------------------------------------- + # 1, 2, 6, and 7 | supported | supported | supported (*) + #-------------------------------------------------------------- + # 3, 4, and 5 | supported (**) + #-------------------------------------------------------------- + # + #(*) LPSR and SUSPEND states use same voltage but both states have own + # enable / + # disable settings. Voltage 0 can be specified for a state to make + # regulator disabled on that state. + # + #(**) All states use same voltage but have own enable / disable + # settings. Voltage 0 can be specified for a state to make + # regulator disabled on that state. + + required: + - regulator-name + additionalProperties: false +additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-booster.txt b/Documentation/devicetree/bindings/regulator/st,stm32-booster.txt deleted file mode 100644 index 479ad4c8758e..000000000000 --- a/Documentation/devicetree/bindings/regulator/st,stm32-booster.txt +++ /dev/null @@ -1,18 +0,0 @@ -STM32 BOOSTER - Booster for ADC analog input switches - -Some STM32 devices embed a 3.3V booster supplied by Vdda, that can be used -to supply ADC analog input switches. - -Required properties: -- compatible: Should be one of: - "st,stm32h7-booster" - "st,stm32mp1-booster" -- st,syscfg: Phandle to system configuration controller. -- vdda-supply: Phandle to the vdda input analog voltage. - -Example: - booster: regulator-booster { - compatible = "st,stm32mp1-booster"; - st,syscfg = <&syscfg>; - vdda-supply = <&vdda>; - }; diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml new file mode 100644 index 000000000000..64f1183ce841 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/st,stm32-booster.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 booster for ADC analog input switches bindings + +maintainers: + - Fabrice Gasnier <fabrice.gasnier@st.com> + +description: | + Some STM32 devices embed a 3.3V booster supplied by Vdda, that can be used + to supply ADC analog input switches. + +allOf: + - $ref: "regulator.yaml#" + +properties: + compatible: + enum: + - st,stm32h7-booster + - st,stm32mp1-booster + + st,syscfg: + allOf: + - $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: phandle to system configuration controller. + + vdda-supply: + description: phandle to the vdda input analog voltage. + +required: + - compatible + - st,syscfg + - vdda-supply + +examples: + - | + regulator-booster { + compatible = "st,stm32mp1-booster"; + st,syscfg = <&syscfg>; + vdda-supply = <&vdda>; + }; + +... diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt deleted file mode 100644 index 5ddb8500a929..000000000000 --- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt +++ /dev/null @@ -1,20 +0,0 @@ -STM32 VREFBUF - Voltage reference buffer - -Some STM32 devices embed a voltage reference buffer which can be used as -voltage reference for ADCs, DACs and also as voltage reference for external -components through the dedicated VREF+ pin. - -Required properties: -- compatible: Must be "st,stm32-vrefbuf". -- reg: Offset and length of VREFBUF register set. -- clocks: Must contain an entry for peripheral clock. - -Example: - vrefbuf: regulator@58003c00 { - compatible = "st,stm32-vrefbuf"; - reg = <0x58003C00 0x8>; - clocks = <&rcc VREF_CK>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - vdda-supply = <&vdda>; - }; diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml new file mode 100644 index 000000000000..33cdaeb25aee --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/st,stm32-vrefbuf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Voltage reference buffer bindings + +description: | + Some STM32 devices embed a voltage reference buffer which can be used as + voltage reference for ADCs, DACs and also as voltage reference for external + components through the dedicated VREF+ pin. + +maintainers: + - Fabrice Gasnier <fabrice.gasnier@st.com> + +allOf: + - $ref: "regulator.yaml#" + +properties: + compatible: + const: st,stm32-vrefbuf + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + vdda-supply: + description: phandle to the vdda input analog voltage. + +required: + - compatible + - reg + - clocks + - vdda-supply + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; + vdda-supply = <&vdda>; + }; + +... + diff --git a/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.txt b/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.txt deleted file mode 100644 index e372dd3f0c8a..000000000000 --- a/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.txt +++ /dev/null @@ -1,43 +0,0 @@ -STM32MP1 PWR Regulators ------------------------ - -Available Regulators in STM32MP1 PWR block are: - - reg11 for regulator 1V1 - - reg18 for regulator 1V8 - - usb33 for the swtich USB3V3 - -Required properties: -- compatible: Must be "st,stm32mp1,pwr-reg" -- list of child nodes that specify the regulator reg11, reg18 or usb33 - initialization data for defined regulators. The definition for each of - these nodes is defined using the standard binding for regulators found at - Documentation/devicetree/bindings/regulator/regulator.txt. -- vdd-supply: phandle to the parent supply/regulator node for vdd input -- vdd_3v3_usbfs-supply: phandle to the parent supply/regulator node for usb33 - -Example: - -pwr_regulators: pwr@50001000 { - compatible = "st,stm32mp1,pwr-reg"; - reg = <0x50001000 0x10>; - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; - - reg11: reg11 { - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - reg18: reg18 { - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usb33: usb33 { - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml b/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml new file mode 100644 index 000000000000..8d8f38fe85dc --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/st,stm32mp1-pwr-reg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32MP1 PWR voltage regulators + +maintainers: + - Pascal Paillet <p.paillet@st.com> + +properties: + compatible: + const: st,stm32mp1,pwr-reg + + reg: + maxItems: 1 + + vdd-supply: + description: Input supply phandle(s) for vdd input + + vdd_3v3_usbfs-supply: + description: Input supply phandle(s) for vdd_3v3_usbfs input + +patternProperties: + "^(reg11|reg18|usb33)$": + type: object + + allOf: + - $ref: "regulator.yaml#" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>; + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + + reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index acf18d170352..c0d83865e933 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -50,6 +50,8 @@ properties: description: Should contain the WWDG1 watchdog reset interrupt maxItems: 1 + wakeup-source: true + mboxes: description: This property is required only if the rpmsg/virtio functionality is used. diff --git a/Documentation/devicetree/bindings/reset/allwinner,sun6i-a31-clock-reset.yaml b/Documentation/devicetree/bindings/reset/allwinner,sun6i-a31-clock-reset.yaml new file mode 100644 index 000000000000..001c0d2a8c1f --- /dev/null +++ b/Documentation/devicetree/bindings/reset/allwinner,sun6i-a31-clock-reset.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 Peripheral Reset Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +select: + properties: + compatible: + contains: + enum: + - allwinner,sun6i-a31-ahb1-reset + - allwinner,sun6i-a31-clock-reset + + # The PRCM on the A31 and A23 will have the reg property missing, + # since it's set at the upper level node, and will be validated by + # PRCM's schema. Make sure we only validate standalone nodes. + required: + - compatible + - reg + +properties: + "#reset-cells": + const: 1 + description: > + This additional argument passed to that reset controller is the + offset of the bit controlling this particular reset line in the + register. + + compatible: + enum: + - allwinner,sun6i-a31-ahb1-reset + - allwinner,sun6i-a31-clock-reset + + reg: + maxItems: 1 + +required: + - "#reset-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + ahb1_rst: reset@1c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-ahb1-reset"; + reg = <0x01c202c0 0xc>; + }; + + - | + apbs_rst: reset@80014b0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x080014b0 0x4>; + }; + +... diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt deleted file mode 100644 index 4ca66c96fe97..000000000000 --- a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt +++ /dev/null @@ -1,21 +0,0 @@ -Allwinner sunxi Peripheral Reset Controller -=========================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be one of the following: - "allwinner,sun6i-a31-ahb1-reset" - "allwinner,sun6i-a31-clock-reset" -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -example: - -ahb1_rst: reset@1c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-reset"; - reg = <0x01c202c0 0xc>; -}; diff --git a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt index 6e5341b4f891..ee59409640f2 100644 --- a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt +++ b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt @@ -22,6 +22,6 @@ Example: }; ðernet_switch { - resets = <&reset>; + resets = <&reset 26>; reset-names = "switch"; }; diff --git a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt index c223e54452da..802523196ee5 100644 --- a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt +++ b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt @@ -2,6 +2,7 @@ HWRNG support for the iproc-rng200 driver Required properties: - compatible : Must be one of: + "brcm,bcm2711-rng200" "brcm,bcm7211-rng200" "brcm,bcm7278-rng200" "brcm,iproc-rng200" diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun4i-a10-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun4i-a10-rtc.yaml index 46d69c32b89b..478b0234e8fa 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun4i-a10-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun4i-a10-rtc.yaml @@ -11,7 +11,7 @@ allOf: maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index d7a57ec4a640..37c2a601c3fa 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -8,7 +8,7 @@ title: Allwinner A31 RTC Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#clock-cells": diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt deleted file mode 100644 index 5d3791e789c6..000000000000 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt +++ /dev/null @@ -1,17 +0,0 @@ -Atmel AT91RM9200 Real Time Clock - -Required properties: -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: rtc alarm/event interrupt -- clocks: phandle to input clock. - -Example: - -rtc@fffffe00 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffe00 0x100>; - interrupts = <1 4 7>; - clocks = <&clk32k>; -}; diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml new file mode 100644 index 000000000000..02bbfe726c62 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/atmel,at91rm9200-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel AT91 RTC Device Tree Bindings + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +properties: + compatible: + enum: + - atmel,at91rm9200-rtc + - atmel,at91sam9x5-rtc + - atmel,sama5d4-rtc + - atmel,sama5d2-rtc + - microchip,sam9x60-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + rtc@fffffe00 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffe00 0x100>; + interrupts = <1 4 7>; + clocks = <&clk32k>; + }; +... diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt deleted file mode 100644 index 130ca5b98253..000000000000 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt +++ /dev/null @@ -1,61 +0,0 @@ -STM32 Real Time Clock - -Required properties: -- compatible: can be one of the following: - - "st,stm32-rtc" for devices compatible with stm32(f4/f7). - - "st,stm32h7-rtc" for devices compatible with stm32h7. - - "st,stm32mp1-rtc" for devices compatible with stm32mp1. -- reg: address range of rtc register set. -- clocks: can use up to two clocks, depending on part used: - - "rtc_ck": RTC clock source. - - "pclk": RTC APB interface clock. - It is not present on stm32(f4/f7). - It is required on stm32(h7/mp1). -- clock-names: must be "rtc_ck" and "pclk". - It is required on stm32(h7/mp1). -- interrupts: rtc alarm interrupt. On stm32mp1, a second interrupt is required - for rtc alarm wakeup interrupt. -- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to - access control register at offset, and change the dbp (Disable Backup - Protection) bit represented by the mask, mandatory to disable/enable backup - domain (RTC registers) write protection. - It is required on stm32(f4/f7/h7). - -Optional properties (to override default rtc_ck parent clock on stm32(f4/f7/h7): -- assigned-clocks: reference to the rtc_ck clock entry. -- assigned-clock-parents: phandle of the new parent clock of rtc_ck. - -Example: - - rtc: rtc@40002800 { - compatible = "st,stm32-rtc"; - reg = <0x40002800 0x400>; - clocks = <&rcc 1 CLK_RTC>; - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSE>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - st,syscfg = <&pwrcfg 0x00 0x100>; - }; - - rtc: rtc@58004000 { - compatible = "st,stm32h7-rtc"; - reg = <0x58004000 0x400>; - clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; - clock-names = "pclk", "rtc_ck"; - assigned-clocks = <&rcc RTC_CK>; - assigned-clock-parents = <&rcc LSE_CK>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - interrupt-names = "alarm"; - st,syscfg = <&pwrcfg 0x00 0x100>; - }; - - rtc: rtc@5c004000 { - compatible = "st,stm32mp1-rtc"; - reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; - clock-names = "pclk", "rtc_ck"; - interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_NONE>, - <&exti 19 1>; - }; diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml new file mode 100644 index 000000000000..0a54296d7218 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Real Time Clock Bindings + +maintainers: + - Gabriel Fernandez <gabriel.fernandez@st.com> + +properties: + compatible: + enum: + - st,stm32-rtc + - st,stm32h7-rtc + - st,stm32mp1-rtc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: rtc_ck + + interrupts: + maxItems: 1 + + st,syscfg: + allOf: + - $ref: "/schemas/types.yaml#/definitions/phandle-array" + - items: + minItems: 3 + maxItems: 3 + description: | + Phandle/offset/mask triplet. The phandle to pwrcfg used to + access control register at offset, and change the dbp (Disable Backup + Protection) bit represented by the mask, mandatory to disable/enable backup + domain (RTC registers) write protection. + + assigned-clocks: + description: | + override default rtc_ck parent clock reference to the rtc_ck clock entry + maxItems: 1 + + assigned-clock-parents: + description: | + override default rtc_ck parent clock phandle of the new parent clock of rtc_ck + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: st,stm32-rtc + + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + + clock-names: false + + required: + - st,syscfg + + - if: + properties: + compatible: + contains: + const: st,stm32h7-rtc + + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + + required: + - clock-names + - st,syscfg + + - if: + properties: + compatible: + contains: + const: st,stm32mp1-rtc + + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + + assigned-clocks: false + assigned-clock-parents: false + + required: + - clock-names + +required: + - compatible + - reg + - clocks + - interrupts + +examples: + - | + #include <dt-bindings/mfd/stm32f4-rcc.h> + #include <dt-bindings/clock/stm32fx-clock.h> + rtc@40002800 { + compatible = "st,stm32-rtc"; + reg = <0x40002800 0x400>; + clocks = <&rcc 1 CLK_RTC>; + assigned-clocks = <&rcc 1 CLK_RTC>; + assigned-clock-parents = <&rcc 1 CLK_LSE>; + interrupt-parent = <&exti>; + interrupts = <17 1>; + st,syscfg = <&pwrcfg 0x00 0x100>; + }; + + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + clocks = <&rcc RTCAPB>, <&rcc RTC>; + clock-names = "pclk", "rtc_ck"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; + +... diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index f5f5ab0fd14e..c904e2e68332 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -10,6 +10,8 @@ Required properties: on i.MX7ULP SoC with 32-bit little-endian register organization - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated on i.MX8QXP SoC with 32-bit little-endian register organization + - "fsl,imx8qm-lpuart" for lpuart compatible with the one integrated + on i.MX8QM SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt index b92592dff6dd..a7fe93efc4a5 100644 --- a/Documentation/devicetree/bindings/serial/rs485.txt +++ b/Documentation/devicetree/bindings/serial/rs485.txt @@ -1,31 +1 @@ -* RS485 serial communications - -The RTS signal is capable of automatically controlling line direction for -the built-in half-duplex mode. -The properties described hereafter shall be given to a half-duplex capable -UART node. - -Optional properties: -- rs485-rts-delay: prop-encoded-array <a b> where: - * a is the delay between rts signal and beginning of data sent in milliseconds. - it corresponds to the delay before sending data. - * b is the delay between end of data sent and rts signal in milliseconds - it corresponds to the delay after sending data and actual release of the line. - If this property is not specified, <0 0> is assumed. -- rs485-rts-active-low: drive RTS low when sending (default is high). -- linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485 - feature at boot time. It can be disabled later with proper ioctl. -- rs485-rx-during-tx: empty property that enables the receiving of data even - while sending data. - -RS485 example for Atmel USART: - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x4000>; - interrupts = <7>; - atmel,use-dma-rx; - atmel,use-dma-tx; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 200>; // in milliseconds - }; - +See rs485.yaml diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml new file mode 100644 index 000000000000..d4beaf11222d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/rs485.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/rs485.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RS485 serial communications Bindings + +description: The RTS signal is capable of automatically controlling + line direction for the built-in half-duplex mode. + The properties described hereafter shall be given to a + half-duplex capable UART node. + +maintainers: + - Rob Herring <robh@kernel.org> + +properties: + rs485-rts-delay: + description: prop-encoded-array <a b> + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + items: + - description: + Delay between rts signal and beginning of data sent in milliseconds. + It corresponds to the delay before sending data. + default: 0 + maximum: 1000 + - description: + Delay between end of data sent and rts signal in milliseconds. + It corresponds to the delay after sending data and actual release of the line. + default: 0 + maximum: 1000 + + rs485-rts-active-low: + description: drive RTS low when sending (default is high). + $ref: /schemas/types.yaml#/definitions/flag + + linux,rs485-enabled-at-boot-time: + description: enables the rs485 feature at boot time. It can be disabled later with proper ioctl. + $ref: /schemas/types.yaml#/definitions/flag + + rs485-rx-during-tx: + description: enables the receiving of data even while sending data. + $ref: /schemas/types.yaml#/definitions/flag diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml new file mode 100644 index 000000000000..238c44192d31 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Erwan Le Ray <erwan.leray@st.com> + +title: STMicroelectronics STM32 USART bindings + +allOf: + - $ref: rs485.yaml + +properties: + compatible: + enum: + - st,stm32-uart + - st,stm32f7-uart + - st,stm32h7-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + label: + description: label associated with this uart + + st,hw-flow-ctrl: + description: enable hardware flow control + $ref: /schemas/types.yaml#/definitions/flag + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + items: + enum: [ rx, tx ] + minItems: 1 + maxItems: 2 + + wakeup-source: true + + rs485-rts-delay: true + rs485-rts-active-low: true + linux,rs485-enabled-at-boot-time: true + rs485-rx-during-tx: true + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + usart1: serial@40011000 { + compatible = "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 0 164>; + dmas = <&dma2 2 4 0x414 0x0>, + <&dma2 7 4 0x414 0x0>; + dma-names = "rx", "tx"; + rs485-rts-active-low; + }; + +... diff --git a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt deleted file mode 100644 index 8620f7fcbd50..000000000000 --- a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt +++ /dev/null @@ -1,57 +0,0 @@ -* STMicroelectronics STM32 USART - -Required properties: -- compatible: can be either: - - "st,stm32-uart", - - "st,stm32f7-uart", - - "st,stm32h7-uart". - depending is compatible with stm32(f4), stm32f7 or stm32h7. -- reg: The address and length of the peripheral registers space -- interrupts: - - The interrupt line for the USART instance, - - An optional wake-up interrupt. -- clocks: The input clock of the USART instance - -Optional properties: -- resets: Must contain the phandle to the reset controller. -- pinctrl: The reference on the pins configuration -- st,hw-flow-ctrl: bool flag to enable hardware flow control. -- rs485-rts-delay, rs485-rx-during-tx, rs485-rts-active-low, - linux,rs485-enabled-at-boot-time: see rs485.txt. -- dmas: phandle(s) to DMA controller node(s). Refer to stm32-dma.txt -- dma-names: "rx" and/or "tx" -- wakeup-source: bool flag to indicate this device has wakeup capabilities -- interrupt-names, if optional wake-up interrupt is used, should be: - - "event": the name for the interrupt line of the USART instance - - "wakeup" the name for the optional wake-up interrupt - - -Examples: -usart4: serial@40004c00 { - compatible = "st,stm32-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&clk_pclk1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart4>; -}; - -usart2: serial@40004400 { - compatible = "st,stm32-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&clk_pclk1>; - st,hw-flow-ctrl; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rtscts>; -}; - -usart1: serial@40011000 { - compatible = "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 0 164>; - dmas = <&dma2 2 4 0x414 0x0>, - <&dma2 7 4 0x414 0x0>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/serio/allwinner,sun4i-a10-ps2.yaml b/Documentation/devicetree/bindings/serio/allwinner,sun4i-a10-ps2.yaml index ee9712f1c97d..2ecab8ed702a 100644 --- a/Documentation/devicetree/bindings/serio/allwinner,sun4i-a10-ps2.yaml +++ b/Documentation/devicetree/bindings/serio/allwinner,sun4i-a10-ps2.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 PS2 Host Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> description: A20 PS2 is dual role controller (PS2 host and PS2 device). These diff --git a/Documentation/devicetree/bindings/slimbus/bus.txt b/Documentation/devicetree/bindings/slimbus/bus.txt index 52fa6426388c..bbe871f82a8b 100644 --- a/Documentation/devicetree/bindings/slimbus/bus.txt +++ b/Documentation/devicetree/bindings/slimbus/bus.txt @@ -32,6 +32,10 @@ Required property for SLIMbus child node if it is present: Product Code, shall be in lower case hexadecimal with leading zeroes suppressed +Optional property for SLIMbus child node if it is present: +- slim-ifc-dev - Should be phandle to SLIMBus Interface device. + Required for devices which deal with streams. + SLIMbus example for Qualcomm's slimbus manager component: slim@28080000 { @@ -43,8 +47,14 @@ SLIMbus example for Qualcomm's slimbus manager component: #address-cells = <2>; #size-cell = <0>; + codec_ifd: ifd@0,0{ + compatible = "slim217,60"; + reg = <0 0>; + }; + codec: wcd9310@1,0{ compatible = "slim217,60"; reg = <1 0>; + slim-ifc-dev = <&codec_ifd>; }; }; diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt new file mode 100644 index 000000000000..59758ccce809 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt @@ -0,0 +1,59 @@ +* Texas Instruments K3 NavigatorSS Ring Accelerator + +The Ring Accelerator (RA) is a machine which converts read/write accesses +from/to a constant address into corresponding read/write accesses from/to a +circular data structure in memory. The RA eliminates the need for each DMA +controller which needs to access ring elements from having to know the current +state of the ring (base address, current offset). The DMA controller +performs a read or write access to a specific address range (which maps to the +source interface on the RA) and the RA replaces the address for the transaction +with a new address which corresponds to the head or tail element of the ring +(head for reads, tail for writes). + +The Ring Accelerator is a hardware module that is responsible for accelerating +management of the packet queues. The K3 SoCs can have more than one RA instances + +Required properties: +- compatible : Must be "ti,am654-navss-ringacc"; +- reg : Should contain register location and length of the following + named register regions. +- reg-names : should be + "rt" - The RA Ring Real-time Control/Status Registers + "fifos" - The RA Queues Registers + "proxy_gcfg" - The RA Proxy Global Config Registers + "proxy_target" - The RA Proxy Datapath Registers +- ti,num-rings : Number of rings supported by RA +- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range +- ti,sci : phandle on TI-SCI compatible System controller node +- ti,sci-dev-id : TI-SCI device id of the ring accelerator +- msi-parent : phandle for "ti,sci-inta" interrupt controller + +Optional properties: + -- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability + issue software w/a + +Example: + +ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", + "proxy_gcfg", "proxy_target"; + ti,num-rings = <818>; + ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ + ti,dma-ring-reset-quirk; + ti,sci = <&dmsc>; + ti,sci-dev-id = <187>; + msi-parent = <&inta_main_udmass>; +}; + +client: + +dma_ipx: dma_ipx@<addr> { + ... + ti,ringacc = <&ringacc>; + ... +} diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml index b8f89c7258eb..ea1d2efb2aaa 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 Codec Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#sound-dai-cells": diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index eb3992138eec..112ae00d63c1 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 I2S Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#sound-dai-cells": diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml index 38d4cede0860..444a432912bb 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml @@ -10,7 +10,7 @@ maintainers: - Chen-Yu Tsai <wens@csie.org> - Liam Girdwood <lgirdwood@gmail.com> - Mark Brown <broonie@kernel.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#sound-dai-cells": diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun50i-a64-codec-analog.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun50i-a64-codec-analog.yaml index f290eb72a878..3b764415c9ab 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun50i-a64-codec-analog.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun50i-a64-codec-analog.yaml @@ -8,7 +8,7 @@ title: Allwinner A64 Analog Codec Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml index 85305b4c2729..9718358826ab 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml @@ -8,7 +8,7 @@ title: Allwinner A23 Analog Codec Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml index 5e7cc05bbff1..55d28268d2f4 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml @@ -8,7 +8,7 @@ title: Allwinner A33 Codec Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#sound-dai-cells": diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt index 3080979350a0..fa4545ed81ca 100644 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt @@ -17,6 +17,9 @@ Required properties: * "arb" : memory ARB line (required) * "rst" : dedicated device reset line (optional) - #sound-dai-cells: must be 0. +- amlogic,fifo-depth: The size of the controller's fifo in bytes. This + is useful for determining certain configuration such + as the flush threshold of the fifo Example of FRDDR A on the A113 SoC: @@ -27,4 +30,5 @@ frddr_a: audio-controller@1c0 { interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; resets = <&arb AXG_ARB_FRDDR_A>; + fifo-depth = <512>; }; diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt index 1d4d9f938689..cb9a25165503 100644 --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt @@ -8,7 +8,12 @@ three substreams within totally 10 channels. Required properties: - - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc". + - compatible : Compatible list, should contain one of the following + compatibles: + "fsl,imx35-asrc", + "fsl,imx53-asrc", + "fsl,imx8qm-asrc", + "fsl,imx8qxp-asrc", - reg : Offset and length of the register set for the device. @@ -35,6 +40,11 @@ Required properties: - fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends. + - fsl,asrc-clk-map : Defines clock map used in driver. which is required + by imx8qm/imx8qxp platform + <0> - select the map for asrc0 in imx8qm/imx8qxp + <1> - select the map for asrc1 in imx8qm/imx8qxp + Optional properties: - big-endian : If this property is absent, the little endian mode diff --git a/Documentation/devicetree/bindings/sound/gtm601.txt b/Documentation/devicetree/bindings/sound/gtm601.txt index 5efc8c068de0..efa32a486c4a 100644 --- a/Documentation/devicetree/bindings/sound/gtm601.txt +++ b/Documentation/devicetree/bindings/sound/gtm601.txt @@ -1,10 +1,16 @@ GTM601 UMTS modem audio interface CODEC -This device has no configuration interface. Sample rate is fixed - 8kHz. +This device has no configuration interface. The sample rate and channels are +based on the compatible string + "option,gtm601" = 8kHz mono + "broadmobi,bm818" = 48KHz stereo Required properties: - - compatible : "option,gtm601" + - compatible : one of + "option,gtm601" + "broadmobi,bm818" + Example: diff --git a/Documentation/devicetree/bindings/sound/ingenic,codec.yaml b/Documentation/devicetree/bindings/sound/ingenic,codec.yaml new file mode 100644 index 000000000000..eb4be86464bb --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ingenic,codec.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ingenic,codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic JZ47xx internal codec DT bindings + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +properties: + $nodename: + pattern: '^audio-codec@.*' + + compatible: + oneOf: + - const: ingenic,jz4770-codec + - const: ingenic,jz4725b-codec + - const: ingenic,jz4740-codec + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: aic + + '#sound-dai-cells': + const: 0 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#sound-dai-cells' + +examples: + - | + #include <dt-bindings/clock/jz4740-cgu.h> + codec: audio-codec@10020080 { + compatible = "ingenic,jz4740-codec"; + reg = <0x10020080 0x8>; + #sound-dai-cells = <0>; + clocks = <&cgu JZ4740_CLK_AIC>; + clock-names = "aic"; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/ingenic,jz4725b-codec.txt b/Documentation/devicetree/bindings/sound/ingenic,jz4725b-codec.txt deleted file mode 100644 index 05adc0d47b13..000000000000 --- a/Documentation/devicetree/bindings/sound/ingenic,jz4725b-codec.txt +++ /dev/null @@ -1,20 +0,0 @@ -Ingenic JZ4725B codec controller - -Required properties: -- compatible : "ingenic,jz4725b-codec" -- reg : codec registers location and length -- clocks : phandle to the AIC clock. -- clock-names: must be set to "aic". -- #sound-dai-cells: Must be set to 0. - -Example: - -codec: audio-codec@100200a4 { - compatible = "ingenic,jz4725b-codec"; - reg = <0x100200a4 0x8>; - - #sound-dai-cells = <0>; - - clocks = <&cgu JZ4725B_CLK_AIC>; - clock-names = "aic"; -}; diff --git a/Documentation/devicetree/bindings/sound/ingenic,jz4740-codec.txt b/Documentation/devicetree/bindings/sound/ingenic,jz4740-codec.txt deleted file mode 100644 index 1ffcade87e7b..000000000000 --- a/Documentation/devicetree/bindings/sound/ingenic,jz4740-codec.txt +++ /dev/null @@ -1,20 +0,0 @@ -Ingenic JZ4740 codec controller - -Required properties: -- compatible : "ingenic,jz4740-codec" -- reg : codec registers location and length -- clocks : phandle to the AIC clock. -- clock-names: must be set to "aic". -- #sound-dai-cells: Must be set to 0. - -Example: - -codec: audio-codec@10020080 { - compatible = "ingenic,jz4740-codec"; - reg = <0x10020080 0x8>; - - #sound-dai-cells = <0>; - - clocks = <&cgu JZ4740_CLK_AIC>; - clock-names = "aic"; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,sdm845.txt b/Documentation/devicetree/bindings/sound/qcom,sdm845.txt index 408c4837e6d5..ca8c89e88bfa 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sdm845.txt +++ b/Documentation/devicetree/bindings/sound/qcom,sdm845.txt @@ -5,7 +5,10 @@ This binding describes the SDM845 sound card, which uses qdsp for audio. - compatible: Usage: required Value type: <stringlist> - Definition: must be "qcom,sdm845-sndcard" + Definition: must be one of this + "qcom,sdm845-sndcard" + "qcom,db845c-sndcard" + "lenovo,yoga-c630-sndcard" - audio-routing: Usage: Optional diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml new file mode 100644 index 000000000000..38eaf0c028f9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd934x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Qualcomm WCD9340/WCD9341 Audio Codec + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + Qualcomm WCD9340/WCD9341 Codec is a standalone Hi-Fi audio codec IC. + It has in-built Soundwire controller, pin controller, interrupt mux and + supports both I2S/I2C and SLIMbus audio interfaces. + +properties: + compatible: + const: slim217,250 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + description: GPIO spec for reset line to use + maxItems: 1 + + slim-ifc-dev: true + + clocks: + maxItems: 1 + + clock-names: + const: extclk + + vdd-buck-supply: + description: A reference to the 1.8V buck supply + + vdd-buck-sido-supply: + description: A reference to the 1.8V SIDO buck supply + + vdd-rx-supply: + description: A reference to the 1.8V rx supply + + vdd-tx-supply: + description: A reference to the 1.8V tx supply + + vdd-vbat-supply: + description: A reference to the vbat supply + + vdd-io-supply: + description: A reference to the 1.8V I/O supply + + vdd-micbias-supply: + description: A reference to the micbias supply + + qcom,micbias1-microvolt: + description: micbias1 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias2-microvolt: + description: micbias2 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias3-microvolt: + description: micbias3 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias4-microvolt: + description: micbias4 voltage + minimum: 1800000 + maximum: 2850000 + + clock-output-names: + const: mclk + + clock-frequency: + description: Clock frequency of output clk in Hz + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + '#clock-cells': + const: 0 + + '#sound-dai-cells': + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + gpio@42: + type: object + allOf: + - $ref: ../gpio/qcom,wcd934x-gpio.yaml# + +patternProperties: + "^.*@[0-9a-f]+$": + type: object + description: | + WCD934x subnode for each slave devices. Bindings of each subnodes + depends on the specific driver providing the functionality and + documented in their respective bindings. + + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - reset-gpios + - slim-ifc-dev + - interrupts + - interrupt-controller + - clock-frequency + - clock-output-names + - qcom,micbias1-microvolt + - qcom,micbias2-microvolt + - qcom,micbias3-microvolt + - qcom,micbias4-microvolt + - "#interrupt-cells" + - "#clock-cells" + - "#sound-dai-cells" + - "#address-cells" + - "#size-cells" + +examples: + - | + codec@1,0{ + compatible = "slim217,250"; + reg = <1 0>; + reset-gpios = <&tlmm 64 0>; + slim-ifc-dev = <&wcd9340_ifd>; + #sound-dai-cells = <1>; + interrupt-parent = <&tlmm>; + interrupts = <54 4>; + interrupt-controller; + #interrupt-cells = <1>; + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + clock-names = "extclk"; + clocks = <&rpmhcc 2>; + + #address-cells = <1>; + #size-cells = <1>; + + gpio@42 { + compatible = "qcom,wcd9340-gpio"; + reg = <0x42 0x2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/qcom,wsa881x.yaml b/Documentation/devicetree/bindings/sound/qcom,wsa881x.yaml new file mode 100644 index 000000000000..ea44d03e58ca --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,wsa881x.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wsa881x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Qualcomm WSA8810/WSA8815 Class-D Smart Speaker Amplifier + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + WSA8810 is a class-D smart speaker amplifier and WSA8815 + is a high-output power class-D smart speaker amplifier. + Their primary operating mode uses a SoundWire digital audio + interface. This binding is for SoundWire interface. + +properties: + compatible: + const: sdw10217201000 + + reg: + maxItems: 1 + + powerdown-gpios: + description: GPIO spec for Powerdown/Shutdown line to use + maxItems: 1 + + '#thermal-sensor-cells': + const: 0 + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - reg + - powerdown-gpios + - "#thermal-sensor-cells" + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + soundwire@c2d0000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x0c2d0000 0x2000>; + + speaker@0,1 { + compatible = "sdw10217201000"; + reg = <0 1>; + powerdown-gpios = <&wcdpinctrl 2 0>; + #thermal-sensor-cells = <0>; + #sound-dai-cells = <0>; + }; + + speaker@0,2 { + compatible = "sdw10217201000"; + reg = <0 2>; + powerdown-gpios = <&wcdpinctrl 2 0>; + #thermal-sensor-cells = <0>; + #sound-dai-cells = <0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/rt1015.txt b/Documentation/devicetree/bindings/sound/rt1015.txt new file mode 100644 index 000000000000..fcfd02d8d32f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rt1015.txt @@ -0,0 +1,17 @@ +RT1015 Mono Class D Audio Amplifier + +This device supports I2C only. + +Required properties: + +- compatible : "realtek,rt1015". + +- reg : The I2C address of the device. + + +Example: + +rt1015: codec@28 { + compatible = "realtek,rt1015"; + reg = <0x28>; +}; diff --git a/Documentation/devicetree/bindings/sound/rt5645.txt b/Documentation/devicetree/bindings/sound/rt5645.txt index a03f9a872a71..41a62fd2ae1f 100644 --- a/Documentation/devicetree/bindings/sound/rt5645.txt +++ b/Documentation/devicetree/bindings/sound/rt5645.txt @@ -10,6 +10,10 @@ Required properties: - interrupts : The CODEC's interrupt output. +- avdd-supply: Power supply for AVDD, providing 1.8V. + +- cpvdd-supply: Power supply for CPVDD, providing 3.5V. + Optional properties: - hp-detect-gpios: diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt new file mode 100644 index 000000000000..436547f3b155 --- /dev/null +++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt @@ -0,0 +1,167 @@ +Qualcomm SoundWire Controller Bindings + + +This binding describes the Qualcomm SoundWire Controller along with its +board specific bus parameters. + +- compatible: + Usage: required + Value type: <stringlist> + Definition: must be "qcom,soundwire-v<MAJOR>.<MINOR>.<STEP>", + Example: + "qcom,soundwire-v1.3.0" + "qcom,soundwire-v1.5.0" + "qcom,soundwire-v1.6.0" +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of SoundWire controller + address space. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the SoundWire Controller IRQ + +- clock-names: + Usage: required + Value type: <stringlist> + Definition: should be "iface" for SoundWire Controller interface clock + +- clocks: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the SoundWire Controller interface clock + +- #sound-dai-cells: + Usage: required + Value type: <u32> + Definition: must be 1 for digital audio interfaces on the controller. + +- qcom,dout-ports: + Usage: required + Value type: <u32> + Definition: must be count of data out ports + +- qcom,din-ports: + Usage: required + Value type: <u32> + Definition: must be count of data in ports + +- qcom,ports-offset1: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify payload transport window offset1 of each + data port. Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-offset2: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify payload transport window offset2 of each + data port. Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-sinterval-low: + Usage: required + Value type: <prop-encoded-array> + Definition: should be sample interval low of each data port. + Out ports followed by In ports. Used for Sample Interval + calculation. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-word-length: + Usage: optional + Value type: <prop-encoded-array> + Definition: should be size of payload channel sample. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-block-pack-mode: + Usage: optional + Value type: <prop-encoded-array> + Definition: should be 0 or 1 to indicate the block packing mode. + 0 to indicate Blocks are per Channel + 1 to indicate Blocks are per Port. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-block-group-count: + Usage: optional + Value type: <prop-encoded-array> + Definition: should be in range 1 to 4 to indicate how many sample + intervals are combined into a payload. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-lane-control: + Usage: optional + Value type: <prop-encoded-array> + Definition: should be in range 0 to 7 to identify which data lane + the data port uses. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-hstart: + Usage: optional + Value type: <prop-encoded-array> + Definition: should be number identifying lowerst numbered coloum in + SoundWire Frame, i.e. left edge of the Transport sub-frame + for each port. Values between 0 and 15 are valid. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-hstop: + Usage: optional + Value type: <prop-encoded-array> + Definition: should be number identifying highest numbered coloum in + SoundWire Frame, i.e. the right edge of the Transport + sub-frame for each port. Values between 0 and 15 are valid. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,dports-type: + Usage: optional + Value type: <prop-encoded-array> + Definition: should be one of the following types + 0 for reduced port + 1 for simple ports + 2 for full port + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +Note: + More Information on detail of encoding of these fields can be +found in MIPI Alliance SoundWire 1.0 Specifications. + += SoundWire devices +Each subnode of the bus represents SoundWire device attached to it. +The properties of these nodes are defined by the individual bindings. + += EXAMPLE +The following example represents a SoundWire controller on DB845c board +which has controller integrated inside WCD934x codec on SDM845 SoC. + +soundwire: soundwire@c85 { + compatible = "qcom,soundwire-v1.3.0"; + reg = <0xc85 0x20>; + interrupts = <20 IRQ_TYPE_EDGE_RISING>; + clocks = <&wcc>; + clock-names = "iface"; + #sound-dai-cells = <1>; + qcom,dports-type = <0>; + qcom,dout-ports = <6>; + qcom,din-ports = <2>; + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; + + /* Left Speaker */ + left{ + .... + }; + + /* Right Speaker */ + right{ + .... + }; +}; diff --git a/Documentation/devicetree/bindings/soundwire/soundwire-controller.yaml b/Documentation/devicetree/bindings/soundwire/soundwire-controller.yaml index 1b43993bccdb..330924b8618e 100644 --- a/Documentation/devicetree/bindings/soundwire/soundwire-controller.yaml +++ b/Documentation/devicetree/bindings/soundwire/soundwire-controller.yaml @@ -69,6 +69,7 @@ examples: reg = <0 1>; powerdown-gpios = <&wcdpinctrl 2 0>; #thermal-sensor-cells = <0>; + #sound-dai-cells = <0>; }; speaker@0,2 { @@ -76,6 +77,7 @@ examples: reg = <0 2>; powerdown-gpios = <&wcdpinctrl 2 0>; #thermal-sensor-cells = <0>; + #sound-dai-cells = <0>; }; }; diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml index 6d1329c28170..8036499112f5 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml @@ -11,7 +11,7 @@ allOf: maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#address-cells": true diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index f36c46d236d7..0565dc49e449 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -11,7 +11,7 @@ allOf: maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#address-cells": true diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt index 1fd9a4406a1d..b98203ca656d 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt @@ -12,6 +12,7 @@ Required properties: - clock-names: Should be "clk_apb5". - pinctrl-names : a pinctrl state named "default" must be defined. - pinctrl-0 : phandle referencing pin configuration of the device. + - resets : phandle to the reset control for this device. - cs-gpios: Specifies the gpio pins to be used for chipselects. See: Documentation/devicetree/bindings/spi/spi-bus.txt @@ -19,16 +20,6 @@ Optional properties: - clock-frequency : Input clock frequency to the PSPI block in Hz. Default is 25000000 Hz. -Aliases: -- All the SPI controller nodes should be represented in the aliases node using - the following format 'spi{n}' withe the correct numbered in "aliases" node. - -Example: - -aliases { - spi0 = &spi0; -}; - spi0: spi@f0200000 { compatible = "nuvoton,npcm750-pspi"; reg = <0xf0200000 0x1000>; @@ -39,5 +30,6 @@ spi0: spi@f0200000 { interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM7XX_CLK_APB5>; clock-names = "clk_apb5"; + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1> cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; }; diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml index 732339275848..1e0ca6ccf64b 100644 --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml @@ -111,7 +111,7 @@ patternProperties: spi-rx-bus-width: allOf: - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 1, 2, 4 ] + - enum: [ 1, 2, 4, 8 ] - default: 1 description: Bus width to the SPI bus used for MISO. @@ -123,7 +123,7 @@ patternProperties: spi-tx-bus-width: allOf: - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 1, 2, 4 ] + - enum: [ 1, 2, 4, 8 ] - default: 1 description: Bus width to the SPI bus used for MOSI. diff --git a/Documentation/devicetree/bindings/spi/spi-stm32.txt b/Documentation/devicetree/bindings/spi/spi-stm32.txt deleted file mode 100644 index d82755c63eaf..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-stm32.txt +++ /dev/null @@ -1,62 +0,0 @@ -STMicroelectronics STM32 SPI Controller - -The STM32 SPI controller is used to communicate with external devices using -the Serial Peripheral Interface. It supports full-duplex, half-duplex and -simplex synchronous serial communication with external devices. It supports -from 4 to 32-bit data size. Although it can be configured as master or slave, -only master is supported by the driver. - -Required properties: -- compatible: Should be one of: - "st,stm32h7-spi" - "st,stm32f4-spi" -- reg: Offset and length of the device's register set. -- interrupts: Must contain the interrupt id. -- clocks: Must contain an entry for spiclk (which feeds the internal clock - generator). -- #address-cells: Number of cells required to define a chip select address. -- #size-cells: Should be zero. - -Optional properties: -- resets: Must contain the phandle to the reset controller. -- A pinctrl state named "default" may be defined to set pins in mode of - operation for SPI transfer. -- dmas: DMA specifiers for tx and rx dma. DMA fifo mode must be used. See the - STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt. -- dma-names: DMA request names should include "tx" and "rx" if present. -- cs-gpios: list of GPIO chip selects. See the SPI bus bindings, - Documentation/devicetree/bindings/spi/spi-bus.txt - - -Child nodes represent devices on the SPI bus - See ../spi/spi-bus.txt - -Optional properties: -- st,spi-midi-ns: Only for STM32H7, (Master Inter-Data Idleness) minimum time - delay in nanoseconds inserted between two consecutive data - frames. - - -Example: - spi2: spi@40003800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40003800 0x400>; - interrupts = <36>; - clocks = <&rcc SPI2_CK>; - resets = <&rcc 1166>; - dmas = <&dmamux1 0 39 0x400 0x01>, - <&dmamux1 1 40 0x400 0x01>; - dma-names = "rx", "tx"; - pinctrl-0 = <&spi2_pins_b>; - pinctrl-names = "default"; - cs-gpios = <&gpioa 11 0>; - - aardvark@0 { - compatible = "totalphase,aardvark"; - reg = <0>; - spi-max-frequency = <4000000>; - st,spi-midi-ns = <4000>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt index f99c733d75c1..5bb4a8f1df7a 100644 --- a/Documentation/devicetree/bindings/spi/spi_atmel.txt +++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt @@ -1,7 +1,7 @@ Atmel SPI device Required properties: -- compatible : should be "atmel,at91rm9200-spi". +- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi". - reg: Address and length of the register set for the device - interrupts: Should contain spi interrupt - cs-gpios: chipselects (optional for SPI controller version >= 2 with the diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml new file mode 100644 index 000000000000..f0d979664f07 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 SPI Controller bindings + +description: | + The STM32 SPI controller is used to communicate with external devices using + the Serial Peripheral Interface. It supports full-duplex, half-duplex and + simplex synchronous serial communication with external devices. It supports + from 4 to 32-bit data size. + +maintainers: + - Erwan Leray <erwan.leray@st.com> + - Fabrice Gasnier <fabrice.gasnier@st.com> + +allOf: + - $ref: "spi-controller.yaml#" + - if: + properties: + compatible: + contains: + const: st,stm32f4-spi + + then: + properties: + st,spi-midi-ns: false + +properties: + compatible: + enum: + - st,stm32f4-spi + - st,stm32h7-spi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + description: | + DMA specifiers for tx and rx dma. DMA fifo mode must be used. See + the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32-dma.txt. + items: + - description: rx DMA channel + - description: tx DMA channel + + dma-names: + items: + - const: rx + - const: tx + +patternProperties: + "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$": + type: object + # SPI slave nodes must be children of the SPI master node and can + # contain the following properties. + properties: + st,spi-midi-ns: + description: | + Only for STM32H7, (Master Inter-Data Idleness) minimum time + delay in nanoseconds inserted between two consecutive data frames. + +required: + - compatible + - reg + - clocks + - interrupts + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + spi@4000b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + dmas = <&dmamux1 0 39 0x400 0x05>, + <&dmamux1 1 40 0x400 0x05>; + dma-names = "rx", "tx"; + cs-gpios = <&gpioa 11 0>; + + aardvark@0 { + compatible = "totalphase,aardvark"; + reg = <0>; + spi-max-frequency = <4000000>; + st,spi-midi-ns = <4000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml new file mode 100644 index 000000000000..80bac7a182d5 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 System Control Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: + The SRAM controller found on most Allwinner devices is represented + by a regular node for the SRAM controller itself, with sub-nodes + representing the SRAM handled by the SRAM controller. + +properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + compatible: + oneOf: + - const: allwinner,sun4i-a10-sram-controller + deprecated: true + - const: allwinner,sun4i-a10-system-control + - const: allwinner,sun5i-a13-system-control + - items: + - const: allwinner,sun7i-a20-system-control + - const: allwinner,sun4i-a10-system-control + - const: allwinner,sun8i-a23-system-control + - const: allwinner,sun8i-h3-system-control + - const: allwinner,sun50i-a64-sram-controller + deprecated: true + - const: allwinner,sun50i-a64-system-control + - const: allwinner,sun50i-h5-system-control + - items: + - const: allwinner,sun50i-h6-system-control + - const: allwinner,sun50i-a64-system-control + - items: + - const: allwinner,suniv-f1c100s-system-control + - const: allwinner,sun4i-a10-system-control + + reg: + maxItems: 1 + + ranges: true + +patternProperties: + "^sram@[a-z0-9]+": + type: object + + properties: + compatible: + const: mmio-sram + + patternProperties: + "^sram-section?@[a-f0-9]+$": + type: object + + properties: + compatible: + oneOf: + - const: allwinner,sun4i-a10-sram-a3-a4 + - const: allwinner,sun4i-a10-sram-c1 + - const: allwinner,sun4i-a10-sram-d + - const: allwinner,sun50i-a64-sram-c + - items: + - const: allwinner,sun5i-a13-sram-a3-a4 + - const: allwinner,sun4i-a10-sram-a3-a4 + - items: + - const: allwinner,sun7i-a20-sram-a3-a4 + - const: allwinner,sun4i-a10-sram-a3-a4 + - items: + - const: allwinner,sun5i-a13-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 + - items: + - const: allwinner,sun7i-a20-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 + - items: + - const: allwinner,sun8i-a23-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 + - items: + - const: allwinner,sun8i-h3-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 + - items: + - const: allwinner,sun50i-a64-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 + - items: + - const: allwinner,sun50i-h5-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 + - items: + - const: allwinner,sun50i-h6-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 + - items: + - const: allwinner,sun5i-a13-sram-d + - const: allwinner,sun4i-a10-sram-d + - items: + - const: allwinner,sun7i-a20-sram-d + - const: allwinner,sun4i-a10-sram-d + - items: + - const: allwinner,suniv-f1c100s-sram-d + - const: allwinner,sun4i-a10-sram-d + - items: + - const: allwinner,sun50i-h6-sram-c + - const: allwinner,sun50i-a64-sram-c + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + system-control@1c00000 { + compatible = "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index ee2287a1b14d..7b83cc6c9bfa 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -55,7 +55,7 @@ properties: type: boolean patternProperties: - "^([a-z]*-)?sram@[a-f0-9]+$": + "^([a-z]*-)?sram(-section)?@[a-f0-9]+$": type: object description: Each child of the sram node specifies a region of reserved memory. @@ -64,15 +64,20 @@ patternProperties: description: Should contain a vendor specific string in the form <vendor>,[<device>-]<usage> - enum: - - allwinner,sun9i-a80-smp-sram - - amlogic,meson8-smp-sram - - amlogic,meson8b-smp-sram - - renesas,smp-sram - - rockchip,rk3066-smp-sram - - samsung,exynos4210-sysram - - samsung,exynos4210-sysram-ns - - socionext,milbeaut-smp-sram + contains: + enum: + - allwinner,sun4i-a10-sram-a3-a4 + - allwinner,sun4i-a10-sram-c1 + - allwinner,sun4i-a10-sram-d + - allwinner,sun9i-a80-smp-sram + - allwinner,sun50i-a64-sram-c + - amlogic,meson8-smp-sram + - amlogic,meson8b-smp-sram + - renesas,smp-sram + - rockchip,rk3066-smp-sram + - samsung,exynos4210-sysram + - samsung,exynos4210-sysram-ns + - socionext,milbeaut-smp-sram reg: description: diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt deleted file mode 100644 index 380246a805f2..000000000000 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ /dev/null @@ -1,113 +0,0 @@ -Allwinnner SoC SRAM controllers ------------------------------------------------------ - -The SRAM controller found on most Allwinner devices is represented by -a regular node for the SRAM controller itself, with sub-nodes -reprensenting the SRAM handled by the SRAM controller. - -Controller Node ---------------- - -Required properties: -- compatible : should be: - - "allwinner,sun4i-a10-sram-controller" (deprecated) - - "allwinner,sun4i-a10-system-control" - - "allwinner,sun5i-a13-system-control" - - "allwinner,sun7i-a20-system-control", "allwinner,sun4i-a10-system-control" - - "allwinner,sun8i-a23-system-control" - - "allwinner,sun8i-h3-system-control" - - "allwinner,sun50i-a64-sram-controller" (deprecated) - - "allwinner,sun50i-a64-system-control" - - "allwinner,sun50i-h5-system-control" - - "allwinner,sun50i-h6-system-control", "allwinner,sun50i-a64-system-control" - - "allwinner,suniv-f1c100s-system-control", "allwinner,sun4i-a10-system-control" -- reg : sram controller register offset + length - -SRAM nodes ----------- - -Each SRAM is described using the mmio-sram bindings documented in -Documentation/devicetree/bindings/sram/sram.txt - -Each SRAM will have SRAM sections that are going to be handled by the -SRAM controller as subnodes. These sections are represented following -once again the representation described in the mmio-sram binding. - -The valid sections compatible for A10 are: - - allwinner,sun4i-a10-sram-a3-a4 - - allwinner,sun4i-a10-sram-c1 - - allwinner,sun4i-a10-sram-d - -The valid sections compatible for A13 are: - - allwinner,sun5i-a13-sram-a3-a4, allwinner,sun4i-a10-sram-a3-a4 - - allwinner,sun5i-a13-sram-c1, allwinner,sun4i-a10-sram-c1 - - allwinner,sun5i-a13-sram-d, allwinner,sun4i-a10-sram-d - -The valid sections compatible for A20 are: - - allwinner,sun7i-a20-sram-a3-a4, allwinner,sun4i-a10-sram-a3-a4 - - allwinner,sun7i-a20-sram-c1, allwinner,sun4i-a10-sram-c1 - - allwinner,sun7i-a20-sram-d, allwinner,sun4i-a10-sram-d - -The valid sections compatible for A23/A33 are: - - allwinner,sun8i-a23-sram-c1, allwinner,sun4i-a10-sram-c1 - -The valid sections compatible for H3 are: - - allwinner,sun8i-h3-sram-c1, allwinner,sun4i-a10-sram-c1 - -The valid sections compatible for A64 are: - - allwinner,sun50i-a64-sram-c - - allwinner,sun50i-a64-sram-c1, allwinner,sun4i-a10-sram-c1 - -The valid sections compatible for H5 are: - - allwinner,sun50i-h5-sram-c1, allwinner,sun4i-a10-sram-c1 - -The valid sections compatible for H6 are: - - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c - - allwinner,sun50i-h6-sram-c1, allwinner,sun4i-a10-sram-c1 - -The valid sections compatible for F1C100s are: - - allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d - -Devices using SRAM sections ---------------------------- - -Some devices need to request to the SRAM controller to map an SRAM for -their exclusive use. - -The relationship between such a device and an SRAM section is -expressed through the allwinner,sram property, that will take a -phandle and an argument. - -This valid values for this argument are: - - 0: CPU - - 1: Device - -Example -------- -system-control@1c00000 { - compatible = "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@00000000 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - }; - }; -}; - -emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - ... - - allwinner,sram = <&emac_sram 1>; -}; diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml new file mode 100644 index 000000000000..87369264feb9 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/allwinner,sun8i-a83t-ths.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SUN8I Thermal Controller Device Tree Bindings + +maintainers: + - Vasily Khoruzhick <anarsoul@gmail.com> + - Yangtao Li <tiny.windzz@gmail.com> + +properties: + compatible: + enum: + - allwinner,sun8i-a83t-ths + - allwinner,sun8i-h3-ths + - allwinner,sun8i-r40-ths + - allwinner,sun50i-a64-ths + - allwinner,sun50i-h5-ths + - allwinner,sun50i-h6-ths + + clocks: + minItems: 1 + maxItems: 2 + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: bus + - const: mod + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + nvmem-cells: + maxItems: 1 + description: Calibration data for thermal sensors + + nvmem-cell-names: + const: calibration + + # See ./thermal.txt for details + "#thermal-sensor-cells": + enum: + - 0 + - 1 + +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-ths + + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + else: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-h3-ths + + then: + properties: + "#thermal-sensor-cells": + const: 0 + + else: + properties: + "#thermal-sensor-cells": + const: 1 + + - if: + properties: + compatible: + contains: + enum: + - const: allwinner,sun8i-h3-ths + - const: allwinner,sun8i-r40-ths + - const: allwinner,sun50i-a64-ths + - const: allwinner,sun50i-h5-ths + - const: allwinner,sun50i-h6-ths + + then: + required: + - clocks + - clock-names + - resets + +required: + - compatible + - reg + - interrupts + - '#thermal-sensor-cells' + +additionalProperties: false + +examples: + - | + thermal-sensor@1f04000 { + compatible = "allwinner,sun8i-a83t-ths"; + reg = <0x01f04000 0x100>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + + - | + thermal-sensor@1c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + clocks = <&ccu 0>, <&ccu 1>; + clock-names = "bus", "mod"; + resets = <&ccu 2>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + + - | + thermal-sensor@5070400 { + compatible = "allwinner,sun50i-h6-ths"; + reg = <0x05070400 0x100>; + clocks = <&ccu 0>; + clock-names = "bus"; + resets = <&ccu 2>; + interrupts = <0 15 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.yaml b/Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.yaml new file mode 100644 index 000000000000..d9fdf4809a49 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/brcm,avs-ro-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom AVS ring oscillator thermal + +maintainers: + - Stefan Wahren <wahrenst@gmx.net> + +description: |+ + The thermal node should be the child of a syscon node with the + required property: + + - compatible: Should be one of the following: + "brcm,bcm2711-avs-monitor", "syscon", "simple-mfd" + + Refer to the the bindings described in + Documentation/devicetree/bindings/mfd/syscon.txt + +properties: + compatible: + const: brcm,bcm2711-thermal + + # See ./thermal.txt for details + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - '#thermal-sensor-cells' + +additionalProperties: false + +examples: + - | + avs-monitor@7d5d2000 { + compatible = "brcm,bcm2711-avs-monitor", + "syscon", "simple-mfd"; + reg = <0x7d5d2000 0xf00>; + + thermal: thermal { + compatible = "brcm,bcm2711-thermal"; + #thermal-sensor-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt index 43a9ed545944..74a9ef09db8b 100644 --- a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt +++ b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt @@ -3,9 +3,13 @@ Thermal management core, provided by the AVS TMON hardware block. Required properties: -- compatible: must be "brcm,avs-tmon" and/or "brcm,avs-tmon-bcm7445" +- compatible: must be one of: + "brcm,avs-tmon-bcm7216" + "brcm,avs-tmon-bcm7445" + "brcm,avs-tmon" - reg: address range for the AVS TMON registers -- interrupts: temperature monitor interrupt, for high/low threshold triggers +- interrupts: temperature monitor interrupt, for high/low threshold triggers, + required except for "brcm,avs-tmon-bcm7216" - interrupt-names: should be "tmon" Example: diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml index 20adc1c8e9cc..23e989e09766 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 Timer Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml index dfa0c41fd261..40fc4bcb3145 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml @@ -8,7 +8,7 @@ title: Allwinner A13 High-Speed Timer Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml index b3f0fe96ff0d..102f319833d9 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml @@ -99,22 +99,22 @@ examples: compatible = "arm,armv7-timer-mem"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0 0xf0001000 0x1000>; reg = <0xf0000000 0x1000>; clock-frequency = <50000000>; - frame@f0001000 { + frame@0 { frame-number = <0>; interrupts = <0 13 0x8>, <0 14 0x8>; - reg = <0xf0001000 0x1000>, - <0xf0002000 0x1000>; + reg = <0x0000 0x1000>, + <0x1000 0x1000>; }; - frame@f0003000 { + frame@2000 { frame-number = <1>; interrupts = <0 15 0x8>; - reg = <0xf0003000 0x1000>; + reg = <0x2000 0x1000>; }; }; diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index a444cfc5852a..a747fabab7d3 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -29,6 +29,8 @@ Required Properties: - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1. - "renesas,r8a774a1-cmt1" for the 48-bit CMT devices included in r8a774a1. + - "renesas,r8a774b1-cmt0" for the 32-bit CMT0 device included in r8a774b1. + - "renesas,r8a774b1-cmt1" for the 48-bit CMT devices included in r8a774b1. - "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0. - "renesas,r8a774c0-cmt1" for the 48-bit CMT devices included in r8a774c0. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 765fd1c170df..978de7d37c66 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -104,6 +104,10 @@ properties: - infineon,slb9645tt # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor - infineon,tlv493d-a1b6 + # Infineon Multi-phase Digital VR Controller xdpe12254 + - infineon,xdpe12254 + # Infineon Multi-phase Digital VR Controller xdpe12284 + - infineon,xdpe12284 # Inspur Power System power supply unit version 1 - inspur,ipsps1 # Intersil ISL29028 Ambient Light and Proximity Sensor @@ -132,6 +136,8 @@ properties: - maxim,max6621 # 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface - maxim,max6625 + # 3-Channel Remote Temperature Sensor + - maxim,max31730 # mCube 3-axis 8-bit digital accelerometer - mcube,mc3230 # MEMSIC 2-axis 8-bit digital accelerometer @@ -354,6 +360,10 @@ properties: - ti,tmp103 # Digital Temperature Sensor - ti,tmp275 + # TI Dual channel DCAP+ multiphase controller TPS53679 + - ti,tps53679 + # TI Dual channel DCAP+ multiphase controller TPS53688 + - ti,tps53688 # Winbond/Nuvoton H/W Monitor - winbond,w83793 # i2c trusted platform module (TPM) diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml index 0af70fc8de5a..d9207bf9d894 100644 --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml @@ -8,7 +8,7 @@ title: Allwinner A10 mUSB OTG Controller Device Tree Bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml index 4efb77b653ab..267fce165994 100644 --- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml +++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml @@ -107,7 +107,7 @@ examples: reg = <0xff400000 0x40000>; interrupts = <31>; clocks = <&clkc_usb1>; - clock-names = "ddr"; + clock-names = "otg"; phys = <&usb2_phy1>; dr_mode = "peripheral"; g-rx-fifo-size = <192>; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index cfc9f40ab641..51376cbe5f3d 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -15,6 +15,10 @@ Required properties: "qcom,ci-hdrc" "chipidea,usb2" "xlnx,zynq-usb-2.20a" + "nvidia,tegra20-udc" + "nvidia,tegra30-udc" + "nvidia,tegra114-udc" + "nvidia,tegra124-udc" - reg: base address and length of the registers - interrupts: interrupt for the USB controller diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt deleted file mode 100644 index aafff3a6904d..000000000000 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ /dev/null @@ -1,64 +0,0 @@ -Platform DesignWare HS OTG USB 2.0 controller ------------------------------------------------------ - -Required properties: -- compatible : One of: - - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. - - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC. - - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc; - - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc; - - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc; - - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; - - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; - - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; - - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs; - - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs; - - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs; - - "amlogic,meson-g12a-usb": The DWC2 USB controller instance in Amlogic G12A SoCs; - - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs; - - snps,dwc2: A generic DWC2 USB controller with default parameters. - - "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs - configured in FS mode; - - "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs - configured in HS mode; - - "st,stm32f7-hsotg": The DWC2 USB HS controller instance in STM32F7 SoCs - configured in HS mode; -- reg : Should contain 1 register range (address and length) -- interrupts : Should contain 1 interrupt -- clocks: clock provider specifier -- clock-names: shall be "otg" -Refer to clk/clock-bindings.txt for generic clock consumer properties - -Optional properties: -- phys: phy provider specifier -- phy-names: shall be "usb2-phy" -- vbus-supply: reference to the VBUS regulator. Depending on the current mode - this is enabled (in "host" mode") or disabled (in "peripheral" mode). The - regulator is updated if the controller is configured in "otg" mode and the - status changes between "host" and "peripheral". -Refer to phy/phy-bindings.txt for generic phy consumer properties -- dr_mode: shall be one of "host", "peripheral" and "otg" - Refer to usb/generic.txt -- g-rx-fifo-size: size of rx fifo size in gadget mode. -- g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode. -- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode. -- snps,need-phy-for-wake: If present indicates that the phy needs to be left - on for remote wakeup during suspend. -- snps,reset-phy-on-wake: If present indicates that we need to reset the PHY when - we detect a wakeup. This is due to a hardware errata. - -Deprecated properties: -- g-use-dma: gadget DMA mode is automatically detected - -Example: - - usb@101c0000 { - compatible = "ralink,rt3050-usb, snps,dwc2"; - reg = <0x101c0000 40000>; - interrupts = <18>; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - snps,need-phy-for-wake; - }; diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml new file mode 100644 index 000000000000..71cf7ba32237 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/dwc2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare HS OTG USB 2.0 controller Bindings + +maintainers: + - Rob Herring <robh@kernel.org> + +properties: + compatible: + oneOf: + - const: brcm,bcm2835-usb + - const: hisilicon,hi6220-usb + - items: + - const: rockchip,rk3066-usb + - const: snps,dwc2 + - items: + - const: rockchip,px30-usb + - const: rockchip,rk3066-usb + - const: snps,dwc2 + - items: + - const: rockchip,rk3036-usb + - const: rockchip,rk3066-usb + - const: snps,dwc2 + - items: + - const: rockchip,rv1108-usb + - const: rockchip,rk3066-usb + - const: snps,dwc2 + - items: + - const: rockchip,rk3188-usb + - const: rockchip,rk3066-usb + - const: snps,dwc2 + - items: + - const: rockchip,rk3228-usb + - const: rockchip,rk3066-usb + - const: snps,dwc2 + - items: + - const: rockchip,rk3288-usb + - const: rockchip,rk3066-usb + - const: snps,dwc2 + - const: lantiq,arx100-usb + - const: lantiq,xrx200-usb + - items: + - const: amlogic,meson8-usb + - const: snps,dwc2 + - items: + - const: amlogic,meson8b-usb + - const: snps,dwc2 + - const: amlogic,meson-gxbb-usb + - items: + - const: amlogic,meson-g12a-usb + - const: snps,dwc2 + - const: amcc,dwc-otg + - const: snps,dwc2 + - const: st,stm32f4x9-fsotg + - const: st,stm32f4x9-hsotg + - const: st,stm32f7-hsotg + - const: samsung,s3c6400-hsotg + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: otg + + resets: + items: + - description: common reset + - description: ecc reset + minItems: 1 + + reset-names: + items: + - const: dwc2 + - const: dwc2-ecc + minItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: usb2-phy + + vbus-supply: + description: reference to the VBUS regulator. Depending on the current mode + this is enabled (in "host" mode") or disabled (in "peripheral" mode). The + regulator is updated if the controller is configured in "otg" mode and the + status changes between "host" and "peripheral". + + vusb_d-supply: + description: phandle to voltage regulator of digital section, + + vusb_a-supply: + description: phandle to voltage regulator of analog section. + + dr_mode: + enum: [host, peripheral, otg] + + g-rx-fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: size of rx fifo size in gadget mode. + + g-np-tx-fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: size of non-periodic tx fifo size in gadget mode. + + g-tx-fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: size of periodic tx fifo per endpoint (except ep0) in gadget mode. + + snps,need-phy-for-wake: + $ref: /schemas/types.yaml#/definitions/flag + description: If present indicates that the phy needs to be left on for remote wakeup during suspend. + + snps,reset-phy-on-wake: + $ref: /schemas/types.yaml#/definitions/flag + description: If present indicates that we need to reset the PHY when we detect a wakeup. + This is due to a hardware errata. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + usb@101c0000 { + compatible = "rockchip,rk3066-usb", "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = <18>; + clocks = <&usb_otg_ahb_clk>; + clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; + }; + +... diff --git a/Documentation/devicetree/bindings/usb/generic.txt b/Documentation/devicetree/bindings/usb/generic.txt index cf5a1ad456e6..e6790d2a4da9 100644 --- a/Documentation/devicetree/bindings/usb/generic.txt +++ b/Documentation/devicetree/bindings/usb/generic.txt @@ -2,10 +2,11 @@ Generic USB Properties Optional properties: - maximum-speed: tells USB controllers we want to work up to a certain - speed. Valid arguments are "super-speed", "high-speed", - "full-speed" and "low-speed". In case this isn't passed - via DT, USB controllers should default to their maximum - HW capability. + speed. Valid arguments are "super-speed-plus", + "super-speed", "high-speed", "full-speed" and + "low-speed". In case this isn't passed via DT, USB + controllers should default to their maximum HW + capability. - dr_mode: tells Dual-Role USB controllers that we want to work on a particular mode. Valid arguments are "host", "peripheral" and "otg". In case this attribute isn't diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.txt b/Documentation/devicetree/bindings/usb/mediatek,musb.txt new file mode 100644 index 000000000000..2b8a87c90d9e --- /dev/null +++ b/Documentation/devicetree/bindings/usb/mediatek,musb.txt @@ -0,0 +1,57 @@ +MediaTek musb DRD/OTG controller +------------------------------------------- + +Required properties: + - compatible : should be one of: + "mediatek,mt2701-musb" + ... + followed by "mediatek,mtk-musb" + - reg : specifies physical base address and size of + the registers + - interrupts : interrupt used by musb controller + - interrupt-names : must be "mc" + - phys : PHY specifier for the OTG phy + - dr_mode : should be one of "host", "peripheral" or "otg", + refer to usb/generic.txt + - clocks : a list of phandle + clock-specifier pairs, one for + each entry in clock-names + - clock-names : must contain "main", "mcu", "univpll" + for clocks of controller + +Optional properties: + - power-domains : a phandle to USB power domain node to control USB's + MTCMOS + +Required child nodes: + usb connector node as defined in bindings/connector/usb-connector.txt +Optional properties: + - id-gpios : input GPIO for USB ID pin. + - vbus-gpios : input GPIO for USB VBUS pin. + - vbus-supply : reference to the VBUS regulator, needed when supports + dual-role mode + - usb-role-switch : use USB Role Switch to support dual-role switch, see + usb/generic.txt. + +Example: + +usb2: usb@11200000 { + compatible = "mediatek,mt2701-musb", + "mediatek,mtk-musb"; + reg = <0 0x11200000 0 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "mc"; + phys = <&u2port2 PHY_TYPE_USB2>; + dr_mode = "otg"; + clocks = <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB0_MCU>, + <&pericfg CLK_PERI_USB_SLV>; + clock-names = "main","mcu","univpll"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + usb-role-switch; + connector{ + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_vbus>; + }; +}; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6046f4555852..7fcd48adc276 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -109,6 +109,8 @@ patternProperties: description: Artesyn Embedded Technologies Inc. "^asahi-kasei,.*": description: Asahi Kasei Corp. + "^asc,.*": + description: All Sensors Corporation "^aspeed,.*": description: ASPEED Technology Inc. "^asus,.*": @@ -149,6 +151,8 @@ patternProperties: description: Bosch Sensortec GmbH "^boundary,.*": description: Boundary Devices Inc. + "^broadmobi,.*": + description: Shanghai Broadmobi Communication Technology Co.,Ltd. "^brcm,.*": description: Broadcom Corporation "^buffalo,.*": @@ -157,6 +161,8 @@ patternProperties: description: B&R Industrial Automation GmbH "^bticino,.*": description: Bticino International + "^calaosystems,.*": + description: CALAO Systems SAS "^calxeda,.*": description: Calxeda "^capella,.*": @@ -475,6 +481,8 @@ patternProperties: description: Shenzhen Jesurun Electronics Business Dept. "^jianda,.*": description: Jiandangjing Technology Co., Ltd. + "^kam,.*": + description: Kamstrup A/S "^karo,.*": description: Ka-Ro electronics GmbH "^keithkoep,.*": @@ -513,6 +521,8 @@ patternProperties: description: Lantiq Semiconductor "^lattice,.*": description: Lattice Semiconductor + "^leadtek,.*": + description: Shenzhen Leadtek Technology Co., Ltd. "^leez,.*": description: Leez "^lego,.*": @@ -545,6 +555,8 @@ patternProperties: description: Logic PD, Inc. "^longcheer,.*": description: Longcheer Technology (Shanghai) Co., Ltd. + "^loongson,.*": + description: Loongson Technology Corporation Limited "^lsi,.*": description: LSI Corp. (LSI Logic) "^lwn,.*": @@ -613,6 +625,8 @@ patternProperties: description: Moxa Inc. "^mpl,.*": description: MPL AG + "^mps,.*": + description: Monolithic Power Systems Inc. "^mqmaker,.*": description: mqmaker Inc. "^mscc,.*": @@ -717,6 +731,8 @@ patternProperties: description: Panasonic Corporation "^parade,.*": description: Parade Technologies Inc. + "^parallax,.*": + description: Parallax Inc. "^pda,.*": description: Precision Design Associates, Inc. "^pericom,.*": @@ -823,6 +839,8 @@ patternProperties: description: Sancloud Ltd "^sandisk,.*": description: Sandisk Corporation + "^satoz,.*": + description: Satoz International Co., Ltd "^sbs,.*": description: Smart Battery System "^schindler,.*": @@ -911,8 +929,12 @@ patternProperties: description: Startek "^ste,.*": description: ST-Ericsson + deprecated: true "^stericsson,.*": description: ST-Ericsson + "^st-ericsson,.*": + description: ST-Ericsson + deprecated: true "^summit,.*": description: Summit microelectronics "^sunchip,.*": @@ -1056,10 +1078,16 @@ patternProperties: description: Extreme Engineering Solutions (X-ES) "^xillybus,.*": description: Xillybus Ltd. + "^xinpeng,.*": + description: Shenzhen Xinpeng Technology Co., Ltd "^xlnx,.*": description: Xilinx "^xunlong,.*": description: Shenzhen Xunlong Software CO.,Limited + "^xylon,.*": + description: Xylon + "^yna,.*": + description: YSH & ATIL "^yones-toptech,.*": description: Yones Toptech Co., Ltd. "^ysoft,.*": diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 3a54f58683a0..e8f226376108 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -11,7 +11,7 @@ allOf: maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt index a5bf04dba410..79b3c62f183d 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt @@ -19,6 +19,7 @@ Required properties: - "renesas,r8a7794-wdt" (R-Car E2) - "renesas,r8a7795-wdt" (R-Car H3) - "renesas,r8a7796-wdt" (R-Car M3-W) + - "renesas,r8a77961-wdt" (R-Car M3-W+) - "renesas,r8a77965-wdt" (R-Car M3-N) - "renesas,r8a77970-wdt" (R-Car V3M) - "renesas,r8a77990-wdt" (R-Car E3) diff --git a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt deleted file mode 100644 index d8f4430b0a13..000000000000 --- a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt +++ /dev/null @@ -1,26 +0,0 @@ -STM32 Independent WatchDoG (IWDG) ---------------------------------- - -Required properties: -- compatible: Should be either: - - "st,stm32-iwdg" - - "st,stm32mp1-iwdg" -- reg: Physical base address and length of the registers set for the device -- clocks: Reference to the clock entry lsi. Additional pclk clock entry - is required only for st,stm32mp1-iwdg. -- clock-names: Name of the clocks used. - "lsi" for st,stm32-iwdg - "lsi", "pclk" for st,stm32mp1-iwdg - -Optional Properties: -- timeout-sec: Watchdog timeout value in seconds. - -Example: - -iwdg: watchdog@40003000 { - compatible = "st,stm32-iwdg"; - reg = <0x40003000 0x400>; - clocks = <&clk_lsi>; - clock-names = "lsi"; - timeout-sec = <32>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml new file mode 100644 index 000000000000..a27c504e2e4f --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/st,stm32-iwdg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Independent WatchDoG (IWDG) bindings + +maintainers: + - Yannick Fertre <yannick.fertre@st.com> + - Christophe Roullier <christophe.roullier@st.com> + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + enum: + - st,stm32-iwdg + - st,stm32mp1-iwdg + + reg: + maxItems: 1 + + clocks: + items: + - description: Low speed clock + - description: Optional peripheral clock + minItems: 1 + maxItems: 2 + + clock-names: + items: + enum: + - lsi + - pclk + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + timeout-sec = <32>; + }; + +... diff --git a/Documentation/devicetree/writing-schema.rst b/Documentation/devicetree/writing-schema.rst index efcd5d21dc2b..7635ab230456 100644 --- a/Documentation/devicetree/writing-schema.rst +++ b/Documentation/devicetree/writing-schema.rst @@ -121,7 +121,13 @@ Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be installed. Ensure they are in your PATH (~/.local/bin by default). dtc must also be built with YAML output support enabled. This requires that -libyaml and its headers be installed on the host system. +libyaml and its headers be installed on the host system. For some distributions +that involves installing the development package, such as: + +Debian: + apt-get install libyaml-dev +Fedora: + dnf -y install libyaml-devel Running checks ~~~~~~~~~~~~~~ |