diff options
Diffstat (limited to 'Documentation/devicetree')
11 files changed, 244 insertions, 52 deletions
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt new file mode 100644 index 000000000000..7ca52161e7ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -0,0 +1,44 @@ +* ARM L2 Cache Controller + +ARM cores often have a separate level 2 cache controller. There are various +implementations of the L2 cache controller with compatible programming models. +The ARM L2 cache representation in the device tree should be done as follows: + +Required properties: + +- compatible : should be one of: + "arm,pl310-cache" + "arm,l220-cache" + "arm,l210-cache" +- cache-unified : Specifies the cache is a unified cache. +- cache-level : Should be set to 2 for a level 2 cache. +- reg : Physical base address and size of cache controller's memory mapped + registers. + +Optional properties: + +- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of + read, write and setup latencies. Minimum valid values are 1. Controllers + without setup latency control should use a value of 0. +- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of + read, write and setup latencies. Controllers without setup latency control + should use 0. Controllers without separate read and write Tag RAM latency + values should only use the first cell. +- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. +- arm,filter-ranges : <start length> Starting address and length of window to + filter. Addresses in the filter window are directed to the M1 port. Other + addresses will go to the M0 port. +- interrupts : 1 combined interrupt. + +Example: + +L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; + arm,filter-latency = <0x80000000 0x8000000>; + cache-unified; + cache-level = <2>; + interrupts = <45>; +}; diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt index 1d5d7a870ec7..951ca46789d4 100644 --- a/Documentation/devicetree/bindings/arm/primecell.txt +++ b/Documentation/devicetree/bindings/arm/primecell.txt @@ -6,7 +6,9 @@ driver matching. Required properties: -- compatible : should be a specific value for peripheral and "arm,primecell" +- compatible : should be a specific name for the peripheral and + "arm,primecell". The specific name will match the ARM + engineering name for the logic block in the form: "arm,pl???" Optional properties: diff --git a/Documentation/devicetree/bindings/gpio/led.txt b/Documentation/devicetree/bindings/gpio/led.txt index 064db928c3c1..141087cf3107 100644 --- a/Documentation/devicetree/bindings/gpio/led.txt +++ b/Documentation/devicetree/bindings/gpio/led.txt @@ -8,7 +8,7 @@ node's name represents the name of the corresponding LED. LED sub-node properties: - gpios : Should specify the LED's GPIO, see "Specifying GPIO information - for devices" in Documentation/powerpc/booting-without-of.txt. Active + for devices" in Documentation/devicetree/booting-without-of.txt. Active low LEDs should be indicated using flags in the GPIO specifier. - label : (optional) The label for this LED. If omitted, the label is taken from the node name (excluding the unit address). diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt new file mode 100644 index 000000000000..a2c416bcbccc --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt @@ -0,0 +1,10 @@ +ARM PL061 GPIO controller + +Required properties: +- compatible : "arm,pl061", "arm,primecell" +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters: + - bit 0 specifies polarity (0 for normal, 1 for inverted) +- gpio-controller : Marks the device node as a GPIO controller. +- interrupts : Interrupt mapping for GPIO IRQ. + diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index 1a729f089866..1ad80d5865a9 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt @@ -1,61 +1,24 @@ -CAN Device Tree Bindings ------------------------- -2011 Freescale Semiconductor, Inc. +Flexcan CAN contoller on Freescale's ARM and PowerPC system-on-a-chip (SOC). -fsl,flexcan-v1.0 nodes ------------------------ -In addition to the required compatible-, reg- and interrupt-properties, you can -also specify which clock source shall be used for the controller. +Required properties: -CPI Clock- Can Protocol Interface Clock - This CLK_SRC bit of CTRL(control register) selects the clock source to - the CAN Protocol Interface(CPI) to be either the peripheral clock - (driven by the PLL) or the crystal oscillator clock. The selected clock - is the one fed to the prescaler to generate the Serial Clock (Sclock). - The PRESDIV field of CTRL(control register) controls a prescaler that - generates the Serial Clock (Sclock), whose period defines the - time quantum used to compose the CAN waveform. +- compatible : Should be "fsl,<processor>-flexcan" -Can Engine Clock Source - There are two sources for CAN clock - - Platform Clock It represents the bus clock - - Oscillator Clock + An implementation should also claim any of the following compatibles + that it is fully backwards compatible with: - Peripheral Clock (PLL) - -------------- - | - --------- ------------- - | |CPI Clock | Prescaler | Sclock - | |---------------->| (1.. 256) |------------> - --------- ------------- - | | - -------------- ---------------------CLK_SRC - Oscillator Clock + - fsl,p1010-flexcan -- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects - the peripheral clock. PLL clock is fed to the - prescaler to generate the Serial Clock (Sclock). - Valid values are "oscillator" and "platform" - "oscillator": CAN engine clock source is oscillator clock. - "platform" The CAN engine clock source is the bus clock - (platform clock). +- reg : Offset and length of the register set for this device +- interrupts : Interrupt tuple for this device +- clock-frequency : The oscillator frequency driving the flexcan device -- fsl,flexcan-clock-divider : for the reference and system clock, an additional - clock divider can be specified. -- clock-frequency: frequency required to calculate the bitrate for FlexCAN. +Example: -Note: - - v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC. - - P1010 does not have oscillator as the Clock Source.So the default - Clock Source is platform clock. -Examples: - - can0@1c000 { - compatible = "fsl,flexcan-v1.0"; + can@1c000 { + compatible = "fsl,p1010-flexcan"; reg = <0x1c000 0x1000>; interrupts = <48 0x2>; interrupt-parent = <&mpic>; - fsl,flexcan-clock-source = "platform"; - fsl,flexcan-clock-divider = <2>; - clock-frequency = <fixed by u-boot>; + clock-frequency = <200000000>; // filled in by bootloader }; diff --git a/Documentation/devicetree/bindings/net/smsc911x.txt b/Documentation/devicetree/bindings/net/smsc911x.txt new file mode 100644 index 000000000000..adb5b5744ecd --- /dev/null +++ b/Documentation/devicetree/bindings/net/smsc911x.txt @@ -0,0 +1,38 @@ +* Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller + +Required properties: +- compatible : Should be "smsc,lan<model>", "smsc,lan9115" +- reg : Address and length of the io space for SMSC LAN +- interrupts : Should contain SMSC LAN interrupt line +- interrupt-parent : Should be the phandle for the interrupt controller + that services interrupts for this device +- phy-mode : String, operation mode of the PHY interface. + Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii", + "rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii". + +Optional properties: +- reg-shift : Specify the quantity to shift the register offsets by +- reg-io-width : Specify the size (in bytes) of the IO accesses that + should be performed on the device. Valid value for SMSC LAN is + 2 or 4. If it's omitted or invalid, the size would be 2. +- smsc,irq-active-high : Indicates the IRQ polarity is active-high +- smsc,irq-push-pull : Indicates the IRQ type is push-pull +- smsc,force-internal-phy : Forces SMSC LAN controller to use + internal PHY +- smsc,force-external-phy : Forces SMSC LAN controller to use + external PHY +- smsc,save-mac-address : Indicates that mac address needs to be saved + before resetting the controller +- local-mac-address : 6 bytes, mac address + +Examples: + +lan9220@f4000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0xf4000000 0x2000000>; + phy-mode = "mii"; + interrupt-parent = <&gpio1>; + interrupts = <31>; + reg-io-width = <4>; + smsc,irq-push-pull; +}; diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt new file mode 100644 index 000000000000..1e753c69fc83 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/rs485.txt @@ -0,0 +1,31 @@ +* RS485 serial communications + +The RTS signal is capable of automatically controlling line direction for +the built-in half-duplex mode. +The properties described hereafter shall be given to a half-duplex capable +UART node. + +Required properties: +- rs485-rts-delay: prop-encoded-array <a b> where: + * a is the delay beteween rts signal and beginning of data sent in milliseconds. + it corresponds to the delay before sending data. + * b is the delay between end of data sent and rts signal in milliseconds + it corresponds to the delay after sending data and actual release of the line. + +Optional properties: +- linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485 + feature at boot time. It can be disabled later with proper ioctl. +- rs485-rx-during-tx: empty property that enables the receiving of data even + whilst sending data. + +RS485 example for Atmel USART: + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x4000>; + interrupts = <7>; + atmel,use-dma-rx; + atmel,use-dma-tx; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 200>; // in milliseconds + }; + diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt new file mode 100644 index 000000000000..306ec3ff3c0e --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt @@ -0,0 +1,12 @@ +ARM PL022 SPI controller + +Required properties: +- compatible : "arm,pl022", "arm,primecell" +- reg : Offset and length of the register set for the device +- interrupts : Should contain SPI controller interrupt + +Optional properties: +- cs-gpios : should specify GPIOs used for chipselects. + The gpios will be referred to as reg = <index> in the SPI child nodes. + If unspecified, a single SPI device without a chip select can be used. + diff --git a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt new file mode 100644 index 000000000000..a49d9a1d4ccf --- /dev/null +++ b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt @@ -0,0 +1,27 @@ +* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) + +Required properties: +- compatible: Should be "atmel,<chip>-usart" + The compatible <chip> indicated will be the first SoC to support an + additional mode or an USART new feature. +- reg: Should contain registers location and length +- interrupts: Should contain interrupt + +Optional properties: +- atmel,use-dma-rx: use of PDC or DMA for receiving data +- atmel,use-dma-tx: use of PDC or DMA for transmitting data + +<chip> compatible description: +- at91rm9200: legacy USART support +- at91sam9260: generic USART implementation for SAM9 SoCs + +Example: + + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x4000>; + interrupts = <7>; + atmel,use-dma-rx; + atmel,use-dma-tx; + }; + diff --git a/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt new file mode 100644 index 000000000000..f13f1c5be91c --- /dev/null +++ b/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt @@ -0,0 +1,25 @@ +* Synopsys DesignWare ABP UART + +Required properties: +- compatible : "snps,dw-apb-uart" +- reg : offset and length of the register set for the device. +- interrupts : should contain uart interrupt. +- clock-frequency : the input clock frequency for the UART. + +Optional properties: +- reg-shift : quantity to shift the register offsets by. If this property is + not present then the register offsets are not shifted. +- reg-io-width : the size (in bytes) of the IO accesses that should be + performed on the device. If this property is not present then single byte + accesses are used. + +Example: + + uart@80230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x80230000 0x100>; + clock-frequency = <3686400>; + interrupts = <10>; + reg-shift = <2>; + reg-io-width = <4>; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt new file mode 100644 index 000000000000..e8552782b440 --- /dev/null +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -0,0 +1,40 @@ +Device tree binding vendor prefix registry. Keep list in alphabetical order. + +This isn't an exhaustive list, but you should add new prefixes to it before +using them to avoid name-space collisions. + +adi Analog Devices, Inc. +amcc Applied Micro Circuits Corporation (APM, formally AMCC) +apm Applied Micro Circuits Corporation (APM) +arm ARM Ltd. +atmel Atmel Corporation +chrp Common Hardware Reference Platform +dallas Maxim Integrated Products (formerly Dallas Semiconductor) +denx Denx Software Engineering +epson Seiko Epson Corp. +est ESTeem Wireless Modems +fsl Freescale Semiconductor +GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. +gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. +hp Hewlett Packard +ibm International Business Machines (IBM) +idt Integrated Device Technologies, Inc. +intercontrol Inter Control Group +linux Linux-specific binding +marvell Marvell Technology Group Ltd. +maxim Maxim Integrated Products +mosaixtech Mosaix Technologies, Inc. +national National Semiconductor +nintendo Nintendo +nvidia NVIDIA +nxp NXP Semiconductors +powervr Imagination Technologies +qcom Qualcomm, Inc. +ramtron Ramtron International +samsung Samsung Semiconductor +schindler Schindler +simtek +sirf SiRF Technology, Inc. +stericsson ST-Ericsson +ti Texas Instruments +xlnx Xilinx |