diff options
Diffstat (limited to 'Documentation/devicetree')
10 files changed, 467 insertions, 152 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index c23c24ff7575..7a9c3ce2dbef 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -242,6 +242,21 @@ properties: where voltage is in V, frequency is in MHz. + power-domains: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + List of phandles and PM domain specifiers, as defined by bindings of the + PM domain provider (see also ../power_domain.txt). + + power-domain-names: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: + A list of power domain name strings sorted in the same order as the + power-domains property. + + For PSCI based platforms, the name corresponding to the index of the PSCI + PM domain provider, must be "psci". + qcom,saw: $ref: '/schemas/types.yaml#/definitions/phandle' description: | diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 558749065b97..79902f470e4b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -47,7 +47,7 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - cache-controller@1100000 { + system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; reg-names = "llcc_base", "llcc_broadcast_base"; diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 7abdf58b335e..8ef85420b2ab 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -102,6 +102,34 @@ properties: [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt + "#power-domain-cells": + description: + The number of cells in a PM domain specifier as per binding in [3]. + Must be 0 as to represent a single PM domain. + + ARM systems can have multiple cores, sometimes in an hierarchical + arrangement. This often, but not always, maps directly to the processor + power topology of the system. Individual nodes in a topology have their + own specific power states and can be better represented hierarchically. + + For these cases, the definitions of the idle states for the CPUs and the + CPU topology, must conform to the binding in [3]. The idle states + themselves must conform to the binding in [4] and must specify the + arm,psci-suspend-param property. + + It should also be noted that, in PSCI firmware v1.0 the OS-Initiated + (OSI) CPU suspend mode is introduced. Using a hierarchical representation + helps to implement support for OSI mode and OS implementations may choose + to mandate it. + + [3] Documentation/devicetree/bindings/power/power_domain.txt + [4] Documentation/devicetree/bindings/power/domain-idle-state.txt + + power-domains: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + List of phandles and PM domain specifiers, as defined by bindings of the + PM domain provider. required: - compatible @@ -160,4 +188,80 @@ examples: cpu_on = <0x95c10002>; cpu_off = <0x95c10001>; }; + + - |+ + + // Case 4: CPUs and CPU idle states described using the hierarchical model. + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + }; + + idle-states { + + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000011>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000031>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt deleted file mode 100644 index bc75bf49cdae..000000000000 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt +++ /dev/null @@ -1,148 +0,0 @@ -Qualcomm RPM/RPMh Power domains - -For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh -which then translates it into a corresponding voltage on a rail - -Required Properties: - - compatible: Should be one of the following - * qcom,msm8976-rpmpd: RPM Power domain for the msm8976 family of SoC - * qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC - * qcom,msm8998-rpmpd: RPM Power domain for the msm8998 family of SoC - * qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC - * qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC - - #power-domain-cells: number of cells in Power domain specifier - must be 1. - - operating-points-v2: Phandle to the OPP table for the Power domain. - Refer to Documentation/devicetree/bindings/power/power_domain.txt - and Documentation/devicetree/bindings/opp/opp.txt for more details - -Refer to <dt-bindings/power/qcom-rpmpd.h> for the level values for -various OPPs for different platforms as well as Power domain indexes - -Example: rpmh power domain controller and OPP table - -#include <dt-bindings/power/qcom-rpmhpd.h> - -opp-level values specified in the OPP tables for RPMh power domains -should use the RPMH_REGULATOR_LEVEL_* constants from -<dt-bindings/power/qcom-rpmhpd.h> - - rpmhpd: power-controller { - compatible = "qcom,sdm845-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS>; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM>; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; - }; - }; - }; - -Example: rpm power domain controller and OPP table - - rpmpd: power-controller { - compatible = "qcom,msm8996-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_low: opp1 { - opp-level = <1>; - }; - - rpmpd_opp_ret: opp2 { - opp-level = <2>; - }; - - rpmpd_opp_svs: opp3 { - opp-level = <3>; - }; - - rpmpd_opp_normal: opp4 { - opp-level = <4>; - }; - - rpmpd_opp_high: opp5 { - opp-level = <5>; - }; - - rpmpd_opp_turbo: opp6 { - opp-level = <6>; - }; - }; - }; - -Example: Client/Consumer device using OPP table - - leaky-device0@12350000 { - compatible = "foo,i-leak-current"; - reg = <0x12350000 0x1000>; - power-domains = <&rpmhpd SDM845_MX>; - operating-points-v2 = <&leaky_opp_table>; - }; - - - leaky_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp1 { - opp-hz = /bits/ 64 <144000>; - required-opps = <&rpmhpd_opp_low>; - }; - - opp2 { - opp-hz = /bits/ 64 <400000>; - required-opps = <&rpmhpd_opp_ret>; - }; - - opp3 { - opp-hz = /bits/ 64 <20000000>; - required-opps = <&rpmpd_opp_svs>; - }; - - opp4 { - opp-hz = /bits/ 64 <25000000>; - required-opps = <&rpmpd_opp_normal>; - }; - }; diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml new file mode 100644 index 000000000000..ba605310abeb --- /dev/null +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/qcom,rpmpd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPM/RPMh Power domains + +maintainers: + - Rajendra Nayak <rnayak@codeaurora.org> + +description: + For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh + which then translates it into a corresponding voltage on a rail. + +properties: + compatible: + enum: + - qcom,msm8976-rpmpd + - qcom,msm8996-rpmpd + - qcom,msm8998-rpmpd + - qcom,qcs404-rpmpd + - qcom,sc7180-rpmhpd + - qcom,sdm845-rpmhpd + - qcom,sm8150-rpmhpd + + '#power-domain-cells': + const: 1 + + operating-points-v2: true + + opp-table: + type: object + +required: + - compatible + - '#power-domain-cells' + - operating-points-v2 + +additionalProperties: false + +examples: + - | + + // Example 1 (rpmh power domain controller and OPP table): + + #include <dt-bindings/power/qcom-rpmpd.h> + + rpmhpd: power-controller { + compatible = "qcom,sdm845-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + + - | + + // Example 2 (rpm power domain controller and OPP table): + + rpmpd: power-controller { + compatible = "qcom,msm8996-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_low: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_ret: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_normal: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_high: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + + - | + + // Example 3 (Client/Consumer device using OPP table): + + leaky-device0@12350000 { + compatible = "foo,i-leak-current"; + reg = <0x12350000 0x1000>; + power-domains = <&rpmhpd 0>; + operating-points-v2 = <&leaky_opp_table>; + }; + + leaky_opp_table: opp-table { + compatible = "operating-points-v2"; + opp1 { + opp-hz = /bits/ 64 <144000>; + required-opps = <&rpmhpd_opp_low>; + }; + + opp2 { + opp-hz = /bits/ 64 <400000>; + required-opps = <&rpmhpd_opp_ret>; + }; + + opp3 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp4 { + opp-hz = /bits/ 64 <25000000>; + required-opps = <&rpmpd_opp_normal>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt index d366f1eb623a..bb529ecf8a57 100644 --- a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt +++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt @@ -8,9 +8,41 @@ Required properties: - compatible: Must contain: "xlnx,zynqmp-power" - interrupts: Interrupt specifier -------- -Example -------- +Optional properties: + - mbox-names : Name given to channels seen in the 'mboxes' property. + "tx" - Mailbox corresponding to transmit path + "rx" - Mailbox corresponding to receive path + - mboxes : Standard property to specify a Mailbox. Each value of + the mboxes property should contain a phandle to the + mailbox controller device node and an args specifier + that will be the phandle to the intended sub-mailbox + child node to be used for communication. See + Documentation/devicetree/bindings/mailbox/mailbox.txt + for more details about the generic mailbox controller + and client driver bindings. Also see + Documentation/devicetree/bindings/mailbox/ \ + xlnx,zynqmp-ipi-mailbox.txt for typical controller that + is used to communicate with this System controllers. + +-------- +Examples +-------- + +Example with interrupt method: + +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + zynqmp_power: zynqmp-power { + compatible = "xlnx,zynqmp-power"; + interrupts = <0 35 4>; + }; + }; +}; + +Example with IPI mailbox method: firmware { zynqmp_firmware: zynqmp-firmware { @@ -19,7 +51,11 @@ firmware { zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; + interrupt-parent = <&gic>; interrupts = <0 35 4>; + mboxes = <&ipi_mailbox_pmu0 0>, + <&ipi_mailbox_pmu0 1>; + mbox-names = "tx", "rx"; }; }; }; diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml new file mode 100644 index 000000000000..411bd76f1b64 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 Broadcom +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/brcm,bcm7216-pcie-sata-rescal.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: BCM7216 RESCAL reset controller + +description: This document describes the BCM7216 RESCAL reset controller which is responsible for controlling the reset of the SATA and PCIe0/1 instances on BCM7216. + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + - Jim Quinlan <jim2101024@gmail.com> + +properties: + compatible: + const: brcm,bcm7216-pcie-sata-rescal + + reg: + maxItems: 1 + + "#reset-cells": + const: 0 + +required: + - compatible + - reg + - "#reset-cells" + +examples: + - | + reset-controller@8b2c800 { + compatible = "brcm,bcm7216-pcie-sata-rescal"; + reg = <0x8b2c800 0x10>; + #reset-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml new file mode 100644 index 000000000000..246dea8a2ec9 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: System Reset Controller on Intel Gateway SoCs + +maintainers: + - Dilip Kota <eswara.kota@linux.intel.com> + +properties: + compatible: + enum: + - intel,rcu-lgm + - intel,rcu-xrx200 + + reg: + description: Reset controller registers. + maxItems: 1 + + intel,global-reset: + description: Global reset register offset and bit offset. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - maxItems: 2 + + "#reset-cells": + minimum: 2 + maximum: 3 + description: | + First cell is reset request register offset. + Second cell is bit offset in reset request register. + Third cell is bit offset in reset status register. + For LGM SoC, reset cell count is 2 as bit offset in + reset request and reset status registers is same. Whereas + 3 for legacy SoCs as bit offset differs. + +required: + - compatible + - reg + - intel,global-reset + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rcu0: reset-controller@e0000000 { + compatible = "intel,rcu-lgm"; + reg = <0xe0000000 0x20000>; + intel,global-reset = <0x10 30>; + #reset-cells = <2>; + }; + + pwm: pwm@e0d00000 { + status = "disabled"; + compatible = "intel,lgm-pwm"; + reg = <0xe0d00000 0x30>; + clocks = <&cgu0 1>; + #pwm-cells = <2>; + resets = <&rcu0 0x30 21>; + }; diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt new file mode 100644 index 000000000000..6e802703af60 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt @@ -0,0 +1,32 @@ +Nuvoton NPCM Reset controller + +Required properties: +- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC +- reg : specifies physical base address and size of the register. +- #reset-cells: must be set to 2 + +Optional property: +- nuvoton,sw-reset-number - Contains the software reset number to restart the SoC. + NPCM7xx contain four software reset that represent numbers 1 to 4. + + If 'nuvoton,sw-reset-number' is not specfied software reset is disabled. + +Example: + rstc: rstc@f0801000 { + compatible = "nuvoton,npcm750-reset"; + reg = <0xf0801000 0x70>; + #reset-cells = <2>; + nuvoton,sw-reset-number = <2>; + }; + +Specifying reset lines connected to IP NPCM7XX modules +====================================================== +example: + + spi0: spi@..... { + ... + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; + ... + }; + +The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>. diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index 8f469d85833b..2bc367793aec 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -11,6 +11,7 @@ The driver implements the Generic PM domain bindings described in power/power-domain.yaml. It provides the power domains defined in - include/dt-bindings/power/mt8173-power.h - include/dt-bindings/power/mt6797-power.h +- include/dt-bindings/power/mt6765-power.h - include/dt-bindings/power/mt2701-power.h - include/dt-bindings/power/mt2712-power.h - include/dt-bindings/power/mt7622-power.h @@ -19,6 +20,7 @@ Required properties: - compatible: Should be one of: - "mediatek,mt2701-scpsys" - "mediatek,mt2712-scpsys" + - "mediatek,mt6765-scpsys" - "mediatek,mt6797-scpsys" - "mediatek,mt7622-scpsys" - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC @@ -33,6 +35,10 @@ Required properties: enabled before enabling certain power domains. Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif" Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec" + Required clocks for MT6765: MUX: "mm", "mfg" + CG: "mm-0", "mm-1", "mm-2", "mm-3", "isp-0", + "isp-1", "cam-0", "cam-1", "cam-2", + "cam-3","cam-4" Required clocks for MT6797: "mm", "mfg", "vdec" Required clocks for MT7622 or MT7629: "hif_sel" Required clocks for MT7623A: "ethif" |