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-rw-r--r--arch/arc/plat-eznps/include/plat/ctop.h28
1 files changed, 9 insertions, 19 deletions
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h
index 4f6a1673b3a6..a4a61531c7fb 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -1,17 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright(c) 2015 EZchip Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * The full GNU General Public License is included in this distribution in
- * the file called "COPYING".
*/
#ifndef _PLAT_EZNPS_CTOP_H
@@ -21,6 +10,7 @@
#error "Incorrect ctop.h include"
#endif
+#include <linux/bits.h>
#include <linux/types.h>
#include <soc/nps/common.h>
@@ -62,19 +52,19 @@
#define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06
/* Do not use D$ for address in 2G-3G */
-#define HW_COMPLY_KRN_NOT_D_CACHED _BITUL(28)
+#define HW_COMPLY_KRN_NOT_D_CACHED BIT(28)
#define NPS_MSU_EN_CFG 0x80
#define NPS_CRG_BLKID 0x480
-#define NPS_CRG_SYNC_BIT _BITUL(0)
+#define NPS_CRG_SYNC_BIT BIT(0)
#define NPS_GIM_BLKID 0x5C0
/* GIM registers and fields*/
-#define NPS_GIM_UART_LINE _BITUL(7)
-#define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE _BITUL(10)
-#define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE _BITUL(11)
-#define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE _BITUL(25)
-#define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE _BITUL(26)
+#define NPS_GIM_UART_LINE BIT(7)
+#define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE BIT(10)
+#define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE BIT(11)
+#define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE BIT(25)
+#define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE BIT(26)
#ifndef __ASSEMBLY__
/* Functional registers definition */