diff options
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 102 |
1 files changed, 70 insertions, 32 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 90542db1220d..14b4cf75ceec 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -327,7 +327,6 @@ choice config ARCH_MULTIPLATFORM bool "Allow multiple platforms to be selected" depends on MMU - select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_HAS_SG_CHAIN select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR @@ -342,7 +341,6 @@ config ARCH_MULTIPLATFORM config ARM_SINGLE_ARMV7M bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" depends on !MMU - select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_NVIC select AUTO_ZRELADDR select CLKSRC_OF @@ -353,26 +351,12 @@ config ARM_SINGLE_ARMV7M select SPARSE_IRQ select USE_OF - -config ARCH_CLPS711X - bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" - select ARCH_REQUIRE_GPIOLIB - select AUTO_ZRELADDR - select CLKSRC_MMIO - select COMMON_CLK - select CPU_ARM720T - select GENERIC_CLOCKEVENTS - select MFD_SYSCON - select SOC_BUS - help - Support for Cirrus Logic 711x/721x/731x based boards. - config ARCH_GEMINI bool "Cortina Systems Gemini" - select ARCH_REQUIRE_GPIOLIB select CLKSRC_MMIO select CPU_FA526 select GENERIC_CLOCKEVENTS + select GPIOLIB help Support for the Cortina Systems Gemini family SoCs @@ -393,7 +377,6 @@ config ARCH_EBSA110 config ARCH_EP93XX bool "EP93xx-based" select ARCH_HAS_HOLES_MEMORYMODEL - select ARCH_REQUIRE_GPIOLIB select ARM_AMBA select ARM_PATCH_PHYS_VIRT select ARM_VIC @@ -402,6 +385,7 @@ config ARCH_EP93XX select CLKSRC_MMIO select CPU_ARM920T select GENERIC_CLOCKEVENTS + select GPIOLIB help This enables support for the Cirrus EP93xx series of CPUs. @@ -442,9 +426,9 @@ config ARCH_IOP13XX config ARCH_IOP32X bool "IOP32x-based" depends on MMU - select ARCH_REQUIRE_GPIOLIB select CPU_XSCALE select GPIO_IOP + select GPIOLIB select NEED_RET_TO_USER select PCI select PLAT_IOP @@ -455,9 +439,9 @@ config ARCH_IOP32X config ARCH_IOP33X bool "IOP33x-based" depends on MMU - select ARCH_REQUIRE_GPIOLIB select CPU_XSCALE select GPIO_IOP + select GPIOLIB select NEED_RET_TO_USER select PCI select PLAT_IOP @@ -468,12 +452,12 @@ config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU select ARCH_HAS_DMA_SET_COHERENT_MASK - select ARCH_REQUIRE_GPIOLIB select ARCH_SUPPORTS_BIG_ENDIAN select CLKSRC_MMIO select CPU_XSCALE select DMABOUNCE if PCI select GENERIC_CLOCKEVENTS + select GPIOLIB select MIGHT_HAVE_PCI select NEED_MACH_IO_H select USB_EHCI_BIG_ENDIAN_DESC @@ -483,9 +467,9 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" - select ARCH_REQUIRE_GPIOLIB select CPU_PJ4 select GENERIC_CLOCKEVENTS + select GPIOLIB select MIGHT_HAVE_PCI select MULTI_IRQ_HANDLER select MVEBU_MBUS @@ -499,10 +483,10 @@ config ARCH_DOVE config ARCH_KS8695 bool "Micrel/Kendin KS8695" - select ARCH_REQUIRE_GPIOLIB select CLKSRC_MMIO select CPU_ARM922T select GENERIC_CLOCKEVENTS + select GPIOLIB select NEED_MACH_MEMORY_H help Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based @@ -510,11 +494,11 @@ config ARCH_KS8695 config ARCH_W90X900 bool "Nuvoton W90X900 CPU" - select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CLKSRC_MMIO select CPU_ARM926T select GENERIC_CLOCKEVENTS + select GPIOLIB help Support for Nuvoton (Winbond logic dept.) ARM9 processor, At present, the w90x900 has been renamed nuc900, regarding @@ -526,13 +510,13 @@ config ARCH_W90X900 config ARCH_LPC32XX bool "NXP LPC32XX" - select ARCH_REQUIRE_GPIOLIB select ARM_AMBA select CLKDEV_LOOKUP select CLKSRC_LPC32XX select COMMON_CLK select CPU_ARM926T select GENERIC_CLOCKEVENTS + select GPIOLIB select MULTI_IRQ_HANDLER select SPARSE_IRQ select USE_OF @@ -543,7 +527,6 @@ config ARCH_PXA bool "PXA2xx/PXA3xx-based" depends on MMU select ARCH_MTD_XIP - select ARCH_REQUIRE_GPIOLIB select ARM_CPU_SUSPEND if PM select AUTO_ZRELADDR select COMMON_CLK @@ -554,6 +537,7 @@ config ARCH_PXA select CPU_XSCALE if !CPU_XSC3 select GENERIC_CLOCKEVENTS select GPIO_PXA + select GPIOLIB select HAVE_IDE select IRQ_DOMAIN select MULTI_IRQ_HANDLER @@ -584,7 +568,6 @@ config ARCH_RPC config ARCH_SA1100 bool "SA1100-based" select ARCH_MTD_XIP - select ARCH_REQUIRE_GPIOLIB select ARCH_SPARSEMEM_ENABLE select CLKDEV_LOOKUP select CLKSRC_MMIO @@ -593,6 +576,7 @@ config ARCH_SA1100 select CPU_FREQ select CPU_SA1100 select GENERIC_CLOCKEVENTS + select GPIOLIB select HAVE_IDE select IRQ_DOMAIN select ISA @@ -604,12 +588,12 @@ config ARCH_SA1100 config ARCH_S3C24XX bool "Samsung S3C24XX SoCs" - select ARCH_REQUIRE_GPIOLIB select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG + select GPIOLIB select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -625,12 +609,12 @@ config ARCH_S3C24XX config ARCH_DAVINCI bool "TI DaVinci" select ARCH_HAS_HOLES_MEMORYMODEL - select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CPU_ARM926T select GENERIC_ALLOCATOR select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP + select GPIOLIB select HAVE_IDE select USE_OF select ZONE_DMA @@ -642,11 +626,11 @@ config ARCH_OMAP1 depends on MMU select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_OMAP - select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP + select GPIOLIB select HAVE_IDE select IRQ_DOMAIN select MULTI_IRQ_HANDLER @@ -868,7 +852,7 @@ source "arch/arm/mach-zynq/Kconfig" config ARCH_EFM32 bool "Energy Micro efm32" depends on ARM_SINGLE_ARMV7M - select ARCH_REQUIRE_GPIOLIB + select GPIOLIB help Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko processors. @@ -901,7 +885,7 @@ config MACH_STM32F429 default y config ARCH_MPS2 - bool "ARM MPS2 paltform" + bool "ARM MPS2 platform" depends on ARM_SINGLE_ARMV7M select ARM_AMBA select CLKSRC_MPS2 @@ -1186,6 +1170,60 @@ config ARM_ERRATA_773022 loop buffer may deliver incorrect instructions. This workaround disables the loop buffer to avoid the erratum. +config ARM_ERRATA_818325_852422 + bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" + depends on CPU_V7 + help + This option enables the workaround for: + - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM + instruction might deadlock. Fixed in r0p1. + - Cortex-A12 852422: Execution of a sequence of instructions might + lead to either a data corruption or a CPU deadlock. Not fixed in + any Cortex-A12 cores yet. + This workaround for all both errata involves setting bit[12] of the + Feature Register. This bit disables an optimisation applied to a + sequence of 2 instructions that use opposing condition codes. + +config ARM_ERRATA_821420 + bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" + depends on CPU_V7 + help + This option enables the workaround for the 821420 Cortex-A12 + (all revs) erratum. In very rare timing conditions, a sequence + of VMOV to Core registers instructions, for which the second + one is in the shadow of a branch or abort, can lead to a + deadlock when the VMOV instructions are issued out-of-order. + +config ARM_ERRATA_825619 + bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 825619 Cortex-A12 + (all revs) erratum. Within rare timing constraints, executing a + DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable + and Device/Strongly-Ordered loads and stores might cause deadlock + +config ARM_ERRATA_852421 + bool "ARM errata: A17: DMB ST might fail to create order between stores" + depends on CPU_V7 + help + This option enables the workaround for the 852421 Cortex-A17 + (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, + execution of a DMB ST instruction might fail to properly order + stores from GroupA and stores from GroupB. + +config ARM_ERRATA_852423 + bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" + depends on CPU_V7 + help + This option enables the workaround for: + - Cortex-A17 852423: Execution of a sequence of instructions might + lead to either a data corruption or a CPU deadlock. Not fixed in + any Cortex-A17 cores yet. + This is identical to Cortex-A12 erratum 852422. It is a separate + config option from the A12 erratum due to the way errata are checked + for and handled. + endmenu source "arch/arm/common/Kconfig" |