diff options
Diffstat (limited to 'arch/arm/boot/dts/arm-realview-eb.dts')
| -rw-r--r-- | arch/arm/boot/dts/arm-realview-eb.dts | 166 |
1 files changed, 166 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/arm-realview-eb.dts b/arch/arm/boot/dts/arm-realview-eb.dts new file mode 100644 index 000000000000..15431077f00c --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb.dts @@ -0,0 +1,166 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include "arm-realview-eb.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard"; + compatible = "arm,realview-eb"; + arm,hbi = <0x140>; + + /* + * This is the core tile with the CPU and GIC etc for the + * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache + * or PMU. + * + * To run this machine with QEMU, specify the following: + * qemu-system-arm -M realview-eb + * Unless specified, QEMU will emulate an ARM926EJ-S core tile. + * Switches -cpu arm1136 or -cpu arm1176 emulates the other + * core tiles. + */ + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-eb-soc", "simple-bus"; + regmap = <&syscon>; + ranges; + + intc: interrupt-controller@10040000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10041000 0x1000>, + <0x10040000 0x100>; + }; + }; +}; + +/* + * This adapts all the peripherals to the interrupt routing + * to the GIC on the core tile. + */ + +ðernet { + interrupt-parent = <&intc>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usb { + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +}; + +&aaci { + interrupt-parent = <&intc>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi0 { + interrupt-parent = <&intc>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi1 { + interrupt-parent = <&intc>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +}; + +&charlcd { + interrupt-parent = <&intc>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial0 { + interrupt-parent = <&intc>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial1 { + interrupt-parent = <&intc>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial2 { + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial3 { + interrupt-parent = <&intc>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ssp { + interrupt-parent = <&intc>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog { + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer01 { + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer23 { + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio0 { + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&rtc { + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +}; + +&clcd { + interrupt-parent = <&intc>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +}; |