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Diffstat (limited to 'arch/arm/boot/dts/exynos54xx.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos54xx.dtsi35
1 files changed, 24 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 0389e8a10d0b..de26e5ee0d2d 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos54xx SoC series common device tree source
*
@@ -8,10 +9,6 @@
* Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
* Exynos 54xx SoCs should include this file and customize it further
* (e.g. with clocks).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include "exynos5.dtsi"
@@ -29,7 +26,27 @@
};
soc: soc {
- sysram@02020000 {
+ arm_a7_pmu: arm-a7-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ arm_a15_pmu: arm-a15-pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <1 2>,
+ <7 0>,
+ <16 6>,
+ <19 2>;
+ status = "disabled";
+ };
+
+ sysram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
#address-cells = <1>;
@@ -79,12 +96,6 @@
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
- sss: sss@10830000 {
- compatible = "samsung,exynos4210-secss";
- reg = <0x10830000 0x300>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- };
-
/* i2c_0-3 are defined in exynos5.dtsi */
hsi2c_4: i2c@12ca0000 {
compatible = "samsung,exynos5250-hsi2c";
@@ -134,6 +145,7 @@
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
+ snps,dis_u3_susphy_quirk;
};
};
@@ -154,6 +166,7 @@
reg = <0x12400000 0x10000>;
phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
phy-names = "usb2-phy", "usb3-phy";
+ snps,dis_u3_susphy_quirk;
};
};