diff options
Diffstat (limited to '')
-rw-r--r-- | arch/arm/boot/dts/qcom-apq8064.dtsi | 368 |
1 files changed, 206 insertions, 162 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 8b79b4112ee1..942aa2278355 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -2,6 +2,7 @@ /dts-v1/; #include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/clock/qcom,lcc-msm8960.h> #include <dt-bindings/reset/qcom,gcc-msm8960.h> #include <dt-bindings/clock/qcom,mmcc-msm8960.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -95,17 +96,17 @@ }; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0>; }; thermal-zones { - cpu-thermal0 { + cpu0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 7>; + thermal-sensors = <&tsens 7>; coefficients = <1199 0>; trips { @@ -122,11 +123,11 @@ }; }; - cpu-thermal1 { + cpu1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 8>; + thermal-sensors = <&tsens 8>; coefficients = <1132 0>; trips { @@ -143,11 +144,11 @@ }; }; - cpu-thermal2 { + cpu2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 9>; + thermal-sensors = <&tsens 9>; coefficients = <1199 0>; trips { @@ -164,11 +165,11 @@ }; }; - cpu-thermal3 { + cpu3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 10>; + thermal-sensors = <&tsens 10>; coefficients = <1132 0>; trips { @@ -198,7 +199,7 @@ clock-frequency = <19200000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -227,7 +228,7 @@ smd { compatible = "qcom,smd"; - modem@0 { + modem-edge { interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&l2cc 8 3>; @@ -236,7 +237,7 @@ status = "disabled"; }; - q6@1 { + q6-edge { interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&l2cc 8 15>; @@ -245,7 +246,7 @@ status = "disabled"; }; - dsps@3 { + dsps-edge { interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&sps_sic_non_secure 0x4080 0>; @@ -254,7 +255,7 @@ status = "disabled"; }; - riva@6 { + riva-edge { interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&l2cc 8 25>; @@ -315,7 +316,7 @@ firmware { scm { - compatible = "qcom,scm-apq8064"; + compatible = "qcom,scm-apq8064", "qcom,scm"; clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; clock-names = "core"; @@ -350,6 +351,7 @@ reg = <0x800000 0x4000>; gpio-controller; + gpio-ranges = <&tlmm_pinmux 0 0 90>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -429,8 +431,8 @@ }; sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; - reg = <0x12100000 0x10000>; + compatible = "syscon"; + reg = <0x12100000 0x10000>; }; gsbi1: gsbi@12440000 { @@ -682,12 +684,11 @@ pm8821_mpps: mpps@50 { compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; reg = <0x50>; - interrupts = <24 IRQ_TYPE_NONE>, - <25 IRQ_TYPE_NONE>, - <26 IRQ_TYPE_NONE>, - <27 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8821_mpps 0 0 4>; }; }; }; @@ -725,19 +726,9 @@ reg = <0x50>; gpio-controller; #gpio-cells = <2>; - interrupts = - <128 IRQ_TYPE_NONE>, - <129 IRQ_TYPE_NONE>, - <130 IRQ_TYPE_NONE>, - <131 IRQ_TYPE_NONE>, - <132 IRQ_TYPE_NONE>, - <133 IRQ_TYPE_NONE>, - <134 IRQ_TYPE_NONE>, - <135 IRQ_TYPE_NONE>, - <136 IRQ_TYPE_NONE>, - <137 IRQ_TYPE_NONE>, - <138 IRQ_TYPE_NONE>, - <139 IRQ_TYPE_NONE>; + gpio-ranges = <&pm8921_mpps 0 0 12>; + interrupt-controller; + #interrupt-cells = <2>; }; rtc@11d { @@ -765,40 +756,40 @@ #size-cells = <0>; #io-channel-cells = <2>; - vcoin: adc-channel@00 { + vcoin: adc-channel@0 { reg = <0x00 0x00>; }; - vbat: adc-channel@01 { + vbat: adc-channel@1 { reg = <0x00 0x01>; }; - dcin: adc-channel@02 { + dcin: adc-channel@2 { reg = <0x00 0x02>; }; - vph_pwr: adc-channel@04 { + vph_pwr: adc-channel@4 { reg = <0x00 0x04>; }; - batt_therm: adc-channel@08 { + batt_therm: adc-channel@8 { reg = <0x00 0x08>; }; - batt_id: adc-channel@09 { + batt_id: adc-channel@9 { reg = <0x00 0x09>; }; - usb_vbus: adc-channel@0a { + usb_vbus: adc-channel@a { reg = <0x00 0x0a>; }; - die_temp: adc-channel@0b { + die_temp: adc-channel@b { reg = <0x00 0x0b>; }; - ref_625mv: adc-channel@0c { + ref_625mv: adc-channel@c { reg = <0x00 0x0c>; }; - ref_1250mv: adc-channel@0d { + ref_1250mv: adc-channel@d { reg = <0x00 0x0d>; }; - chg_temp: adc-channel@0e { + chg_temp: adc-channel@e { reg = <0x00 0x0e>; }; - ref_muxoff: adc-channel@0f { + ref_muxoff: adc-channel@f { reg = <0x00 0x0f>; }; }; @@ -806,27 +797,41 @@ }; qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; + compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ranges; - tsens_calib: calib { + tsens_calib: calib@404 { reg = <0x404 0x10>; }; - tsens_backup: backup_calib { + tsens_backup: backup_calib@414 { reg = <0x414 0x10>; }; }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; + compatible = "qcom,gcc-apq8064", "syscon"; reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; - #thermal-sensor-cells = <1>; + clocks = <&cxo_board>, + <&pxo_board>, + <&lcc PLL4>; + clock-names = "cxo", "pxo", "pll4"; + + tsens: thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; }; lcc: clock-controller@28000000 { @@ -834,33 +839,66 @@ reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; mmcc: clock-controller@4000000 { compatible = "qcom,mmcc-apq8064"; reg = <0x4000000 0x1000>; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; }; l2cc: clock-controller@2011000 { - compatible = "syscon"; - reg = <0x2011000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; }; rpm@108000 { - compatible = "qcom,rpm-apq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; + compatible = "qcom,rpm-apq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", "err", "wakeup"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; + compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; }; regulators { @@ -1012,43 +1050,43 @@ }; sata_phy0: phy@1b400000 { - compatible = "qcom,apq8064-sata-phy"; - status = "disabled"; - reg = <0x1b400000 0x200>; - reg-names = "phy_mem"; - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - #phy-cells = <0>; + compatible = "qcom,apq8064-sata-phy"; + status = "disabled"; + reg = <0x1b400000 0x200>; + reg-names = "phy_mem"; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + #phy-cells = <0>; }; sata0: sata@29000000 { - compatible = "qcom,apq8064-ahci", "generic-ahci"; - status = "disabled"; - reg = <0x29000000 0x180>; - interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_iface", - "iface", - "bus", - "rxoob", - "core_pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy0>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; + compatible = "qcom,apq8064-ahci", "generic-ahci"; + status = "disabled"; + reg = <0x29000000 0x180>; + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_iface", + "iface", + "bus", + "rxoob", + "core_pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy0>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; }; /* Temporary fixed regulator */ - sdcc1bam:dma@12402000{ + sdcc1bam: dma-controller@12402000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; @@ -1058,7 +1096,7 @@ qcom,ee = <0>; }; - sdcc3bam:dma@12182000{ + sdcc3bam: dma-controller@12182000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; @@ -1068,7 +1106,7 @@ qcom,ee = <0>; }; - sdcc4bam:dma@121c2000{ + sdcc4bam: dma-controller@121c2000{ compatible = "qcom,bam-v1.3.0"; reg = <0x121c2000 0x8000>; interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; @@ -1083,19 +1121,19 @@ #address-cells = <1>; #size-cells = <1>; ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - pinctrl-names = "default"; - pinctrl-0 = <&sdcc1_pins>; + sdcc1: mmc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + pinctrl-names = "default"; + pinctrl-0 = <&sdcc1_pins>; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; + reg = <0x12400000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; @@ -1103,37 +1141,37 @@ dma-names = "tx", "rx"; }; - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <192000000>; + max-frequency = <192000000>; no-1-8-v; dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; dma-names = "tx", "rx"; }; - sdcc4: sdcc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; + sdcc4: mmc@121c0000 { + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x2000>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x121c0000 0x2000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; dma-names = "tx", "rx"; pinctrl-names = "default"; @@ -1147,22 +1185,21 @@ }; gpu: adreno-3xx@4300000 { - compatible = "qcom,adreno-3xx"; + compatible = "qcom,adreno-320.2", "qcom,adreno"; reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "kgsl_3d0_irq"; clock-names = - "core_clk", - "iface_clk", - "mem_clk", - "mem_iface_clk"; + "core", + "iface", + "mem", + "mem_iface"; clocks = <&mmcc GFX3D_CLK>, <&mmcc GFX3D_AHB_CLK>, <&mmcc GFX3D_AXI_CLK>, <&mmcc MMSS_IMEM_AHB_CLK>; - qcom,chipid = <0x03020002>; iommus = <&gfx3d 0 &gfx3d 1 @@ -1229,13 +1266,17 @@ &gfx3d1 30 &gfx3d1 31>; - qcom,gpu-pwrlevels { - compatible = "qcom,gpu-pwrlevels"; - qcom,gpu-pwrlevel@0 { - qcom,gpu-freq = <450000000>; + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <450000000>; }; - qcom,gpu-pwrlevel@1 { - qcom,gpu-freq = <27000000>; + + opp-27000000 { + opp-hz = /bits/ 64 <27000000>; }; }; }; @@ -1245,7 +1286,7 @@ reg = <0x5700000 0x70>; }; - dsi0: mdss_dsi@4700000 { + dsi0: dsi@4700000 { compatible = "qcom,mdss-dsi-ctrl"; label = "MDSS DSI CTRL->0"; #address-cells = <1>; @@ -1261,9 +1302,9 @@ <&mmcc DSI1_BYTE_CLK>, <&mmcc DSI_PIXEL_CLK>, <&mmcc DSI1_ESC_CLK>; - clock-names = "iface_clk", "bus_clk", "core_mmss_clk", - "src_clk", "byte_clk", "pixel_clk", - "core_clk"; + clock-names = "iface", "bus", "core_mmss", + "src", "byte", "pixel", + "core"; assigned-clocks = <&mmcc DSI1_BYTE_SRC>, <&mmcc DSI1_ESC_SRC>, @@ -1275,6 +1316,9 @@ <&dsi0_phy 1>; syscon-sfpb = <&mmss_sfpb>; phys = <&dsi0_phy>; + phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1303,9 +1347,10 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk", "ref"; + clock-names = "iface", "ref"; clocks = <&mmcc DSI_M_AHB_CLK>, - <&cxo_board>; + <&pxo_board>; + status = "disabled"; }; @@ -1374,11 +1419,11 @@ }; pcie: pci@1b500000 { - compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; + compatible = "qcom,pcie-apq8064"; + reg = <0x1b500000 0x1000>, + <0x1b502000 0x80>, + <0x1b600000 0x100>, + <0x0ff00000 0x100000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; @@ -1386,8 +1431,8 @@ num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */ + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */ + <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -1419,12 +1464,11 @@ clocks = <&mmcc HDMI_APP_CLK>, <&mmcc HDMI_M_AHB_CLK>, <&mmcc HDMI_S_AHB_CLK>; - clock-names = "core_clk", - "master_iface_clk", - "slave_iface_clk"; + clock-names = "core", + "master_iface", + "slave_iface"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; ports { #address-cells = <1>; @@ -1452,7 +1496,7 @@ "hdmi_pll"; clocks = <&mmcc HDMI_S_AHB_CLK>; - clock-names = "slave_iface_clk"; + clock-names = "slave_iface"; #phy-cells = <0>; }; @@ -1552,7 +1596,7 @@ qcom,mmio = <&riva>; - bt { + bluetooth { compatible = "qcom,wcnss-bt"; }; |