diff options
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8660.dtsi')
-rw-r--r-- | arch/arm/boot/dts/qcom-msm8660.dtsi | 178 |
1 files changed, 119 insertions, 59 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 1e8aab357f9c..ddce7d64ba99 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -50,22 +50,25 @@ }; clocks { - cxo_board { + cxo_board: cxo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; + clock-output-names = "cxo_board"; }; - pxo_board { + pxo_board: pxo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "pxo_board"; }; - sleep_clk { + sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; + clock-output-names = "sleep_clk"; }; }; @@ -126,8 +129,62 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8660"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + }; + + gsbi1: gsbi@16000000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16000000 0x100>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi1_spi: spi@16080000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + status = "disabled"; + + gsbi3_i2c: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16280000 0x1000>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; gsbi6: gsbi@16500000 { @@ -211,6 +268,7 @@ ranges; syscon-tcsr = <&tcsr>; + status = "disabled"; gsbi8_i2c: i2c@19880000 { compatible = "qcom,i2c-qup-v1.1.1"; @@ -390,25 +448,27 @@ }; l2cc: clock-controller@2082000 { - compatible = "syscon"; - reg = <0x02082000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x02082000 0x1000>; }; rpm: rpm@104000 { - compatible = "qcom,rpm-msm8660"; - reg = <0x00104000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; + compatible = "qcom,rpm-msm8660"; + reg = <0x00104000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", "err", "wakeup"; clocks = <&gcc RPM_MSG_RAM_H_CLK>; clock-names = "ram"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; + compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&pxo_board>; + clock-names = "pxo"; }; pm8901-regulators { @@ -484,80 +544,80 @@ #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; + reg = <0x12400000 0x8000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc2: mmc@12140000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12140000 0x8000>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; + reg = <0x12140000 0x8000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; no-1-8-v; }; sdcc4: mmc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x8000>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - max-frequency = <48000000>; + status = "disabled"; + reg = <0x121c0000 0x8000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc5: mmc@12200000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12200000 0x8000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12200000 0x8000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; }; }; |