diff options
Diffstat (limited to '')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 47 |
1 files changed, 33 insertions, 14 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 2a86e72d9791..4370e3cbbb4b 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -15,13 +15,13 @@ #size-cells = <0>; enable-method = "altr,socfpga-a10-smp"; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; @@ -29,7 +29,16 @@ }; }; - intc: intc@ffffd000 { + pmu: pmu@ff111000 { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 124 4>, <0 125 4>; + interrupt-affinity = <&cpu0>, <&cpu1>; + reg = <0xff111000 0x1000>, + <0xff113000 0x1000>; + }; + + intc: interrupt-controller@ffffd000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -64,8 +73,6 @@ <0 90 IRQ_TYPE_LEVEL_HIGH>, <0 91 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; @@ -431,8 +438,8 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; + clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; + clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; @@ -451,8 +458,8 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; + clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; + clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; @@ -471,8 +478,8 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; + clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; + clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; @@ -613,6 +620,7 @@ /*32bit_access;*/ clocks = <&spi_m_clk>; resets = <&rst SPIM0_RESET>; + reset-names = "spi"; status = "disabled"; }; @@ -628,6 +636,7 @@ rx-dma-channel = <&pdma 17>; clocks = <&spi_m_clk>; resets = <&rst SPIM1_RESET>; + reset-names = "spi"; status = "disabled"; }; @@ -636,7 +645,7 @@ reg = <0xffcfb100 0x80>; }; - L2: l2-cache@fffff000 { + L2: cache-controller@fffff000 { compatible = "arm,pl310-cache"; reg = <0xfffff000 0x1000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; @@ -727,6 +736,16 @@ <37 IRQ_TYPE_LEVEL_HIGH>; }; + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; + dma-ecc@ff8c8000 { compatible = "altr,socfpga-dma-ecc"; reg = <0xff8c8000 0x400>; @@ -745,7 +764,7 @@ }; qspi: spi@ff809000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff809000 0x100>, @@ -819,7 +838,7 @@ timer3: timer3@ffd00100 { compatible = "snps,dw-apb-timer"; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd01000 0x100>; + reg = <0xffd00100 0x100>; clocks = <&l4_sys_free_clk>; clock-names = "timer"; resets = <&rst L4SYSTIMER1_RESET>; |