8 files changed, 28 insertions, 13 deletions
diff --git a/arch/arm/boot/compressed/head-at91rm9200.S b/arch/arm/boot/compressed/head-at91rm9200.S
index 2119ea62b547..d68b9acd826e 100644
--- a/arch/arm/boot/compressed/head-at91rm9200.S
+++ b/arch/arm/boot/compressed/head-at91rm9200.S
@@ -49,6 +49,24 @@
 		cmp	r7, r3
 		beq	99f
 
+		@ Embest ATEB9200 : 923
+		mov	r3,	#(MACH_TYPE_ATEB9200 & 0xff)
+		orr	r3, r3,	#(MACH_TYPE_ATEB9200 & 0xff00)
+		cmp	r7, r3
+		beq	99f
+
+		@ Sperry-Sun KAFA : 662
+		mov	r3,	#(MACH_TYPE_KAFA & 0xff)
+		orr	r3, r3,	#(MACH_TYPE_KAFA & 0xff00)
+		cmp	r7, r3
+		beq	99f
+
+		@ Ajeco 1ARM : 1075
+		mov	r3,	#(MACH_TYPE_ONEARM & 0xff)
+		orr	r3, r3, #(MACH_TYPE_ONEARM & 0xff00)
+		cmp	r7, r3
+		beq	99f
+
 		@ Unknown board, use the AT91RM9200DK board
 		@ mov	r7, #MACH_TYPE_AT91RM9200
 		mov	r7,	#(MACH_TYPE_AT91RM9200DK & 0xff)
diff --git a/arch/arm/boot/compressed/head-clps7500.S b/arch/arm/boot/compressed/head-clps7500.S
index 4a8a689d15e6..941c5f5cbacf 100644
--- a/arch/arm/boot/compressed/head-clps7500.S
+++ b/arch/arm/boot/compressed/head-clps7500.S
@@ -4,7 +4,6 @@
  * Copyright (C) 1999, 2000, 2001 Nexus Electronics Ltd
  */
 
-#include <linux/config.h>
 
 		/* There are three different ways the kernel can be
 		   booted on a 7500 system: from Angel (loaded in RAM), from
diff --git a/arch/arm/boot/compressed/head-l7200.S b/arch/arm/boot/compressed/head-l7200.S
index b08bd23f8d16..d0e3b20856cd 100644
--- a/arch/arm/boot/compressed/head-l7200.S
+++ b/arch/arm/boot/compressed/head-l7200.S
@@ -7,7 +7,6 @@
  * is merged with head.S by the linker.
  */
 
-#include <linux/config.h>
 #include <asm/mach-types.h>
 
 #ifndef CONFIG_ARCH_L7200
diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
index 5aefffd46048..4c8c0e46027d 100644
--- a/arch/arm/boot/compressed/head-sa1100.S
+++ b/arch/arm/boot/compressed/head-sa1100.S
@@ -7,7 +7,6 @@
  *
  */
 
-#include <linux/config.h>
 #include <linux/linkage.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/boot/compressed/head-sharpsl.S b/arch/arm/boot/compressed/head-sharpsl.S
index 59ad69640d6b..eb0084ea1ec4 100644
--- a/arch/arm/boot/compressed/head-sharpsl.S
+++ b/arch/arm/boot/compressed/head-sharpsl.S
@@ -12,7 +12,6 @@
  *
  */
 
-#include <linux/config.h>
 #include <linux/linkage.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
index d3fe2533907e..73c5d9e0201c 100644
--- a/arch/arm/boot/compressed/head-xscale.S
+++ b/arch/arm/boot/compressed/head-xscale.S
@@ -5,7 +5,6 @@
  *
  */
 
-#include <linux/config.h>
 #include <linux/linkage.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b56f5e691d65..14a9ff9c68df 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -8,7 +8,6 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/config.h>
 #include <linux/linkage.h>
 
 /*
@@ -448,8 +447,11 @@ __common_mmu_cache_on:
 		mov	r1, #-1
 		mcr	p15, 0, r3, c2, c0, 0	@ load page table pointer
 		mcr	p15, 0, r1, c3, c0, 0	@ load domain access control
-		mcr	p15, 0, r0, c1, c0, 0	@ load control register
-		mov	pc, lr
+		b	1f
+		.align	5			@ cache line aligned
+1:		mcr	p15, 0, r0, c1, c0, 0	@ load control register
+		mrc	p15, 0, r0, c1, c0, 0	@ and read it back to
+		sub	pc, lr, r0, lsr #32	@ properly flush pipeline
 
 /*
  * All code following this line is relocatable.  It is relocated by
@@ -605,8 +607,8 @@ proc_types:
 		b	__armv4_mmu_cache_off
 		b	__armv4_mmu_cache_flush
 
-		.word	0x00070000		@ ARMv6
-		.word	0x000f0000
+		.word	0x0007b000		@ ARMv6
+		.word	0x0007f000
 		b	__armv4_mmu_cache_on
 		b	__armv4_mmu_cache_off
 		b	__armv6_mmu_cache_flush
diff --git a/arch/arm/boot/compressed/ll_char_wr.S b/arch/arm/boot/compressed/ll_char_wr.S
index d7bbd9da2fca..8517c8606b4a 100644
--- a/arch/arm/boot/compressed/ll_char_wr.S
+++ b/arch/arm/boot/compressed/ll_char_wr.S
@@ -77,7 +77,7 @@ Lrow4bpplp:
 	subne	r1, r1, #1
 	ldrneb	r7, [r6, r1]
 	bne	Lrow4bpplp
-	LOADREGS(fd, sp!, {r4 - r7, pc})
+	ldmfd	sp!, {r4 - r7, pc}
 
 @
 @ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
@@ -105,7 +105,7 @@ Lrow8bpplp:
 	subne	r1, r1, #1
 	ldrneb	r7, [r6, r1]
 	bne	Lrow8bpplp
-	LOADREGS(fd, sp!, {r4 - r7, pc})
+	ldmfd	sp!, {r4 - r7, pc}
 
 @
 @ Smashable regs: {r0 - r3}, [r4], {r5, r6}, [r7], (r8 - fp), [ip], (sp), [lr], (pc)
@@ -127,7 +127,7 @@ Lrow1bpp:
 	strb	r7, [r0], r5
 	mov	r7, r7, lsr #8
 	strb	r7, [r0], r5
-	LOADREGS(fd, sp!, {r4 - r7, pc})
+	ldmfd	sp!, {r4 - r7, pc}
 
 	.bss
 ENTRY(con_charconvtable)