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-rw-r--r--arch/arm/mach-davinci/da8xx.h (renamed from arch/arm/mach-davinci/include/mach/da8xx.h)11
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h79
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h86
-rw-r--r--arch/arm/mach-davinci/include/mach/hardware.h33
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h990
-rw-r--r--arch/arm/mach-davinci/include/mach/pm.h54
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h37
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h97
8 files changed, 5 insertions, 1382 deletions
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/da8xx.h
index 1618b30661a9..382811dbbc3b 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/da8xx.h
@@ -1,12 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Chip specific defines for DA8XX/OMAP L1XX SoC
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
- * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007, 2009-2010 (c) MontaVista Software, Inc.
*/
#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
#define __ASM_ARCH_DAVINCI_DA8XX_H
@@ -21,8 +19,9 @@
#include <linux/regmap.h>
#include <linux/videodev2.h>
-#include <mach/serial.h>
-#include <mach/pm.h>
+#include "serial.h"
+#include "pm.h"
+
#include <linux/platform_data/edma.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/mmc-davinci.h>
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
deleted file mode 100644
index 139b83de011d..000000000000
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Header for code common to all DaVinci machines.
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
-#define __ARCH_ARM_MACH_DAVINCI_COMMON_H
-
-#include <linux/clk.h>
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/reboot.h>
-
-#include <asm/irq.h>
-
-#define DAVINCI_INTC_START NR_IRQS
-#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
-
-struct davinci_gpio_controller;
-
-/*
- * SoC info passed into common davinci modules.
- *
- * Base addresses in this structure should be physical and not virtual.
- * Modules that take such base addresses, should internally ioremap() them to
- * use.
- */
-struct davinci_soc_info {
- struct map_desc *io_desc;
- unsigned long io_desc_num;
- u32 cpu_id;
- u32 jtag_id;
- u32 jtag_id_reg;
- struct davinci_id *ids;
- unsigned long ids_num;
- u32 pinmux_base;
- const struct mux_config *pinmux_pins;
- unsigned long pinmux_pins_num;
- int gpio_type;
- u32 gpio_base;
- unsigned gpio_num;
- unsigned gpio_irq;
- unsigned gpio_unbanked;
- struct davinci_gpio_controller *gpio_ctlrs;
- int gpio_ctlrs_num;
- struct emac_platform_data *emac_pdata;
- dma_addr_t sram_dma;
- unsigned sram_len;
-};
-
-extern struct davinci_soc_info davinci_soc_info;
-
-extern void davinci_common_init(const struct davinci_soc_info *soc_info);
-extern void davinci_init_ide(void);
-void davinci_init_late(void);
-
-#ifdef CONFIG_CPU_FREQ
-int davinci_cpufreq_init(void);
-#else
-static inline int davinci_cpufreq_init(void) { return 0; }
-#endif
-
-#ifdef CONFIG_SUSPEND
-int davinci_pm_init(void);
-#else
-static inline int davinci_pm_init(void) { return 0; }
-#endif
-
-void __init pdata_quirks_init(void);
-
-#define SRAM_SIZE SZ_128K
-
-#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
deleted file mode 100644
index 1fc84e21664d..000000000000
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * DaVinci CPU type detection
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * Defines the cpu_is_*() macros for runtime detection of DaVinci
- * device type. In addition, if support for a given device is not
- * compiled in to the kernel, the macros return 0 so that
- * resulting code can be optimized out.
- *
- * 2009 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef _ASM_ARCH_CPU_H
-#define _ASM_ARCH_CPU_H
-
-#include <mach/common.h>
-
-struct davinci_id {
- u8 variant; /* JTAG ID bits 31:28 */
- u16 part_no; /* JTAG ID bits 27:12 */
- u16 manufacturer; /* JTAG ID bits 11:1 */
- u32 cpu_id;
- char *name;
-};
-
-/* Can use lower 16 bits of cpu id for a variant when required */
-#define DAVINCI_CPU_ID_DM6446 0x64460000
-#define DAVINCI_CPU_ID_DM6467 0x64670000
-#define DAVINCI_CPU_ID_DM355 0x03550000
-#define DAVINCI_CPU_ID_DM365 0x03650000
-#define DAVINCI_CPU_ID_DA830 0x08300000
-#define DAVINCI_CPU_ID_DA850 0x08500000
-
-#define IS_DAVINCI_CPU(type, id) \
-static inline int is_davinci_ ##type(void) \
-{ \
- return (davinci_soc_info.cpu_id == (id)); \
-}
-
-IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
-IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
-IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
-IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
-IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
-IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
-
-#ifdef CONFIG_ARCH_DAVINCI_DM644x
-#define cpu_is_davinci_dm644x() is_davinci_dm644x()
-#else
-#define cpu_is_davinci_dm644x() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DM646x
-#define cpu_is_davinci_dm646x() is_davinci_dm646x()
-#else
-#define cpu_is_davinci_dm646x() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DM355
-#define cpu_is_davinci_dm355() is_davinci_dm355()
-#else
-#define cpu_is_davinci_dm355() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DM365
-#define cpu_is_davinci_dm365() is_davinci_dm365()
-#else
-#define cpu_is_davinci_dm365() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DA830
-#define cpu_is_davinci_da830() is_davinci_da830()
-#else
-#define cpu_is_davinci_da830() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DA850
-#define cpu_is_davinci_da850() is_davinci_da850()
-#else
-#define cpu_is_davinci_da850() 0
-#endif
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
deleted file mode 100644
index 16bb42291d39..000000000000
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Hardware definitions common to all DaVinci family processors
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/*
- * Before you add anything to ths file:
- *
- * This header is for defines common to ALL DaVinci family chips.
- * Anything that is chip specific should go in <chipname>.h,
- * and the chip/board init code should then explicitly include
- * <chipname>.h
- */
-/*
- * I/O mapping
- */
-#define IO_PHYS UL(0x01c00000)
-#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
-#define IO_SIZE 0x00400000
-#define IO_VIRT (IO_PHYS + IO_OFFSET)
-#define io_v2p(va) ((va) - IO_OFFSET)
-#define __IO_ADDRESS(x) ((x) + IO_OFFSET)
-#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
deleted file mode 100644
index 631655e68ae0..000000000000
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ /dev/null
@@ -1,990 +0,0 @@
-/*
- * Table of the DAVINCI register configurations for the PINMUX combinations
- *
- * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
- *
- * Based on linux/include/asm-arm/arch-omap/mux.h:
- * Copyright (C) 2003 - 2005 Nokia Corporation
- *
- * Written by Tony Lindgren
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Copyright (C) 2008 Texas Instruments.
- */
-
-#ifndef __INC_MACH_MUX_H
-#define __INC_MACH_MUX_H
-
-struct mux_config {
- const char *name;
- const char *mux_reg_name;
- const unsigned char mux_reg;
- const unsigned char mask_offset;
- const unsigned char mask;
- const unsigned char mode;
- bool debug;
-};
-
-enum davinci_dm644x_index {
- /* ATA and HDDIR functions */
- DM644X_HDIREN,
- DM644X_ATAEN,
- DM644X_ATAEN_DISABLE,
-
- /* HPI functions */
- DM644X_HPIEN_DISABLE,
-
- /* AEAW functions */
- DM644X_AEAW,
- DM644X_AEAW0,
- DM644X_AEAW1,
- DM644X_AEAW2,
- DM644X_AEAW3,
- DM644X_AEAW4,
-
- /* Memory Stick */
- DM644X_MSTK,
-
- /* I2C */
- DM644X_I2C,
-
- /* ASP function */
- DM644X_MCBSP,
-
- /* UART1 */
- DM644X_UART1,
-
- /* UART2 */
- DM644X_UART2,
-
- /* PWM0 */
- DM644X_PWM0,
-
- /* PWM1 */
- DM644X_PWM1,
-
- /* PWM2 */
- DM644X_PWM2,
-
- /* VLYNQ function */
- DM644X_VLYNQEN,
- DM644X_VLSCREN,
- DM644X_VLYNQWD,
-
- /* EMAC and MDIO function */
- DM644X_EMACEN,
-
- /* GPIO3V[0:16] pins */
- DM644X_GPIO3V,
-
- /* GPIO pins */
- DM644X_GPIO0,
- DM644X_GPIO3,
- DM644X_GPIO43_44,
- DM644X_GPIO46_47,
-
- /* VPBE */
- DM644X_RGB666,
-
- /* LCD */
- DM644X_LOEEN,
- DM644X_LFLDEN,
-};
-
-enum davinci_dm646x_index {
- /* ATA function */
- DM646X_ATAEN,
-
- /* AUDIO Clock */
- DM646X_AUDCK1,
- DM646X_AUDCK0,
-
- /* CRGEN Control */
- DM646X_CRGMUX,
-
- /* VPIF Control */
- DM646X_STSOMUX_DISABLE,
- DM646X_STSIMUX_DISABLE,
- DM646X_PTSOMUX_DISABLE,
- DM646X_PTSIMUX_DISABLE,
-
- /* TSIF Control */
- DM646X_STSOMUX,
- DM646X_STSIMUX,
- DM646X_PTSOMUX_PARALLEL,
- DM646X_PTSIMUX_PARALLEL,
- DM646X_PTSOMUX_SERIAL,
- DM646X_PTSIMUX_SERIAL,
-};
-
-enum davinci_dm355_index {
- /* MMC/SD 0 */
- DM355_MMCSD0,
-
- /* MMC/SD 1 */
- DM355_SD1_CLK,
- DM355_SD1_CMD,
- DM355_SD1_DATA3,
- DM355_SD1_DATA2,
- DM355_SD1_DATA1,
- DM355_SD1_DATA0,
-
- /* I2C */
- DM355_I2C_SDA,
- DM355_I2C_SCL,
-
- /* ASP0 function */
- DM355_MCBSP0_BDX,
- DM355_MCBSP0_X,
- DM355_MCBSP0_BFSX,
- DM355_MCBSP0_BDR,
- DM355_MCBSP0_R,
- DM355_MCBSP0_BFSR,
-
- /* SPI0 */
- DM355_SPI0_SDI,
- DM355_SPI0_SDENA0,
- DM355_SPI0_SDENA1,
-
- /* IRQ muxing */
- DM355_INT_EDMA_CC,
- DM355_INT_EDMA_TC0_ERR,
- DM355_INT_EDMA_TC1_ERR,
-
- /* EDMA event muxing */
- DM355_EVT8_ASP1_TX,
- DM355_EVT9_ASP1_RX,
- DM355_EVT26_MMC0_RX,
-
- /* Video Out */
- DM355_VOUT_FIELD,
- DM355_VOUT_FIELD_G70,
- DM355_VOUT_HVSYNC,
- DM355_VOUT_COUTL_EN,
- DM355_VOUT_COUTH_EN,
-
- /* Video In Pin Mux */
- DM355_VIN_PCLK,
- DM355_VIN_CAM_WEN,
- DM355_VIN_CAM_VD,
- DM355_VIN_CAM_HD,
- DM355_VIN_YIN_EN,
- DM355_VIN_CINL_EN,
- DM355_VIN_CINH_EN,
-};
-
-enum davinci_dm365_index {
- /* MMC/SD 0 */
- DM365_MMCSD0,
-
- /* MMC/SD 1 */
- DM365_SD1_CLK,
- DM365_SD1_CMD,
- DM365_SD1_DATA3,
- DM365_SD1_DATA2,
- DM365_SD1_DATA1,
- DM365_SD1_DATA0,
-
- /* I2C */
- DM365_I2C_SDA,
- DM365_I2C_SCL,
-
- /* AEMIF */
- DM365_AEMIF_AR_A14,
- DM365_AEMIF_AR_BA0,
- DM365_AEMIF_A3,
- DM365_AEMIF_A7,
- DM365_AEMIF_D15_8,
- DM365_AEMIF_CE0,
- DM365_AEMIF_CE1,
- DM365_AEMIF_WE_OE,
-
- /* ASP0 function */
- DM365_MCBSP0_BDX,
- DM365_MCBSP0_X,
- DM365_MCBSP0_BFSX,
- DM365_MCBSP0_BDR,
- DM365_MCBSP0_R,
- DM365_MCBSP0_BFSR,
-
- /* SPI0 */
- DM365_SPI0_SCLK,
- DM365_SPI0_SDI,
- DM365_SPI0_SDO,
- DM365_SPI0_SDENA0,
- DM365_SPI0_SDENA1,
-
- /* UART */
- DM365_UART0_RXD,
- DM365_UART0_TXD,
- DM365_UART1_RXD,
- DM365_UART1_TXD,
- DM365_UART1_RTS,
- DM365_UART1_CTS,
-
- /* EMAC */
- DM365_EMAC_TX_EN,
- DM365_EMAC_TX_CLK,
- DM365_EMAC_COL,
- DM365_EMAC_TXD3,
- DM365_EMAC_TXD2,
- DM365_EMAC_TXD1,
- DM365_EMAC_TXD0,
- DM365_EMAC_RXD3,
- DM365_EMAC_RXD2,
- DM365_EMAC_RXD1,
- DM365_EMAC_RXD0,
- DM365_EMAC_RX_CLK,
- DM365_EMAC_RX_DV,
- DM365_EMAC_RX_ER,
- DM365_EMAC_CRS,
- DM365_EMAC_MDIO,
- DM365_EMAC_MDCLK,
-
- /* Key Scan */
- DM365_KEYSCAN,
-
- /* PWM */
- DM365_PWM0,
- DM365_PWM0_G23,
- DM365_PWM1,
- DM365_PWM1_G25,
- DM365_PWM2_G87,
- DM365_PWM2_G88,
- DM365_PWM2_G89,
- DM365_PWM2_G90,
- DM365_PWM3_G80,
- DM365_PWM3_G81,
- DM365_PWM3_G85,
- DM365_PWM3_G86,
-
- /* SPI1 */
- DM365_SPI1_SCLK,
- DM365_SPI1_SDO,
- DM365_SPI1_SDI,
- DM365_SPI1_SDENA0,
- DM365_SPI1_SDENA1,
-
- /* SPI2 */
- DM365_SPI2_SCLK,
- DM365_SPI2_SDO,
- DM365_SPI2_SDI,
- DM365_SPI2_SDENA0,
- DM365_SPI2_SDENA1,
-
- /* SPI3 */
- DM365_SPI3_SCLK,
- DM365_SPI3_SDO,
- DM365_SPI3_SDI,
- DM365_SPI3_SDENA0,
- DM365_SPI3_SDENA1,
-
- /* SPI4 */
- DM365_SPI4_SCLK,
- DM365_SPI4_SDO,
- DM365_SPI4_SDI,
- DM365_SPI4_SDENA0,
- DM365_SPI4_SDENA1,
-
- /* Clock */
- DM365_CLKOUT0,
- DM365_CLKOUT1,
- DM365_CLKOUT2,
-
- /* GPIO */
- DM365_GPIO20,
- DM365_GPIO30,
- DM365_GPIO31,
- DM365_GPIO32,
- DM365_GPIO33,
- DM365_GPIO40,
- DM365_GPIO64_57,
-
- /* Video */
- DM365_VOUT_FIELD,
- DM365_VOUT_FIELD_G81,
- DM365_VOUT_HVSYNC,
- DM365_VOUT_COUTL_EN,
- DM365_VOUT_COUTH_EN,
- DM365_VIN_CAM_WEN,
- DM365_VIN_CAM_VD,
- DM365_VIN_CAM_HD,
- DM365_VIN_YIN4_7_EN,
- DM365_VIN_YIN0_3_EN,
-
- /* IRQ muxing */
- DM365_INT_EDMA_CC,
- DM365_INT_EDMA_TC0_ERR,
- DM365_INT_EDMA_TC1_ERR,
- DM365_INT_EDMA_TC2_ERR,
- DM365_INT_EDMA_TC3_ERR,
- DM365_INT_PRTCSS,
- DM365_INT_EMAC_RXTHRESH,
- DM365_INT_EMAC_RXPULSE,
- DM365_INT_EMAC_TXPULSE,
- DM365_INT_EMAC_MISCPULSE,
- DM365_INT_IMX0_ENABLE,
- DM365_INT_IMX0_DISABLE,
- DM365_INT_HDVICP_ENABLE,
- DM365_INT_HDVICP_DISABLE,
- DM365_INT_IMX1_ENABLE,
- DM365_INT_IMX1_DISABLE,
- DM365_INT_NSF_ENABLE,
- DM365_INT_NSF_DISABLE,
-
- /* EDMA event muxing */
- DM365_EVT2_ASP_TX,
- DM365_EVT3_ASP_RX,
- DM365_EVT2_VC_TX,
- DM365_EVT3_VC_RX,
- DM365_EVT26_MMC0_RX,
-};
-
-enum da830_index {
- DA830_GPIO7_14,
- DA830_RTCK,
- DA830_GPIO7_15,
- DA830_EMU_0,
- DA830_EMB_SDCKE,
- DA830_EMB_CLK_GLUE,
- DA830_EMB_CLK,
- DA830_NEMB_CS_0,
- DA830_NEMB_CAS,
- DA830_NEMB_RAS,
- DA830_NEMB_WE,
- DA830_EMB_BA_1,
- DA830_EMB_BA_0,
- DA830_EMB_A_0,
- DA830_EMB_A_1,
- DA830_EMB_A_2,
- DA830_EMB_A_3,
- DA830_EMB_A_4,
- DA830_EMB_A_5,
- DA830_GPIO7_0,
- DA830_GPIO7_1,
- DA830_GPIO7_2,
- DA830_GPIO7_3,
- DA830_GPIO7_4,
- DA830_GPIO7_5,
- DA830_GPIO7_6,
- DA830_GPIO7_7,
- DA830_EMB_A_6,
- DA830_EMB_A_7,
- DA830_EMB_A_8,
- DA830_EMB_A_9,
- DA830_EMB_A_10,
- DA830_EMB_A_11,
- DA830_EMB_A_12,
- DA830_EMB_D_31,
- DA830_GPIO7_8,
- DA830_GPIO7_9,
- DA830_GPIO7_10,
- DA830_GPIO7_11,
- DA830_GPIO7_12,
- DA830_GPIO7_13,
- DA830_GPIO3_13,
- DA830_EMB_D_30,
- DA830_EMB_D_29,
- DA830_EMB_D_28,
- DA830_EMB_D_27,
- DA830_EMB_D_26,
- DA830_EMB_D_25,
- DA830_EMB_D_24,
- DA830_EMB_D_23,
- DA830_EMB_D_22,
- DA830_EMB_D_21,
- DA830_EMB_D_20,
- DA830_EMB_D_19,
- DA830_EMB_D_18,
- DA830_EMB_D_17,
- DA830_EMB_D_16,
- DA830_NEMB_WE_DQM_3,
- DA830_NEMB_WE_DQM_2,
- DA830_EMB_D_0,
- DA830_EMB_D_1,
- DA830_EMB_D_2,
- DA830_EMB_D_3,
- DA830_EMB_D_4,
- DA830_EMB_D_5,
- DA830_EMB_D_6,
- DA830_GPIO6_0,
- DA830_GPIO6_1,
- DA830_GPIO6_2,
- DA830_GPIO6_3,
- DA830_GPIO6_4,
- DA830_GPIO6_5,
- DA830_GPIO6_6,
- DA830_EMB_D_7,
- DA830_EMB_D_8,
- DA830_EMB_D_9,
- DA830_EMB_D_10,
- DA830_EMB_D_11,
- DA830_EMB_D_12,
- DA830_EMB_D_13,
- DA830_EMB_D_14,
- DA830_GPIO6_7,
- DA830_GPIO6_8,
- DA830_GPIO6_9,
- DA830_GPIO6_10,
- DA830_GPIO6_11,
- DA830_GPIO6_12,
- DA830_GPIO6_13,
- DA830_GPIO6_14,
- DA830_EMB_D_15,
- DA830_NEMB_WE_DQM_1,
- DA830_NEMB_WE_DQM_0,
- DA830_SPI0_SOMI_0,
- DA830_SPI0_SIMO_0,
- DA830_SPI0_CLK,
- DA830_NSPI0_ENA,
- DA830_NSPI0_SCS_0,
- DA830_EQEP0I,
- DA830_EQEP0S,
- DA830_EQEP1I,
- DA830_NUART0_CTS,
- DA830_NUART0_RTS,
- DA830_EQEP0A,
- DA830_EQEP0B,
- DA830_GPIO6_15,
- DA830_GPIO5_14,
- DA830_GPIO5_15,
- DA830_GPIO5_0,
- DA830_GPIO5_1,
- DA830_GPIO5_2,
- DA830_GPIO5_3,
- DA830_GPIO5_4,
- DA830_SPI1_SOMI_0,
- DA830_SPI1_SIMO_0,
- DA830_SPI1_CLK,
- DA830_UART0_RXD,
- DA830_UART0_TXD,
- DA830_AXR1_10,
- DA830_AXR1_11,
- DA830_NSPI1_ENA,
- DA830_I2C1_SCL,
- DA830_I2C1_SDA,
- DA830_EQEP1S,
- DA830_I2C0_SDA,
- DA830_I2C0_SCL,
- DA830_UART2_RXD,
- DA830_TM64P0_IN12,
- DA830_TM64P0_OUT12,
- DA830_GPIO5_5,
- DA830_GPIO5_6,
- DA830_GPIO5_7,
- DA830_GPIO5_8,
- DA830_GPIO5_9,
- DA830_GPIO5_10,
- DA830_GPIO5_11,
- DA830_GPIO5_12,
- DA830_NSPI1_SCS_0,
- DA830_USB0_DRVVBUS,
- DA830_AHCLKX0,
- DA830_ACLKX0,
- DA830_AFSX0,
- DA830_AHCLKR0,
- DA830_ACLKR0,
- DA830_AFSR0,
- DA830_UART2_TXD,
- DA830_AHCLKX2,
- DA830_ECAP0_APWM0,
- DA830_RMII_MHZ_50_CLK,
- DA830_ECAP1_APWM1,
- DA830_USB_REFCLKIN,
- DA830_GPIO5_13,
- DA830_GPIO4_15,
- DA830_GPIO2_11,
- DA830_GPIO2_12,
- DA830_GPIO2_13,
- DA830_GPIO2_14,
- DA830_GPIO2_15,
- DA830_GPIO3_12,
- DA830_AMUTE0,
- DA830_AXR0_0,
- DA830_AXR0_1,
- DA830_AXR0_2,
- DA830_AXR0_3,
- DA830_AXR0_4,
- DA830_AXR0_5,
- DA830_AXR0_6,
- DA830_RMII_TXD_0,
- DA830_RMII_TXD_1,
- DA830_RMII_TXEN,
- DA830_RMII_CRS_DV,
- DA830_RMII_RXD_0,
- DA830_RMII_RXD_1,
- DA830_RMII_RXER,
- DA830_AFSR2,
- DA830_ACLKX2,
- DA830_AXR2_3,
- DA830_AXR2_2,
- DA830_AXR2_1,
- DA830_AFSX2,
- DA830_ACLKR2,
- DA830_NRESETOUT,
- DA830_GPIO3_0,
- DA830_GPIO3_1,
- DA830_GPIO3_2,
- DA830_GPIO3_3,
- DA830_GPIO3_4,
- DA830_GPIO3_5,
- DA830_GPIO3_6,
- DA830_AXR0_7,
- DA830_AXR0_8,
- DA830_UART1_RXD,
- DA830_UART1_TXD,
- DA830_AXR0_11,
- DA830_AHCLKX1,
- DA830_ACLKX1,
- DA830_AFSX1,
- DA830_MDIO_CLK,
- DA830_MDIO_D,
- DA830_AXR0_9,
- DA830_AXR0_10,
- DA830_EPWM0B,
- DA830_EPWM0A,
- DA830_EPWMSYNCI,
- DA830_AXR2_0,
- DA830_EPWMSYNC0,
- DA830_GPIO3_7,
- DA830_GPIO3_8,
- DA830_GPIO3_9,
- DA830_GPIO3_10,
- DA830_GPIO3_11,
- DA830_GPIO3_14,
- DA830_GPIO3_15,
- DA830_GPIO4_10,
- DA830_AHCLKR1,
- DA830_ACLKR1,
- DA830_AFSR1,
- DA830_AMUTE1,
- DA830_AXR1_0,
- DA830_AXR1_1,
- DA830_AXR1_2,
- DA830_AXR1_3,
- DA830_ECAP2_APWM2,
- DA830_EHRPWMGLUETZ,
- DA830_EQEP1A,
- DA830_GPIO4_11,
- DA830_GPIO4_12,
- DA830_GPIO4_13,
- DA830_GPIO4_14,
- DA830_GPIO4_0,
- DA830_GPIO4_1,
- DA830_GPIO4_2,
- DA830_GPIO4_3,
- DA830_AXR1_4,
- DA830_AXR1_5,
- DA830_AXR1_6,
- DA830_AXR1_7,
- DA830_AXR1_8,
- DA830_AXR1_9,
- DA830_EMA_D_0,
- DA830_EMA_D_1,
- DA830_EQEP1B,
- DA830_EPWM2B,
- DA830_EPWM2A,
- DA830_EPWM1B,
- DA830_EPWM1A,
- DA830_MMCSD_DAT_0,
- DA830_MMCSD_DAT_1,
- DA830_UHPI_HD_0,
- DA830_UHPI_HD_1,
- DA830_GPIO4_4,
- DA830_GPIO4_5,
- DA830_GPIO4_6,
- DA830_GPIO4_7,
- DA830_GPIO4_8,
- DA830_GPIO4_9,
- DA830_GPIO0_0,
- DA830_GPIO0_1,
- DA830_EMA_D_2,
- DA830_EMA_D_3,
- DA830_EMA_D_4,
- DA830_EMA_D_5,
- DA830_EMA_D_6,
- DA830_EMA_D_7,
- DA830_EMA_D_8,
- DA830_EMA_D_9,
- DA830_MMCSD_DAT_2,
- DA830_MMCSD_DAT_3,
- DA830_MMCSD_DAT_4,
- DA830_MMCSD_DAT_5,
- DA830_MMCSD_DAT_6,
- DA830_MMCSD_DAT_7,
- DA830_UHPI_HD_8,
- DA830_UHPI_HD_9,
- DA830_UHPI_HD_2,
- DA830_UHPI_HD_3,
- DA830_UHPI_HD_4,
- DA830_UHPI_HD_5,
- DA830_UHPI_HD_6,
- DA830_UHPI_HD_7,
- DA830_LCD_D_8,
- DA830_LCD_D_9,
- DA830_GPIO0_2,
- DA830_GPIO0_3,
- DA830_GPIO0_4,
- DA830_GPIO0_5,
- DA830_GPIO0_6,
- DA830_GPIO0_7,
- DA830_GPIO0_8,
- DA830_GPIO0_9,
- DA830_EMA_D_10,
- DA830_EMA_D_11,
- DA830_EMA_D_12,
- DA830_EMA_D_13,
- DA830_EMA_D_14,
- DA830_EMA_D_15,
- DA830_EMA_A_0,
- DA830_EMA_A_1,
- DA830_UHPI_HD_10,
- DA830_UHPI_HD_11,
- DA830_UHPI_HD_12,
- DA830_UHPI_HD_13,
- DA830_UHPI_HD_14,
- DA830_UHPI_HD_15,
- DA830_LCD_D_7,
- DA830_MMCSD_CLK,
- DA830_LCD_D_10,
- DA830_LCD_D_11,
- DA830_LCD_D_12,
- DA830_LCD_D_13,
- DA830_LCD_D_14,
- DA830_LCD_D_15,
- DA830_UHPI_HCNTL0,
- DA830_GPIO0_10,
- DA830_GPIO0_11,
- DA830_GPIO0_12,
- DA830_GPIO0_13,
- DA830_GPIO0_14,
- DA830_GPIO0_15,
- DA830_GPIO1_0,
- DA830_GPIO1_1,
- DA830_EMA_A_2,
- DA830_EMA_A_3,
- DA830_EMA_A_4,
- DA830_EMA_A_5,
- DA830_EMA_A_6,
- DA830_EMA_A_7,
- DA830_EMA_A_8,
- DA830_EMA_A_9,
- DA830_MMCSD_CMD,
- DA830_LCD_D_6,
- DA830_LCD_D_3,
- DA830_LCD_D_2,
- DA830_LCD_D_1,
- DA830_LCD_D_0,
- DA830_LCD_PCLK,
- DA830_LCD_HSYNC,
- DA830_UHPI_HCNTL1,
- DA830_GPIO1_2,
- DA830_GPIO1_3,
- DA830_GPIO1_4,
- DA830_GPIO1_5,
- DA830_GPIO1_6,
- DA830_GPIO1_7,
- DA830_GPIO1_8,
- DA830_GPIO1_9,
- DA830_EMA_A_10,
- DA830_EMA_A_11,
- DA830_EMA_A_12,
- DA830_EMA_BA_1,
- DA830_EMA_BA_0,
- DA830_EMA_CLK,
- DA830_EMA_SDCKE,
- DA830_NEMA_CAS,
- DA830_LCD_VSYNC,
- DA830_NLCD_AC_ENB_CS,
- DA830_LCD_MCLK,
- DA830_LCD_D_5,
- DA830_LCD_D_4,
- DA830_OBSCLK,
- DA830_NEMA_CS_4,
- DA830_UHPI_HHWIL,
- DA830_AHCLKR2,
- DA830_GPIO1_10,
- DA830_GPIO1_11,
- DA830_GPIO1_12,
- DA830_GPIO1_13,
- DA830_GPIO1_14,
- DA830_GPIO1_15,
- DA830_GPIO2_0,
- DA830_GPIO2_1,
- DA830_NEMA_RAS,
- DA830_NEMA_WE,
- DA830_NEMA_CS_0,
- DA830_NEMA_CS_2,
- DA830_NEMA_CS_3,
- DA830_NEMA_OE,
- DA830_NEMA_WE_DQM_1,
- DA830_NEMA_WE_DQM_0,
- DA830_NEMA_CS_5,
- DA830_UHPI_HRNW,
- DA830_NUHPI_HAS,
- DA830_NUHPI_HCS,
- DA830_NUHPI_HDS1,
- DA830_NUHPI_HDS2,
- DA830_NUHPI_HINT,
- DA830_AXR0_12,
- DA830_AMUTE2,
- DA830_AXR0_13,
- DA830_AXR0_14,
- DA830_AXR0_15,
- DA830_GPIO2_2,
- DA830_GPIO2_3,
- DA830_GPIO2_4,
- DA830_GPIO2_5,
- DA830_GPIO2_6,
- DA830_GPIO2_7,
- DA830_GPIO2_8,
- DA830_GPIO2_9,
- DA830_EMA_WAIT_0,
- DA830_NUHPI_HRDY,
- DA830_GPIO2_10,
-};
-
-enum davinci_da850_index {
- /* UART0 function */
- DA850_NUART0_CTS,
- DA850_NUART0_RTS,
- DA850_UART0_RXD,
- DA850_UART0_TXD,
-
- /* UART1 function */
- DA850_NUART1_CTS,
- DA850_NUART1_RTS,
- DA850_UART1_RXD,
- DA850_UART1_TXD,
-
- /* UART2 function */
- DA850_NUART2_CTS,
- DA850_NUART2_RTS,
- DA850_UART2_RXD,
- DA850_UART2_TXD,
-
- /* I2C1 function */
- DA850_I2C1_SCL,
- DA850_I2C1_SDA,
-
- /* I2C0 function */
- DA850_I2C0_SDA,
- DA850_I2C0_SCL,
-
- /* EMAC function */
- DA850_MII_TXEN,
- DA850_MII_TXCLK,
- DA850_MII_COL,
- DA850_MII_TXD_3,
- DA850_MII_TXD_2,
- DA850_MII_TXD_1,
- DA850_MII_TXD_0,
- DA850_MII_RXER,
- DA850_MII_CRS,
- DA850_MII_RXCLK,
- DA850_MII_RXDV,
- DA850_MII_RXD_3,
- DA850_MII_RXD_2,
- DA850_MII_RXD_1,
- DA850_MII_RXD_0,
- DA850_MDIO_CLK,
- DA850_MDIO_D,
- DA850_RMII_TXD_0,
- DA850_RMII_TXD_1,
- DA850_RMII_TXEN,
- DA850_RMII_CRS_DV,
- DA850_RMII_RXD_0,
- DA850_RMII_RXD_1,
- DA850_RMII_RXER,
- DA850_RMII_MHZ_50_CLK,
-
- /* McASP function */
- DA850_ACLKR,
- DA850_ACLKX,
- DA850_AFSR,
- DA850_AFSX,
- DA850_AHCLKR,
- DA850_AHCLKX,
- DA850_AMUTE,
- DA850_AXR_15,
- DA850_AXR_14,
- DA850_AXR_13,
- DA850_AXR_12,
- DA850_AXR_11,
- DA850_AXR_10,
- DA850_AXR_9,
- DA850_AXR_8,
- DA850_AXR_7,
- DA850_AXR_6,
- DA850_AXR_5,
- DA850_AXR_4,
- DA850_AXR_3,
- DA850_AXR_2,
- DA850_AXR_1,
- DA850_AXR_0,
-
- /* LCD function */
- DA850_LCD_D_7,
- DA850_LCD_D_6,
- DA850_LCD_D_5,
- DA850_LCD_D_4,
- DA850_LCD_D_3,
- DA850_LCD_D_2,
- DA850_LCD_D_1,
- DA850_LCD_D_0,
- DA850_LCD_D_15,
- DA850_LCD_D_14,
- DA850_LCD_D_13,
- DA850_LCD_D_12,
- DA850_LCD_D_11,
- DA850_LCD_D_10,
- DA850_LCD_D_9,
- DA850_LCD_D_8,
- DA850_LCD_PCLK,
- DA850_LCD_HSYNC,
- DA850_LCD_VSYNC,
- DA850_NLCD_AC_ENB_CS,
-
- /* MMC/SD0 function */
- DA850_MMCSD0_DAT_0,
- DA850_MMCSD0_DAT_1,
- DA850_MMCSD0_DAT_2,
- DA850_MMCSD0_DAT_3,
- DA850_MMCSD0_CLK,
- DA850_MMCSD0_CMD,
-
- /* MMC/SD1 function */
- DA850_MMCSD1_DAT_0,
- DA850_MMCSD1_DAT_1,
- DA850_MMCSD1_DAT_2,
- DA850_MMCSD1_DAT_3,
- DA850_MMCSD1_CLK,
- DA850_MMCSD1_CMD,
-
- /* EMIF2.5/EMIFA function */
- DA850_EMA_D_7,
- DA850_EMA_D_6,
- DA850_EMA_D_5,
- DA850_EMA_D_4,
- DA850_EMA_D_3,
- DA850_EMA_D_2,
- DA850_EMA_D_1,
- DA850_EMA_D_0,
- DA850_EMA_A_1,
- DA850_EMA_A_2,
- DA850_NEMA_CS_3,
- DA850_NEMA_CS_4,
- DA850_NEMA_WE,
- DA850_NEMA_OE,
- DA850_EMA_D_15,
- DA850_EMA_D_14,
- DA850_EMA_D_13,
- DA850_EMA_D_12,
- DA850_EMA_D_11,
- DA850_EMA_D_10,
- DA850_EMA_D_9,
- DA850_EMA_D_8,
- DA850_EMA_A_0,
- DA850_EMA_A_3,
- DA850_EMA_A_4,
- DA850_EMA_A_5,
- DA850_EMA_A_6,
- DA850_EMA_A_7,
- DA850_EMA_A_8,
- DA850_EMA_A_9,
- DA850_EMA_A_10,
- DA850_EMA_A_11,
- DA850_EMA_A_12,
- DA850_EMA_A_13,
- DA850_EMA_A_14,
- DA850_EMA_A_15,
- DA850_EMA_A_16,
- DA850_EMA_A_17,
- DA850_EMA_A_18,
- DA850_EMA_A_19,
- DA850_EMA_A_20,
- DA850_EMA_A_21,
- DA850_EMA_A_22,
- DA850_EMA_A_23,
- DA850_EMA_BA_1,
- DA850_EMA_CLK,
- DA850_EMA_WAIT_1,
- DA850_NEMA_CS_2,
-
- /* GPIO function */
- DA850_GPIO2_4,
- DA850_GPIO2_6,
- DA850_GPIO2_8,
- DA850_GPIO2_15,
- DA850_GPIO3_12,
- DA850_GPIO3_13,
- DA850_GPIO4_0,
- DA850_GPIO4_1,
- DA850_GPIO6_9,
- DA850_GPIO6_10,
- DA850_GPIO6_13,
- DA850_RTC_ALARM,
-
- /* VPIF Capture */
- DA850_VPIF_DIN0,
- DA850_VPIF_DIN1,
- DA850_VPIF_DIN2,
- DA850_VPIF_DIN3,
- DA850_VPIF_DIN4,
- DA850_VPIF_DIN5,
- DA850_VPIF_DIN6,
- DA850_VPIF_DIN7,
- DA850_VPIF_DIN8,
- DA850_VPIF_DIN9,
- DA850_VPIF_DIN10,
- DA850_VPIF_DIN11,
- DA850_VPIF_DIN12,
- DA850_VPIF_DIN13,
- DA850_VPIF_DIN14,
- DA850_VPIF_DIN15,
- DA850_VPIF_CLKIN0,
- DA850_VPIF_CLKIN1,
- DA850_VPIF_CLKIN2,
- DA850_VPIF_CLKIN3,
-
- /* VPIF Display */
- DA850_VPIF_DOUT0,
- DA850_VPIF_DOUT1,
- DA850_VPIF_DOUT2,
- DA850_VPIF_DOUT3,
- DA850_VPIF_DOUT4,
- DA850_VPIF_DOUT5,
- DA850_VPIF_DOUT6,
- DA850_VPIF_DOUT7,
- DA850_VPIF_DOUT8,
- DA850_VPIF_DOUT9,
- DA850_VPIF_DOUT10,
- DA850_VPIF_DOUT11,
- DA850_VPIF_DOUT12,
- DA850_VPIF_DOUT13,
- DA850_VPIF_DOUT14,
- DA850_VPIF_DOUT15,
- DA850_VPIF_CLKO2,
- DA850_VPIF_CLKO3,
-};
-
-#define PINMUX(x) (4 * (x))
-
-#ifdef CONFIG_DAVINCI_MUX
-/* setup pin muxing */
-extern int davinci_cfg_reg(unsigned long reg_cfg);
-extern int davinci_cfg_reg_list(const short pins[]);
-#else
-/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
-static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
-static inline int davinci_cfg_reg_list(const short pins[])
-{
- return 0;
-}
-#endif
-
-#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/include/mach/pm.h
deleted file mode 100644
index 37b19bf35a85..000000000000
--- a/arch/arm/mach-davinci/include/mach/pm.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * TI DaVinci platform support for power management.
- *
- * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef _MACH_DAVINCI_PM_H
-#define _MACH_DAVINCI_PM_H
-
-/*
- * Caution: Assembly code in sleep.S makes assumtion on the order
- * of the members of this structure.
- */
-struct davinci_pm_config {
- void __iomem *ddr2_ctlr_base;
- void __iomem *ddrpsc_reg_base;
- int ddrpsc_num;
- void __iomem *ddrpll_reg_base;
- void __iomem *deepsleep_reg;
- void __iomem *cpupll_reg_base;
- /*
- * Note on SLEEPCOUNT:
- * The SLEEPCOUNT feature is mainly intended for cases in which
- * the internal oscillator is used. The internal oscillator is
- * fully disabled in deep sleep mode. When you exist deep sleep
- * mode, the oscillator will be turned on and will generate very
- * small oscillations which will not be detected by the deep sleep
- * counter. Eventually those oscillations will grow to an amplitude
- * large enough to start incrementing the deep sleep counter.
- * In this case recommendation from hardware engineers is that the
- * SLEEPCOUNT be set to 4096. This means that 4096 valid clock cycles
- * must be detected before the clock is passed to the rest of the
- * system.
- * In the case that the internal oscillator is not used and the
- * clock is generated externally, the SLEEPCOUNT value can be very
- * small since the clock input is assumed to be stable before SoC
- * is taken out of deepsleep mode. A value of 128 would be more than
- * adequate.
- */
- int sleepcount;
-};
-
-extern unsigned int davinci_cpu_suspend_sz;
-extern void davinci_cpu_suspend(struct davinci_pm_config *);
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
deleted file mode 100644
index d4b4aa87964f..000000000000
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * DaVinci serial device definitions
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-#include <asm/memory.h>
-
-#include <mach/hardware.h>
-
-#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
-#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
-#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
-
-#define DA8XX_UART0_BASE (IO_PHYS + 0x042000)
-#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
-#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
-
-/* DaVinci UART register offsets */
-#define UART_DAVINCI_PWREMU 0x0c
-#define UART_DM646X_SCR 0x10
-#define UART_DM646X_SCR_TX_WATERMARK 0x08
-
-#ifndef __ASSEMBLY__
-#include <linux/platform_device.h>
-
-extern int davinci_serial_init(struct platform_device *);
-#endif
-
-#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
deleted file mode 100644
index 53b456a5bbe0..000000000000
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * arch/arm/plat-omap/include/mach/uncompress.h
- *
- * Original copyrights follow.
- *
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-
-#include <asm/mach-types.h>
-
-#include <mach/serial.h>
-
-#define IOMEM(x) ((void __force __iomem *)(x))
-
-u32 *uart;
-
-/* PORT_16C550A, in polled non-fifo mode */
-static inline void putc(char c)
-{
- if (!uart)
- return;
-
- while (!(uart[UART_LSR] & UART_LSR_THRE))
- barrier();
- uart[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
- if (!uart)
- return;
-
- while (!(uart[UART_LSR] & UART_LSR_THRE))
- barrier();
-}
-
-static inline void set_uart_info(u32 phys)
-{
- uart = (u32 *)phys;
-}
-
-#define _DEBUG_LL_ENTRY(machine, phys) \
- { \
- if (machine_is_##machine()) { \
- set_uart_info(phys); \
- break; \
- } \
- }
-
-#define DEBUG_LL_DAVINCI(machine, port) \
- _DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE)
-
-#define DEBUG_LL_DA8XX(machine, port) \
- _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
-
-static inline void __arch_decomp_setup(unsigned long arch_id)
-{
- /*
- * Initialize the port based on the machine ID from the bootloader.
- * Note that we're using macros here instead of switch statement
- * as machine_is functions are optimized out for the boards that
- * are not selected.
- */
- do {
- /* Davinci boards */
- DEBUG_LL_DAVINCI(davinci_evm, 0);
- DEBUG_LL_DAVINCI(sffsdr, 0);
- DEBUG_LL_DAVINCI(neuros_osd2, 0);
- DEBUG_LL_DAVINCI(davinci_dm355_evm, 0);
- DEBUG_LL_DAVINCI(dm355_leopard, 0);
- DEBUG_LL_DAVINCI(davinci_dm6467_evm, 0);
- DEBUG_LL_DAVINCI(davinci_dm365_evm, 0);
-
- /* DA8xx boards */
- DEBUG_LL_DA8XX(davinci_da830_evm, 2);
- DEBUG_LL_DA8XX(davinci_da850_evm, 2);
- DEBUG_LL_DA8XX(mityomapl138, 1);
- DEBUG_LL_DA8XX(omapl138_hawkboard, 2);
- } while (0);
-}
-
-#define arch_decomp_setup() __arch_decomp_setup(arch_id)
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