diff options
Diffstat (limited to 'arch/arm/mach-dove/include/mach')
| -rw-r--r-- | arch/arm/mach-dove/include/mach/bridge-regs.h | 57 | ||||
| -rw-r--r-- | arch/arm/mach-dove/include/mach/dove.h | 192 | ||||
| -rw-r--r-- | arch/arm/mach-dove/include/mach/hardware.h | 19 | ||||
| -rw-r--r-- | arch/arm/mach-dove/include/mach/irqs.h | 96 | ||||
| -rw-r--r-- | arch/arm/mach-dove/include/mach/pm.h | 64 | ||||
| -rw-r--r-- | arch/arm/mach-dove/include/mach/uncompress.h | 8 |
6 files changed, 3 insertions, 433 deletions
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h deleted file mode 100644 index f4a5b34489b7..000000000000 --- a/arch/arm/mach-dove/include/mach/bridge-regs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/bridge-regs.h - * - * Mbus-L to Mbus Bridge Registers - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_BRIDGE_REGS_H -#define __ASM_ARCH_BRIDGE_REGS_H - -#include <mach/dove.h> - -#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) - -#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) -#define CPU_CTRL_PCIE0_LINK 0x00000001 -#define CPU_RESET 0x00000002 -#define CPU_CTRL_PCIE1_LINK 0x00000008 - -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) -#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) -#define SOFT_RESET_OUT_EN 0x00000004 - -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) -#define SOFT_RESET 0x00000001 - -#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) -#define BRIDGE_INT_TIMER1_CLR (~0x0004) - -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) -#define IRQ_CAUSE_LOW_OFF 0x0000 -#define IRQ_MASK_LOW_OFF 0x0004 -#define FIQ_MASK_LOW_OFF 0x0008 -#define ENDPOINT_MASK_LOW_OFF 0x000c -#define IRQ_CAUSE_HIGH_OFF 0x0010 -#define IRQ_MASK_HIGH_OFF 0x0014 -#define FIQ_MASK_HIGH_OFF 0x0018 -#define ENDPOINT_MASK_HIGH_OFF 0x001c -#define PCIE_INTERRUPT_MASK_OFF 0x0020 - -#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) -#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) -#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) -#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) -#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) -#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) -#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) - -#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) - -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) - -#endif diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h deleted file mode 100644 index 00f45458b3ec..000000000000 --- a/arch/arm/mach-dove/include/mach/dove.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/dove.h - * - * Generic definitions for Marvell Dove 88AP510 SoC - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_DOVE_H -#define __ASM_ARCH_DOVE_H - -#include <mach/irqs.h> - -/* - * Marvell Dove address maps. - * - * phys virt size - * c8000000 fdb00000 1M Cryptographic SRAM - * e0000000 @runtime 128M PCIe-0 Memory space - * e8000000 @runtime 128M PCIe-1 Memory space - * f1000000 fde00000 8M on-chip south-bridge registers - * f1800000 fe600000 8M on-chip north-bridge registers - * f2000000 fee00000 1M PCIe-0 I/O space - * f2100000 fef00000 1M PCIe-1 I/O space - */ - -#define DOVE_CESA_PHYS_BASE 0xc8000000 -#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) -#define DOVE_CESA_SIZE SZ_1M - -#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 -#define DOVE_PCIE0_MEM_SIZE SZ_128M - -#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000 -#define DOVE_PCIE1_MEM_SIZE SZ_128M - -#define DOVE_BOOTROM_PHYS_BASE 0xf8000000 -#define DOVE_BOOTROM_SIZE SZ_128M - -#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 -#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) -#define DOVE_SCRATCHPAD_SIZE SZ_1M - -#define DOVE_SB_REGS_PHYS_BASE 0xf1000000 -#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) -#define DOVE_SB_REGS_SIZE SZ_8M - -#define DOVE_NB_REGS_PHYS_BASE 0xf1800000 -#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000) -#define DOVE_NB_REGS_SIZE SZ_8M - -#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 -#define DOVE_PCIE0_IO_BUS_BASE 0x00000000 -#define DOVE_PCIE0_IO_SIZE SZ_64K - -#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 -#define DOVE_PCIE1_IO_BUS_BASE 0x00010000 -#define DOVE_PCIE1_IO_SIZE SZ_64K - -/* - * Dove Core Registers Map - */ - -/* SPI, I2C, UART */ -#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000) -#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000) -#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000) -#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100) -#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100) -#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200) -#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200) -#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300) -#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300) -#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600) -#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600) - -/* North-South Bridge */ -#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) -#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) -#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) -#define BRIDGE_WINS_SZ (0x80) - -/* Cryptographic Engine */ -#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) - -/* PCIe 0 */ -#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000) - -/* USB */ -#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000) -#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000) - -/* XOR 0 Engine */ -#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800) -#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800) -#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00) -#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00) - -/* XOR 1 Engine */ -#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900) -#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900) -#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00) -#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00) - -/* Gigabit Ethernet */ -#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000) - -/* PCIe 1 */ -#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000) - -/* CAFE */ -#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000) -#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000) -#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000) -#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000) - -/* SATA */ -#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000) - -/* I2S/SPDIF */ -#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000) -#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000) - -/* NAND Flash Controller */ -#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000) - -/* MPP, GPIO, Reset Sampling */ -#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) -#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) -#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014) -#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018) -#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) -#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420) -#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400) -#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) -#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) -#define DOVE_NAND_GPIO_EN (1 << 0) -#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) -#define DOVE_SPI_GPIO_SEL (1 << 5) -#define DOVE_UART1_GPIO_SEL (1 << 4) -#define DOVE_AU1_GPIO_SEL (1 << 3) -#define DOVE_CAM_GPIO_SEL (1 << 2) -#define DOVE_SD1_GPIO_SEL (1 << 1) -#define DOVE_SD0_GPIO_SEL (1 << 0) - -/* Power Management */ -#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000) -#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) - -/* Real Time Clock */ -#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500) - -/* AC97 */ -#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000) -#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000) - -/* Peripheral DMA */ -#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000) -#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000) - -#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) -#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) -#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) -#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) -#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) -#define DOVE_TWSI_OPTION3_GPIO (1 << 22) -#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000) -#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) -#define DOVE_SSP_ON_AU1 (1 << 0) -#define DOVE_SSP_CLOCK_ENABLE (1 << 1) -#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) -/* Memory Controller */ -#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000) -#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100) -#define DOVE_MC_WINS_SZ (0x8) -#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) - -/* LCD Controller */ -#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) -#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000) -#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) -#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000) - -/* Graphic Engine */ -#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000) - -/* Video Engine */ -#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000) - -#endif diff --git a/arch/arm/mach-dove/include/mach/hardware.h b/arch/arm/mach-dove/include/mach/hardware.h deleted file mode 100644 index f1368b9a8ece..000000000000 --- a/arch/arm/mach-dove/include/mach/hardware.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/hardware.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "dove.h" - -/* Macros below are required for compatibility with PXA AC'97 driver. */ -#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ - DOVE_SB_REGS_VIRT_BASE))) -#define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \ - DOVE_SB_REGS_PHYS_BASE) -#endif diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h deleted file mode 100644 index 8ff0fa8b4fcd..000000000000 --- a/arch/arm/mach-dove/include/mach/irqs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/irqs.h - * - * IRQ definitions for Marvell Dove 88AP510 SoC - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* - * Dove Low Interrupt Controller - */ -#define IRQ_DOVE_BRIDGE (1 + 0) -#define IRQ_DOVE_H2C (1 + 1) -#define IRQ_DOVE_C2H (1 + 2) -#define IRQ_DOVE_NAND (1 + 3) -#define IRQ_DOVE_PDMA (1 + 4) -#define IRQ_DOVE_SPI1 (1 + 5) -#define IRQ_DOVE_SPI0 (1 + 6) -#define IRQ_DOVE_UART_0 (1 + 7) -#define IRQ_DOVE_UART_1 (1 + 8) -#define IRQ_DOVE_UART_2 (1 + 9) -#define IRQ_DOVE_UART_3 (1 + 10) -#define IRQ_DOVE_I2C (1 + 11) -#define IRQ_DOVE_GPIO_0_7 (1 + 12) -#define IRQ_DOVE_GPIO_8_15 (1 + 13) -#define IRQ_DOVE_GPIO_16_23 (1 + 14) -#define IRQ_DOVE_PCIE0_ERR (1 + 15) -#define IRQ_DOVE_PCIE0 (1 + 16) -#define IRQ_DOVE_PCIE1_ERR (1 + 17) -#define IRQ_DOVE_PCIE1 (1 + 18) -#define IRQ_DOVE_I2S0 (1 + 19) -#define IRQ_DOVE_I2S0_ERR (1 + 20) -#define IRQ_DOVE_I2S1 (1 + 21) -#define IRQ_DOVE_I2S1_ERR (1 + 22) -#define IRQ_DOVE_USB_ERR (1 + 23) -#define IRQ_DOVE_USB0 (1 + 24) -#define IRQ_DOVE_USB1 (1 + 25) -#define IRQ_DOVE_GE00_RX (1 + 26) -#define IRQ_DOVE_GE00_TX (1 + 27) -#define IRQ_DOVE_GE00_MISC (1 + 28) -#define IRQ_DOVE_GE00_SUM (1 + 29) -#define IRQ_DOVE_GE00_ERR (1 + 30) -#define IRQ_DOVE_CRYPTO (1 + 31) - -/* - * Dove High Interrupt Controller - */ -#define IRQ_DOVE_AC97 (1 + 32) -#define IRQ_DOVE_PMU (1 + 33) -#define IRQ_DOVE_CAM (1 + 34) -#define IRQ_DOVE_SDIO0 (1 + 35) -#define IRQ_DOVE_SDIO1 (1 + 36) -#define IRQ_DOVE_SDIO0_WAKEUP (1 + 37) -#define IRQ_DOVE_SDIO1_WAKEUP (1 + 38) -#define IRQ_DOVE_XOR_00 (1 + 39) -#define IRQ_DOVE_XOR_01 (1 + 40) -#define IRQ_DOVE_XOR0_ERR (1 + 41) -#define IRQ_DOVE_XOR_10 (1 + 42) -#define IRQ_DOVE_XOR_11 (1 + 43) -#define IRQ_DOVE_XOR1_ERR (1 + 44) -#define IRQ_DOVE_LCD_DCON (1 + 45) -#define IRQ_DOVE_LCD1 (1 + 46) -#define IRQ_DOVE_LCD0 (1 + 47) -#define IRQ_DOVE_GPU (1 + 48) -#define IRQ_DOVE_PERFORM_MNTR (1 + 49) -#define IRQ_DOVE_VPRO_DMA1 (1 + 51) -#define IRQ_DOVE_SSP_TIMER (1 + 54) -#define IRQ_DOVE_SSP (1 + 55) -#define IRQ_DOVE_MC_L2_ERR (1 + 56) -#define IRQ_DOVE_CRYPTO_ERR (1 + 59) -#define IRQ_DOVE_GPIO_24_31 (1 + 60) -#define IRQ_DOVE_HIGH_GPIO (1 + 61) -#define IRQ_DOVE_SATA (1 + 62) - -/* - * DOVE General Purpose Pins - */ -#define IRQ_DOVE_GPIO_START 65 -#define NR_GPIO_IRQS 64 - -/* - * PMU interrupts - */ -#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS) -#define NR_PMU_IRQS 7 -#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5) - -#define DOVE_NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS) - - -#endif diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h deleted file mode 100644 index d22b9b174007..000000000000 --- a/arch/arm/mach-dove/include/mach/pm.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/pm.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_PM_H -#define __ASM_ARCH_PM_H - -#include <asm/errno.h> -#include <mach/irqs.h> - -#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38) -#define CLOCK_GATING_BIT_USB0 0 -#define CLOCK_GATING_BIT_USB1 1 -#define CLOCK_GATING_BIT_GBE 2 -#define CLOCK_GATING_BIT_SATA 3 -#define CLOCK_GATING_BIT_PCIE0 4 -#define CLOCK_GATING_BIT_PCIE1 5 -#define CLOCK_GATING_BIT_SDIO0 8 -#define CLOCK_GATING_BIT_SDIO1 9 -#define CLOCK_GATING_BIT_NAND 10 -#define CLOCK_GATING_BIT_CAMERA 11 -#define CLOCK_GATING_BIT_I2S0 12 -#define CLOCK_GATING_BIT_I2S1 13 -#define CLOCK_GATING_BIT_CRYPTO 15 -#define CLOCK_GATING_BIT_AC97 21 -#define CLOCK_GATING_BIT_PDMA 22 -#define CLOCK_GATING_BIT_XOR0 23 -#define CLOCK_GATING_BIT_XOR1 24 -#define CLOCK_GATING_BIT_GIGA_PHY 30 -#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0) -#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1) -#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE) -#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA) -#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0) -#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1) -#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0) -#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1) -#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND) -#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA) -#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0) -#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1) -#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO) -#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97) -#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA) -#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0) -#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1) -#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY) - -#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) - -#define PMU_SW_RST_VIDEO_MASK BIT(16) -#define PMU_SW_RST_GPU_MASK BIT(18) - -#define PMU_PWR_GPU_PWR_DWN_MASK BIT(2) -#define PMU_PWR_VPU_PWR_DWN_MASK BIT(3) - -#define PMU_ISO_VIDEO_MASK BIT(0) -#define PMU_ISO_GPU_MASK BIT(1) - -#endif diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h index 5c8ae9b9d39a..7a4bd8838036 100644 --- a/arch/arm/mach-dove/include/mach/uncompress.h +++ b/arch/arm/mach-dove/include/mach/uncompress.h @@ -1,15 +1,13 @@ /* - * arch/arm/mach-dove/include/mach/uncompress.h - * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <mach/dove.h> +#define UART0_PHYS_BASE (0xf1000000 + 0x12000) -#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0)) -#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14)) +#define UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) +#define UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) #define LSR_THRE 0x20 |