diff options
Diffstat (limited to '')
23 files changed, 714 insertions, 1062 deletions
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index f2db5fd38145..2c40996a444b 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -1,4 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_EP93XX + bool "EP93xx-based" + depends on ATAGS + depends on ARCH_MULTI_V4T + depends on CPU_LITTLE_ENDIAN + select ARCH_SPARSEMEM_ENABLE + select ARM_AMBA + select ARM_VIC + select CLKSRC_MMIO + select CPU_ARM920T + select GPIOLIB + help + This enables support for the Cirrus EP93xx series of CPUs. + if ARCH_EP93XX menu "Cirrus EP93xx Implementation Options" @@ -9,15 +23,11 @@ config EP93XX_SOC_COMMON select SOC_BUS select LEDS_GPIO_REGISTER -config CRUNCH - bool "Support for MaverickCrunch" - help - Enable kernel support for MaverickCrunch. - comment "EP93xx Platforms" config MACH_ADSSPHERE bool "Support ADS Sphere" + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the ADS Sphere board. @@ -90,6 +100,7 @@ config MACH_EDB9315A config MACH_GESBC9312 bool "Support Glomation GESBC-9312-sx" + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Glomation GESBC-9312-sx board. @@ -100,6 +111,7 @@ config MACH_MICRO9 config MACH_MICRO9H bool "Support Contec Micro9-High" select MACH_MICRO9 + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Contec Micro9-High board. @@ -107,6 +119,7 @@ config MACH_MICRO9H config MACH_MICRO9M bool "Support Contec Micro9-Mid" select MACH_MICRO9 + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Contec Micro9-Mid board. @@ -114,6 +127,7 @@ config MACH_MICRO9M config MACH_MICRO9L bool "Support Contec Micro9-Lite" select MACH_MICRO9 + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Contec Micro9-Lite board. @@ -121,18 +135,21 @@ config MACH_MICRO9L config MACH_MICRO9S bool "Support Contec Micro9-Slim" select MACH_MICRO9 + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Contec Micro9-Slim board. config MACH_SIM_ONE bool "Support Simplemachines Sim.One board" + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Simplemachines Sim.One board. config MACH_SNAPPER_CL15 bool "Support Bluewater Systems Snapper CL15 Module" + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Bluewater Systems Snapper CL15 Module. diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index 86768495f61d..cfad517fac46 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile @@ -6,9 +6,6 @@ obj-y := core.o clock.o timer-ep93xx.o obj-$(CONFIG_EP93XX_DMA) += dma.o -obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o -AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 - obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o diff --git a/arch/arm/mach-ep93xx/Makefile.boot b/arch/arm/mach-ep93xx/Makefile.boot deleted file mode 100644 index 4c0a039a5027..000000000000 --- a/arch/arm/mach-ep93xx/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# Empty file waiting for deletion once Makefile.boot isn't needed any more. diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c index 57cfd8ebe04f..0c48d3c5b8e7 100644 --- a/arch/arm/mach-ep93xx/adssphere.c +++ b/arch/arm/mach-ep93xx/adssphere.c @@ -32,10 +32,10 @@ static void __init adssphere_init_machine(void) MACHINE_START(ADSSPHERE, "ADS Sphere board") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = adssphere_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 2810eb5b2aca..85a496ddc619 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c @@ -16,6 +16,7 @@ #include <linux/io.h> #include <linux/spinlock.h> #include <linux/clkdev.h> +#include <linux/clk-provider.h> #include <linux/soc/cirrus/ep93xx.h> #include "hardware.h" @@ -24,348 +25,196 @@ #include "soc.h" -struct clk { - struct clk *parent; - unsigned long rate; - int users; - int sw_locked; - void __iomem *enable_reg; - u32 enable_mask; - - unsigned long (*get_rate)(struct clk *clk); - int (*set_rate)(struct clk *clk, unsigned long rate); -}; - - -static unsigned long get_uart_rate(struct clk *clk); - -static int set_keytchclk_rate(struct clk *clk, unsigned long rate); -static int set_div_rate(struct clk *clk, unsigned long rate); -static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate); -static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate); +static DEFINE_SPINLOCK(clk_lock); -static struct clk clk_xtali = { - .rate = EP93XX_EXT_CLK_RATE, -}; -static struct clk clk_uart1 = { - .parent = &clk_xtali, - .sw_locked = 1, - .enable_reg = EP93XX_SYSCON_DEVCFG, - .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN, - .get_rate = get_uart_rate, -}; -static struct clk clk_uart2 = { - .parent = &clk_xtali, - .sw_locked = 1, - .enable_reg = EP93XX_SYSCON_DEVCFG, - .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN, - .get_rate = get_uart_rate, -}; -static struct clk clk_uart3 = { - .parent = &clk_xtali, - .sw_locked = 1, - .enable_reg = EP93XX_SYSCON_DEVCFG, - .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN, - .get_rate = get_uart_rate, -}; -static struct clk clk_pll1 = { - .parent = &clk_xtali, -}; -static struct clk clk_f = { - .parent = &clk_pll1, -}; -static struct clk clk_h = { - .parent = &clk_pll1, -}; -static struct clk clk_p = { - .parent = &clk_pll1, -}; -static struct clk clk_pll2 = { - .parent = &clk_xtali, -}; -static struct clk clk_usb_host = { - .parent = &clk_pll2, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, -}; -static struct clk clk_keypad = { - .parent = &clk_xtali, - .sw_locked = 1, - .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV, - .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN, - .set_rate = set_keytchclk_rate, -}; -static struct clk clk_adc = { - .parent = &clk_xtali, - .sw_locked = 1, - .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV, - .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, - .set_rate = set_keytchclk_rate, -}; -static struct clk clk_spi = { - .parent = &clk_xtali, - .rate = EP93XX_EXT_CLK_RATE, -}; -static struct clk clk_pwm = { - .parent = &clk_xtali, - .rate = EP93XX_EXT_CLK_RATE, -}; +static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; +static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; +static char pclk_divisors[] = { 1, 2, 4, 8 }; -static struct clk clk_video = { - .sw_locked = 1, - .enable_reg = EP93XX_SYSCON_VIDCLKDIV, - .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE, - .set_rate = set_div_rate, -}; +static char adc_divisors[] = { 16, 4 }; +static char sclk_divisors[] = { 2, 4 }; +static char lrclk_divisors[] = { 32, 64, 128 }; -static struct clk clk_i2s_mclk = { - .sw_locked = 1, - .enable_reg = EP93XX_SYSCON_I2SCLKDIV, - .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE, - .set_rate = set_div_rate, +static const char * const mux_parents[] = { + "xtali", + "pll1", + "pll2" }; -static struct clk clk_i2s_sclk = { - .sw_locked = 1, - .parent = &clk_i2s_mclk, - .enable_reg = EP93XX_SYSCON_I2SCLKDIV, - .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA, - .set_rate = set_i2s_sclk_rate, -}; +/* + * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS + */ +static unsigned long calc_pll_rate(unsigned long long rate, u32 config_word) +{ + int i; -static struct clk clk_i2s_lrclk = { - .sw_locked = 1, - .parent = &clk_i2s_sclk, - .enable_reg = EP93XX_SYSCON_I2SCLKDIV, - .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA, - .set_rate = set_i2s_lrclk_rate, -}; + rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ + rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ + do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ + for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */ + rate >>= 1; -/* DMA Clocks */ -static struct clk clk_m2p0 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0, -}; -static struct clk clk_m2p1 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1, -}; -static struct clk clk_m2p2 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2, -}; -static struct clk clk_m2p3 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3, -}; -static struct clk clk_m2p4 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4, -}; -static struct clk clk_m2p5 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5, -}; -static struct clk clk_m2p6 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6, -}; -static struct clk clk_m2p7 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7, -}; -static struct clk clk_m2p8 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8, -}; -static struct clk clk_m2p9 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9, -}; -static struct clk clk_m2m0 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0, -}; -static struct clk clk_m2m1 = { - .parent = &clk_h, - .enable_reg = EP93XX_SYSCON_PWRCNT, - .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1, -}; + return (unsigned long)rate; +} -#define INIT_CK(dev,con,ck) \ - { .dev_id = dev, .con_id = con, .clk = ck } - -static struct clk_lookup clocks[] = { - INIT_CK(NULL, "xtali", &clk_xtali), - INIT_CK("apb:uart1", NULL, &clk_uart1), - INIT_CK("apb:uart2", NULL, &clk_uart2), - INIT_CK("apb:uart3", NULL, &clk_uart3), - INIT_CK(NULL, "pll1", &clk_pll1), - INIT_CK(NULL, "fclk", &clk_f), - INIT_CK(NULL, "hclk", &clk_h), - INIT_CK(NULL, "apb_pclk", &clk_p), - INIT_CK(NULL, "pll2", &clk_pll2), - INIT_CK("ohci-platform", NULL, &clk_usb_host), - INIT_CK("ep93xx-keypad", NULL, &clk_keypad), - INIT_CK("ep93xx-adc", NULL, &clk_adc), - INIT_CK("ep93xx-fb", NULL, &clk_video), - INIT_CK("ep93xx-spi.0", NULL, &clk_spi), - INIT_CK("ep93xx-i2s", "mclk", &clk_i2s_mclk), - INIT_CK("ep93xx-i2s", "sclk", &clk_i2s_sclk), - INIT_CK("ep93xx-i2s", "lrclk", &clk_i2s_lrclk), - INIT_CK(NULL, "pwm_clk", &clk_pwm), - INIT_CK(NULL, "m2p0", &clk_m2p0), - INIT_CK(NULL, "m2p1", &clk_m2p1), - INIT_CK(NULL, "m2p2", &clk_m2p2), - INIT_CK(NULL, "m2p3", &clk_m2p3), - INIT_CK(NULL, "m2p4", &clk_m2p4), - INIT_CK(NULL, "m2p5", &clk_m2p5), - INIT_CK(NULL, "m2p6", &clk_m2p6), - INIT_CK(NULL, "m2p7", &clk_m2p7), - INIT_CK(NULL, "m2p8", &clk_m2p8), - INIT_CK(NULL, "m2p9", &clk_m2p9), - INIT_CK(NULL, "m2m0", &clk_m2m0), - INIT_CK(NULL, "m2m1", &clk_m2m1), +struct clk_psc { + struct clk_hw hw; + void __iomem *reg; + u8 bit_idx; + u32 mask; + u8 shift; + u8 width; + char *div; + u8 num_div; + spinlock_t *lock; }; -static DEFINE_SPINLOCK(clk_lock); +#define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw) -static void __clk_enable(struct clk *clk) +static int ep93xx_clk_is_enabled(struct clk_hw *hw) { - if (!clk->users++) { - if (clk->parent) - __clk_enable(clk->parent); - - if (clk->enable_reg) { - u32 v; - - v = __raw_readl(clk->enable_reg); - v |= clk->enable_mask; - if (clk->sw_locked) - ep93xx_syscon_swlocked_write(v, clk->enable_reg); - else - __raw_writel(v, clk->enable_reg); - } - } + struct clk_psc *psc = to_clk_psc(hw); + u32 val = readl(psc->reg); + + return (val & BIT(psc->bit_idx)) ? 1 : 0; } -int clk_enable(struct clk *clk) +static int ep93xx_clk_enable(struct clk_hw *hw) { - unsigned long flags; + struct clk_psc *psc = to_clk_psc(hw); + unsigned long flags = 0; + u32 val; - if (!clk) - return -EINVAL; + if (psc->lock) + spin_lock_irqsave(psc->lock, flags); - spin_lock_irqsave(&clk_lock, flags); - __clk_enable(clk); - spin_unlock_irqrestore(&clk_lock, flags); + val = __raw_readl(psc->reg); + val |= BIT(psc->bit_idx); + + ep93xx_syscon_swlocked_write(val, psc->reg); + + if (psc->lock) + spin_unlock_irqrestore(psc->lock, flags); return 0; } -EXPORT_SYMBOL(clk_enable); -static void __clk_disable(struct clk *clk) +static void ep93xx_clk_disable(struct clk_hw *hw) { - if (!--clk->users) { - if (clk->enable_reg) { - u32 v; - - v = __raw_readl(clk->enable_reg); - v &= ~clk->enable_mask; - if (clk->sw_locked) - ep93xx_syscon_swlocked_write(v, clk->enable_reg); - else - __raw_writel(v, clk->enable_reg); - } + struct clk_psc *psc = to_clk_psc(hw); + unsigned long flags = 0; + u32 val; - if (clk->parent) - __clk_disable(clk->parent); - } -} + if (psc->lock) + spin_lock_irqsave(psc->lock, flags); -void clk_disable(struct clk *clk) -{ - unsigned long flags; + val = __raw_readl(psc->reg); + val &= ~BIT(psc->bit_idx); - if (!clk) - return; + ep93xx_syscon_swlocked_write(val, psc->reg); - spin_lock_irqsave(&clk_lock, flags); - __clk_disable(clk); - spin_unlock_irqrestore(&clk_lock, flags); + if (psc->lock) + spin_unlock_irqrestore(psc->lock, flags); } -EXPORT_SYMBOL(clk_disable); -static unsigned long get_uart_rate(struct clk *clk) +static const struct clk_ops clk_ep93xx_gate_ops = { + .enable = ep93xx_clk_enable, + .disable = ep93xx_clk_disable, + .is_enabled = ep93xx_clk_is_enabled, +}; + +static struct clk_hw *ep93xx_clk_register_gate(const char *name, + const char *parent_name, + void __iomem *reg, + u8 bit_idx) { - unsigned long rate = clk_get_rate(clk->parent); - u32 value; + struct clk_init_data init; + struct clk_psc *psc; + struct clk *clk; + + psc = kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &clk_ep93xx_gate_ops; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + + psc->reg = reg; + psc->bit_idx = bit_idx; + psc->hw.init = &init; + psc->lock = &clk_lock; + + clk = clk_register(NULL, &psc->hw); + if (IS_ERR(clk)) { + kfree(psc); + return ERR_CAST(clk); + } - value = __raw_readl(EP93XX_SYSCON_PWRCNT); - if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) - return rate; - else - return rate / 2; + return &psc->hw; } -unsigned long clk_get_rate(struct clk *clk) +static u8 ep93xx_mux_get_parent(struct clk_hw *hw) { - if (clk->get_rate) - return clk->get_rate(clk); + struct clk_psc *psc = to_clk_psc(hw); + u32 val = __raw_readl(psc->reg); + + if (!(val & EP93XX_SYSCON_CLKDIV_ESEL)) + return 0; - return clk->rate; + if (!(val & EP93XX_SYSCON_CLKDIV_PSEL)) + return 1; + + return 2; } -EXPORT_SYMBOL(clk_get_rate); -static int set_keytchclk_rate(struct clk *clk, unsigned long rate) +static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index) { + struct clk_psc *psc = to_clk_psc(hw); + unsigned long flags = 0; u32 val; - u32 div_bit; - val = __raw_readl(clk->enable_reg); + if (index >= ARRAY_SIZE(mux_parents)) + return -EINVAL; - /* - * The Key Matrix and ADC clocks are configured using the same - * System Controller register. The clock used will be either - * 1/4 or 1/16 the external clock rate depending on the - * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV - * bit being set or cleared. - */ - div_bit = clk->enable_mask >> 15; + if (psc->lock) + spin_lock_irqsave(psc->lock, flags); - if (rate == EP93XX_KEYTCHCLK_DIV4) - val |= div_bit; - else if (rate == EP93XX_KEYTCHCLK_DIV16) - val &= ~div_bit; - else - return -EINVAL; + val = __raw_readl(psc->reg); + val &= ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL); + + + if (index != 0) { + val |= EP93XX_SYSCON_CLKDIV_ESEL; + val |= (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0; + } + + ep93xx_syscon_swlocked_write(val, psc->reg); + + if (psc->lock) + spin_unlock_irqrestore(psc->lock, flags); - ep93xx_syscon_swlocked_write(val, clk->enable_reg); - clk->rate = rate; return 0; } -static int calc_clk_div(struct clk *clk, unsigned long rate, - int *psel, int *esel, int *pdiv, int *div) +static bool is_best(unsigned long rate, unsigned long now, + unsigned long best) { - struct clk *mclk; - unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1; - int i, found = 0, __div = 0, __pdiv = 0; + return abs(rate - now) < abs(rate - best); +} - /* Don't exceed the maximum rate */ - max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); - rate = min(rate, max_rate); +static int ep93xx_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long rate = req->rate; + struct clk *best_parent = NULL; + unsigned long __parent_rate; + unsigned long best_rate = 0, actual_rate, mclk_rate; + unsigned long best_parent_rate; + int __div = 0, __pdiv = 0; + int i; /* * Try the two pll's and the external clock @@ -376,14 +225,11 @@ static int calc_clk_div(struct clk *clk, unsigned long rate, * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf * */ - for (i = 0; i < 3; i++) { - if (i == 0) - mclk = &clk_xtali; - else if (i == 1) - mclk = &clk_pll1; - else - mclk = &clk_pll2; - mclk_rate = mclk->rate * 2; + for (i = 0; i < ARRAY_SIZE(mux_parents); i++) { + struct clk *parent = clk_get_sys(mux_parents[i], NULL); + + __parent_rate = clk_get_rate(parent); + mclk_rate = __parent_rate * 2; /* Try each predivider value */ for (__pdiv = 4; __pdiv <= 6; __pdiv++) { @@ -392,197 +238,496 @@ static int calc_clk_div(struct clk *clk, unsigned long rate, continue; actual_rate = mclk_rate / (__pdiv * __div); - - if (!found || abs(actual_rate - rate) < rate_err) { - *pdiv = __pdiv - 3; - *div = __div; - *psel = (i == 2); - *esel = (i != 0); - clk->parent = mclk; - clk->rate = actual_rate; - rate_err = abs(actual_rate - rate); - found = 1; + if (is_best(rate, actual_rate, best_rate)) { + best_rate = actual_rate; + best_parent_rate = __parent_rate; + best_parent = parent; } } } - if (!found) + if (!best_parent) return -EINVAL; + req->best_parent_rate = best_parent_rate; + req->best_parent_hw = __clk_get_hw(best_parent); + req->rate = best_rate; + return 0; } -static int set_div_rate(struct clk *clk, unsigned long rate) +static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) { - int err, psel = 0, esel = 0, pdiv = 0, div = 0; - u32 val; + struct clk_psc *psc = to_clk_psc(hw); + unsigned long rate = 0; + u32 val = __raw_readl(psc->reg); + int __pdiv = ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03); + int __div = val & 0x7f; - err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div); - if (err) - return err; + if (__div > 0) + rate = (parent_rate * 2) / ((__pdiv + 3) * __div); - /* Clear the esel, psel, pdiv and div bits */ - val = __raw_readl(clk->enable_reg); - val &= ~0x7fff; - - /* Set the new esel, psel, pdiv and div bits for the new clock rate */ - val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) | - (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) | - (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; - ep93xx_syscon_swlocked_write(val, clk->enable_reg); - return 0; + return rate; } -static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate) +static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { - unsigned val = __raw_readl(clk->enable_reg); - - if (rate == clk_i2s_mclk.rate / 2) - ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, - clk->enable_reg); - else if (rate == clk_i2s_mclk.rate / 4) - ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, - clk->enable_reg); - else + struct clk_psc *psc = to_clk_psc(hw); + int pdiv = 0, div = 0; + unsigned long best_rate = 0, actual_rate, mclk_rate; + int __div = 0, __pdiv = 0; + u32 val; + + mclk_rate = parent_rate * 2; + + for (__pdiv = 4; __pdiv <= 6; __pdiv++) { + __div = mclk_rate / (rate * __pdiv); + if (__div < 2 || __div > 127) + continue; + + actual_rate = mclk_rate / (__pdiv * __div); + if (is_best(rate, actual_rate, best_rate)) { + pdiv = __pdiv - 3; + div = __div; + best_rate = actual_rate; + } + } + + if (!best_rate) return -EINVAL; - clk_i2s_sclk.rate = rate; + val = __raw_readl(psc->reg); + + /* Clear old dividers */ + val &= ~0x37f; + + /* Set the new pdiv and div bits for the new clock rate */ + val |= (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; + ep93xx_syscon_swlocked_write(val, psc->reg); + return 0; } -static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate) -{ - unsigned val = __raw_readl(clk->enable_reg) & - ~EP93XX_I2SCLKDIV_LRDIV_MASK; - - if (rate == clk_i2s_sclk.rate / 32) - ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32, - clk->enable_reg); - else if (rate == clk_i2s_sclk.rate / 64) - ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64, - clk->enable_reg); - else if (rate == clk_i2s_sclk.rate / 128) - ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128, - clk->enable_reg); - else - return -EINVAL; +static const struct clk_ops clk_ddiv_ops = { + .enable = ep93xx_clk_enable, + .disable = ep93xx_clk_disable, + .is_enabled = ep93xx_clk_is_enabled, + .get_parent = ep93xx_mux_get_parent, + .set_parent = ep93xx_mux_set_parent_lock, + .determine_rate = ep93xx_mux_determine_rate, + .recalc_rate = ep93xx_ddiv_recalc_rate, + .set_rate = ep93xx_ddiv_set_rate, +}; - clk_i2s_lrclk.rate = rate; - return 0; +static struct clk_hw *clk_hw_register_ddiv(const char *name, + void __iomem *reg, + u8 bit_idx) +{ + struct clk_init_data init; + struct clk_psc *psc; + struct clk *clk; + + psc = kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &clk_ddiv_ops; + init.flags = 0; + init.parent_names = mux_parents; + init.num_parents = ARRAY_SIZE(mux_parents); + + psc->reg = reg; + psc->bit_idx = bit_idx; + psc->lock = &clk_lock; + psc->hw.init = &init; + + clk = clk_register(NULL, &psc->hw); + if (IS_ERR(clk)) { + kfree(psc); + return ERR_CAST(clk); + } + return &psc->hw; } -int clk_set_rate(struct clk *clk, unsigned long rate) +static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) { - if (clk->set_rate) - return clk->set_rate(clk, rate); + struct clk_psc *psc = to_clk_psc(hw); + u32 val = __raw_readl(psc->reg); + u8 index = (val & psc->mask) >> psc->shift; - return -EINVAL; + if (index > psc->num_div) + return 0; + + return DIV_ROUND_UP_ULL(parent_rate, psc->div[index]); } -EXPORT_SYMBOL(clk_set_rate); -long clk_round_rate(struct clk *clk, unsigned long rate) +static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) { - WARN_ON(clk); - return 0; + struct clk_psc *psc = to_clk_psc(hw); + unsigned long best = 0, now, maxdiv; + int i; + + maxdiv = psc->div[psc->num_div - 1]; + + for (i = 0; i < psc->num_div; i++) { + if ((rate * psc->div[i]) == *parent_rate) + return DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); + + now = DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); + + if (is_best(rate, now, best)) + best = now; + } + + if (!best) + best = DIV_ROUND_UP_ULL(*parent_rate, maxdiv); + + return best; } -EXPORT_SYMBOL(clk_round_rate); -int clk_set_parent(struct clk *clk, struct clk *parent) +static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { - WARN_ON(clk); + struct clk_psc *psc = to_clk_psc(hw); + u32 val = __raw_readl(psc->reg) & ~psc->mask; + int i; + + for (i = 0; i < psc->num_div; i++) + if (rate == parent_rate / psc->div[i]) { + val |= i << psc->shift; + break; + } + + if (i == psc->num_div) + return -EINVAL; + + ep93xx_syscon_swlocked_write(val, psc->reg); + return 0; } -EXPORT_SYMBOL(clk_set_parent); -struct clk *clk_get_parent(struct clk *clk) +static const struct clk_ops ep93xx_div_ops = { + .enable = ep93xx_clk_enable, + .disable = ep93xx_clk_disable, + .is_enabled = ep93xx_clk_is_enabled, + .recalc_rate = ep93xx_div_recalc_rate, + .round_rate = ep93xx_div_round_rate, + .set_rate = ep93xx_div_set_rate, +}; + +static struct clk_hw *clk_hw_register_div(const char *name, + const char *parent_name, + void __iomem *reg, + u8 enable_bit, + u8 shift, + u8 width, + char *clk_divisors, + u8 num_div) { - return clk->parent; + struct clk_init_data init; + struct clk_psc *psc; + struct clk *clk; + + psc = kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &ep93xx_div_ops; + init.flags = 0; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = 1; + + psc->reg = reg; + psc->bit_idx = enable_bit; + psc->mask = GENMASK(shift + width - 1, shift); + psc->shift = shift; + psc->div = clk_divisors; + psc->num_div = num_div; + psc->lock = &clk_lock; + psc->hw.init = &init; + + clk = clk_register(NULL, &psc->hw); + if (IS_ERR(clk)) { + kfree(psc); + return ERR_CAST(clk); + } + return &psc->hw; } -EXPORT_SYMBOL(clk_get_parent); +struct ep93xx_gate { + unsigned int bit; + const char *dev_id; + const char *con_id; +}; -static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; -static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; -static char pclk_divisors[] = { 1, 2, 4, 8 }; +static struct ep93xx_gate ep93xx_uarts[] = { + {EP93XX_SYSCON_DEVCFG_U1EN, "apb:uart1", NULL}, + {EP93XX_SYSCON_DEVCFG_U2EN, "apb:uart2", NULL}, + {EP93XX_SYSCON_DEVCFG_U3EN, "apb:uart3", NULL}, +}; -/* - * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS - */ -static unsigned long calc_pll_rate(u32 config_word) +static void __init ep93xx_uart_clock_init(void) { - unsigned long long rate; - int i; + unsigned int i; + struct clk_hw *hw; + u32 value; + unsigned int clk_uart_div; - rate = clk_xtali.rate; - rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ - rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ - do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ - for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */ - rate >>= 1; + value = __raw_readl(EP93XX_SYSCON_PWRCNT); + if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) + clk_uart_div = 1; + else + clk_uart_div = 2; - return (unsigned long)rate; + hw = clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart_div); + + /* parenting uart gate clocks to uart clock */ + for (i = 0; i < ARRAY_SIZE(ep93xx_uarts); i++) { + hw = ep93xx_clk_register_gate(ep93xx_uarts[i].dev_id, + "uart", + EP93XX_SYSCON_DEVCFG, + ep93xx_uarts[i].bit); + + clk_hw_register_clkdev(hw, NULL, ep93xx_uarts[i].dev_id); + } } +static struct ep93xx_gate ep93xx_dmas[] = { + {EP93XX_SYSCON_PWRCNT_DMA_M2P0, NULL, "m2p0"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2P1, NULL, "m2p1"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2P2, NULL, "m2p2"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2P3, NULL, "m2p3"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2P4, NULL, "m2p4"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2P5, NULL, "m2p5"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2P6, NULL, "m2p6"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2P7, NULL, "m2p7"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2P8, NULL, "m2p8"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2P9, NULL, "m2p9"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2M0, NULL, "m2m0"}, + {EP93XX_SYSCON_PWRCNT_DMA_M2M1, NULL, "m2m1"}, +}; + static void __init ep93xx_dma_clock_init(void) { - clk_m2p0.rate = clk_h.rate; - clk_m2p1.rate = clk_h.rate; - clk_m2p2.rate = clk_h.rate; - clk_m2p3.rate = clk_h.rate; - clk_m2p4.rate = clk_h.rate; - clk_m2p5.rate = clk_h.rate; - clk_m2p6.rate = clk_h.rate; - clk_m2p7.rate = clk_h.rate; - clk_m2p8.rate = clk_h.rate; - clk_m2p9.rate = clk_h.rate; - clk_m2m0.rate = clk_h.rate; - clk_m2m1.rate = clk_h.rate; + unsigned int i; + struct clk_hw *hw; + int ret; + + for (i = 0; i < ARRAY_SIZE(ep93xx_dmas); i++) { + hw = clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id, + "hclk", 0, + EP93XX_SYSCON_PWRCNT, + ep93xx_dmas[i].bit, + 0, + &clk_lock); + + ret = clk_hw_register_clkdev(hw, ep93xx_dmas[i].con_id, NULL); + if (ret) + pr_err("%s: failed to register lookup %s\n", + __func__, ep93xx_dmas[i].con_id); + } } static int __init ep93xx_clock_init(void) { u32 value; + struct clk_hw *hw; + unsigned long clk_pll1_rate; + unsigned long clk_f_rate; + unsigned long clk_h_rate; + unsigned long clk_p_rate; + unsigned long clk_pll2_rate; + unsigned int clk_f_div; + unsigned int clk_h_div; + unsigned int clk_p_div; + unsigned int clk_usb_div; + unsigned long clk_spi_div; + + hw = clk_hw_register_fixed_rate(NULL, "xtali", NULL, 0, EP93XX_EXT_CLK_RATE); + clk_hw_register_clkdev(hw, NULL, "xtali"); /* Determine the bootloader configured pll1 rate */ value = __raw_readl(EP93XX_SYSCON_CLKSET1); if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) - clk_pll1.rate = clk_xtali.rate; + clk_pll1_rate = EP93XX_EXT_CLK_RATE; else - clk_pll1.rate = calc_pll_rate(value); + clk_pll1_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value); + + hw = clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate); + clk_hw_register_clkdev(hw, NULL, "pll1"); /* Initialize the pll1 derived clocks */ - clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; - clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; - clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; + clk_f_div = fclk_divisors[(value >> 25) & 0x7]; + clk_h_div = hclk_divisors[(value >> 20) & 0x7]; + clk_p_div = pclk_divisors[(value >> 18) & 0x3]; + + hw = clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div); + clk_f_rate = clk_get_rate(hw->clk); + hw = clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div); + clk_h_rate = clk_get_rate(hw->clk); + hw = clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div); + clk_p_rate = clk_get_rate(hw->clk); + + clk_hw_register_clkdev(hw, "apb_pclk", NULL); + ep93xx_dma_clock_init(); /* Determine the bootloader configured pll2 rate */ value = __raw_readl(EP93XX_SYSCON_CLKSET2); if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) - clk_pll2.rate = clk_xtali.rate; + clk_pll2_rate = EP93XX_EXT_CLK_RATE; else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) - clk_pll2.rate = calc_pll_rate(value); + clk_pll2_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value); else - clk_pll2.rate = 0; + clk_pll2_rate = 0; + + hw = clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate); + clk_hw_register_clkdev(hw, NULL, "pll2"); /* Initialize the pll2 derived clocks */ - clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); + /* + * These four bits set the divide ratio between the PLL2 + * output and the USB clock. + * 0000 - Divide by 1 + * 0001 - Divide by 2 + * 0010 - Divide by 3 + * 0011 - Divide by 4 + * 0100 - Divide by 5 + * 0101 - Divide by 6 + * 0110 - Divide by 7 + * 0111 - Divide by 8 + * 1000 - Divide by 9 + * 1001 - Divide by 10 + * 1010 - Divide by 11 + * 1011 - Divide by 12 + * 1100 - Divide by 13 + * 1101 - Divide by 14 + * 1110 - Divide by 15 + * 1111 - Divide by 1 + * On power-on-reset these bits are reset to 0000b. + */ + clk_usb_div = (((value >> 28) & 0xf) + 1); + hw = clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_usb_div); + hw = clk_hw_register_gate(NULL, "ohci-platform", + "usb_clk", 0, + EP93XX_SYSCON_PWRCNT, + EP93XX_SYSCON_PWRCNT_USH_EN, + 0, + &clk_lock); + clk_hw_register_clkdev(hw, NULL, "ohci-platform"); /* * EP93xx SSP clock rate was doubled in version E2. For more information * see: * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf */ + clk_spi_div = 1; if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) - clk_spi.rate /= 2; + clk_spi_div = 2; + hw = clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, clk_spi_div); + clk_hw_register_clkdev(hw, NULL, "ep93xx-spi.0"); + + /* pwm clock */ + hw = clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1); + clk_hw_register_clkdev(hw, "pwm_clk", NULL); pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", - clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); + clk_pll1_rate / 1000000, clk_pll2_rate / 1000000); pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", - clk_f.rate / 1000000, clk_h.rate / 1000000, - clk_p.rate / 1000000); + clk_f_rate / 1000000, clk_h_rate / 1000000, + clk_p_rate / 1000000); + + ep93xx_uart_clock_init(); + + /* touchscreen/adc clock */ + hw = clk_hw_register_div("ep93xx-adc", + "xtali", + EP93XX_SYSCON_KEYTCHCLKDIV, + EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, + EP93XX_SYSCON_KEYTCHCLKDIV_ADIV, + 1, + adc_divisors, + ARRAY_SIZE(adc_divisors)); + + clk_hw_register_clkdev(hw, NULL, "ep93xx-adc"); + + /* keypad clock */ + hw = clk_hw_register_div("ep93xx-keypad", + "xtali", + EP93XX_SYSCON_KEYTCHCLKDIV, + EP93XX_SYSCON_KEYTCHCLKDIV_KEN, + EP93XX_SYSCON_KEYTCHCLKDIV_KDIV, + 1, + adc_divisors, + ARRAY_SIZE(adc_divisors)); + + clk_hw_register_clkdev(hw, NULL, "ep93xx-keypad"); + + /* On reset PDIV and VDIV is set to zero, while PDIV zero + * means clock disable, VDIV shouldn't be zero. + * So i set both dividers to minimum. + */ + /* ENA - Enable CLK divider. */ + /* PDIV - 00 - Disable clock */ + /* VDIV - at least 2 */ + /* Check and enable video clk registers */ + value = __raw_readl(EP93XX_SYSCON_VIDCLKDIV); + value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; + ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV); + + /* check and enable i2s clk registers */ + value = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); + value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; + ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV); + + /* video clk */ + hw = clk_hw_register_ddiv("ep93xx-fb", + EP93XX_SYSCON_VIDCLKDIV, + EP93XX_SYSCON_CLKDIV_ENABLE); + + clk_hw_register_clkdev(hw, NULL, "ep93xx-fb"); + + /* i2s clk */ + hw = clk_hw_register_ddiv("mclk", + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_CLKDIV_ENABLE); + + clk_hw_register_clkdev(hw, "mclk", "ep93xx-i2s"); + + /* i2s sclk */ +#define EP93XX_I2SCLKDIV_SDIV_SHIFT 16 +#define EP93XX_I2SCLKDIV_SDIV_WIDTH 1 + hw = clk_hw_register_div("sclk", + "mclk", + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_I2SCLKDIV_SENA, + EP93XX_I2SCLKDIV_SDIV_SHIFT, + EP93XX_I2SCLKDIV_SDIV_WIDTH, + sclk_divisors, + ARRAY_SIZE(sclk_divisors)); + + clk_hw_register_clkdev(hw, "sclk", "ep93xx-i2s"); + + /* i2s lrclk */ +#define EP93XX_I2SCLKDIV_LRDIV32_SHIFT 17 +#define EP93XX_I2SCLKDIV_LRDIV32_WIDTH 3 + hw = clk_hw_register_div("lrclk", + "sclk", + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_I2SCLKDIV_SENA, + EP93XX_I2SCLKDIV_LRDIV32_SHIFT, + EP93XX_I2SCLKDIV_LRDIV32_WIDTH, + lrclk_divisors, + ARRAY_SIZE(lrclk_divisors)); + + clk_hw_register_clkdev(hw, "lrclk", "ep93xx-i2s"); - clkdev_add_table(clocks, ARRAY_SIZE(clocks)); return 0; } postcore_initcall(ep93xx_clock_init); diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 6fb19a393fd2..95e731676cea 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/leds.h> +#include <linux/uaccess.h> #include <linux/termios.h> #include <linux/amba/bus.h> #include <linux/amba/serial.h> @@ -47,6 +48,7 @@ #include <asm/mach/map.h> #include "soc.h" +#include "irqs.h" /************************************************************************* * Static I/O mappings that are needed for all EP93xx platforms @@ -75,8 +77,8 @@ void __init ep93xx_map_io(void) *************************************************************************/ void __init ep93xx_init_irq(void) { - vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); - vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); + vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0); + vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0); } @@ -214,7 +216,7 @@ static int ep93xx_ohci_power_on(struct platform_device *pdev) return PTR_ERR(ep93xx_ohci_host_clock); } - return clk_enable(ep93xx_ohci_host_clock); + return clk_prepare_enable(ep93xx_ohci_host_clock); } static void ep93xx_ohci_power_off(struct platform_device *pdev) @@ -1004,8 +1006,3 @@ void ep93xx_restart(enum reboot_mode mode, const char *cmd) while (1) ; } - -void __init ep93xx_init_late(void) -{ - crunch_init(); -} diff --git a/arch/arm/mach-ep93xx/crunch-bits.S b/arch/arm/mach-ep93xx/crunch-bits.S deleted file mode 100644 index fb2dbf76f09e..000000000000 --- a/arch/arm/mach-ep93xx/crunch-bits.S +++ /dev/null @@ -1,310 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/kernel/crunch-bits.S - * Cirrus MaverickCrunch context switching and handling - * - * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> - * - * Shamelessly stolen from the iWMMXt code by Nicolas Pitre, which is - * Copyright (c) 2003-2004, MontaVista Software, Inc. - */ - -#include <linux/linkage.h> -#include <asm/ptrace.h> -#include <asm/thread_info.h> -#include <asm/asm-offsets.h> -#include <asm/assembler.h> -#include <mach/ep93xx-regs.h> - -/* - * We can't use hex constants here due to a bug in gas. - */ -#define CRUNCH_MVDX0 0 -#define CRUNCH_MVDX1 8 -#define CRUNCH_MVDX2 16 -#define CRUNCH_MVDX3 24 -#define CRUNCH_MVDX4 32 -#define CRUNCH_MVDX5 40 -#define CRUNCH_MVDX6 48 -#define CRUNCH_MVDX7 56 -#define CRUNCH_MVDX8 64 -#define CRUNCH_MVDX9 72 -#define CRUNCH_MVDX10 80 -#define CRUNCH_MVDX11 88 -#define CRUNCH_MVDX12 96 -#define CRUNCH_MVDX13 104 -#define CRUNCH_MVDX14 112 -#define CRUNCH_MVDX15 120 -#define CRUNCH_MVAX0L 128 -#define CRUNCH_MVAX0M 132 -#define CRUNCH_MVAX0H 136 -#define CRUNCH_MVAX1L 140 -#define CRUNCH_MVAX1M 144 -#define CRUNCH_MVAX1H 148 -#define CRUNCH_MVAX2L 152 -#define CRUNCH_MVAX2M 156 -#define CRUNCH_MVAX2H 160 -#define CRUNCH_MVAX3L 164 -#define CRUNCH_MVAX3M 168 -#define CRUNCH_MVAX3H 172 -#define CRUNCH_DSPSC 176 - -#define CRUNCH_SIZE 184 - - .text - -/* - * Lazy switching of crunch coprocessor context - * - * r10 = struct thread_info pointer - * r9 = ret_from_exception - * lr = undefined instr exit - * - * called from prefetch exception handler with interrupts enabled - */ -ENTRY(crunch_task_enable) - inc_preempt_count r10, r3 - - ldr r8, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr - - ldr r1, [r8, #0x80] - tst r1, #0x00800000 @ access to crunch enabled? - bne 2f @ if so no business here - mov r3, #0xaa @ unlock syscon swlock - str r3, [r8, #0xc0] - orr r1, r1, #0x00800000 @ enable access to crunch - str r1, [r8, #0x80] - - ldr r3, =crunch_owner - add r0, r10, #TI_CRUNCH_STATE @ get task crunch save area - ldr r2, [sp, #60] @ current task pc value - ldr r1, [r3] @ get current crunch owner - str r0, [r3] @ this task now owns crunch - sub r2, r2, #4 @ adjust pc back - str r2, [sp, #60] - - ldr r2, [r8, #0x80] - mov r2, r2 @ flush out enable (@@@) - - teq r1, #0 @ test for last ownership - mov lr, r9 @ normal exit from exception - beq crunch_load @ no owner, skip save - -crunch_save: - cfstr64 mvdx0, [r1, #CRUNCH_MVDX0] @ save 64b registers - cfstr64 mvdx1, [r1, #CRUNCH_MVDX1] - cfstr64 mvdx2, [r1, #CRUNCH_MVDX2] - cfstr64 mvdx3, [r1, #CRUNCH_MVDX3] - cfstr64 mvdx4, [r1, #CRUNCH_MVDX4] - cfstr64 mvdx5, [r1, #CRUNCH_MVDX5] - cfstr64 mvdx6, [r1, #CRUNCH_MVDX6] - cfstr64 mvdx7, [r1, #CRUNCH_MVDX7] - cfstr64 mvdx8, [r1, #CRUNCH_MVDX8] - cfstr64 mvdx9, [r1, #CRUNCH_MVDX9] - cfstr64 mvdx10, [r1, #CRUNCH_MVDX10] - cfstr64 mvdx11, [r1, #CRUNCH_MVDX11] - cfstr64 mvdx12, [r1, #CRUNCH_MVDX12] - cfstr64 mvdx13, [r1, #CRUNCH_MVDX13] - cfstr64 mvdx14, [r1, #CRUNCH_MVDX14] - cfstr64 mvdx15, [r1, #CRUNCH_MVDX15] - -#ifdef __ARMEB__ -#error fix me for ARMEB -#endif - - cfmv32al mvfx0, mvax0 @ save 72b accumulators - cfstr32 mvfx0, [r1, #CRUNCH_MVAX0L] - cfmv32am mvfx0, mvax0 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX0M] - cfmv32ah mvfx0, mvax0 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX0H] - cfmv32al mvfx0, mvax1 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX1L] - cfmv32am mvfx0, mvax1 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX1M] - cfmv32ah mvfx0, mvax1 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX1H] - cfmv32al mvfx0, mvax2 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX2L] - cfmv32am mvfx0, mvax2 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX2M] - cfmv32ah mvfx0, mvax2 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX2H] - cfmv32al mvfx0, mvax3 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX3L] - cfmv32am mvfx0, mvax3 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX3M] - cfmv32ah mvfx0, mvax3 - cfstr32 mvfx0, [r1, #CRUNCH_MVAX3H] - - cfmv32sc mvdx0, dspsc @ save status word - cfstr64 mvdx0, [r1, #CRUNCH_DSPSC] - - teq r0, #0 @ anything to load? - cfldr64eq mvdx0, [r1, #CRUNCH_MVDX0] @ mvdx0 was clobbered - beq 1f - -crunch_load: - cfldr64 mvdx0, [r0, #CRUNCH_DSPSC] @ load status word - cfmvsc32 dspsc, mvdx0 - - cfldr32 mvfx0, [r0, #CRUNCH_MVAX0L] @ load 72b accumulators - cfmval32 mvax0, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX0M] - cfmvam32 mvax0, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX0H] - cfmvah32 mvax0, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX1L] - cfmval32 mvax1, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX1M] - cfmvam32 mvax1, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX1H] - cfmvah32 mvax1, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX2L] - cfmval32 mvax2, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX2M] - cfmvam32 mvax2, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX2H] - cfmvah32 mvax2, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX3L] - cfmval32 mvax3, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX3M] - cfmvam32 mvax3, mvfx0 - cfldr32 mvfx0, [r0, #CRUNCH_MVAX3H] - cfmvah32 mvax3, mvfx0 - - cfldr64 mvdx0, [r0, #CRUNCH_MVDX0] @ load 64b registers - cfldr64 mvdx1, [r0, #CRUNCH_MVDX1] - cfldr64 mvdx2, [r0, #CRUNCH_MVDX2] - cfldr64 mvdx3, [r0, #CRUNCH_MVDX3] - cfldr64 mvdx4, [r0, #CRUNCH_MVDX4] - cfldr64 mvdx5, [r0, #CRUNCH_MVDX5] - cfldr64 mvdx6, [r0, #CRUNCH_MVDX6] - cfldr64 mvdx7, [r0, #CRUNCH_MVDX7] - cfldr64 mvdx8, [r0, #CRUNCH_MVDX8] - cfldr64 mvdx9, [r0, #CRUNCH_MVDX9] - cfldr64 mvdx10, [r0, #CRUNCH_MVDX10] - cfldr64 mvdx11, [r0, #CRUNCH_MVDX11] - cfldr64 mvdx12, [r0, #CRUNCH_MVDX12] - cfldr64 mvdx13, [r0, #CRUNCH_MVDX13] - cfldr64 mvdx14, [r0, #CRUNCH_MVDX14] - cfldr64 mvdx15, [r0, #CRUNCH_MVDX15] - -1: -#ifdef CONFIG_PREEMPT_COUNT - get_thread_info r10 -#endif -2: dec_preempt_count r10, r3 - ret lr - -/* - * Back up crunch regs to save area and disable access to them - * (mainly for gdb or sleep mode usage) - * - * r0 = struct thread_info pointer of target task or NULL for any - */ -ENTRY(crunch_task_disable) - stmfd sp!, {r4, r5, lr} - - mrs ip, cpsr - orr r2, ip, #PSR_I_BIT @ disable interrupts - msr cpsr_c, r2 - - ldr r4, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr - - ldr r3, =crunch_owner - add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area - ldr r1, [r3] @ get current crunch owner - teq r1, #0 @ any current owner? - beq 1f @ no: quit - teq r0, #0 @ any owner? - teqne r1, r2 @ or specified one? - bne 1f @ no: quit - - ldr r5, [r4, #0x80] @ enable access to crunch - mov r2, #0xaa - str r2, [r4, #0xc0] - orr r5, r5, #0x00800000 - str r5, [r4, #0x80] - - mov r0, #0 @ nothing to load - str r0, [r3] @ no more current owner - ldr r2, [r4, #0x80] @ flush out enable (@@@) - mov r2, r2 - bl crunch_save - - mov r2, #0xaa @ disable access to crunch - str r2, [r4, #0xc0] - bic r5, r5, #0x00800000 - str r5, [r4, #0x80] - ldr r5, [r4, #0x80] @ flush out enable (@@@) - mov r5, r5 - -1: msr cpsr_c, ip @ restore interrupt mode - ldmfd sp!, {r4, r5, pc} - -/* - * Copy crunch state to given memory address - * - * r0 = struct thread_info pointer of target task - * r1 = memory address where to store crunch state - * - * this is called mainly in the creation of signal stack frames - */ -ENTRY(crunch_task_copy) - mrs ip, cpsr - orr r2, ip, #PSR_I_BIT @ disable interrupts - msr cpsr_c, r2 - - ldr r3, =crunch_owner - add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area - ldr r3, [r3] @ get current crunch owner - teq r2, r3 @ does this task own it... - beq 1f - - @ current crunch values are in the task save area - msr cpsr_c, ip @ restore interrupt mode - mov r0, r1 - mov r1, r2 - mov r2, #CRUNCH_SIZE - b memcpy - -1: @ this task owns crunch regs -- grab a copy from there - mov r0, #0 @ nothing to load - mov r3, lr @ preserve return address - bl crunch_save - msr cpsr_c, ip @ restore interrupt mode - ret r3 - -/* - * Restore crunch state from given memory address - * - * r0 = struct thread_info pointer of target task - * r1 = memory address where to get crunch state from - * - * this is used to restore crunch state when unwinding a signal stack frame - */ -ENTRY(crunch_task_restore) - mrs ip, cpsr - orr r2, ip, #PSR_I_BIT @ disable interrupts - msr cpsr_c, r2 - - ldr r3, =crunch_owner - add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area - ldr r3, [r3] @ get current crunch owner - teq r2, r3 @ does this task own it... - beq 1f - - @ this task doesn't own crunch regs -- use its save area - msr cpsr_c, ip @ restore interrupt mode - mov r0, r2 - mov r2, #CRUNCH_SIZE - b memcpy - -1: @ this task owns crunch regs -- load them directly - mov r0, r1 - mov r1, #0 @ nothing to save - mov r3, lr @ preserve return address - bl crunch_load - msr cpsr_c, ip @ restore interrupt mode - ret r3 diff --git a/arch/arm/mach-ep93xx/crunch.c b/arch/arm/mach-ep93xx/crunch.c deleted file mode 100644 index 1c05c5bf7e5c..000000000000 --- a/arch/arm/mach-ep93xx/crunch.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/kernel/crunch.c - * Cirrus MaverickCrunch context switching and handling - * - * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> - */ - -#include <linux/module.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/init.h> -#include <linux/io.h> - -#include <asm/thread_notify.h> - -#include "soc.h" - -struct crunch_state *crunch_owner; - -void crunch_task_release(struct thread_info *thread) -{ - local_irq_disable(); - if (crunch_owner == &thread->crunchstate) - crunch_owner = NULL; - local_irq_enable(); -} - -static int crunch_enabled(u32 devcfg) -{ - return !!(devcfg & EP93XX_SYSCON_DEVCFG_CPENA); -} - -static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t) -{ - struct thread_info *thread = (struct thread_info *)t; - struct crunch_state *crunch_state; - u32 devcfg; - - crunch_state = &thread->crunchstate; - - switch (cmd) { - case THREAD_NOTIFY_FLUSH: - memset(crunch_state, 0, sizeof(*crunch_state)); - - /* - * FALLTHROUGH: Ensure we don't try to overwrite our newly - * initialised state information on the first fault. - */ - /* Fall through */ - - case THREAD_NOTIFY_EXIT: - crunch_task_release(thread); - break; - - case THREAD_NOTIFY_SWITCH: - devcfg = __raw_readl(EP93XX_SYSCON_DEVCFG); - if (crunch_enabled(devcfg) || crunch_owner == crunch_state) { - /* - * We don't use ep93xx_syscon_swlocked_write() here - * because we are on the context switch path and - * preemption is already disabled. - */ - devcfg ^= EP93XX_SYSCON_DEVCFG_CPENA; - __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); - __raw_writel(devcfg, EP93XX_SYSCON_DEVCFG); - } - break; - } - - return NOTIFY_DONE; -} - -static struct notifier_block crunch_notifier_block = { - .notifier_call = crunch_do, -}; - -int __init crunch_init(void) -{ - thread_register_notifier(&crunch_notifier_block); - elf_hwcap |= HWCAP_CRUNCH; - - return 0; -} diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index 7b7280c21ee0..4b90899a66e9 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -243,11 +243,11 @@ static void __init edb93xx_init_machine(void) MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -256,11 +256,11 @@ MACHINE_END MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") /* Maintainer: George Kashperko <george@chas.com.ua> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -269,11 +269,11 @@ MACHINE_END MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -282,11 +282,11 @@ MACHINE_END MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -295,11 +295,11 @@ MACHINE_END MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -308,11 +308,11 @@ MACHINE_END MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -321,11 +321,11 @@ MACHINE_END MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -334,11 +334,11 @@ MACHINE_END MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/ep93xx-regs.h index 6839ea032e58..8fa3646de0a4 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/ep93xx-regs.h @@ -1,8 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h - */ - #ifndef __ASM_ARCH_EP93XX_REGS_H #define __ASM_ARCH_EP93XX_REGS_H diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c index 8905db1edd5a..0b7043e3e178 100644 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ b/arch/arm/mach-ep93xx/gesbc9312.c @@ -32,10 +32,10 @@ static void __init gesbc9312_init_machine(void) MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = gesbc9312_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END diff --git a/arch/arm/mach-ep93xx/gpio-ep93xx.h b/arch/arm/mach-ep93xx/gpio-ep93xx.h index 242af4a401ea..7b46eb7e5507 100644 --- a/arch/arm/mach-ep93xx/gpio-ep93xx.h +++ b/arch/arm/mach-ep93xx/gpio-ep93xx.h @@ -4,7 +4,7 @@ #ifndef __GPIO_EP93XX_H #define __GPIO_EP93XX_H -#include <mach/ep93xx-regs.h> +#include "ep93xx-regs.h" #define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000) #define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) diff --git a/arch/arm/mach-ep93xx/include/mach/irqs.h b/arch/arm/mach-ep93xx/include/mach/irqs.h deleted file mode 100644 index 244daf83ce6d..000000000000 --- a/arch/arm/mach-ep93xx/include/mach/irqs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/irqs.h - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define IRQ_EP93XX_COMMRX 2 -#define IRQ_EP93XX_COMMTX 3 -#define IRQ_EP93XX_TIMER1 4 -#define IRQ_EP93XX_TIMER2 5 -#define IRQ_EP93XX_AACINTR 6 -#define IRQ_EP93XX_DMAM2P0 7 -#define IRQ_EP93XX_DMAM2P1 8 -#define IRQ_EP93XX_DMAM2P2 9 -#define IRQ_EP93XX_DMAM2P3 10 -#define IRQ_EP93XX_DMAM2P4 11 -#define IRQ_EP93XX_DMAM2P5 12 -#define IRQ_EP93XX_DMAM2P6 13 -#define IRQ_EP93XX_DMAM2P7 14 -#define IRQ_EP93XX_DMAM2P8 15 -#define IRQ_EP93XX_DMAM2P9 16 -#define IRQ_EP93XX_DMAM2M0 17 -#define IRQ_EP93XX_DMAM2M1 18 -#define IRQ_EP93XX_GPIO0MUX 19 -#define IRQ_EP93XX_GPIO1MUX 20 -#define IRQ_EP93XX_GPIO2MUX 21 -#define IRQ_EP93XX_GPIO3MUX 22 -#define IRQ_EP93XX_UART1RX 23 -#define IRQ_EP93XX_UART1TX 24 -#define IRQ_EP93XX_UART2RX 25 -#define IRQ_EP93XX_UART2TX 26 -#define IRQ_EP93XX_UART3RX 27 -#define IRQ_EP93XX_UART3TX 28 -#define IRQ_EP93XX_KEY 29 -#define IRQ_EP93XX_TOUCH 30 -#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc - -#define IRQ_EP93XX_EXT0 32 -#define IRQ_EP93XX_EXT1 33 -#define IRQ_EP93XX_EXT2 34 -#define IRQ_EP93XX_64HZ 35 -#define IRQ_EP93XX_WATCHDOG 36 -#define IRQ_EP93XX_RTC 37 -#define IRQ_EP93XX_IRDA 38 -#define IRQ_EP93XX_ETHERNET 39 -#define IRQ_EP93XX_EXT3 40 -#define IRQ_EP93XX_PROG 41 -#define IRQ_EP93XX_1HZ 42 -#define IRQ_EP93XX_VSYNC 43 -#define IRQ_EP93XX_VIDEO_FIFO 44 -#define IRQ_EP93XX_SSP1RX 45 -#define IRQ_EP93XX_SSP1TX 46 -#define IRQ_EP93XX_GPIO4MUX 47 -#define IRQ_EP93XX_GPIO5MUX 48 -#define IRQ_EP93XX_GPIO6MUX 49 -#define IRQ_EP93XX_GPIO7MUX 50 -#define IRQ_EP93XX_TIMER3 51 -#define IRQ_EP93XX_UART1 52 -#define IRQ_EP93XX_SSP 53 -#define IRQ_EP93XX_UART2 54 -#define IRQ_EP93XX_UART3 55 -#define IRQ_EP93XX_USB 56 -#define IRQ_EP93XX_ETHERNET_PME 57 -#define IRQ_EP93XX_DSP 58 -#define IRQ_EP93XX_GPIO_AB 59 -#define IRQ_EP93XX_SAI 60 -#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff - -#define NR_EP93XX_IRQS (64 + 24) - -#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) -#define EP93XX_BOARD_IRQS 32 - -#define NR_IRQS (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS) - - -#endif diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h deleted file mode 100644 index b3ec1db988db..000000000000 --- a/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-ep93xx/include/mach/uncompress.h - * - * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> - */ - -#include <mach/ep93xx-regs.h> -#include <asm/mach-types.h> - -static unsigned char __raw_readb(unsigned int ptr) -{ - return *((volatile unsigned char *)ptr); -} - -static unsigned int __raw_readl(unsigned int ptr) -{ - return *((volatile unsigned int *)ptr); -} - -static void __raw_writeb(unsigned char value, unsigned int ptr) -{ - *((volatile unsigned char *)ptr) = value; -} - -static void __raw_writel(unsigned int value, unsigned int ptr) -{ - *((volatile unsigned int *)ptr) = value; -} - -#define PHYS_UART_DATA (CONFIG_DEBUG_UART_PHYS + 0x00) -#define PHYS_UART_FLAG (CONFIG_DEBUG_UART_PHYS + 0x18) -#define UART_FLAG_TXFF 0x20 - -static inline void putc(int c) -{ - int i; - - for (i = 0; i < 10000; i++) { - /* Transmit fifo not full? */ - if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)) - break; - } - - __raw_writeb(c, PHYS_UART_DATA); -} - -static inline void flush(void) -{ -} - - -/* - * Some bootloaders don't turn off DMA from the ethernet MAC before - * jumping to linux, which means that we might end up with bits of RX - * status and packet data scribbled over the uncompressed kernel image. - * Work around this by resetting the ethernet MAC before we uncompress. - */ -#define PHYS_ETH_SELF_CTL 0x80010020 -#define ETH_SELF_CTL_RESET 0x00000001 - -static void ethernet_reset(void) -{ - unsigned int v; - - /* Reset the ethernet MAC. */ - v = __raw_readl(PHYS_ETH_SELF_CTL); - __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL); - - /* Wait for reset to finish. */ - while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET) - ; -} - -#define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000 -#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000 -#define TS72XX_WDT_FEED_VAL 0x05 - -static void __maybe_unused ts72xx_watchdog_disable(void) -{ - __raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE); - __raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE); -} - -static void arch_decomp_setup(void) -{ - if (machine_is_ts72xx()) - ts72xx_watchdog_disable(); - ethernet_reset(); -} diff --git a/arch/arm/mach-ep93xx/irqs.h b/arch/arm/mach-ep93xx/irqs.h new file mode 100644 index 000000000000..353201b90c66 --- /dev/null +++ b/arch/arm/mach-ep93xx/irqs.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#define IRQ_EP93XX_VIC0 1 + +#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2) +#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3) +#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4) +#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5) +#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6) +#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7) +#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8) +#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9) +#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10) +#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11) +#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12) +#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13) +#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14) +#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15) +#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16) +#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17) +#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18) +#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19) +#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20) +#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21) +#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22) +#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23) +#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24) +#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25) +#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26) +#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27) +#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28) +#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29) +#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30) +#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc + +#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32) + +#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0) +#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1) +#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2) +#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3) +#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4) +#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5) +#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6) +#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7) +#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8) +#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9) +#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10) +#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11) +#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12) +#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13) +#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14) +#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15) +#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16) +#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17) +#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18) +#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19) +#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20) +#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21) +#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22) +#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23) +#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24) +#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25) +#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26) +#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27) +#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28) +#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff + +#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24) + +#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) +#define EP93XX_BOARD_IRQS 32 + +#endif diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c index b18ebf26da45..c121c459aa17 100644 --- a/arch/arm/mach-ep93xx/micro9.c +++ b/arch/arm/mach-ep93xx/micro9.c @@ -76,11 +76,11 @@ static void __init micro9_init_machine(void) MACHINE_START(MICRO9, "Contec Micro9-High") /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = micro9_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -89,11 +89,11 @@ MACHINE_END MACHINE_START(MICRO9M, "Contec Micro9-Mid") /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = micro9_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -102,11 +102,11 @@ MACHINE_END MACHINE_START(MICRO9L, "Contec Micro9-Lite") /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = micro9_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif @@ -115,11 +115,11 @@ MACHINE_END MACHINE_START(MICRO9S, "Contec Micro9-Slim") /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = micro9_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END #endif diff --git a/arch/arm/mach-ep93xx/platform.h b/arch/arm/mach-ep93xx/platform.h index b4045a186239..5fb1b919133f 100644 --- a/arch/arm/mach-ep93xx/platform.h +++ b/arch/arm/mach-ep93xx/platform.h @@ -38,12 +38,5 @@ struct device *ep93xx_init_devices(void); extern void ep93xx_timer_init(void); void ep93xx_restart(enum reboot_mode, const char *); -void ep93xx_init_late(void); - -#ifdef CONFIG_CRUNCH -int crunch_init(void); -#else -static inline int crunch_init(void) { return 0; } -#endif #endif diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index 8a53b74dc4b2..569e72413561 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -119,10 +119,10 @@ static void __init simone_init_machine(void) MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") /* Maintainer: Ryan Mallon */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = simone_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c index 703f25f19d51..1dfb725671b1 100644 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ b/arch/arm/mach-ep93xx/snappercl15.c @@ -153,10 +153,10 @@ static void __init snappercl15_init_machine(void) MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") /* Maintainer: Ryan Mallon */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = snappercl15_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h index f2dace1c9154..3245ebbd5069 100644 --- a/arch/arm/mach-ep93xx/soc.h +++ b/arch/arm/mach-ep93xx/soc.h @@ -9,7 +9,8 @@ #ifndef _EP93XX_SOC_H #define _EP93XX_SOC_H -#include <mach/ep93xx-regs.h> +#include "ep93xx-regs.h" +#include "irqs.h" /* * EP93xx Physical Memory Map: @@ -111,19 +112,19 @@ #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) #define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31) #define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29) -#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28) -#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27) -#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17) -#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16) +#define EP93XX_SYSCON_PWRCNT_USH_EN 28 +#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27 +#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16 #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20) @@ -139,13 +140,13 @@ #define EP93XX_SYSCON_DEVCFG_GONK (1<<27) #define EP93XX_SYSCON_DEVCFG_TONG (1<<26) #define EP93XX_SYSCON_DEVCFG_MONG (1<<25) -#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24) +#define EP93XX_SYSCON_DEVCFG_U3EN 24 #define EP93XX_SYSCON_DEVCFG_CPENA (1<<23) #define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22) #define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21) -#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20) +#define EP93XX_SYSCON_DEVCFG_U2EN 20 #define EP93XX_SYSCON_DEVCFG_EXVC (1<<19) -#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18) +#define EP93XX_SYSCON_DEVCFG_U1EN 18 #define EP93XX_SYSCON_DEVCFG_TIN (1<<17) #define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15) #define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14) @@ -163,12 +164,12 @@ #define EP93XX_SYSCON_DEVCFG_KEYS (1<<1) #define EP93XX_SYSCON_DEVCFG_SHENA (1<<0) #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84) -#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15) +#define EP93XX_SYSCON_CLKDIV_ENABLE 15 #define EP93XX_SYSCON_CLKDIV_ESEL (1<<14) #define EP93XX_SYSCON_CLKDIV_PSEL (1<<13) #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 #define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c) -#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31) +#define EP93XX_SYSCON_I2SCLKDIV_SENA 31 #define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29) #define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19) #define EP93XX_I2SCLKDIV_SDIV (1 << 16) @@ -177,9 +178,9 @@ #define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17) #define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17) #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90) -#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31) -#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16) -#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15) +#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31 +#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16 +#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15 #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0) #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c) #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000) diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/timer-ep93xx.c index de998830f534..dd4b164d1831 100644 --- a/arch/arm/mach-ep93xx/timer-ep93xx.c +++ b/arch/arm/mach-ep93xx/timer-ep93xx.c @@ -117,15 +117,11 @@ static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction ep93xx_timer_irq = { - .name = "ep93xx timer", - .flags = IRQF_TIMER | IRQF_IRQPOLL, - .handler = ep93xx_timer_interrupt, - .dev_id = &ep93xx_clockevent, -}; - void __init ep93xx_timer_init(void) { + int irq = IRQ_EP93XX_TIMER3; + unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL; + /* Enable and register clocksource and sched_clock on timer 4 */ writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, EP93XX_TIMER4_VALUE_HIGH); @@ -136,7 +132,9 @@ void __init ep93xx_timer_init(void) EP93XX_TIMER4_RATE); /* Set up clockevent on timer 3 */ - setup_irq(IRQ_EP93XX_TIMER3, &ep93xx_timer_irq); + if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer", + &ep93xx_clockevent)) + pr_err("Failed to request irq %d (ep93xx timer)\n", irq); clockevents_config_and_register(&ep93xx_clockevent, EP93XX_TIMER123_RATE, 1, diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index e0e1b11032f1..d3de7283ecb3 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -22,7 +22,6 @@ #include "gpio-ep93xx.h" #include "hardware.h" -#include <mach/irqs.h> #include <asm/mach-types.h> #include <asm/mach/map.h> @@ -151,7 +150,7 @@ static struct platform_device ts72xx_nand_flash = { .num_resources = ARRAY_SIZE(ts72xx_nand_resource), }; -void __init ts72xx_register_flash(struct mtd_partition *parts, int n, +static void __init ts72xx_register_flash(struct mtd_partition *parts, int n, resource_size_t start) { /* @@ -350,11 +349,11 @@ static void __init ts72xx_init_machine(void) MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ts72xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = ts72xx_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END @@ -414,10 +413,10 @@ static void __init bk3_init_machine(void) MACHINE_START(BK3, "Liebherr controller BK3.1") /* Maintainer: Lukasz Majewski <lukma@denx.de> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ts72xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = bk3_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c index cbcba3136d74..30d9cf3791eb 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -302,10 +302,10 @@ static void __init vision_init_machine(void) MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307") /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS + EP93XX_BOARD_IRQS, .map_io = vision_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, .init_machine = vision_init_machine, - .init_late = ep93xx_init_late, .restart = ep93xx_restart, MACHINE_END |