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-rw-r--r--arch/arm/mach-integrator/Kconfig2
-rw-r--r--arch/arm/mach-integrator/common.h8
-rw-r--r--arch/arm/mach-integrator/core.c141
-rw-r--r--arch/arm/mach-integrator/impd1.c76
-rw-r--r--arch/arm/mach-integrator/include/mach/irqs.h109
-rw-r--r--arch/arm/mach-integrator/include/mach/platform.h1
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c163
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c121
-rw-r--r--arch/arm/mach-integrator/pci_v3.c32
9 files changed, 404 insertions, 249 deletions
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index 350e26636a06..abeff25532ab 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -8,6 +8,7 @@ config ARCH_INTEGRATOR_AP
select MIGHT_HAVE_PCI
select SERIAL_AMBA_PL010
select SERIAL_AMBA_PL010_CONSOLE
+ select SOC_BUS
help
Include support for the ARM(R) Integrator/AP and
Integrator/PP2 platforms.
@@ -19,6 +20,7 @@ config ARCH_INTEGRATOR_CP
select PLAT_VERSATILE_CLCD
select SERIAL_AMBA_PL011
select SERIAL_AMBA_PL011_CONSOLE
+ select SOC_BUS
help
Include support for the ARM(R) Integrator CP platform.
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index c3ff21b5ea24..79197d8b34aa 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,6 +1,12 @@
#include <linux/amba/serial.h>
-extern struct amba_pl010_data integrator_uart_data;
+#ifdef CONFIG_ARCH_INTEGRATOR_AP
+extern struct amba_pl010_data ap_uart_data;
+#else
+/* Not used without Integrator/AP support anyway */
+struct amba_pl010_data ap_uart_data {};
+#endif
void integrator_init_early(void);
int integrator_init(bool is_cp);
void integrator_reserve(void);
void integrator_restart(char, const char *);
+void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index ea22a17246d7..39c060f75e47 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -18,10 +18,10 @@
#include <linux/memblock.h>
#include <linux/sched.h>
#include <linux/smp.h>
-#include <linux/termios.h>
#include <linux/amba/bus.h>
#include <linux/amba/serial.h>
#include <linux/io.h>
+#include <linux/stat.h>
#include <mach/hardware.h>
#include <mach/platform.h>
@@ -46,10 +46,10 @@ static AMBA_APB_DEVICE(rtc, "rtc", 0,
INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
static AMBA_APB_DEVICE(uart0, "uart0", 0,
- INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
+ INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, NULL);
static AMBA_APB_DEVICE(uart1, "uart1", 0,
- INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
+ INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, NULL);
static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL);
static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL);
@@ -77,6 +77,8 @@ int __init integrator_init(bool is_cp)
uart1_device.periphid = 0x00041010;
kmi0_device.periphid = 0x00041050;
kmi1_device.periphid = 0x00041050;
+ uart0_device.dev.platform_data = &ap_uart_data;
+ uart1_device.dev.platform_data = &ap_uart_data;
}
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
@@ -89,49 +91,6 @@ int __init integrator_init(bool is_cp)
#endif
-/*
- * On the Integrator platform, the port RTS and DTR are provided by
- * bits in the following SC_CTRLS register bits:
- * RTS DTR
- * UART0 7 6
- * UART1 5 4
- */
-#define SC_CTRLC __io_address(INTEGRATOR_SC_CTRLC)
-#define SC_CTRLS __io_address(INTEGRATOR_SC_CTRLS)
-
-static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
-{
- unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
- u32 phybase = dev->res.start;
-
- if (phybase == INTEGRATOR_UART0_BASE) {
- /* UART0 */
- rts_mask = 1 << 4;
- dtr_mask = 1 << 5;
- } else {
- /* UART1 */
- rts_mask = 1 << 6;
- dtr_mask = 1 << 7;
- }
-
- if (mctrl & TIOCM_RTS)
- ctrlc |= rts_mask;
- else
- ctrls |= rts_mask;
-
- if (mctrl & TIOCM_DTR)
- ctrlc |= dtr_mask;
- else
- ctrls |= dtr_mask;
-
- __raw_writel(ctrls, SC_CTRLS);
- __raw_writel(ctrlc, SC_CTRLC);
-}
-
-struct amba_pl010_data integrator_uart_data = {
- .set_mctrl = integrator_uart_set_mctrl,
-};
-
static DEFINE_RAW_SPINLOCK(cm_lock);
/**
@@ -169,3 +128,93 @@ void integrator_restart(char mode, const char *cmd)
{
cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
}
+
+static u32 integrator_id;
+
+static ssize_t intcp_get_manf(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%02x\n", integrator_id >> 24);
+}
+
+static struct device_attribute intcp_manf_attr =
+ __ATTR(manufacturer, S_IRUGO, intcp_get_manf, NULL);
+
+static ssize_t intcp_get_arch(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ const char *arch;
+
+ switch ((integrator_id >> 16) & 0xff) {
+ case 0x00:
+ arch = "ASB little-endian";
+ break;
+ case 0x01:
+ arch = "AHB little-endian";
+ break;
+ case 0x03:
+ arch = "AHB-Lite system bus, bi-endian";
+ break;
+ case 0x04:
+ arch = "AHB";
+ break;
+ default:
+ arch = "Unknown";
+ break;
+ }
+
+ return sprintf(buf, "%s\n", arch);
+}
+
+static struct device_attribute intcp_arch_attr =
+ __ATTR(architecture, S_IRUGO, intcp_get_arch, NULL);
+
+static ssize_t intcp_get_fpga(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ const char *fpga;
+
+ switch ((integrator_id >> 12) & 0xf) {
+ case 0x01:
+ fpga = "XC4062";
+ break;
+ case 0x02:
+ fpga = "XC4085";
+ break;
+ case 0x04:
+ fpga = "EPM7256AE (Altera PLD)";
+ break;
+ default:
+ fpga = "Unknown";
+ break;
+ }
+
+ return sprintf(buf, "%s\n", fpga);
+}
+
+static struct device_attribute intcp_fpga_attr =
+ __ATTR(fpga, S_IRUGO, intcp_get_fpga, NULL);
+
+static ssize_t intcp_get_build(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%02x\n", (integrator_id >> 4) & 0xFF);
+}
+
+static struct device_attribute intcp_build_attr =
+ __ATTR(build, S_IRUGO, intcp_get_build, NULL);
+
+
+
+void integrator_init_sysfs(struct device *parent, u32 id)
+{
+ integrator_id = id;
+ device_create_file(parent, &intcp_manf_attr);
+ device_create_file(parent, &intcp_arch_attr);
+ device_create_file(parent, &intcp_fpga_attr);
+ device_create_file(parent, &intcp_build_attr);
+}
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index e428f3ab15c7..9f82f9dcbb98 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -21,10 +21,9 @@
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/io.h>
+#include <linux/platform_data/clk-integrator.h>
#include <linux/slab.h>
-#include <linux/clkdev.h>
-#include <asm/hardware/icst.h>
#include <mach/lm.h>
#include <mach/impd1.h>
#include <asm/sizes.h>
@@ -36,45 +35,6 @@ MODULE_PARM_DESC(lmid, "logic module stack position");
struct impd1_module {
void __iomem *base;
- struct clk vcos[2];
- struct clk_lookup *clks[3];
-};
-
-static const struct icst_params impd1_vco_params = {
- .ref = 24000000, /* 24 MHz */
- .vco_max = ICST525_VCO_MAX_3V,
- .vco_min = ICST525_VCO_MIN,
- .vd_min = 12,
- .vd_max = 519,
- .rd_min = 3,
- .rd_max = 120,
- .s2div = icst525_s2div,
- .idx2s = icst525_idx2s,
-};
-
-static void impd1_setvco(struct clk *clk, struct icst_vco vco)
-{
- struct impd1_module *impd1 = clk->data;
- u32 val = vco.v | (vco.r << 9) | (vco.s << 16);
-
- writel(0xa05f, impd1->base + IMPD1_LOCK);
- writel(val, clk->vcoreg);
- writel(0, impd1->base + IMPD1_LOCK);
-
-#ifdef DEBUG
- vco.v = val & 0x1ff;
- vco.r = (val >> 9) & 0x7f;
- vco.s = (val >> 16) & 7;
-
- pr_debug("IM-PD1: VCO%d clock is %ld Hz\n",
- vconr, icst525_hz(&impd1_vco_params, vco));
-#endif
-}
-
-static const struct clk_ops impd1_clk_ops = {
- .round = icst_clk_round,
- .set = icst_clk_set,
- .setvco = impd1_setvco,
};
void impd1_tweak_control(struct device *dev, u32 mask, u32 val)
@@ -344,10 +304,6 @@ static struct impd1_device impd1_devs[] = {
}
};
-static struct clk fixed_14745600 = {
- .rate = 14745600,
-};
-
static int impd1_probe(struct lm_device *dev)
{
struct impd1_module *impd1;
@@ -376,23 +332,7 @@ static int impd1_probe(struct lm_device *dev)
printk("IM-PD1 found at 0x%08lx\n",
(unsigned long)dev->resource.start);
- for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) {
- impd1->vcos[i].ops = &impd1_clk_ops,
- impd1->vcos[i].owner = THIS_MODULE,
- impd1->vcos[i].params = &impd1_vco_params,
- impd1->vcos[i].data = impd1;
- }
- impd1->vcos[0].vcoreg = impd1->base + IMPD1_OSC1;
- impd1->vcos[1].vcoreg = impd1->base + IMPD1_OSC2;
-
- impd1->clks[0] = clkdev_alloc(&impd1->vcos[0], NULL, "lm%x:01000",
- dev->id);
- impd1->clks[1] = clkdev_alloc(&fixed_14745600, NULL, "lm%x:00100",
- dev->id);
- impd1->clks[2] = clkdev_alloc(&fixed_14745600, NULL, "lm%x:00200",
- dev->id);
- for (i = 0; i < ARRAY_SIZE(impd1->clks); i++)
- clkdev_add(impd1->clks[i]);
+ integrator_impd1_clk_init(impd1->base, dev->id);
for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) {
struct impd1_device *idev = impd1_devs + i;
@@ -402,9 +342,10 @@ static int impd1_probe(struct lm_device *dev)
pc_base = dev->resource.start + idev->offset;
snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
- d = amba_ahb_device_add(&dev->dev, devname, pc_base, SZ_4K,
- dev->irq, dev->irq,
- idev->platform_data, idev->id);
+ d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K,
+ dev->irq, dev->irq,
+ idev->platform_data, idev->id,
+ &dev->resource);
if (IS_ERR(d)) {
dev_err(&dev->dev, "unable to register device: %ld\n", PTR_ERR(d));
continue;
@@ -431,12 +372,9 @@ static int impd1_remove_one(struct device *dev, void *data)
static void impd1_remove(struct lm_device *dev)
{
struct impd1_module *impd1 = lm_get_drvdata(dev);
- int i;
device_for_each_child(&dev->dev, NULL, impd1_remove_one);
-
- for (i = 0; i < ARRAY_SIZE(impd1->clks); i++)
- clkdev_drop(impd1->clks[i]);
+ integrator_impd1_clk_exit(dev->id);
lm_set_drvdata(dev, NULL);
diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h
index 7371018455d2..eff0adad9ae3 100644
--- a/arch/arm/mach-integrator/include/mach/irqs.h
+++ b/arch/arm/mach-integrator/include/mach/irqs.h
@@ -19,64 +19,63 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-/*
- * Interrupt numbers
+/*
+ * Interrupt numbers, all of the above are just static reservations
+ * used so they can be encoded into device resources. They will finally
+ * be done away with when switching to device tree.
*/
-#define IRQ_PIC_START 1
-#define IRQ_SOFTINT 1
-#define IRQ_UARTINT0 2
-#define IRQ_UARTINT1 3
-#define IRQ_KMIINT0 4
-#define IRQ_KMIINT1 5
-#define IRQ_TIMERINT0 6
-#define IRQ_TIMERINT1 7
-#define IRQ_TIMERINT2 8
-#define IRQ_RTCINT 9
-#define IRQ_AP_EXPINT0 10
-#define IRQ_AP_EXPINT1 11
-#define IRQ_AP_EXPINT2 12
-#define IRQ_AP_EXPINT3 13
-#define IRQ_AP_PCIINT0 14
-#define IRQ_AP_PCIINT1 15
-#define IRQ_AP_PCIINT2 16
-#define IRQ_AP_PCIINT3 17
-#define IRQ_AP_V3INT 18
-#define IRQ_AP_CPINT0 19
-#define IRQ_AP_CPINT1 20
-#define IRQ_AP_LBUSTIMEOUT 21
-#define IRQ_AP_APCINT 22
-#define IRQ_CP_CLCDCINT 23
-#define IRQ_CP_MMCIINT0 24
-#define IRQ_CP_MMCIINT1 25
-#define IRQ_CP_AACIINT 26
-#define IRQ_CP_CPPLDINT 27
-#define IRQ_CP_ETHINT 28
-#define IRQ_CP_TSPENINT 29
-#define IRQ_PIC_END 29
+#define IRQ_PIC_START 64
+#define IRQ_SOFTINT (IRQ_PIC_START+0)
+#define IRQ_UARTINT0 (IRQ_PIC_START+1)
+#define IRQ_UARTINT1 (IRQ_PIC_START+2)
+#define IRQ_KMIINT0 (IRQ_PIC_START+3)
+#define IRQ_KMIINT1 (IRQ_PIC_START+4)
+#define IRQ_TIMERINT0 (IRQ_PIC_START+5)
+#define IRQ_TIMERINT1 (IRQ_PIC_START+6)
+#define IRQ_TIMERINT2 (IRQ_PIC_START+7)
+#define IRQ_RTCINT (IRQ_PIC_START+8)
+#define IRQ_AP_EXPINT0 (IRQ_PIC_START+9)
+#define IRQ_AP_EXPINT1 (IRQ_PIC_START+10)
+#define IRQ_AP_EXPINT2 (IRQ_PIC_START+11)
+#define IRQ_AP_EXPINT3 (IRQ_PIC_START+12)
+#define IRQ_AP_PCIINT0 (IRQ_PIC_START+13)
+#define IRQ_AP_PCIINT1 (IRQ_PIC_START+14)
+#define IRQ_AP_PCIINT2 (IRQ_PIC_START+15)
+#define IRQ_AP_PCIINT3 (IRQ_PIC_START+16)
+#define IRQ_AP_V3INT (IRQ_PIC_START+17)
+#define IRQ_AP_CPINT0 (IRQ_PIC_START+18)
+#define IRQ_AP_CPINT1 (IRQ_PIC_START+19)
+#define IRQ_AP_LBUSTIMEOUT (IRQ_PIC_START+20)
+#define IRQ_AP_APCINT (IRQ_PIC_START+21)
+#define IRQ_CP_CLCDCINT (IRQ_PIC_START+22)
+#define IRQ_CP_MMCIINT0 (IRQ_PIC_START+23)
+#define IRQ_CP_MMCIINT1 (IRQ_PIC_START+24)
+#define IRQ_CP_AACIINT (IRQ_PIC_START+25)
+#define IRQ_CP_CPPLDINT (IRQ_PIC_START+26)
+#define IRQ_CP_ETHINT (IRQ_PIC_START+27)
+#define IRQ_CP_TSPENINT (IRQ_PIC_START+28)
+#define IRQ_PIC_END (IRQ_PIC_START+28)
-#define IRQ_CIC_START 32
-#define IRQ_CM_SOFTINT 32
-#define IRQ_CM_COMMRX 33
-#define IRQ_CM_COMMTX 34
-#define IRQ_CIC_END 34
+#define IRQ_CIC_START (IRQ_PIC_END+1)
+#define IRQ_CM_SOFTINT (IRQ_CIC_START+0)
+#define IRQ_CM_COMMRX (IRQ_CIC_START+1)
+#define IRQ_CM_COMMTX (IRQ_CIC_START+2)
+#define IRQ_CIC_END (IRQ_CIC_START+2)
/*
* IntegratorCP only
*/
-#define IRQ_SIC_START 35
-#define IRQ_SIC_CP_SOFTINT 35
-#define IRQ_SIC_CP_RI0 36
-#define IRQ_SIC_CP_RI1 37
-#define IRQ_SIC_CP_CARDIN 38
-#define IRQ_SIC_CP_LMINT0 39
-#define IRQ_SIC_CP_LMINT1 40
-#define IRQ_SIC_CP_LMINT2 41
-#define IRQ_SIC_CP_LMINT3 42
-#define IRQ_SIC_CP_LMINT4 43
-#define IRQ_SIC_CP_LMINT5 44
-#define IRQ_SIC_CP_LMINT6 45
-#define IRQ_SIC_CP_LMINT7 46
-#define IRQ_SIC_END 46
-
-#define NR_IRQS_INTEGRATOR_AP 34
-#define NR_IRQS_INTEGRATOR_CP 47
+#define IRQ_SIC_START (IRQ_CIC_END+1)
+#define IRQ_SIC_CP_SOFTINT (IRQ_SIC_START+0)
+#define IRQ_SIC_CP_RI0 (IRQ_SIC_START+1)
+#define IRQ_SIC_CP_RI1 (IRQ_SIC_START+2)
+#define IRQ_SIC_CP_CARDIN (IRQ_SIC_START+3)
+#define IRQ_SIC_CP_LMINT0 (IRQ_SIC_START+4)
+#define IRQ_SIC_CP_LMINT1 (IRQ_SIC_START+5)
+#define IRQ_SIC_CP_LMINT2 (IRQ_SIC_START+6)
+#define IRQ_SIC_CP_LMINT3 (IRQ_SIC_START+7)
+#define IRQ_SIC_CP_LMINT4 (IRQ_SIC_START+8)
+#define IRQ_SIC_CP_LMINT5 (IRQ_SIC_START+9)
+#define IRQ_SIC_CP_LMINT6 (IRQ_SIC_START+10)
+#define IRQ_SIC_CP_LMINT7 (IRQ_SIC_START+11)
+#define IRQ_SIC_END (IRQ_SIC_START+11)
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index efeac5d0bc9e..be5859efe10e 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -190,7 +190,6 @@
#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
#define INTEGRATOR_SC_DEC_OFFSET 0x10
#define INTEGRATOR_SC_ARB_OFFSET 0x14
-#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
#define INTEGRATOR_SC_BASE 0x11000000
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index e6617c134faf..11e2a4145807 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -31,12 +31,16 @@
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/irqchip/versatile-fpga.h>
#include <linux/mtd/physmap.h>
#include <linux/clk.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
+#include <linux/stat.h>
+#include <linux/sys_soc.h>
+#include <linux/termios.h>
#include <video/vga.h>
#include <mach/hardware.h>
@@ -56,11 +60,12 @@
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
-#include <plat/fpga-irq.h>
-
#include "common.h"
-/*
+/* Base address to the AP system controller */
+void __iomem *ap_syscon_base;
+
+/*
* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
* is the (PA >> 12).
*
@@ -68,7 +73,6 @@
* just for now).
*/
#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
-#define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
@@ -97,11 +101,6 @@ static struct map_desc ap_io_desc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE
}, {
- .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
- .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE
- }, {
.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
.length = SZ_4K,
@@ -122,11 +121,6 @@ static struct map_desc ap_io_desc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE
}, {
- .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
- .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE
- }, {
.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
.length = SZ_4K,
@@ -201,8 +195,6 @@ device_initcall(irq_syscore_init);
/*
* Flash handling.
*/
-#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
-#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
@@ -210,7 +202,8 @@ static int ap_flash_init(struct platform_device *dev)
{
u32 tmp;
- writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
+ writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
+ ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
writel(tmp, EBI_CSR1);
@@ -227,7 +220,8 @@ static void ap_flash_exit(struct platform_device *dev)
{
u32 tmp;
- writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
+ writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
+ ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
writel(tmp, EBI_CSR1);
@@ -241,9 +235,12 @@ static void ap_flash_exit(struct platform_device *dev)
static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{
- void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
-
- writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
+ if (on)
+ writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
+ ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
+ else
+ writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
+ ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
}
static struct physmap_flash_data ap_flash_data = {
@@ -254,6 +251,45 @@ static struct physmap_flash_data ap_flash_data = {
};
/*
+ * For the PL010 found in the Integrator/AP some of the UART control is
+ * implemented in the system controller and accessed using a callback
+ * from the driver.
+ */
+static void integrator_uart_set_mctrl(struct amba_device *dev,
+ void __iomem *base, unsigned int mctrl)
+{
+ unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
+ u32 phybase = dev->res.start;
+
+ if (phybase == INTEGRATOR_UART0_BASE) {
+ /* UART0 */
+ rts_mask = 1 << 4;
+ dtr_mask = 1 << 5;
+ } else {
+ /* UART1 */
+ rts_mask = 1 << 6;
+ dtr_mask = 1 << 7;
+ }
+
+ if (mctrl & TIOCM_RTS)
+ ctrlc |= rts_mask;
+ else
+ ctrls |= rts_mask;
+
+ if (mctrl & TIOCM_DTR)
+ ctrlc |= dtr_mask;
+ else
+ ctrls |= dtr_mask;
+
+ __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
+ __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
+}
+
+struct amba_pl010_data ap_uart_data = {
+ .set_mctrl = integrator_uart_set_mctrl,
+};
+
+/*
* Where is the timer (VA)?
*/
#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
@@ -450,9 +486,9 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
"rtc", NULL),
OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
- "uart0", &integrator_uart_data),
+ "uart0", &ap_uart_data),
OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
- "uart1", &integrator_uart_data),
+ "uart1", &ap_uart_data),
OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
"kmi0", NULL),
OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
@@ -465,12 +501,60 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
static void __init ap_init_of(void)
{
unsigned long sc_dec;
+ struct device_node *root;
+ struct device_node *syscon;
+ struct device *parent;
+ struct soc_device *soc_dev;
+ struct soc_device_attribute *soc_dev_attr;
+ u32 ap_sc_id;
+ int err;
int i;
- of_platform_populate(NULL, of_default_bus_match_table,
- ap_auxdata_lookup, NULL);
+ /* Here we create an SoC device for the root node */
+ root = of_find_node_by_path("/");
+ if (!root)
+ return;
+ syscon = of_find_node_by_path("/syscon");
+ if (!syscon)
+ return;
+
+ ap_syscon_base = of_iomap(syscon, 0);
+ if (!ap_syscon_base)
+ return;
+
+ ap_sc_id = readl(ap_syscon_base);
+
+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ return;
+
+ err = of_property_read_string(root, "compatible",
+ &soc_dev_attr->soc_id);
+ if (err)
+ return;
+ err = of_property_read_string(root, "model", &soc_dev_attr->machine);
+ if (err)
+ return;
+ soc_dev_attr->family = "Integrator";
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
+ 'A' + (ap_sc_id & 0x0f));
+
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR_OR_NULL(soc_dev)) {
+ kfree(soc_dev_attr->revision);
+ kfree(soc_dev_attr);
+ return;
+ }
+
+ parent = soc_device_to_device(soc_dev);
+
+ if (!IS_ERR_OR_NULL(parent))
+ integrator_init_sysfs(parent, ap_sc_id);
- sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+ of_platform_populate(root, of_default_bus_match_table,
+ ap_auxdata_lookup, parent);
+
+ sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
for (i = 0; i < 4; i++) {
struct lm_device *lmdev;
@@ -499,7 +583,6 @@ static const char * ap_dt_board_compat[] = {
DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
.reserve = integrator_reserve,
.map_io = ap_map_io,
- .nr_irqs = NR_IRQS_INTEGRATOR_AP,
.init_early = ap_init_early,
.init_irq = ap_init_irq_of,
.handle_irq = fpga_handle_irq,
@@ -514,6 +597,27 @@ MACHINE_END
#ifdef CONFIG_ATAGS
/*
+ * For the ATAG boot some static mappings are needed. This will
+ * go away with the ATAG support down the road.
+ */
+
+static struct map_desc ap_io_desc_atag[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
+ .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ },
+};
+
+static void __init ap_map_io_atag(void)
+{
+ iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
+ ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
+ ap_map_io();
+}
+
+/*
* This is where non-devicetree initialization code is collected and stashed
* for eventual deletion.
*/
@@ -581,7 +685,7 @@ static void __init ap_init(void)
platform_device_register(&cfi_flash_device);
- sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+ sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
for (i = 0; i < 4; i++) {
struct lm_device *lmdev;
@@ -608,8 +712,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.atag_offset = 0x100,
.reserve = integrator_reserve,
- .map_io = ap_map_io,
- .nr_irqs = NR_IRQS_INTEGRATOR_AP,
+ .map_io = ap_map_io_atag,
.init_early = ap_init_early,
.init_irq = ap_init_irq,
.handle_irq = fpga_handle_irq,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 5b08e8e4cc83..7322838c0447 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -20,12 +20,14 @@
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
+#include <linux/irqchip/versatile-fpga.h>
#include <linux/gfp.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
+#include <linux/sys_soc.h>
#include <mach/hardware.h>
#include <mach/platform.h>
@@ -46,16 +48,17 @@
#include <asm/hardware/timer-sp.h>
#include <plat/clcd.h>
-#include <plat/fpga-irq.h>
#include <plat/sched_clock.h>
#include "common.h"
+/* Base address to the CP controller */
+static void __iomem *intcp_con_base;
+
#define INTCP_PA_FLASH_BASE 0x24000000
#define INTCP_PA_CLCD_BASE 0xc0000000
-#define INTCP_VA_CTRL_BASE __io_address(INTEGRATOR_CP_CTL_BASE)
#define INTCP_FLASHPROG 0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
@@ -82,11 +85,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE
}, {
- .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
- .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE
- }, {
.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
.length = SZ_4K,
@@ -107,11 +105,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE
}, {
- .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
- .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE
- }, {
.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
.length = SZ_4K,
@@ -126,11 +119,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
.length = SZ_4K,
.type = MT_DEVICE
- }, {
- .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
- .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE
}
};
@@ -146,9 +134,9 @@ static int intcp_flash_init(struct platform_device *dev)
{
u32 val;
- val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+ val = readl(intcp_con_base + INTCP_FLASHPROG);
val |= CINTEGRATOR_FLASHPROG_FLWREN;
- writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+ writel(val, intcp_con_base + INTCP_FLASHPROG);
return 0;
}
@@ -157,21 +145,21 @@ static void intcp_flash_exit(struct platform_device *dev)
{
u32 val;
- val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+ val = readl(intcp_con_base + INTCP_FLASHPROG);
val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
- writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+ writel(val, intcp_con_base + INTCP_FLASHPROG);
}
static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
{
u32 val;
- val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+ val = readl(intcp_con_base + INTCP_FLASHPROG);
if (on)
val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
else
val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
- writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+ writel(val, intcp_con_base + INTCP_FLASHPROG);
}
static struct physmap_flash_data intcp_flash_data = {
@@ -190,7 +178,7 @@ static struct physmap_flash_data intcp_flash_data = {
static unsigned int mmc_status(struct device *dev)
{
unsigned int status = readl(__io_address(0xca000000 + 4));
- writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8));
+ writel(8, intcp_con_base + 8);
return status & 8;
}
@@ -318,9 +306,9 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
"rtc", NULL),
OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
- "uart0", &integrator_uart_data),
+ "uart0", NULL),
OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
- "uart1", &integrator_uart_data),
+ "uart1", NULL),
OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
"kmi0", NULL),
OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
@@ -338,8 +326,57 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
static void __init intcp_init_of(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- intcp_auxdata_lookup, NULL);
+ struct device_node *root;
+ struct device_node *cpcon;
+ struct device *parent;
+ struct soc_device *soc_dev;
+ struct soc_device_attribute *soc_dev_attr;
+ u32 intcp_sc_id;
+ int err;
+
+ /* Here we create an SoC device for the root node */
+ root = of_find_node_by_path("/");
+ if (!root)
+ return;
+ cpcon = of_find_node_by_path("/cpcon");
+ if (!cpcon)
+ return;
+
+ intcp_con_base = of_iomap(cpcon, 0);
+ if (!intcp_con_base)
+ return;
+
+ intcp_sc_id = readl(intcp_con_base);
+
+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ return;
+
+ err = of_property_read_string(root, "compatible",
+ &soc_dev_attr->soc_id);
+ if (err)
+ return;
+ err = of_property_read_string(root, "model", &soc_dev_attr->machine);
+ if (err)
+ return;
+ soc_dev_attr->family = "Integrator";
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
+ 'A' + (intcp_sc_id & 0x0f));
+
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR_OR_NULL(soc_dev)) {
+ kfree(soc_dev_attr->revision);
+ kfree(soc_dev_attr);
+ return;
+ }
+
+ parent = soc_device_to_device(soc_dev);
+
+ if (!IS_ERR_OR_NULL(parent))
+ integrator_init_sysfs(parent, intcp_sc_id);
+
+ of_platform_populate(root, of_default_bus_match_table,
+ intcp_auxdata_lookup, parent);
}
static const char * intcp_dt_board_compat[] = {
@@ -350,7 +387,6 @@ static const char * intcp_dt_board_compat[] = {
DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
.reserve = integrator_reserve,
.map_io = intcp_map_io,
- .nr_irqs = NR_IRQS_INTEGRATOR_CP,
.init_early = intcp_init_early,
.init_irq = intcp_init_irq_of,
.handle_irq = fpga_handle_irq,
@@ -365,6 +401,28 @@ MACHINE_END
#ifdef CONFIG_ATAGS
/*
+ * For the ATAG boot some static mappings are needed. This will
+ * go away with the ATAG support down the road.
+ */
+
+static struct map_desc intcp_io_desc_atag[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
+ .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ },
+};
+
+static void __init intcp_map_io_atag(void)
+{
+ iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag));
+ intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE);
+ intcp_map_io();
+}
+
+
+/*
* This is where non-devicetree initialization code is collected and stashed
* for eventual deletion.
*/
@@ -423,7 +481,7 @@ static void __init intcp_init_irq(void)
u32 pic_mask, cic_mask, sic_mask;
/* These masks are for the HW IRQ registers */
- pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
+ pic_mask = ~((~0u) << (11 - 0));
pic_mask |= (~((~0u) << (29 - 22))) << 22;
cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
@@ -503,8 +561,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.atag_offset = 0x100,
.reserve = integrator_reserve,
- .map_io = intcp_map_io,
- .nr_irqs = NR_IRQS_INTEGRATOR_CP,
+ .map_io = intcp_map_io_atag,
.init_early = intcp_init_early,
.init_irq = intcp_init_irq,
.handle_irq = fpga_handle_irq,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index bbeca59df66b..be50e795536d 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -191,12 +191,9 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus,
/*
* Trap out illegal values
*/
- if (offset > 255)
- BUG();
- if (busnr > 255)
- BUG();
- if (devfn > 255)
- BUG();
+ BUG_ON(offset > 255);
+ BUG_ON(busnr > 255);
+ BUG_ON(devfn > 255);
if (busnr == 0) {
int slot = PCI_SLOT(devfn);
@@ -388,9 +385,10 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
* means I can't get additional information on the reason for the pm2fb
* problems. I suppose I'll just have to mind-meld with the machine. ;)
*/
-#define SC_PCI __io_address(INTEGRATOR_SC_PCIENABLE)
-#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20)
-#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24)
+static void __iomem *ap_syscon_base;
+#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
+#define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
+#define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
static int
v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
@@ -401,13 +399,13 @@ v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
char buf[128];
sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
- addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
+ addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
v3_readb(V3_LB_ISTAT));
printk(KERN_DEBUG "%s", buf);
#endif
v3_writeb(V3_LB_ISTAT, 0);
- __raw_writel(3, SC_PCI);
+ __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
/*
* If the instruction being executed was a read,
@@ -449,15 +447,15 @@ static irqreturn_t v3_irq(int dummy, void *devid)
sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
"ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
- __raw_readl(SC_LBFADDR),
- __raw_readl(SC_LBFCODE) & 255,
+ __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
+ __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
v3_readb(V3_LB_ISTAT));
printascii(buf);
#endif
v3_writew(V3_PCI_STAT, 0xf000);
v3_writeb(V3_LB_ISTAT, 0);
- __raw_writel(3, SC_PCI);
+ __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
#ifdef CONFIG_DEBUG_LL
/*
@@ -480,6 +478,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
if (nr == 0) {
sys->mem_offset = PHYS_PCI_MEM_BASE;
ret = pci_v3_setup_resources(sys);
+ /* Remap the Integrator system controller */
+ ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
+ if (!ap_syscon_base)
+ return -EINVAL;
}
return ret;
@@ -568,7 +570,7 @@ void __init pci_v3_preinit(void)
v3_writeb(V3_LB_ISTAT, 0);
v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
v3_writeb(V3_LB_IMASK, 0x28);
- __raw_writel(3, SC_PCI);
+ __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
/*
* Grab the PCI error interrupt.
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.