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-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h42
1 files changed, 32 insertions, 10 deletions
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a15cf0ee22bd..93fc2ec95e76 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -16,36 +16,48 @@
* Marvell Kirkwood address maps.
*
* phys
- * e0000000 PCIe Memory space
+ * e0000000 PCIe #0 Memory space
+ * e8000000 PCIe #1 Memory space
* f1000000 on-chip peripheral registers
- * f2000000 PCIe I/O space
- * f3000000 NAND controller address window
- * f4000000 Security Accelerator SRAM
+ * f2000000 PCIe #0 I/O space
+ * f3000000 PCIe #1 I/O space
+ * f4000000 NAND controller address window
+ * f5000000 Security Accelerator SRAM
*
* virt phys size
- * fee00000 f1000000 1M on-chip peripheral registers
- * fef00000 f2000000 1M PCIe I/O space
+ * fed00000 f1000000 1M on-chip peripheral registers
+ * fee00000 f2000000 1M PCIe #0 I/O space
+ * fef00000 f3000000 1M PCIe #1 I/O space
*/
-#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000
+#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000
#define KIRKWOOD_SRAM_SIZE SZ_2K
-#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000
+#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000
#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
+
#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000
#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000
+#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
#define KIRKWOOD_REGS_SIZE SZ_1M
#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M
+
/*
* Register Map
*/
@@ -72,6 +84,9 @@
#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
+#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70)
+#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04)
#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
@@ -96,6 +111,9 @@
#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
+#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000)
+#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000)
+
/*
* Supported devices and revisions.
*/
@@ -107,8 +125,12 @@
#define MV88F6192_DEV_ID 0x6192
#define MV88F6192_REV_Z0 0
#define MV88F6192_REV_A0 2
+#define MV88F6192_REV_A1 3
#define MV88F6180_DEV_ID 0x6180
#define MV88F6180_REV_A0 2
+#define MV88F6180_REV_A1 3
+#define MV88F6282_DEV_ID 0x6282
+#define MV88F6282_REV_A0 0
#endif