diff options
Diffstat (limited to 'arch/arm/mach-ks8695/include/mach')
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/entry-macro.S | 47 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/gpio-ks8695.h | 36 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/hardware.h | 42 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/irqs.h | 51 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/memory.h | 51 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-gpio.h | 55 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-irq.h | 41 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-misc.h | 97 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-switch.h | 66 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/regs-uart.h | 89 | ||||
| -rw-r--r-- | arch/arm/mach-ks8695/include/mach/uncompress.h | 33 |
11 files changed, 0 insertions, 608 deletions
diff --git a/arch/arm/mach-ks8695/include/mach/entry-macro.S b/arch/arm/mach-ks8695/include/mach/entry-macro.S deleted file mode 100644 index 7ff812cb010b..000000000000 --- a/arch/arm/mach-ks8695/include/mach/entry-macro.S +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/entry-macro.S - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * Low-level IRQ helper macros for KS8695 - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -#include <mach/hardware.h> -#include <mach/regs-irq.h> - - .macro get_irqnr_preamble, base, tmp - ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register - - teq \irqstat, #0 - beq 1001f - - mov \irqnr, #0 - - tst \irqstat, #0xff - moveq \irqstat, \irqstat, lsr #8 - addeq \irqnr, \irqnr, #8 - tsteq \irqstat, #0xff - moveq \irqstat, \irqstat, lsr #8 - addeq \irqnr, \irqnr, #8 - tsteq \irqstat, #0xff - moveq \irqstat, \irqstat, lsr #8 - addeq \irqnr, \irqnr, #8 - tst \irqstat, #0x0f - moveq \irqstat, \irqstat, lsr #4 - addeq \irqnr, \irqnr, #4 - tst \irqstat, #0x03 - moveq \irqstat, \irqstat, lsr #2 - addeq \irqnr, \irqnr, #2 - tst \irqstat, #0x01 - addseq \irqnr, \irqnr, #1 -1001: - .endm diff --git a/arch/arm/mach-ks8695/include/mach/gpio-ks8695.h b/arch/arm/mach-ks8695/include/mach/gpio-ks8695.h deleted file mode 100644 index 600115f48fb3..000000000000 --- a/arch/arm/mach-ks8695/include/mach/gpio-ks8695.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2006 Andrew Victor - */ - -#ifndef __MACH_KS8659_GPIO_H -#define __MACH_KS8659_GPIO_H - -#include <linux/kernel.h> - -#define KS8695_GPIO_0 0 -#define KS8695_GPIO_1 1 -#define KS8695_GPIO_2 2 -#define KS8695_GPIO_3 3 -#define KS8695_GPIO_4 4 -#define KS8695_GPIO_5 5 -#define KS8695_GPIO_6 6 -#define KS8695_GPIO_7 7 -#define KS8695_GPIO_8 8 -#define KS8695_GPIO_9 9 -#define KS8695_GPIO_10 10 -#define KS8695_GPIO_11 11 -#define KS8695_GPIO_12 12 -#define KS8695_GPIO_13 13 -#define KS8695_GPIO_14 14 -#define KS8695_GPIO_15 15 - -/* - * Configure GPIO pin as external interrupt source. - */ -extern int ks8695_gpio_interrupt(unsigned int pin, unsigned int type); - -/* Register the GPIOs */ -extern void ks8695_register_gpios(void); - -#endif /* __MACH_KS8659_GPIO_H */ diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h deleted file mode 100644 index 0fb889be8112..000000000000 --- a/arch/arm/mach-ks8695/include/mach/hardware.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ks8695/include/mach/hardware.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - Memory Map definitions -*/ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <linux/sizes.h> - -/* - * Clocks are derived from MCLK, which is 25MHz - */ -#define KS8695_CLOCK_RATE 25000000 - -/* - * Physical RAM address. - */ -#define KS8695_SDRAM_PA 0x00000000 - - -/* - * We map an entire MiB with the System Configuration Registers in even - * though only 64KiB is needed. This makes it easier for use with the - * head debug code as the initial MMU setup only deals in L1 sections. - */ -#define KS8695_IO_PA 0x03F00000 -#define KS8695_IO_VA IOMEM(0xF0000000) -#define KS8695_IO_SIZE SZ_1M - -#define KS8695_PCIMEM_PA 0x60000000 -#define KS8695_PCIMEM_SIZE SZ_512M - -#define KS8695_PCIIO_PA 0x80000000 -#define KS8695_PCIIO_SIZE SZ_64K - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/irqs.h b/arch/arm/mach-ks8695/include/mach/irqs.h deleted file mode 100644 index 0cbb30672427..000000000000 --- a/arch/arm/mach-ks8695/include/mach/irqs.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ks8695/include/mach/irqs.h - * - * Copyright (C) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - - -#define NR_IRQS 32 - -/* - * IRQ definitions - */ -#define KS8695_IRQ_COMM_RX 0 -#define KS8695_IRQ_COMM_TX 1 -#define KS8695_IRQ_EXTERN0 2 -#define KS8695_IRQ_EXTERN1 3 -#define KS8695_IRQ_EXTERN2 4 -#define KS8695_IRQ_EXTERN3 5 -#define KS8695_IRQ_TIMER0 6 -#define KS8695_IRQ_TIMER1 7 -#define KS8695_IRQ_UART_TX 8 -#define KS8695_IRQ_UART_RX 9 -#define KS8695_IRQ_UART_LINE_STATUS 10 -#define KS8695_IRQ_UART_MODEM_STATUS 11 -#define KS8695_IRQ_LAN_RX_STOP 12 -#define KS8695_IRQ_LAN_TX_STOP 13 -#define KS8695_IRQ_LAN_RX_BUF 14 -#define KS8695_IRQ_LAN_TX_BUF 15 -#define KS8695_IRQ_LAN_RX_STATUS 16 -#define KS8695_IRQ_LAN_TX_STATUS 17 -#define KS8695_IRQ_HPNA_RX_STOP 18 -#define KS8695_IRQ_HPNA_TX_STOP 19 -#define KS8695_IRQ_HPNA_RX_BUF 20 -#define KS8695_IRQ_HPNA_TX_BUF 21 -#define KS8695_IRQ_HPNA_RX_STATUS 22 -#define KS8695_IRQ_HPNA_TX_STATUS 23 -#define KS8695_IRQ_BUS_ERROR 24 -#define KS8695_IRQ_WAN_RX_STOP 25 -#define KS8695_IRQ_WAN_TX_STOP 26 -#define KS8695_IRQ_WAN_RX_BUF 27 -#define KS8695_IRQ_WAN_TX_BUF 28 -#define KS8695_IRQ_WAN_RX_STATUS 29 -#define KS8695_IRQ_WAN_TX_STATUS 30 -#define KS8695_IRQ_WAN_LINK 31 - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h deleted file mode 100644 index ab0d27fa8969..000000000000 --- a/arch/arm/mach-ks8695/include/mach/memory.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/memory.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 Memory definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include <mach/hardware.h> - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_PCI - -/* PCI mappings */ -#define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA) -#define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET) - -/* Platform-bus mapping */ -extern struct bus_type platform_bus_type; -#define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type) -#define __arch_dma_to_virt(dev, x) ({ (void *) (is_lbus_device(dev) ? \ - __phys_to_virt(x) : __bus_to_virt(x)); }) -#define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ - (dma_addr_t)__virt_to_phys((unsigned long)x) \ - : (dma_addr_t)__virt_to_bus(x); }) -#define __arch_pfn_to_dma(dev, pfn) \ - ({ dma_addr_t __dma = __pfn_to_phys(pfn); \ - if (!is_lbus_device(dev)) \ - __dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \ - __dma; }) - -#define __arch_dma_to_pfn(dev, x) \ - ({ dma_addr_t __dma = x; \ - if (!is_lbus_device(dev)) \ - __dma += PHYS_OFFSET - KS8695_PCIMEM_PA; \ - __phys_to_pfn(__dma); \ - }) - -#endif - -#endif - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-gpio.h b/arch/arm/mach-ks8695/include/mach/regs-gpio.h deleted file mode 100644 index 90614a7d0548..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-gpio.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-gpio.h - * - * Copyright (C) 2007 Andrew Victor - * - * KS8695 - GPIO control registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_GPIO_H -#define KS8695_GPIO_H - -#define KS8695_GPIO_OFFSET (0xF0000 + 0xE600) -#define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET) -#define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET) - - -#define KS8695_IOPM (0x00) /* I/O Port Mode Register */ -#define KS8695_IOPC (0x04) /* I/O Port Control Register */ -#define KS8695_IOPD (0x08) /* I/O Port Data Register */ - - -/* Port Mode Register */ -#define IOPM(x) (1 << (x)) /* Mode for GPIO Pin x */ - -/* Port Control Register */ -#define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */ -#define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */ -#define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */ -#define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */ -#define IOPC_IOEINT3_MODE(x) ((x) << 12) -#define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */ -#define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */ -#define IOPC_IOEINT2_MODE(x) ((x) << 8) -#define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */ -#define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */ -#define IOPC_IOEINT1_MODE(x) ((x) << 4) -#define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */ -#define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */ -#define IOPC_IOEINT0_MODE(x) ((x) << 0) - - /* Trigger Modes */ -#define IOPC_TM_LOW (0) /* Level Detection (Active Low) */ -#define IOPC_TM_HIGH (1) /* Level Detection (Active High) */ -#define IOPC_TM_RISING (2) /* Rising Edge Detection */ -#define IOPC_TM_FALLING (4) /* Falling Edge Detection */ -#define IOPC_TM_EDGE (6) /* Both Edge Detection */ - -/* Port Data Register */ -#define IOPD(x) (1 << (x)) /* Signal Level of GPIO Pin x */ - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-irq.h b/arch/arm/mach-ks8695/include/mach/regs-irq.h deleted file mode 100644 index 352b7e8704d5..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-irq.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-irq.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - IRQ registers and bit definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_IRQ_H -#define KS8695_IRQ_H - -#define KS8695_IRQ_OFFSET (0xF0000 + 0xE200) -#define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET) -#define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET) - - -/* - * Interrupt Controller registers - */ -#define KS8695_INTMC (0x00) /* Mode Control Register */ -#define KS8695_INTEN (0x04) /* Interrupt Enable Register */ -#define KS8695_INTST (0x08) /* Interrupt Status Register */ -#define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */ -#define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */ -#define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */ -#define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */ -#define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */ -#define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */ -#define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */ -#define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */ -#define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */ -#define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */ -#define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-misc.h b/arch/arm/mach-ks8695/include/mach/regs-misc.h deleted file mode 100644 index 2740c52494a0..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-misc.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-misc.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - Miscellaneous Registers - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_MISC_H -#define KS8695_MISC_H - -#define KS8695_MISC_OFFSET (0xF0000 + 0xEA00) -#define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET) -#define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET) - - -/* - * Miscellaneous registers - */ -#define KS8695_DID (0x00) /* Device ID */ -#define KS8695_RID (0x04) /* Revision ID */ -#define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */ -#define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */ -#define KS8695_WPPM (0x10) /* WAN PHY Power Management */ -#define KS8695_PPS (0x1c) /* PHY PowerSave */ - -/* Device ID Register */ -#define DID_ID (0xffff << 0) /* Device ID */ - -/* Revision ID Register */ -#define RID_SUBID (0xf << 4) /* Sub-Device ID */ -#define RID_REVISION (0xf << 0) /* Revision ID */ - -/* HPNA Miscellaneous Control Register */ -#define HMC_HSS (1 << 1) /* Speed */ -#define HMC_HDS (1 << 0) /* Duplex */ - -/* WAN Miscellaneous Control Register */ -#define WMC_WANC (1 << 30) /* Auto-negotiation complete */ -#define WMC_WANR (1 << 29) /* Auto-negotiation restart */ -#define WMC_WANAP (1 << 28) /* Advertise Pause */ -#define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */ -#define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */ -#define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */ -#define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */ -#define WMC_WLS (1 << 23) /* Link status */ -#define WMC_WDS (1 << 22) /* Duplex status */ -#define WMC_WSS (1 << 21) /* Speed status */ -#define WMC_WLPP (1 << 20) /* Link Partner Pause */ -#define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */ -#define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */ -#define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */ -#define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */ -#define WMC_WAND (1 << 15) /* Auto-negotiation disable */ -#define WMC_WANF100 (1 << 14) /* Force 100 */ -#define WMC_WANFF (1 << 13) /* Force FDX */ -#define WMC_WLED1S (7 << 4) /* LED1 Select */ -#define WLED1S_SPEED (0 << 4) -#define WLED1S_LINK (1 << 4) -#define WLED1S_DUPLEX (2 << 4) -#define WLED1S_COLLISION (3 << 4) -#define WLED1S_ACTIVITY (4 << 4) -#define WLED1S_FDX_COLLISION (5 << 4) -#define WLED1S_LINK_ACTIVITY (6 << 4) -#define WMC_WLED0S (7 << 0) /* LED0 Select */ -#define WLED0S_SPEED (0 << 0) -#define WLED0S_LINK (1 << 0) -#define WLED0S_DUPLEX (2 << 0) -#define WLED0S_COLLISION (3 << 0) -#define WLED0S_ACTIVITY (4 << 0) -#define WLED0S_FDX_COLLISION (5 << 0) -#define WLED0S_LINK_ACTIVITY (6 << 0) - -/* WAN PHY Power Management Register */ -#define WPPM_WLPBK (1 << 14) /* Local Loopback */ -#define WPPM_WRLPKB (1 << 13) /* Remove Loopback */ -#define WPPM_WPI (1 << 12) /* PHY isolate */ -#define WPPM_WFL (1 << 10) /* Force link */ -#define WPPM_MDIXS (1 << 9) /* MDIX Status */ -#define WPPM_FEF (1 << 8) /* Far End Fault */ -#define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */ -#define WPPM_TXDIS (1 << 6) /* Disable transmitter */ -#define WPPM_DFEF (1 << 5) /* Disable Far End Fault */ -#define WPPM_PD (1 << 4) /* Power Down */ -#define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */ -#define WPPM_FMDX (1 << 2) /* Force MDIX */ -#define WPPM_LPBK (1 << 1) /* MAX Loopback */ - -/* PHY Power Save Register */ -#define PPS_PPSM (1 << 0) /* PHY Power Save Mode */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-switch.h b/arch/arm/mach-ks8695/include/mach/regs-switch.h deleted file mode 100644 index 97e8acb1cf6c..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-switch.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-switch.h - * - * Copyright (C) 2006 Andrew Victor - * - * KS8695 - Switch Registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_SWITCH_H -#define KS8695_SWITCH_H - -#define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800) -#define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET) -#define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET) - - -/* - * Switch registers - */ -#define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */ -#define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */ -#define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */ - -#define KS8695_SEPXCZ(x,z) (0x0c + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */ - -#define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */ -#define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */ -#define KS8695_SEIAC (0x50) /* Indirect Access Control */ -#define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */ -#define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */ -#define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */ -#define KS8695_SEAFC (0x60) /* Advance Feature Control */ -#define KS8695_SEDSCPH (0x64) /* TOS Priority High */ -#define KS8695_SEDSCPL (0x68) /* TOS Priority Low */ -#define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */ -#define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */ -#define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */ -#define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */ - - -/* Switch Engine Control 0 */ -#define SEC0_LLED1S (7 << 25) /* LED1 Select */ -#define LLED1S_SPEED (0 << 25) -#define LLED1S_LINK (1 << 25) -#define LLED1S_DUPLEX (2 << 25) -#define LLED1S_COLLISION (3 << 25) -#define LLED1S_ACTIVITY (4 << 25) -#define LLED1S_FDX_COLLISION (5 << 25) -#define LLED1S_LINK_ACTIVITY (6 << 25) -#define SEC0_LLED0S (7 << 22) /* LED0 Select */ -#define LLED0S_SPEED (0 << 22) -#define LLED0S_LINK (1 << 22) -#define LLED0S_DUPLEX (2 << 22) -#define LLED0S_COLLISION (3 << 22) -#define LLED0S_ACTIVITY (4 << 22) -#define LLED0S_FDX_COLLISION (5 << 22) -#define LLED0S_LINK_ACTIVITY (6 << 22) -#define SEC0_ENABLE (1 << 0) /* Enable Switch */ - - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/regs-uart.h b/arch/arm/mach-ks8695/include/mach/regs-uart.h deleted file mode 100644 index 941a542c5f23..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-uart.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ks8695/include/mach/regs-uart.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - UART register and bit definitions. - */ - -#ifndef KS8695_UART_H -#define KS8695_UART_H - -#define KS8695_UART_OFFSET (0xF0000 + 0xE000) -#define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET) -#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET) - - -/* - * UART registers - */ -#define KS8695_URRB (0x00) /* Receive Buffer Register */ -#define KS8695_URTH (0x04) /* Transmit Holding Register */ -#define KS8695_URFC (0x08) /* FIFO Control Register */ -#define KS8695_URLC (0x0C) /* Line Control Register */ -#define KS8695_URMC (0x10) /* Modem Control Register */ -#define KS8695_URLS (0x14) /* Line Status Register */ -#define KS8695_URMS (0x18) /* Modem Status Register */ -#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */ -#define KS8695_USR (0x20) /* Status Register */ - - -/* FIFO Control Register */ -#define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */ -#define URFC_URFRT_1 (0 << 6) -#define URFC_URFRT_4 (1 << 6) -#define URFC_URFRT_8 (2 << 6) -#define URFC_URFRT_14 (3 << 6) -#define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ -#define URFC_URRFR (1 << 1) /* Receive FIFO Reset */ -#define URFC_URFE (1 << 0) /* FIFO Enable */ - -/* Line Control Register */ -#define URLC_URSBC (1 << 6) /* Set Break Condition */ -#define URLC_PARITY (7 << 3) /* Parity */ -#define URPE_NONE (0 << 3) -#define URPE_ODD (1 << 3) -#define URPE_EVEN (3 << 3) -#define URPE_MARK (5 << 3) -#define URPE_SPACE (7 << 3) -#define URLC_URSB (1 << 2) /* Stop Bits */ -#define URLC_URCL (3 << 0) /* Character Length */ -#define URCL_5 (0 << 0) -#define URCL_6 (1 << 0) -#define URCL_7 (2 << 0) -#define URCL_8 (3 << 0) - -/* Modem Control Register */ -#define URMC_URLB (1 << 4) /* Loop-back mode */ -#define URMC_UROUT2 (1 << 3) /* OUT2 signal */ -#define URMC_UROUT1 (1 << 2) /* OUT1 signal */ -#define URMC_URRTS (1 << 1) /* Request to Send */ -#define URMC_URDTR (1 << 0) /* Data Terminal Ready */ - -/* Line Status Register */ -#define URLS_URRFE (1 << 7) /* Receive FIFO Error */ -#define URLS_URTE (1 << 6) /* Transmit Empty */ -#define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */ -#define URLS_URBI (1 << 4) /* Break Interrupt */ -#define URLS_URFE (1 << 3) /* Framing Error */ -#define URLS_URPE (1 << 2) /* Parity Error */ -#define URLS_URROE (1 << 1) /* Receive Overrun Error */ -#define URLS_URDR (1 << 0) /* Receive Data Ready */ - -/* Modem Status Register */ -#define URMS_URDCD (1 << 7) /* Data Carrier Detect */ -#define URMS_URRI (1 << 6) /* Ring Indicator */ -#define URMS_URDSR (1 << 5) /* Data Set Ready */ -#define URMS_URCTS (1 << 4) /* Clear to Send */ -#define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */ -#define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define URMS_URDDST (1 << 1) /* Delta Data Set Ready */ -#define URMS_URDCTS (1 << 0) /* Delta Clear to Send */ - -/* Status Register */ -#define USR_UTI (1 << 0) /* Timeout Indication */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h deleted file mode 100644 index dc78a29759b5..000000000000 --- a/arch/arm/mach-ks8695/include/mach/uncompress.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ks8695/include/mach/uncompress.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - Kernel uncompressor - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <linux/io.h> -#include <mach/regs-uart.h> - -static inline void putc(char c) -{ - while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) - barrier(); - - __raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH); -} - -static inline void flush(void) -{ - while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) - barrier(); -} - -#define arch_decomp_setup() - -#endif |