diff options
Diffstat (limited to 'arch/arm/mach-omap2')
34 files changed, 293 insertions, 4314 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index ad08d470a2ca..dca7d06c0b93 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -95,6 +95,7 @@ config ARCH_OMAP2PLUS bool select ARCH_HAS_BANDGAP select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_HAS_RESET_CONTROLLER select ARCH_OMAP select CLKSRC_MMIO select GENERIC_IRQ_CHIP @@ -105,11 +106,11 @@ config ARCH_OMAP2PLUS select OMAP_DM_TIMER select OMAP_GPMC select PINCTRL + select RESET_CONTROLLER select SOC_BUS select TI_SYSC select OMAP_IRQCHIP select CLKSRC_TI_32K - select ARCH_HAS_RESET_CONTROLLER help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index f07cfda85156..e1135b9d67c6 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -16,11 +16,11 @@ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ clock-common = clock.o secure-common = omap-smc.o omap-secure.o -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) -obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) -obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c index 751708d727af..c96a2b1efbad 100644 --- a/arch/arm/mach-omap2/clockdomains43xx_data.c +++ b/arch/arm/mach-omap2/clockdomains43xx_data.c @@ -84,6 +84,15 @@ static struct clockdomain l3s_tsc_43xx_clkdm = { .flags = CLKDM_CAN_SWSUP, }; +static struct clockdomain lcdc_43xx_clkdm = { + .name = "lcdc_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .prcm_partition = AM43XX_CM_PARTITION, + .cm_inst = AM43XX_CM_PER_INST, + .clkdm_offs = AM43XX_CM_PER_LCDC_CDOFFS, + .flags = CLKDM_CAN_SWSUP, +}; + static struct clockdomain dss_43xx_clkdm = { .name = "dss_clkdm", .pwrdm = { .name = "per_pwrdm" }, @@ -173,6 +182,7 @@ static struct clockdomain *clockdomains_am43xx[] __initdata = { &pruss_ocp_43xx_clkdm, &ocpwp_l3_43xx_clkdm, &l3s_tsc_43xx_clkdm, + &lcdc_43xx_clkdm, &dss_43xx_clkdm, &l3_aon_43xx_clkdm, &emif_43xx_clkdm, diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c index 3068802824b7..27835c4d1aa9 100644 --- a/arch/arm/mach-omap2/clockdomains7xx_data.c +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c @@ -606,7 +606,7 @@ static struct clockdomain cam_7xx_clkdm = { .dep_bit = DRA7XX_CAM_STATDEP_SHIFT, .wkdep_srcs = cam_wkup_sleep_deps, .sleepdep_srcs = cam_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain l4per_7xx_clkdm = { diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 223b37c48389..75d729943958 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -255,7 +255,7 @@ extern void gic_dist_disable(void); extern void gic_dist_enable(void); extern bool gic_dist_disabled(void); extern void gic_timer_retrigger(void); -extern void omap_smc1(u32 fn, u32 arg); +extern void _omap_smc1(u32 fn, u32 arg); extern void omap4_sar_ram_init(void); extern void __iomem *omap4_get_sar_ram_base(void); extern void omap4_mpuss_early_init(void); @@ -345,9 +345,12 @@ static inline int dra7xx_pciess_reset(struct omap_hwmod *oh) } #endif +struct omap_system_dma_plat_info; + void pdata_quirks_init(const struct of_device_id *); void omap_auxdata_legacy_init(struct device *dev); void omap_pcs_legacy_init(int irq, void (*rearm)(void)); +extern struct omap_system_dma_plat_info dma_plat_info; struct omap_sdrc_params; extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 0c105baa5e88..8cc109cc242a 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -30,10 +30,6 @@ #include <linux/omap-dma.h> #include "soc.h" -#include "omap_hwmod.h" -#include "omap_device.h" - -static enum omap_reg_offsets dma_common_ch_end; static const struct omap_dma_reg reg_map[] = { [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT }, @@ -81,42 +77,6 @@ static const struct omap_dma_reg reg_map[] = { [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT }, }; -static void __iomem *dma_base; -static inline void dma_write(u32 val, int reg, int lch) -{ - void __iomem *addr = dma_base; - - addr += reg_map[reg].offset; - addr += reg_map[reg].stride * lch; - - writel_relaxed(val, addr); -} - -static inline u32 dma_read(int reg, int lch) -{ - void __iomem *addr = dma_base; - - addr += reg_map[reg].offset; - addr += reg_map[reg].stride * lch; - - return readl_relaxed(addr); -} - -static void omap2_clear_dma(int lch) -{ - int i; - - for (i = CSDP; i <= dma_common_ch_end; i += 1) - dma_write(0, i, lch); -} - -static void omap2_show_dma_caps(void) -{ - u8 revision = dma_read(REVISION, 0) & 0xff; - printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", - revision >> 4, revision & 0xf); -} - static unsigned configure_dma_errata(void) { unsigned errata = 0; @@ -211,82 +171,35 @@ static const struct dma_slave_map omap24xx_sdma_dt_map[] = { { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */ }; -static struct omap_system_dma_plat_info dma_plat_info __initdata = { - .reg_map = reg_map, - .channel_stride = 0x60, - .show_dma_caps = omap2_show_dma_caps, - .clear_dma = omap2_clear_dma, - .dma_write = dma_write, - .dma_read = dma_read, +static struct omap_dma_dev_attr dma_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .lch_count = 32, }; -static struct platform_device_info omap_dma_dev_info __initdata = { - .name = "omap-dma-engine", - .id = -1, - .dma_mask = DMA_BIT_MASK(32), +struct omap_system_dma_plat_info dma_plat_info = { + .reg_map = reg_map, + .channel_stride = 0x60, + .dma_attr = &dma_attr, }; /* One time initializations */ -static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) +static int __init omap2_system_dma_init(void) { - struct platform_device *pdev; - struct omap_system_dma_plat_info p; - struct omap_dma_dev_attr *d; - struct resource *mem; - char *name = "omap_dma_system"; - - p = dma_plat_info; - p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; - p.errata = configure_dma_errata(); + dma_plat_info.errata = configure_dma_errata(); if (soc_is_omap24xx()) { /* DMA slave map for drivers not yet converted to DT */ - p.slave_map = omap24xx_sdma_dt_map; - p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map); + dma_plat_info.slave_map = omap24xx_sdma_dt_map; + dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map); } - pdev = omap_device_build(name, 0, oh, &p, sizeof(p)); - if (IS_ERR(pdev)) { - pr_err("%s: Can't build omap_device for %s:%s.\n", - __func__, name, oh->name); - return PTR_ERR(pdev); - } - - omap_dma_dev_info.res = pdev->resource; - omap_dma_dev_info.num_res = pdev->num_resources; + if (!soc_is_omap242x()) + dma_attr.dev_caps |= IS_RW_PRIORITY; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) { - dev_err(&pdev->dev, "%s: no mem resource\n", __func__); - return -EINVAL; - } - - dma_base = ioremap(mem->start, resource_size(mem)); - if (!dma_base) { - dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); - return -ENOMEM; - } - - d = oh->dev_attr; - - if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) - d->dev_caps |= HS_CHANNELS_RESERVED; - - if (platform_get_irq_byname(pdev, "0") < 0) - d->dev_caps |= DMA_ENGINE_HANDLE_IRQ; - - /* Check the capabilities register for descriptor loading feature */ - if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) - dma_common_ch_end = CCDN; - else - dma_common_ch_end = CCFN; + if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) + dma_attr.dev_caps |= HS_CHANNELS_RESERVED; return 0; } - -static int __init omap2_system_dma_init(void) -{ - return omap_hwmod_for_each_by_class("dma", - omap2_system_dma_init_dev, NULL); -} omap_arch_initcall(omap2_system_dma_init); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 349e48042982..f28047233665 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -51,6 +51,7 @@ #include "prm33xx.h" #include "prm44xx.h" #include "opp2xxx.h" +#include "omap-secure.h" /* * omap_clk_soc_init: points to a function that does the SoC-specific @@ -430,6 +431,7 @@ void __init omap2420_init_early(void) omap_hwmod_init_postsetup(); omap_clk_soc_init = omap2420_dt_clk_init; rate_table = omap2420_rate_table; + omap_secure_init(); } void __init omap2420_init_late(void) @@ -454,6 +456,7 @@ void __init omap2430_init_early(void) omap_hwmod_init_postsetup(); omap_clk_soc_init = omap2430_dt_clk_init; rate_table = omap2430_rate_table; + omap_secure_init(); } void __init omap2430_init_late(void) @@ -481,6 +484,7 @@ void __init omap3_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_secure_init(); } void __init omap3430_init_early(void) @@ -533,6 +537,7 @@ void __init ti814x_init_early(void) dm814x_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dm814x_dt_clk_init; + omap_secure_init(); } void __init ti816x_init_early(void) @@ -549,6 +554,7 @@ void __init ti816x_init_early(void) dm816x_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dm816x_dt_clk_init; + omap_secure_init(); } #endif @@ -566,6 +572,7 @@ void __init am33xx_init_early(void) am33xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = am33xx_dt_clk_init; + omap_secure_init(); } void __init am33xx_init_late(void) @@ -589,6 +596,7 @@ void __init am43xx_init_early(void) omap_hwmod_init_postsetup(); omap_l2_cache_init(); omap_clk_soc_init = am43xx_dt_clk_init; + omap_secure_init(); } void __init am43xx_init_late(void) @@ -617,6 +625,7 @@ void __init omap4430_init_early(void) omap_hwmod_init_postsetup(); omap_l2_cache_init(); omap_clk_soc_init = omap4xxx_dt_clk_init; + omap_secure_init(); } void __init omap4430_init_late(void) @@ -643,6 +652,7 @@ void __init omap5_init_early(void) omap54xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = omap5xxx_dt_clk_init; + omap_secure_init(); } void __init omap5_init_late(void) @@ -666,6 +676,7 @@ void __init dra7xx_init_early(void) dra7xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dra7xx_dt_clk_init; + omap_secure_init(); } void __init dra7xx_init_late(void) diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index f1a6ece8108e..54aff33e55e6 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -8,36 +8,134 @@ #include <linux/platform_device.h> #include <linux/err.h> +#include <linux/clk.h> +#include <linux/list.h> -#include "omap_hwmod.h" -#include "omap_device.h" +#include "clockdomain.h" #include "powerdomain.h" +struct pwrdm_link { + struct device *dev; + struct powerdomain *pwrdm; + struct list_head node; +}; + +static DEFINE_SPINLOCK(iommu_lock); +static struct clockdomain *emu_clkdm; +static atomic_t emu_count; + +static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev, + bool enable) +{ + struct device_node *np = pdev->dev.of_node; + unsigned long flags; + + if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) + return; + + if (!emu_clkdm) { + emu_clkdm = clkdm_lookup("emu_clkdm"); + if (WARN_ON_ONCE(!emu_clkdm)) + return; + } + + spin_lock_irqsave(&iommu_lock, flags); + + if (enable && (atomic_inc_return(&emu_count) == 1)) + clkdm_deny_idle(emu_clkdm); + else if (!enable && (atomic_dec_return(&emu_count) == 0)) + clkdm_allow_idle(emu_clkdm); + + spin_unlock_irqrestore(&iommu_lock, flags); +} + +static struct powerdomain *_get_pwrdm(struct device *dev) +{ + struct clk *clk; + struct clk_hw_omap *hwclk; + struct clockdomain *clkdm; + struct powerdomain *pwrdm = NULL; + struct pwrdm_link *entry; + unsigned long flags; + static LIST_HEAD(cache); + + spin_lock_irqsave(&iommu_lock, flags); + + list_for_each_entry(entry, &cache, node) { + if (entry->dev == dev) { + pwrdm = entry->pwrdm; + break; + } + } + + spin_unlock_irqrestore(&iommu_lock, flags); + + if (pwrdm) + return pwrdm; + + clk = of_clk_get(dev->of_node->parent, 0); + if (!clk) { + dev_err(dev, "no fck found\n"); + return NULL; + } + + hwclk = to_clk_hw_omap(__clk_get_hw(clk)); + clk_put(clk); + if (!hwclk || !hwclk->clkdm_name) { + dev_err(dev, "no hwclk data\n"); + return NULL; + } + + clkdm = clkdm_lookup(hwclk->clkdm_name); + if (!clkdm) { + dev_err(dev, "clkdm not found: %s\n", hwclk->clkdm_name); + return NULL; + } + + pwrdm = clkdm_get_pwrdm(clkdm); + if (!pwrdm) { + dev_err(dev, "pwrdm not found: %s\n", clkdm->name); + return NULL; + } + + entry = kmalloc(sizeof(*entry), GFP_KERNEL); + if (entry) { + entry->dev = dev; + entry->pwrdm = pwrdm; + spin_lock_irqsave(&iommu_lock, flags); + list_add(&entry->node, &cache); + spin_unlock_irqrestore(&iommu_lock, flags); + } + + return pwrdm; +} + int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, u8 *pwrst) { struct powerdomain *pwrdm; - struct omap_device *od; u8 next_pwrst; + int ret = 0; - od = to_omap_device(pdev); - if (!od) - return -ENODEV; - - if (od->hwmods_cnt != 1) - return -EINVAL; - - pwrdm = omap_hwmod_get_pwrdm(od->hwmods[0]); + pwrdm = _get_pwrdm(&pdev->dev); if (!pwrdm) - return -EINVAL; + return -ENODEV; - if (request) + if (request) { *pwrst = pwrdm_read_next_pwrst(pwrdm); + omap_iommu_dra7_emu_swsup_config(pdev, true); + } if (*pwrst > PWRDM_POWER_RET) - return 0; + goto out; next_pwrst = request ? PWRDM_POWER_ON : *pwrst; - return pwrdm_set_next_pwrst(pwrdm, next_pwrst); + ret = pwrdm_set_next_pwrst(pwrdm, next_pwrst); + +out: + if (!request) + omap_iommu_dra7_emu_swsup_config(pdev, false); + + return ret; } diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 24298e47b9f1..d00e3c72e37d 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -8,18 +8,42 @@ * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com> */ +#include <linux/arm-smccc.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> #include <linux/memblock.h> +#include <linux/of.h> #include <asm/cacheflush.h> #include <asm/memblock.h> +#include "common.h" #include "omap-secure.h" static phys_addr_t omap_secure_memblock_base; +bool optee_available; + +#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +static void __init omap_optee_init_check(void) +{ + struct device_node *np; + + /* + * We only check that the OP-TEE node is present and available. The + * OP-TEE kernel driver is not needed for the type of interaction made + * with OP-TEE here so the driver's status is not checked. + */ + np = of_find_node_by_path("/firmware/optee"); + if (np && of_device_is_available(np)) + optee_available = true; + of_node_put(np); +} + /** * omap_sec_dispatcher: Routine to dispatch low power secure * service routines @@ -53,6 +77,27 @@ u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, return ret; } +void omap_smccc_smc(u32 fn, u32 arg) +{ + struct arm_smccc_res res; + + arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg, + 0, 0, 0, 0, 0, 0, &res); + WARN(res.a0, "Secure function call 0x%08x failed\n", fn); +} + +void omap_smc1(u32 fn, u32 arg) +{ + /* + * If this platform has OP-TEE installed we use ARM SMC calls + * otherwise fall back to the OMAP ROM style calls. + */ + if (optee_available) + omap_smccc_smc(fn, arg); + else + _omap_smc1(fn, arg); +} + /* Allocate the memory to save secure ram */ int __init omap_secure_ram_reserve_memblock(void) { @@ -163,3 +208,8 @@ u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) NO_FLAG, 3, ptr, count, flag, 0); } + +void __init omap_secure_init(void) +{ + omap_optee_init_check(); +} diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 20046e8f8ecb..ba8c486c0454 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -10,6 +10,8 @@ #ifndef OMAP_ARCH_OMAP_SECURE_H #define OMAP_ARCH_OMAP_SECURE_H +#include <linux/types.h> + /* Monitor error code */ #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF @@ -51,6 +53,9 @@ #define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 +#define AM43xx_PPA_SVC_PM_SUSPEND 0x71 +#define AM43xx_PPA_SVC_PM_RESUME 0x72 + /* Secure RX-51 PPA (Primary Protected Application) APIs */ #define RX51_PPA_HWRNG 29 #define RX51_PPA_L2_INVAL 40 @@ -60,6 +65,8 @@ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, u32 arg3, u32 arg4); +extern void omap_smccc_smc(u32 fn, u32 arg); +extern void omap_smc1(u32 fn, u32 arg); extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); extern phys_addr_t omap_secure_ram_mempool_base(void); @@ -72,6 +79,9 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); +extern bool optee_available; +void omap_secure_init(void); + #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER void set_cntfreq(void); #else diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S index fd2bcd91f4a1..d4832845a4e8 100644 --- a/arch/arm/mach-omap2/omap-smc.S +++ b/arch/arm/mach-omap2/omap-smc.S @@ -18,18 +18,18 @@ * the monitor API number. It uses few CPU registers * internally and hence they need be backed up including * link register "lr". - * Function signature : void omap_smc1(u32 fn, u32 arg) + * Function signature : void _omap_smc1(u32 fn, u32 arg) */ .arch armv7-a .arch_extension sec -ENTRY(omap_smc1) +ENTRY(_omap_smc1) stmfd sp!, {r2-r12, lr} mov r12, r0 mov r0, r1 dsb smc #0 ldmfd sp!, {r2-r12, pc} -ENDPROC(omap_smc1) +ENDPROC(_omap_smc1) /** * u32 omap_smc2(u32 id, u32 falg, u32 pargs) diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index 1d55602b3f8f..6b4548f3b57f 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -373,176 +373,6 @@ void omap_device_delete(struct omap_device *od) kfree(od); } -/** - * omap_device_copy_resources - Add legacy IO and IRQ resources - * @oh: interconnect target module - * @pdev: platform device to copy resources to - * - * We still have legacy DMA and smartreflex needing resources. - * Let's populate what they need until we can eventually just - * remove this function. Note that there should be no need to - * call this from omap_device_build_from_dt(), nor should there - * be any need to call it for other devices. - */ -static int -omap_device_copy_resources(struct omap_hwmod *oh, - struct platform_device *pdev) -{ - struct device_node *np, *child; - struct property *prop; - struct resource *res; - const char *name; - int error, irq = 0; - - if (!oh || !oh->od || !oh->od->pdev) - return -EINVAL; - - np = oh->od->pdev->dev.of_node; - if (!np) { - error = -ENODEV; - goto error; - } - - res = kcalloc(2, sizeof(*res), GFP_KERNEL); - if (!res) - return -ENOMEM; - - /* Do we have a dts range for the interconnect target module? */ - error = omap_hwmod_parse_module_range(oh, np, res); - - /* No ranges, rely on device reg entry */ - if (error) - error = of_address_to_resource(np, 0, res); - if (error) - goto free; - - /* SmartReflex needs first IO resource name to be "mpu" */ - res[0].name = "mpu"; - - /* - * We may have a configured "ti,sysc" interconnect target with a - * dts child with the interrupt. If so use the first child's - * first interrupt for "ti-hwmods" legacy support. - */ - of_property_for_each_string(np, "compatible", prop, name) - if (!strncmp("ti,sysc-", name, 8)) - break; - - child = of_get_next_available_child(np, NULL); - - if (name) - irq = irq_of_parse_and_map(child, 0); - if (!irq) - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - error = -EINVAL; - goto free; - } - - /* Legacy DMA code needs interrupt name to be "0" */ - res[1].start = irq; - res[1].end = irq; - res[1].flags = IORESOURCE_IRQ; - res[1].name = "0"; - - error = platform_device_add_resources(pdev, res, 2); - -free: - kfree(res); - -error: - WARN(error, "%s: %s device %s failed: %i\n", - __func__, oh->name, dev_name(&pdev->dev), - error); - - return error; -} - -/** - * omap_device_build - build and register an omap_device with one omap_hwmod - * @pdev_name: name of the platform_device driver to use - * @pdev_id: this platform_device's connection ID - * @oh: ptr to the single omap_hwmod that backs this omap_device - * @pdata: platform_data ptr to associate with the platform_device - * @pdata_len: amount of memory pointed to by @pdata - * - * Convenience function for building and registering a single - * omap_device record, which in turn builds and registers a - * platform_device record. See omap_device_build_ss() for more - * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise, - * passes along the return value of omap_device_build_ss(). - */ -struct platform_device __init *omap_device_build(const char *pdev_name, - int pdev_id, - struct omap_hwmod *oh, - void *pdata, int pdata_len) -{ - int ret = -ENOMEM; - struct platform_device *pdev; - struct omap_device *od; - - if (!oh || !pdev_name) - return ERR_PTR(-EINVAL); - - if (!pdata && pdata_len > 0) - return ERR_PTR(-EINVAL); - - if (strncmp(oh->name, "smartreflex", 11) && - strncmp(oh->name, "dma", 3)) { - pr_warn("%s need to update %s to probe with dt\na", - __func__, pdev_name); - ret = -ENODEV; - goto odbs_exit; - } - - pdev = platform_device_alloc(pdev_name, pdev_id); - if (!pdev) { - ret = -ENOMEM; - goto odbs_exit; - } - - /* Set the dev_name early to allow dev_xxx in omap_device_alloc */ - if (pdev->id != -1) - dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); - else - dev_set_name(&pdev->dev, "%s", pdev->name); - - /* - * Must be called before omap_device_alloc() as oh->od - * only contains the currently registered omap_device - * and will get overwritten by omap_device_alloc(). - */ - ret = omap_device_copy_resources(oh, pdev); - if (ret) - goto odbs_exit1; - - od = omap_device_alloc(pdev, &oh, 1); - if (IS_ERR(od)) { - ret = PTR_ERR(od); - goto odbs_exit1; - } - - ret = platform_device_add_data(pdev, pdata, pdata_len); - if (ret) - goto odbs_exit2; - - ret = omap_device_register(pdev); - if (ret) - goto odbs_exit2; - - return pdev; - -odbs_exit2: - omap_device_delete(od); -odbs_exit1: - platform_device_put(pdev); -odbs_exit: - - pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret); - - return ERR_PTR(ret); -} - #ifdef CONFIG_PM static int _od_runtime_suspend(struct device *dev) { diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h index ced775e401cf..f77e76a7841a 100644 --- a/arch/arm/mach-omap2/omap_device.h +++ b/arch/arm/mach-omap2/omap_device.h @@ -68,10 +68,6 @@ int omap_device_idle(struct platform_device *pdev); /* Core code interface */ -struct platform_device *omap_device_build(const char *pdev_name, int pdev_id, - struct omap_hwmod *oh, void *pdata, - int pdata_len); - struct omap_device *omap_device_alloc(struct platform_device *pdev, struct omap_hwmod **ohs, int oh_cnt); void omap_device_delete(struct omap_device *od); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index a136788db839..17d337ed18be 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1853,23 +1853,6 @@ static int _omap4_get_context_lost(struct omap_hwmod *oh) } /** - * _enable_preprogram - Pre-program an IP block during the _enable() process - * @oh: struct omap_hwmod * - * - * Some IP blocks (such as AESS) require some additional programming - * after enable before they can enter idle. If a function pointer to - * do so is present in the hwmod data, then call it and pass along the - * return value; otherwise, return 0. - */ -static int _enable_preprogram(struct omap_hwmod *oh) -{ - if (!oh->class->enable_preprogram) - return 0; - - return oh->class->enable_preprogram(oh); -} - -/** * _enable - enable an omap_hwmod * @oh: struct omap_hwmod * * @@ -1952,7 +1935,6 @@ static int _enable(struct omap_hwmod *oh) _update_sysc_cache(oh); _enable_sysc(oh); } - r = _enable_preprogram(oh); } else { if (soc_ops.disable_module) soc_ops.disable_module(oh); diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 2d0fd99d4713..eebf2fdf434c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -501,7 +501,6 @@ struct omap_hwmod_omap4_prcm { * @sysc: device SYSCONFIG/SYSSTATUS register data * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown * @reset: ptr to fn to be executed in place of the standard hwmod reset fn - * @enable_preprogram: ptr to fn to be executed during device enable * @lock: ptr to fn to be executed to lock IP registers * @unlock: ptr to fn to be executed to unlock IP registers * @@ -526,7 +525,6 @@ struct omap_hwmod_class { struct omap_hwmod_class_sysconfig *sysc; int (*pre_shutdown)(struct omap_hwmod *oh); int (*reset)(struct omap_hwmod *oh); - int (*enable_preprogram)(struct omap_hwmod *oh); void (*lock)(struct omap_hwmod *oh); void (*unlock)(struct omap_hwmod *oh); }; @@ -662,7 +660,6 @@ const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); * */ -extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh); void omap_hwmod_rtc_unlock(struct omap_hwmod *oh); void omap_hwmod_rtc_lock(struct omap_hwmod *oh); diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index d49df96b4052..b14442cf6179 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -11,7 +11,6 @@ */ #include <linux/platform_data/i2c-omap.h> -#include <linux/omap-dma.h> #include "omap_hwmod.h" #include "l3_2xxx.h" @@ -126,21 +125,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = { .flags = HWMOD_16BIT_REG, }; -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32, - .lch_count = 32, -}; - -static struct omap_hwmod omap2420_dma_system_hwmod = { - .name = "dma", - .class = &omap2xxx_dma_hwmod_class, - .main_clk = "core_l3_ck", - .dev_attr = &dma_dev_attr, - .flags = HWMOD_NO_IDLEST, -}; - /* mailbox */ static struct omap_hwmod omap2420_mailbox_hwmod = { .name = "mailbox", @@ -328,22 +312,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { - .master = &omap2420_dma_system_hwmod, - .slave = &omap2xxx_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> dma_system */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2420_dma_system_hwmod, - .clk = "sdma_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_core -> mailbox */ static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { .master = &omap2xxx_l4_core_hwmod, @@ -435,8 +403,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_wkup__gpio2, &omap2420_l4_wkup__gpio3, &omap2420_l4_wkup__gpio4, - &omap2420_dma_system__l3, - &omap2420_l4_core__dma_system, &omap2420_l4_core__mailbox, &omap2420_l4_core__mcbsp1, &omap2420_l4_core__mcbsp2, diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index c51ef84ff64d..41a37c74f9a6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -12,7 +12,6 @@ #include <linux/platform_data/i2c-omap.h> #include <linux/platform_data/hsmmc-omap.h> -#include <linux/omap-dma.h> #include "omap_hwmod.h" #include "l3_2xxx.h" @@ -121,21 +120,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { .class = &omap2xxx_gpio_hwmod_class, }; -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - -static struct omap_hwmod omap2430_dma_system_hwmod = { - .name = "dma", - .class = &omap2xxx_dma_hwmod_class, - .main_clk = "core_l3_ck", - .dev_attr = &dma_dev_attr, - .flags = HWMOD_NO_IDLEST, -}; - /* mailbox */ static struct omap_hwmod omap2430_mailbox_hwmod = { .name = "mailbox", @@ -508,22 +492,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { - .master = &omap2430_dma_system_hwmod, - .slave = &omap2xxx_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> dma_system */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2430_dma_system_hwmod, - .clk = "sdma_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_core -> mailbox */ static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { .master = &omap2xxx_l4_core_hwmod, @@ -635,8 +603,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2430_l4_wkup__gpio3, &omap2430_l4_wkup__gpio4, &omap2430_l4_core__gpio5, - &omap2430_dma_system__l3, - &omap2430_l4_core__dma_system, &omap2430_l4_core__mailbox, &omap2430_l4_core__mcbsp1, &omap2430_l4_core__mcbsp2, diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index f767524d06b5..a445704d43d9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -7,7 +7,6 @@ */ #include <linux/types.h> -#include <linux/omap-dma.h> #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" @@ -95,23 +94,6 @@ struct omap_hwmod_class omap2xxx_gpio_hwmod_class = { .sysc = &omap2xxx_gpio_sysc, }; -/* system dma */ -static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x002c, - .syss_offs = 0x0028, - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | - SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -struct omap_hwmod_class omap2xxx_dma_hwmod_class = { - .name = "dma", - .sysc = &omap2xxx_dma_sysc, -}; - /* * 'mailbox' class * mailbox module allowing communication between the on-chip processors diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h index 26e13d4fa19c..5ef76fe3f33d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h @@ -28,29 +28,13 @@ extern struct omap_hwmod_ocp_if am33xx_pruss__l3_main; extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main; extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx; extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc; -extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0; -extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2; extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1; extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer3; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer4; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer5; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer6; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer7; extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc; extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0; extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1; extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2; extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc; -extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0; -extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0; extern struct omap_hwmod am33xx_l3_main_hwmod; extern struct omap_hwmod am33xx_l3_s_hwmod; @@ -61,29 +45,13 @@ extern struct omap_hwmod am33xx_mpu_hwmod; extern struct omap_hwmod am33xx_pruss_hwmod; extern struct omap_hwmod am33xx_gfx_hwmod; extern struct omap_hwmod am33xx_prcm_hwmod; -extern struct omap_hwmod am33xx_aes0_hwmod; -extern struct omap_hwmod am33xx_sha0_hwmod; extern struct omap_hwmod am33xx_ocmcram_hwmod; extern struct omap_hwmod am33xx_smartreflex0_hwmod; extern struct omap_hwmod am33xx_smartreflex1_hwmod; -extern struct omap_hwmod am33xx_dcan0_hwmod; -extern struct omap_hwmod am33xx_dcan1_hwmod; -extern struct omap_hwmod am33xx_elm_hwmod; -extern struct omap_hwmod am33xx_epwmss0_hwmod; -extern struct omap_hwmod am33xx_epwmss1_hwmod; -extern struct omap_hwmod am33xx_epwmss2_hwmod; extern struct omap_hwmod am33xx_gpmc_hwmod; extern struct omap_hwmod am33xx_rtc_hwmod; -extern struct omap_hwmod am33xx_spi0_hwmod; -extern struct omap_hwmod am33xx_spi1_hwmod; -extern struct omap_hwmod am33xx_spinlock_hwmod; extern struct omap_hwmod am33xx_timer1_hwmod; extern struct omap_hwmod am33xx_timer2_hwmod; -extern struct omap_hwmod am33xx_timer3_hwmod; -extern struct omap_hwmod am33xx_timer4_hwmod; -extern struct omap_hwmod am33xx_timer5_hwmod; -extern struct omap_hwmod am33xx_timer6_hwmod; -extern struct omap_hwmod am33xx_timer7_hwmod; extern struct omap_hwmod am33xx_tpcc_hwmod; extern struct omap_hwmod am33xx_tptc0_hwmod; extern struct omap_hwmod am33xx_tptc1_hwmod; @@ -94,7 +62,6 @@ extern struct omap_hwmod_class am33xx_l4_hwmod_class; extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class; extern struct omap_hwmod_class am33xx_control_hwmod_class; extern struct omap_hwmod_class am33xx_timer_hwmod_class; -extern struct omap_hwmod_class am33xx_epwmss_hwmod_class; extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class; extern struct omap_hwmod_class am33xx_spi_hwmod_class; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index 7123c455aaa9..ac7d5bb1a02f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -106,50 +106,6 @@ struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { .user = OCP_USER_MPU, }; -/* l4 per/ls -> DCAN0 */ -struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_dcan0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 per/ls -> DCAN1 */ -struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_dcan1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_elm_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_epwmss0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_epwmss1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_epwmss2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - /* l3s cfg -> gpmc */ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { .master = &am33xx_l3_s_hwmod, @@ -158,30 +114,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { .user = OCP_USER_MPU, }; -/* l4 ls -> spinlock */ -struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_spinlock_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 ls -> mcspi0 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_spi0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 ls -> mcspi1 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_spi1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - /* l4 per -> timer2 */ struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { .master = &am33xx_l4_ls_hwmod, @@ -190,46 +122,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { .user = OCP_USER_MPU, }; -/* l4 per -> timer3 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer4 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer5 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer5_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer6 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer6_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer7 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer7_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - /* l3 main -> tpcc */ struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { .master = &am33xx_l3_main_hwmod, @@ -268,19 +160,3 @@ struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { .slave = &am33xx_ocmcram_hwmod, .user = OCP_USER_MPU | OCP_USER_SDMA, }; - -/* l3 main -> sha0 HIB2 */ -struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_sha0_hwmod, - .clk = "sha0_fck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 main -> AES0 HIB2 */ -struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_aes0_hwmod, - .clk = "aes0_fck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 2df8659612ef..78ec1bc8e3a1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -213,57 +213,7 @@ struct omap_hwmod_class am33xx_emif_hwmod_class = { .sysc = &am33xx_emif_sysc, }; -/* - * 'aes0' class - */ -static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { - .rev_offs = 0x80, - .sysc_offs = 0x84, - .syss_offs = 0x88, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class am33xx_aes0_hwmod_class = { - .name = "aes0", - .sysc = &am33xx_aes0_sysc, -}; - -struct omap_hwmod am33xx_aes0_hwmod = { - .name = "aes", - .class = &am33xx_aes0_hwmod_class, - .clkdm_name = "l3_clkdm", - .main_clk = "aes0_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* sha0 HIB2 (the 'P' (public) device) */ -static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { - .rev_offs = 0x100, - .sysc_offs = 0x110, - .syss_offs = 0x114, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; -static struct omap_hwmod_class am33xx_sha0_hwmod_class = { - .name = "sha0", - .sysc = &am33xx_sha0_sysc, -}; - -struct omap_hwmod am33xx_sha0_hwmod = { - .name = "sham", - .class = &am33xx_sha0_hwmod_class, - .clkdm_name = "l3_clkdm", - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; /* ocmcram */ static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { @@ -321,122 +271,6 @@ struct omap_hwmod_class am33xx_control_hwmod_class = { .name = "control", }; -/* - * dcan class - */ -static struct omap_hwmod_class am33xx_dcan_hwmod_class = { - .name = "d_can", -}; - -/* dcan0 */ -struct omap_hwmod am33xx_dcan0_hwmod = { - .name = "d_can0", - .class = &am33xx_dcan_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dcan0_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* dcan1 */ -struct omap_hwmod am33xx_dcan1_hwmod = { - .name = "d_can1", - .class = &am33xx_dcan_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dcan1_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* elm */ -static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_elm_hwmod_class = { - .name = "elm", - .sysc = &am33xx_elm_sysc, -}; - -struct omap_hwmod am33xx_elm_hwmod = { - .name = "elm", - .class = &am33xx_elm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* pwmss */ -static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x4, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -struct omap_hwmod_class am33xx_epwmss_hwmod_class = { - .name = "epwmss", - .sysc = &am33xx_epwmss_sysc, -}; - -/* epwmss0 */ -struct omap_hwmod am33xx_epwmss0_hwmod = { - .name = "epwmss0", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* epwmss1 */ -struct omap_hwmod am33xx_epwmss1_hwmod = { - .name = "epwmss1", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* epwmss2 */ -struct omap_hwmod am33xx_epwmss2_hwmod = { - .name = "epwmss2", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; /* gpmc */ static struct omap_hwmod_class_sysconfig gpmc_sysc = { @@ -501,83 +335,6 @@ struct omap_hwmod am33xx_rtc_hwmod = { }, }; -/* 'spi' class */ -static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0110, - .syss_offs = 0x0114, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -struct omap_hwmod_class am33xx_spi_hwmod_class = { - .name = "mcspi", - .sysc = &am33xx_mcspi_sysc, -}; - -/* spi0 */ -struct omap_hwmod am33xx_spi0_hwmod = { - .name = "spi0", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* spi1 */ -struct omap_hwmod am33xx_spi1_hwmod = { - .name = "spi1", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'spinlock' class - * spinlock provides hardware assistance for synchronizing the - * processes running on multiple processors - */ - -static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { - .name = "spinlock", - .sysc = &am33xx_spinlock_sysc, -}; - -struct omap_hwmod am33xx_spinlock_hwmod = { - .name = "spinlock", - .class = &am33xx_spinlock_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* 'timer 2-7' class */ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { .rev_offs = 0x0000, @@ -636,66 +393,6 @@ struct omap_hwmod am33xx_timer2_hwmod = { }, }; -struct omap_hwmod am33xx_timer3_hwmod = { - .name = "timer3", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer3_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer4_hwmod = { - .name = "timer4", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer4_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer5_hwmod = { - .name = "timer5", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer5_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer6_hwmod = { - .name = "timer6", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer6_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer7_hwmod = { - .name = "timer7", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer7_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* tpcc */ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { .name = "tpcc", @@ -772,21 +469,7 @@ struct omap_hwmod am33xx_tptc2_hwmod = { static void omap_hwmod_am33xx_clkctrl(void) { - CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET); CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex0_hwmod, AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex1_hwmod, @@ -807,8 +490,6 @@ static void omap_hwmod_am33xx_clkctrl(void) CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); - CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET); } static void omap_hwmod_am33xx_rst(void) @@ -826,21 +507,7 @@ void omap_hwmod_am33xx_reg(void) static void omap_hwmod_am43xx_clkctrl(void) { - CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET); CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex0_hwmod, AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex1_hwmod, @@ -860,8 +527,6 @@ static void omap_hwmod_am43xx_clkctrl(void) CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); - CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET); } static void omap_hwmod_am43xx_rst(void) diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index c63f66427e46..f1ea8c604595 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -81,36 +81,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = { .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), }; -/* - * 'adc/tsc' class - * TouchScreen Controller (Anolog-To-Digital Converter) - */ -static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { - .rev_offs = 0x00, - .sysc_offs = 0x10, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { - .name = "adc_tsc", - .sysc = &am33xx_adc_tsc_sysc, -}; - -static struct omap_hwmod am33xx_adc_tsc_hwmod = { - .name = "adc_tsc", - .class = &am33xx_adc_tsc_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .main_clk = "adc_tsc_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; /* * Modules omap_hwmod structures @@ -226,34 +196,6 @@ static struct omap_hwmod am33xx_control_hwmod = { }, }; -/* lcdc */ -static struct omap_hwmod_class_sysconfig lcdc_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x54, - .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE, - .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART, - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { - .name = "lcdc", - .sysc = &lcdc_sysc, -}; - -static struct omap_hwmod am33xx_lcdc_hwmod = { - .name = "lcdc", - .class = &am33xx_lcdc_hwmod_class, - .clkdm_name = "lcdc_clkdm", - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, - .main_clk = "lcd_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; /* * Interfaces @@ -331,21 +273,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { .user = OCP_USER_MPU, }; -/* L4 WKUP -> ADC_TSC */ -static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_adc_tsc_hwmod, - .clk = "dpll_core_m4_div2_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_lcdc_hwmod, - .clk = "dpll_core_m4_ck", - .user = OCP_USER_MPU, -}; - /* l4 wkup -> timer1 */ static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { .master = &am33xx_l4_wkup_hwmod, @@ -375,32 +302,14 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_wkup__smartreflex1, &am33xx_l4_wkup__timer1, &am33xx_l4_wkup__rtc, - &am33xx_l4_wkup__adc_tsc, &am33xx_l4_hs__pruss, - &am33xx_l4_per__dcan0, - &am33xx_l4_per__dcan1, &am33xx_l4_ls__timer2, - &am33xx_l4_ls__timer3, - &am33xx_l4_ls__timer4, - &am33xx_l4_ls__timer5, - &am33xx_l4_ls__timer6, - &am33xx_l4_ls__timer7, &am33xx_l3_main__tpcc, - &am33xx_l4_ls__spinlock, - &am33xx_l4_ls__elm, - &am33xx_l4_ls__epwmss0, - &am33xx_l4_ls__epwmss1, - &am33xx_l4_ls__epwmss2, &am33xx_l3_s__gpmc, - &am33xx_l3_main__lcdc, - &am33xx_l4_ls__mcspi0, - &am33xx_l4_ls__mcspi1, &am33xx_l3_main__tptc0, &am33xx_l3_main__tptc1, &am33xx_l3_main__tptc2, &am33xx_l3_main__ocmc, - &am33xx_l3_main__sha0, - &am33xx_l3_main__aes0, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index f52438bdfc14..3c8d2b6e887a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -16,7 +16,6 @@ #include <linux/power/smartreflex.h> #include <linux/platform_data/hsmmc-omap.h> -#include <linux/omap-dma.h> #include "l3_3xxx.h" #include "l4_3xxx.h" @@ -833,47 +832,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = { .class = &omap3xxx_gpio_hwmod_class, }; -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - -static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x002c, - .syss_offs = 0x0028, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { - .name = "dma", - .sysc = &omap3xxx_dma_sysc, -}; - -/* dma_system */ -static struct omap_hwmod omap3xxx_dma_system_hwmod = { - .name = "dma", - .class = &omap3xxx_dma_hwmod_class, - .main_clk = "core_l3_ick", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, - }, - }, - .dev_attr = &dma_dev_attr, - .flags = HWMOD_NO_IDLEST, -}; - /* * 'mcbsp' class * multi channel buffered serial port controller @@ -2233,23 +2191,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { - .master = &omap3xxx_dma_system_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dma_system_hwmod, - .clk = "core_l4_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - - /* l4_core -> mcbsp1 */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { .master = &omap3xxx_l4_core_hwmod, @@ -2628,8 +2569,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_per__gpio4, &omap3xxx_l4_per__gpio5, &omap3xxx_l4_per__gpio6, - &omap3xxx_dma_system__l3, - &omap3xxx_l4_core__dma_system, &omap3xxx_l4_core__mcbsp1, &omap3xxx_l4_per__mcbsp2, &omap3xxx_l4_per__mcbsp3, diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index b81f83466c94..d0867dbd788e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -112,165 +112,6 @@ static struct omap_hwmod am43xx_synctimer_hwmod = { }, }; -static struct omap_hwmod am43xx_timer8_hwmod = { - .name = "timer8", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer8_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_timer9_hwmod = { - .name = "timer9", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer9_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_timer10_hwmod = { - .name = "timer10", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer10_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_timer11_hwmod = { - .name = "timer11", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer11_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_epwmss3_hwmod = { - .name = "epwmss3", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_epwmss4_hwmod = { - .name = "epwmss4", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_epwmss5_hwmod = { - .name = "epwmss5", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_spi2_hwmod = { - .name = "spi2", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_spi3_hwmod = { - .name = "spi3", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_spi4_hwmod = { - .name = "spi4", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = { - .name = "ocp2scp", -}; - -static struct omap_hwmod am43xx_ocp2scp0_hwmod = { - .name = "ocp2scp0", - .class = &am43xx_ocp2scp_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_ocp2scp1_hwmod = { - .name = "ocp2scp1", - .class = &am43xx_ocp2scp_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = { .rev_offs = 0x0000, @@ -315,89 +156,6 @@ static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = { }, }; -static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = { - .rev_offs = 0, - .sysc_offs = 0x0010, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class am43xx_qspi_hwmod_class = { - .name = "qspi", - .sysc = &am43xx_qspi_sysc, -}; - -static struct omap_hwmod am43xx_qspi_hwmod = { - .name = "qspi", - .class = &am43xx_qspi_hwmod_class, - .clkdm_name = "l3s_clkdm", - .main_clk = "l3s_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'adc/tsc' class - * TouchScreen Controller (Analog-To-Digital Converter) - */ -static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = { - .rev_offs = 0x00, - .sysc_offs = 0x10, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = { - .name = "adc_tsc", - .sysc = &am43xx_adc_tsc_sysc, -}; - -static struct omap_hwmod am43xx_adc_tsc_hwmod = { - .name = "adc_tsc", - .class = &am43xx_adc_tsc_hwmod_class, - .clkdm_name = "l3s_tsc_clkdm", - .main_clk = "adc_tsc_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_class_sysconfig am43xx_des_sysc = { - .rev_offs = 0x30, - .sysc_offs = 0x34, - .syss_offs = 0x38, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class am43xx_des_hwmod_class = { - .name = "des", - .sysc = &am43xx_des_sysc, -}; - -static struct omap_hwmod am43xx_des_hwmod = { - .name = "des", - .class = &am43xx_des_hwmod_class, - .clkdm_name = "l3_clkdm", - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* dss */ static struct omap_hwmod am43xx_dss_core_hwmod = { @@ -467,44 +225,6 @@ static struct omap_hwmod am43xx_dss_rfbi_hwmod = { }; -static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x104, - .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class am43xx_vpfe_hwmod_class = { - .name = "vpfe", - .sysc = &am43xx_vpfe_sysc, -}; - -static struct omap_hwmod am43xx_vpfe0_hwmod = { - .name = "vpfe0", - .class = &am43xx_vpfe_hwmod_class, - .clkdm_name = "l3s_clkdm", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET, - }, - }, -}; - -static struct omap_hwmod am43xx_vpfe1_hwmod = { - .name = "vpfe1", - .class = &am43xx_vpfe_hwmod_class, - .clkdm_name = "l3s_clkdm", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET, - }, - }, -}; - /* Interfaces */ static struct omap_hwmod_ocp_if am43xx_l3_main__emif = { .master = &am33xx_l3_main_hwmod, @@ -562,13 +282,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am43xx_adc_tsc_hwmod, - .clk = "dpll_core_m4_div2_ck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_timer1_hwmod, @@ -583,90 +296,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_timer8_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_timer9_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_timer10_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_timer11_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_epwmss3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_epwmss4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_epwmss5_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_spi2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_spi3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_spi4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_ocp2scp0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_ocp2scp1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = { .master = &am33xx_l3_s_hwmod, .slave = &am43xx_usb_otg_ss0_hwmod, @@ -681,13 +310,6 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = { - .master = &am33xx_l3_s_hwmod, - .slave = &am43xx_qspi_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if am43xx_dss__l3_main = { .master = &am43xx_dss_core_hwmod, .slave = &am33xx_l3_main_hwmod, @@ -716,53 +338,8 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = { - .master = &am43xx_vpfe0_hwmod, - .slave = &am33xx_l3_main_hwmod, - .clk = "l3_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = { - .master = &am43xx_vpfe1_hwmod, - .slave = &am33xx_l3_main_hwmod, - .clk = "l3_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_vpfe0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_vpfe1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l3_main__des = { - .master = &am33xx_l3_main_hwmod, - .slave = &am43xx_des_hwmod, - .clk = "l3_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_wkup__synctimer, - &am43xx_l4_ls__timer8, - &am43xx_l4_ls__timer9, - &am43xx_l4_ls__timer10, - &am43xx_l4_ls__timer11, - &am43xx_l4_ls__epwmss3, - &am43xx_l4_ls__epwmss4, - &am43xx_l4_ls__epwmss5, - &am43xx_l4_ls__mcspi2, - &am43xx_l4_ls__mcspi3, - &am43xx_l4_ls__mcspi4, &am43xx_l3_main__pruss, &am33xx_mpu__l3_main, &am33xx_mpu__prcm, @@ -782,44 +359,19 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am43xx_l4_wkup__smartreflex0, &am43xx_l4_wkup__smartreflex1, &am43xx_l4_wkup__timer1, - &am43xx_l4_wkup__adc_tsc, - &am43xx_l3_s__qspi, - &am33xx_l4_per__dcan0, - &am33xx_l4_per__dcan1, &am33xx_l4_ls__timer2, - &am33xx_l4_ls__timer3, - &am33xx_l4_ls__timer4, - &am33xx_l4_ls__timer5, - &am33xx_l4_ls__timer6, - &am33xx_l4_ls__timer7, &am33xx_l3_main__tpcc, - &am33xx_l4_ls__spinlock, - &am33xx_l4_ls__elm, - &am33xx_l4_ls__epwmss0, - &am33xx_l4_ls__epwmss1, - &am33xx_l4_ls__epwmss2, &am33xx_l3_s__gpmc, - &am33xx_l4_ls__mcspi0, - &am33xx_l4_ls__mcspi1, &am33xx_l3_main__tptc0, &am33xx_l3_main__tptc1, &am33xx_l3_main__tptc2, &am33xx_l3_main__ocmc, - &am33xx_l3_main__sha0, - &am33xx_l3_main__aes0, - &am43xx_l3_main__des, - &am43xx_l4_ls__ocp2scp0, - &am43xx_l4_ls__ocp2scp1, &am43xx_l3_s__usbotgss0, &am43xx_l3_s__usbotgss1, &am43xx_dss__l3_main, &am43xx_l4_ls__dss, &am43xx_l4_ls__dss_dispc, &am43xx_l4_ls__dss_rfbi, - &am43xx_l3__vpfe0, - &am43xx_l3__vpfe1, - &am43xx_l4_ls__vpfe0, - &am43xx_l4_ls__vpfe1, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 292f544bd62d..b7c51ea8c9a6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -18,9 +18,6 @@ */ #include <linux/io.h> -#include <linux/power/smartreflex.h> - -#include <linux/omap-dma.h> #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" @@ -32,9 +29,6 @@ /* Base offset for all OMAP4 interrupts external to MPUSS */ #define OMAP44XX_IRQ_GIC_START 32 -/* Base offset for all OMAP4 dma requests */ -#define OMAP44XX_DMA_REQ_START 1 - /* * IP blocks */ @@ -238,43 +232,6 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { */ /* - * 'aess' class - * audio engine sub system - */ - -static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | - MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_aess_hwmod_class = { - .name = "aess", - .sysc = &omap44xx_aess_sysc, - .enable_preprogram = omap_hwmod_aess_preprogram, -}; - -/* aess */ -static struct omap_hwmod omap44xx_aess_hwmod = { - .name = "aess", - .class = &omap44xx_aess_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "aess_fclk", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, - .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* * 'counter' class * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock */ @@ -399,87 +356,6 @@ static struct omap_hwmod omap44xx_debugss_hwmod = { }; /* - * 'dma' class - * dma controller for data exchange between memory to memory (i.e. internal or - * external memory) and gp peripherals to memory or memory to gp peripherals - */ - -static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x002c, - .syss_offs = 0x0028, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_dma_hwmod_class = { - .name = "dma", - .sysc = &omap44xx_dma_sysc, -}; - -/* dma dev_attr */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - -/* dma_system */ -static struct omap_hwmod omap44xx_dma_system_hwmod = { - .name = "dma_system", - .class = &omap44xx_dma_hwmod_class, - .clkdm_name = "l3_dma_clkdm", - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, - }, - }, - .dev_attr = &dma_dev_attr, -}; - -/* - * 'dmic' class - * digital microphone controller - */ - -static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { - .name = "dmic", - .sysc = &omap44xx_dmic_sysc, -}; - -/* dmic */ -static struct omap_hwmod omap44xx_dmic_hwmod = { - .name = "dmic", - .class = &omap44xx_dmic_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "func_dmic_abe_gfclk", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* * 'dsp' class * dsp sub-system */ @@ -777,66 +653,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), }; -/* sha0 HIB2 (the 'P' (public) device) */ -static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = { - .rev_offs = 0x100, - .sysc_offs = 0x110, - .syss_offs = 0x114, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class omap44xx_sha0_hwmod_class = { - .name = "sham", - .sysc = &omap44xx_sha0_sysc, -}; -static struct omap_hwmod omap44xx_sha0_hwmod = { - .name = "sham", - .class = &omap44xx_sha0_hwmod_class, - .clkdm_name = "l4_secure_clkdm", - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'elm' class - * bch error location module - */ - -static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_elm_hwmod_class = { - .name = "elm", - .sysc = &omap44xx_elm_sysc, -}; - -/* elm */ -static struct omap_hwmod omap44xx_elm_hwmod = { - .name = "elm", - .class = &omap44xx_elm_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, - }, - }, -}; /* * 'emif' class @@ -885,147 +702,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = { }; /* - Crypto modules AES0/1 belong to: - PD_L4_PER power domain - CD_L4_SEC clock domain - On the L3, the AES modules are mapped to - L3_CLK2: Peripherals and multimedia sub clock domain -*/ -static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = { - .rev_offs = 0x80, - .sysc_offs = 0x84, - .syss_offs = 0x88, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class omap44xx_aes_hwmod_class = { - .name = "aes", - .sysc = &omap44xx_aes_sysc, -}; - -static struct omap_hwmod omap44xx_aes1_hwmod = { - .name = "aes1", - .class = &omap44xx_aes_hwmod_class, - .clkdm_name = "l4_secure_clkdm", - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET, - .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_aes1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod omap44xx_aes2_hwmod = { - .name = "aes2", - .class = &omap44xx_aes_hwmod_class, - .clkdm_name = "l4_secure_clkdm", - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET, - .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_aes2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* - * 'des' class for DES3DES module - */ -static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = { - .rev_offs = 0x30, - .sysc_offs = 0x34, - .syss_offs = 0x38, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class omap44xx_des_hwmod_class = { - .name = "des", - .sysc = &omap44xx_des_sysc, -}; - -static struct omap_hwmod omap44xx_des_hwmod = { - .name = "des", - .class = &omap44xx_des_hwmod_class, - .clkdm_name = "l4_secure_clkdm", - .main_clk = "l3_div_ck", - .prcm = { - .omap4 = { - .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET, - .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_des_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* - * 'fdif' class - * face detection hw accelerator module - */ - -static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - /* - * FDIF needs 100 OCP clk cycles delay after a softreset before - * accessing sysconfig again. - * The lowest frequency at the moment for L3 bus is 100 MHz, so - * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). - * - * TODO: Indicate errata when available. - */ - .srst_udelay = 2, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { - .name = "fdif", - .sysc = &omap44xx_fdif_sysc, -}; - -/* fdif */ -static struct omap_hwmod omap44xx_fdif_hwmod = { - .name = "fdif", - .class = &omap44xx_fdif_hwmod_class, - .clkdm_name = "iss_clkdm", - .main_clk = "fdif_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* * 'gpmc' class * general purpose memory controller */ @@ -1063,45 +739,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { /* - * 'hsi' class - * mipi high-speed synchronous serial interface (multichannel and full-duplex - * serial if) - */ - -static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | - SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { - .name = "hsi", - .sysc = &omap44xx_hsi_sysc, -}; - -/* hsi */ -static struct omap_hwmod omap44xx_hsi_hwmod = { - .name = "hsi", - .class = &omap44xx_hsi_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "hsi_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* * 'ipu' class * imaging processor unit */ @@ -1218,177 +855,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = { }; /* - * 'kbd' class - * keyboard controller - */ - -static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { - .name = "kbd", - .sysc = &omap44xx_kbd_sysc, -}; - -/* kbd */ -static struct omap_hwmod omap44xx_kbd_hwmod = { - .name = "kbd", - .class = &omap44xx_kbd_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .main_clk = "sys_32k_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - - -/* - * 'mcpdm' class - * multi channel pdm controller (proprietary interface with phoenix power - * ic) - */ - -static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { - .name = "mcpdm", - .sysc = &omap44xx_mcpdm_sysc, -}; - -/* mcpdm */ -static struct omap_hwmod omap44xx_mcpdm_hwmod = { - .name = "mcpdm", - .class = &omap44xx_mcpdm_hwmod_class, - .clkdm_name = "abe_clkdm", - /* - * It's suspected that the McPDM requires an off-chip main - * functional clock, controlled via I2C. This IP block is - * currently reset very early during boot, before I2C is - * available, so it doesn't seem that we have any choice in - * the kernel other than to avoid resetting it. - * - * Also, McPDM needs to be configured to NO_IDLE mode when it - * is in used otherwise vital clocks will be gated which - * results 'slow motion' audio playback. - */ - .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, - .main_clk = "pad_clks_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'mmu' class - * The memory management unit performs virtual to physical address translation - * for its requestors. - */ - -static struct omap_hwmod_class_sysconfig mmu_sysc = { - .rev_offs = 0x000, - .sysc_offs = 0x010, - .syss_offs = 0x014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { - .name = "mmu", - .sysc = &mmu_sysc, -}; - -/* mmu ipu */ - -static struct omap_hwmod omap44xx_mmu_ipu_hwmod; -static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { - { .name = "mmu_cache", .rst_shift = 2 }, -}; - -/* l3_main_2 -> mmu_ipu */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_mmu_ipu_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { - .name = "mmu_ipu", - .class = &omap44xx_mmu_hwmod_class, - .clkdm_name = "ducati_clkdm", - .rst_lines = omap44xx_mmu_ipu_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), - .main_clk = "ducati_clk_mux_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, - .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* mmu dsp */ - -static struct omap_hwmod omap44xx_mmu_dsp_hwmod; -static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { - { .name = "mmu_cache", .rst_shift = 1 }, -}; - -/* l4_cfg -> dsp */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_mmu_dsp_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { - .name = "mmu_dsp", - .class = &omap44xx_mmu_hwmod_class, - .clkdm_name = "tesla_clkdm", - .rst_lines = omap44xx_mmu_dsp_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), - .main_clk = "dpll_iva_m4x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, - .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* * 'mpu' class * mpu sub-system */ @@ -1434,51 +900,6 @@ static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { }, }; -/* - * 'ocp2scp' class - * bridge to transform ocp interface protocol to scp (serial control port) - * protocol - */ - -static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { - .name = "ocp2scp", - .sysc = &omap44xx_ocp2scp_sysc, -}; - -/* ocp2scp_usb_phy */ -static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { - .name = "ocp2scp_usb_phy", - .class = &omap44xx_ocp2scp_hwmod_class, - .clkdm_name = "l3_init_clkdm", - /* - * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP - * block as an "optional clock," and normally should never be - * specified as the main_clk for an OMAP IP block. However it - * turns out that this clock is actually the main clock for - * the ocp2scp_usb_phy IP block: - * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html - * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems - * to be the best workaround. - */ - .main_clk = "ocp2scp_usb_phy_phy_48m", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; /* * 'prcm' class @@ -1585,189 +1006,6 @@ static struct omap_hwmod omap44xx_sl2if_hwmod = { }; /* - * 'slimbus' class - * bidirectional, multi-drop, multi-channel two-line serial interface between - * the device and external components - */ - -static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { - .name = "slimbus", - .sysc = &omap44xx_slimbus_sysc, -}; - -/* slimbus1 */ -static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { - { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, - { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, - { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, - { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, -}; - -static struct omap_hwmod omap44xx_slimbus1_hwmod = { - .name = "slimbus1", - .class = &omap44xx_slimbus_hwmod_class, - .clkdm_name = "abe_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = slimbus1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), -}; - -/* slimbus2 */ -static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { - { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, - { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, - { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, -}; - -static struct omap_hwmod omap44xx_slimbus2_hwmod = { - .name = "slimbus2", - .class = &omap44xx_slimbus_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = slimbus2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), -}; - -/* - * 'smartreflex' class - * smartreflex module (monitor silicon performance and outputs a measure of - * performance error) - */ - -/* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { - .rev_offs = -ENODEV, - .sysc_offs = 0x0038, - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap36xx_sr_sysc_fields, -}; - -static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { - .name = "smartreflex", - .sysc = &omap44xx_smartreflex_sysc, -}; - -/* smartreflex_core */ -static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { - .sensor_voltdm_name = "core", -}; - -static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { - .name = "smartreflex_core", - .class = &omap44xx_smartreflex_hwmod_class, - .clkdm_name = "l4_ao_clkdm", - - .main_clk = "smartreflex_core_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &smartreflex_core_dev_attr, -}; - -/* smartreflex_iva */ -static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { - .sensor_voltdm_name = "iva", -}; - -static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { - .name = "smartreflex_iva", - .class = &omap44xx_smartreflex_hwmod_class, - .clkdm_name = "l4_ao_clkdm", - .main_clk = "smartreflex_iva_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &smartreflex_iva_dev_attr, -}; - -/* smartreflex_mpu */ -static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { - .sensor_voltdm_name = "mpu", -}; - -static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { - .name = "smartreflex_mpu", - .class = &omap44xx_smartreflex_hwmod_class, - .clkdm_name = "l4_ao_clkdm", - .main_clk = "smartreflex_mpu_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &smartreflex_mpu_dev_attr, -}; - -/* - * 'spinlock' class - * spinlock provides hardware assistance for synchronizing the processes - * running on multiple processors - */ - -static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { - .name = "spinlock", - .sysc = &omap44xx_spinlock_sysc, -}; - -/* spinlock */ -static struct omap_hwmod omap44xx_spinlock_hwmod = { - .name = "spinlock", - .class = &omap44xx_spinlock_hwmod_class, - .clkdm_name = "l4_cfg_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, - }, - }, -}; - -/* * 'timer' class * general purpose timer module with accurate 1ms tick * This class contains several variants: ['timer_1ms', 'timer'] @@ -1790,21 +1028,6 @@ static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { .sysc = &omap44xx_timer_1ms_sysc, }; -static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_timer_hwmod_class = { - .name = "timer", - .sysc = &omap44xx_timer_sysc, -}; - /* timer1 */ static struct omap_hwmod omap44xx_timer1_hwmod = { .name = "timer1", @@ -1821,158 +1044,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { }, }; -/* timer2 */ -static struct omap_hwmod omap44xx_timer2_hwmod = { - .name = "timer2", - .class = &omap44xx_timer_1ms_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "cm2_dm2_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer3 */ -static struct omap_hwmod omap44xx_timer3_hwmod = { - .name = "timer3", - .class = &omap44xx_timer_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .main_clk = "cm2_dm3_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer4 */ -static struct omap_hwmod omap44xx_timer4_hwmod = { - .name = "timer4", - .class = &omap44xx_timer_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .main_clk = "cm2_dm4_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer5 */ -static struct omap_hwmod omap44xx_timer5_hwmod = { - .name = "timer5", - .class = &omap44xx_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "timer5_sync_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer6 */ -static struct omap_hwmod omap44xx_timer6_hwmod = { - .name = "timer6", - .class = &omap44xx_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "timer6_sync_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer7 */ -static struct omap_hwmod omap44xx_timer7_hwmod = { - .name = "timer7", - .class = &omap44xx_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "timer7_sync_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer8 */ -static struct omap_hwmod omap44xx_timer8_hwmod = { - .name = "timer8", - .class = &omap44xx_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "timer8_sync_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer9 */ -static struct omap_hwmod omap44xx_timer9_hwmod = { - .name = "timer9", - .class = &omap44xx_timer_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .main_clk = "cm2_dm9_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer10 */ -static struct omap_hwmod omap44xx_timer10_hwmod = { - .name = "timer10", - .class = &omap44xx_timer_1ms_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "cm2_dm10_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer11 */ -static struct omap_hwmod omap44xx_timer11_hwmod = { - .name = "timer11", - .class = &omap44xx_timer_hwmod_class, - .clkdm_name = "l4_per_clkdm", - .main_clk = "cm2_dm11_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'usb_host_fs' class * full-speed usb host controller @@ -2213,30 +1284,6 @@ static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { - .master = &omap44xx_dma_system_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* fdif -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { - .master = &omap44xx_fdif_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* hsi -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { - .master = &omap44xx_hsi_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* ipu -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { .master = &omap44xx_ipu_hwmod, @@ -2317,14 +1364,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* aess -> l4_abe */ -static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = { - .master = &omap44xx_aess_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* dsp -> l4_abe */ static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { .master = &omap44xx_dsp_hwmod, @@ -2389,22 +1428,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_abe -> aess */ -static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> aess (dma) */ -static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, -}; - /* l4_wkup -> counter_32k */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { .master = &omap44xx_l4_wkup_hwmod, @@ -2453,22 +1476,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_dma_system_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe -> dmic */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* dsp -> iva */ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { .master = &omap44xx_dsp_hwmod, @@ -2605,30 +1612,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { .user = OCP_USER_MPU, }; -/* l3_main_2 -> sham */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_sha0_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> elm */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_elm_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> fdif */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_fdif_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_2 -> gpmc */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { .master = &omap44xx_l3_main_2_hwmod, @@ -2637,14 +1620,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> hsi */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_hsi_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_2 -> ipu */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { .master = &omap44xx_l3_main_2_hwmod, @@ -2677,22 +1652,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { .user = OCP_USER_MPU, }; -/* l4_wkup -> kbd */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_kbd_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe -> mcpdm */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_2 -> ocmc_ram */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { .master = &omap44xx_l3_main_2_hwmod, @@ -2701,14 +1660,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> ocp2scp_usb_phy */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_ocp2scp_usb_phy_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mpu_private -> prcm_mpu */ static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { .master = &omap44xx_mpu_private_hwmod, @@ -2757,62 +1708,6 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_abe -> slimbus1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_slimbus1_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> slimbus1 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_slimbus1_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, -}; - -/* l4_per -> slimbus2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_slimbus2_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> smartreflex_core */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_core_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> smartreflex_iva */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_iva_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> smartreflex_mpu */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_mpu_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> spinlock */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_spinlock_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> timer1 */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { .master = &omap44xx_l4_wkup_hwmod, @@ -2821,86 +1716,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer2_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer3_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer4_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe -> timer5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe -> timer6 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe -> timer7 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe -> timer8 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer9_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> timer10 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer10_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> timer11 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer11_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_cfg -> usb_host_fs */ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { .master = &omap44xx_l4_cfg_hwmod, @@ -2953,9 +1768,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_cfg__l3_main_1, &omap44xx_mpu__l3_main_1, &omap44xx_debugss__l3_main_2, - &omap44xx_dma_system__l3_main_2, - &omap44xx_fdif__l3_main_2, - &omap44xx_hsi__l3_main_2, &omap44xx_ipu__l3_main_2, &omap44xx_iss__l3_main_2, &omap44xx_iva__l3_main_2, @@ -2966,7 +1778,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_main_1__l3_main_3, &omap44xx_l3_main_2__l3_main_3, &omap44xx_l4_cfg__l3_main_3, - &omap44xx_aess__l4_abe, &omap44xx_dsp__l4_abe, &omap44xx_l3_main_1__l4_abe, &omap44xx_mpu__l4_abe, @@ -2975,16 +1786,12 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_cfg__l4_wkup, &omap44xx_mpu__mpu_private, &omap44xx_l4_cfg__ocp_wp_noc, - &omap44xx_l4_abe__aess, - &omap44xx_l4_abe__aess_dma, &omap44xx_l4_wkup__counter_32k, &omap44xx_l4_cfg__ctrl_module_core, &omap44xx_l4_cfg__ctrl_module_pad_core, &omap44xx_l4_wkup__ctrl_module_wkup, &omap44xx_l4_wkup__ctrl_module_pad_wkup, &omap44xx_l3_instr__debugss, - &omap44xx_l4_cfg__dma_system, - &omap44xx_l4_abe__dmic, &omap44xx_dsp__iva, /* &omap44xx_dsp__sl2if, */ &omap44xx_l4_cfg__dsp, @@ -3002,53 +1809,24 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__dss_rfbi, &omap44xx_l3_main_2__dss_venc, &omap44xx_l4_per__dss_venc, - &omap44xx_l4_per__elm, - &omap44xx_l4_cfg__fdif, &omap44xx_l3_main_2__gpmc, - &omap44xx_l4_cfg__hsi, &omap44xx_l3_main_2__ipu, &omap44xx_l3_main_2__iss, /* &omap44xx_iva__sl2if, */ &omap44xx_l3_main_2__iva, - &omap44xx_l4_wkup__kbd, - &omap44xx_l4_abe__mcpdm, - &omap44xx_l3_main_2__mmu_ipu, - &omap44xx_l4_cfg__mmu_dsp, &omap44xx_l3_main_2__ocmc_ram, - &omap44xx_l4_cfg__ocp2scp_usb_phy, &omap44xx_mpu_private__prcm_mpu, &omap44xx_l4_wkup__cm_core_aon, &omap44xx_l4_cfg__cm_core, &omap44xx_l4_wkup__prm, &omap44xx_l4_wkup__scrm, /* &omap44xx_l3_main_2__sl2if, */ - &omap44xx_l4_abe__slimbus1, - &omap44xx_l4_abe__slimbus1_dma, - &omap44xx_l4_per__slimbus2, - &omap44xx_l4_cfg__smartreflex_core, - &omap44xx_l4_cfg__smartreflex_iva, - &omap44xx_l4_cfg__smartreflex_mpu, - &omap44xx_l4_cfg__spinlock, &omap44xx_l4_wkup__timer1, - &omap44xx_l4_per__timer2, - &omap44xx_l4_per__timer3, - &omap44xx_l4_per__timer4, - &omap44xx_l4_abe__timer5, - &omap44xx_l4_abe__timer6, - &omap44xx_l4_abe__timer7, - &omap44xx_l4_abe__timer8, - &omap44xx_l4_per__timer9, - &omap44xx_l4_per__timer10, - &omap44xx_l4_per__timer11, /* &omap44xx_l4_cfg__usb_host_fs, */ &omap44xx_l4_cfg__usb_host_hs, &omap44xx_l4_cfg__usb_tll_hs, &omap44xx_mpu__emif1, &omap44xx_mpu__emif2, - &omap44xx_l3_main_2__aes1, - &omap44xx_l3_main_2__aes2, - &omap44xx_l3_main_2__des, - &omap44xx_l3_main_2__sha0, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index cc5ad6acab1d..ad398f6bc011 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -17,8 +17,6 @@ #include <linux/io.h> #include <linux/power/smartreflex.h> -#include <linux/omap-dma.h> - #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" #include "cm1_54xx.h" @@ -28,10 +26,6 @@ /* Base offset for all OMAP5 interrupts external to MPUSS */ #define OMAP54XX_IRQ_GIC_START 32 -/* Base offset for all OMAP5 dma requests */ -#define OMAP54XX_DMA_REQ_START 1 - - /* * IP blocks */ @@ -233,87 +227,6 @@ static struct omap_hwmod omap54xx_counter_32k_hwmod = { }; /* - * 'dma' class - * dma controller for data exchange between memory to memory (i.e. internal or - * external memory) and gp peripherals to memory or memory to gp peripherals - */ - -static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x002c, - .syss_offs = 0x0028, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_dma_hwmod_class = { - .name = "dma", - .sysc = &omap54xx_dma_sysc, -}; - -/* dma dev_attr */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - -/* dma_system */ -static struct omap_hwmod omap54xx_dma_system_hwmod = { - .name = "dma_system", - .class = &omap54xx_dma_hwmod_class, - .clkdm_name = "dma_clkdm", - .main_clk = "l3_iclk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, - }, - }, - .dev_attr = &dma_dev_attr, -}; - -/* - * 'dmic' class - * digital microphone controller - */ - -static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap54xx_dmic_hwmod_class = { - .name = "dmic", - .sysc = &omap54xx_dmic_sysc, -}; - -/* dmic */ -static struct omap_hwmod omap54xx_dmic_hwmod = { - .name = "dmic", - .class = &omap54xx_dmic_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "dmic_gfclk", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* * 'dss' class * display sub-system */ @@ -593,154 +506,8 @@ static struct omap_hwmod omap54xx_emif2_hwmod = { }, }; -/* - * 'kbd' class - * keyboard controller - */ - -static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_kbd_hwmod_class = { - .name = "kbd", - .sysc = &omap54xx_kbd_sysc, -}; - -/* kbd */ -static struct omap_hwmod omap54xx_kbd_hwmod = { - .name = "kbd", - .class = &omap54xx_kbd_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .main_clk = "sys_32k_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'mcpdm' class - * multi channel pdm controller (proprietary interface with phoenix power - * ic) - */ - -static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = { - .name = "mcpdm", - .sysc = &omap54xx_mcpdm_sysc, -}; - -/* mcpdm */ -static struct omap_hwmod omap54xx_mcpdm_hwmod = { - .name = "mcpdm", - .class = &omap54xx_mcpdm_hwmod_class, - .clkdm_name = "abe_clkdm", - /* - * It's suspected that the McPDM requires an off-chip main - * functional clock, controlled via I2C. This IP block is - * currently reset very early during boot, before I2C is - * available, so it doesn't seem that we have any choice in - * the kernel other than to avoid resetting it. XXX This is - * really a hardware issue workaround: every IP block should - * be able to source its main functional clock from either - * on-chip or off-chip sources. McPDM seems to be the only - * current exception. - */ - - .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, - .main_clk = "pad_clks_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'mmu' class - * The memory management unit performs virtual to physical address translation - * for its requestors. - */ -static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_mmu_hwmod_class = { - .name = "mmu", - .sysc = &omap54xx_mmu_sysc, -}; - -static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = { - { .name = "mmu_cache", .rst_shift = 1 }, -}; - -static struct omap_hwmod omap54xx_mmu_dsp_hwmod = { - .name = "mmu_dsp", - .class = &omap54xx_mmu_hwmod_class, - .clkdm_name = "dsp_clkdm", - .rst_lines = omap54xx_mmu_dsp_resets, - .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets), - .main_clk = "dpll_iva_h11x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, - .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* mmu ipu */ -static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = { - { .name = "mmu_cache", .rst_shift = 2 }, -}; - -static struct omap_hwmod omap54xx_mmu_ipu_hwmod = { - .name = "mmu_ipu", - .class = &omap54xx_mmu_hwmod_class, - .clkdm_name = "ipu_clkdm", - .rst_lines = omap54xx_mmu_ipu_resets, - .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets), - .main_clk = "dpll_core_h22x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, - .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; /* * 'mpu' class @@ -766,76 +533,6 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { }, }; -/* - * 'spinlock' class - * spinlock provides hardware assistance for synchronizing the processes - * running on multiple processors - */ - -static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = { - .name = "spinlock", - .sysc = &omap54xx_spinlock_sysc, -}; - -/* spinlock */ -static struct omap_hwmod omap54xx_spinlock_hwmod = { - .name = "spinlock", - .class = &omap54xx_spinlock_hwmod_class, - .clkdm_name = "l4cfg_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET, - }, - }, -}; - -/* - * 'ocp2scp' class - * bridge to transform ocp interface protocol to scp (serial control port) - * protocol - */ - -static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = { - .name = "ocp2scp", - .sysc = &omap54xx_ocp2scp_sysc, -}; - -/* ocp2scp1 */ -static struct omap_hwmod omap54xx_ocp2scp1_hwmod = { - .name = "ocp2scp1", - .class = &omap54xx_ocp2scp_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "l4_root_clk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; /* * 'timer' class @@ -858,21 +555,6 @@ static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = { .sysc = &omap54xx_timer_1ms_sysc, }; -static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap54xx_timer_hwmod_class = { - .name = "timer", - .sysc = &omap54xx_timer_sysc, -}; - /* timer1 */ static struct omap_hwmod omap54xx_timer1_hwmod = { .name = "timer1", @@ -889,158 +571,6 @@ static struct omap_hwmod omap54xx_timer1_hwmod = { }, }; -/* timer2 */ -static struct omap_hwmod omap54xx_timer2_hwmod = { - .name = "timer2", - .class = &omap54xx_timer_1ms_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer2_gfclk_mux", - .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer3 */ -static struct omap_hwmod omap54xx_timer3_hwmod = { - .name = "timer3", - .class = &omap54xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer3_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer4 */ -static struct omap_hwmod omap54xx_timer4_hwmod = { - .name = "timer4", - .class = &omap54xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer4_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer5 */ -static struct omap_hwmod omap54xx_timer5_hwmod = { - .name = "timer5", - .class = &omap54xx_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "timer5_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer6 */ -static struct omap_hwmod omap54xx_timer6_hwmod = { - .name = "timer6", - .class = &omap54xx_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "timer6_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer7 */ -static struct omap_hwmod omap54xx_timer7_hwmod = { - .name = "timer7", - .class = &omap54xx_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "timer7_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer8 */ -static struct omap_hwmod omap54xx_timer8_hwmod = { - .name = "timer8", - .class = &omap54xx_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .main_clk = "timer8_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer9 */ -static struct omap_hwmod omap54xx_timer9_hwmod = { - .name = "timer9", - .class = &omap54xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer9_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer10 */ -static struct omap_hwmod omap54xx_timer10_hwmod = { - .name = "timer10", - .class = &omap54xx_timer_1ms_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer10_gfclk_mux", - .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer11 */ -static struct omap_hwmod omap54xx_timer11_hwmod = { - .name = "timer11", - .class = &omap54xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer11_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'usb_host_hs' class * high-speed multi-port usb host controller @@ -1193,35 +723,6 @@ static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = { .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks), }; - -/* - * 'ocp2scp' class - * bridge to transform ocp interface protocol to scp (serial control port) - * protocol - */ -/* ocp2scp3 */ -static struct omap_hwmod omap54xx_ocp2scp3_hwmod; -/* l4_cfg -> ocp2scp3 */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_ocp2scp3_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod omap54xx_ocp2scp3_hwmod = { - .name = "ocp2scp3", - .class = &omap54xx_ocp2scp_hwmod_class, - .clkdm_name = "l3init_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - /* * 'sata' class * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx) @@ -1303,14 +804,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> mmu_dsp */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_mmu_dsp_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mpu -> l3_main_1 */ static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { .master = &omap54xx_mpu_hwmod, @@ -1335,14 +828,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_2 -> mmu_ipu */ -static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = { - .master = &omap54xx_l3_main_2_hwmod, - .slave = &omap54xx_mmu_ipu_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> l3_main_3 */ static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { .master = &omap54xx_l3_main_1_hwmod, @@ -1423,22 +908,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_dma_system_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe -> dmic */ -static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = { - .master = &omap54xx_l4_abe_hwmod, - .slave = &omap54xx_dmic_hwmod, - .clk = "abe_iclk", - .user = OCP_USER_MPU, -}; - /* l3_main_2 -> dss */ static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = { .master = &omap54xx_l3_main_2_hwmod, @@ -1503,22 +972,6 @@ static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> kbd */ -static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = { - .master = &omap54xx_l4_wkup_hwmod, - .slave = &omap54xx_kbd_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe -> mcpdm */ -static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = { - .master = &omap54xx_l4_abe_hwmod, - .slave = &omap54xx_mcpdm_hwmod, - .clk = "abe_iclk", - .user = OCP_USER_MPU, -}; - /* l4_cfg -> mpu */ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { .master = &omap54xx_l4_cfg_hwmod, @@ -1527,22 +980,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> spinlock */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_spinlock_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> ocp2scp1 */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_ocp2scp1_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> timer1 */ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { .master = &omap54xx_l4_wkup_hwmod, @@ -1551,86 +988,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = { - .master = &omap54xx_l4_per_hwmod, - .slave = &omap54xx_timer2_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = { - .master = &omap54xx_l4_per_hwmod, - .slave = &omap54xx_timer3_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = { - .master = &omap54xx_l4_per_hwmod, - .slave = &omap54xx_timer4_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe -> timer5 */ -static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = { - .master = &omap54xx_l4_abe_hwmod, - .slave = &omap54xx_timer5_hwmod, - .clk = "abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> timer6 */ -static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = { - .master = &omap54xx_l4_abe_hwmod, - .slave = &omap54xx_timer6_hwmod, - .clk = "abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> timer7 */ -static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = { - .master = &omap54xx_l4_abe_hwmod, - .slave = &omap54xx_timer7_hwmod, - .clk = "abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> timer8 */ -static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = { - .master = &omap54xx_l4_abe_hwmod, - .slave = &omap54xx_timer8_hwmod, - .clk = "abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = { - .master = &omap54xx_l4_per_hwmod, - .slave = &omap54xx_timer9_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> timer10 */ -static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = { - .master = &omap54xx_l4_per_hwmod, - .slave = &omap54xx_timer10_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> timer11 */ -static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = { - .master = &omap54xx_l4_per_hwmod, - .slave = &omap54xx_timer11_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_cfg -> usb_host_hs */ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = { .master = &omap54xx_l4_cfg_hwmod, @@ -1673,9 +1030,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_1__l4_wkup, &omap54xx_mpu__mpu_private, &omap54xx_l4_wkup__counter_32k, - &omap54xx_l4_cfg__dma_system, - &omap54xx_l4_abe__dmic, - &omap54xx_l4_cfg__mmu_dsp, &omap54xx_l3_main_2__dss, &omap54xx_l3_main_2__dss_dispc, &omap54xx_l3_main_2__dss_dsi1_a, @@ -1684,27 +1038,11 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_2__dss_rfbi, &omap54xx_mpu__emif1, &omap54xx_mpu__emif2, - &omap54xx_l3_main_2__mmu_ipu, - &omap54xx_l4_wkup__kbd, - &omap54xx_l4_abe__mcpdm, &omap54xx_l4_cfg__mpu, - &omap54xx_l4_cfg__spinlock, - &omap54xx_l4_cfg__ocp2scp1, &omap54xx_l4_wkup__timer1, - &omap54xx_l4_per__timer2, - &omap54xx_l4_per__timer3, - &omap54xx_l4_per__timer4, - &omap54xx_l4_abe__timer5, - &omap54xx_l4_abe__timer6, - &omap54xx_l4_abe__timer7, - &omap54xx_l4_abe__timer8, - &omap54xx_l4_per__timer9, - &omap54xx_l4_per__timer10, - &omap54xx_l4_per__timer11, &omap54xx_l4_cfg__usb_host_hs, &omap54xx_l4_cfg__usb_tll_hs, &omap54xx_l4_cfg__usb_otg_ss, - &omap54xx_l4_cfg__ocp2scp3, &omap54xx_l4_cfg__sata, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index f8715bd96687..acef3733db4c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -15,9 +15,6 @@ */ #include <linux/io.h> -#include <linux/power/smartreflex.h> - -#include <linux/omap-dma.h> #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" @@ -29,10 +26,6 @@ /* Base offset for all DRA7XX interrupts external to MPUSS */ #define DRA7XX_IRQ_GIC_START 32 -/* Base offset for all DRA7XX dma requests */ -#define DRA7XX_DMA_REQ_START 1 - - /* * IP blocks */ @@ -284,156 +277,6 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { }; /* - * 'dcan' class - * - */ - -static struct omap_hwmod_class dra7xx_dcan_hwmod_class = { - .name = "dcan", -}; - -/* dcan1 */ -static struct omap_hwmod dra7xx_dcan1_hwmod = { - .name = "dcan1", - .class = &dra7xx_dcan_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .main_clk = "dcan1_sys_clk_mux", - .flags = HWMOD_CLKDM_NOAUTO, - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* dcan2 */ -static struct omap_hwmod dra7xx_dcan2_hwmod = { - .name = "dcan2", - .class = &dra7xx_dcan_hwmod_class, - .clkdm_name = "l4per2_clkdm", - .main_clk = "sys_clkin1", - .flags = HWMOD_CLKDM_NOAUTO, - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* pwmss */ -static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x4, - .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSC_HAS_RESET_STATUS, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -/* - * epwmss class - */ -static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = { - .name = "epwmss", - .sysc = &dra7xx_epwmss_sysc, -}; - -/* epwmss0 */ -static struct omap_hwmod dra7xx_epwmss0_hwmod = { - .name = "epwmss0", - .class = &dra7xx_epwmss_hwmod_class, - .clkdm_name = "l4per2_clkdm", - .main_clk = "l4_root_clk_div", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET, - }, - }, -}; - -/* epwmss1 */ -static struct omap_hwmod dra7xx_epwmss1_hwmod = { - .name = "epwmss1", - .class = &dra7xx_epwmss_hwmod_class, - .clkdm_name = "l4per2_clkdm", - .main_clk = "l4_root_clk_div", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET, - }, - }, -}; - -/* epwmss2 */ -static struct omap_hwmod dra7xx_epwmss2_hwmod = { - .name = "epwmss2", - .class = &dra7xx_epwmss_hwmod_class, - .clkdm_name = "l4per2_clkdm", - .main_clk = "l4_root_clk_div", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET, - }, - }, -}; - -/* - * 'dma' class - * - */ - -static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x002c, - .syss_offs = 0x0028, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class dra7xx_dma_hwmod_class = { - .name = "dma", - .sysc = &dra7xx_dma_sysc, -}; - -/* dma dev_attr */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - -/* dma_system */ -static struct omap_hwmod dra7xx_dma_system_hwmod = { - .name = "dma_system", - .class = &dra7xx_dma_hwmod_class, - .clkdm_name = "dma_clkdm", - .main_clk = "l3_iclk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, - }, - }, - .dev_attr = &dma_dev_attr, -}; - -/* * 'tpcc' class * */ @@ -626,112 +469,9 @@ static struct omap_hwmod dra7xx_dss_hdmi_hwmod = { .parent_hwmod = &dra7xx_dss_hwmod, }; -/* AES (the 'P' (public) device) */ -static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = { - .rev_offs = 0x0080, - .sysc_offs = 0x0084, - .syss_offs = 0x0088, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; -static struct omap_hwmod_class dra7xx_aes_hwmod_class = { - .name = "aes", - .sysc = &dra7xx_aes_sysc, -}; -/* AES1 */ -static struct omap_hwmod dra7xx_aes1_hwmod = { - .name = "aes1", - .class = &dra7xx_aes_hwmod_class, - .clkdm_name = "l4sec_clkdm", - .main_clk = "l3_iclk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* AES2 */ -static struct omap_hwmod dra7xx_aes2_hwmod = { - .name = "aes2", - .class = &dra7xx_aes_hwmod_class, - .clkdm_name = "l4sec_clkdm", - .main_clk = "l3_iclk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* sha0 HIB2 (the 'P' (public) device) */ -static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = { - .rev_offs = 0x100, - .sysc_offs = 0x110, - .syss_offs = 0x114, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class dra7xx_sha0_hwmod_class = { - .name = "sham", - .sysc = &dra7xx_sha0_sysc, -}; -static struct omap_hwmod dra7xx_sha0_hwmod = { - .name = "sham", - .class = &dra7xx_sha0_hwmod_class, - .clkdm_name = "l4sec_clkdm", - .main_clk = "l3_iclk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* - * 'elm' class - * - */ - -static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class dra7xx_elm_hwmod_class = { - .name = "elm", - .sysc = &dra7xx_elm_sysc, -}; - -/* elm */ - -static struct omap_hwmod dra7xx_elm_hwmod = { - .name = "elm", - .class = &dra7xx_elm_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "l3_iclk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET, - }, - }, -}; /* * 'gpmc' class @@ -797,55 +537,6 @@ static struct omap_hwmod dra7xx_mpu_hwmod = { }, }; -/* - * 'ocp2scp' class - * - */ - -static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = { - .name = "ocp2scp", - .sysc = &dra7xx_ocp2scp_sysc, -}; - -/* ocp2scp1 */ -static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { - .name = "ocp2scp1", - .class = &dra7xx_ocp2scp_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "l4_root_clk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* ocp2scp3 */ -static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { - .name = "ocp2scp3", - .class = &dra7xx_ocp2scp_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "l4_root_clk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; /* * 'PCIE' class @@ -1032,103 +723,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = { }; /* - * 'smartreflex' class - * - */ - -/* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = { - .rev_offs = -ENODEV, - .sysc_offs = 0x0038, - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap36xx_sr_sysc_fields, -}; - -static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = { - .name = "smartreflex", - .sysc = &dra7xx_smartreflex_sysc, -}; - -/* smartreflex_core */ -/* smartreflex_core dev_attr */ -static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { - .sensor_voltdm_name = "core", -}; - -static struct omap_hwmod dra7xx_smartreflex_core_hwmod = { - .name = "smartreflex_core", - .class = &dra7xx_smartreflex_hwmod_class, - .clkdm_name = "coreaon_clkdm", - .main_clk = "wkupaon_iclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &smartreflex_core_dev_attr, -}; - -/* smartreflex_mpu */ -/* smartreflex_mpu dev_attr */ -static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { - .sensor_voltdm_name = "mpu", -}; - -static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = { - .name = "smartreflex_mpu", - .class = &dra7xx_smartreflex_hwmod_class, - .clkdm_name = "coreaon_clkdm", - .main_clk = "wkupaon_iclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &smartreflex_mpu_dev_attr, -}; - -/* - * 'spinlock' class - * - */ - -static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = { - .name = "spinlock", - .sysc = &dra7xx_spinlock_sysc, -}; - -/* spinlock */ -static struct omap_hwmod dra7xx_spinlock_hwmod = { - .name = "spinlock", - .class = &dra7xx_spinlock_hwmod_class, - .clkdm_name = "l4cfg_clkdm", - .main_clk = "l3_iclk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET, - }, - }, -}; - -/* * 'timer' class * * This class contains several variants: ['timer_1ms', 'timer_secure', @@ -1225,213 +819,6 @@ static struct omap_hwmod dra7xx_timer4_hwmod = { }, }; -/* timer5 */ -static struct omap_hwmod dra7xx_timer5_hwmod = { - .name = "timer5", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "ipu_clkdm", - .main_clk = "timer5_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer6 */ -static struct omap_hwmod dra7xx_timer6_hwmod = { - .name = "timer6", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "ipu_clkdm", - .main_clk = "timer6_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer7 */ -static struct omap_hwmod dra7xx_timer7_hwmod = { - .name = "timer7", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "ipu_clkdm", - .main_clk = "timer7_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer8 */ -static struct omap_hwmod dra7xx_timer8_hwmod = { - .name = "timer8", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "ipu_clkdm", - .main_clk = "timer8_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer9 */ -static struct omap_hwmod dra7xx_timer9_hwmod = { - .name = "timer9", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer9_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer10 */ -static struct omap_hwmod dra7xx_timer10_hwmod = { - .name = "timer10", - .class = &dra7xx_timer_1ms_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer10_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer11 */ -static struct omap_hwmod dra7xx_timer11_hwmod = { - .name = "timer11", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer11_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer12 */ -static struct omap_hwmod dra7xx_timer12_hwmod = { - .name = "timer12", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .main_clk = "secure_32k_clk_src_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET, - }, - }, -}; - -/* timer13 */ -static struct omap_hwmod dra7xx_timer13_hwmod = { - .name = "timer13", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per3_clkdm", - .main_clk = "timer13_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer14 */ -static struct omap_hwmod dra7xx_timer14_hwmod = { - .name = "timer14", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per3_clkdm", - .main_clk = "timer14_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer15 */ -static struct omap_hwmod dra7xx_timer15_hwmod = { - .name = "timer15", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per3_clkdm", - .main_clk = "timer15_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer16 */ -static struct omap_hwmod dra7xx_timer16_hwmod = { - .name = "timer16", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per3_clkdm", - .main_clk = "timer16_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* DES (the 'P' (public) device) */ -static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = { - .rev_offs = 0x0030, - .sysc_offs = 0x0034, - .syss_offs = 0x0038, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class dra7xx_des_hwmod_class = { - .name = "des", - .sysc = &dra7xx_des_sysc, -}; - -/* DES */ -static struct omap_hwmod dra7xx_des_hwmod = { - .name = "des", - .class = &dra7xx_des_hwmod_class, - .clkdm_name = "l4sec_clkdm", - .main_clk = "l3_iclk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - /* * 'usb_otg_ss' class * @@ -1690,30 +1077,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> dcan1 */ -static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = { - .master = &dra7xx_l4_wkup_hwmod, - .slave = &dra7xx_dcan1_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per2 -> dcan2 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = { - .master = &dra7xx_l4_per2_hwmod, - .slave = &dra7xx_dcan2_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = { - .master = &dra7xx_l4_cfg_hwmod, - .slave = &dra7xx_dma_system_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> tpcc */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = { .master = &dra7xx_l3_main_1_hwmod, @@ -1762,38 +1125,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_1 -> aes1 */ -static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = { - .master = &dra7xx_l3_main_1_hwmod, - .slave = &dra7xx_aes1_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_1 -> aes2 */ -static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = { - .master = &dra7xx_l3_main_1_hwmod, - .slave = &dra7xx_aes2_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_1 -> sha0 */ -static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = { - .master = &dra7xx_l3_main_1_hwmod, - .slave = &dra7xx_sha0_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> elm */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_elm_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> gpmc */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { .master = &dra7xx_l3_main_1_hwmod, @@ -1810,22 +1141,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> ocp2scp1 */ -static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { - .master = &dra7xx_l4_cfg_hwmod, - .slave = &dra7xx_ocp2scp1_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> ocp2scp3 */ -static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { - .master = &dra7xx_l4_cfg_hwmod, - .slave = &dra7xx_ocp2scp3_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> pciess1 */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = { .master = &dra7xx_l3_main_1_hwmod, @@ -1882,30 +1197,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> smartreflex_core */ -static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = { - .master = &dra7xx_l4_cfg_hwmod, - .slave = &dra7xx_smartreflex_core_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> smartreflex_mpu */ -static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = { - .master = &dra7xx_l4_cfg_hwmod, - .slave = &dra7xx_smartreflex_mpu_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> spinlock */ -static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = { - .master = &dra7xx_l4_cfg_hwmod, - .slave = &dra7xx_spinlock_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> timer1 */ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = { .master = &dra7xx_l4_wkup_hwmod, @@ -1938,110 +1229,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per3 -> timer5 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_timer5_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> timer6 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_timer6_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> timer7 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_timer7_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> timer8 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_timer8_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> timer9 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_timer9_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> timer10 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_timer10_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> timer11 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_timer11_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> timer12 */ -static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = { - .master = &dra7xx_l4_wkup_hwmod, - .slave = &dra7xx_timer12_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> timer13 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_timer13_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> timer14 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_timer14_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> timer15 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_timer15_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> timer16 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_timer16_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> des */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_des_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_per3 -> usb_otg_ss1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { .master = &dra7xx_l4_per3_hwmod, @@ -2106,30 +1293,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per2 -> epwmss0 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = { - .master = &dra7xx_l4_per2_hwmod, - .slave = &dra7xx_epwmss0_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU, -}; - -/* l4_per2 -> epwmss1 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = { - .master = &dra7xx_l4_per2_hwmod, - .slave = &dra7xx_epwmss1_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU, -}; - -/* l4_per2 -> epwmss2 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = { - .master = &dra7xx_l4_per2_hwmod, - .slave = &dra7xx_epwmss2_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__dmm, &dra7xx_l3_main_2__l3_instr, @@ -2146,48 +1309,24 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__bb2d, &dra7xx_l4_wkup__counter_32k, &dra7xx_l4_wkup__ctrl_module_wkup, - &dra7xx_l4_wkup__dcan1, - &dra7xx_l4_per2__dcan2, - &dra7xx_l4_cfg__dma_system, &dra7xx_l3_main_1__tpcc, &dra7xx_l3_main_1__tptc0, &dra7xx_l3_main_1__tptc1, &dra7xx_l3_main_1__dss, &dra7xx_l3_main_1__dispc, &dra7xx_l3_main_1__hdmi, - &dra7xx_l3_main_1__aes1, - &dra7xx_l3_main_1__aes2, - &dra7xx_l3_main_1__sha0, - &dra7xx_l4_per1__elm, &dra7xx_l3_main_1__gpmc, &dra7xx_l4_cfg__mpu, - &dra7xx_l4_cfg__ocp2scp1, - &dra7xx_l4_cfg__ocp2scp3, &dra7xx_l3_main_1__pciess1, &dra7xx_l4_cfg__pciess1, &dra7xx_l3_main_1__pciess2, &dra7xx_l4_cfg__pciess2, &dra7xx_l3_main_1__qspi, &dra7xx_l4_cfg__sata, - &dra7xx_l4_cfg__smartreflex_core, - &dra7xx_l4_cfg__smartreflex_mpu, - &dra7xx_l4_cfg__spinlock, &dra7xx_l4_wkup__timer1, &dra7xx_l4_per1__timer2, &dra7xx_l4_per1__timer3, &dra7xx_l4_per1__timer4, - &dra7xx_l4_per3__timer5, - &dra7xx_l4_per3__timer6, - &dra7xx_l4_per3__timer7, - &dra7xx_l4_per3__timer8, - &dra7xx_l4_per1__timer9, - &dra7xx_l4_per1__timer10, - &dra7xx_l4_per1__timer11, - &dra7xx_l4_per3__timer13, - &dra7xx_l4_per3__timer14, - &dra7xx_l4_per3__timer15, - &dra7xx_l4_per3__timer16, - &dra7xx_l4_per1__des, &dra7xx_l4_per3__usb_otg_ss1, &dra7xx_l4_per3__usb_otg_ss2, &dra7xx_l4_per3__usb_otg_ss3, @@ -2195,15 +1334,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per2__vcp1, &dra7xx_l3_main_1__vcp2, &dra7xx_l4_per2__vcp2, - &dra7xx_l4_per2__epwmss0, - &dra7xx_l4_per2__epwmss1, - &dra7xx_l4_per2__epwmss2, - NULL, -}; - -/* GP-only hwmod links */ -static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = { - &dra7xx_l4_wkup__timer12, NULL, }; @@ -2256,8 +1386,5 @@ int __init dra7xx_hwmod_init(void) } } - if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP) - ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs); - return ret; } diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index ca56563e3fec..c85cb8b5831c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -98,7 +98,6 @@ extern struct omap_hwmod_class omap2_hdq1w_class; extern struct omap_hwmod_class omap2xxx_timer_hwmod_class; extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class; extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class; -extern struct omap_hwmod_class omap2xxx_dma_hwmod_class; extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class; extern struct omap_hwmod_class omap2xxx_mcspi_class; diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c index d5ddba00bb73..143623bb056d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_reset.c +++ b/arch/arm/mach-omap2/omap_hwmod_reset.c @@ -26,8 +26,6 @@ #include <linux/kernel.h> #include <linux/errno.h> -#include <sound/aess.h> - #include "omap_hwmod.h" #include "common.h" @@ -41,28 +39,6 @@ #define OMAP_RTC_MAX_READY_TIME 50 /** - * omap_hwmod_aess_preprogram - enable AESS internal autogating - * @oh: struct omap_hwmod * - * - * The AESS will not IdleAck to the PRCM until its internal autogating - * is enabled. Since internal autogating is disabled by default after - * AESS reset, we must enable autogating after the hwmod code resets - * the AESS. Returns 0. - */ -int omap_hwmod_aess_preprogram(struct omap_hwmod *oh) -{ - void __iomem *va; - - va = omap_hwmod_get_mpu_rt_va(oh); - if (!va) - return -EINVAL; - - aess_enable_autogating(va); - - return 0; -} - -/** * omap_rtc_wait_not_busy - Wait for the RTC BUSY flag * @oh: struct omap_hwmod * * diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index ca52271de5a8..dbb7c2acef31 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -23,6 +23,7 @@ #include <linux/platform_data/ti-sysc.h> #include <linux/platform_data/wkup_m3.h> #include <linux/platform_data/asoc-ti-mcbsp.h> +#include <linux/platform_data/ti-prm.h> #include "clockdomain.h" #include "common.h" @@ -42,6 +43,17 @@ struct pdata_init { static struct of_dev_auxdata omap_auxdata_lookup[]; static struct twl4030_gpio_platform_data twl_gpio_auxdata; +#if IS_ENABLED(CONFIG_OMAP_IOMMU) +int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, + u8 *pwrst); +#else +static inline int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, + bool request, u8 *pwrst) +{ + return 0; +} +#endif + #ifdef CONFIG_MACH_NOKIA_N8X0 static void __init omap2420_n8x0_legacy_init(void) { @@ -260,16 +272,6 @@ static void __init omap3_pandora_legacy_init(void) } #endif /* CONFIG_ARCH_OMAP3 */ -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) -static struct iommu_platform_data omap4_iommu_pdata = { - .reset_name = "mmu_cache", - .assert_reset = omap_device_assert_hardreset, - .deassert_reset = omap_device_deassert_hardreset, - .device_enable = omap_device_enable, - .device_idle = omap_device_idle, -}; -#endif - #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) static struct wkup_m3_platform_data wkup_m3_data = { .reset_name = "wkup_m3", @@ -285,6 +287,10 @@ static void __init omap5_uevm_legacy_init(void) #endif #ifdef CONFIG_SOC_DRA7XX +static struct iommu_platform_data dra7_ipu1_dsp_iommu_pdata = { + .set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint, +}; + static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; @@ -306,10 +312,14 @@ static void __init dra7x_evm_mmc_quirk(void) static struct clockdomain *ti_sysc_find_one_clockdomain(struct clk *clk) { + struct clk_hw *hw = __clk_get_hw(clk); struct clockdomain *clkdm = NULL; struct clk_hw_omap *hwclk; - hwclk = to_clk_hw_omap(__clk_get_hw(clk)); + hwclk = to_clk_hw_omap(hw); + if (!omap2_clk_is_hw_omap(hw)) + return NULL; + if (hwclk && hwclk->clkdm_name) clkdm = clkdm_lookup(hwclk->clkdm_name); @@ -408,6 +418,12 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void)) pcs_pdata.rearm = rearm; } +static struct ti_prm_platform_data ti_prm_pdata = { + .clkdm_deny_idle = clkdm_deny_idle, + .clkdm_allow_idle = clkdm_allow_idle, + .clkdm_lookup = clkdm_lookup, +}; + /* * GPIOs for TWL are initialized by the I2C bus and need custom * handing until DSS has device tree bindings. @@ -488,10 +504,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { &wkup_m3_data), #endif #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) - OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu", - &omap4_iommu_pdata), - OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu", - &omap4_iommu_pdata), OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000, "4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]), OF_DEV_AUXDATA("ti,omap4-smartreflex-core", 0x4a0dd000, @@ -506,10 +518,18 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { &dra7_hsmmc_data_mmc2), OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", &dra7_hsmmc_data_mmc3), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu", + &dra7_ipu1_dsp_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu", + &dra7_ipu1_dsp_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu", + &dra7_ipu1_dsp_iommu_pdata), #endif /* Common auxdata */ OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata), OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata), + OF_DEV_AUXDATA("ti,omap-prm-inst", 0, NULL, &ti_prm_pdata), + OF_DEV_AUXDATA("ti,omap-sdma", 0, NULL, &dma_plat_info), { /* sentinel */ }, }; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 1581b6a6a416..6953c47d8dc6 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -83,8 +83,6 @@ static int omap2_enter_full_retention(void) l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); - cpu_cluster_pm_enter(); - /* One last check for pending IRQs to avoid extra latency due * to sleeping unnecessarily. */ if (omap_irq_pending()) @@ -96,8 +94,6 @@ static int omap2_enter_full_retention(void) OMAP_SDRC_REGADDR(SDRC_POWER)); no_sleep: - cpu_cluster_pm_exit(); - clk_enable(osc_ck); /* clear CORE wake-up events */ @@ -162,25 +158,27 @@ static int omap2_can_sleep(void) return 0; if (__clk_is_enabled(osc_ck)) return 0; - if (omap_dma_running()) - return 0; return 1; } static void omap2_pm_idle(void) { - if (!omap2_can_sleep()) { - if (omap_irq_pending()) - return; - omap2_enter_mpu_retention(); - return; - } + int error; if (omap_irq_pending()) return; + error = cpu_cluster_pm_enter(); + if (error || !omap2_can_sleep()) { + omap2_enter_mpu_retention(); + goto out_cpu_cluster_pm; + } + omap2_enter_full_retention(); + +out_cpu_cluster_pm: + cpu_cluster_pm_exit(); } static void __init prcm_setup_regs(void) diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c index f11442ed3eff..7461b0346549 100644 --- a/arch/arm/mach-omap2/pm33xx-core.c +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -28,6 +28,7 @@ #include "prm33xx.h" #include "soc.h" #include "sram.h" +#include "omap-secure.h" static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; static struct clockdomain *gfx_l4ls_clkdm; @@ -166,6 +167,16 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), { int ret = 0; + /* Suspend secure side on HS devices */ + if (omap_type() != OMAP2_DEVICE_TYPE_GP) { + if (optee_available) + omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0); + else + omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND, + FLAG_START_CRITICAL, + 0, 0, 0, 0, 0); + } + amx3_pre_suspend_common(); scu_power_mode(scu_base, SCU_PM_POWEROFF); ret = cpu_suspend(args, fn); @@ -174,6 +185,19 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), if (!am43xx_check_off_mode_enable()) amx3_post_suspend_common(); + /* + * Resume secure side on HS devices. + * + * Note that even on systems with OP-TEE available this resume call is + * issued to the ROM. This is because upon waking from suspend the ROM + * is restored as the secure monitor. On systems with OP-TEE ROM will + * restore OP-TEE during this call. + */ + if (omap_type() != OMAP2_DEVICE_TYPE_GP) + omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME, + FLAG_START_CRITICAL, + 0, 0, 0, 0, 0); + return ret; } diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 54254fc92c2e..e66e9948636c 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -25,7 +25,6 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/slab.h> -#include <linux/omap-dma.h> #include <linux/omap-gpmc.h> #include <trace/events/power.h> @@ -85,7 +84,6 @@ static void omap3_core_save_context(void) omap3_gpmc_save_context(); /* Save the system control module context, padconf already save above*/ omap3_control_save_context(); - omap_dma_global_context_save(); } static void omap3_core_restore_context(void) @@ -96,7 +94,6 @@ static void omap3_core_restore_context(void) omap3_gpmc_restore_context(); /* Restore the interrupt controller context */ omap_intc_restore_context(); - omap_dma_global_context_restore(); } /* @@ -547,9 +544,7 @@ int __init omap3_pm_init(void) local_irq_disable(); - omap_dma_global_context_save(); omap3_save_secure_ram_context(); - omap_dma_global_context_restore(); local_irq_enable(); } diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index e2ad14e77064..7078a61c1d3f 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h @@ -68,6 +68,7 @@ #define AM43XX_CM_PER_ICSS_CDOFFS 0x0300 #define AM43XX_CM_PER_L4LS_CDOFFS 0x0400 #define AM43XX_CM_PER_EMIF_CDOFFS 0x0700 +#define AM43XX_CM_PER_LCDC_CDOFFS 0x0800 #define AM43XX_CM_PER_DSS_CDOFFS 0x0a00 #define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00 #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 |