diff options
Diffstat (limited to 'arch/arm/mach-omap2')
27 files changed, 189 insertions, 1059 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 2f722a805948..c15bbcad5f67 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -232,6 +232,3 @@ obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) obj-y += omap_phy_internal.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o - -onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o -obj-y += $(onenand-m) $(onenand-y) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 518926410b62..b79b1ca9aee9 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1224,14 +1224,6 @@ ccd_exit: return 0; } -u32 clkdm_xlate_address(struct clockdomain *clkdm) -{ - if (arch_clkdm->clkdm_xlate_address) - return arch_clkdm->clkdm_xlate_address(clkdm); - - return 0; -} - /** * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm * @clkdm: struct clockdomain * diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 827f01e2d0af..24667a5a9dc0 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -175,7 +175,6 @@ struct clkdm_ops { void (*clkdm_deny_idle)(struct clockdomain *clkdm); int (*clkdm_clk_enable)(struct clockdomain *clkdm); int (*clkdm_clk_disable)(struct clockdomain *clkdm); - u32 (*clkdm_xlate_address)(struct clockdomain *clkdm); }; int clkdm_register_platform_funcs(struct clkdm_ops *co); @@ -214,7 +213,6 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); -u32 clkdm_xlate_address(struct clockdomain *clkdm); extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index d7a5d11cbcbf..9ff0fc70f152 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -14,38 +14,8 @@ * published by the Free Software Foundation. */ -#define OMAP24XX_EN_CAM_SHIFT 31 -#define OMAP24XX_EN_WDT4_SHIFT 29 -#define OMAP2420_EN_WDT3_SHIFT 28 -#define OMAP24XX_EN_MSPRO_SHIFT 27 -#define OMAP24XX_EN_FAC_SHIFT 25 -#define OMAP2420_EN_EAC_SHIFT 24 -#define OMAP24XX_EN_HDQ_SHIFT 23 -#define OMAP2420_EN_I2C2_SHIFT 20 -#define OMAP2420_EN_I2C1_SHIFT 19 -#define OMAP2430_EN_MCBSP5_SHIFT 5 -#define OMAP2430_EN_MCBSP4_SHIFT 4 -#define OMAP2430_EN_MCBSP3_SHIFT 3 -#define OMAP24XX_EN_SSI_SHIFT 1 -#define OMAP24XX_EN_MPU_WDT_SHIFT 3 -#define OMAP24XX_CLKSEL_MPU_SHIFT 0 -#define OMAP24XX_CLKSEL_MPU_WIDTH 5 #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) -#define OMAP24XX_EN_TV_SHIFT 2 -#define OMAP24XX_EN_DSS2_SHIFT 1 -#define OMAP24XX_EN_DSS1_SHIFT 0 #define OMAP24XX_EN_DSS1_MASK (1 << 0) -#define OMAP2430_EN_I2CHS2_SHIFT 20 -#define OMAP2430_EN_I2CHS1_SHIFT 19 -#define OMAP2430_EN_MMCHSDB2_SHIFT 17 -#define OMAP2430_EN_MMCHSDB1_SHIFT 16 -#define OMAP24XX_EN_MAILBOXES_SHIFT 30 -#define OMAP2430_EN_SDRC_SHIFT 2 -#define OMAP24XX_EN_PKA_SHIFT 4 -#define OMAP24XX_EN_AES_SHIFT 3 -#define OMAP24XX_EN_RNG_SHIFT 2 -#define OMAP24XX_EN_SHA_SHIFT 1 -#define OMAP24XX_EN_DES_SHIFT 0 #define OMAP24XX_ST_MAILBOXES_SHIFT 30 #define OMAP24XX_ST_HDQ_SHIFT 23 #define OMAP2420_ST_I2C2_SHIFT 20 @@ -54,81 +24,30 @@ #define OMAP2430_ST_I2CHS2_SHIFT 20 #define OMAP24XX_ST_MCBSP2_SHIFT 16 #define OMAP24XX_ST_MCBSP1_SHIFT 15 -#define OMAP24XX_ST_DSS_SHIFT 0 #define OMAP2430_ST_MCBSP5_SHIFT 5 #define OMAP2430_ST_MCBSP4_SHIFT 4 #define OMAP2430_ST_MCBSP3_SHIFT 3 #define OMAP24XX_ST_AES_SHIFT 3 #define OMAP24XX_ST_RNG_SHIFT 2 #define OMAP24XX_ST_SHA_SHIFT 1 -#define OMAP24XX_AUTO_SDRC_SHIFT 2 -#define OMAP24XX_AUTO_GPMC_SHIFT 1 -#define OMAP24XX_AUTO_SDMA_SHIFT 0 -#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) -#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) -#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) -#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) -#define OMAP24XX_CLKSEL_L4_SHIFT 5 -#define OMAP24XX_CLKSEL_L4_WIDTH 2 -#define OMAP24XX_CLKSEL_L3_SHIFT 0 -#define OMAP24XX_CLKSEL_L3_WIDTH 5 -#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) -#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) -#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) -#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) -#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) -#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) -#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) -#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) -#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) -#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) -#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) -#define OMAP24XX_EN_3D_SHIFT 2 -#define OMAP24XX_EN_2D_SHIFT 1 #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) -#define OMAP2430_EN_ICR_SHIFT 6 -#define OMAP24XX_EN_OMAPCTRL_SHIFT 5 -#define OMAP24XX_EN_WDT1_SHIFT 4 -#define OMAP24XX_EN_32KSYNC_SHIFT 1 #define OMAP24XX_ST_MPU_WDT_SHIFT 3 #define OMAP24XX_ST_32KSYNC_SHIFT 1 -#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) #define OMAP24XX_EN_54M_PLL_SHIFT 6 #define OMAP24XX_EN_96M_PLL_SHIFT 2 -#define OMAP24XX_EN_DPLL_MASK (0x3 << 0) #define OMAP24XX_ST_54M_APLL_SHIFT 9 #define OMAP24XX_ST_96M_APLL_SHIFT 8 #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) #define OMAP24XX_AUTO_DPLL_SHIFT 0 #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) -#define OMAP24XX_APLLS_CLKIN_SHIFT 23 -#define OMAP24XX_APLLS_CLKIN_WIDTH 3 -#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) -#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) -#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) -#define OMAP24XX_54M_SOURCE_SHIFT 5 -#define OMAP24XX_54M_SOURCE_WIDTH 1 -#define OMAP2430_96M_SOURCE_SHIFT 4 -#define OMAP2430_96M_SOURCE_WIDTH 1 -#define OMAP24XX_48M_SOURCE_MASK (1 << 3) #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) -#define OMAP2420_EN_IVA_COP_SHIFT 10 -#define OMAP2420_EN_IVA_MPU_SHIFT 8 -#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 -#define OMAP2420_EN_DSP_IPI_SHIFT 1 -#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) -#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) -#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) -#define OMAP2430_EN_OSC_SHIFT 1 -#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 -#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index ee6c784cd6b7..38656ce2432c 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -14,68 +14,11 @@ * published by the Free Software Foundation. */ -#define OMAP3430ES2_EN_MMC3_SHIFT 30 -#define OMAP3430_EN_MSPRO_SHIFT 23 -#define OMAP3430_EN_HDQ_SHIFT 22 -#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 -#define OMAP3430ES1_EN_D2D_SHIFT 3 -#define OMAP3430_EN_SSI_SHIFT 0 -#define OMAP3430ES2_EN_USBTLL_SHIFT 2 -#define OMAP3430_EN_WDT2_SHIFT 5 -#define OMAP3430_EN_CAM_SHIFT 0 -#define OMAP3430_EN_WDT3_SHIFT 12 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) -#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 -#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 -#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) -#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_IVA2_DPLL_SHIFT 0 -#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) #define OMAP3430_ST_IVA2_SHIFT 0 -#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) -#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 -#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) -#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 -#define OMAP3430_IVA2_CLK_SRC_WIDTH 3 -#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) -#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) -#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) -#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) -#define OMAP3430_ST_MPU_CLK_SHIFT 0 -#define OMAP3430_ST_MPU_CLK_MASK (1 << 0) -#define OMAP3430_ST_MPU_CLK_WIDTH 1 -#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) -#define OMAP3430_MPU_CLK_SRC_SHIFT 19 -#define OMAP3430_MPU_CLK_SRC_WIDTH 3 -#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) -#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) -#define OMAP3430_EN_MODEM_SHIFT 31 -#define OMAP3430_EN_ICR_SHIFT 29 -#define OMAP3430_EN_AES2_SHIFT 28 -#define OMAP3430_EN_SHA12_SHIFT 27 -#define OMAP3430_EN_DES2_SHIFT 26 -#define OMAP3430ES1_EN_FAC_SHIFT 8 -#define OMAP3430_EN_MAILBOXES_SHIFT 7 -#define OMAP3430_EN_OMAPCTRL_SHIFT 6 -#define OMAP3430_EN_SAD2D_SHIFT 3 -#define OMAP3430_EN_SDRC_SHIFT 1 -#define AM35XX_EN_IPSS_SHIFT 4 -#define OMAP3430_EN_PKA_SHIFT 4 -#define OMAP3430_EN_AES1_SHIFT 3 -#define OMAP3430_EN_RNG_SHIFT 2 -#define OMAP3430_EN_SHA11_SHIFT 1 -#define OMAP3430_EN_DES1_SHIFT 0 -#define OMAP3430_EN_MAD2D_SHIFT 3 -#define OMAP3430ES2_EN_TS_SHIFT 1 -#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 #define OMAP3430_ST_AES2_SHIFT 28 #define OMAP3430_ST_SHA12_SHIFT 27 #define AM35XX_ST_UART4_SHIFT 23 @@ -84,131 +27,26 @@ #define OMAP3430_ST_MAILBOXES_SHIFT 7 #define OMAP3430_ST_SAD2D_SHIFT 3 #define OMAP3430_ST_SDMA_SHIFT 2 -#define AM35XX_ST_IPSS_SHIFT 5 #define OMAP3430ES2_ST_USBTLL_SHIFT 2 -#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) -#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) -#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) -#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) -#define OMAP3430_CLKSEL_L4_SHIFT 2 -#define OMAP3430_CLKSEL_L4_WIDTH 2 -#define OMAP3430_CLKSEL_L3_SHIFT 0 -#define OMAP3430_CLKSEL_L3_WIDTH 2 -#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) -#define OMAP3430ES1_EN_3D_SHIFT 2 -#define OMAP3430ES1_EN_2D_SHIFT 1 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) -#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 -#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 -#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) -#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 -#define OMAP3430_EN_WDT1_SHIFT 4 -#define OMAP3430_EN_32KSYNC_SHIFT 2 #define OMAP3430_ST_WDT2_SHIFT 5 #define OMAP3430_ST_32KSYNC_SHIFT 2 -#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) -#define OMAP3430_CLKSEL_RM_SHIFT 1 -#define OMAP3430_CLKSEL_RM_WIDTH 2 -#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) -#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 -#define OMAP3430_PWRDN_CAM_SHIFT 30 -#define OMAP3430_PWRDN_DSS1_SHIFT 29 -#define OMAP3430_PWRDN_TV_SHIFT 28 -#define OMAP3430_PWRDN_96M_SHIFT 27 -#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) -#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 -#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) -#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 -#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) -#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) -#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) -#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) -#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) -#define OMAP3430_ST_CORE_CLK_MASK (1 << 0) -#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) -#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) -#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) -#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 -#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 -#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) -#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) -#define OMAP3430_SOURCE_96M_SHIFT 6 -#define OMAP3430_SOURCE_96M_WIDTH 1 -#define OMAP3430_SOURCE_54M_SHIFT 5 -#define OMAP3430_SOURCE_54M_WIDTH 1 -#define OMAP3430_SOURCE_48M_MASK (1 << 3) -#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) -#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) -#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) -#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) -#define OMAP3430_DIV_96M_SHIFT 0 -#define OMAP3630_DIV_96M_WIDTH 6 -#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) -#define OMAP3430ES2_DIV_120M_SHIFT 0 -#define OMAP3430ES2_DIV_120M_WIDTH 5 -#define OMAP3430_CLKOUT2_EN_SHIFT 7 -#define OMAP3430_CLKOUT2_DIV_SHIFT 3 -#define OMAP3430_CLKOUT2_DIV_WIDTH 3 -#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) -#define OMAP3430_EN_TV_SHIFT 2 -#define OMAP3430_EN_DSS2_SHIFT 1 -#define OMAP3430_EN_DSS1_SHIFT 0 -#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 -#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 -#define OMAP3430ES1_ST_DSS_SHIFT 0 -#define OMAP3430_CLKSEL_TV_SHIFT 8 -#define OMAP3630_CLKSEL_TV_WIDTH 6 -#define OMAP3430_CLKSEL_DSS1_SHIFT 0 -#define OMAP3630_CLKSEL_DSS1_WIDTH 6 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) -#define OMAP3430_EN_CSI2_SHIFT 1 -#define OMAP3430_CLKSEL_CAM_SHIFT 0 -#define OMAP3630_CLKSEL_CAM_WIDTH 6 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) #define OMAP3430_ST_MCBSP4_SHIFT 2 #define OMAP3430_ST_MCBSP3_SHIFT 1 #define OMAP3430_ST_MCBSP2_SHIFT 0 -#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) -#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) -#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) -#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) -#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) -#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) -#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) -#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) -#define OMAP3430_DIV_DPLL4_SHIFT 24 -#define OMAP3630_DIV_DPLL4_WIDTH 6 -#define OMAP3430_DIV_DPLL3_SHIFT 16 -#define OMAP3430_DIV_DPLL3_WIDTH 5 -#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 -#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 -#define OMAP3430_CLKSEL_PCLK_SHIFT 8 -#define OMAP3430_CLKSEL_PCLK_WIDTH 3 -#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 -#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 -#define OMAP3430_CLKSEL_ATCLK_SHIFT 4 -#define OMAP3430_CLKSEL_ATCLK_WIDTH 2 -#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 -#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 -#define OMAP3430_MUX_CTRL_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 -#define OMAP3430ES2_EN_USBHOST1_SHIFT 0 -#define OMAP3430ES2_EN_USBHOST_SHIFT 0 #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 -#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index e833984cc85e..b19e83d53501 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -52,6 +52,7 @@ extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl * @module_enable: ptr to the SoC CM-specific module_enable impl * @module_disable: ptr to the SoC CM-specific module_disable impl + * @xlate_clkctrl: ptr to the SoC CM-specific clkctrl xlate addr impl */ struct cm_ll_data { int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, @@ -62,6 +63,7 @@ struct cm_ll_data { u8 idlest_shift); void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs); + u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs); }; extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, @@ -72,8 +74,9 @@ int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg, u8 idlest_shift); int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs); -extern int cm_register(struct cm_ll_data *cld); -extern int cm_unregister(struct cm_ll_data *cld); +u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs); +extern int cm_register(const struct cm_ll_data *cld); +extern int cm_unregister(const struct cm_ll_data *cld); int omap_cm_init(void); int omap2_cm_base_init(void); diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c index cd90b4c6a06b..d5b87f42a96e 100644 --- a/arch/arm/mach-omap2/cm2xxx.c +++ b/arch/arm/mach-omap2/cm2xxx.c @@ -385,7 +385,7 @@ void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm) * */ -static struct cm_ll_data omap2xxx_cm_ll_data = { +static const struct cm_ll_data omap2xxx_cm_ll_data = { .split_idlest_reg = &omap2xxx_cm_split_idlest_reg, .wait_module_ready = &omap2xxx_cm_wait_module_ready, }; diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index a9e08d89104e..1cc0247a2cb5 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c @@ -333,6 +333,11 @@ static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) return 0; } +static u32 am33xx_cm_xlate_clkctrl(u8 part, u16 inst, u16 offset) +{ + return cm_base.pa + inst + offset; +} + struct clkdm_ops am33xx_clkdm_operations = { .clkdm_sleep = am33xx_clkdm_sleep, .clkdm_wakeup = am33xx_clkdm_wakeup, @@ -342,11 +347,12 @@ struct clkdm_ops am33xx_clkdm_operations = { .clkdm_clk_disable = am33xx_clkdm_clk_disable, }; -static struct cm_ll_data am33xx_cm_ll_data = { +static const struct cm_ll_data am33xx_cm_ll_data = { .wait_module_ready = &am33xx_cm_wait_module_ready, .wait_module_idle = &am33xx_cm_wait_module_idle, .module_enable = &am33xx_cm_module_enable, .module_disable = &am33xx_cm_module_disable, + .xlate_clkctrl = &am33xx_cm_xlate_clkctrl, }; int __init am33xx_cm_init(const struct omap_prcm_init_data *data) diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index 961bc478b9de..ec580fd094a6 100644 --- a/arch/arm/mach-omap2/cm3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -662,7 +662,7 @@ void omap3_cm_save_scratchpad_contents(u32 *ptr) * */ -static struct cm_ll_data omap3xxx_cm_ll_data = { +static const struct cm_ll_data omap3xxx_cm_ll_data = { .split_idlest_reg = &omap3xxx_cm_split_idlest_reg, .wait_module_ready = &omap3xxx_cm_wait_module_ready, }; diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c index 83c6fa74cc31..aff747ecad51 100644 --- a/arch/arm/mach-omap2/cm_common.c +++ b/arch/arm/mach-omap2/cm_common.c @@ -29,7 +29,7 @@ * common CM functions */ static struct cm_ll_data null_cm_ll_data; -static struct cm_ll_data *cm_ll_data = &null_cm_ll_data; +static const struct cm_ll_data *cm_ll_data = &null_cm_ll_data; /* cm_base: base virtual address of the CM IP block */ struct omap_domain_base cm_base; @@ -178,6 +178,16 @@ int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) return 0; } +u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs) +{ + if (!cm_ll_data->xlate_clkctrl) { + WARN_ONCE(1, "cm: %s: no low-level function defined\n", + __func__); + return 0; + } + return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs); +} + /** * cm_register - register per-SoC low-level data with the CM * @cld: low-level per-SoC OMAP CM data & function pointers to register @@ -189,7 +199,7 @@ int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) * is NULL, or -EEXIST if cm_register() has already been called * without an intervening cm_unregister(). */ -int cm_register(struct cm_ll_data *cld) +int cm_register(const struct cm_ll_data *cld) { if (!cld) return -EINVAL; @@ -213,7 +223,7 @@ int cm_register(struct cm_ll_data *cld) * -EINVAL if @cld is NULL or if @cld does not match the struct * cm_ll_data * previously registered by cm_register(). */ -int cm_unregister(struct cm_ll_data *cld) +int cm_unregister(const struct cm_ll_data *cld) { if (!cld || cm_ll_data != cld) return -EINVAL; diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index 8774e983bea1..7deefee49fc3 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -476,12 +476,9 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) return 0; } -static u32 omap4_clkdm_xlate_address(struct clockdomain *clkdm) +static u32 omap4_cminst_xlate_clkctrl(u8 part, u16 inst, u16 offset) { - u32 addr = _cm_bases[clkdm->prcm_partition].pa + clkdm->cm_inst + - clkdm->clkdm_offs; - - return addr; + return _cm_bases[part].pa + inst + offset; } struct clkdm_ops omap4_clkdm_operations = { @@ -499,7 +496,6 @@ struct clkdm_ops omap4_clkdm_operations = { .clkdm_deny_idle = omap4_clkdm_deny_idle, .clkdm_clk_enable = omap4_clkdm_clk_enable, .clkdm_clk_disable = omap4_clkdm_clk_disable, - .clkdm_xlate_address = omap4_clkdm_xlate_address, }; struct clkdm_ops am43xx_clkdm_operations = { @@ -509,14 +505,14 @@ struct clkdm_ops am43xx_clkdm_operations = { .clkdm_deny_idle = omap4_clkdm_deny_idle, .clkdm_clk_enable = omap4_clkdm_clk_enable, .clkdm_clk_disable = omap4_clkdm_clk_disable, - .clkdm_xlate_address = omap4_clkdm_xlate_address, }; -static struct cm_ll_data omap4xxx_cm_ll_data = { +static const struct cm_ll_data omap4xxx_cm_ll_data = { .wait_module_ready = &omap4_cminst_wait_module_ready, .wait_module_idle = &omap4_cminst_wait_module_idle, .module_enable = &omap4_cminst_module_enable, .module_disable = &omap4_cminst_module_disable, + .xlate_clkctrl = &omap4_cminst_xlate_clkctrl, }; int __init omap4_cm_init(const struct omap_prcm_init_data *data) diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c deleted file mode 100644 index 2944af820558..000000000000 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/gpmc-onenand.c - * - * Copyright (C) 2006 - 2009 Nokia Corporation - * Contacts: Juha Yrjola - * Tony Lindgren - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/string.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mtd/onenand_regs.h> -#include <linux/io.h> -#include <linux/omap-gpmc.h> -#include <linux/platform_data/mtd-onenand-omap2.h> -#include <linux/err.h> - -#include <asm/mach/flash.h> - -#include "soc.h" - -#define ONENAND_IO_SIZE SZ_128K - -#define ONENAND_FLAG_SYNCREAD (1 << 0) -#define ONENAND_FLAG_SYNCWRITE (1 << 1) -#define ONENAND_FLAG_HF (1 << 2) -#define ONENAND_FLAG_VHF (1 << 3) - -static unsigned onenand_flags; -static unsigned latency; - -static struct omap_onenand_platform_data *gpmc_onenand_data; - -static struct resource gpmc_onenand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device gpmc_onenand_device = { - .name = "omap2-onenand", - .id = -1, - .num_resources = 1, - .resource = &gpmc_onenand_resource, -}; - -static struct gpmc_settings onenand_async = { - .device_width = GPMC_DEVWIDTH_16BIT, - .mux_add_data = GPMC_MUX_AD, -}; - -static struct gpmc_settings onenand_sync = { - .burst_read = true, - .burst_wrap = true, - .burst_len = GPMC_BURST_16, - .device_width = GPMC_DEVWIDTH_16BIT, - .mux_add_data = GPMC_MUX_AD, - .wait_pin = 0, -}; - -static void omap2_onenand_calc_async_timings(struct gpmc_timings *t) -{ - struct gpmc_device_timings dev_t; - const int t_cer = 15; - const int t_avdp = 12; - const int t_aavdh = 7; - const int t_ce = 76; - const int t_aa = 76; - const int t_oe = 20; - const int t_cez = 20; /* max of t_cez, t_oez */ - const int t_wpl = 40; - const int t_wph = 30; - - memset(&dev_t, 0, sizeof(dev_t)); - - dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000; - dev_t.t_avdp_w = dev_t.t_avdp_r; - dev_t.t_aavdh = t_aavdh * 1000; - dev_t.t_aa = t_aa * 1000; - dev_t.t_ce = t_ce * 1000; - dev_t.t_oe = t_oe * 1000; - dev_t.t_cez_r = t_cez * 1000; - dev_t.t_cez_w = dev_t.t_cez_r; - dev_t.t_wpl = t_wpl * 1000; - dev_t.t_wph = t_wph * 1000; - - gpmc_calc_timings(t, &onenand_async, &dev_t); -} - -static void omap2_onenand_set_async_mode(void __iomem *onenand_base) -{ - u32 reg; - - /* Ensure sync read and sync write are disabled */ - reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); - reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); -} - -static void set_onenand_cfg(void __iomem *onenand_base) -{ - u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT; - - reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) | - ONENAND_SYS_CFG1_BL_16; - if (onenand_flags & ONENAND_FLAG_SYNCREAD) - reg |= ONENAND_SYS_CFG1_SYNC_READ; - else - reg &= ~ONENAND_SYS_CFG1_SYNC_READ; - if (onenand_flags & ONENAND_FLAG_SYNCWRITE) - reg |= ONENAND_SYS_CFG1_SYNC_WRITE; - else - reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE; - if (onenand_flags & ONENAND_FLAG_HF) - reg |= ONENAND_SYS_CFG1_HF; - else - reg &= ~ONENAND_SYS_CFG1_HF; - if (onenand_flags & ONENAND_FLAG_VHF) - reg |= ONENAND_SYS_CFG1_VHF; - else - reg &= ~ONENAND_SYS_CFG1_VHF; - - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); -} - -static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, - void __iomem *onenand_base) -{ - u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); - int freq; - - switch ((ver >> 4) & 0xf) { - case 0: - freq = 40; - break; - case 1: - freq = 54; - break; - case 2: - freq = 66; - break; - case 3: - freq = 83; - break; - case 4: - freq = 104; - break; - default: - pr_err("onenand rate not detected, bad GPMC async timings?\n"); - freq = 0; - } - - return freq; -} - -static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t, - unsigned int flags, - int freq) -{ - struct gpmc_device_timings dev_t; - const int t_cer = 15; - const int t_avdp = 12; - const int t_cez = 20; /* max of t_cez, t_oez */ - const int t_wpl = 40; - const int t_wph = 30; - int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; - int div, gpmc_clk_ns; - - if (flags & ONENAND_SYNC_READ) - onenand_flags = ONENAND_FLAG_SYNCREAD; - else if (flags & ONENAND_SYNC_READWRITE) - onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE; - - switch (freq) { - case 104: - min_gpmc_clk_period = 9600; /* 104 MHz */ - t_ces = 3; - t_avds = 4; - t_avdh = 2; - t_ach = 3; - t_aavdh = 6; - t_rdyo = 6; - break; - case 83: - min_gpmc_clk_period = 12000; /* 83 MHz */ - t_ces = 5; - t_avds = 4; - t_avdh = 2; - t_ach = 6; - t_aavdh = 6; - t_rdyo = 9; - break; - case 66: - min_gpmc_clk_period = 15000; /* 66 MHz */ - t_ces = 6; - t_avds = 5; - t_avdh = 2; - t_ach = 6; - t_aavdh = 6; - t_rdyo = 11; - break; - default: - min_gpmc_clk_period = 18500; /* 54 MHz */ - t_ces = 7; - t_avds = 7; - t_avdh = 7; - t_ach = 9; - t_aavdh = 7; - t_rdyo = 15; - onenand_flags &= ~ONENAND_FLAG_SYNCWRITE; - break; - } - - div = gpmc_calc_divider(min_gpmc_clk_period); - gpmc_clk_ns = gpmc_ticks_to_ns(div); - if (gpmc_clk_ns < 15) /* >66MHz */ - onenand_flags |= ONENAND_FLAG_HF; - else - onenand_flags &= ~ONENAND_FLAG_HF; - if (gpmc_clk_ns < 12) /* >83MHz */ - onenand_flags |= ONENAND_FLAG_VHF; - else - onenand_flags &= ~ONENAND_FLAG_VHF; - if (onenand_flags & ONENAND_FLAG_VHF) - latency = 8; - else if (onenand_flags & ONENAND_FLAG_HF) - latency = 6; - else if (gpmc_clk_ns >= 25) /* 40 MHz*/ - latency = 3; - else - latency = 4; - - /* Set synchronous read timings */ - memset(&dev_t, 0, sizeof(dev_t)); - - if (onenand_flags & ONENAND_FLAG_SYNCREAD) - onenand_sync.sync_read = true; - if (onenand_flags & ONENAND_FLAG_SYNCWRITE) { - onenand_sync.sync_write = true; - onenand_sync.burst_write = true; - } else { - dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; - dev_t.t_wpl = t_wpl * 1000; - dev_t.t_wph = t_wph * 1000; - dev_t.t_aavdh = t_aavdh * 1000; - } - dev_t.ce_xdelay = true; - dev_t.avd_xdelay = true; - dev_t.oe_xdelay = true; - dev_t.we_xdelay = true; - dev_t.clk = min_gpmc_clk_period; - dev_t.t_bacc = dev_t.clk; - dev_t.t_ces = t_ces * 1000; - dev_t.t_avds = t_avds * 1000; - dev_t.t_avdh = t_avdh * 1000; - dev_t.t_ach = t_ach * 1000; - dev_t.cyc_iaa = (latency + 1); - dev_t.t_cez_r = t_cez * 1000; - dev_t.t_cez_w = dev_t.t_cez_r; - dev_t.cyc_aavdh_oe = 1; - dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; - - gpmc_calc_timings(t, &onenand_sync, &dev_t); -} - -static int omap2_onenand_setup_async(void __iomem *onenand_base) -{ - struct gpmc_timings t; - int ret; - - /* - * Note that we need to keep sync_write set for the call to - * omap2_onenand_set_async_mode() to work to detect the onenand - * supported clock rate for the sync timings. - */ - if (gpmc_onenand_data->of_node) { - gpmc_read_settings_dt(gpmc_onenand_data->of_node, - &onenand_async); - if (onenand_async.sync_read || onenand_async.sync_write) { - if (onenand_async.sync_write) - gpmc_onenand_data->flags |= - ONENAND_SYNC_READWRITE; - else - gpmc_onenand_data->flags |= ONENAND_SYNC_READ; - onenand_async.sync_read = false; - } - } - - onenand_async.sync_write = true; - omap2_onenand_calc_async_timings(&t); - - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async); - if (ret < 0) - return ret; - - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async); - if (ret < 0) - return ret; - - omap2_onenand_set_async_mode(onenand_base); - - return 0; -} - -static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) -{ - int ret, freq = *freq_ptr; - struct gpmc_timings t; - - if (!freq) { - /* Very first call freq is not known */ - freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base); - if (!freq) - return -ENODEV; - set_onenand_cfg(onenand_base); - } - - if (gpmc_onenand_data->of_node) { - gpmc_read_settings_dt(gpmc_onenand_data->of_node, - &onenand_sync); - } else { - /* - * FIXME: Appears to be legacy code from initial ONENAND commit. - * Unclear what boards this is for and if this can be removed. - */ - if (!cpu_is_omap34xx()) - onenand_sync.wait_on_read = true; - } - - omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq); - - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync); - if (ret < 0) - return ret; - - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync); - if (ret < 0) - return ret; - - set_onenand_cfg(onenand_base); - - *freq_ptr = freq; - - return 0; -} - -static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) -{ - struct device *dev = &gpmc_onenand_device.dev; - unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE; - int ret; - - ret = omap2_onenand_setup_async(onenand_base); - if (ret) { - dev_err(dev, "unable to set to async mode\n"); - return ret; - } - - if (!(gpmc_onenand_data->flags & l)) - return 0; - - ret = omap2_onenand_setup_sync(onenand_base, freq_ptr); - if (ret) - dev_err(dev, "unable to set to sync mode\n"); - return ret; -} - -int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) -{ - int err; - struct device *dev = &gpmc_onenand_device.dev; - - gpmc_onenand_data = _onenand_data; - gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; - gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; - - if (cpu_is_omap24xx() && - (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) { - dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n"); - gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE; - gpmc_onenand_data->flags |= ONENAND_SYNC_READ; - } - - if (cpu_is_omap34xx()) - gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX; - else - gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX; - - err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, - (unsigned long *)&gpmc_onenand_resource.start); - if (err < 0) { - dev_err(dev, "Cannot request GPMC CS %d, error %d\n", - gpmc_onenand_data->cs, err); - return err; - } - - gpmc_onenand_resource.end = gpmc_onenand_resource.start + - ONENAND_IO_SIZE - 1; - - err = platform_device_register(&gpmc_onenand_device); - if (err) { - dev_err(dev, "Unable to register OneNAND device\n"); - gpmc_cs_free(gpmc_onenand_data->cs); - } - - return err; -} diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index df2c29edbbcd..68ba5f472f6b 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -657,8 +657,11 @@ void __init dra7xxx_check_revision(void) { u32 idcode; u16 hawkeye; - u8 rev; + u8 rev, package; + struct omap_die_id odi; + omap_get_die_id(&odi); + package = (odi.id_2 >> 16) & 0x3; idcode = read_tap_reg(OMAP_TAP_IDCODE); hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0xff; @@ -667,7 +670,17 @@ void __init dra7xxx_check_revision(void) switch (rev) { case 0: default: - omap_revision = DRA762_REV_ES1_0; + switch (package) { + case 0x2: + omap_revision = DRA762_ABZ_REV_ES1_0; + break; + case 0x3: + omap_revision = DRA762_ACD_REV_ES1_0; + break; + default: + omap_revision = DRA762_REV_ES1_0; + break; + } break; } break; diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 4bb6751864a5..fc5fb776a710 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -299,8 +299,6 @@ static void irq_save_context(void) if (soc_is_dra7xx()) return; - if (!sar_base) - sar_base = omap4_get_sar_ram_base(); if (wakeupgen_ops && wakeupgen_ops->save_context) wakeupgen_ops->save_context(); } @@ -598,6 +596,8 @@ static int __init wakeupgen_init(struct device_node *node, irq_hotplug_init(); irq_pm_init(); + sar_base = omap4_get_sar_ram_base(); + return 0; } IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 104256a5f0f7..34156eca8e23 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -143,6 +143,8 @@ #include <linux/of_address.h> #include <linux/bootmem.h> +#include <linux/platform_data/ti-sysc.h> + #include <asm/system_misc.h> #include "clock.h" @@ -185,15 +187,15 @@ /** * struct clkctrl_provider - clkctrl provider mapping data * @addr: base address for the provider - * @offset: base offset for the provider - * @clkdm: base clockdomain for provider + * @size: size of the provider address space + * @offset: offset of the provider from PRCM instance base * @node: device node associated with the provider * @link: list link */ struct clkctrl_provider { u32 addr; + u32 size; u16 offset; - struct clockdomain *clkdm; struct device_node *node; struct list_head link; }; @@ -223,8 +225,7 @@ struct omap_hwmod_soc_ops { void (*update_context_lost)(struct omap_hwmod *oh); int (*get_context_lost)(struct omap_hwmod *oh); int (*disable_direct_prcm)(struct omap_hwmod *oh); - u32 (*xlate_clkctrl)(struct omap_hwmod *oh, - struct clkctrl_provider *provider); + u32 (*xlate_clkctrl)(struct omap_hwmod *oh); }; /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ @@ -716,52 +717,35 @@ static const struct of_device_id ti_clkctrl_match_table[] __initconst = { { } }; -static int _match_clkdm(struct clockdomain *clkdm, void *user) -{ - struct clkctrl_provider *provider = user; - - if (clkdm_xlate_address(clkdm) == provider->addr) { - pr_debug("%s: Matched clkdm %s for addr %x (%s)\n", __func__, - clkdm->name, provider->addr, - provider->node->parent->name); - provider->clkdm = clkdm; - - return -1; - } - - return 0; -} - -static int _setup_clkctrl_provider(struct device_node *np) +static int __init _setup_clkctrl_provider(struct device_node *np) { const __be32 *addrp; struct clkctrl_provider *provider; + u64 size; provider = memblock_virt_alloc(sizeof(*provider), 0); if (!provider) return -ENOMEM; - addrp = of_get_address(np, 0, NULL, NULL); + addrp = of_get_address(np, 0, &size, NULL); provider->addr = (u32)of_translate_address(np, addrp); - provider->offset = provider->addr & 0xff; + addrp = of_get_address(np->parent, 0, NULL, NULL); + provider->offset = provider->addr - + (u32)of_translate_address(np->parent, addrp); provider->addr &= ~0xff; + provider->size = size | 0xff; provider->node = np; - clkdm_for_each(_match_clkdm, provider); - - if (!provider->clkdm) { - pr_err("%s: nothing matched for node %s (%x)\n", - __func__, np->parent->name, provider->addr); - memblock_free_early(__pa(provider), sizeof(*provider)); - return -EINVAL; - } + pr_debug("%s: %s: %x...%x [+%x]\n", __func__, np->parent->name, + provider->addr, provider->addr + provider->size, + provider->offset); list_add(&provider->link, &clkctrl_providers); return 0; } -static int _init_clkctrl_providers(void) +static int __init _init_clkctrl_providers(void) { struct device_node *np; int ret = 0; @@ -775,32 +759,48 @@ static int _init_clkctrl_providers(void) return ret; } -static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh, - struct clkctrl_provider *provider) +static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh) { - return oh->prcm.omap4.clkctrl_offs - - provider->offset - provider->clkdm->clkdm_offs; + if (!oh->prcm.omap4.modulemode) + return 0; + + return omap_cm_xlate_clkctrl(oh->clkdm->prcm_partition, + oh->clkdm->cm_inst, + oh->prcm.omap4.clkctrl_offs); } static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh) { struct clkctrl_provider *provider; struct clk *clk; + u32 addr; if (!soc_ops.xlate_clkctrl) return NULL; + addr = soc_ops.xlate_clkctrl(oh); + if (!addr) + return NULL; + + pr_debug("%s: %s: addr=%x\n", __func__, oh->name, addr); + list_for_each_entry(provider, &clkctrl_providers, link) { - if (provider->clkdm == oh->clkdm) { + if (provider->addr <= addr && + provider->addr + provider->size >= addr) { struct of_phandle_args clkspec; clkspec.np = provider->node; clkspec.args_count = 2; - clkspec.args[0] = soc_ops.xlate_clkctrl(oh, provider); + clkspec.args[0] = addr - provider->addr - + provider->offset; clkspec.args[1] = 0; clk = of_clk_get_from_provider(&clkspec); + pr_debug("%s: %s got %p (offset=%x, provider=%s)\n", + __func__, oh->name, clk, clkspec.args[0], + provider->node->parent->name); + return clk; } } @@ -977,6 +977,9 @@ static int _enable_clocks(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); + if (oh->flags & HWMOD_OPT_CLKS_NEEDED) + _enable_optional_clocks(oh); + if (oh->_clk) clk_enable(oh->_clk); @@ -985,9 +988,6 @@ static int _enable_clocks(struct omap_hwmod *oh) clk_enable(os->_clk); } - if (oh->flags & HWMOD_OPT_CLKS_NEEDED) - _enable_optional_clocks(oh); - /* The opt clocks are controlled by the device driver. */ return 0; @@ -3521,6 +3521,7 @@ void __init omap_hwmod_init(void) soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; soc_ops.init_clkdm = _init_clkdm; soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm; + soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl; } else { WARN(1, "omap_hwmod: unknown SoC type\n"); } diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index df2239a58555..0b8e19f40402 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -37,9 +37,15 @@ struct omap_device; -extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; -extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; -extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3; +extern struct sysc_regbits omap_hwmod_sysc_type1; +extern struct sysc_regbits omap_hwmod_sysc_type2; +extern struct sysc_regbits omap_hwmod_sysc_type3; +extern struct sysc_regbits omap34xx_sr_sysc_fields; +extern struct sysc_regbits omap36xx_sr_sysc_fields; +extern struct sysc_regbits omap3_sham_sysc_fields; +extern struct sysc_regbits omap3xxx_aes_sysc_fields; +extern struct sysc_regbits omap_hwmod_sysc_type_mcasp; +extern struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs; /* * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant @@ -285,26 +291,6 @@ struct omap_hwmod_ocp_if { #define CLOCKACT_TEST_NONE 0x3 /** - * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets. - * @midle_shift: Offset of the midle bit - * @clkact_shift: Offset of the clockactivity bit - * @sidle_shift: Offset of the sidle bit - * @enwkup_shift: Offset of the enawakeup bit - * @srst_shift: Offset of the softreset bit - * @autoidle_shift: Offset of the autoidle bit - * @dmadisable_shift: Offset of the dmadisable bit - */ -struct omap_hwmod_sysc_fields { - u8 midle_shift; - u8 clkact_shift; - u8 sidle_shift; - u8 enwkup_shift; - u8 srst_shift; - u8 autoidle_shift; - u8 dmadisable_shift; -}; - -/** * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data * @rev_offs: IP block revision register offset (from module base addr) * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) @@ -335,7 +321,7 @@ struct omap_hwmod_class_sysconfig { u32 sysc_offs; u32 syss_offs; u16 sysc_flags; - struct omap_hwmod_sysc_fields *sysc_fields; + struct sysc_regbits *sysc_fields; u8 srst_udelay; u8 idlemodes; }; @@ -343,11 +329,8 @@ struct omap_hwmod_class_sysconfig { /** * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data * @module_offs: PRCM submodule offset from the start of the PRM/CM - * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3) - * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3) * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit - * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit * * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST, * WKEN, GRPSEL registers. In an ideal world, no extra information @@ -357,11 +340,8 @@ struct omap_hwmod_class_sysconfig { */ struct omap_hwmod_omap2_prcm { s16 module_offs; - u8 prcm_reg_id; - u8 module_bit; u8 idlest_reg_id; u8 idlest_idle_bit; - u8 idlest_stdby_bit; }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 1a15a347945a..0afb014b211f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -111,8 +111,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2420_EN_I2C1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, }, @@ -134,8 +132,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2420_EN_I2C2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, }, @@ -167,8 +163,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = { .main_clk = "mailboxes_ick", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, @@ -197,8 +191,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, @@ -215,8 +207,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = { .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, @@ -247,8 +237,6 @@ static struct omap_hwmod omap2420_msdi1_hwmod = { .main_clk = "mmc_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP2420_EN_MMC_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT, @@ -264,8 +252,6 @@ static struct omap_hwmod omap2420_hdq1w_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_HDQ_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, }, diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 3801850bccec..013b26b305d2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -97,8 +97,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { * to hwmod framework. */ .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_I2CHS1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, }, @@ -115,8 +113,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_I2CHS2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, }, @@ -132,8 +128,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { .main_clk = "gpio5_fck", .prcm = { .omap2 = { - .prcm_reg_id = 2, - .module_bit = OMAP2430_EN_GPIO5_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 2, .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, @@ -165,8 +159,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { .main_clk = "mailboxes_ick", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, @@ -185,8 +177,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP2430_EN_MCSPI3_SHIFT, .idlest_reg_id = 2, .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, }, @@ -219,8 +209,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = { .main_clk = "usbhs_ick", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_USBHS_MASK, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, @@ -266,8 +254,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, @@ -284,8 +270,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, @@ -302,8 +286,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { .main_clk = "mcbsp3_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_MCBSP3_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 2, .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, @@ -320,8 +302,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { .main_clk = "mcbsp4_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_MCBSP4_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 2, .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, @@ -338,8 +318,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = { .main_clk = "mcbsp5_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP2430_EN_MCBSP5_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 2, .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, @@ -384,8 +362,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP2430_EN_MMCHS1_SHIFT, .idlest_reg_id = 2, .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, }, @@ -408,8 +384,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP2430_EN_MMCHS2_SHIFT, .idlest_reg_id = 2, .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, }, @@ -424,8 +398,6 @@ static struct omap_hwmod omap2430_hdq1w_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_HDQ_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, }, diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index beec4cd617b1..4b094cb384cb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -242,8 +242,6 @@ struct omap_hwmod omap2xxx_timer1_hwmod = { .main_clk = "gpt1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT1_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, @@ -261,8 +259,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = { .main_clk = "gpt2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT2_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, @@ -279,8 +275,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = { .main_clk = "gpt3_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT3_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, @@ -297,8 +291,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = { .main_clk = "gpt4_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT4_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, @@ -315,8 +307,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = { .main_clk = "gpt5_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT5_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, @@ -334,8 +324,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = { .main_clk = "gpt6_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT6_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, @@ -353,8 +341,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = { .main_clk = "gpt7_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT7_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, @@ -372,8 +358,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = { .main_clk = "gpt8_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT8_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, @@ -391,8 +375,6 @@ struct omap_hwmod omap2xxx_timer9_hwmod = { .main_clk = "gpt9_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT9_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, @@ -410,8 +392,6 @@ struct omap_hwmod omap2xxx_timer10_hwmod = { .main_clk = "gpt10_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT10_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, @@ -429,8 +409,6 @@ struct omap_hwmod omap2xxx_timer11_hwmod = { .main_clk = "gpt11_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT11_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, @@ -448,8 +426,6 @@ struct omap_hwmod omap2xxx_timer12_hwmod = { .main_clk = "gpt12_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT12_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, @@ -467,8 +443,6 @@ struct omap_hwmod omap2xxx_wd_timer2_hwmod = { .main_clk = "mpu_wdt_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, @@ -485,8 +459,6 @@ struct omap_hwmod omap2xxx_uart1_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, }, @@ -503,8 +475,6 @@ struct omap_hwmod omap2xxx_uart2_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, }, @@ -521,8 +491,6 @@ struct omap_hwmod omap2xxx_uart3_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP24XX_EN_UART3_SHIFT, .idlest_reg_id = 2, .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, }, @@ -547,11 +515,8 @@ struct omap_hwmod omap2xxx_dss_core_hwmod = { .main_clk = "dss1_fck", /* instead of dss_fck */ .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, }, }, .opt_clks = dss_opt_clks, @@ -565,11 +530,8 @@ struct omap_hwmod omap2xxx_dss_dispc_hwmod = { .main_clk = "dss1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, }, }, .flags = HWMOD_NO_IDLEST, @@ -586,8 +548,6 @@ struct omap_hwmod omap2xxx_dss_rfbi_hwmod = { .main_clk = "dss1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, .module_offs = CORE_MOD, }, }, @@ -602,8 +562,6 @@ struct omap_hwmod omap2xxx_dss_venc_hwmod = { .main_clk = "dss_54m_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, .module_offs = CORE_MOD, }, }, @@ -623,8 +581,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = { .main_clk = "gpios_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, @@ -641,8 +597,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = { .main_clk = "gpios_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, @@ -659,8 +613,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = { .main_clk = "gpios_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, @@ -677,8 +629,6 @@ struct omap_hwmod omap2xxx_gpio4_hwmod = { .main_clk = "gpios_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, @@ -699,8 +649,6 @@ struct omap_hwmod omap2xxx_mcspi1_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, }, @@ -720,8 +668,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, }, @@ -740,8 +686,6 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = { .prcm = { .omap2 = { .module_offs = WKUP_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_ST_32KSYNC_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT, }, @@ -758,8 +702,6 @@ struct omap_hwmod omap2xxx_gpmc_hwmod = { .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, .prcm = { .omap2 = { - .prcm_reg_id = 3, - .module_bit = OMAP24XX_EN_GPMC_MASK, .module_offs = CORE_MOD, }, }, @@ -787,8 +729,6 @@ struct omap_hwmod omap2xxx_rng_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 4, - .module_bit = OMAP24XX_EN_RNG_SHIFT, .idlest_reg_id = 4, .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT, }, @@ -825,8 +765,6 @@ struct omap_hwmod omap2xxx_sham_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 4, - .module_bit = OMAP24XX_EN_SHA_SHIFT, .idlest_reg_id = 4, .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT, }, @@ -856,8 +794,6 @@ struct omap_hwmod omap2xxx_aes_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 4, - .module_bit = OMAP24XX_EN_AES_SHIFT, .idlest_reg_id = 4, .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT, }, diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 52c9d585b44d..1a2f2242e31b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -113,8 +113,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .prcm = { .omap2 = { .module_offs = OMAP3430_IVA2_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, }, @@ -188,8 +186,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = { .main_clk = "gpt1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT1_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, @@ -206,8 +202,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { .main_clk = "gpt2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT2_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, @@ -223,8 +217,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = { .main_clk = "gpt3_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT3_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, @@ -240,8 +232,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = { .main_clk = "gpt4_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT4_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, @@ -257,8 +247,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { .main_clk = "gpt5_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT5_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, @@ -275,8 +263,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { .main_clk = "gpt6_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT6_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, @@ -293,8 +279,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { .main_clk = "gpt7_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT7_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, @@ -311,8 +295,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { .main_clk = "gpt8_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT8_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, @@ -329,8 +311,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = { .main_clk = "gpt9_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT9_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, @@ -347,8 +327,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = { .main_clk = "gpt10_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT10_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, @@ -365,8 +343,6 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { .main_clk = "gpt11_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT11_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, @@ -384,8 +360,6 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = { .main_clk = "gpt12_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPT12_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, @@ -439,8 +413,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { .main_clk = "wdt2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_WDT2_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, @@ -461,8 +433,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, }, @@ -478,8 +448,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, }, @@ -496,8 +464,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { .prcm = { .omap2 = { .module_offs = OMAP3430_PER_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_UART3_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, }, @@ -515,8 +481,6 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { .prcm = { .omap2 = { .module_offs = OMAP3430_PER_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3630_EN_UART4_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, }, @@ -546,8 +510,6 @@ static struct omap_hwmod am35xx_uart4_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = AM35XX_EN_UART4_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, }, @@ -583,11 +545,8 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = { .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, .module_offs = OMAP3430_DSS_MOD, .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, }, }, .opt_clks = dss_opt_clks, @@ -602,12 +561,9 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, .module_offs = OMAP3430_DSS_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, - .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, }, }, .opt_clks = dss_opt_clks, @@ -642,8 +598,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, .module_offs = OMAP3430_DSS_MOD, }, }, @@ -683,8 +637,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, .module_offs = OMAP3430_DSS_MOD, }, }, @@ -703,8 +655,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, .module_offs = OMAP3430_DSS_MOD, }, }, @@ -724,8 +674,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = { .main_clk = "dss_tv_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_DSS1_SHIFT, .module_offs = OMAP3430_DSS_MOD, }, }, @@ -747,8 +695,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_I2C1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, }, @@ -770,8 +716,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_I2C2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, }, @@ -795,8 +739,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_I2C3_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, }, @@ -846,8 +788,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = { .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO1_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, @@ -870,8 +810,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = { .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO2_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, @@ -894,8 +832,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = { .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO3_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, @@ -918,8 +854,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO4_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, @@ -943,8 +877,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO5_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, @@ -968,8 +900,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = { .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_GPIO6_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, @@ -1012,8 +942,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_ST_SDMA_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, }, @@ -1060,8 +988,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP1_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, @@ -1083,8 +1009,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP2_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, @@ -1107,8 +1031,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { .main_clk = "mcbsp3_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP3_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, @@ -1128,8 +1050,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { .main_clk = "mcbsp4_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP4_SHIFT, .module_offs = OMAP3430_PER_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, @@ -1148,8 +1068,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { .main_clk = "mcbsp5_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCBSP5_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, @@ -1190,10 +1108,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { }; /* SR common */ -static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { - .clkact_shift = 20, -}; - static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { .sysc_offs = 0x24, .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), @@ -1206,11 +1120,6 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { .rev = 1, }; -static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { - .sidle_shift = 24, - .enwkup_shift = 26, -}; - static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { .sysc_offs = 0x38, .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), @@ -1237,8 +1146,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = { .main_clk = "sr1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR1_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, @@ -1254,8 +1161,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = { .main_clk = "sr1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR1_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, @@ -1276,8 +1181,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = { .main_clk = "sr2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR2_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, @@ -1293,8 +1196,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = { .main_clk = "sr2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SR2_SHIFT, .module_offs = WKUP_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, @@ -1330,8 +1231,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = { .main_clk = "mailboxes_ick", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, @@ -1373,8 +1272,6 @@ static struct omap_hwmod omap34xx_mcspi1 = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, }, @@ -1394,8 +1291,6 @@ static struct omap_hwmod omap34xx_mcspi2 = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, }, @@ -1417,8 +1312,6 @@ static struct omap_hwmod omap34xx_mcspi3 = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI3_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, }, @@ -1440,8 +1333,6 @@ static struct omap_hwmod omap34xx_mcspi4 = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MCSPI4_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, }, @@ -1475,12 +1366,9 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { .main_clk = "hsotgusb_ick", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, - .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT, }, }, .class = &usbotg_class, @@ -1555,8 +1443,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, }, @@ -1573,8 +1459,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, }, @@ -1604,8 +1488,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, }, @@ -1622,8 +1504,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, }, @@ -1647,8 +1527,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_MMC3_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, }, @@ -1688,11 +1566,8 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { .prcm = { .omap2 = { .module_offs = OMAP3430ES2_USBHOST_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, - .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, }, }, @@ -1766,8 +1641,6 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 3, - .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, .idlest_reg_id = 3, .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, }, @@ -1780,8 +1653,6 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_HDQ_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, }, @@ -1807,8 +1678,6 @@ static struct omap_hwmod omap3xxx_sad2d_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SAD2D_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, }, @@ -1842,8 +1711,6 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = { .prcm = { .omap2 = { .module_offs = WKUP_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_ST_32KSYNC_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, }, @@ -2454,7 +2321,6 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { .prcm = { .omap2 = { .module_offs = OMAP3430_IVA2_MOD, - .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, }, @@ -2732,12 +2598,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { }; /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ -static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { - .sidle_shift = 4, - .srst_shift = 1, - .autoidle_shift = 0, -}; - static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { .rev_offs = 0x5c, .sysc_offs = 0x60, @@ -2760,8 +2620,6 @@ static struct omap_hwmod omap3xxx_sham_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SHA12_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, }, @@ -2778,12 +2636,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { }; /* l4_core -> AES */ -static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { - .sidle_shift = 6, - .srst_shift = 1, - .autoidle_shift = 0, -}; - static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { .rev_offs = 0x44, .sysc_offs = 0x48, @@ -2806,8 +2658,6 @@ static struct omap_hwmod omap3xxx_aes_hwmod = { .prcm = { .omap2 = { .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_AES2_SHIFT, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, }, @@ -2850,8 +2700,6 @@ static struct omap_hwmod omap3xxx_ssi_hwmod = { .main_clk = "ssi_ssr_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SSI_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index c47709659a54..a1901c22a0f0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1658,10 +1658,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { */ /* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { - .sidle_shift = 0, -}; - static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { .sysc_offs = 0x0004, .sysc_flags = SYSC_HAS_SIDLEMODE, @@ -2403,17 +2399,12 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = { */ /* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { - .sidle_shift = 24, - .enwkup_shift = 26, -}; - static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { .sysc_offs = 0x0038, .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type_smartreflex, + .sysc_fields = &omap36xx_sr_sysc_fields, }; static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { @@ -2844,12 +2835,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { */ /* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { - .midle_shift = 4, - .sidle_shift = 2, - .srst_shift = 1, -}; - static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0210, diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index d05e553d6346..4c2a05b1bd19 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -2055,17 +2055,12 @@ static struct omap_hwmod dra7xx_sata_hwmod = { */ /* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { - .sidle_shift = 24, - .enwkup_shift = 26, -}; - static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = { .sysc_offs = 0x0038, .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type_smartreflex, + .sysc_fields = &omap36xx_sr_sysc_fields, }; static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = { @@ -4019,6 +4014,10 @@ static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = { NULL, }; +static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = { + NULL, +}; + static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, NULL, @@ -4028,7 +4027,7 @@ static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { NULL, }; -static struct omap_hwmod_ocp_if *dra74x_dra72x_hwmod_ocp_ifs[] __initdata = { +static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__rtcss, NULL, }; @@ -4040,19 +4039,26 @@ int __init dra7xx_hwmod_init(void) omap_hwmod_init(); ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); - if (!ret && soc_is_dra74x()) + if (!ret && soc_is_dra74x()) { ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); - else if (!ret && soc_is_dra72x()) + if (!ret) + ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); + } else if (!ret && soc_is_dra72x()) { ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); - else if (!ret && soc_is_dra76x()) + if (!ret && !of_machine_is_compatible("ti,dra718")) + ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); + } else if (!ret && soc_is_dra76x()) { ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs); + if (!ret && soc_is_dra76x_acd()) { + ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs); + } else if (!ret && soc_is_dra76x_abz()) { + ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); + } + } + if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP) ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs); - /* now for the IPs available only in dra74 and dra72 */ - if (!ret && !of_machine_is_compatible("ti,dra718") && !soc_is_dra76x()) - ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs); - return ret; } diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 77a515b11ec2..84f118280a0e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -988,7 +988,7 @@ static struct omap_hwmod_class dm81xx_sata_hwmod_class = { static struct omap_hwmod dm81xx_sata_hwmod = { .name = "sata", - .clkdm_name = "default_sata_clkdm", + .clkdm_name = "default_clkdm", .flags = HWMOD_NO_IDLEST, .prcm = { .omap4 = { diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c index 79d623b83e49..77c0b7618ea2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c @@ -16,6 +16,9 @@ * data and their integration with other OMAP modules and Linux. */ +#include <linux/types.h> +#include <linux/platform_data/ti-sysc.h> + #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" @@ -27,7 +30,7 @@ * if the device ip is compliant with the original PRCM protocol * defined for OMAP2420. */ -struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = { +struct sysc_regbits omap_hwmod_sysc_type1 = { .midle_shift = SYSC_TYPE1_MIDLEMODE_SHIFT, .clkact_shift = SYSC_TYPE1_CLOCKACTIVITY_SHIFT, .sidle_shift = SYSC_TYPE1_SIDLEMODE_SHIFT, @@ -43,7 +46,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = { * device ip is compliant with the new PRCM protocol defined for new * OMAP4 IPs. */ -struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = { +struct sysc_regbits omap_hwmod_sysc_type2 = { .midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT, .sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT, .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, @@ -54,7 +57,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = { * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme. * Used by some IPs on AM33xx */ -struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = { +struct sysc_regbits omap_hwmod_sysc_type3 = { .midle_shift = SYSC_TYPE3_MIDLEMODE_SHIFT, .sidle_shift = SYSC_TYPE3_SIDLEMODE_SHIFT, }; @@ -63,3 +66,34 @@ struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = { .manager_count = 2, .has_framedonetv_irq = 0 }; + +struct sysc_regbits omap34xx_sr_sysc_fields = { + .clkact_shift = 20, +}; + +struct sysc_regbits omap36xx_sr_sysc_fields = { + .sidle_shift = 24, + .enwkup_shift = 26, +}; + +struct sysc_regbits omap3_sham_sysc_fields = { + .sidle_shift = 4, + .srst_shift = 1, + .autoidle_shift = 0, +}; + +struct sysc_regbits omap3xxx_aes_sysc_fields = { + .sidle_shift = 6, + .srst_shift = 1, + .autoidle_shift = 0, +}; + +struct sysc_regbits omap_hwmod_sysc_type_mcasp = { + .sidle_shift = 0, +}; + +struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs = { + .midle_shift = 4, + .sidle_shift = 2, + .srst_shift = 1, +}; diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 366158a54fcd..6f68576e5695 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -186,7 +186,7 @@ static void omap_pm_end(void) cpu_idle_poll_ctrl(false); } -static void omap_pm_finish(void) +static void omap_pm_wake(void) { if (soc_is_omap34xx()) omap_prcm_irq_complete(); @@ -196,7 +196,7 @@ static const struct platform_suspend_ops omap_pm_ops = { .begin = omap_pm_begin, .end = omap_pm_end, .enter = omap_pm_enter, - .finish = omap_pm_finish, + .wake = omap_pm_wake, .valid = suspend_valid_only_mem, }; diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 28fa1f8d8363..050891e055a4 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -143,6 +143,14 @@ static inline int is_dra ##subclass (void) \ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ } +#define GET_DRA_PACKAGE (omap_rev() & 0xff) + +#define IS_DRA_SUBCLASS_PACKAGE(subclass, package, id) \ +static inline int is_dra ##subclass ##_ ##package (void) \ +{ \ + return (is_dra ##subclass () && GET_DRA_PACKAGE == id) ? 1 : 0; \ +} + IS_OMAP_CLASS(24xx, 0x24) IS_OMAP_CLASS(34xx, 0x34) IS_OMAP_CLASS(44xx, 0x44) @@ -168,6 +176,8 @@ IS_TI_SUBCLASS(814x, 0x814) IS_AM_SUBCLASS(335x, 0x335) IS_AM_SUBCLASS(437x, 0x437) IS_DRA_SUBCLASS(76x, 0x76) +IS_DRA_SUBCLASS_PACKAGE(76x, abz, 2) +IS_DRA_SUBCLASS_PACKAGE(76x, acd, 3) IS_DRA_SUBCLASS(75x, 0x75) IS_DRA_SUBCLASS(72x, 0x72) @@ -317,10 +327,14 @@ IS_OMAP_TYPE(3430, 0x3430) #if defined(CONFIG_SOC_DRA7XX) #undef soc_is_dra7xx #undef soc_is_dra76x +#undef soc_is_dra76x_abz +#undef soc_is_dra76x_acd #undef soc_is_dra74x #undef soc_is_dra72x #define soc_is_dra7xx() is_dra7xx() #define soc_is_dra76x() is_dra76x() +#define soc_is_dra76x_abz() is_dra76x_abz() +#define soc_is_dra76x_acd() is_dra76x_acd() #define soc_is_dra74x() is_dra75x() #define soc_is_dra72x() is_dra72x() #endif @@ -391,6 +405,8 @@ IS_OMAP_TYPE(3430, 0x3430) #define DRA7XX_CLASS 0x07000000 #define DRA762_REV_ES1_0 (DRA7XX_CLASS | (0x62 << 16) | (0x10 << 8)) +#define DRA762_ABZ_REV_ES1_0 (DRA762_REV_ES1_0 | (2 << 0)) +#define DRA762_ACD_REV_ES1_0 (DRA762_REV_ES1_0 | (3 << 0)) #define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8)) #define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8)) #define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8)) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index ece09c9461f7..d61fbd7a2840 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -156,12 +156,6 @@ static struct clock_event_device clockevent_gpt = { .tick_resume = omap2_gp_timer_shutdown, }; -static struct property device_disabled = { - .name = "status", - .length = sizeof("disabled"), - .value = "disabled", -}; - static const struct of_device_id omap_timer_match[] __initconst = { { .compatible = "ti,omap2420-timer", }, { .compatible = "ti,omap3430-timer", }, @@ -203,8 +197,17 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id * of_get_property(np, "ti,timer-secure", NULL))) continue; - if (!of_device_is_compatible(np, "ti,omap-counter32k")) - of_add_property(np, &device_disabled); + if (!of_device_is_compatible(np, "ti,omap-counter32k")) { + struct property *prop; + + prop = kzalloc(sizeof(*prop), GFP_KERNEL); + if (!prop) + return NULL; + prop->name = "status"; + prop->value = "disabled"; + prop->length = strlen(prop->value); + of_add_property(np, prop); + } return np; } |