diff options
Diffstat (limited to 'arch/arm/mach-realview')
| -rw-r--r-- | arch/arm/mach-realview/Kconfig | 15 | ||||
| -rw-r--r-- | arch/arm/mach-realview/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-realview/core.c | 53 | ||||
| -rw-r--r-- | arch/arm/mach-realview/core.h | 5 | ||||
| -rw-r--r-- | arch/arm/mach-realview/platsmp.c | 56 | ||||
| -rw-r--r-- | arch/arm/mach-realview/realview_eb.c | 149 | ||||
| -rw-r--r-- | arch/arm/mach-realview/realview_pb1176.c | 292 | ||||
| -rw-r--r-- | arch/arm/mach-realview/realview_pb11mp.c | 342 |
8 files changed, 819 insertions, 95 deletions
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 39b3bb7f1020..5ccde7cf39e8 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -10,7 +10,6 @@ config MACH_REALVIEW_EB config REALVIEW_EB_ARM11MP bool "Support ARM11MPCore tile" depends on MACH_REALVIEW_EB - select CACHE_L2X0 help Enable support for the ARM11MPCore tile on the Realview platform. @@ -24,4 +23,18 @@ config REALVIEW_EB_ARM11MP_REVB kernel built with this option enabled is not compatible with other revisions of the ARM11MPCore tile. +config MACH_REALVIEW_PB11MP + bool "Support RealView/PB11MPCore platform" + select ARM_GIC + help + Include support for the ARM(R) RealView MPCore Platform Baseboard. + PB11MPCore is a platform with an on-board ARM11MPCore and has + support for PCI-E and Compact Flash. + +config MACH_REALVIEW_PB1176 + bool "Support RealView/PB1176 platform" + select ARM_GIC + help + Include support for the ARM(R) RealView ARM1176 Platform Baseboard. + endmenu diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index ca1e390c3c28..d2ae077431dd 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile @@ -4,5 +4,7 @@ obj-y := core.o clock.o obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o +obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o +obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 98aefc9f4df3..131990d196f5 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -109,22 +109,21 @@ static struct flash_platform_data realview_flash_data = { .set_vpp = realview_flash_set_vpp, }; -static struct resource realview_flash_resource = { - .start = REALVIEW_FLASH_BASE, - .end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE, - .flags = IORESOURCE_MEM, -}; - struct platform_device realview_flash_device = { .name = "armflash", .id = 0, .dev = { .platform_data = &realview_flash_data, }, - .num_resources = 1, - .resource = &realview_flash_resource, }; +int realview_flash_register(struct resource *res, u32 num) +{ + realview_flash_device.resource = res; + realview_flash_device.num_resources = num; + return platform_device_register(&realview_flash_device); +} + static struct resource realview_i2c_resource = { .start = REALVIEW_I2C_BASE, .end = REALVIEW_I2C_BASE + SZ_4K - 1, @@ -445,10 +444,10 @@ void realview_leds_event(led_event_t ledevt) /* * Where is the timer (VA)? */ -#define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE) -#define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20) -#define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE) -#define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20) +void __iomem *timer0_va_base; +void __iomem *timer1_va_base; +void __iomem *timer2_va_base; +void __iomem *timer3_va_base; /* * How long is the timer interval? @@ -475,7 +474,7 @@ static void timer_set_mode(enum clock_event_mode mode, switch(mode) { case CLOCK_EVT_MODE_PERIODIC: - writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); + writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD); ctrl = TIMER_CTRL_PERIODIC; ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; @@ -491,16 +490,16 @@ static void timer_set_mode(enum clock_event_mode mode, ctrl = 0; } - writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); + writel(ctrl, timer0_va_base + TIMER_CTRL); } static int timer_set_next_event(unsigned long evt, struct clock_event_device *unused) { - unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); + unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL); - writel(evt, TIMER0_VA_BASE + TIMER_LOAD); - writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); + writel(evt, timer0_va_base + TIMER_LOAD); + writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL); return 0; } @@ -536,7 +535,7 @@ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = &timer0_clockevent; /* clear the interrupt */ - writel(1, TIMER0_VA_BASE + TIMER_INTCLR); + writel(1, timer0_va_base + TIMER_INTCLR); evt->event_handler(evt); @@ -551,7 +550,7 @@ static struct irqaction realview_timer_irq = { static cycle_t realview_get_cycles(void) { - return ~readl(TIMER3_VA_BASE + TIMER_VALUE); + return ~readl(timer3_va_base + TIMER_VALUE); } static struct clocksource clocksource_realview = { @@ -566,11 +565,11 @@ static struct clocksource clocksource_realview = { static void __init realview_clocksource_init(void) { /* setup timer 0 as free-running clocksource */ - writel(0, TIMER3_VA_BASE + TIMER_CTRL); - writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); - writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); + writel(0, timer3_va_base + TIMER_CTRL); + writel(0xffffffff, timer3_va_base + TIMER_LOAD); + writel(0xffffffff, timer3_va_base + TIMER_VALUE); writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - TIMER3_VA_BASE + TIMER_CTRL); + timer3_va_base + TIMER_CTRL); clocksource_realview.mult = clocksource_khz2mult(1000, clocksource_realview.shift); @@ -607,10 +606,10 @@ void __init realview_timer_init(unsigned int timer_irq) /* * Initialise to a known state (all timers off) */ - writel(0, TIMER0_VA_BASE + TIMER_CTRL); - writel(0, TIMER1_VA_BASE + TIMER_CTRL); - writel(0, TIMER2_VA_BASE + TIMER_CTRL); - writel(0, TIMER3_VA_BASE + TIMER_CTRL); + writel(0, timer0_va_base + TIMER_CTRL); + writel(0, timer1_va_base + TIMER_CTRL); + writel(0, timer2_va_base + TIMER_CTRL); + writel(0, timer3_va_base + TIMER_CTRL); /* * Make irqs happen for the system timer diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 492a14c0d604..33dbbb41a663 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -55,8 +55,13 @@ extern void __iomem *gic_cpu_base_addr; extern void __iomem *twd_base_addr; extern unsigned int twd_size; #endif +extern void __iomem *timer0_va_base; +extern void __iomem *timer1_va_base; +extern void __iomem *timer2_va_base; +extern void __iomem *timer3_va_base; extern void realview_leds_event(led_event_t ledevt); extern void realview_timer_init(unsigned int timer_irq); +extern int realview_flash_register(struct resource *res, u32 num); #endif diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index de2b7159557d..3e57428affee 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -15,11 +15,14 @@ #include <linux/smp.h> #include <asm/cacheflush.h> -#include <asm/hardware/arm_scu.h> #include <asm/hardware.h> #include <asm/io.h> #include <asm/mach-types.h> +#include <asm/arch/board-eb.h> +#include <asm/arch/board-pb11mp.h> +#include <asm/arch/scu.h> + extern void realview_secondary_startup(void); /* @@ -31,9 +34,15 @@ volatile int __cpuinitdata pen_release = -1; static unsigned int __init get_core_count(void) { unsigned int ncores; + void __iomem *scu_base = 0; + + if (machine_is_realview_eb() && core_tile_eb11mp()) + scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); + else if (machine_is_realview_pb11mp()) + scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); - if (machine_is_realview_eb() && core_tile_eb11mp()) { - ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); + if (scu_base) { + ncores = __raw_readl(scu_base + SCU_CONFIG); ncores = (ncores & 0x03) + 1; } else ncores = 1; @@ -41,6 +50,26 @@ static unsigned int __init get_core_count(void) return ncores; } +/* + * Setup the SCU + */ +static void scu_enable(void) +{ + u32 scu_ctrl; + void __iomem *scu_base; + + if (machine_is_realview_eb() && core_tile_eb11mp()) + scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); + else if (machine_is_realview_pb11mp()) + scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); + else + BUG(); + + scu_ctrl = __raw_readl(scu_base + SCU_CTRL); + scu_ctrl |= 1; + __raw_writel(scu_ctrl, scu_base + SCU_CTRL); +} + static DEFINE_SPINLOCK(boot_lock); void __cpuinit platform_secondary_init(unsigned int cpu) @@ -57,7 +86,10 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); + if (machine_is_realview_eb() && core_tile_eb11mp()) + gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); + else if (machine_is_realview_pb11mp()) + gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); /* * let the primary processor know we're out of the @@ -198,7 +230,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in * realview_timer_init */ - if (machine_is_realview_eb() && core_tile_eb11mp()) + if ((machine_is_realview_eb() && core_tile_eb11mp()) || + machine_is_realview_pb11mp()) local_timer_setup(cpu); #endif @@ -210,11 +243,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus) cpu_set(i, cpu_present_map); /* - * Do we need any more CPUs? If so, then let them know where - * to start. Note that, on modern versions of MILO, the "poke" - * doesn't actually do anything until each individual core is - * sent a soft interrupt to get it out of WFI + * Initialise the SCU if there are more than one CPU and let + * them know where to start. Note that, on modern versions of + * MILO, the "poke" doesn't actually do anything until each + * individual core is sent a soft interrupt to get it out of + * WFI */ - if (max_cpus > 1) + if (max_cpus > 1) { + scu_enable(); poke_milo(); + } } diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 60d9eb810246..5782d83fd886 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -51,13 +51,13 @@ static struct map_desc realview_eb_io_desc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = IO_ADDRESS(REALVIEW_GIC_CPU_BASE), - .pfn = __phys_to_pfn(REALVIEW_GIC_CPU_BASE), + .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE), .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = IO_ADDRESS(REALVIEW_GIC_DIST_BASE), - .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE), + .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE), .length = SZ_4K, .type = MT_DEVICE, }, { @@ -66,20 +66,20 @@ static struct map_desc realview_eb_io_desc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = IO_ADDRESS(REALVIEW_TIMER0_1_BASE), - .pfn = __phys_to_pfn(REALVIEW_TIMER0_1_BASE), + .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE), .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = IO_ADDRESS(REALVIEW_TIMER2_3_BASE), - .pfn = __phys_to_pfn(REALVIEW_TIMER2_3_BASE), + .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE), .length = SZ_4K, .type = MT_DEVICE, }, #ifdef CONFIG_DEBUG_LL { - .virtual = IO_ADDRESS(REALVIEW_UART0_BASE), - .pfn = __phys_to_pfn(REALVIEW_UART0_BASE), + .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE), .length = SZ_4K, .type = MT_DEVICE, } @@ -136,12 +136,12 @@ static void __init realview_eb_map_io(void) /* * These devices are connected directly to the multi-layer AHB switch */ -#define SMC_IRQ { NO_IRQ, NO_IRQ } -#define SMC_DMA { 0, 0 } +#define EB_SMC_IRQ { NO_IRQ, NO_IRQ } +#define EB_SMC_DMA { 0, 0 } #define MPMC_IRQ { NO_IRQ, NO_IRQ } #define MPMC_DMA { 0, 0 } -#define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } -#define CLCD_DMA { 0, 0 } +#define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } +#define EB_CLCD_DMA { 0, 0 } #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } #define DMAC_DMA { 0, 0 } @@ -150,53 +150,53 @@ static void __init realview_eb_map_io(void) */ #define SCTL_IRQ { NO_IRQ, NO_IRQ } #define SCTL_DMA { 0, 0 } -#define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } -#define WATCHDOG_DMA { 0, 0 } -#define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } -#define GPIO0_DMA { 0, 0 } +#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } +#define EB_WATCHDOG_DMA { 0, 0 } +#define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } +#define EB_GPIO0_DMA { 0, 0 } #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } #define GPIO1_DMA { 0, 0 } -#define RTC_IRQ { IRQ_EB_RTC, NO_IRQ } -#define RTC_DMA { 0, 0 } +#define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } +#define EB_RTC_DMA { 0, 0 } /* * These devices are connected via the DMA APB bridge */ #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } #define SCI_DMA { 7, 6 } -#define UART0_IRQ { IRQ_EB_UART0, NO_IRQ } -#define UART0_DMA { 15, 14 } -#define UART1_IRQ { IRQ_EB_UART1, NO_IRQ } -#define UART1_DMA { 13, 12 } -#define UART2_IRQ { IRQ_EB_UART2, NO_IRQ } -#define UART2_DMA { 11, 10 } -#define UART3_IRQ { IRQ_EB_UART3, NO_IRQ } -#define UART3_DMA { 0x86, 0x87 } -#define SSP_IRQ { IRQ_EB_SSP, NO_IRQ } -#define SSP_DMA { 9, 8 } +#define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } +#define EB_UART0_DMA { 15, 14 } +#define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } +#define EB_UART1_DMA { 13, 12 } +#define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } +#define EB_UART2_DMA { 11, 10 } +#define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } +#define EB_UART3_DMA { 0x86, 0x87 } +#define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } +#define EB_SSP_DMA { 9, 8 } /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); -AMBA_DEVICE(uart3, "fpga:09", UART3, NULL); +AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL); /* DevChip Primecells */ -AMBA_DEVICE(smc, "dev:00", SMC, NULL); -AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data); +AMBA_DEVICE(smc, "dev:00", EB_SMC, NULL); +AMBA_DEVICE(clcd, "dev:20", EB_CLCD, &clcd_plat_data); AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); -AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); -AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL); +AMBA_DEVICE(wdog, "dev:e1", EB_WATCHDOG, NULL); +AMBA_DEVICE(gpio0, "dev:e4", EB_GPIO0, NULL); AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); -AMBA_DEVICE(rtc, "dev:e8", RTC, NULL); +AMBA_DEVICE(rtc, "dev:e8", EB_RTC, NULL); AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); -AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); -AMBA_DEVICE(uart1, "dev:f2", UART1, NULL); -AMBA_DEVICE(uart2, "dev:f3", UART2, NULL); -AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL); +AMBA_DEVICE(uart0, "dev:f1", EB_UART0, NULL); +AMBA_DEVICE(uart1, "dev:f2", EB_UART1, NULL); +AMBA_DEVICE(uart2, "dev:f3", EB_UART2, NULL); +AMBA_DEVICE(ssp0, "dev:f4", EB_SSP, NULL); static struct amba_device *amba_devs[] __initdata = { &dmac_device, @@ -223,11 +223,16 @@ static struct amba_device *amba_devs[] __initdata = { /* * RealView EB platform devices */ +static struct resource realview_eb_flash_resource = { + .start = REALVIEW_EB_FLASH_BASE, + .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; -static struct resource realview_eb_smc91x_resources[] = { +static struct resource realview_eb_eth_resources[] = { [0] = { - .start = REALVIEW_ETH_BASE, - .end = REALVIEW_ETH_BASE + SZ_64K - 1, + .start = REALVIEW_EB_ETH_BASE, + .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -237,13 +242,36 @@ static struct resource realview_eb_smc91x_resources[] = { }, }; -static struct platform_device realview_eb_smc91x_device = { - .name = "smc91x", +static struct platform_device realview_eb_eth_device = { .id = 0, - .num_resources = ARRAY_SIZE(realview_eb_smc91x_resources), - .resource = realview_eb_smc91x_resources, + .num_resources = ARRAY_SIZE(realview_eb_eth_resources), + .resource = realview_eb_eth_resources, }; +/* + * Detect and register the correct Ethernet device. RealView/EB rev D + * platforms use the newer SMSC LAN9118 Ethernet chip + */ +static int eth_device_register(void) +{ + void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K); + u32 idrev; + + if (!eth_addr) + return -ENOMEM; + + idrev = readl(eth_addr + 0x50); + if ((idrev & 0xFFFF0000) == 0x01180000) + /* SMSC LAN9118 chip present */ + realview_eb_eth_device.name = "smc911x"; + else + /* SMSC 91C111 chip present */ + realview_eb_eth_device.name = "smc91x"; + + iounmap(eth_addr); + return platform_device_register(&realview_eb_eth_device); +} + static void __init gic_init_irq(void) { if (core_tile_eb11mp()) { @@ -263,14 +291,14 @@ static void __init gic_init_irq(void) #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB /* board GIC, secondary */ - gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64); - gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE)); + gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64); + gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE)); gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); #endif } else { /* board GIC, primary */ - gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE); - gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); + gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29); gic_cpu_init(0, gic_cpu_base_addr); } } @@ -301,14 +329,19 @@ static void realview_eb11mp_fixup(void) kmi1_device.irq[0] = IRQ_EB11MP_KMI1; /* platform devices */ - realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH; - realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH; + realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH; + realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH; } static void __init realview_eb_timer_init(void) { unsigned int timer_irq; + timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE); + timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20; + timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE); + timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20; + if (core_tile_eb11mp()) { #ifdef CONFIG_LOCAL_TIMERS twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE); @@ -332,16 +365,18 @@ static void __init realview_eb_init(void) if (core_tile_eb11mp()) { realview_eb11mp_fixup(); +#ifdef CONFIG_CACHE_L2X0 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled * Bits: .... ...0 0111 1001 0000 .... .... .... */ l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); +#endif } clk_register(&realview_clcd_clk); - platform_device_register(&realview_flash_device); - platform_device_register(&realview_eb_smc91x_device); + realview_flash_register(&realview_eb_flash_resource, 1); platform_device_register(&realview_i2c_device); + eth_device_register(); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; @@ -355,8 +390,8 @@ static void __init realview_eb_init(void) MACHINE_START(REALVIEW_EB, "ARM-RealView EB") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .phys_io = REALVIEW_UART0_BASE, - .io_pg_offst = (IO_ADDRESS(REALVIEW_UART0_BASE) >> 18) & 0xfffc, + .phys_io = REALVIEW_EB_UART0_BASE, + .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc, .boot_params = 0x00000100, .map_io = realview_eb_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c new file mode 100644 index 000000000000..cf7f576a5860 --- /dev/null +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -0,0 +1,292 @@ +/* + * linux/arch/arm/mach-realview/realview_pb1176.c + * + * Copyright (C) 2008 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/amba/bus.h> + +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/leds.h> +#include <asm/mach-types.h> +#include <asm/hardware/gic.h> +#include <asm/hardware/icst307.h> +#include <asm/hardware/cache-l2x0.h> + +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> +#include <asm/mach/map.h> +#include <asm/mach/mmc.h> +#include <asm/mach/time.h> + +#include <asm/arch/board-pb1176.h> +#include <asm/arch/irqs.h> + +#include "core.h" +#include "clock.h" + +static struct map_desc realview_pb1176_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), + .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), + .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB1176_L220_BASE), + .length = SZ_8K, + .type = MT_DEVICE, + }, +#ifdef CONFIG_DEBUG_LL + { + .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif +}; + +static void __init realview_pb1176_map_io(void) +{ + iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc)); +} + +/* + * RealView PB1176 AMBA devices + */ +#define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ } +#define GPIO2_DMA { 0, 0 } +#define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ } +#define GPIO3_DMA { 0, 0 } +#define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ } +#define AACI_DMA { 0x80, 0x81 } +#define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B } +#define MMCI0_DMA { 0x84, 0 } +#define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ } +#define KMI0_DMA { 0, 0 } +#define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ } +#define KMI1_DMA { 0, 0 } +#define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ } +#define PB1176_SMC_DMA { 0, 0 } +#define MPMC_IRQ { NO_IRQ, NO_IRQ } +#define MPMC_DMA { 0, 0 } +#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } +#define PB1176_CLCD_DMA { 0, 0 } +#define DMAC_IRQ { IRQ_PB1176_DMAC, NO_IRQ } +#define DMAC_DMA { 0, 0 } +#define SCTL_IRQ { NO_IRQ, NO_IRQ } +#define SCTL_DMA { 0, 0 } +#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } +#define PB1176_WATCHDOG_DMA { 0, 0 } +#define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ } +#define PB1176_GPIO0_DMA { 0, 0 } +#define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ } +#define GPIO1_DMA { 0, 0 } +#define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ } +#define PB1176_RTC_DMA { 0, 0 } +#define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ } +#define SCI_DMA { 7, 6 } +#define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ } +#define PB1176_UART0_DMA { 15, 14 } +#define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ } +#define PB1176_UART1_DMA { 13, 12 } +#define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ } +#define PB1176_UART2_DMA { 11, 10 } +#define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } +#define PB1176_UART3_DMA { 0x86, 0x87 } +#define PB1176_SSP_IRQ { IRQ_PB1176_SSP, NO_IRQ } +#define PB1176_SSP_DMA { 9, 8 } + +/* FPGA Primecells */ +AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); +AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); +AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); +AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); +AMBA_DEVICE(uart3, "fpga:09", PB1176_UART3, NULL); + +/* DevChip Primecells */ +AMBA_DEVICE(smc, "dev:00", PB1176_SMC, NULL); +AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); +AMBA_DEVICE(wdog, "dev:e1", PB1176_WATCHDOG, NULL); +AMBA_DEVICE(gpio0, "dev:e4", PB1176_GPIO0, NULL); +AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); +AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); +AMBA_DEVICE(rtc, "dev:e8", PB1176_RTC, NULL); +AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); +AMBA_DEVICE(uart0, "dev:f1", PB1176_UART0, NULL); +AMBA_DEVICE(uart1, "dev:f2", PB1176_UART1, NULL); +AMBA_DEVICE(uart2, "dev:f3", PB1176_UART2, NULL); +AMBA_DEVICE(ssp0, "dev:f4", PB1176_SSP, NULL); + +/* Primecells on the NEC ISSP chip */ +AMBA_DEVICE(clcd, "issp:20", PB1176_CLCD, &clcd_plat_data); +//AMBA_DEVICE(dmac, "issp:30", PB1176_DMAC, NULL); + +static struct amba_device *amba_devs[] __initdata = { +// &dmac_device, + &uart0_device, + &uart1_device, + &uart2_device, + &uart3_device, + &smc_device, + &clcd_device, + &sctl_device, + &wdog_device, + &gpio0_device, + &gpio1_device, + &gpio2_device, + &rtc_device, + &sci0_device, + &ssp0_device, + &aaci_device, + &mmc0_device, + &kmi0_device, + &kmi1_device, +}; + +/* + * RealView PB1176 platform devices + */ +static struct resource realview_pb1176_flash_resource = { + .start = REALVIEW_PB1176_FLASH_BASE, + .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct resource realview_pb1176_smsc911x_resources[] = { + [0] = { + .start = REALVIEW_PB1176_ETH_BASE, + .end = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PB1176_ETH, + .end = IRQ_PB1176_ETH, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device realview_pb1176_smsc911x_device = { + .name = "smc911x", + .id = 0, + .num_resources = ARRAY_SIZE(realview_pb1176_smsc911x_resources), + .resource = realview_pb1176_smsc911x_resources, +}; + +static void __init gic_init_irq(void) +{ + /* ARM1176 DevChip GIC, primary */ + gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START); + gic_cpu_init(0, gic_cpu_base_addr); + + /* board GIC, secondary */ + gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START); + gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE)); + gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1); +} + +static void __init realview_pb1176_timer_init(void) +{ + timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE); + timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20; + timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE); + timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20; + + realview_timer_init(IRQ_DC1176_TIMER0); +} + +static struct sys_timer realview_pb1176_timer = { + .init = realview_pb1176_timer_init, +}; + +static void __init realview_pb1176_init(void) +{ + int i; + +#ifdef CONFIG_CACHE_L2X0 + /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */ + l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff); +#endif + + clk_register(&realview_clcd_clk); + + realview_flash_register(&realview_pb1176_flash_resource, 1); + platform_device_register(&realview_pb1176_smsc911x_device); + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + +#ifdef CONFIG_LEDS + leds_event = realview_leds_event; +#endif +} + +MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") + /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ + .phys_io = REALVIEW_PB1176_UART0_BASE, + .io_pg_offst = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = realview_pb1176_map_io, + .init_irq = gic_init_irq, + .timer = &realview_pb1176_timer, + .init_machine = realview_pb1176_init, +MACHINE_END diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c new file mode 100644 index 000000000000..f7ce1c5a178a --- /dev/null +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -0,0 +1,342 @@ +/* + * linux/arch/arm/mach-realview/realview_pb11mp.c + * + * Copyright (C) 2008 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/amba/bus.h> + +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/leds.h> +#include <asm/mach-types.h> +#include <asm/hardware/gic.h> +#include <asm/hardware/icst307.h> +#include <asm/hardware/cache-l2x0.h> + +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> +#include <asm/mach/map.h> +#include <asm/mach/mmc.h> +#include <asm/mach/time.h> + +#include <asm/arch/board-pb11mp.h> +#include <asm/arch/irqs.h> + +#include "core.h" +#include "clock.h" + +static struct map_desc realview_pb11mp_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), + .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), + .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE), + .pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE), + .length = SZ_8K, + .type = MT_DEVICE, + }, +#ifdef CONFIG_DEBUG_LL + { + .virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE), + .pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif +}; + +static void __init realview_pb11mp_map_io(void) +{ + iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc)); +} + +/* + * RealView PB11MPCore AMBA devices + */ + +#define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ } +#define GPIO2_DMA { 0, 0 } +#define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ } +#define GPIO3_DMA { 0, 0 } +#define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ } +#define AACI_DMA { 0x80, 0x81 } +#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B } +#define MMCI0_DMA { 0x84, 0 } +#define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ } +#define KMI0_DMA { 0, 0 } +#define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ } +#define KMI1_DMA { 0, 0 } +#define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ } +#define PB11MP_SMC_DMA { 0, 0 } +#define MPMC_IRQ { NO_IRQ, NO_IRQ } +#define MPMC_DMA { 0, 0 } +#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ } +#define PB11MP_CLCD_DMA { 0, 0 } +#define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ } +#define DMAC_DMA { 0, 0 } +#define SCTL_IRQ { NO_IRQ, NO_IRQ } +#define SCTL_DMA { 0, 0 } +#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ } +#define PB11MP_WATCHDOG_DMA { 0, 0 } +#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ } +#define PB11MP_GPIO0_DMA { 0, 0 } +#define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ } +#define GPIO1_DMA { 0, 0 } +#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ } +#define PB11MP_RTC_DMA { 0, 0 } +#define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ } +#define SCI_DMA { 7, 6 } +#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ } +#define PB11MP_UART0_DMA { 15, 14 } +#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ } +#define PB11MP_UART1_DMA { 13, 12 } +#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ } +#define PB11MP_UART2_DMA { 11, 10 } +#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ } +#define PB11MP_UART3_DMA { 0x86, 0x87 } +#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ } +#define PB11MP_SSP_DMA { 9, 8 } + +/* FPGA Primecells */ +AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); +AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); +AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); +AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); +AMBA_DEVICE(uart3, "fpga:09", PB11MP_UART3, NULL); + +/* DevChip Primecells */ +AMBA_DEVICE(smc, "dev:00", PB11MP_SMC, NULL); +AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); +AMBA_DEVICE(wdog, "dev:e1", PB11MP_WATCHDOG, NULL); +AMBA_DEVICE(gpio0, "dev:e4", PB11MP_GPIO0, NULL); +AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); +AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); +AMBA_DEVICE(rtc, "dev:e8", PB11MP_RTC, NULL); +AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); +AMBA_DEVICE(uart0, "dev:f1", PB11MP_UART0, NULL); +AMBA_DEVICE(uart1, "dev:f2", PB11MP_UART1, NULL); +AMBA_DEVICE(uart2, "dev:f3", PB11MP_UART2, NULL); +AMBA_DEVICE(ssp0, "dev:f4", PB11MP_SSP, NULL); + +/* Primecells on the NEC ISSP chip */ +AMBA_DEVICE(clcd, "issp:20", PB11MP_CLCD, &clcd_plat_data); +AMBA_DEVICE(dmac, "issp:30", DMAC, NULL); + +static struct amba_device *amba_devs[] __initdata = { + &dmac_device, + &uart0_device, + &uart1_device, + &uart2_device, + &uart3_device, + &smc_device, + &clcd_device, + &sctl_device, + &wdog_device, + &gpio0_device, + &gpio1_device, + &gpio2_device, + &rtc_device, + &sci0_device, + &ssp0_device, + &aaci_device, + &mmc0_device, + &kmi0_device, + &kmi1_device, +}; + +/* + * RealView PB11MPCore platform devices + */ +static struct resource realview_pb11mp_flash_resource[] = { + [0] = { + .start = REALVIEW_PB11MP_FLASH0_BASE, + .end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = REALVIEW_PB11MP_FLASH1_BASE, + .end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource realview_pb11mp_smsc911x_resources[] = { + [0] = { + .start = REALVIEW_PB11MP_ETH_BASE, + .end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TC11MP_ETH, + .end = IRQ_TC11MP_ETH, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device realview_pb11mp_smsc911x_device = { + .name = "smc911x", + .id = 0, + .num_resources = ARRAY_SIZE(realview_pb11mp_smsc911x_resources), + .resource = realview_pb11mp_smsc911x_resources, +}; + +struct resource realview_pb11mp_cf_resources[] = { + [0] = { + .start = REALVIEW_PB11MP_CF_BASE, + .end = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = REALVIEW_PB11MP_CF_MEM_BASE, + .end = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = -1, /* FIXME: Find correct irq */ + .end = -1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device realview_pb11mp_cf_device = { + .name = "compactflash", + .id = 0, + .num_resources = ARRAY_SIZE(realview_pb11mp_cf_resources), + .resource = realview_pb11mp_cf_resources, +}; + +static void __init gic_init_irq(void) +{ + unsigned int pldctrl; + + /* new irq mode with no DCC */ + writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); + pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1); + pldctrl |= 2 << 22; + writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1); + writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); + + /* ARM11MPCore test chip GIC, primary */ + gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29); + gic_cpu_init(0, gic_cpu_base_addr); + + /* board GIC, secondary */ + gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START); + gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE)); + gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1); +} + +static void __init realview_pb11mp_timer_init(void) +{ + timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE); + timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20; + timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); + timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; + +#ifdef CONFIG_LOCAL_TIMERS + twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE); + twd_size = REALVIEW_TC11MP_TWD_SIZE; +#endif + realview_timer_init(IRQ_TC11MP_TIMER0_1); +} + +static struct sys_timer realview_pb11mp_timer = { + .init = realview_pb11mp_timer_init, +}; + +static void __init realview_pb11mp_init(void) +{ + int i; + +#ifdef CONFIG_CACHE_L2X0 + /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled + * Bits: .... ...0 0111 1001 0000 .... .... .... */ + l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff); +#endif + + clk_register(&realview_clcd_clk); + + realview_flash_register(realview_pb11mp_flash_resource, + ARRAY_SIZE(realview_pb11mp_flash_resource)); + platform_device_register(&realview_pb11mp_smsc911x_device); + platform_device_register(&realview_i2c_device); + platform_device_register(&realview_pb11mp_cf_device); + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + +#ifdef CONFIG_LEDS + leds_event = realview_leds_event; +#endif +} + +MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") + /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ + .phys_io = REALVIEW_PB11MP_UART0_BASE, + .io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = realview_pb11mp_map_io, + .init_irq = gic_init_irq, + .timer = &realview_pb11mp_timer, + .init_machine = realview_pb11mp_init, +MACHINE_END |