diff options
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 2072b637b5af..ae0a7cfeeb47 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -2,7 +2,7 @@ /* * dts file for Hisilicon Hi6220 SoC * - * Copyright (C) 2015, Hisilicon Ltd. + * Copyright (C) 2015, HiSilicon Ltd. */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -193,7 +193,7 @@ }; }; - cpu_opp_table: cpu_opp_table { + cpu_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -302,7 +302,7 @@ mboxes = <&mailbox 1 0 11>; }; - uart0: uart@f8015000 { /* console */ + uart0: serial@f8015000 { /* console */ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -311,7 +311,7 @@ clock-names = "uartclk", "apb_pclk"; }; - uart1: uart@f7111000 { + uart1: serial@f7111000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7111000 0x0 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -325,7 +325,7 @@ status = "disabled"; }; - uart2: uart@f7112000 { + uart2: serial@f7112000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7112000 0x0 0x1000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -337,7 +337,7 @@ status = "disabled"; }; - uart3: uart@f7113000 { + uart3: serial@f7113000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7113000 0x0 0x1000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; @@ -349,7 +349,7 @@ status = "disabled"; }; - uart4: uart@f7114000 { + uart4: serial@f7114000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7114000 0x0 0x1000>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; @@ -371,7 +371,7 @@ clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; dma-no-cci; dma-type = "hi6220_dma"; - status = "ok"; + status = "okay"; }; dual_timer0: timer@f8008000 { @@ -725,8 +725,8 @@ interrupts = <0 50 4>; bus-id = <0>; enable-dma = <0>; - clocks = <&sys_ctrl HI6220_SPI_CLK>; - clock-names = "apb_pclk"; + clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; num-cs = <1>; @@ -840,11 +840,12 @@ }; watchdog0: watchdog@f8005000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xf8005000 0x0 0x1000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ao_ctrl HI6220_WDT0_PCLK>; - clock-names = "apb_pclk"; + clocks = <&ao_ctrl HI6220_WDT0_PCLK>, + <&ao_ctrl HI6220_WDT0_PCLK>; + clock-names = "wdog_clk", "apb_pclk"; }; tsensor: tsensor@0,f7030700 { @@ -871,7 +872,7 @@ thermal-zones { - cls0: cls0 { + cls0: cls0-thermal { polling-delay = <1000>; polling-delay-passive = <100>; sustainable-power = <3326>; @@ -880,13 +881,13 @@ thermal-sensors = <&tsensor 2>; trips { - threshold: trip-point@0 { + threshold: trip-point0 { temperature = <65000>; hysteresis = <0>; type = "passive"; }; - target: trip-point@1 { + target: trip-point1 { temperature = <75000>; hysteresis = <0>; type = "passive"; @@ -1052,7 +1053,7 @@ "ppmmu3"; clocks = <&media_ctrl HI6220_G3D_CLK>, <&media_ctrl HI6220_G3D_PCLK>; - clock-names = "core", "bus"; + clock-names = "bus", "core"; assigned-clocks = <&media_ctrl HI6220_G3D_CLK>, <&media_ctrl HI6220_G3D_PCLK>; assigned-clock-rates = <500000000>, <144000000>; |