diff options
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8183.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8183.dtsi | 481 |
1 files changed, 462 insertions, 19 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index ba4584faca5a..a70b669c49ba 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -42,6 +42,252 @@ rdma1 = &rdma1; }; + cluster0_opp: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + opp0-793000000 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <650000>; + required-opps = <&opp2_00>; + }; + opp0-910000000 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <687500>; + required-opps = <&opp2_01>; + }; + opp0-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <718750>; + required-opps = <&opp2_02>; + }; + opp0-1131000000 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <756250>; + required-opps = <&opp2_03>; + }; + opp0-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp0-1326000000 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <818750>; + required-opps = <&opp2_05>; + }; + opp0-1417000000 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp0-1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <868750>; + required-opps = <&opp2_07>; + }; + opp0-1586000000 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <893750>; + required-opps = <&opp2_08>; + }; + opp0-1625000000 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <906250>; + required-opps = <&opp2_09>; + }; + opp0-1677000000 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp0-1716000000 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <943750>; + required-opps = <&opp2_11>; + }; + opp0-1781000000 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp0-1846000000 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp0-1924000000 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp0-1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; }; + + cluster1_opp: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + opp1-793000000 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <700000>; + required-opps = <&opp2_00>; + }; + opp1-910000000 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <725000>; + required-opps = <&opp2_01>; + }; + opp1-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <750000>; + required-opps = <&opp2_02>; + }; + opp1-1131000000 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <775000>; + required-opps = <&opp2_03>; + }; + opp1-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp1-1326000000 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <825000>; + required-opps = <&opp2_05>; + }; + opp1-1417000000 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp1-1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <875000>; + required-opps = <&opp2_07>; + }; + opp1-1586000000 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <900000>; + required-opps = <&opp2_08>; + }; + opp1-1625000000 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <912500>; + required-opps = <&opp2_09>; + }; + opp1-1677000000 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp1-1716000000 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <950000>; + required-opps = <&opp2_11>; + }; + opp1-1781000000 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp1-1846000000 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp1-1924000000 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp1-1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; + }; + + cci_opp: opp-table-cci { + compatible = "operating-points-v2"; + opp-shared; + opp2_00: opp-273000000 { + opp-hz = /bits/ 64 <273000000>; + opp-microvolt = <650000>; + }; + opp2_01: opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + opp-microvolt = <687500>; + }; + opp2_02: opp-403000000 { + opp-hz = /bits/ 64 <403000000>; + opp-microvolt = <718750>; + }; + opp2_03: opp-463000000 { + opp-hz = /bits/ 64 <463000000>; + opp-microvolt = <756250>; + }; + opp2_04: opp-546000000 { + opp-hz = /bits/ 64 <546000000>; + opp-microvolt = <800000>; + }; + opp2_05: opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <818750>; + }; + opp2_06: opp-689000000 { + opp-hz = /bits/ 64 <689000000>; + opp-microvolt = <850000>; + }; + opp2_07: opp-767000000 { + opp-hz = /bits/ 64 <767000000>; + opp-microvolt = <868750>; + }; + opp2_08: opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + opp-microvolt = <893750>; + }; + opp2_09: opp-871000000 { + opp-hz = /bits/ 64 <871000000>; + opp-microvolt = <906250>; + }; + opp2_10: opp-923000000 { + opp-hz = /bits/ 64 <923000000>; + opp-microvolt = <931250>; + }; + opp2_11: opp-962000000 { + opp-hz = /bits/ 64 <962000000>; + opp-microvolt = <943750>; + }; + opp2_12: opp-1027000000 { + opp-hz = /bits/ 64 <1027000000>; + opp-microvolt = <975000>; + }; + opp2_13: opp-1092000000 { + opp-hz = /bits/ 64 <1092000000>; + opp-microvolt = <1000000>; + }; + opp2_14: opp-1144000000 { + opp-hz = /bits/ 64 <1144000000>; + opp-microvolt = <1025000>; + }; + opp2_15: opp-1196000000 { + opp-hz = /bits/ 64 <1196000000>; + opp-microvolt = <1050000>; + }; + }; + + cci: cci { + compatible = "mediatek,mt8183-cci"; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -85,8 +331,13 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu1: cpu@1 { @@ -96,8 +347,13 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu2: cpu@2 { @@ -107,8 +363,13 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu3: cpu@3 { @@ -118,8 +379,13 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu4: cpu@100 { @@ -129,8 +395,13 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu5: cpu@101 { @@ -140,8 +411,13 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu6: cpu@102 { @@ -151,8 +427,13 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu7: cpu@103 { @@ -162,8 +443,13 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; idle-states { @@ -197,7 +483,7 @@ }; }; - gpu_opp_table: opp_table0 { + gpu_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -295,8 +581,8 @@ }; psci { - compatible = "arm,psci-1.0"; - method = "smc"; + compatible = "arm,psci-1.0"; + method = "smc"; }; clk26m: oscillator { @@ -321,7 +607,7 @@ compatible = "simple-bus"; ranges; - soc_data: soc_data@8000000 { + soc_data: efuse@8000000 { compatible = "mediatek,mt8183-efuse", "mediatek,efuse"; reg = <0 0x08000000 0 0x0010>; @@ -367,6 +653,70 @@ reg = <0 0x0c530a80 0 0x50>; }; + cpu_debug0: cpu-debug@d410000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd410000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + cpu_debug1: cpu-debug@d510000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd510000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + cpu_debug2: cpu-debug@d610000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd610000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + cpu_debug3: cpu-debug@d710000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd710000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + + cpu_debug4: cpu-debug@d810000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd810000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + }; + + cpu_debug5: cpu-debug@d910000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd910000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + }; + + cpu_debug6: cpu-debug@da10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xda10000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + }; + + cpu_debug7: cpu-debug@db10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xdb10000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + }; + topckgen: syscon@10000000 { compatible = "mediatek,mt8183-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; @@ -411,9 +761,8 @@ }; scpsys: syscon@10006000 { - compatible = "syscon", "simple-mfd"; + compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { @@ -438,9 +787,9 @@ #power-domain-cells = <0>; }; - power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { + mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; - clocks = <&topckgen CLK_TOP_MUX_MFG>; + clocks = <&topckgen CLK_TOP_MUX_MFG>; clock-names = "mfg"; #address-cells = <1>; #size-cells = <0>; @@ -593,6 +942,15 @@ clock-names = "spi", "wrap"; }; + keyboard: keyboard@10010000 { + compatible = "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + scp: scp@10500000 { compatible = "mediatek,mt8183-scp"; reg = <0 0x10500000 0 0x80000>, @@ -618,8 +976,8 @@ compatible = "mediatek,mt8183-m4u"; reg = <0 0x10205000 0 0x1000>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 - &larb4 &larb5 &larb6>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, + <&larb4>, <&larb5>, <&larb6>; #iommu-cells = <1>; }; @@ -743,6 +1101,18 @@ status = "disabled"; }; + svs: svs@1100b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, + <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", + "t-calibration-data"; + }; + thermal: thermal@1100b000 { #thermal-sensor-cells = <1>; compatible = "mediatek,mt8183-thermal"; @@ -759,7 +1129,7 @@ }; thermal_zones: thermal-zones { - cpu_thermal: cpu_thermal { + cpu_thermal: cpu-thermal { polling-delay-passive = <100>; polling-delay = <500>; thermal-sensors = <&thermal 0>; @@ -1086,7 +1456,7 @@ }; ssusb: usb@11201000 { - compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; + compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; @@ -1261,6 +1631,10 @@ mipi_tx_calibration: calib@190 { reg = <0x190 0xc>; }; + + svs_calibration: calib@580 { + reg = <0x580 0x64>; + }; }; u3phy: t-phy@11f40000 { @@ -1325,6 +1699,60 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + mdp3-rdma0@14001000 { + compatible = "mediatek,mt8183-mdp3-rdma"; + reg = <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, + <CMDQ_EVENT_MDP_RDMA0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; + }; + + mdp3-rsz0@14003000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, + <CMDQ_EVENT_MDP_RSZ0_EOF>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3-rsz1@14004000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, + <CMDQ_EVENT_MDP_RSZ1_EOF>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; + + mdp3-wrot0@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, + <CMDQ_EVENT_MDP_WROT0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp3-wdma@14006000 { + compatible = "mediatek,mt8183-mdp3-wdma"; + reg = <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, + <CMDQ_EVENT_MDP_WDMA0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu M4U_PORT_MDP_WDMA0>; + }; + ovl0: ovl@14008000 { compatible = "mediatek,mt8183-disp-ovl"; reg = <0 0x14008000 0 0x1000>; @@ -1332,7 +1760,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; @@ -1343,7 +1770,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; @@ -1354,7 +1780,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; @@ -1365,7 +1790,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb = <&larb0>; mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; @@ -1377,7 +1801,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb0>; mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; @@ -1402,8 +1825,7 @@ }; aal0: aal@14010000 { - compatible = "mediatek,mt8183-disp-aal", - "mediatek,mt8173-disp-aal"; + compatible = "mediatek,mt8183-disp-aal"; reg = <0 0x14010000 0 0x1000>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; @@ -1450,6 +1872,7 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, <CMDQ_EVENT_MUTEX_STREAM_DONE1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; }; larb0: larb@14017000 { @@ -1473,6 +1896,15 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; }; + mdp3-ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp3-ccorr"; + reg = <0 0x1401c000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, + <CMDQ_EVENT_MDP_CCORR_EOF>; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; @@ -1530,6 +1962,17 @@ power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; }; + venc_jpg: venc_jpg@17030000 { + compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; + reg = <0 0x17030000 0 0x1000>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_JPGENC_RDMA>, + <&iommu M4U_PORT_JPGENC_BSDMA>; + power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_JPGENC>; + clock-names = "jpgenc"; + }; + ipu_conn: syscon@19000000 { compatible = "mediatek,mt8183-ipu_conn", "syscon"; reg = <0 0x19000000 0 0x1000>; |