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-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi247
1 files changed, 233 insertions, 14 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 3c4acfca459d..41f3a7e188d0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -23,7 +23,7 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
- misc@100000 {
+ apbmisc: misc@100000 {
compatible = "nvidia,tegra194-misc";
reg = <0x00100000 0xf000>,
<0x0010f000 0x1000>;
@@ -88,6 +88,27 @@
gpio-controller;
};
+ cbb-noc@2300000 {
+ compatible = "nvidia,tegra194-cbb-noc";
+ reg = <0x02300000 0x1000>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,axi2apb = <&axi2apb>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
+ axi2apb: axi2apb@2390000 {
+ compatible = "nvidia,tegra194-axi2apb";
+ reg = <0x2390000 0x1000>,
+ <0x23a0000 0x1000>,
+ <0x23b0000 0x1000>,
+ <0x23c0000 0x1000>,
+ <0x23d0000 0x1000>,
+ <0x23e0000 0x1000>;
+ status = "okay";
+ };
+
ethernet@2490000 {
compatible = "nvidia,tegra194-eqos",
"nvidia,tegra186-eqos",
@@ -115,6 +136,49 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma-controller@2600000 {
+ compatible = "nvidia,tegra194-gpcdma",
+ "nvidia,tegra186-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA194_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ status = "okay";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra194-aconnect",
"nvidia,tegra210-aconnect";
@@ -243,6 +307,10 @@
"rx19", "tx19",
"rx20", "tx20";
status = "disabled";
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_APE>;
};
tegra_i2s1: i2s@2901000 {
@@ -515,6 +583,29 @@
status = "disabled";
};
+ tegra_ope1: processing-engine@2908000 {
+ compatible = "nvidia,tegra194-ope",
+ "nvidia,tegra210-ope";
+ reg = <0x2908000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ sound-name-prefix = "OPE1";
+ status = "disabled";
+
+ equalizer@2908100 {
+ compatible = "nvidia,tegra194-peq",
+ "nvidia,tegra210-peq";
+ reg = <0x2908100 0x100>;
+ };
+
+ dynamic-range-compressor@2908200 {
+ compatible = "nvidia,tegra194-mbdrc",
+ "nvidia,tegra210-mbdrc";
+ reg = <0x2908200 0x200>;
+ };
+ };
+
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra194-amixer",
"nvidia,tegra210-amixer";
@@ -522,6 +613,14 @@
sound-name-prefix = "MIXER1";
status = "disabled";
};
+
+ tegra_asrc: asrc@2910000 {
+ compatible = "nvidia,tegra194-asrc",
+ "nvidia,tegra186-asrc";
+ reg = <0x2910000 0x2000>;
+ sound-name-prefix = "ASRC1";
+ status = "disabled";
+ };
};
};
@@ -557,9 +656,27 @@
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra194-mc";
- reg = <0x02c00000 0x100000>,
- <0x02b80000 0x040000>,
- <0x01700000 0x100000>;
+ reg = <0x02c00000 0x10000>, /* MC-SID */
+ <0x02c10000 0x10000>, /* MC Broadcast*/
+ <0x02c20000 0x10000>, /* MC0 */
+ <0x02c30000 0x10000>, /* MC1 */
+ <0x02c40000 0x10000>, /* MC2 */
+ <0x02c50000 0x10000>, /* MC3 */
+ <0x02b80000 0x10000>, /* MC4 */
+ <0x02b90000 0x10000>, /* MC5 */
+ <0x02ba0000 0x10000>, /* MC6 */
+ <0x02bb0000 0x10000>, /* MC7 */
+ <0x01700000 0x10000>, /* MC8 */
+ <0x01710000 0x10000>, /* MC9 */
+ <0x01720000 0x10000>, /* MC10 */
+ <0x01730000 0x10000>, /* MC11 */
+ <0x01740000 0x10000>, /* MC12 */
+ <0x01750000 0x10000>, /* MC13 */
+ <0x01760000 0x10000>, /* MC14 */
+ <0x01770000 0x10000>; /* MC15 */
+ reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
+ "ch11", "ch12", "ch13", "ch14", "ch15";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <1>;
status = "disabled";
@@ -602,6 +719,22 @@
};
};
+ timer@3010000 {
+ compatible = "nvidia,tegra186-timer";
+ reg = <0x03010000 0x000e0000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
uarta: serial@3100000 {
compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
reg = <0x03100000 0x40>;
@@ -672,6 +805,10 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C1>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 21>, <&gpcdma 21>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -697,6 +834,10 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C3>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 23>, <&gpcdma 23>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -714,6 +855,10 @@
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
pinctrl-names = "default", "idle";
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 26>, <&gpcdma 26>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -731,6 +876,10 @@
pinctrl-0 = <&state_dpaux0_i2c>;
pinctrl-1 = <&state_dpaux0_off>;
pinctrl-names = "default", "idle";
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 30>, <&gpcdma 30>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -748,6 +897,10 @@
pinctrl-0 = <&state_dpaux2_i2c>;
pinctrl-1 = <&state_dpaux2_off>;
pinctrl-names = "default", "idle";
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 27>, <&gpcdma 27>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -765,6 +918,10 @@
pinctrl-0 = <&state_dpaux3_i2c>;
pinctrl-1 = <&state_dpaux3_off>;
pinctrl-names = "default", "idle";
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 31>, <&gpcdma 31>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -887,6 +1044,11 @@
clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
+ assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
+ <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
+ assigned-clock-parents =
+ <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
+ <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
resets = <&bpmp TEGRA194_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
@@ -921,6 +1083,11 @@
clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
+ assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
+ <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
+ assigned-clock-parents =
+ <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
+ <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
resets = <&bpmp TEGRA194_RESET_SDMMC3>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
@@ -995,9 +1162,8 @@
<&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&bpmp TEGRA194_RESET_HDA>,
- <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
- <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
- reset-names = "hda", "hda2hdmi", "hda2codec_2x";
+ <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
+ reset-names = "hda", "hda2hdmi";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
@@ -1378,6 +1544,26 @@
#phy-cells = <0>;
};
+ sce-noc@b600000 {
+ compatible = "nvidia,tegra194-sce-noc";
+ reg = <0xb600000 0x1000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,axi2apb = <&axi2apb>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
+ rce-noc@be00000 {
+ compatible = "nvidia,tegra194-rce-noc";
+ reg = <0xbe00000 0x1000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,axi2apb = <&axi2apb>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra194-hsp";
reg = <0x0c150000 0x90000>;
@@ -1403,6 +1589,10 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C2>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 22>, <&gpcdma 22>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -1416,6 +1606,10 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C8>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 0>, <&gpcdma 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -1512,6 +1706,25 @@
};
+ aon-noc@c600000 {
+ compatible = "nvidia,tegra194-aon-noc";
+ reg = <0xc600000 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
+ bpmp-noc@d600000 {
+ compatible = "nvidia,tegra194-bpmp-noc";
+ reg = <0xd600000 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,axi2apb = <&axi2apb>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
iommu@10000000 {
compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
reg = <0x10000000 0x800000>;
@@ -1585,7 +1798,7 @@
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
- status = "okay";
+ status = "disabled";
};
smmu: iommu@12000000 {
@@ -1687,6 +1900,16 @@
interconnect-names = "dma-mem";
iommus = <&smmu TEGRA194_SID_HOST1X>;
+ /* Context isolation domains */
+ iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
+ <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>,
+ <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>,
+ <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>,
+ <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>,
+ <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>,
+ <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>,
+ <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
+
nvdec@15140000 {
compatible = "nvidia,tegra194-nvdec";
reg = <0x15140000 0x00040000>;
@@ -2602,6 +2825,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40000000 0x50000>;
+ no-memory-wc;
cpu_bpmp_tx: sram@4e000 {
reg = <0x4e000 0x1000>;
@@ -2840,7 +3064,7 @@
};
pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "nvidia,carmel-pmu";
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
@@ -2877,11 +3101,6 @@
* for 8x and 11.025x sample rate streams.
*/
assigned-clock-rates = <258000000>;
-
- interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
- <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
- interconnect-names = "dma-mem", "write";
- iommus = <&smmu TEGRA194_SID_APE>;
};
tcu: serial {
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