diff options
Diffstat (limited to 'arch/arm64')
124 files changed, 5674 insertions, 289 deletions
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index f5f0c813dfec..a1c9f4ed7a88 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -184,6 +184,12 @@ config ARCH_R8A7796 help This enables support for the Renesas R-Car M3-W SoC. +config ARCH_R8A77995 + bool "Renesas R-Car D3 SoC Platform" + depends on ARCH_RENESAS + help + This enables support for the Renesas R-Car D3 SoC. + config ARCH_STRATIX10 bool "Altera's Stratix 10 SoCFPGA Family" help diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 108f12ce6d1d..19c3fbd75eda 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -1,4 +1,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi new file mode 100644 index 000000000000..ff8af52743ff --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi @@ -0,0 +1,150 @@ +/* + * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * AXP803 Integrated Power Management Chip + * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf + */ + +&axp803 { + interrupt-controller; + #interrupt-cells = <1>; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; + + reg_aldo1: aldo1 { + regulator-name = "aldo1"; + }; + + reg_aldo2: aldo2 { + regulator-name = "aldo2"; + }; + + reg_aldo3: aldo3 { + regulator-name = "aldo3"; + }; + + reg_dc1sw: dc1sw { + regulator-name = "dc1sw"; + }; + + reg_dcdc1: dcdc1 { + regulator-name = "dcdc1"; + }; + + reg_dcdc2: dcdc2 { + regulator-name = "dcdc2"; + }; + + reg_dcdc3: dcdc3 { + regulator-name = "dcdc3"; + }; + + reg_dcdc4: dcdc4 { + regulator-name = "dcdc4"; + }; + + reg_dcdc5: dcdc5 { + regulator-name = "dcdc5"; + }; + + reg_dcdc6: dcdc6 { + regulator-name = "dcdc6"; + }; + + reg_dldo1: dldo1 { + regulator-name = "dldo1"; + }; + + reg_dldo2: dldo2 { + regulator-name = "dldo2"; + }; + + reg_dldo3: dldo3 { + regulator-name = "dldo3"; + }; + + reg_dldo4: dldo4 { + regulator-name = "dldo4"; + }; + + reg_eldo1: eldo1 { + regulator-name = "eldo1"; + }; + + reg_eldo2: eldo2 { + regulator-name = "eldo2"; + }; + + reg_eldo3: eldo3 { + regulator-name = "eldo3"; + }; + + reg_fldo1: fldo1 { + regulator-name = "fldo1"; + }; + + reg_fldo2: fldo2 { + regulator-name = "fldo2"; + }; + + reg_ldo_io0: ldo-io0 { + regulator-name = "ldo-io0"; + status = "disabled"; + }; + + reg_ldo_io1: ldo-io1 { + regulator-name = "ldo-io1"; + status = "disabled"; + }; + + reg_rtc_ldo: rtc-ldo { + /* RTC_LDO is a fixed, always-on regulator */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "rtc-ldo"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 0d1f026d831a..8f07d1b10ca7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -59,19 +59,22 @@ stdout-path = "serial0:115200n8"; }; - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; }; +&ehci1 { + status = "okay"; +}; + &emac { pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dc1sw>; status = "okay"; }; @@ -95,7 +98,7 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; cd-inverted; disable-wp; @@ -106,22 +109,143 @@ &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo4>; + mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; non-removable; status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ + interrupt-names = "host-wake"; + }; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; status = "okay"; }; +&ohci1 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp803.dtsi" + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-phy"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi-dsi"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_dldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +/* + * The A64 chip cannot work without this regulator off, although + * it seems to be only driving the AR100 core. + * Maybe we don't still know well about CPUs domain. + */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -133,3 +257,7 @@ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; status = "okay"; }; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts new file mode 100644 index 000000000000..2beef9e6cb88 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2017 Jagan Teki <jteki@openedev.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "FriendlyARM NanoPi A64"; + compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +/* i2c1 connected with gpio headers like pine64, bananapi */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; +}; + +&i2c1_pins { + bias-pull-up; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp803.dtsi" + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi-dsi"; +}; + +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pg-wifi-io"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +/* + * The A64 chip cannot work without this regulator off, although + * it seems to be only driving the AR100 core. + * Maybe we don't still know well about CPUs domain. + */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts new file mode 100644 index 000000000000..338e786155b1 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2017 Jagan Teki <jteki@openedev.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Olimex A64-Olinuxino"; + compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp803.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-ddr3"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-avdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dvdd-csi"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +/* + * The A64 chip cannot work without this regulator off, although + * it seems to be only driving the AR100 core. + * Maybe we don't still know well about CPUs domain. + */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 08cda24ea194..2bcf0a3e36b4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -83,6 +83,7 @@ pinctrl-0 = <&rmii_pins>; phy-mode = "rmii"; phy-handle = <&ext_rmii_phy1>; + phy-supply = <®_dc1sw>; status = "okay"; }; @@ -123,6 +124,118 @@ status = "okay"; }; +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp803.dtsi" + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-phy"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +/* + * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can + * work at 1.35V with less power consumption. + * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead. + */ +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +/* + * The A64 chip cannot work without this regulator off, although + * it seems to be only driving the AR100 core. + * Maybe we don't still know well about CPUs domain. + */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + /* On Exp and Euler connectors */ &uart0 { pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 17eb1cc5bf6b..834a5d249bb2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -81,6 +81,7 @@ pinctrl-0 = <&rgmii_pins>; phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dc1sw>; status = "okay"; }; @@ -110,6 +111,28 @@ status = "okay"; }; +®_dc1sw { + regulator-name = "vcc-phy"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi index 475518b031dd..a5da18a6f286 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi @@ -63,3 +63,89 @@ bus-width = <4>; status = "okay"; }; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp803.dtsi" + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vdd-1v8-lpddr"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +/* + * The A64 chip cannot work without this regulator off, although + * it seems to be only driving the AR100 core. + * Maybe we don't still know well about CPUs domain. + */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 9d00622ce845..50f17bab0c07 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -452,7 +452,7 @@ emac: ethernet@1c30000 { compatible = "allwinner,sun50i-a64-emac"; syscon = <&syscon>; - reg = <0x01c30000 0x100>; + reg = <0x01c30000 0x10000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; resets = <&ccu RST_BUS_EMAC>; @@ -487,6 +487,15 @@ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun50i-a64-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c00 0x400>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + r_ccu: clock@1f01400 { compatible = "allwinner,sun50i-a64-r-ccu"; reg = <0x01f01400 0x100>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 35b8c88c3220..8814708947fc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -225,7 +225,7 @@ }; uart_A: serial@84c0 { - compatible = "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; reg = <0x0 0x84c0 0x0 0x14>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; clocks = <&xtal>; @@ -233,7 +233,7 @@ }; uart_B: serial@84dc { - compatible = "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; reg = <0x0 0x84dc 0x0 0x14>; interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; clocks = <&xtal>; @@ -279,7 +279,7 @@ }; uart_C: serial@8700 { - compatible = "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; reg = <0x0 0x8700 0x0 0x14>; interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; clocks = <&xtal>; @@ -374,19 +374,23 @@ #reset-cells = <1>; }; + sec_AO: ao-secure@140 { + compatible = "amlogic,meson-gx-ao-secure", "syscon"; + reg = <0x0 0x140 0x0 0x140>; + amlogic,has-chip-id; + }; + uart_AO: serial@4c0 { - compatible = "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; reg = <0x0 0x004c0 0x0 0x14>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; uart_AO_B: serial@4e0 { - compatible = "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; reg = <0x0 0x004e0 0x0 0x14>; interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; status = "disabled"; }; @@ -400,7 +404,7 @@ }; pwm_AO_ab: pwm@550 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; reg = <0x0 0x00550 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; @@ -437,9 +441,9 @@ mailbox: mailbox@404 { compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; reg = <0 0x404 0 0x4c>; - interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, - <0 209 IRQ_TYPE_EDGE_RISING>, - <0 210 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; #mbox-cells = <1>; }; }; @@ -448,7 +452,7 @@ compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; - interrupts = <0 8 1>; + interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; interrupt-names = "macirq"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index fa462831ccaf..9697a7a79464 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -175,6 +175,64 @@ pinctrl-names = "default"; }; +&pinctrl_aobus { + gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In", + "VCCK En", "CON1 Header Pin31", + "I2S Header Pin6", "IR In", "I2S Header Pin7", + "I2S Header Pin3", "I2S Header Pin4", + "I2S Header Pin5", "HDMI CEC", "SYS LED"; +}; + +&pinctrl_periphs { + gpio-line-names = /* Bank GPIOZ */ + "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", + "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", + "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", + "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", + "Eth PHY nRESET", "Eth PHY Intc", + /* Bank GPIOH */ + "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", + "CON1 Header Pin33", + /* Bank BOOT */ + "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", + "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", + "eMMC Reset", "eMMC CMD", + "", "", "", "", "eMMC DS", + "", "", + /* Bank CARD */ + "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", + "SDCard D3", "SDCard D2", "SDCard Det", + /* Bank GPIODV */ + "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", + "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", + "VDDEE Regulator", "VCCK Regulator", + /* Bank GPIOY */ + "CON1 Header Pin7", "CON1 Header Pin11", + "CON1 Header Pin13", "CON1 Header Pin15", + "CON1 Header Pin18", "CON1 Header Pin19", + "CON1 Header Pin22", "CON1 Header Pin21", + "CON1 Header Pin24", "CON1 Header Pin23", + "CON1 Header Pin26", "CON1 Header Pin29", + "CON1 Header Pin32", "CON1 Header Pin8", + "CON1 Header Pin10", "CON1 Header Pin16", + "CON1 Header Pin12", + /* Bank GPIOX */ + "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", + "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", + "WIFI Power Enable", "WIFI WAKE HOST", + "Bluetooth PCM DOUT", "Bluetooth PCM DIN", + "Bluetooth PCM SYNC", "Bluetooth PCM CLK", + "Bluetooth UART TX", "Bluetooth UART RX", + "Bluetooth UART CTS", "Bluetooth UART RTS", + "", "", "", "WIFI 32K", "Bluetooth Enable", + "Bluetooth WAKE HOST", + /* Bank GPIOCLK */ + "", "CON1 Header Pin35", "", "", + /* GPIO_TEST_N */ + ""; +}; + &pwm_ef { status = "okay"; pinctrl-0 = <&pwm_e_pins>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index d904deb1018c..58b32f272a0e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -84,6 +84,9 @@ /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ states = <1800000 0 3300000 1>; + + regulator-settling-time-up-us = <10000>; + regulator-settling-time-down-us = <150000>; }; vddio_boot: regulator-vddio_boot { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 17d3efdf1469..ea53cc248ef4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -682,6 +682,31 @@ clocks = <&clkc CLKID_SPI>; }; +&uart_A { + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_AO { + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_AO_B { + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_B { + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "core", "baud"; +}; + +&uart_C { + clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; + clock-names = "xtal", "core", "baud"; +}; + &vpu { compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 72c5a9f64ca8..9b66220dea81 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -105,12 +105,68 @@ linux,rc-map-name = "rc-geekbox"; }; +&pinctrl_aobus { + gpio-line-names = "UART TX", + "UART RX", + "Power Key In", + "J9 Header Pin35", + "J9 Header Pin16", + "J9 Header Pin15", + "J9 Header Pin33", + "IR In", + "HDMI CEC", + "SYS LED"; +}; + +&pinctrl_periphs { + gpio-line-names = /* Bank GPIOZ */ + "", "", "", "", "", "", "", + "", "", "", "", "", "", "", + "Power OFF", + "VCCK Enable", + /* Bank GPIOH */ + "HDMI HPD", "HDMI SDA", "HDMI SCL", + "HDMI_5V_EN", "SPDIF", + "J9 Header Pin37", + "J9 Header Pin30", + "J9 Header Pin29", + "J9 Header Pin32", + "J9 Header Pin31", + /* Bank BOOT */ + "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", + "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", + "eMMC Clk", "eMMC Reset", "eMMC CMD", + "", "BOOT_MODE", "", "", "eMMC Data Strobe", + /* Bank CARD */ + "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", + "SDCard D3", "SDCard D2", "SDCard Det", + /* Bank GPIODV */ + "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", + "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", + "VCCK Regulator", "VDDEE Regulator", + /* Bank GPIOX */ + "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", + "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", + "WIFI Power Enable", "WIFI WAKE HOST", + "Bluetooth PCM DOUT", "Bluetooth PCM DIN", + "Bluetooth PCM SYNC", "Bluetooth PCM CLK", + "Bluetooth UART TX", "Bluetooth UART RX", + "Bluetooth UART CTS", "Bluetooth UART RTS", + "WIFI 32K", "Bluetooth Enable", + "Bluetooth WAKE HOST", + /* Bank GPIOCLK */ + "", "J9 Header Pin39", + /* GPIO_TEST_N */ + ""; +}; + &pwm_AO_ab { status = "okay"; pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; + clocks = <&xtal> , <&xtal>; + clock-names = "clkin0", "clkin1" ; }; &pwm_ef { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index 890821d6e52b..266fbcf3e47f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -10,12 +10,20 @@ #include <dt-bindings/input/input.h> -#include "meson-gxl-s905x-p212.dtsi" +#include "meson-gxl-s905x.dtsi" / { compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl"; model = "Libre Technology CC"; + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + cvbs-connector { compatible = "composite-video-connector"; @@ -26,6 +34,11 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + hdmi-connector { compatible = "hdmi-connector"; type = "a"; @@ -53,6 +66,39 @@ linux,default-trigger = "heartbeat"; }; }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_card: regulator-vcc-card { + compatible = "regulator-gpio"; + + regulator-name = "VCC_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0>, + <1800000 1>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &cvbs_vdac_port { @@ -61,6 +107,16 @@ }; }; +ðmac { + status = "okay"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; @@ -73,20 +129,43 @@ }; }; -/* - * The following devices exists but are exposed on the general - * purpose GPIO header. End user may well decide to use those pins - * for another purpose - */ +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; -&sd_emmc_a { - status = "disabled"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_card>; }; -&uart_A { - status = "disabled"; +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <50000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; }; -&wifi32k { - status = "disabled"; +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 8d4f3160a0ee..9e674441fd90 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -623,6 +623,31 @@ clocks = <&clkc CLKID_SPI>; }; +&uart_A { + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "core", "baud"; +}; + +&uart_AO { + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_AO_B { + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; + +&uart_B { + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "core", "baud"; +}; + +&uart_C { + clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; + clock-names = "xtal", "core", "baud"; +}; + &vpu { compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; }; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 72720e9132a1..c9ffffb96e43 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -626,6 +626,7 @@ 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4 @@ -651,6 +652,7 @@ 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4 diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 63be8e51eaa8..c09a36fed917 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -626,6 +626,7 @@ 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 @@ -651,6 +652,7 @@ 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 @@ -676,6 +678,7 @@ 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 @@ -701,6 +704,7 @@ 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 @@ -726,6 +730,7 @@ 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 7cfa8e414e7f..8ecdd4331980 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -226,7 +226,7 @@ clock-names = "uartclk", "apb_pclk"; }; - virtio_block@0130000 { + virtio-block@0130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index e8b7413ec890..fbafe62d6b22 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -201,7 +201,7 @@ }; }; - cpu_debug0: cpu_debug@22010000 { + cpu_debug0: cpu-debug@22010000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x22010000 0x0 0x1000>; @@ -260,7 +260,7 @@ }; }; - cpu_debug1: cpu_debug@22110000 { + cpu_debug1: cpu-debug@22110000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x22110000 0x0 0x1000>; @@ -283,7 +283,7 @@ }; }; - cpu_debug2: cpu_debug@23010000 { + cpu_debug2: cpu-debug@23010000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23010000 0x0 0x1000>; @@ -356,7 +356,7 @@ }; }; - cpu_debug3: cpu_debug@23110000 { + cpu_debug3: cpu-debug@23110000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23110000 0x0 0x1000>; @@ -379,7 +379,7 @@ }; }; - cpu_debug4: cpu_debug@23210000 { + cpu_debug4: cpu-debug@23210000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23210000 0x0 0x1000>; @@ -402,7 +402,7 @@ }; }; - cpu_debug5: cpu_debug@23310000 { + cpu_debug5: cpu-debug@23310000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23310000 0x0 0x1000>; @@ -426,7 +426,7 @@ }; replicator@20120000 { - compatible = "qcom,coresight-replicator1x", "arm,primecell"; + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0 0x20120000 0 0x1000>; clocks = <&soc_smc50mhz>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index 161ac98418a3..528875c75598 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -219,7 +219,7 @@ }; }; - virtio_block@0130000 { + virtio-block@0130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index f11bdd6689ea..3eaef3895d66 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,7 +1,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb -dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb -dts-dirs := stingray +dts-dirs += northstar2 +dts-dirs += stingray always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb diff --git a/arch/arm64/boot/dts/broadcom/northstar2/Makefile b/arch/arm64/boot/dts/broadcom/northstar2/Makefile new file mode 100644 index 000000000000..e01a1485b813 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/northstar2/Makefile @@ -0,0 +1,6 @@ +dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb +dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-xmc.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/broadcom/ns2-clock.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi index 99009fdf10a4..99009fdf10a4 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-clock.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index ec19fbf928a1..ec19fbf928a1 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts diff --git a/arch/arm64/boot/dts/broadcom/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index ab4ae1a32fab..ab4ae1a32fab 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 35c8457e3d1f..35c8457e3d1f 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi index 5dca7d10253b..8862ec907fd8 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi @@ -72,6 +72,78 @@ <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */ }; +&sata0 { + status = "okay"; +}; + +&sata_phy0{ + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata_phy1{ + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata_phy2{ + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; + +&sata_phy3{ + status = "okay"; +}; + +&sata4 { + status = "okay"; +}; + +&sata_phy4{ + status = "okay"; +}; + +&sata5 { + status = "okay"; +}; + +&sata_phy5{ + status = "okay"; +}; + +&sata6 { + status = "okay"; +}; + +&sata_phy6{ + status = "okay"; +}; + +&sata7 { + status = "okay"; +}; + +&sata_phy7{ + status = "okay"; +}; + +&mdio_mux_iproc { + mdio@10 { + gphy0: eth-phy@10 { + reg = <0x10>; + }; + }; +}; + &uart1 { status = "okay"; }; @@ -102,6 +174,12 @@ }; }; +&enet { + phy-mode = "rgmii-id"; + phy-handle = <&gphy0>; + status = "okay"; +}; + &nand { status = "ok"; nandcs@0 { diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts index 5671669ba348..eb6f08cdbd79 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts @@ -39,6 +39,10 @@ model = "Stingray Combo SVK (BCM958742K)"; }; +&gphy0 { + enet-phy-lane-swap; +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts index 6ebe399fda6a..5084b037320f 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts @@ -38,3 +38,7 @@ compatible = "brcm,bcm958742t", "brcm,stingray"; model = "Stingray SST100 (BCM958742T)"; }; + +&gphy0 { + enet-phy-lane-swap; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi new file mode 100644 index 000000000000..8bf1dc6b46ca --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi @@ -0,0 +1,118 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016-2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + fs4: fs4 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x67000000 0x00800000>; + + crypto_mbox: crypto_mbox@00000000 { + compatible = "brcm,iproc-flexrm-mbox"; + reg = <0x00000000 0x200000>; + msi-parent = <&gic_its 0x4100>; + #mbox-cells = <3>; + dma-coherent; + }; + + raid_mbox: raid_mbox@00400000 { + compatible = "brcm,iproc-flexrm-mbox"; + reg = <0x00400000 0x200000>; + dma-coherent; + msi-parent = <&gic_its 0x4300>; + #mbox-cells = <3>; + }; + + raid0: raid@0 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 0 0x1 0xff00>, + <&raid_mbox 1 0x1 0xff00>, + <&raid_mbox 2 0x1 0xff00>, + <&raid_mbox 3 0x1 0xff00>; + }; + + raid1: raid@1 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 4 0x1 0xff00>, + <&raid_mbox 5 0x1 0xff00>, + <&raid_mbox 6 0x1 0xff00>, + <&raid_mbox 7 0x1 0xff00>; + }; + + raid2: raid@2 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 8 0x1 0xff00>, + <&raid_mbox 9 0x1 0xff00>, + <&raid_mbox 10 0x1 0xff00>, + <&raid_mbox 11 0x1 0xff00>; + }; + + raid3: raid@3 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 12 0x1 0xff00>, + <&raid_mbox 13 0x1 0xff00>, + <&raid_mbox 14 0x1 0xff00>, + <&raid_mbox 15 0x1 0xff00>; + }; + + raid4: raid@4 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 16 0x1 0xff00>, + <&raid_mbox 17 0x1 0xff00>, + <&raid_mbox 18 0x1 0xff00>, + <&raid_mbox 19 0x1 0xff00>; + }; + + raid5: raid@5 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 20 0x1 0xff00>, + <&raid_mbox 21 0x1 0xff00>, + <&raid_mbox 22 0x1 0xff00>, + <&raid_mbox 23 0x1 0xff00>; + }; + + raid6: raid@6 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 24 0x1 0xff00>, + <&raid_mbox 25 0x1 0xff00>, + <&raid_mbox 26 0x1 0xff00>, + <&raid_mbox 27 0x1 0xff00>; + }; + + raid7: raid@7 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 28 0x1 0xff00>, + <&raid_mbox 29 0x1 0xff00>, + <&raid_mbox 30 0x1 0xff00>, + <&raid_mbox 31 0x1 0xff00>; + }; + }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi new file mode 100644 index 000000000000..a774709388df --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi @@ -0,0 +1,278 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016-2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + sata { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x67d00000 0x00800000>; + + sata0: ahci@00210000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x00210000 0x1000>; + reg-names = "ahci"; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata0_port0: sata-port@0 { + reg = <0>; + phys = <&sata0_phy0>; + phy-names = "sata-phy"; + }; + }; + + sata_phy0: sata_phy@00212100 { + compatible = "brcm,iproc-sr-sata-phy"; + reg = <0x00212100 0x1000>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata0_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + sata1: ahci@00310000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x00310000 0x1000>; + reg-names = "ahci"; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata1_port0: sata-port@0 { + reg = <0>; + phys = <&sata1_phy0>; + phy-names = "sata-phy"; + }; + }; + + sata_phy1: sata_phy@00312100 { + compatible = "brcm,iproc-sr-sata-phy"; + reg = <0x00312100 0x1000>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata1_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + sata2: ahci@00120000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x00120000 0x1000>; + reg-names = "ahci"; + interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata2_port0: sata-port@0 { + reg = <0>; + phys = <&sata2_phy0>; + phy-names = "sata-phy"; + }; + }; + + sata_phy2: sata_phy@00122100 { + compatible = "brcm,iproc-sr-sata-phy"; + reg = <0x00122100 0x1000>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata2_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + sata3: ahci@00130000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x00130000 0x1000>; + reg-names = "ahci"; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata3_port0: sata-port@0 { + reg = <0>; + phys = <&sata3_phy0>; + phy-names = "sata-phy"; + }; + }; + + sata_phy3: sata_phy@00132100 { + compatible = "brcm,iproc-sr-sata-phy"; + reg = <0x00132100 0x1000>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata3_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + sata4: ahci@00330000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x00330000 0x1000>; + reg-names = "ahci"; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata4_port0: sata-port@0 { + reg = <0>; + phys = <&sata4_phy0>; + phy-names = "sata-phy"; + }; + }; + + sata_phy4: sata_phy@00332100 { + compatible = "brcm,iproc-sr-sata-phy"; + reg = <0x00332100 0x1000>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata4_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + sata5: ahci@00400000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x00400000 0x1000>; + reg-names = "ahci"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata5_port0: sata-port@0 { + reg = <0>; + phys = <&sata5_phy0>; + phy-names = "sata-phy"; + }; + }; + + sata_phy5: sata_phy@00402100 { + compatible = "brcm,iproc-sr-sata-phy"; + reg = <0x00402100 0x1000>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata5_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + sata6: ahci@00410000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x00410000 0x1000>; + reg-names = "ahci"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata6_port0: sata-port@0 { + reg = <0>; + phys = <&sata6_phy0>; + phy-names = "sata-phy"; + }; + }; + + sata_phy6: sata_phy@00412100 { + compatible = "brcm,iproc-sr-sata-phy"; + reg = <0x00412100 0x1000>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata6_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + sata7: ahci@00420000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x00420000 0x1000>; + reg-names = "ahci"; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata7_port0: sata-port@0 { + reg = <0>; + phys = <&sata7_phy0>; + phy-names = "sata-phy"; + }; + }; + + sata_phy7: sata_phy@00422100 { + compatible = "brcm,iproc-sr-sata-phy"; + reg = <0x00422100 0x1000>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata7_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 49933cf16c92..e6f75c633623 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -152,6 +152,12 @@ #size-cells = <1>; ranges = <0x0 0x0 0x61000000 0x05000000>; + ccn: ccn@00000000 { + compatible = "arm,ccn-502"; + reg = <0x00000000 0x900000>; + interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; + }; + gic: interrupt-controller@02c00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -261,6 +267,9 @@ }; }; + #include "stingray-fs4.dtsi" + #include "stingray-sata.dtsi" + hsls { compatible = "simple-bus"; #address-cells = <1>; @@ -269,6 +278,37 @@ #include "stingray-pinctrl.dtsi" + mdio_mux_iproc: mdio-mux@0002023c { + compatible = "brcm,mdio-mux-iproc"; + reg = <0x0002023c 0x14>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { /* PCIe serdes */ + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@2 { /* SATA */ + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* USB */ + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@10 { /* RGMII */ + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + pwm: pwm@00010000 { compatible = "brcm,iproc-pwm"; reg = <0x00010000 0x1000>; @@ -277,6 +317,93 @@ status = "disabled"; }; + timer0: timer@00030000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00030000 0x1000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer1: timer@00040000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00040000 0x1000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer2: timer@00050000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00050000 0x1000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer3: timer@00060000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00060000 0x1000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer4: timer@00070000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00070000 0x1000>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer5: timer@00080000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00080000 0x1000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer6: timer@00090000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00090000 0x1000>; + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer7: timer@000a0000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x000a0000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + i2c0: i2c@000b0000 { compatible = "brcm,iproc-i2c"; reg = <0x000b0000 0x100>; @@ -424,6 +551,15 @@ iommus = <&smmu 0x6000 0x0000>; }; + enet: ethernet@00340000{ + compatible = "brcm,amac"; + reg = <0x00340000 0x1000>; + reg-names = "amac_base"; + dma-coherent; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; + status= "disabled"; + }; + nand: nand@00360000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x00360000 0x600>, diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index e2b0da2c0bc7..94cde8773c6a 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -310,20 +310,6 @@ samsung,pll-clock-frequency = <24000000>; pinctrl-names = "default"; pinctrl-0 = <&te_irq>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi_out: endpoint { - samsung,burst-clock-frequency = <512000000>; - samsung,esc-clock-frequency = <16000000>; - }; - }; - }; }; &hdmi { @@ -846,7 +832,6 @@ &mshc_0 { status = "okay"; - num-slots = <1>; mmc-hs200-1_8v; mmc-hs400-1_8v; cap-mmc-highspeed; @@ -868,7 +853,6 @@ &mshc_2 { status = "okay"; - num-slots = <1>; cap-sd-highspeed; disable-wp; cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>; @@ -1216,8 +1200,9 @@ status = "okay"; }; -&usbdrd_dwc3_0 { +&usbdrd_dwc3 { dr_mode = "otg"; + extcon = <&muic>; }; &usbdrd30_phy { diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 727f36abf3d4..7fe994b750da 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1367,7 +1367,7 @@ ranges; status = "disabled"; - dwc3@15400000 { + usbdrd_dwc3: dwc3@15400000 { compatible = "snps,dwc3"; reg = <0x15400000 0x10000>; interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; @@ -1414,7 +1414,7 @@ ranges; status = "disabled"; - usbdrd_dwc3_0: dwc3@15a00000 { + usbhost_dwc3: dwc3@15a00000 { compatible = "snps,dwc3"; reg = <0x15a00000 0x10000>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index e5892bb0ae6e..4a8b1fb51243 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -359,7 +359,6 @@ &mmc_0 { status = "okay"; - num-slots = <1>; cap-mmc-highspeed; mmc-hs200-1_8v; non-removable; @@ -375,7 +374,6 @@ &mmc_2 { status = "okay"; - num-slots = <1>; cap-sd-highspeed; card-detect-delay = <200>; clock-frequency = <400000000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index b1554cbd2c54..df83915d6ea6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -444,6 +444,15 @@ <&clockgen 4 3>; }; + usb0: usb3@2f00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 0x4>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + }; + sata: sata@3200000 { compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; reg = <0x0 0x3200000 0x0 0x10000>, @@ -454,5 +463,13 @@ dma-coherent; status = "disabled"; }; + + usb1: usb2@8600000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + reg = <0x0 0x8600000 0x0 0x1000>; + interrupts = <0 139 0x4>; + dr_mode = "host"; + phy_type = "ulpi"; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 213abb72de93..0f6fcda36b9e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -49,7 +49,7 @@ #include "fsl-ls1088a.dtsi" / { - model = "L1088A RDB Board"; + model = "LS1088A RDB Board"; compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index c144d06a6e33..33797b373674 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -52,6 +52,10 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + crypto = &crypto; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -62,6 +66,7 @@ compatible = "arm,cortex-a53"; reg = <0x0>; clocks = <&clockgen 1 0>; + cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -70,6 +75,7 @@ compatible = "arm,cortex-a53"; reg = <0x1>; clocks = <&clockgen 1 0>; + cpu-idle-states = <&CPU_PH20>; }; cpu2: cpu@2 { @@ -77,6 +83,7 @@ compatible = "arm,cortex-a53"; reg = <0x2>; clocks = <&clockgen 1 0>; + cpu-idle-states = <&CPU_PH20>; }; cpu3: cpu@3 { @@ -84,6 +91,7 @@ compatible = "arm,cortex-a53"; reg = <0x3>; clocks = <&clockgen 1 0>; + cpu-idle-states = <&CPU_PH20>; }; cpu4: cpu@100 { @@ -91,6 +99,7 @@ compatible = "arm,cortex-a53"; reg = <0x100>; clocks = <&clockgen 1 1>; + cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; @@ -99,6 +108,7 @@ compatible = "arm,cortex-a53"; reg = <0x101>; clocks = <&clockgen 1 1>; + cpu-idle-states = <&CPU_PH20>; }; cpu6: cpu@102 { @@ -106,6 +116,7 @@ compatible = "arm,cortex-a53"; reg = <0x102>; clocks = <&clockgen 1 1>; + cpu-idle-states = <&CPU_PH20>; }; cpu7: cpu@103 { @@ -113,6 +124,16 @@ compatible = "arm,cortex-a53"; reg = <0x103>; clocks = <&clockgen 1 1>; + cpu-idle-states = <&CPU_PH20>; + }; + + CPU_PH20: cpu-ph20 { + compatible = "arm,idle-state"; + idle-state-name = "PH20"; + arm,psci-suspend-param = <0x00010000>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <3000>; }; }; @@ -136,6 +157,11 @@ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -369,6 +395,45 @@ dma-coherent; status = "disabled"; }; + + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts index ed209cd57283..3c99608b9b45 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts @@ -55,11 +55,6 @@ model = "Freescale Layerscape 2080a QDS Board"; compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; - aliases { - serial0 = &serial0; - serial1 = &serial1; - }; - chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts index 67ec3f9c81a1..a4e7de9f70d8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts @@ -55,11 +55,6 @@ model = "Freescale Layerscape 2080a RDB Board"; compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; - aliases { - serial0 = &serial0; - serial1 = &serial1; - }; - chosen { stdout-path = "serial1:115200n8"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts index 3ee718f0aaf8..fbbb73e571c0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts @@ -52,11 +52,6 @@ model = "Freescale Layerscape 2080a software Simulator model"; compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; - aliases { - serial0 = &serial0; - serial1 = &serial1; - }; - ethernet@2210000 { compatible = "smsc,lan91c111"; reg = <0x0 0x2210000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index d789c6814e6a..8d739301e7b8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -53,6 +53,7 @@ compatible = "arm,cortex-a57"; reg = <0x0>; clocks = <&clockgen 1 0>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; #cooling-cells = <2>; }; @@ -62,6 +63,7 @@ compatible = "arm,cortex-a57"; reg = <0x1>; clocks = <&clockgen 1 0>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; }; @@ -70,6 +72,7 @@ compatible = "arm,cortex-a57"; reg = <0x100>; clocks = <&clockgen 1 1>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; #cooling-cells = <2>; }; @@ -79,6 +82,7 @@ compatible = "arm,cortex-a57"; reg = <0x101>; clocks = <&clockgen 1 1>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; }; @@ -87,6 +91,7 @@ compatible = "arm,cortex-a57"; reg = <0x200>; clocks = <&clockgen 1 2>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; #cooling-cells = <2>; }; @@ -96,6 +101,7 @@ compatible = "arm,cortex-a57"; reg = <0x201>; clocks = <&clockgen 1 2>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; }; @@ -105,6 +111,7 @@ reg = <0x300>; clocks = <&clockgen 1 3>; next-level-cache = <&cluster3_l2>; + cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; }; @@ -113,6 +120,7 @@ compatible = "arm,cortex-a57"; reg = <0x301>; clocks = <&clockgen 1 3>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; }; @@ -131,6 +139,15 @@ cluster3_l2: l2-cache3 { compatible = "cache"; }; + + CPU_PW20: cpu-pw20 { + compatible = "arm,idle-state"; + idle-state-name = "PW20"; + arm,psci-suspend-param = <0x00010000>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; }; &pcie1 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts index 4a1df5ce3229..eaee5b1c3a44 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts @@ -54,11 +54,6 @@ model = "Freescale Layerscape 2088A QDS Board"; compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; - aliases { - serial0 = &serial0; - serial1 = &serial1; - }; - chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index a76d4b4debd1..c411442cac62 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -54,11 +54,6 @@ model = "Freescale Layerscape 2088A RDB Board"; compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; - aliases { - serial0 = &serial0; - serial1 = &serial1; - }; - chosen { stdout-path = "serial1:115200n8"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 5c695c658056..6aa319dae396 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -53,6 +53,7 @@ compatible = "arm,cortex-a72"; reg = <0x0>; clocks = <&clockgen 1 0>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; #cooling-cells = <2>; }; @@ -62,6 +63,7 @@ compatible = "arm,cortex-a72"; reg = <0x1>; clocks = <&clockgen 1 0>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; }; @@ -70,6 +72,7 @@ compatible = "arm,cortex-a72"; reg = <0x100>; clocks = <&clockgen 1 1>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; #cooling-cells = <2>; }; @@ -79,6 +82,7 @@ compatible = "arm,cortex-a72"; reg = <0x101>; clocks = <&clockgen 1 1>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; }; @@ -88,6 +92,7 @@ reg = <0x200>; clocks = <&clockgen 1 2>; next-level-cache = <&cluster2_l2>; + cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; }; @@ -96,6 +101,7 @@ compatible = "arm,cortex-a72"; reg = <0x201>; clocks = <&clockgen 1 2>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; }; @@ -104,6 +110,7 @@ compatible = "arm,cortex-a72"; reg = <0x300>; clocks = <&clockgen 1 3>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; #cooling-cells = <2>; }; @@ -113,6 +120,7 @@ compatible = "arm,cortex-a72"; reg = <0x301>; clocks = <&clockgen 1 3>; + cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; }; @@ -131,6 +139,15 @@ cluster3_l2: l2-cache3 { compatible = "cache"; }; + + CPU_PW20: cpu-pw20 { + compatible = "arm,idle-state"; + idle-state-name = "PW20"; + arm,psci-suspend-param = <0x00010000>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; }; &pcie1 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 94cdd3045037..4fb9a0966a84 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -46,6 +46,7 @@ */ #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "fsl,ls2080a"; @@ -53,6 +54,12 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + crypto = &crypto; + serial0 = &serial0; + serial1 = &serial1; + }; + cpu: cpus { #address-cells = <1>; #size-cells = <0>; @@ -118,6 +125,11 @@ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -301,6 +313,45 @@ clock-names = "apb_pclk", "wdog_clk"; }; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 6609b0fe7a8b..fd4705c451e2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -39,6 +39,34 @@ reg = <0x0 0x0 0x0 0x0>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@32000000 { + compatible = "ramoops"; + reg = <0x0 0x32000000 0x0 0x00100000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; + }; + }; + + reboot-mode-syscon@32100000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x32100000 0x0 0x00001000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x0>; + + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; + }; + keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -159,6 +187,13 @@ startup-delay-us = <70000>; enable-active-high; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; &i2c0 { @@ -195,7 +230,7 @@ bluetooth { compatible = "ti,wl1837-st"; enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>; - max-speed = <921600>; + max-speed = <3000000>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index c6a1961e8d55..b7a90d632959 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -58,6 +58,8 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; cpu1: cpu@1 { @@ -65,6 +67,8 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; cpu2: cpu@2 { @@ -72,6 +76,8 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; cpu3: cpu@3 { @@ -79,6 +85,8 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; cpu4: cpu@100 { @@ -86,6 +94,12 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + next-level-cache = <&A73_L2>; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; }; cpu5: cpu@101 { @@ -93,6 +107,12 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + next-level-cache = <&A73_L2>; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; }; cpu6: cpu@102 { @@ -100,6 +120,12 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + next-level-cache = <&A73_L2>; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; }; cpu7: cpu@103 { @@ -107,6 +133,59 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + next-level-cache = <&A73_L2>; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; + }; + + idle-states { + entry-method = "psci"; + + CPU_NAP: cpu-nap { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <7>; + exit-latency-us = <2>; + min-residency-us = <15>; + }; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <70>; + min-residency-us = <3000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <5000>; + min-residency-us = <20000>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <1000>; + exit-latency-us = <5000>; + min-residency-us = <20000>; + }; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + + A73_L2: l2-cache1 { + compatible = "cache"; }; }; @@ -123,6 +202,26 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>, + <&cpu4>, + <&cpu5>, + <&cpu6>, + <&cpu7>; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; @@ -337,6 +436,19 @@ status = "disabled"; }; + dma0: dma@fdf30000 { + compatible = "hisilicon,k3-dma-1.0"; + reg = <0x0 0xfdf30000 0x0 0x1000>; + #dma-cells = <1>; + dma-channels = <16>; + dma-requests = <32>; + dma-min-chan = <1>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; + dma-no-cci; + dma-type = "hi3660_dma"; + }; + rtc0: rtc@fff04000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x0 0Xfff04000 0x0 0x1000>; @@ -810,6 +922,7 @@ clock-names = "ciu", "biu"; clock-frequency = <3200000>; resets = <&crg_rst 0x94 18>; + reset-names = "reset"; cd-gpios = <&gpio25 3 0>; hisilicon,peripheral-syscon = <&sctrl>; pinctrl-names = "default"; @@ -839,6 +952,7 @@ <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; clock-names = "ciu", "biu"; resets = <&crg_rst 0x94 20>; + reset-names = "reset"; card-detect-delay = <200>; supports-highspeed; keep-power-in-suspend; @@ -848,5 +962,21 @@ &sdio_cfg_func>; status = "disabled"; }; + + watchdog0: watchdog@e8a06000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xe8a06000 0x0 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_OSC32K>; + clock-names = "apb_pclk"; + }; + + watchdog1: watchdog@e8a07000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xe8a07000 0x0 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_OSC32K>; + clock-names = "apb_pclk"; + }; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index eacbe0db5bc2..02a3aa4b2165 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -262,6 +262,12 @@ #clock-cells = <1>; }; + acpu_sctrl: acpu_sctrl@f6504000 { + compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; + reg = <0x0 0xf6504000 0x0 0x1000>; + #clock-cells = <1>; + }; + medianoc_ade: medianoc_ade@f4520000 { compatible = "syscon"; reg = <0x0 0xf4520000 0x0 0x4000>; @@ -755,7 +761,8 @@ dr_mode = "otg"; g-rx-fifo-size = <512>; g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 128 128 128 128>; + g-tx-fifo-size = <128 128 128 128 128 128 128 128 + 16 16 16 16 16 16 16>; interrupts = <0 77 0x4>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts index f5d7f0889b41..fe7c16c36025 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts @@ -84,3 +84,7 @@ &sas1 { status = "ok"; }; + +&p0_pcie2_a { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 283d7b532e16..2c01a21c3665 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1534,5 +1534,27 @@ <637 1>,<638 1>,<639 1>; status = "disabled"; }; + + p0_pcie2_a: pcie@a00a0000 { + compatible = "hisilicon,hip07-pcie-ecam"; + reg = <0 0xaf800000 0 0x800000>, + <0 0xa00a0000 0 0x10000>; + bus-range = <0xf8 0xff>; + msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; + msi-map-mask = <0xffff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000 + 0x01000000 0 0 0 0xaf7f0000 0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 + 0x0 0 0 2 &mbigen_pcie2_a 671 4 + 0x0 0 0 3 &mbigen_pcie2_a 671 4 + 0x0 0 0 4 &mbigen_pcie2_a 671 4>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index e3a136ed77b0..2ce52ba74f73 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -45,6 +45,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "armada-372x.dtsi" / { @@ -59,6 +60,20 @@ device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x20000000>; }; + + vcc_sd_reg1: regulator { + compatible = "regulator-gpio"; + regulator-name = "vcc_sd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1 + 3300000 0x0>; + enable-active-high; + }; }; /* J9 */ @@ -71,6 +86,16 @@ status = "okay"; }; +/* J1 */ +&sdhci1 { + wp-inverted; + bus-width = <4>; + cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; + marvell,pad-type = "sd"; + vqmmc-supply = <&vcc_sd_reg1>; + status = "okay"; +}; + /* Exported on the micro USB connector J5 through an FTDI */ &uart0 { status = "okay"; @@ -81,6 +106,11 @@ status = "okay"; }; +/* J8 */ +&usb2 { + status = "okay"; +}; + &mdio { switch0: switch0@1 { compatible = "marvell,mv88e6085"; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index dbcc3d4e2ed5..8c0cf7efac65 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -81,6 +81,11 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -219,7 +224,7 @@ reg = <0x18800 0x100>, <0x18C00 0x20>; gpiosb: gpio { #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-ranges = <&pinctrl_sb 0 0 30>; gpio-controller; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, @@ -322,7 +327,11 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x1d00000 0x10000>, /* GICD */ - <0x1d40000 0x40000>; /* GICR */ + <0x1d40000 0x40000>, /* GICR */ + <0x1d80000 0x2000>, /* GICC */ + <0x1d90000 0x2000>, /* GICH */ + <0x1da0000 0x20000>; /* GICV */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index 92c761c380d3..9c3bdf87e543 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -44,6 +44,7 @@ * Device Tree file for Marvell Armada 7040 Development board platform */ +#include <dt-bindings/gpio/gpio.h> #include "armada-7040.dtsi" / { @@ -59,6 +60,34 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cpm_usb3_0_phy: cpm-usb3-0-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cpm_reg_usb3_0_vbus>; + }; + + cpm_usb3_1_phy: cpm-usb3-1-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cpm_reg_usb3_1_vbus>; + }; }; &i2c0 { @@ -105,6 +134,14 @@ &cpm_i2c0 { status = "okay"; clock-frequency = <100000>; + + expander0: pca9555@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x21>; + }; }; &cpm_spi1 { @@ -140,10 +177,12 @@ }; &cpm_usb3_0 { + usb-phy = <&cpm_usb3_0_phy>; status = "okay"; }; &cpm_usb3_1 { + usb-phy = <&cpm_usb3_1_phy>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 1e8f7242ed6f..0d7b2ae46610 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -44,6 +44,7 @@ * Device Tree file for Marvell Armada 8040 Development board platform */ +#include <dt-bindings/gpio/gpio.h> #include "armada-8040.dtsi" / { @@ -59,6 +60,48 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus { + compatible = "regulator-fixed"; + regulator-name = "cpm-usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus { + compatible = "regulator-fixed"; + regulator-name = "cpm-usb3h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cpm_usb3_0_phy: cpm-usb3-0-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cpm_reg_usb3_0_vbus>; + }; + + cpm_usb3_1_phy: cpm-usb3-1-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cpm_reg_usb3_1_vbus>; + }; + + cps_reg_usb3_0_vbus: cps-usb3-0-vbus { + compatible = "regulator-fixed"; + regulator-name = "cps-usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; + }; + + cps_usb3_0_phy: cps-usb3-0-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cps_reg_usb3_0_vbus>; + }; }; &i2c0 { @@ -107,6 +150,25 @@ &cpm_i2c0 { status = "okay"; clock-frequency = <100000>; + + /* U31 */ + expander0: pca9555@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x21>; + }; + + /* U25 */ + expander1: pca9555@25 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x25>; + }; + }; /* CON4 on CP0 expansion */ @@ -116,11 +178,13 @@ /* CON9 on CP0 expansion */ &cpm_usb3_0 { + usb-phy = <&cpm_usb3_0_phy>; status = "okay"; }; /* CON10 on CP0 expansion */ &cpm_usb3_1 { + usb-phy = <&cpm_usb3_1_phy>; status = "okay"; }; @@ -159,6 +223,7 @@ /* CON9 on CP1 expansion */ &cps_usb3_0 { + usb-phy = <&cps_usb3_0_phy>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index 4968e731de61..21fb721be6cb 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -46,11 +46,17 @@ #include "armada-8040.dtsi" +#include <dt-bindings/gpio/gpio.h> + / { model = "Marvell 8040 MACHIATOBin"; compatible = "marvell,armada8040-mcbin", "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory@00000000 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; @@ -77,11 +83,13 @@ v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { compatible = "regulator-fixed"; + enable-active-high; + gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_xhci_vbus_pins>; regulator-name = "v_5v0_usb3_hst_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - /* actually GPIO controlled, but 8k has no GPIO support yet */ - regulator-always-on; status = "okay"; }; @@ -112,10 +120,44 @@ &cpm_i2c0 { clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c0_pins>; status = "okay"; }; +&cpm_i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c1_pins>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + sfpp0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + sfpp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + sfp_1g_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; +}; + &cpm_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_ge_mdio_pins>; status = "okay"; ge_phy: ethernet-phy@0 { @@ -123,6 +165,43 @@ }; }; +&cpm_pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + num-viewport = <8>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cpm_pinctrl { + cpm_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp32", "mpp34"; + marvell,function = "ge"; + }; + cpm_i2c1_pins: i2c1-pins { + marvell,pins = "mpp35", "mpp36"; + marvell,function = "i2c1"; + }; + cpm_i2c0_pins: i2c0-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "i2c0"; + }; + cpm_xhci_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + cpm_pcie_pins: pcie-pins { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + cpm_sdhci_pins: sdhci-pins { + marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", + "mpp60", "mpp61"; + marvell,function = "sdio"; + }; +}; + &cpm_sata0 { /* CPM Lane 0 - U29 */ status = "okay"; @@ -132,6 +211,8 @@ /* U6 */ broken-cd; bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_sdhci_pins>; status = "okay"; vqmmc-supply = <&v_3_3>; }; @@ -157,6 +238,13 @@ phy-mode = "sgmii"; }; +&cps_pinctrl { + cps_spi1_pins: spi1-pins { + marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "spi1"; + }; +}; + &cps_sata0 { /* CPS Lane 1 - U32 */ /* CPS Lane 3 - U31 */ @@ -164,6 +252,8 @@ }; &cps_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cps_spi1_pins>; status = "okay"; spi-flash@0 { diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 726528ce54e9..8b019a9f4f59 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -115,6 +115,13 @@ msi-parent = <&gicp>; }; + cpm_rtc: rtc@284000 { + compatible = "marvell,armada-8k-rtc"; + reg = <0x284000 0x20>, <0x284080 0x24>; + reg-names = "rtc", "rtc-soc"; + interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; + }; + cpm_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; reg = <0x440000 0x1000>; @@ -131,8 +138,12 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&cpm_pinctrl 0 0 32>; + interrupt-controller; + interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - }; cpm_gpio2: gpio@140 { @@ -142,26 +153,15 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&cpm_pinctrl 0 32 31>; + interrupt-controller; + interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; }; - cpm_rtc: rtc@284000 { - compatible = "marvell,armada-8k-rtc"; - reg = <0x284000 0x20>, <0x284080 0x24>; - reg-names = "rtc", "rtc-soc"; - interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; - }; - - cpm_sata0: sata@540000 { - compatible = "marvell,armada-8k-ahci", - "generic-ahci"; - reg = <0x540000 0x30000>; - interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_clk 1 15>; - status = "disabled"; - }; - cpm_usb3_0: usb3@500000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; @@ -182,6 +182,15 @@ status = "disabled"; }; + cpm_sata0: sata@540000 { + compatible = "marvell,armada-8k-ahci", + "generic-ahci"; + reg = <0x540000 0x30000>; + interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpm_clk 1 15>; + status = "disabled"; + }; + cpm_xor0: xor@6a0000 { compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x6a0000 0x1000>, @@ -240,6 +249,21 @@ status = "disabled"; }; + cpm_nand: nand@720000 { + /* + * Due to the limiation of the pin available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ + compatible = "marvell,armada370-nand"; + reg = <0x720000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpm_clk 1 2>; + status = "disabled"; + }; + cpm_trng: trng@760000 { compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; reg = <0x760000 0x7d>; @@ -270,6 +294,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cpm_clk 1 26>; + dma-coherent; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 95f8e5f607f6..7c1100133731 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -60,13 +60,6 @@ compatible = "simple-bus"; ranges = <0x0 0x0 0xf4000000 0x2000000>; - cps_rtc: rtc@284000 { - compatible = "marvell,armada-8k-rtc"; - reg = <0x284000 0x20>, <0x284080 0x24>; - reg-names = "rtc", "rtc-soc"; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - }; - cps_ethernet: ethernet@0 { compatible = "marvell,armada-7k-pp22"; reg = <0x0 0x100000>, <0x129000 0xb000>; @@ -122,6 +115,13 @@ msi-parent = <&gicp>; }; + cps_rtc: rtc@284000 { + compatible = "marvell,armada-8k-rtc"; + reg = <0x284000 0x20>, <0x284080 0x24>; + reg-names = "rtc", "rtc-soc"; + interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; + }; + cps_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; reg = <0x440000 0x1000>; @@ -138,8 +138,12 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&cps_pinctrl 0 0 32>; + interrupt-controller; + interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - }; cps_gpio2: gpio@140 { @@ -149,20 +153,16 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&cps_pinctrl 0 32 31>; + interrupt-controller; + interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, + <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; }; - cps_sata0: sata@540000 { - compatible = "marvell,armada-8k-ahci", - "generic-ahci"; - reg = <0x540000 0x30000>; - interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_clk 1 15>; - status = "disabled"; - }; - cps_usb3_0: usb3@500000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; @@ -183,6 +183,15 @@ status = "disabled"; }; + cps_sata0: sata@540000 { + compatible = "marvell,armada-8k-ahci", + "generic-ahci"; + reg = <0x540000 0x30000>; + interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_clk 1 15>; + status = "disabled"; + }; + cps_xor0: xor@6a0000 { compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x6a0000 0x1000>, @@ -241,6 +250,21 @@ status = "disabled"; }; + cps_nand: nand@720000 { + /* + * Due to the limiation of the pin available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ + compatible = "marvell,armada370-nand"; + reg = <0x720000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_clk 1 2>; + status = "disabled"; + }; + cps_trng: trng@760000 { compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; reg = <0x760000 0x7d>; @@ -261,6 +285,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cps_clk 1 26>; + dma-coherent; /* * The cryptographic engine found on the cp110 * master is enabled by default at the SoC diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 015eb072ddef..151723b5c733 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,6 +1,8 @@ +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb always := $(dtb-y) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts new file mode 100644 index 000000000000..8c804df3da4e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: YT Shen <yt.shen@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include "mt2712e.dtsi" + +/ { + model = "MediaTek MT2712 evaluation board"; + compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi new file mode 100644 index 000000000000..57d0396b7faa --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: YT Shen <yt.shen@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt2712"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x001>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x200>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + baud_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + sys_clk: dummyclk { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; + }; + + uart5: serial@1000f000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x1000f000 0 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + sysirq: interrupt-controller@10220a80 { + compatible = "mediatek,mt2712-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10220a80 0 0x40>; + }; + + gic: interrupt-controller@10510000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10510000 0 0x10000>, + <0 0x10520000 0 0x20000>, + <0 0x10540000 0 0x20000>, + <0 0x10560000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart4: serial@11019000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11019000 0 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 31088a9f71de..4beaa71107d7 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -108,13 +108,6 @@ clock-output-names = "clk26m"; }; - clk32k: oscillator@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "clk32k"; - }; - timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; @@ -147,6 +140,11 @@ infracfg = <&infrasys>; }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + apmixedsys: apmixed@1000c000 { compatible = "mediatek,mt6797-apmixedsys"; reg = <0 0x1000c000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts new file mode 100644 index 000000000000..c08309df2cc7 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Ming Huang <ming.huang@mediatek.com> + * Sean Wang <sean.wang@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include "mt7622.dtsi" + +/ { + model = "MediaTek MT7622 RFB1 board"; + compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; + + chosen { + bootargs = "console=ttyS0,115200n1"; + }; + + memory { + reg = <0 0x40000000 0 0x3F000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi new file mode 100644 index 000000000000..b111fec2ed9d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Ming Huang <ming.huang@mediatek.com> + * Sean Wang <sean.wang@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt7622"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + clock-frequency = <1300000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + clock-frequency = <1300000000>; + }; + }; + + uart_clk: dummy25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + bus_clk: dummy280m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <280000000>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,mt7622-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10310000 0 0x1000>, + <0 0x10320000 0 0x1000>, + <0 0x10340000 0 0x2000>, + <0 0x10360000 0 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>, <&bus_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index cc0f02d9dd02..ff81d7e5805e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,5 +1,6 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi index d94640812194..790b7775b901 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi @@ -17,6 +17,7 @@ function = PMIC_GPIO_FUNC_NORMAL; power-source = <PM8916_GPIO_VPH>; input-disable; + output-high; }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index bd310ac1967a..1d63e6b879de 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -88,6 +88,8 @@ interrupts = <31 2>; adi,dsi-lanes = <4>; + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; pd-gpios = <&msmgpio 32 0>; @@ -213,11 +215,14 @@ }; usb@78d9000 { - extcon = <&usb_id>, <&usb_id>; + extcon = <&usb_id>; status = "okay"; adp-disable; hnp-disable; srp-disable; + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_sw_sel_pm>; ulpi { phy { v1p8-supply = <&pm8916_l7>; @@ -337,19 +342,11 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; - usb-switch { - compatible = "toshiba,tc7usb40mu"; - switch-gpios = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>; - extcon = <&usb_id>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_sw_sel_pm>; - }; - hdmi-out { compatible = "hdmi-connector"; type = "a"; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi index b1142c45fdc9..8e379782597a 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi @@ -24,4 +24,28 @@ power-source = <PM8994_GPIO_S4>; // 1.8V }; }; + + usb3_vbus_det_gpio: pm8996_gpio22 { + pinconf { + pins = "gpio22"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + power-source = <PM8994_GPIO_S4>; // 1.8V + }; + }; +}; + +&pmi8994_gpios { + usb2_vbus_det_gpio: pmi8996_gpio6 { + pinconf { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + power-source = <PM8994_GPIO_S4>; // 1.8V + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index d2196fc6d739..789f3e87321e 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -13,6 +13,7 @@ #include "msm8996.dtsi" #include "pm8994.dtsi" +#include "pmi8994.dtsi" #include "apq8096-db820c-pins.dtsi" #include "apq8096-db820c-pmic-pins.dtsi" #include <dt-bindings/input/input.h> @@ -88,6 +89,55 @@ cd-gpios = <&msmgpio 38 0x1>; status = "okay"; }; + + phy@34000 { + status = "okay"; + }; + + phy@7410000 { + status = "okay"; + }; + + phy@7411000 { + status = "okay"; + }; + + phy@7412000 { + status = "okay"; + }; + + usb@6a00000 { + status = "okay"; + + dwc3@6a00000 { + extcon = <&usb3_id>; + dr_mode = "otg"; + }; + }; + + usb3_id: usb3-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_det_gpio>; + }; + + usb@7600000 { + status = "okay"; + + dwc3@7600000 { + extcon = <&usb2_id>; + dr_mode = "otg"; + maximum-speed = "high-speed"; + }; + }; + + usb2_id: usb2-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_det_gpio>; + }; }; @@ -106,4 +156,152 @@ gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; }; }; + + rpm-glink { + rpm_requests { + pm8994-regulators { + vdd_l1-supply = <&pm8994_s3>; + vdd_l2_l26_l28-supply = <&pm8994_s3>; + vdd_l3_l11-supply = <&pm8994_s3>; + vdd_l4_l27_l31-supply = <&pm8994_s3>; + vdd_l5_l7-supply = <&pm8994_s5>; + vdd_l14_l15-supply = <&pm8994_s5>; + vdd_l20_l21-supply = <&pm8994_s5>; + vdd_l25-supply = <&pm8994_s3>; + + s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + s7 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + l2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + l3 { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + }; + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l11 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + l17 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + l19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + l22 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + l25 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + l28 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + l29 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + l30 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l32 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts new file mode 100644 index 000000000000..6a838b5d321e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -0,0 +1,52 @@ +/dts-v1/; +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "ipq8074.dtsi" + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; + compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + }; + + chosen { + stdout-path = "serial0"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x20000000>; + }; + + soc { + pinctrl@1000000 { + serial_4_pins: serial4_pinmux { + mux { + pins = "gpio23", "gpio24"; + function = "blsp4_uart1"; + bias-disable; + }; + }; + }; + + serial@78b3000 { + pinctrl-0 = <&serial_4_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi new file mode 100644 index 000000000000..2bc5dec5614d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-ipq8074.h> + +/ { + model = "Qualcomm Technologies, Inc. IPQ8074"; + compatible = "qcom,ipq8074"; + + soc: soc { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + pinctrl@1000000 { + compatible = "qcom,ipq8074-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <0x2>; + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <0x3>; + reg = <0xb000000 0x1000>, <0xb002000 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + clock-frequency = <19200000>; + + frame@b120000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + + gcc: gcc@1800000 { + compatible = "qcom,gcc-ipq8074"; + reg = <0x1800000 0x80000>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + }; + + blsp1_uart5: serial@78b3000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b3000 0x200>; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x1>; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x2>; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x3>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <0x2>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>; + }; + + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 039991f80831..dc3817593e14 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -88,6 +88,11 @@ no-map; }; + venus_mem: venus@89900000 { + reg = <0x0 0x89900000 0x0 0x600000>; + no-map; + }; + mba_mem: mba@8ea00000 { no-map; reg = <0 0x8ea00000 0 0x100000>; @@ -204,6 +209,17 @@ }; + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -694,6 +710,84 @@ #thermal-sensor-cells = <1>; }; + apps_iommu: iommu@1ef0000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1e20000 0x40000>; + reg = <0x1ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + // mdp_0: + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + }; + + // venus_ns: + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <18>; + + // gfx3d_user: + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + }; + + // gfx3d_priv: + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 242 0>; + }; + }; + + gpu@1c00000 { + compatible = "qcom,adreno-306.0", "qcom,adreno"; + reg = <0x01c00000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d"; + clocks = + <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>; + power-domains = <&gcc OXILI_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + }; + mdss: mdss@1a00000 { compatible = "qcom,mdss"; reg = <0x1a00000 0x1000>, @@ -735,6 +829,8 @@ "core_clk", "vsync_clk"; + iommus = <&apps_iommu 4>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -990,7 +1086,7 @@ }; replicator@824000 { - compatible = "qcom,coresight-replicator1x", "arm,primecell"; + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0x824000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; @@ -1207,6 +1303,28 @@ }; }; }; + + venus: video-codec@1d00000 { + compatible = "qcom,msm8916-venus"; + reg = <0x01d00000 0xff000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&gcc VENUS_GDSC>; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>; + clock-names = "core", "iface", "bus"; + iommus = <&apps_iommu 5>; + memory-region = <&venus_mem>; + status = "okay"; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + }; }; smd { diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8f085716e258..887b61c872dd 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -276,12 +276,83 @@ hwlocks = <&tcsr_mutex 3>; }; + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + mboxes = <&apcs_glb 0>; + + rpm_requests { + compatible = "qcom,rpm-msm8996"; + qcom,glink-channels = "rpm_requests"; + + pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + pm8994_s1: s1 {}; + pm8994_s2: s2 {}; + pm8994_s3: s3 {}; + pm8994_s4: s4 {}; + pm8994_s5: s5 {}; + pm8994_s6: s6 {}; + pm8994_s7: s7 {}; + pm8994_s8: s8 {}; + pm8994_s9: s9 {}; + pm8994_s10: s10 {}; + pm8994_s11: s11 {}; + pm8994_s12: s12 {}; + + pm8994_l1: l1 {}; + pm8994_l2: l2 {}; + pm8994_l3: l3 {}; + pm8994_l4: l4 {}; + pm8994_l5: l5 {}; + pm8994_l6: l6 {}; + pm8994_l7: l7 {}; + pm8994_l8: l8 {}; + pm8994_l9: l9 {}; + pm8994_l10: l10 {}; + pm8994_l11: l11 {}; + pm8994_l12: l12 {}; + pm8994_l13: l13 {}; + pm8994_l14: l14 {}; + pm8994_l15: l15 {}; + pm8994_l16: l16 {}; + pm8994_l17: l17 {}; + pm8994_l18: l18 {}; + pm8994_l19: l19 {}; + pm8994_l20: l20 {}; + pm8994_l21: l21 {}; + pm8994_l22: l22 {}; + pm8994_l23: l23 {}; + pm8994_l24: l24 {}; + pm8994_l25: l25 {}; + pm8994_l26: l26 {}; + pm8994_l27: l27 {}; + pm8994_l28: l28 {}; + pm8994_l29: l29 {}; + pm8994_l30: l30 {}; + pm8994_l31: l31 {}; + pm8994_l32: l32 {}; + }; + + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + rpm_msg_ram: memory@68000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x68000 0x6000>; + }; + tcsr_mutex_regs: syscon@740000 { compatible = "syscon"; reg = <0x740000 0x20000>; @@ -303,6 +374,13 @@ reg = <0x9820000 0x1000>; }; + apcs_glb: mailbox@9820000 { + compatible = "qcom,msm8996-apcs-hmss-global"; + reg = <0x9820000 0x1000>; + + #mbox-cells = <1>; + }; + gcc: clock-controller@300000 { compatible = "qcom,gcc-msm8996"; #clock-cells = <1>; @@ -538,6 +616,209 @@ <960000000>, <825000000>; }; + + qfprom@74000 { + compatible = "qcom,qfprom"; + reg = <0x74000 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2p_hstx_trim: hstx_trim@24e { + reg = <0x24e 0x2>; + bits = <5 4>; + }; + + qusb2s_hstx_trim: hstx_trim@24f { + reg = <0x24f 0x1>; + bits = <1 4>; + }; + }; + + phy@34000 { + compatible = "qcom,msm8996-qmp-pcie-phy"; + reg = <0x34000 0x488>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; + + resets = <&gcc GCC_PCIE_PHY_BCR>, + <&gcc GCC_PCIE_PHY_COM_BCR>, + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; + reset-names = "phy", "common", "cfg"; + status = "disabled"; + + pciephy_0: lane@35000 { + reg = <0x035000 0x130>, + <0x035200 0x200>, + <0x035400 0x1dc>; + #phy-cells = <0>; + + clock-output-names = "pcie_0_pipe_clk_src"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "lane0"; + }; + + pciephy_1: lane@36000 { + reg = <0x036000 0x130>, + <0x036200 0x200>, + <0x036400 0x1dc>; + #phy-cells = <0>; + + clock-output-names = "pcie_1_pipe_clk_src"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe1"; + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "lane1"; + }; + + pciephy_2: lane@37000 { + reg = <0x037000 0x130>, + <0x037200 0x200>, + <0x037400 0x1dc>; + #phy-cells = <0>; + + clock-output-names = "pcie_2_pipe_clk_src"; + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "pipe2"; + resets = <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "lane2"; + }; + }; + + phy@7410000 { + compatible = "qcom,msm8996-qmp-usb3-phy"; + reg = <0x7410000 0x1c4>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", "common"; + status = "disabled"; + + ssusb_phy_0: lane@7410200 { + reg = <0x7410200 0x200>, + <0x7410400 0x130>, + <0x7410600 0x1a8>; + #phy-cells = <0>; + + clock-output-names = "usb3_phy_pipe_clk_src"; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + }; + }; + + hsusb_phy1: phy@7411000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x7411000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + vdda-pll-supply = <&pm8994_l12>; + vdda-phy-dpdm-supply = <&pm8994_l24>; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2p_hstx_trim>; + status = "disabled"; + }; + + hsusb_phy2: phy@7412000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x7412000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX2_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + vdda-pll-supply = <&pm8994_l12>; + vdda-phy-dpdm-supply = <&pm8994_l24>; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + nvmem-cells = <&qusb2s_hstx_trim>; + status = "disabled"; + }; + + usb2: usb@7600000 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <60000000>; + + power-domains = <&gcc USB30_GDSC>; + status = "disabled"; + + dwc3@7600000 { + compatible = "snps,dwc3"; + reg = <0x7600000 0xcc00>; + interrupts = <0 138 0>; + phys = <&hsusb_phy2>; + phy-names = "usb2-phy"; + }; + }; + + usb3: usb@6a00000 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_AGGRE2_USB3_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + status = "disabled"; + + dwc3@6a00000 { + compatible = "snps,dwc3"; + reg = <0x6a00000 0xcc00>; + interrupts = <0 131 0>; + phys = <&hsusb_phy1>, <&ssusb_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; }; adsp-pil { @@ -558,6 +839,15 @@ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + smd-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + + label = "lpass"; + qcom,ipc = <&apcs 16 8>; + qcom,smd-edge = <1>; + qcom,remote-pid = <2>; + }; }; adsp-smp2p { @@ -584,6 +874,30 @@ }; }; + modem-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 16 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smp2p-slpi { compatible = "qcom,smp2p"; qcom,smem = <481>, <430>; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index d3879a4e8076..57673f92805d 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -8,6 +8,23 @@ reg = <0x2 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmi8994_gpios: gpios@c000 { + compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 0xc0 0 IRQ_TYPE_NONE>, + <2 0xc1 0 IRQ_TYPE_NONE>, + <2 0xc2 0 IRQ_TYPE_NONE>, + <2 0xc3 0 IRQ_TYPE_NONE>, + <2 0xc4 0 IRQ_TYPE_NONE>, + <2 0xc5 0 IRQ_TYPE_NONE>, + <2 0xc6 0 IRQ_TYPE_NONE>, + <2 0xc7 0 IRQ_TYPE_NONE>, + <2 0xc8 0 IRQ_TYPE_NONE>, + <2 0xc9 0 IRQ_TYPE_NONE>; + }; }; pmic@3 { diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index acc4bb30d485..381928bc1358 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb +dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb always := $(dtb-y) clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts index 95fe207cb6a3..dd4f9b6a4254 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts @@ -9,8 +9,6 @@ * kind, whether express or implied. */ -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - /dts-v1/; #include "r8a7795-es1.dtsi" #include "ulcb.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts index b84c156ed696..3f7d5f51e428 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts @@ -8,8 +8,6 @@ * kind, whether express or implied. */ -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - /dts-v1/; #include "r8a7795-es1.dtsi" #include "salvator-x.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index a0ba7bd21ea3..aaa5e67a963e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -21,6 +21,14 @@ status = "disabled"; }; + /delete-node/ usb-phy@ee0e0200; + /delete-node/ usb@ee0e0100; + /delete-node/ usb@ee0e0000; + /delete-node/ usb@e659c000; + + /delete-node/ dma-controller@e6460000; + /delete-node/ dma-controller@e6470000; + fcpf2: fcp@fe952000 { compatible = "renesas,fcpf"; reg = <0 0xfe952000 0 0x200>; @@ -79,6 +87,5 @@ }; &du { - compatible = "renesas,du-r8a7795"; vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 0426f41765f0..0afe777973de 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -9,8 +9,6 @@ * kind, whether express or implied. */ -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - /dts-v1/; #include "r8a7795.dtsi" #include "ulcb.dtsi" @@ -40,3 +38,17 @@ reg = <0x7 0x00000000 0x0 0x40000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>, + <&versaclock5 1>, + <&versaclock5 3>, + <&versaclock5 4>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", + "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 684fb3b9d154..17953070f38d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -8,8 +8,6 @@ * kind, whether express or implied. */ -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - /dts-v1/; #include "r8a7795.dtsi" #include "salvator-x.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts index de354957144b..7675de5d4f2c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts @@ -8,8 +8,6 @@ * kind, whether express or implied. */ -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - /dts-v1/; #include "r8a7795.dtsi" #include "salvator-xs.dtsi" @@ -46,10 +44,12 @@ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, <&cpg CPG_MOD 727>, + <&versaclock6 1>, <&x21_clk>, - <&x22_clk>; + <&x22_clk>, + <&versaclock6 2>; clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", - "dclkin.1", "dclkin.2"; + "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; }; &ehci2 { diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index e31c1b660b3f..2938195b9571 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -12,6 +12,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7795-sysc.h> +#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 + / { compatible = "renesas,r8a7795"; #address-cells = <2>; @@ -691,6 +693,126 @@ }; }; + drif00: rif@e6f40000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x64>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; + status = "disabled"; + }; + + drif01: rif@e6f50000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x64>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; + status = "disabled"; + }; + + drif10: rif@e6f60000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x64>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; + status = "disabled"; + }; + + drif11: rif@e6f70000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x64>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; + status = "disabled"; + }; + + drif20: rif@e6f80000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x64>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; + status = "disabled"; + }; + + drif21: rif@e6f90000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x64>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; + status = "disabled"; + }; + + drif30: rif@e6fa0000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x64>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; + status = "disabled"; + }; + + drif31: rif@e6fb0000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x64>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; + status = "disabled"; + }; + hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", @@ -776,6 +898,68 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7795", "renesas,rcar-gen3-scif", "renesas,scif"; @@ -1267,7 +1451,8 @@ }; sata: sata@ee300000 { - compatible = "renesas,sata-r8a7795"; + compatible = "renesas,sata-r8a7795", + "renesas,rcar-gen3-sata"; reg = <0 0xee300000 0 0x200000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 815>; @@ -1314,6 +1499,34 @@ dma-channels = <2>; }; + usb_dmac2: dma-controller@e6460000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe6460000 0 0x100>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 326>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 326>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac3: dma-controller@e6470000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe6470000 0 0x100>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 329>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 329>; + #dma-cells = <1>; + dma-channels = <2>; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7795"; reg = <0 0xee100000 0 0x2000>; @@ -1392,6 +1605,18 @@ status = "disabled"; }; + usb2_phy3: usb-phy@ee0e0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0e0200 0 0x700>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 700>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 700>; + #phy-cells = <0>; + status = "disabled"; + }; + ehci0: usb@ee080100 { compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; @@ -1399,6 +1624,7 @@ clocks = <&cpg CPG_MOD 703>; phys = <&usb2_phy0>; phy-names = "usb"; + companion = <&ohci0>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; @@ -1411,6 +1637,7 @@ clocks = <&cpg CPG_MOD 702>; phys = <&usb2_phy1>; phy-names = "usb"; + companion = <&ohci1>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 702>; status = "disabled"; @@ -1423,11 +1650,25 @@ clocks = <&cpg CPG_MOD 701>; phys = <&usb2_phy2>; phy-names = "usb"; + companion = <&ohci2>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 701>; status = "disabled"; }; + ehci3: usb@ee0e0100 { + compatible = "generic-ehci"; + reg = <0 0xee0e0100 0 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 700>; + phys = <&usb2_phy3>; + phy-names = "usb"; + companion = <&ohci3>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 700>; + status = "disabled"; + }; + ohci0: usb@ee080000 { compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; @@ -1464,6 +1705,18 @@ status = "disabled"; }; + ohci3: usb@ee0e0000 { + compatible = "generic-ohci"; + reg = <0 0xee0e0000 0 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 700>; + phys = <&usb2_phy3>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 700>; + status = "disabled"; + }; + hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a7795", "renesas,rcar-gen3-usbhs"; @@ -1481,6 +1734,23 @@ status = "disabled"; }; + hsusb3: usb@e659c000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe659c000 0 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 705>; + dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, + <&usb_dmac3 0>, <&usb_dmac3 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy3>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a7795", "renesas,pcie-rcar-gen3"; @@ -1535,6 +1805,46 @@ status = "disabled"; }; + imr-lx4@fe860000 { + compatible = "renesas,r8a7795-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe860000 0 0x2000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 823>; + power-domains = <&sysc R8A7795_PD_A3VC>; + resets = <&cpg 823>; + }; + + imr-lx4@fe870000 { + compatible = "renesas,r8a7795-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe870000 0 0x2000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 822>; + power-domains = <&sysc R8A7795_PD_A3VC>; + resets = <&cpg 822>; + }; + + imr-lx4@fe880000 { + compatible = "renesas,r8a7795-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe880000 0 0x2000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 821>; + power-domains = <&sysc R8A7795_PD_A3VC>; + resets = <&cpg 821>; + }; + + imr-lx4@fe890000 { + compatible = "renesas,r8a7795-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe890000 0 0x2000>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 820>; + power-domains = <&sysc R8A7795_PD_A3VC>; + resets = <&cpg 820>; + }; + vspbc: vsp@fe920000 { compatible = "renesas,vsp2"; reg = <0 0xfe920000 0 0x8000>; @@ -1755,6 +2065,7 @@ }; du: display@feb00000 { + compatible = "renesas,du-r8a7795"; reg = <0 0xfeb00000 0 0x80000>, <0 0xfeb90000 0 0x14>; reg-names = "du", "lvds.0"; @@ -1768,6 +2079,7 @@ <&cpg CPG_MOD 721>, <&cpg CPG_MOD 727>; clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; + vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>; status = "disabled"; ports { diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 38b58b7fca4b..daee1f1a3f68 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -9,8 +9,6 @@ * kind, whether express or implied. */ -#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 - /dts-v1/; #include "r8a7796.dtsi" #include "ulcb.dtsi" @@ -30,3 +28,15 @@ reg = <0x6 0x00000000 0x0 0x40000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 727>, + <&versaclock5 1>, + <&versaclock5 3>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", "lvds.0", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index db4f162d6bdd..b317be03306e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -8,8 +8,6 @@ * kind, whether express or implied. */ -#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 - /dts-v1/; #include "r8a7796.dtsi" #include "salvator-x.dtsi" @@ -29,3 +27,32 @@ reg = <0x6 0x00000000 0x0 0x80000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 727>, + <&versaclock5 1>, + <&x21_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", "lvds.0", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; +}; + +&hdmi0_con { + remote-endpoint = <&rcar_dw_hdmi0_out>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 1f6710912045..369092e17e34 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -12,6 +12,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7796-sysc.h> +#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 + / { compatible = "renesas,r8a7796"; #address-cells = <2>; @@ -639,6 +641,126 @@ }; }; + drif00: rif@e6f40000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x64>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; + status = "disabled"; + }; + + drif01: rif@e6f50000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x64>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; + status = "disabled"; + }; + + drif10: rif@e6f60000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x64>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; + status = "disabled"; + }; + + drif11: rif@e6f70000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x64>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; + status = "disabled"; + }; + + drif20: rif@e6f80000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x64>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; + status = "disabled"; + }; + + drif21: rif@e6f90000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x64>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; + status = "disabled"; + }; + + drif30: rif@e6fa0000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x64>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; + status = "disabled"; + }; + + drif31: rif@e6fb0000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x64>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; + status = "disabled"; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a7796", "renesas,etheravb-rcar-gen3"; @@ -877,7 +999,7 @@ clocks = <&cpg CPG_MOD 211>; dmas = <&dmac1 0x41>, <&dmac1 0x40>, <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx"; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 211>; #address-cells = <1>; @@ -893,7 +1015,7 @@ clocks = <&cpg CPG_MOD 210>; dmas = <&dmac1 0x43>, <&dmac1 0x42>, <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx"; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 210>; #address-cells = <1>; @@ -1101,36 +1223,133 @@ dma-channels = <16>; }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7796-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7796-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + hsusb: usb@e6590000 { - /* placeholder */ + compatible = "renesas,usbhs-r8a7796", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; }; xhci0: usb@ee000000 { - /* placeholder */ + compatible = "renesas,xhci-r8a7796", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; }; ohci0: usb@ee080000 { - /* placeholder */ + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; }; ehci0: usb@ee080100 { - /* placeholder */ + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion= <&ohci0>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; }; usb2_phy0: usb-phy@ee080200 { - /* placeholder */ + compatible = "renesas,usb2-phy-r8a7796", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; }; ohci1: usb@ee0a0000 { - /* placeholder */ + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; }; ehci1: usb@ee0a0100 { - /* placeholder */ + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion= <&ohci1>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; }; usb2_phy1: usb-phy@ee0a0200 { - /* placeholder */ + compatible = "renesas,usb2-phy-r8a7796", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <0>; + status = "disabled"; }; sdhi0: sd@ee100000 { @@ -1440,8 +1659,150 @@ /* placeholder */ }; + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 615>; + }; + + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 607>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 611>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x4000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x4000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x4000>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 621>; + + renesas,fcp = <&fcpvd2>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 601>; + }; + + hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi"; + reg = <0 0xfead0000 0 0x10000>; + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + }; + }; + }; + du: display@feb00000 { - /* placeholder */ + compatible = "renesas,du-r8a7796"; + reg = <0 0xfeb00000 0 0x70000>, + <0 0xfeb90000 0 0x14>; + reg-names = "du", "lvds.0"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 727>; + clock-names = "du.0", "du.1", "du.2", "lvds.0"; + status = "disabled"; + + vsps = <&vspd0 &vspd1 &vspd2>; ports { #address-cells = <1>; @@ -1452,7 +1813,38 @@ du_out_rgb: endpoint { }; }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds0: endpoint { + }; + }; }; }; + + imr-lx4@fe860000 { + compatible = "renesas,r8a7796-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe860000 0 0x2000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 823>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 823>; + }; + + imr-lx4@fe870000 { + compatible = "renesas,r8a7796-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe870000 0 0x2000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 822>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 822>; + }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts new file mode 100644 index 000000000000..d144370051d5 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -0,0 +1,46 @@ +/* + * Device Tree Source for the Draak board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2017 Glider bvba + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a77995.dtsi" + +/ { + model = "Renesas Draak board based on r8a77995"; + compatible = "renesas,draak", "renesas,r8a77995"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x18000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&scif2 { + status = "okay"; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi new file mode 100644 index 000000000000..d0f95b78c022 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -0,0 +1,155 @@ +/* + * Device Tree Source for the r8a77995 SoC + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2017 Glider bvba + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "renesas,r8a77995"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a53_0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc 21>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77995-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc 32>; + resets = <&cpg 402>; + status = "disabled"; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77995-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77995-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a77995"; + reg = <0 0xe6060000 0 0x508>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77995-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE 16>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 310>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index aef35e0b685a..a39a0abeeffe 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -268,10 +268,6 @@ remote-endpoint = <&adv7123_in>; }; }; - port@3 { - lvds_connector: endpoint { - }; - }; }; }; @@ -508,7 +504,7 @@ /* audio_clkout0/1/2/3 */ #clock-cells = <1>; - clock-frequency = <11289600 12288000>; + clock-frequency = <12288000 11289600>; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi index 81227e3c2c6f..bf4d200fb546 100644 --- a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi @@ -18,3 +18,13 @@ &extal_clk { clock-frequency = <16640000>; }; + +&i2c4 { + versaclock6: clock-generator@6a { + compatible = "idt,5p49v6901"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x23_clk>; + clock-names = "xin"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index b5c6ee07d7f9..1b868df2393f 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -34,6 +34,16 @@ clock-frequency = <11289600>; }; + hdmi0-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con: endpoint { + }; + }; + }; + keyboard { compatible = "gpio-keys"; @@ -120,6 +130,12 @@ #clock-cells = <0>; clock-frequency = <24576000>; }; + + x23_clk: x23-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; &audio_clk_a { @@ -153,6 +169,23 @@ clock-frequency = <32768>; }; +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; +}; + +&hdmi0_con { + remote-endpoint = <&rcar_dw_hdmi0_out>; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -189,6 +222,24 @@ }; }; +&i2c4 { + status = "okay"; + + clock-frequency = <400000>; + + versaclock5: clock-generator@6a { + compatible = "idt,5p49v5925"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x23_clk>; + clock-names = "xin"; + }; +}; + +&i2c_dvfs { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -281,7 +332,7 @@ /* audio_clkout0/1/2/3 */ #clock-cells = <1>; - clock-frequency = <11289600 12288000>; + clock-frequency = <12288000 11289600>; status = "okay"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts index 115357018ef7..2452b2243f42 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "uniphier-ld11.dtsi" +#include "uniphier-ld11.dtsi" / { model = "UniPhier LD11 Global Board (REF_LD11_GP)"; @@ -68,3 +68,7 @@ &usb2 { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts index cc8ebe34c27c..ffb473ad2e0f 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts @@ -8,9 +8,9 @@ */ /dts-v1/; -/include/ "uniphier-ld11.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" +#include "uniphier-ld11.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi" / { model = "UniPhier LD11 Reference Board"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index bdce5b89baec..166d121ce3a7 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -367,8 +367,23 @@ compatible = "socionext,uniphier-ld11-reset"; #reset-cells = <1>; }; + + watchdog { + compatible = "socionext,uniphier-wdt"; + }; + }; + + nand: nand@68000000 { + compatible = "socionext,uniphier-denali-nand-v5b"; + status = "disabled"; + reg-names = "nand_data", "denali_reg"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + interrupts = <0 65 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + clocks = <&sys_clk 2>; }; }; }; -/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index 9f620d4101b5..fc2bc9d75d35 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "uniphier-ld20.dtsi" +#include "uniphier-ld20.dtsi" / { model = "UniPhier LD20 Global Board (REF_LD20_GP)"; @@ -50,3 +50,7 @@ &i2c0 { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts index 494166aee24c..1ca0c8620dc5 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts @@ -8,9 +8,9 @@ */ /dts-v1/; -/include/ "uniphier-ld20.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" +#include "uniphier-ld20.dtsi" +#include "uniphier-ref-daughter.dtsi" +#include "uniphier-support-card.dtsi" / { model = "UniPhier LD20 Reference Board"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index de1e75362817..58f8fdfc137c 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -388,8 +388,23 @@ compatible = "socionext,uniphier-ld20-reset"; #reset-cells = <1>; }; + + watchdog { + compatible = "socionext,uniphier-wdt"; + }; + }; + + nand: nand@68000000 { + compatible = "socionext,uniphier-denali-nand-v5b"; + status = "disabled"; + reg-names = "nand_data", "denali_reg"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + interrupts = <0 65 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + clocks = <&sys_clk 2>; }; }; }; -/include/ "uniphier-pinctrl.dtsi" +#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi index f42fb6f38bd3..9caabbb8bae3 120000..100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi @@ -1 +1 @@ -../../../../arm/boot/dts/uniphier-pinctrl.dtsi
\ No newline at end of file +#include <arm/uniphier-pinctrl.dtsi> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi index 4685a8d89cba..e66d999d9f5d 120000..100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi @@ -1 +1 @@ -../../../../arm/boot/dts/uniphier-ref-daughter.dtsi
\ No newline at end of file +#include <arm/uniphier-ref-daughter.dtsi> diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi index 1246db9be2a1..28c5b4ed1d95 120000..100644 --- a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi @@ -1 +1 @@ -../../../../arm/boot/dts/uniphier-support-card.dtsi
\ No newline at end of file +#include <arm/uniphier-support-card.dtsi> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi index cdc6a437dcc7..b87b8316f4ac 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi @@ -11,7 +11,7 @@ * the License, or (at your option) any later version. */ -&amba { +/ { misc_clk: misc_clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -29,12 +29,60 @@ #clock-cells = <0>; clock-frequency = <75000000>; }; + + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk600: clk600 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; }; &can0 { clocks = <&misc_clk &misc_clk>; }; +&can1 { + clocks = <&misc_clk &misc_clk>; +}; + +&fpd_dma_chan1 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan2 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan3 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan4 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan5 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan6 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan7 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan8 { + clocks = <&clk600>, <&clk100>; +}; + &gem0 { clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts index ef1b9e573af0..bf552674a834 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts @@ -13,13 +13,15 @@ /dts-v1/; -/include/ "zynqmp.dtsi" -/include/ "zynqmp-ep108-clk.dtsi" +#include "zynqmp.dtsi" +#include "zynqmp-ep108-clk.dtsi" / { model = "ZynqMP EP108"; aliases { + mmc0 = &sdhci0; + mmc1 = &sdhci1; serial0 = &uart0; }; @@ -37,6 +39,10 @@ status = "okay"; }; +&can1 { + status = "okay"; +}; + &gem0 { status = "okay"; phy-handle = <&phy0>; @@ -55,7 +61,7 @@ status = "okay"; clock-frequency = <400000>; eeprom@54 { - compatible = "at,24c64"; + compatible = "atmel,24c64"; reg = <0x54>; }; }; @@ -64,7 +70,7 @@ status = "okay"; clock-frequency = <400000>; eeprom@55 { - compatible = "at,24c64"; + compatible = "atmel,24c64"; reg = <0x55>; }; }; @@ -92,7 +98,7 @@ spi-max-frequency = <50000000>; reg = <0>; - spi0_flash0@00000000 { + spi0_flash0@0 { label = "spi0_flash0"; reg = <0x0 0x100000>; }; @@ -109,7 +115,7 @@ spi-max-frequency = <50000000>; reg = <0>; - spi1_flash0@00000000 { + spi1_flash0@0 { label = "spi1_flash0"; reg = <0x0 0x100000>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 54dc28351c8c..7665fbddff28 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -20,33 +20,84 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; + cpu-idle-states = <&CPU_SLEEP_0>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <600>; + min-residency-us = <10000>; + }; + }; + }; + + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <1199999988>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp01 { + opp-hz = /bits/ 64 <599999994>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp02 { + opp-hz = /bits/ 64 <399999996>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp03 { + opp-hz = /bits/ 64 <299999997>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; }; pmu { @@ -119,6 +170,190 @@ rx-fifo-depth = <0x40>; }; + cci: cci@fd6e0000 { + compatible = "arm,cci-400"; + reg = <0x0 0xfd6e0000 0x0 0x9000>; + ranges = <0x0 0x0 0xfd6e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupt-parent = <&gic>; + interrupts = <0 123 4>, + <0 123 4>, + <0 123 4>, + <0 123 4>, + <0 123 4>; + }; + }; + + /* GDMA */ + fpd_dma_chan1: dma@fd500000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd500000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 124 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan2: dma@fd510000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd510000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 125 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan3: dma@fd520000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd520000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 126 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan4: dma@fd530000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd530000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 127 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan5: dma@fd540000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd540000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 128 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan6: dma@fd550000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd550000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 129 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan7: dma@fd560000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd560000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 130 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan8: dma@fd570000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd570000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 131 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + }; + + /* LPDDMA default allows only secured access. inorder to enable + * These dma channels, Users should ensure that these dma + * Channels are allowed for non secure access. + */ + lpd_dma_chan1: dma@ffa80000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffa80000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 77 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan2: dma@ffa90000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffa90000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 78 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan3: dma@ffaa0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffaa0000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 79 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan4: dma@ffab0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffab0000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 80 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan5: dma@ffac0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffac0000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 81 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan6: dma@ffad0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffad0000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 82 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan7: dma@ffae0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffae0000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 83 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan8: dma@ffaf0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffaf0000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 84 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <64>; + }; + gem0: ethernet@ff0b0000 { compatible = "cdns,gem"; status = "disabled"; @@ -215,12 +450,9 @@ <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 - 0xe0000000 0x00000000 0x10000000 - /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 - 0x00000000 0x00000002 0x00000000>; - /* prefetchable memory */ + ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ + 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, @@ -233,6 +465,16 @@ }; }; + rtc: rtc@ffa60000 { + compatible = "xlnx,zynqmp-rtc"; + status = "disabled"; + reg = <0x0 0xffa60000 0x0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 26 4>, <0 27 4>; + interrupt-names = "alarm", "sec"; + calibration = <0x8000>; + }; + sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; @@ -262,13 +504,14 @@ smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; + status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; - interrupts = <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; + interrupts = <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { @@ -330,7 +573,7 @@ }; uart0: serial@ff000000 { - compatible = "cdns,uart-r1p8"; + compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; @@ -339,7 +582,7 @@ }; uart1: serial@ff010000 { - compatible = "cdns,uart-r1p8"; + compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; diff --git a/arch/arm64/boot/dts/zte/Makefile b/arch/arm64/boot/dts/zte/Makefile index 667806620f59..d86c4def6bc9 100644 --- a/arch/arm64/boot/dts/zte/Makefile +++ b/arch/arm64/boot/dts/zte/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb +dtb-$(CONFIG_ARCH_ZX) += zx296718-pcbox.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts index bb900d2bbcfb..cb2519ecd724 100644 --- a/arch/arm64/boot/dts/zte/zx296718-evb.dts +++ b/arch/arm64/boot/dts/zte/zx296718-evb.dts @@ -57,16 +57,28 @@ reg = <0x40000000 0x40000000>; }; - sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "zx_snd_spdif0"; + sound-spdif0 { + compatible = "audio-graph-card"; + dais = <&spdif0_port>; + }; - simple-audio-card,cpu { - sound-dai = <&spdif0>; - }; + sound-i2s0 { + compatible = "audio-graph-card"; + dais = <&i2s0_port>; + pinctrl-names = "default"; + pinctrl-0 = <&lifier_pins>; + pa-gpios = <&bgpio4 0 GPIO_ACTIVE_HIGH>; + widgets = "Line", "Line Out Jack"; + routing = "Amplifier", "LINEOUTL", + "Amplifier", "LINEOUTR", + "Line Out Jack", "Amplifier"; + }; +}; - simple-audio-card,codec { - sound-dai = <&hdmi>; +&aud96p22 { + port { + aud96p22_endpoint: endpoint { + remote-endpoint = <&i2s0_endpoint>; }; }; }; @@ -77,6 +89,36 @@ &hdmi { status = "okay"; + + port { + hdmi_endpoint: endpoint { + remote-endpoint = <&spdif0_endpoint>; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2s0 { + status = "okay"; + + i2s0_port: port { + i2s0_endpoint: endpoint { + remote-endpoint = <&aud96p22_endpoint>; + dai-format = "i2s"; + frame-master; + bitclock-master; + }; + }; +}; + +&pmm { + amplifier_pins: amplifier { + pins = "TSI3_DATA"; + function = "BGPIO"; + }; }; &sd1 { @@ -85,6 +127,16 @@ &spdif0 { status = "okay"; + + spdif0_port: port { + spdif0_endpoint: endpoint { + remote-endpoint = <&hdmi_endpoint>; + }; + }; +}; + +&tvenc { + status = "okay"; }; &uart0 { diff --git a/arch/arm64/boot/dts/zte/zx296718-pcbox.dts b/arch/arm64/boot/dts/zte/zx296718-pcbox.dts new file mode 100644 index 000000000000..e02509f7082b --- /dev/null +++ b/arch/arm64/boot/dts/zte/zx296718-pcbox.dts @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include "zx296718.dtsi" +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "ZTE ZX296718 PCBOX Board"; + compatible = "zte,zx296718-pcbox", "zte,zx296718"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + a53_vdd0v9: regulator-a53 { + compatible = "pwm-regulator"; + pwms = <&pwm 3 1250 PWM_POLARITY_INVERTED>; + regulator-name = "A53_VDD0V9"; + regulator-min-microvolt = <855000>; + regulator-max-microvolt = <1183000>; + pwm-dutycycle-unit = <100>; + pwm-dutycycle-range = <0 100>; + regulator-always-on; + regulator-boot-on; + }; + + sound-spdif0 { + compatible = "audio-graph-card"; + dais = <&spdif0_port>; + }; + + sound-i2s0 { + compatible = "audio-graph-card"; + dais = <&i2s0_port>; + }; +}; + +&aud96p22 { + port { + aud96p22_endpoint: endpoint { + remote-endpoint = <&i2s0_endpoint>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&a53_vdd0v9>; +}; + +&emmc { + status = "okay"; +}; + +&hdmi { + status = "disabled"; + + port { + hdmi_endpoint: endpoint { + remote-endpoint = <&spdif0_endpoint>; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2s0 { + status = "okay"; + + i2s0_port: port { + i2s0_endpoint: endpoint { + remote-endpoint = <&aud96p22_endpoint>; + dai-format = "i2s"; + frame-master; + bitclock-master; + }; + }; +}; + +&irdec { + status = "okay"; +}; + +&pmm { + pwm3_pins: pwm3 { + pins = "KEY_ROW2"; + function = "PWM"; + }; + + vga_pins: vga { + pins = "KEY_COL1", "KEY_COL2", "VGA_HS", "VGA_VS"; + function = "VGA"; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins>; + status = "okay"; +}; + +&sd0 { + status = "okay"; +}; + +&sd1 { + status = "okay"; +}; + +&spdif0 { + status = "okay"; + + spdif0_port: port { + spdif0_endpoint: endpoint { + remote-endpoint = <&hdmi_endpoint>; + }; + }; +}; + +&tvenc { + status = "disabled"; +}; + +&uart0 { + status = "okay"; +}; + +&vga { + pinctrl-names = "default"; + pinctrl-0 = <&vga_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi index d83bf789c864..6eef64761009 100644 --- a/arch/arm64/boot/dts/zte/zx296718.dtsi +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi @@ -53,6 +53,13 @@ interrupt-parent = <&gic>; aliases { + gpio0 = &bgpio0; + gpio1 = &bgpio1; + gpio2 = &bgpio2; + gpio3 = &bgpio3; + gpio4 = &bgpio4; + gpio5 = &bgpio5; + gpio6 = &bgpio6; serial0 = &uart0; }; @@ -120,26 +127,31 @@ opp-500000000 { opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <866000>; clock-latency-ns = <500000>; }; opp-648000000 { opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <866000>; clock-latency-ns = <500000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <888000>; clock-latency-ns = <500000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <898000>; clock-latency-ns = <500000>; }; opp-1188000000 { opp-hz = /bits/ 64 <1188000000>; + opp-microvolt = <1015000>; clock-latency-ns = <500000>; }; }; @@ -283,11 +295,23 @@ compatible = "simple-bus"; ranges; + irdec: ir-decoder@111000 { + compatible = "zte,zx296718-irdec"; + reg = <0x111000 0x1000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + aon_sysctrl: aon-sysctrl@116000 { compatible = "zte,zx296718-aon-sysctrl", "syscon"; reg = <0x116000 0x1000>; }; + iocfg: pin-controller@119000 { + compatible = "zte,zx296718-iocfg"; + reg = <0x119000 0x1000>; + }; + uart0: uart@11f000 { compatible = "arm,pl011", "arm,primecell"; arm,primecell-periphid = <0x001feffe>; @@ -311,7 +335,6 @@ clock-frequency = <50000000>; clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; clock-names = "biu", "ciu"; - num-slots = <1>; max-frequency = <50000000>; cap-sdio-irq; cap-sd-highspeed; @@ -336,7 +359,6 @@ clock-frequency = <167000000>; clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>; clock-names = "biu", "ciu"; - num-slots = <1>; max-frequency = <167000000>; cap-sdio-irq; cap-sd-highspeed; @@ -360,12 +382,109 @@ #clock-cells = <1>; }; + bgpio0: gpio@142d000 { + compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; + reg = <0x142d000 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm 0 48 16>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + bgpio1: gpio@142d040 { + compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; + reg = <0x142d040 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm 0 80 16>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + bgpio2: gpio@142d080 { + compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; + reg = <0x142d080 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm 0 80 3 + &pmm 3 32 4 + &pmm 7 83 9>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + bgpio3: gpio@142d0c0 { + compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; + reg = <0x142d0c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm 0 92 16>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + bgpio4: gpio@142d100 { + compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; + reg = <0x142d100 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm 0 108 12 + &pmm 12 121 4>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + bgpio5: gpio@142d140 { + compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; + reg = <0x142d140 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm 0 125 16>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + bgpio6: gpio@142d180 { + compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; + reg = <0x142d180 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm 0 141 2>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + }; + lsp1crm: clock-controller@1430000 { compatible = "zte,zx296718-lsp1crm"; reg = <0x01430000 0x1000>; #clock-cells = <1>; }; + pwm: pwm@1439000 { + compatible = "zte,zx296718-pwm"; + reg = <0x1439000 0x1000>; + clocks = <&lsp1crm LSP1_PWM_PCLK>, + <&lsp1crm LSP1_PWM_WCLK>; + clock-names = "pclk", "wclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + vou: vou@1440000 { compatible = "zte,zx296718-vou"; #address-cells = <1>; @@ -387,6 +506,16 @@ "main_wclk", "aux_wclk"; }; + vga: vga@8000 { + compatible = "zte,zx296718-vga"; + reg = <0x8000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topcrm VGA_I2C_WCLK>; + clock-names = "i2c_wclk"; + zte,vga-power-control = <&sysctrl 0x170 0xe0>; + status = "disabled"; + }; + hdmi: hdmi@c000 { compatible = "zte,zx296718-hdmi"; reg = <0xc000 0x4000>; @@ -413,6 +542,12 @@ #clock-cells = <1>; }; + pmm: pin-controller@1462000 { + compatible = "zte,zx296718-pmm"; + reg = <0x1462000 0x1000>; + zte,auxiliary-controller = <&iocfg>; + }; + sysctrl: sysctrl@1463000 { compatible = "zte,zx296718-sysctrl", "syscon"; reg = <0x1463000 0x1000>; @@ -445,6 +580,38 @@ #clock-cells = <1>; }; + i2s0: i2s@1482000 { + compatible = "zte,zx296718-i2s", "zte,zx296702-i2s"; + reg = <0x01482000 0x1000>; + clocks = <&audiocrm AUDIO_I2S0_WCLK>, + <&audiocrm AUDIO_I2S0_PCLK>; + clock-names = "wclk", "pclk"; + assigned-clocks = <&audiocrm I2S0_WCLK_MUX>; + assigned-clock-parents = <&topcrm AUDIO_99M>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma 22>, <&dma 23>; + dma-names = "tx", "rx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@1486000 { + compatible = "zte,zx296718-i2c"; + reg = <0x01486000 0x1000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&audiocrm AUDIO_I2C0_WCLK>; + clock-frequency = <1600000>; + status = "disabled"; + + aud96p22: codec@22 { + compatible = "zte,zx-aud96p22"; + #sound-dai-cells = <0>; + reg = <0x22>; + }; + }; + spdif0: spdif@1488000 { compatible = "zte,zx296702-spdif"; reg = <0x1488000 0x1000>; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6c7d147eed54..b4ca115b3be1 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -476,6 +476,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_MSM_GCC_8916=y CONFIG_MSM_GCC_8994=y CONFIG_MSM_MMCC_8996=y +CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_ARM_MHU=y CONFIG_PLATFORM_MHU=y diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h index 99fa69c9c3cf..9ef0797380cb 100644 --- a/arch/arm64/include/asm/atomic_lse.h +++ b/arch/arm64/include/asm/atomic_lse.h @@ -435,7 +435,7 @@ static inline long atomic64_dec_if_positive(atomic64_t *v) " sub x30, x30, %[ret]\n" " cbnz x30, 1b\n" "2:") - : [ret] "+&r" (x0), [v] "+Q" (v->counter) + : [ret] "+r" (x0), [v] "+Q" (v->counter) : : __LL_SC_CLOBBERS, "cc", "memory"); diff --git a/arch/arm64/include/asm/bug.h b/arch/arm64/include/asm/bug.h index 366448eb0fb7..a02a57186f56 100644 --- a/arch/arm64/include/asm/bug.h +++ b/arch/arm64/include/asm/bug.h @@ -36,7 +36,7 @@ #ifdef CONFIG_GENERIC_BUG #define __BUG_ENTRY(flags) \ - ".pushsection __bug_table,\"a\"\n\t" \ + ".pushsection __bug_table,\"aw\"\n\t" \ ".align 2\n\t" \ "0: .long 1f - 0b\n\t" \ _BUGVERBOSE_LOCATION(__FILE__, __LINE__) \ diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index 32f82723338a..ef39dcb9ca6a 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -64,8 +64,10 @@ * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. */ #define VA_BITS (CONFIG_ARM64_VA_BITS) -#define VA_START (UL(0xffffffffffffffff) << VA_BITS) -#define PAGE_OFFSET (UL(0xffffffffffffffff) << (VA_BITS - 1)) +#define VA_START (UL(0xffffffffffffffff) - \ + (UL(1) << VA_BITS) + 1) +#define PAGE_OFFSET (UL(0xffffffffffffffff) - \ + (UL(1) << (VA_BITS - 1)) + 1) #define KIMAGE_VADDR (MODULES_END) #define MODULES_END (MODULES_VADDR + MODULES_VSIZE) #define MODULES_VADDR (VA_START + KASAN_SHADOW_SIZE) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 16e44fa9b3b6..248339e4aaf5 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -492,7 +492,7 @@ asm( * the "%x0" template means XZR. */ #define write_sysreg(v, r) do { \ - u64 __val = (u64)v; \ + u64 __val = (u64)(v); \ asm volatile("msr " __stringify(r) ", %x0" \ : : "rZ" (__val)); \ } while (0) @@ -508,7 +508,7 @@ asm( }) #define write_sysreg_s(v, r) do { \ - u64 __val = (u64)v; \ + u64 __val = (u64)(v); \ asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ } while (0) diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 8f0a1de11e4a..fab46a0ea223 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -69,7 +69,7 @@ static inline void set_fs(mm_segment_t fs) */ #define __range_ok(addr, size) \ ({ \ - unsigned long __addr = (unsigned long __force)(addr); \ + unsigned long __addr = (unsigned long)(addr); \ unsigned long flag, roksum; \ __chk_user_ptr(addr); \ asm("adds %1, %1, %3; ccmp %1, %4, #2, cc; cset %0, ls" \ diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c index e137ceaf5016..d16978213c5b 100644 --- a/arch/arm64/kernel/cpu_ops.c +++ b/arch/arm64/kernel/cpu_ops.c @@ -82,8 +82,8 @@ static const char *__init cpu_read_enable_method(int cpu) * Don't warn spuriously. */ if (cpu != 0) - pr_err("%s: missing enable-method property\n", - dn->full_name); + pr_err("%pOF: missing enable-method property\n", + dn); } } else { enable_method = acpi_get_enable_method(cpu); diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 321119881abf..dc66e6ec3a99 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -469,7 +469,7 @@ static u64 __init of_get_cpu_mpidr(struct device_node *dn) */ cell = of_get_property(dn, "reg", NULL); if (!cell) { - pr_err("%s: missing reg property\n", dn->full_name); + pr_err("%pOF: missing reg property\n", dn); return INVALID_HWID; } @@ -478,7 +478,7 @@ static u64 __init of_get_cpu_mpidr(struct device_node *dn) * Non affinity bits must be set to 0 in the DT */ if (hwid & ~MPIDR_HWID_BITMASK) { - pr_err("%s: invalid reg property\n", dn->full_name); + pr_err("%pOF: invalid reg property\n", dn); return INVALID_HWID; } return hwid; @@ -627,8 +627,8 @@ static void __init of_parse_and_init_cpus(void) goto next; if (is_mpidr_duplicate(cpu_count, hwid)) { - pr_err("%s: duplicate cpu reg properties in the DT\n", - dn->full_name); + pr_err("%pOF: duplicate cpu reg properties in the DT\n", + dn); goto next; } @@ -640,8 +640,8 @@ static void __init of_parse_and_init_cpus(void) */ if (hwid == cpu_logical_map(0)) { if (bootcpu_valid) { - pr_err("%s: duplicate boot cpu reg property in DT\n", - dn->full_name); + pr_err("%pOF: duplicate boot cpu reg property in DT\n", + dn); goto next; } diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 79244c75eaec..8d48b233e6ce 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -45,7 +45,7 @@ static int __init get_cpu_for_node(struct device_node *node) } } - pr_crit("Unable to find CPU node for %s\n", cpu_node->full_name); + pr_crit("Unable to find CPU node for %pOF\n", cpu_node); of_node_put(cpu_node); return -1; @@ -71,8 +71,8 @@ static int __init parse_core(struct device_node *core, int cluster_id, cpu_topology[cpu].core_id = core_id; cpu_topology[cpu].thread_id = i; } else { - pr_err("%s: Can't get CPU for thread\n", - t->full_name); + pr_err("%pOF: Can't get CPU for thread\n", + t); of_node_put(t); return -EINVAL; } @@ -84,15 +84,15 @@ static int __init parse_core(struct device_node *core, int cluster_id, cpu = get_cpu_for_node(core); if (cpu >= 0) { if (!leaf) { - pr_err("%s: Core has both threads and CPU\n", - core->full_name); + pr_err("%pOF: Core has both threads and CPU\n", + core); return -EINVAL; } cpu_topology[cpu].cluster_id = cluster_id; cpu_topology[cpu].core_id = core_id; } else if (leaf) { - pr_err("%s: Can't get CPU for leaf core\n", core->full_name); + pr_err("%pOF: Can't get CPU for leaf core\n", core); return -EINVAL; } @@ -137,8 +137,8 @@ static int __init parse_cluster(struct device_node *cluster, int depth) has_cores = true; if (depth == 0) { - pr_err("%s: cpu-map children should be clusters\n", - c->full_name); + pr_err("%pOF: cpu-map children should be clusters\n", + c); of_node_put(c); return -EINVAL; } @@ -146,8 +146,8 @@ static int __init parse_cluster(struct device_node *cluster, int depth) if (leaf) { ret = parse_core(c, cluster_id, core_id++); } else { - pr_err("%s: Non-leaf cluster with core %s\n", - cluster->full_name, name); + pr_err("%pOF: Non-leaf cluster with core %s\n", + cluster, name); ret = -EINVAL; } @@ -159,7 +159,7 @@ static int __init parse_cluster(struct device_node *cluster, int depth) } while (c); if (leaf && !has_cores) - pr_warn("%s: empty cluster\n", cluster->full_name); + pr_warn("%pOF: empty cluster\n", cluster); if (leaf) cluster_id++; diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index c7c7088097be..8a62648848e5 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -274,10 +274,12 @@ static DEFINE_RAW_SPINLOCK(die_lock); void die(const char *str, struct pt_regs *regs, int err) { int ret; + unsigned long flags; + + raw_spin_lock_irqsave(&die_lock, flags); oops_enter(); - raw_spin_lock_irq(&die_lock); console_verbose(); bust_spinlocks(1); ret = __die(str, err, regs); @@ -287,13 +289,15 @@ void die(const char *str, struct pt_regs *regs, int err) bust_spinlocks(0); add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); - raw_spin_unlock_irq(&die_lock); oops_exit(); if (in_interrupt()) panic("Fatal exception in interrupt"); if (panic_on_oops) panic("Fatal exception"); + + raw_spin_unlock_irqrestore(&die_lock, flags); + if (ret != NOTIFY_STOP) do_exit(SIGSEGV); } @@ -519,7 +523,7 @@ static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) { int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; - pt_regs_write_reg(regs, rt, read_sysreg(cntfrq_el0)); + pt_regs_write_reg(regs, rt, arch_timer_get_rate()); regs->pc += 4; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 77862881ae86..2e070d3baf9f 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -764,7 +764,7 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, if (p->is_write) { if (r->CRm & 0x2) /* accessing PMOVSSET_EL0 */ - kvm_pmu_overflow_set(vcpu, p->regval & mask); + vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); else /* accessing PMOVSCLR_EL0 */ vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); diff --git a/arch/arm64/lib/copy_page.S b/arch/arm64/lib/copy_page.S index c3cd65e31814..076c43715e64 100644 --- a/arch/arm64/lib/copy_page.S +++ b/arch/arm64/lib/copy_page.S @@ -30,9 +30,10 @@ */ ENTRY(copy_page) alternative_if ARM64_HAS_NO_HW_PREFETCH - # Prefetch two cache lines ahead. - prfm pldl1strm, [x1, #128] - prfm pldl1strm, [x1, #256] + // Prefetch three cache lines ahead. + prfm pldl1strm, [x1, #128] + prfm pldl1strm, [x1, #256] + prfm pldl1strm, [x1, #384] alternative_else_nop_endif ldp x2, x3, [x1] @@ -50,7 +51,7 @@ alternative_else_nop_endif subs x18, x18, #128 alternative_if ARM64_HAS_NO_HW_PREFETCH - prfm pldl1strm, [x1, #384] + prfm pldl1strm, [x1, #384] alternative_else_nop_endif stnp x2, x3, [x0] diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index e90cd1db42a8..f27d4dd04384 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -329,7 +329,7 @@ static int __swiotlb_mmap(struct device *dev, vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot, is_device_dma_coherent(dev)); - if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) + if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) return ret; return __swiotlb_mmap_pfn(vma, pfn, size); @@ -706,7 +706,7 @@ static int __iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot, is_device_dma_coherent(dev)); - if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) + if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) return ret; if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) { diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index c7861c9864e6..2509e4fe6992 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -163,26 +163,27 @@ int ptep_set_access_flags(struct vm_area_struct *vma, /* only preserve the access flags and write permission */ pte_val(entry) &= PTE_AF | PTE_WRITE | PTE_DIRTY; - /* - * PTE_RDONLY is cleared by default in the asm below, so set it in - * back if necessary (read-only or clean PTE). - */ + /* set PTE_RDONLY if actual read-only or clean PTE */ if (!pte_write(entry) || !pte_sw_dirty(entry)) pte_val(entry) |= PTE_RDONLY; /* * Setting the flags must be done atomically to avoid racing with the - * hardware update of the access/dirty state. + * hardware update of the access/dirty state. The PTE_RDONLY bit must + * be set to the most permissive (lowest value) of *ptep and entry + * (calculated as: a & b == ~(~a | ~b)). */ + pte_val(entry) ^= PTE_RDONLY; asm volatile("// ptep_set_access_flags\n" " prfm pstl1strm, %2\n" "1: ldxr %0, %2\n" - " and %0, %0, %3 // clear PTE_RDONLY\n" + " eor %0, %0, %3 // negate PTE_RDONLY in *ptep\n" " orr %0, %0, %4 // set flags\n" + " eor %0, %0, %3 // negate final PTE_RDONLY\n" " stxr %w1, %0, %2\n" " cbnz %w1, 1b\n" : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) - : "L" (~PTE_RDONLY), "r" (pte_val(entry))); + : "L" (PTE_RDONLY), "r" (pte_val(entry))); flush_tlb_fix_spurious_fault(vma, address); return 1; diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 23c2d89a362e..f1eb15e0e864 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -496,7 +496,7 @@ void mark_rodata_ro(void) static void __init map_kernel_segment(pgd_t *pgd, void *va_start, void *va_end, pgprot_t prot, struct vm_struct *vma, - int flags) + int flags, unsigned long vm_flags) { phys_addr_t pa_start = __pa_symbol(va_start); unsigned long size = va_end - va_start; @@ -507,10 +507,13 @@ static void __init map_kernel_segment(pgd_t *pgd, void *va_start, void *va_end, __create_pgd_mapping(pgd, pa_start, (unsigned long)va_start, size, prot, early_pgtable_alloc, flags); + if (!(vm_flags & VM_NO_GUARD)) + size += PAGE_SIZE; + vma->addr = va_start; vma->phys_addr = pa_start; vma->size = size; - vma->flags = VM_MAP; + vma->flags = VM_MAP | vm_flags; vma->caller = __builtin_return_address(0); vm_area_add_early(vma); @@ -541,14 +544,15 @@ static void __init map_kernel(pgd_t *pgd) * Only rodata will be remapped with different permissions later on, * all other segments are allowed to use contiguous mappings. */ - map_kernel_segment(pgd, _text, _etext, text_prot, &vmlinux_text, 0); + map_kernel_segment(pgd, _text, _etext, text_prot, &vmlinux_text, 0, + VM_NO_GUARD); map_kernel_segment(pgd, __start_rodata, __inittext_begin, PAGE_KERNEL, - &vmlinux_rodata, NO_CONT_MAPPINGS); + &vmlinux_rodata, NO_CONT_MAPPINGS, VM_NO_GUARD); map_kernel_segment(pgd, __inittext_begin, __inittext_end, text_prot, - &vmlinux_inittext, 0); + &vmlinux_inittext, 0, VM_NO_GUARD); map_kernel_segment(pgd, __initdata_begin, __initdata_end, PAGE_KERNEL, - &vmlinux_initdata, 0); - map_kernel_segment(pgd, _data, _end, PAGE_KERNEL, &vmlinux_data, 0); + &vmlinux_initdata, 0, VM_NO_GUARD); + map_kernel_segment(pgd, _data, _end, PAGE_KERNEL, &vmlinux_data, 0, 0); if (!pgd_val(*pgd_offset_raw(pgd, FIXADDR_START))) { /* diff --git a/arch/arm64/mm/numa.c b/arch/arm64/mm/numa.c index b388a99fea7b..dad128ba98bf 100644 --- a/arch/arm64/mm/numa.c +++ b/arch/arm64/mm/numa.c @@ -208,8 +208,6 @@ int __init numa_add_memblk(int nid, u64 start, u64 end) } node_set(nid, numa_nodes_parsed); - pr_info("Adding memblock [0x%llx - 0x%llx] on node %d\n", - start, (end - 1), nid); return ret; } @@ -223,10 +221,7 @@ static void __init setup_node_data(int nid, u64 start_pfn, u64 end_pfn) void *nd; int tnid; - if (start_pfn < end_pfn) - pr_info("Initmem setup node %d [mem %#010Lx-%#010Lx]\n", nid, - start_pfn << PAGE_SHIFT, (end_pfn << PAGE_SHIFT) - 1); - else + if (start_pfn >= end_pfn) pr_info("Initmem setup node %d [<memory-less node>]\n", nid); nd_pa = memblock_alloc_try_nid(nd_size, SMP_CACHE_BYTES, nid); |