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-rw-r--r--arch/blackfin/include/asm/Kbuild4
-rw-r--r--arch/blackfin/include/asm/bfin_rotary.h74
-rw-r--r--arch/blackfin/include/asm/bfin_sdh.h119
-rw-r--r--arch/blackfin/include/asm/bitops.h2
-rw-r--r--arch/blackfin/include/asm/cache.h2
-rw-r--r--arch/blackfin/include/asm/cdef_LPBlackfin.h8
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h18
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h2
-rw-r--r--arch/blackfin/include/asm/dma.h1
-rw-r--r--arch/blackfin/include/asm/elf.h1
-rw-r--r--arch/blackfin/include/asm/ftrace.h16
-rw-r--r--arch/blackfin/include/asm/gpio.h111
-rw-r--r--arch/blackfin/include/asm/io.h8
-rw-r--r--arch/blackfin/include/asm/local64.h1
-rw-r--r--arch/blackfin/include/asm/mem_init.h18
-rw-r--r--arch/blackfin/include/asm/nand.h3
-rw-r--r--arch/blackfin/include/asm/portmux.h10
-rw-r--r--arch/blackfin/include/asm/scatterlist.h2
18 files changed, 305 insertions, 95 deletions
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index 09c31418cc08..d9eb29e2555c 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -1,4 +1,4 @@
include include/asm-generic/Kbuild.asm
-unifdef-y += bfin_sport.h
-unifdef-y += fixed_code.h
+header-y += bfin_sport.h
+header-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/bfin_rotary.h b/arch/blackfin/include/asm/bfin_rotary.h
index abdb2af52902..0b6910bdc57f 100644
--- a/arch/blackfin/include/asm/bfin_rotary.h
+++ b/arch/blackfin/include/asm/bfin_rotary.h
@@ -2,7 +2,7 @@
* board initialization should put one of these structures into platform_data
* and place the bfin-rotary onto platform_bus named "bfin-rotary".
*
- * Copyright 2008 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@@ -40,4 +40,76 @@ struct bfin_rotary_platform_data {
unsigned short debounce; /* 0..17 */
unsigned short mode;
};
+
+/* CNT_CONFIG bitmasks */
+#define CNTE (1 << 0) /* Counter Enable */
+#define DEBE (1 << 1) /* Debounce Enable */
+#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */
+#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */
+#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */
+#define CNTMODE_SHIFT 8
+#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
+#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */
+#define BNDMODE_SHIFT 12
+#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
+#define INPDIS (1 << 15) /* CUG and CDG Input Disable */
+
+#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */
+#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */
+#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */
+#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */
+#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */
+
+#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */
+#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */
+#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */
+#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */
+
+/* CNT_IMASK bitmasks */
+#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */
+#define UCIE (1 << 1) /* Up count Interrupt Enable */
+#define DCIE (1 << 2) /* Down count Interrupt Enable */
+#define MINCIE (1 << 3) /* Min Count Interrupt Enable */
+#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */
+#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */
+#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */
+#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */
+#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */
+#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */
+#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */
+
+/* CNT_STATUS bitmasks */
+#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */
+#define UCII (1 << 1) /* Up count Interrupt Identifier */
+#define DCII (1 << 2) /* Down count Interrupt Identifier */
+#define MINCII (1 << 3) /* Min Count Interrupt Identifier */
+#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */
+#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */
+#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */
+#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */
+#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */
+#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */
+#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */
+
+/* CNT_COMMAND bitmasks */
+#define W1LCNT 0xf /* Load Counter Register */
+#define W1LMIN 0xf0 /* Load Min Register */
+#define W1LMAX 0xf00 /* Load Max Register */
+#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */
+
+#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */
+#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */
+#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */
+
+#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */
+#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */
+#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */
+
+#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */
+#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */
+#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */
+
+/* CNT_DEBOUNCE bitmasks */
+#define DPRESCALE 0xf /* Load Counter Register */
+
#endif
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h
index d61d5497c590..6a4cfe2d3367 100644
--- a/arch/blackfin/include/asm/bfin_sdh.h
+++ b/arch/blackfin/include/asm/bfin_sdh.h
@@ -1,7 +1,7 @@
/*
- * bfin_sdh.h - Blackfin SDH definitions
+ * Blackfin Secure Digital Host (SDH) definitions
*
- * Copyright 2008 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@@ -9,6 +9,7 @@
#ifndef __BFIN_SDH_H__
#define __BFIN_SDH_H__
+/* Platform resources */
struct bfin_sd_host {
int dma_chan;
int irq_int0;
@@ -16,4 +17,118 @@ struct bfin_sd_host {
u16 pin_req[7];
};
+/* SDH_COMMAND bitmasks */
+#define CMD_IDX 0x3f /* Command Index */
+#define CMD_RSP (1 << 6) /* Response */
+#define CMD_L_RSP (1 << 7) /* Long Response */
+#define CMD_INT_E (1 << 8) /* Command Interrupt */
+#define CMD_PEND_E (1 << 9) /* Command Pending */
+#define CMD_E (1 << 10) /* Command Enable */
+
+/* SDH_PWR_CTL bitmasks */
+#define PWR_ON 0x3 /* Power On */
+#define SD_CMD_OD (1 << 6) /* Open Drain Output */
+#define ROD_CTL (1 << 7) /* Rod Control */
+
+/* SDH_CLK_CTL bitmasks */
+#define CLKDIV 0xff /* MC_CLK Divisor */
+#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
+#define PWR_SV_E (1 << 9) /* Power Save Enable */
+#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
+#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */
+
+/* SDH_RESP_CMD bitmasks */
+#define RESP_CMD 0x3f /* Response Command */
+
+/* SDH_DATA_CTL bitmasks */
+#define DTX_E (1 << 0) /* Data Transfer Enable */
+#define DTX_DIR (1 << 1) /* Data Transfer Direction */
+#define DTX_MODE (1 << 2) /* Data Transfer Mode */
+#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
+#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
+
+/* SDH_STATUS bitmasks */
+#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
+#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */
+#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */
+#define DAT_TIME_OUT (1 << 3) /* Data Time Out */
+#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */
+#define RX_OVERRUN (1 << 5) /* Receive Overrun */
+#define CMD_RESP_END (1 << 6) /* CMD Response End */
+#define CMD_SENT (1 << 7) /* CMD Sent */
+#define DAT_END (1 << 8) /* Data End */
+#define START_BIT_ERR (1 << 9) /* Start Bit Error */
+#define DAT_BLK_END (1 << 10) /* Data Block End */
+#define CMD_ACT (1 << 11) /* CMD Active */
+#define TX_ACT (1 << 12) /* Transmit Active */
+#define RX_ACT (1 << 13) /* Receive Active */
+#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */
+#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */
+#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */
+#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */
+#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */
+#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */
+#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */
+#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */
+
+/* SDH_STATUS_CLR bitmasks */
+#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */
+#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */
+#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */
+#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */
+#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */
+#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */
+#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */
+#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */
+#define DAT_END_STAT (1 << 8) /* Data End Status */
+#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
+#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */
+
+/* SDH_MASK0 bitmasks */
+#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */
+#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */
+#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */
+#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */
+#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */
+#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */
+#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */
+#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */
+#define DAT_END_MASK (1 << 8) /* Data End Mask */
+#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
+#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */
+#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */
+#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */
+#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */
+#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */
+#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */
+#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */
+#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */
+#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */
+#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */
+#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */
+#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */
+
+/* SDH_FIFO_CNT bitmasks */
+#define FIFO_COUNT 0x7fff /* FIFO Count */
+
+/* SDH_E_STATUS bitmasks */
+#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
+#define SD_CARD_DET (1 << 4) /* SD Card Detect */
+
+/* SDH_E_MASK bitmasks */
+#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
+#define SCD_MSK (1 << 6) /* Mask Card Detect */
+
+/* SDH_CFG bitmasks */
+#define CLKS_EN (1 << 0) /* Clocks Enable */
+#define SD4E (1 << 2) /* SDIO 4-Bit Enable */
+#define MWE (1 << 3) /* Moving Window Enable */
+#define SD_RST (1 << 4) /* SDMMC Reset */
+#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
+#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
+#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
+
+/* SDH_RD_WAIT_EN bitmasks */
+#define RWR (1 << 0) /* Read Wait Request */
+
#endif
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 605ba8e9b2e4..d5872cd967ab 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -119,7 +119,7 @@ static inline unsigned int hweight32(unsigned int w)
{
unsigned int res;
- __asm__ ("%0.l = ONES %0;"
+ __asm__ ("%0.l = ONES %1;"
"%0 = %0.l (Z);"
: "=d" (res) : "d" (w));
return res;
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index 93f6c634fdf4..bd0641a267f1 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -15,7 +15,7 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define SMP_CACHE_BYTES L1_CACHE_BYTES
-#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#ifdef CONFIG_SMP
#define __cacheline_aligned
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
index 8778e0f03730..6c39d94b44d0 100644
--- a/arch/blackfin/include/asm/cdef_LPBlackfin.h
+++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h
@@ -216,12 +216,16 @@
#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
#define bfin_read_EVT15() bfin_read32(EVT15)
#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
+#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
+#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val)
#define bfin_read_IMASK() bfin_read32(IMASK)
#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
#define bfin_read_IPEND() bfin_read32(IPEND)
#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
#define bfin_read_ILAT() bfin_read32(ILAT)
#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
+#define bfin_read_IPRIO() bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val)
/*Core Timer Registers*/
#define bfin_read_TCNTL() bfin_read32(TCNTL)
@@ -299,8 +303,4 @@
#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
-/*
-#define IPRIO 0xFFE02110
-*/
-
#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index f342ff0319df..e3f0f4c49819 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -50,6 +50,23 @@
#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
+#define bfin_read(addr) \
+({ \
+ sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
+ sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
+ sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
+ ({ BUG(); 0; }); \
+})
+#define bfin_write(addr, val) \
+({ \
+ switch (sizeof(*(addr))) { \
+ case 1: bfin_write8(addr, val); break; \
+ case 2: bfin_write16(addr, val); break; \
+ case 4: bfin_write32(addr, val); break; \
+ default: BUG(); \
+ } \
+})
+
#endif /* __ASSEMBLY__ */
/**************************************************
@@ -377,6 +394,7 @@
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
+#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index 212cb80fd74b..bbf461076a0a 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -21,8 +21,6 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#define dma_supported(d, m) (1)
-#define dma_get_cache_alignment() (32)
-#define dma_is_consistent(d, h) (1)
static inline int
dma_set_mask(struct device *dev, u64 dma_mask)
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index 2c09b1d50ec9..eedf3ca65ba2 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -276,6 +276,7 @@ static inline void clear_dma_irqstat(unsigned int channel)
}
void *dma_memcpy(void *dest, const void *src, size_t count);
+void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
void *safe_dma_memcpy(void *dest, const void *src, size_t count);
void blackfin_dma_early_init(void);
void early_dma_memcpy(void *dest, const void *src, size_t count);
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
index 117713adea7f..e6c6812a9abd 100644
--- a/arch/blackfin/include/asm/elf.h
+++ b/arch/blackfin/include/asm/elf.h
@@ -119,6 +119,7 @@ do { \
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
memcpy((char *) &pr_reg, (char *)regs, \
sizeof(struct pt_regs));
+#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. */
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h
index 4cfe2d9ba7e8..8a029505d7b7 100644
--- a/arch/blackfin/include/asm/ftrace.h
+++ b/arch/blackfin/include/asm/ftrace.h
@@ -12,6 +12,22 @@
#ifndef __ASSEMBLY__
+#ifdef CONFIG_DYNAMIC_FTRACE
+
+extern void _mcount(void);
+#define MCOUNT_ADDR ((unsigned long)_mcount)
+
+static inline unsigned long ftrace_call_adjust(unsigned long addr)
+{
+ return addr;
+}
+
+struct dyn_arch_ftrace {
+ /* No extra data needed for Blackfin */
+};
+
+#endif
+
#ifdef CONFIG_FRAME_POINTER
#include <linux/mm.h>
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 01b19d0cf509..1ef8417f5d27 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -7,63 +7,63 @@
#ifndef __ARCH_BLACKFIN_GPIO_H__
#define __ARCH_BLACKFIN_GPIO_H__
-#define gpio_bank(x) ((x) >> 4)
-#define gpio_bit(x) (1<<((x) & 0xF))
-#define gpio_sub_n(x) ((x) & 0xF)
+#define gpio_bank(x) ((x) >> 4)
+#define gpio_bit(x) (1<<((x) & 0xF))
+#define gpio_sub_n(x) ((x) & 0xF)
-#define GPIO_BANKSIZE 16
-#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
+#define GPIO_BANKSIZE 16
+#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
#include <mach/gpio.h>
-#define GPIO_0 0
-#define GPIO_1 1
-#define GPIO_2 2
-#define GPIO_3 3
-#define GPIO_4 4
-#define GPIO_5 5
-#define GPIO_6 6
-#define GPIO_7 7
-#define GPIO_8 8
-#define GPIO_9 9
-#define GPIO_10 10
-#define GPIO_11 11
-#define GPIO_12 12
-#define GPIO_13 13
-#define GPIO_14 14
-#define GPIO_15 15
-#define GPIO_16 16
-#define GPIO_17 17
-#define GPIO_18 18
-#define GPIO_19 19
-#define GPIO_20 20
-#define GPIO_21 21
-#define GPIO_22 22
-#define GPIO_23 23
-#define GPIO_24 24
-#define GPIO_25 25
-#define GPIO_26 26
-#define GPIO_27 27
-#define GPIO_28 28
-#define GPIO_29 29
-#define GPIO_30 30
-#define GPIO_31 31
-#define GPIO_32 32
-#define GPIO_33 33
-#define GPIO_34 34
-#define GPIO_35 35
-#define GPIO_36 36
-#define GPIO_37 37
-#define GPIO_38 38
-#define GPIO_39 39
-#define GPIO_40 40
-#define GPIO_41 41
-#define GPIO_42 42
-#define GPIO_43 43
-#define GPIO_44 44
-#define GPIO_45 45
-#define GPIO_46 46
-#define GPIO_47 47
+#define GPIO_0 0
+#define GPIO_1 1
+#define GPIO_2 2
+#define GPIO_3 3
+#define GPIO_4 4
+#define GPIO_5 5
+#define GPIO_6 6
+#define GPIO_7 7
+#define GPIO_8 8
+#define GPIO_9 9
+#define GPIO_10 10
+#define GPIO_11 11
+#define GPIO_12 12
+#define GPIO_13 13
+#define GPIO_14 14
+#define GPIO_15 15
+#define GPIO_16 16
+#define GPIO_17 17
+#define GPIO_18 18
+#define GPIO_19 19
+#define GPIO_20 20
+#define GPIO_21 21
+#define GPIO_22 22
+#define GPIO_23 23
+#define GPIO_24 24
+#define GPIO_25 25
+#define GPIO_26 26
+#define GPIO_27 27
+#define GPIO_28 28
+#define GPIO_29 29
+#define GPIO_30 30
+#define GPIO_31 31
+#define GPIO_32 32
+#define GPIO_33 33
+#define GPIO_34 34
+#define GPIO_35 35
+#define GPIO_36 36
+#define GPIO_37 37
+#define GPIO_38 38
+#define GPIO_39 39
+#define GPIO_40 40
+#define GPIO_41 41
+#define GPIO_42 42
+#define GPIO_43 43
+#define GPIO_44 44
+#define GPIO_45 45
+#define GPIO_46 46
+#define GPIO_47 47
#define PERIPHERAL_USAGE 1
#define GPIO_USAGE 0
@@ -279,6 +279,11 @@ static inline int gpio_direction_output(unsigned gpio, int value)
return bfin_gpio_direction_output(gpio, value);
}
+static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
+{
+ return -EINVAL;
+}
+
static inline int gpio_get_value(unsigned gpio)
{
return bfin_gpio_get_value(gpio);
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 29e55b9d88bc..234fbac17ec1 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -124,7 +124,13 @@ static inline unsigned int readl(const volatile void __iomem *addr)
#define iowrite16(val, x) writew(val, x)
#define iowrite32(val, x) writel(val, x)
-#define mmiowb() wmb()
+/**
+ * I/O write barrier
+ *
+ * Ensure ordering of I/O space writes. This will make sure that writes
+ * following the barrier will arrive after all previous writes.
+ */
+#define mmiowb() do { SSYNC(); wmb(); } while (0)
#define IO_SPACE_LIMIT 0xffffffff
diff --git a/arch/blackfin/include/asm/local64.h b/arch/blackfin/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/blackfin/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 7c8fe834ff22..237579935e29 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -10,7 +10,6 @@
#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
- defined(CONFIG_MEM_GENERIC_BOARD) || \
defined(CONFIG_MEM_MT48LC32M8A2_75) || \
defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
@@ -178,7 +177,6 @@
#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
- defined(CONFIG_MEM_GENERIC_BOARD) || \
defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC32M8A2_75)
@@ -248,22 +246,6 @@
#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
#endif
-#if defined(CONFIG_MEM_GENERIC_BOARD)
-#define DDR_SIZE DEVSZ_512
-#define DDR_WIDTH DEVWD_16
-#define DDR_MAX_tCK 13
-
-#define DDR_tRCD DDR_TRCD(3)
-#define DDR_tWTR DDR_TWTR(2)
-#define DDR_tWR DDR_TWR(2)
-#define DDR_tMRD DDR_TMRD(2)
-#define DDR_tRP DDR_TRP(3)
-#define DDR_tRAS DDR_TRAS(7)
-#define DDR_tRC DDR_TRC(10)
-#define DDR_tRFC DDR_TRFC(12)
-#define DDR_tREFI DDR_TREFI(1288)
-#endif
-
#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
#elif(CONFIG_SCLK_HZ <= 133333333)
diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h
index 3a1e79dfc8d9..256c50d8d465 100644
--- a/arch/blackfin/include/asm/nand.h
+++ b/arch/blackfin/include/asm/nand.h
@@ -15,8 +15,6 @@
* partitions = mtd partition list
*/
-#define NFC_PG_SIZE_256 0
-#define NFC_PG_SIZE_512 1
#define NFC_PG_SIZE_OFFSET 9
#define NFC_NWIDTH_8 0
@@ -30,7 +28,6 @@
struct bf5xx_nand_platform {
/* NAND chip information */
- unsigned short page_size;
unsigned short data_width;
/* RD/WR strobe delay timing information, all times in SCLK cycles */
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
index edd8ef3a3788..9b1e2c37b324 100644
--- a/arch/blackfin/include/asm/portmux.h
+++ b/arch/blackfin/include/asm/portmux.h
@@ -1,9 +1,9 @@
/*
* Common header file for Blackfin family of processors
*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
+ * Copyright 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
*/
#ifndef _PORTMUX_H_
@@ -1042,8 +1042,8 @@ void peripheral_free_list(const unsigned short per[]);
#define P_NOR_CLK P_UNDEF
#endif
-#ifndef P_TMRCLK
-#define P_TMRCLK P_UNDEF
+#ifndef P_TMRCLK
+#define P_TMRCLK P_UNDEF
#endif
#ifndef P_AMC_ARDY_NOR_WAIT
diff --git a/arch/blackfin/include/asm/scatterlist.h b/arch/blackfin/include/asm/scatterlist.h
index 64d41d34ab0b..d177a1588958 100644
--- a/arch/blackfin/include/asm/scatterlist.h
+++ b/arch/blackfin/include/asm/scatterlist.h
@@ -3,6 +3,4 @@
#include <asm-generic/scatterlist.h>
-#define ISA_DMA_THRESHOLD (0xffffffff)
-
#endif /* !(_BLACKFIN_SCATTERLIST_H) */
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.