diff options
Diffstat (limited to 'arch/blackfin/mach-common')
| -rw-r--r-- | arch/blackfin/mach-common/arch_checks.c | 16 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/cache.S | 15 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/dpmc_modes.S | 24 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/pm.c | 17 |
4 files changed, 22 insertions, 50 deletions
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index f2ca211a76a0..bceb98126c21 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c @@ -1,7 +1,7 @@ /* * Do some checking to make sure things are OK * - * Copyright 2007-2009 Analog Devices Inc. + * Copyright 2007-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -47,18 +47,20 @@ # error "The kernel load address is too high; keep it below 10meg for safety" #endif +#if ANOMALY_05000263 && defined(CONFIG_MPU) +# error the MPU will not function safely while Anomaly 05000263 applies +#endif + #if ANOMALY_05000448 # error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. #endif /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ #if ANOMALY_05000220 && \ - ((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \ - (!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK))) -# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. + (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)) +# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory" #endif -#if ANOMALY_05000475 && \ - (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)) -# error "Anomaly 475 does not allow you to use Write Back cache with L2 or External Memory" +#if ANOMALY_05000491 && !defined(CONFIG_CACHE_FLUSH_L1) +# error You need IFLUSH in L1 inst while Anomaly 05000491 applies #endif diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index ea540318a228..790c767ca95a 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -11,7 +11,11 @@ #include <asm/cache.h> #include <asm/page.h> +#ifdef CONFIG_CACHE_FLUSH_L1 +.section .l1.text +#else .text +#endif /* 05000443 - IFLUSH cannot be last instruction in hardware loop */ #if ANOMALY_05000443 @@ -64,17 +68,6 @@ /* Invalidate all instruction cache lines assocoiated with this memory area */ ENTRY(_blackfin_icache_flush_range) -/* - * Walkaround to avoid loading wrong instruction after invalidating icache - * and following sequence is met. - * - * 1) One instruction address is cached in the instruction cache. - * 2) This instruction in SDRAM is changed. - * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range(). - * 4) This instruction is executed again, but the old one is loaded. - */ - P0 = R0; - IFLUSH[P0]; do_flush IFLUSH ENDPROC(_blackfin_icache_flush_range) diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S index b03716896051..5969d86836a5 100644 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ b/arch/blackfin/mach-common/dpmc_modes.S @@ -17,9 +17,6 @@ ENTRY(_sleep_mode) call _set_sic_iwr; - R0 = 0xFFFF (Z); - call _set_rtc_istat; - P0.H = hi(PLL_CTL); P0.L = lo(PLL_CTL); R1 = W[P0](z); @@ -65,9 +62,6 @@ ENTRY(_hibernate_mode) call _set_dram_srfs; SSYNC; - R0 = 0xFFFF (Z); - call _set_rtc_istat; - P0.H = hi(VR_CTL); P0.L = lo(VR_CTL); @@ -95,9 +89,6 @@ ENTRY(_sleep_deeper) call _set_sic_iwr; call _set_dram_srfs; /* Set SDRAM Self Refresh */ - /* Clear all the interrupts,bits sticky */ - R0 = 0xFFFF (Z); - call _set_rtc_istat; P0.H = hi(PLL_DIV); P0.L = lo(PLL_DIV); R6 = W[P0](z); @@ -269,21 +260,6 @@ ENTRY(_set_sic_iwr) RTS; ENDPROC(_set_sic_iwr) -ENTRY(_set_rtc_istat) -#ifndef CONFIG_BF561 - P0.H = hi(RTC_ISTAT); - P0.L = lo(RTC_ISTAT); - w[P0] = R0.L; - SSYNC; -#elif (ANOMALY_05000371) - nop; - nop; - nop; - nop; -#endif - RTS; -ENDPROC(_set_rtc_istat) - ENTRY(_test_pll_locked) P0.H = hi(PLL_STAT); P0.L = lo(PLL_STAT); diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index ea7f95f6bb4c..09c1fb410748 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -61,10 +61,11 @@ void bfin_pm_suspend_standby_enter(void) int bf53x_suspend_l1_mem(unsigned char *memptr) { - dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH); - dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START, - L1_DATA_A_LENGTH); - dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH, + dma_memcpy_nocache(memptr, (const void *) L1_CODE_START, + L1_CODE_LENGTH); + dma_memcpy_nocache(memptr + L1_CODE_LENGTH, + (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH); + dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH, (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH); memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START, @@ -75,10 +76,10 @@ int bf53x_suspend_l1_mem(unsigned char *memptr) int bf53x_resume_l1_mem(unsigned char *memptr) { - dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH); - dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH, + dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH); + dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH, L1_DATA_A_LENGTH); - dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH + + dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH, L1_DATA_B_LENGTH); memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH); @@ -167,7 +168,7 @@ int bfin_pm_suspend_mem_enter(void) _disable_icplb(); bf53x_suspend_l1_mem(memptr); - do_hibernate(wakeup | vr_wakeup); /* Goodbye */ + do_hibernate(wakeup | vr_wakeup); /* See you later! */ bf53x_resume_l1_mem(memptr); |