diff options
Diffstat (limited to 'arch/mips/boot/dts')
-rw-r--r-- | arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts | 14 | ||||
-rw-r--r-- | arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts | 6 | ||||
-rw-r--r-- | arch/mips/boot/dts/ingenic/ci20.dts | 8 | ||||
-rw-r--r-- | arch/mips/boot/dts/ingenic/jz4740.dtsi | 2 | ||||
-rw-r--r-- | arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 8 |
5 files changed, 29 insertions, 9 deletions
diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts index 0fa3dd1819ff..dda0559cef50 100644 --- a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts +++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts @@ -180,14 +180,28 @@ ethernet@0 { phy-handle = <&phy2>; cavium,alt-phy-handle = <&phy100>; + rx-delay = <0>; + tx-delay = <0>; + fixed-link { + speed = <1000>; + full-duplex; + }; }; ethernet@1 { phy-handle = <&phy3>; cavium,alt-phy-handle = <&phy101>; + rx-delay = <0>; + tx-delay = <0>; + fixed-link { + speed = <1000>; + full-duplex; + }; }; ethernet@2 { phy-handle = <&phy4>; cavium,alt-phy-handle = <&phy102>; + rx-delay = <0>; + tx-delay = <0>; }; ethernet@3 { compatible = "cavium,octeon-3860-pip-port"; diff --git a/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts b/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts index 243e5dc444fb..962f37fbc7db 100644 --- a/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts +++ b/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts @@ -33,12 +33,18 @@ interface@0 { ethernet@0 { phy-handle = <&phy7>; + rx-delay = <0>; + tx-delay = <0x10>; }; ethernet@1 { phy-handle = <&phy6>; + rx-delay = <0>; + tx-delay = <0x10>; }; ethernet@2 { phy-handle = <&phy5>; + rx-delay = <0>; + tx-delay = <0x10>; }; }; }; diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 50cff3cbcc6d..4f7b1fa31cf5 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -76,7 +76,7 @@ status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&pins_uart2>; + pinctrl-0 = <&pins_uart3>; }; &uart4 { @@ -196,9 +196,9 @@ bias-disable; }; - pins_uart2: uart2 { - function = "uart2"; - groups = "uart2-data", "uart2-hwflow"; + pins_uart3: uart3 { + function = "uart3"; + groups = "uart3-data", "uart3-hwflow"; bias-disable; }; diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi index 6fb16fd24035..2beb78a62b7d 100644 --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi @@ -161,7 +161,7 @@ #dma-cells = <2>; interrupt-parent = <&intc>; - interrupts = <29>; + interrupts = <20>; clocks = <&cgu JZ4740_CLK_DMA>; diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts index 2152b7ba65fb..cc8dbea0911f 100644 --- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts +++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts @@ -90,11 +90,11 @@ interrupts = <0>; }; - axi_i2c: i2c@10A00000 { + axi_i2c: i2c@10a00000 { compatible = "xlnx,xps-iic-2.00.a"; interrupt-parent = <&axi_intc>; interrupts = <4>; - reg = < 0x10A00000 0x10000 >; + reg = < 0x10a00000 0x10000 >; clocks = <&ext>; xlnx,clk-freq = <0x5f5e100>; xlnx,family = "Artix7"; @@ -106,9 +106,9 @@ #address-cells = <1>; #size-cells = <0>; - ad7420@4B { + ad7420@4b { compatible = "adi,adt7420"; - reg = <0x4B>; + reg = <0x4b>; }; } ; }; |