diff options
Diffstat (limited to 'arch/mips/cavium-octeon')
| -rw-r--r-- | arch/mips/cavium-octeon/dma-octeon.c | 3 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper-board.c | 86 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper.c | 39 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/oct_ilm.c | 32 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/octeon-platform.c | 64 |
5 files changed, 78 insertions, 146 deletions
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index e8eb60ed99f2..11d5a4e90736 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -245,6 +245,9 @@ void __init plat_swiotlb_setup(void) swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT; octeon_swiotlb = memblock_alloc_low(swiotlbsize, PAGE_SIZE); + if (!octeon_swiotlb) + panic("%s: Failed to allocate %zu bytes align=%lx\n", + __func__, swiotlbsize, PAGE_SIZE); if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM) panic("Cannot allocate SWIOTLB buffer"); diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c index ab8362e04461..2e2d45bc850d 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c @@ -31,6 +31,7 @@ * network ports from the rest of the cvmx-helper files. */ +#include <linux/bug.h> #include <asm/octeon/octeon.h> #include <asm/octeon/cvmx-bootinfo.h> @@ -210,56 +211,18 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) { cvmx_helper_link_info_t result; + WARN(!octeon_is_simulation(), + "Using deprecated link status - please update your DT"); + /* Unless we fix it later, all links are defaulted to down */ result.u64 = 0; - /* - * This switch statement should handle all ports that either don't use - * Marvell PHYS, or don't support in-band status. - */ - switch (cvmx_sysinfo_get()->board_type) { - case CVMX_BOARD_TYPE_SIM: + if (octeon_is_simulation()) { /* The simulator gives you a simulated 1Gbps full duplex link */ result.s.link_up = 1; result.s.full_duplex = 1; result.s.speed = 1000; return result; - case CVMX_BOARD_TYPE_EBH3100: - case CVMX_BOARD_TYPE_CN3010_EVB_HS5: - case CVMX_BOARD_TYPE_CN3005_EVB_HS5: - case CVMX_BOARD_TYPE_CN3020_EVB_HS5: - /* Port 1 on these boards is always Gigabit */ - if (ipd_port == 1) { - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - return result; - } - /* Fall through to the generic code below */ - break; - case CVMX_BOARD_TYPE_CUST_NB5: - /* Port 1 on these boards is always Gigabit */ - if (ipd_port == 1) { - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - return result; - } - break; - case CVMX_BOARD_TYPE_BBGW_REF: - /* Port 1 on these boards is always Gigabit */ - if (ipd_port == 2) { - /* Port 2 is not hooked up */ - result.u64 = 0; - return result; - } else { - /* Ports 0 and 1 connect to the switch */ - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - return result; - } - break; } if (OCTEON_IS_MODEL(OCTEON_CN3XXX) @@ -358,45 +321,6 @@ int __cvmx_helper_board_interface_probe(int interface, int supported_ports) } /** - * Enable packet input/output from the hardware. This function is - * called after by cvmx_helper_packet_hardware_enable() to - * perform board specific initialization. For most boards - * nothing is needed. - * - * @interface: Interface to enable - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_board_hardware_enable(int interface) -{ - if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) { - if (interface == 0) { - /* Different config for switch port */ - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); - /* - * Boards with gigabit WAN ports need a - * different setting that is compatible with - * 100 Mbit settings - */ - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), - 0xc); - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), - 0xc); - } - } else if (cvmx_sysinfo_get()->board_type == - CVMX_BOARD_TYPE_UBNT_E100) { - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0); - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10); - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10); - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0); - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10); - } - return 0; -} - -/** * Get the clock type used for the USB block based on board type. * Used by the USB code for auto configuration of clock type. * diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c index 38e0444e57e8..de391541d6f7 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -30,6 +30,7 @@ * Helper functions for common, but complicated tasks. * */ +#include <linux/bug.h> #include <asm/octeon/octeon.h> #include <asm/octeon/cvmx-config.h> @@ -43,7 +44,6 @@ #include <asm/octeon/cvmx-helper-board.h> #include <asm/octeon/cvmx-pip-defs.h> -#include <asm/octeon/cvmx-smix-defs.h> #include <asm/octeon/cvmx-asxx-defs.h> /* Port count per interface */ @@ -317,22 +317,6 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) return CVMX_HELPER_INTERFACE_MODE_DISABLED; } - if (interface == 0 - && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5 - && cvmx_sysinfo_get()->board_rev_major == 1) { - /* - * Lie about interface type of CN3005 board. This - * board has a switch on port 1 like the other - * evaluation boards, but it is connected over RGMII - * instead of GMII. Report GMII mode so that the - * speed is forced to 1 Gbit full duplex. Other than - * some initial configuration (which does not use the - * output of this function) there is no difference in - * setup between GMII and RGMII modes. - */ - return CVMX_HELPER_INTERFACE_MODE_GMII; - } - /* Interface 1 is always disabled on CN31XX and CN30XX */ if ((interface == 1) && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) @@ -778,7 +762,6 @@ static int __cvmx_helper_packet_hardware_enable(int interface) result = __cvmx_helper_loop_enable(interface); break; } - result |= __cvmx_helper_board_hardware_enable(interface); return result; } @@ -1026,7 +1009,6 @@ int cvmx_helper_initialize_packet_io_global(void) int result = 0; int interface; union cvmx_l2c_cfg l2c_cfg; - union cvmx_smix_en smix_en; const int num_interfaces = cvmx_helper_get_number_of_interfaces(); /* @@ -1046,24 +1028,6 @@ int cvmx_helper_initialize_packet_io_global(void) l2c_cfg.s.rfb_arb_mode = 0; cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64); - /* Make sure SMI/MDIO is enabled so we can query PHYs */ - smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0)); - if (!smix_en.s.en) { - smix_en.s.en = 1; - cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64); - } - - /* Newer chips actually have two SMI/MDIO interfaces */ - if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && - !OCTEON_IS_MODEL(OCTEON_CN58XX) && - !OCTEON_IS_MODEL(OCTEON_CN50XX)) { - smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1)); - if (!smix_en.s.en) { - smix_en.s.en = 1; - cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64); - } - } - cvmx_pko_initialize_global(); for (interface = 0; interface < num_interfaces; interface++) { result |= cvmx_helper_interface_probe(interface); @@ -1136,6 +1100,7 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port) if (index == 0) result = __cvmx_helper_rgmii_link_get(ipd_port); else { + WARN(1, "Using deprecated link status - please update your DT"); result.s.full_duplex = 1; result.s.link_up = 1; result.s.speed = 1000; diff --git a/arch/mips/cavium-octeon/oct_ilm.c b/arch/mips/cavium-octeon/oct_ilm.c index 2d68a39f1443..13f6c7716b1e 100644 --- a/arch/mips/cavium-octeon/oct_ilm.c +++ b/arch/mips/cavium-octeon/oct_ilm.c @@ -63,31 +63,11 @@ static int reset_statistics(void *data, u64 value) DEFINE_SIMPLE_ATTRIBUTE(reset_statistics_ops, NULL, reset_statistics, "%llu\n"); -static int init_debufs(void) +static void init_debugfs(void) { - struct dentry *show_dentry; dir = debugfs_create_dir("oct_ilm", 0); - if (!dir) { - pr_err("oct_ilm: failed to create debugfs entry oct_ilm\n"); - return -1; - } - - show_dentry = debugfs_create_file("statistics", 0222, dir, NULL, - &oct_ilm_ops); - if (!show_dentry) { - pr_err("oct_ilm: failed to create debugfs entry oct_ilm/statistics\n"); - return -1; - } - - show_dentry = debugfs_create_file("reset", 0222, dir, NULL, - &reset_statistics_ops); - if (!show_dentry) { - pr_err("oct_ilm: failed to create debugfs entry oct_ilm/reset\n"); - return -1; - } - - return 0; - + debugfs_create_file("statistics", 0222, dir, NULL, &oct_ilm_ops); + debugfs_create_file("reset", 0222, dir, NULL, &reset_statistics_ops); } static void init_latency_info(struct latency_info *li, int startup) @@ -169,11 +149,7 @@ static __init int oct_ilm_module_init(void) int rc; int irq = OCTEON_IRQ_TIMER0 + TIMER_NUM; - rc = init_debufs(); - if (rc) { - WARN(1, "Could not create debugfs entries"); - return rc; - } + init_debugfs(); rc = request_irq(irq, cvm_oct_ciu_timer_interrupt, IRQF_NO_THREAD, "oct_ilm", 0); diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 1f9ba60f7375..51685f893eab 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -458,6 +458,23 @@ static bool __init octeon_has_88e1145(void) !OCTEON_IS_MODEL(OCTEON_CN56XX); } +static bool __init octeon_has_fixed_link(int ipd_port) +{ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: + case CVMX_BOARD_TYPE_CN3010_EVB_HS5: + case CVMX_BOARD_TYPE_CN3020_EVB_HS5: + case CVMX_BOARD_TYPE_CUST_NB5: + case CVMX_BOARD_TYPE_EBH3100: + /* Port 1 on these boards is always gigabit. */ + return ipd_port == 1; + case CVMX_BOARD_TYPE_BBGW_REF: + /* Ports 0 and 1 connect to the switch. */ + return ipd_port == 0 || ipd_port == 1; + } + return false; +} + static void __init octeon_fdt_set_phy(int eth, int phy_addr) { const __be32 *phy_handle; @@ -586,12 +603,52 @@ static void __init octeon_fdt_rm_ethernet(int node) fdt_nop_node(initial_boot_params, node); } +static void __init _octeon_rx_tx_delay(int eth, int rx_delay, int tx_delay) +{ + fdt_setprop_inplace_cell(initial_boot_params, eth, "rx-delay", + rx_delay); + fdt_setprop_inplace_cell(initial_boot_params, eth, "tx-delay", + tx_delay); +} + +static void __init octeon_rx_tx_delay(int eth, int iface, int port) +{ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: + if (iface == 0) { + if (port == 0) { + /* + * Boards with gigabit WAN ports need a + * different setting that is compatible with + * 100 Mbit settings + */ + _octeon_rx_tx_delay(eth, 0xc, 0x0c); + return; + } else if (port == 1) { + /* Different config for switch port. */ + _octeon_rx_tx_delay(eth, 0x0, 0x0); + return; + } + } + break; + case CVMX_BOARD_TYPE_UBNT_E100: + if (iface == 0 && port <= 2) { + _octeon_rx_tx_delay(eth, 0x0, 0x10); + return; + } + break; + } + fdt_nop_property(initial_boot_params, eth, "rx-delay"); + fdt_nop_property(initial_boot_params, eth, "tx-delay"); +} + static void __init octeon_fdt_pip_port(int iface, int i, int p, int max) { char name_buffer[20]; int eth; int phy_addr; int ipd_port; + int fixed_link; snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); @@ -609,6 +666,13 @@ static void __init octeon_fdt_pip_port(int iface, int i, int p, int max) phy_addr = cvmx_helper_board_get_mii_address(ipd_port); octeon_fdt_set_phy(eth, phy_addr); + + fixed_link = fdt_subnode_offset(initial_boot_params, eth, "fixed-link"); + if (fixed_link < 0) + WARN_ON(octeon_has_fixed_link(ipd_port)); + else if (!octeon_has_fixed_link(ipd_port)) + fdt_nop_node(initial_boot_params, fixed_link); + octeon_rx_tx_delay(eth, i, p); } static void __init octeon_fdt_pip_iface(int pip, int idx) |