diff options
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-gpio-defs.h')
| -rw-r--r-- | arch/mips/include/asm/octeon/cvmx-gpio-defs.h | 74 |
1 files changed, 50 insertions, 24 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h index 5fdd6ba48a05..395564e8d1f0 100644 --- a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,29 +28,22 @@ #ifndef __CVMX_GPIO_DEFS_H__ #define __CVMX_GPIO_DEFS_H__ -#define CVMX_GPIO_BIT_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8)) -#define CVMX_GPIO_BOOT_ENA \ - CVMX_ADD_IO_SEG(0x00010700000008A8ull) -#define CVMX_GPIO_CLK_GENX(offset) \ - CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8)) -#define CVMX_GPIO_DBG_ENA \ - CVMX_ADD_IO_SEG(0x00010700000008A0ull) -#define CVMX_GPIO_INT_CLR \ - CVMX_ADD_IO_SEG(0x0001070000000898ull) -#define CVMX_GPIO_RX_DAT \ - CVMX_ADD_IO_SEG(0x0001070000000880ull) -#define CVMX_GPIO_TX_CLR \ - CVMX_ADD_IO_SEG(0x0001070000000890ull) -#define CVMX_GPIO_TX_SET \ - CVMX_ADD_IO_SEG(0x0001070000000888ull) -#define CVMX_GPIO_XBIT_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16) +#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8) +#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull)) +#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8) +#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8) +#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) +#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull)) +#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull)) +#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull)) +#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull)) +#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16) union cvmx_gpio_bit_cfgx { uint64_t u64; struct cvmx_gpio_bit_cfgx_s { - uint64_t reserved_15_63:49; + uint64_t reserved_17_63:47; + uint64_t synce_sel:2; uint64_t clk_gen:1; uint64_t clk_sel:2; uint64_t fil_sel:4; @@ -73,12 +66,24 @@ union cvmx_gpio_bit_cfgx { struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; - struct cvmx_gpio_bit_cfgx_s cn52xx; - struct cvmx_gpio_bit_cfgx_s cn52xxp1; - struct cvmx_gpio_bit_cfgx_s cn56xx; - struct cvmx_gpio_bit_cfgx_s cn56xxp1; + struct cvmx_gpio_bit_cfgx_cn52xx { + uint64_t reserved_15_63:49; + uint64_t clk_gen:1; + uint64_t clk_sel:2; + uint64_t fil_sel:4; + uint64_t fil_cnt:4; + uint64_t int_type:1; + uint64_t int_en:1; + uint64_t rx_xor:1; + uint64_t tx_oe:1; + } cn52xx; + struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1; + struct cvmx_gpio_bit_cfgx_cn52xx cn56xx; + struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1; struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; + struct cvmx_gpio_bit_cfgx_s cn63xx; + struct cvmx_gpio_bit_cfgx_s cn63xxp1; }; union cvmx_gpio_boot_ena { @@ -103,6 +108,19 @@ union cvmx_gpio_clk_genx { struct cvmx_gpio_clk_genx_s cn52xxp1; struct cvmx_gpio_clk_genx_s cn56xx; struct cvmx_gpio_clk_genx_s cn56xxp1; + struct cvmx_gpio_clk_genx_s cn63xx; + struct cvmx_gpio_clk_genx_s cn63xxp1; +}; + +union cvmx_gpio_clk_qlmx { + uint64_t u64; + struct cvmx_gpio_clk_qlmx_s { + uint64_t reserved_3_63:61; + uint64_t div:1; + uint64_t lane_sel:2; + } s; + struct cvmx_gpio_clk_qlmx_s cn63xx; + struct cvmx_gpio_clk_qlmx_s cn63xxp1; }; union cvmx_gpio_dbg_ena { @@ -133,6 +151,8 @@ union cvmx_gpio_int_clr { struct cvmx_gpio_int_clr_s cn56xxp1; struct cvmx_gpio_int_clr_s cn58xx; struct cvmx_gpio_int_clr_s cn58xxp1; + struct cvmx_gpio_int_clr_s cn63xx; + struct cvmx_gpio_int_clr_s cn63xxp1; }; union cvmx_gpio_rx_dat { @@ -155,6 +175,8 @@ union cvmx_gpio_rx_dat { struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; struct cvmx_gpio_rx_dat_cn38xx cn58xx; struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; + struct cvmx_gpio_rx_dat_cn38xx cn63xx; + struct cvmx_gpio_rx_dat_cn38xx cn63xxp1; }; union cvmx_gpio_tx_clr { @@ -177,6 +199,8 @@ union cvmx_gpio_tx_clr { struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; struct cvmx_gpio_tx_clr_cn38xx cn58xx; struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; + struct cvmx_gpio_tx_clr_cn38xx cn63xx; + struct cvmx_gpio_tx_clr_cn38xx cn63xxp1; }; union cvmx_gpio_tx_set { @@ -199,6 +223,8 @@ union cvmx_gpio_tx_set { struct cvmx_gpio_tx_set_cn38xx cn56xxp1; struct cvmx_gpio_tx_set_cn38xx cn58xx; struct cvmx_gpio_tx_set_cn38xx cn58xxp1; + struct cvmx_gpio_tx_set_cn38xx cn63xx; + struct cvmx_gpio_tx_set_cn38xx cn63xxp1; }; union cvmx_gpio_xbit_cfgx { |