diff options
Diffstat (limited to 'arch/mips/include/asm/sibyte/bcm1480_scd.h')
| -rw-r--r-- | arch/mips/include/asm/sibyte/bcm1480_scd.h | 276 |
1 files changed, 138 insertions, 138 deletions
diff --git a/arch/mips/include/asm/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h index 2af3706b9648..8a1e2b05a626 100644 --- a/arch/mips/include/asm/sibyte/bcm1480_scd.h +++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h @@ -1,7 +1,7 @@ /* ********************************************************************* * BCM1280/BCM1400 Board Support Package * - * SCD Constants and Macros File: bcm1480_scd.h + * SCD Constants and Macros File: bcm1480_scd.h * * This module contains constants and macros useful for * manipulating the System Control and Debug module. @@ -74,11 +74,11 @@ * New part definitions */ -#define K_SYS_PART_BCM1480 0x1406 -#define K_SYS_PART_BCM1280 0x1206 -#define K_SYS_PART_BCM1455 0x1407 -#define K_SYS_PART_BCM1255 0x1257 -#define K_SYS_PART_BCM1158 0x1156 +#define K_SYS_PART_BCM1480 0x1406 +#define K_SYS_PART_BCM1280 0x1206 +#define K_SYS_PART_BCM1455 0x1407 +#define K_SYS_PART_BCM1255 0x1257 +#define K_SYS_PART_BCM1158 0x1156 /* * Manufacturing Information Register (Table 14) @@ -91,73 +91,73 @@ * Entire register is different from 1250, all new constants below */ -#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) -#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) -#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) -#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) -#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) -#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) - -#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) -#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) -#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) -#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) - -#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) -#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) -#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) -#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) - -#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) -#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) - -#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) -#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) -#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) -#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) -#define K_BCM1480_SYS_BOOT_MODE_ROM32 0 -#define K_BCM1480_SYS_BOOT_MODE_ROM8 1 +#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) +#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) +#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) +#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) +#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) +#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) + +#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) +#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) +#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) +#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) + +#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) +#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) +#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) +#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) + +#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) +#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) + +#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) +#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) +#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) +#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) +#define K_BCM1480_SYS_BOOT_MODE_ROM32 0 +#define K_BCM1480_SYS_BOOT_MODE_ROM8 1 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 -#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) - -#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) -#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) -#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) -#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) -#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) -#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) - -#define S_BCM1480_SYS_CONFIG 26 -#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) -#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) -#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) - -#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) - -#define S_BCM1480_SYS_NODEID 47 -#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) -#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) -#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) - -#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) -#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) -#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) -#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) -#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) -#define S_BCM1480_SYS_DISABLECPU0 56 -#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) -#define S_BCM1480_SYS_DISABLECPU1 57 -#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) -#define S_BCM1480_SYS_DISABLECPU2 58 -#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) -#define S_BCM1480_SYS_DISABLECPU3 59 -#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) - -#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) -#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) -#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) -#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) +#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) + +#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) +#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) +#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) +#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) +#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) +#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) + +#define S_BCM1480_SYS_CONFIG 26 +#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) +#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) +#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) + +#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) + +#define S_BCM1480_SYS_NODEID 47 +#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) +#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) +#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) + +#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) +#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) +#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) +#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) +#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) +#define S_BCM1480_SYS_DISABLECPU0 56 +#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) +#define S_BCM1480_SYS_DISABLECPU1 57 +#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) +#define S_BCM1480_SYS_DISABLECPU2 58 +#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) +#define S_BCM1480_SYS_DISABLECPU3 59 +#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) + +#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) +#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) +#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) +#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) /* * Scratch Register (Table 16) @@ -193,23 +193,23 @@ * Registers: SCD_WDOG_CFG_x */ -#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) +#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) -#define S_BCM1480_SCD_WDOG_RESET_TYPE 2 -#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) +#define S_BCM1480_SCD_WDOG_RESET_TYPE 2 +#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) #define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) #define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) -#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ -#define K_BCM1480_SCD_WDOG_RESET_SOFT 1 -#define K_BCM1480_SCD_WDOG_RESET_CPU0 3 -#define K_BCM1480_SCD_WDOG_RESET_CPU1 5 -#define K_BCM1480_SCD_WDOG_RESET_CPU2 9 -#define K_BCM1480_SCD_WDOG_RESET_CPU3 17 +#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ +#define K_BCM1480_SCD_WDOG_RESET_SOFT 1 +#define K_BCM1480_SCD_WDOG_RESET_CPU0 3 +#define K_BCM1480_SCD_WDOG_RESET_CPU1 5 +#define K_BCM1480_SCD_WDOG_RESET_CPU2 9 +#define K_BCM1480_SCD_WDOG_RESET_CPU3 17 #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 -#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) +#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) /* * General Timer Initial Count Registers (Table 26) @@ -243,32 +243,32 @@ * The clear/enable bits are in different locations on the 1250 and 1480. */ -#define S_SPC_CFG_SRC4 32 -#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) -#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) -#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) +#define S_SPC_CFG_SRC4 32 +#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) +#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) +#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) -#define S_SPC_CFG_SRC5 40 -#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) -#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) -#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) +#define S_SPC_CFG_SRC5 40 +#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) +#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) +#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) -#define S_SPC_CFG_SRC6 48 -#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) -#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) -#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) +#define S_SPC_CFG_SRC6 48 +#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) +#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) +#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) -#define S_SPC_CFG_SRC7 56 -#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) -#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) -#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) +#define S_SPC_CFG_SRC7 56 +#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) +#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) +#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) /* * System Performance Counter Control Register (Table 32) * Register: PERF_CNT_CFG_1 * BCM1480 specific */ -#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) +#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) #if SIBYTE_HDR_FEATURE_CHIP(1480) #define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR @@ -280,12 +280,12 @@ * Registers: PERF_CNT_x */ -#define S_BCM1480_SPC_CNT_COUNT 0 -#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) -#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) -#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) +#define S_BCM1480_SPC_CNT_COUNT 0 +#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) +#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) +#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) -#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) +#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) /* @@ -325,45 +325,45 @@ #define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) #define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) -#define S_BCM1480_ATRAP_CFG_CNT 0 -#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) -#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) -#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) +#define S_BCM1480_ATRAP_CFG_CNT 0 +#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) +#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) +#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) -#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) -#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) +#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) +#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) #define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) -#define S_BCM1480_ATRAP_CFG_AGENTID 8 -#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) -#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) -#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) +#define S_BCM1480_ATRAP_CFG_AGENTID 8 +#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) +#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) +#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) -#define K_BCM1480_BUS_AGENT_CPU0 0 -#define K_BCM1480_BUS_AGENT_CPU1 1 -#define K_BCM1480_BUS_AGENT_NC 2 -#define K_BCM1480_BUS_AGENT_IOB 3 -#define K_BCM1480_BUS_AGENT_SCD 4 -#define K_BCM1480_BUS_AGENT_L2C 6 -#define K_BCM1480_BUS_AGENT_MC 7 -#define K_BCM1480_BUS_AGENT_CPU2 8 -#define K_BCM1480_BUS_AGENT_CPU3 9 -#define K_BCM1480_BUS_AGENT_PM 10 +#define K_BCM1480_BUS_AGENT_CPU0 0 +#define K_BCM1480_BUS_AGENT_CPU1 1 +#define K_BCM1480_BUS_AGENT_NC 2 +#define K_BCM1480_BUS_AGENT_IOB 3 +#define K_BCM1480_BUS_AGENT_SCD 4 +#define K_BCM1480_BUS_AGENT_L2C 6 +#define K_BCM1480_BUS_AGENT_MC 7 +#define K_BCM1480_BUS_AGENT_CPU2 8 +#define K_BCM1480_BUS_AGENT_CPU3 9 +#define K_BCM1480_BUS_AGENT_PM 10 -#define S_BCM1480_ATRAP_CFG_CATTR 12 -#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) -#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) -#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) +#define S_BCM1480_ATRAP_CFG_CATTR 12 +#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) +#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) +#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 -#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 +#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 -#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) +#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) /* @@ -381,10 +381,10 @@ #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) -#define S_BCM1480_SCD_TRSEQ_SWFUNC 26 -#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) -#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) -#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) +#define S_BCM1480_SCD_TRSEQ_SWFUNC 26 +#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) /* * Trace Control Register (Table 49) @@ -394,13 +394,13 @@ * are defined below. */ -#define S_BCM1480_SCD_TRACE_CFG_MODE 16 -#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) -#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) -#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) +#define S_BCM1480_SCD_TRACE_CFG_MODE 16 +#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) +#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) +#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 -#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 +#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 #endif /* _BCM1480_SCD_H */ |