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-rw-r--r--arch/parisc/include/asm/assembly.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/parisc/include/asm/assembly.h b/arch/parisc/include/asm/assembly.h
index a39250cb7dfc..7085df079702 100644
--- a/arch/parisc/include/asm/assembly.h
+++ b/arch/parisc/include/asm/assembly.h
@@ -42,6 +42,9 @@
#define ASM_ULONG_INSN .word
#endif
+/* Frame alignment for 32- and 64-bit */
+#define FRAME_ALIGN 64
+
#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
#ifdef CONFIG_PA20
@@ -58,6 +61,10 @@
#define PA_ASM_LEVEL 1.1
#endif
+/* Privilege level field in the rightmost two bits of the IA queues */
+#define PRIV_USER 3
+#define PRIV_KERNEL 0
+
#ifdef __ASSEMBLY__
#ifdef CONFIG_64BIT
@@ -71,6 +78,7 @@
#include <asm/types.h>
#include <asm/asmregs.h>
+#include <asm/psw.h>
sp = 30
gp = 27
@@ -497,6 +505,30 @@
nop /* 7 */
.endm
+ /* Switch to virtual mapping, trashing only %r1 */
+ .macro virt_map
+ /* pcxt_ssm_bug */
+ rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
+ mtsp %r0, %sr4
+ mtsp %r0, %sr5
+ mtsp %r0, %sr6
+ tovirt_r1 %r29
+ load32 KERNEL_PSW, %r1
+
+ rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
+ mtctl %r0, %cr17 /* Clear IIASQ tail */
+ mtctl %r0, %cr17 /* Clear IIASQ head */
+ mtctl %r1, %ipsw
+ load32 4f, %r1
+ mtctl %r1, %cr18 /* Set IIAOQ tail */
+ ldo 4(%r1), %r1
+ mtctl %r1, %cr18 /* Set IIAOQ head */
+ rfir
+ nop
+4:
+ .endm
+
+
/*
* ASM_EXCEPTIONTABLE_ENTRY
*