diff options
Diffstat (limited to 'arch/s390/include')
25 files changed, 431 insertions, 676 deletions
diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h index 2a113d6a7dfd..451bfbb9db3d 100644 --- a/arch/s390/include/asm/atomic.h +++ b/arch/s390/include/asm/atomic.h @@ -18,8 +18,6 @@ #define ATOMIC_INIT(i) { (i) } -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) - #define __CS_LOOP(ptr, op_val, op_string) ({ \ int old_val, new_val; \ asm volatile( \ @@ -35,26 +33,6 @@ new_val; \ }) -#else /* __GNUC__ */ - -#define __CS_LOOP(ptr, op_val, op_string) ({ \ - int old_val, new_val; \ - asm volatile( \ - " l %0,0(%3)\n" \ - "0: lr %1,%0\n" \ - op_string " %1,%4\n" \ - " cs %0,%1,0(%3)\n" \ - " jl 0b" \ - : "=&d" (old_val), "=&d" (new_val), \ - "=m" (((atomic_t *)(ptr))->counter) \ - : "a" (ptr), "d" (op_val), \ - "m" (((atomic_t *)(ptr))->counter) \ - : "cc", "memory"); \ - new_val; \ -}) - -#endif /* __GNUC__ */ - static inline int atomic_read(const atomic_t *v) { barrier(); @@ -101,19 +79,11 @@ static inline void atomic_set_mask(unsigned long mask, atomic_t *v) static inline int atomic_cmpxchg(atomic_t *v, int old, int new) { -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) asm volatile( " cs %0,%2,%1" : "+d" (old), "=Q" (v->counter) : "d" (new), "Q" (v->counter) : "cc", "memory"); -#else /* __GNUC__ */ - asm volatile( - " cs %0,%3,0(%2)" - : "+d" (old), "=m" (v->counter) - : "a" (v), "d" (new), "m" (v->counter) - : "cc", "memory"); -#endif /* __GNUC__ */ return old; } @@ -140,8 +110,6 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) #ifdef CONFIG_64BIT -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) - #define __CSG_LOOP(ptr, op_val, op_string) ({ \ long long old_val, new_val; \ asm volatile( \ @@ -157,26 +125,6 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) new_val; \ }) -#else /* __GNUC__ */ - -#define __CSG_LOOP(ptr, op_val, op_string) ({ \ - long long old_val, new_val; \ - asm volatile( \ - " lg %0,0(%3)\n" \ - "0: lgr %1,%0\n" \ - op_string " %1,%4\n" \ - " csg %0,%1,0(%3)\n" \ - " jl 0b" \ - : "=&d" (old_val), "=&d" (new_val), \ - "=m" (((atomic_t *)(ptr))->counter) \ - : "a" (ptr), "d" (op_val), \ - "m" (((atomic_t *)(ptr))->counter) \ - : "cc", "memory"); \ - new_val; \ -}) - -#endif /* __GNUC__ */ - static inline long long atomic64_read(const atomic64_t *v) { barrier(); @@ -214,19 +162,11 @@ static inline void atomic64_set_mask(unsigned long mask, atomic64_t *v) static inline long long atomic64_cmpxchg(atomic64_t *v, long long old, long long new) { -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) asm volatile( " csg %0,%2,%1" : "+d" (old), "=Q" (v->counter) : "d" (new), "Q" (v->counter) : "cc", "memory"); -#else /* __GNUC__ */ - asm volatile( - " csg %0,%3,0(%2)" - : "+d" (old), "=m" (v->counter) - : "a" (v), "d" (new), "m" (v->counter) - : "cc", "memory"); -#endif /* __GNUC__ */ return old; } @@ -243,10 +183,8 @@ static inline long long atomic64_read(const atomic64_t *v) register_pair rp; asm volatile( - " lm %0,%N0,0(%1)" - : "=&d" (rp) - : "a" (&v->counter), "m" (v->counter) - ); + " lm %0,%N0,%1" + : "=&d" (rp) : "Q" (v->counter) ); return rp.pair; } @@ -255,10 +193,8 @@ static inline void atomic64_set(atomic64_t *v, long long i) register_pair rp = {.pair = i}; asm volatile( - " stm %1,%N1,0(%2)" - : "=m" (v->counter) - : "d" (rp), "a" (&v->counter) - ); + " stm %1,%N1,%0" + : "=Q" (v->counter) : "d" (rp) ); } static inline long long atomic64_xchg(atomic64_t *v, long long new) @@ -267,11 +203,11 @@ static inline long long atomic64_xchg(atomic64_t *v, long long new) register_pair rp_old; asm volatile( - " lm %0,%N0,0(%2)\n" - "0: cds %0,%3,0(%2)\n" + " lm %0,%N0,%1\n" + "0: cds %0,%2,%1\n" " jl 0b\n" - : "=&d" (rp_old), "+m" (v->counter) - : "a" (&v->counter), "d" (rp_new) + : "=&d" (rp_old), "=Q" (v->counter) + : "d" (rp_new), "Q" (v->counter) : "cc"); return rp_old.pair; } @@ -283,9 +219,9 @@ static inline long long atomic64_cmpxchg(atomic64_t *v, register_pair rp_new = {.pair = new}; asm volatile( - " cds %0,%3,0(%2)" - : "+&d" (rp_old), "+m" (v->counter) - : "a" (&v->counter), "d" (rp_new) + " cds %0,%2,%1" + : "+&d" (rp_old), "=Q" (v->counter) + : "d" (rp_new), "Q" (v->counter) : "cc"); return rp_old.pair; } diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h index b30606f6d523..2e05972c5085 100644 --- a/arch/s390/include/asm/bitops.h +++ b/arch/s390/include/asm/bitops.h @@ -71,8 +71,6 @@ extern const char _sb_findmap[]; #define __BITOPS_AND "nr" #define __BITOPS_XOR "xr" -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) - #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \ asm volatile( \ " l %0,%2\n" \ @@ -85,22 +83,6 @@ extern const char _sb_findmap[]; : "d" (__val), "Q" (*(unsigned long *) __addr) \ : "cc"); -#else /* __GNUC__ */ - -#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \ - asm volatile( \ - " l %0,0(%4)\n" \ - "0: lr %1,%0\n" \ - __op_string " %1,%3\n" \ - " cs %0,%1,0(%4)\n" \ - " jl 0b" \ - : "=&d" (__old), "=&d" (__new), \ - "=m" (*(unsigned long *) __addr) \ - : "d" (__val), "a" (__addr), \ - "m" (*(unsigned long *) __addr) : "cc"); - -#endif /* __GNUC__ */ - #else /* __s390x__ */ #define __BITOPS_ALIGN 7 @@ -109,8 +91,6 @@ extern const char _sb_findmap[]; #define __BITOPS_AND "ngr" #define __BITOPS_XOR "xgr" -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) - #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \ asm volatile( \ " lg %0,%2\n" \ @@ -123,23 +103,6 @@ extern const char _sb_findmap[]; : "d" (__val), "Q" (*(unsigned long *) __addr) \ : "cc"); -#else /* __GNUC__ */ - -#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \ - asm volatile( \ - " lg %0,0(%4)\n" \ - "0: lgr %1,%0\n" \ - __op_string " %1,%3\n" \ - " csg %0,%1,0(%4)\n" \ - " jl 0b" \ - : "=&d" (__old), "=&d" (__new), \ - "=m" (*(unsigned long *) __addr) \ - : "d" (__val), "a" (__addr), \ - "m" (*(unsigned long *) __addr) : "cc"); - - -#endif /* __GNUC__ */ - #endif /* __s390x__ */ #define __BITOPS_WORDS(bits) (((bits)+__BITOPS_WORDSIZE-1)/__BITOPS_WORDSIZE) @@ -261,9 +224,8 @@ static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr) addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3); asm volatile( - " oc 0(1,%1),0(%2)" - : "=m" (*(char *) addr) : "a" (addr), - "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" ); + " oc %O0(1,%R0),%1" + : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" ); } static inline void @@ -290,9 +252,8 @@ __clear_bit(unsigned long nr, volatile unsigned long *ptr) addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3); asm volatile( - " nc 0(1,%1),0(%2)" - : "=m" (*(char *) addr) : "a" (addr), - "a" (_ni_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc"); + " nc %O0(1,%R0),%1" + : "=Q" (*(char *) addr) : "Q" (_ni_bitmap[nr & 7]) : "cc" ); } static inline void @@ -318,9 +279,8 @@ static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr) addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3); asm volatile( - " xc 0(1,%1),0(%2)" - : "=m" (*(char *) addr) : "a" (addr), - "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" ); + " xc %O0(1,%R0),%1" + : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" ); } static inline void @@ -349,10 +309,9 @@ test_and_set_bit_simple(unsigned long nr, volatile unsigned long *ptr) addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3); ch = *(unsigned char *) addr; asm volatile( - " oc 0(1,%1),0(%2)" - : "=m" (*(char *) addr) - : "a" (addr), "a" (_oi_bitmap + (nr & 7)), - "m" (*(char *) addr) : "cc", "memory"); + " oc %O0(1,%R0),%1" + : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) + : "cc", "memory"); return (ch >> (nr & 7)) & 1; } #define __test_and_set_bit(X,Y) test_and_set_bit_simple(X,Y) @@ -369,10 +328,9 @@ test_and_clear_bit_simple(unsigned long nr, volatile unsigned long *ptr) addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3); ch = *(unsigned char *) addr; asm volatile( - " nc 0(1,%1),0(%2)" - : "=m" (*(char *) addr) - : "a" (addr), "a" (_ni_bitmap + (nr & 7)), - "m" (*(char *) addr) : "cc", "memory"); + " nc %O0(1,%R0),%1" + : "=Q" (*(char *) addr) : "Q" (_ni_bitmap[nr & 7]) + : "cc", "memory"); return (ch >> (nr & 7)) & 1; } #define __test_and_clear_bit(X,Y) test_and_clear_bit_simple(X,Y) @@ -389,10 +347,9 @@ test_and_change_bit_simple(unsigned long nr, volatile unsigned long *ptr) addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3); ch = *(unsigned char *) addr; asm volatile( - " xc 0(1,%1),0(%2)" - : "=m" (*(char *) addr) - : "a" (addr), "a" (_oi_bitmap + (nr & 7)), - "m" (*(char *) addr) : "cc", "memory"); + " xc %O0(1,%R0),%1" + : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) + : "cc", "memory"); return (ch >> (nr & 7)) & 1; } #define __test_and_change_bit(X,Y) test_and_change_bit_simple(X,Y) @@ -591,11 +548,11 @@ static inline unsigned long __load_ulong_le(const unsigned long *p, p = (unsigned long *)((unsigned long) p + offset); #ifndef __s390x__ asm volatile( - " ic %0,0(%1)\n" - " icm %0,2,1(%1)\n" - " icm %0,4,2(%1)\n" - " icm %0,8,3(%1)" - : "=&d" (word) : "a" (p), "m" (*p) : "cc"); + " ic %0,%O1(%R1)\n" + " icm %0,2,%O1+1(%R1)\n" + " icm %0,4,%O1+2(%R1)\n" + " icm %0,8,%O1+3(%R1)" + : "=&d" (word) : "Q" (*p) : "cc"); #else asm volatile( " lrvg %0,%1" diff --git a/arch/s390/include/asm/bug.h b/arch/s390/include/asm/bug.h index b1066b9fb5f8..9beeb9db9b23 100644 --- a/arch/s390/include/asm/bug.h +++ b/arch/s390/include/asm/bug.h @@ -5,12 +5,6 @@ #ifdef CONFIG_BUG -#ifdef CONFIG_64BIT -#define S390_LONG ".quad" -#else -#define S390_LONG ".long" -#endif - #ifdef CONFIG_DEBUG_BUGVERBOSE #define __EMIT_BUG(x) do { \ @@ -21,7 +15,7 @@ "2: .asciz \""__FILE__"\"\n" \ ".previous\n" \ ".section __bug_table,\"a\"\n" \ - "3:\t" S390_LONG "\t1b,2b\n" \ + "3: .long 1b-3b,2b-3b\n" \ " .short %0,%1\n" \ " .org 3b+%2\n" \ ".previous\n" \ @@ -37,7 +31,7 @@ "0: j 0b+2\n" \ "1:\n" \ ".section __bug_table,\"a\"\n" \ - "2:\t" S390_LONG "\t1b\n" \ + "2: .long 1b-2b\n" \ " .short %0\n" \ " .org 2b+%1\n" \ ".previous\n" \ diff --git a/arch/s390/include/asm/crw.h b/arch/s390/include/asm/crw.h index 2185a6d619d3..749a97e61bea 100644 --- a/arch/s390/include/asm/crw.h +++ b/arch/s390/include/asm/crw.h @@ -32,6 +32,7 @@ typedef void (*crw_handler_t)(struct crw *, struct crw *, int); extern int crw_register_handler(int rsc, crw_handler_t handler); extern void crw_unregister_handler(int rsc); extern void crw_handle_channel_report(void); +void crw_wait_for_channel_report(void); #define NR_RSCS 16 diff --git a/arch/s390/include/asm/etr.h b/arch/s390/include/asm/etr.h index 80ef58c61970..538e1b36a726 100644 --- a/arch/s390/include/asm/etr.h +++ b/arch/s390/include/asm/etr.h @@ -145,11 +145,11 @@ static inline int etr_setr(struct etr_eacr *ctrl) int rc = -ENOSYS; asm volatile( - " .insn s,0xb2160000,0(%2)\n" + " .insn s,0xb2160000,%1\n" "0: la %0,0\n" "1:\n" EX_TABLE(0b,1b) - : "+d" (rc) : "m" (*ctrl), "a" (ctrl)); + : "+d" (rc) : "Q" (*ctrl)); return rc; } @@ -159,11 +159,11 @@ static inline int etr_stetr(struct etr_aib *aib) int rc = -ENOSYS; asm volatile( - " .insn s,0xb2170000,0(%2)\n" + " .insn s,0xb2170000,%1\n" "0: la %0,0\n" "1:\n" EX_TABLE(0b,1b) - : "+d" (rc) : "m" (*aib), "a" (aib)); + : "+d" (rc) : "Q" (*aib)); return rc; } @@ -174,11 +174,11 @@ static inline int etr_steai(struct etr_aib *aib, unsigned int func) int rc = -ENOSYS; asm volatile( - " .insn s,0xb2b30000,0(%2)\n" + " .insn s,0xb2b30000,%1\n" "0: la %0,0\n" "1:\n" EX_TABLE(0b,1b) - : "+d" (rc) : "m" (*aib), "a" (aib), "d" (reg0)); + : "+d" (rc) : "Q" (*aib), "d" (reg0)); return rc; } diff --git a/arch/s390/include/asm/irqflags.h b/arch/s390/include/asm/irqflags.h index c2fb432f576a..15b3ac253898 100644 --- a/arch/s390/include/asm/irqflags.h +++ b/arch/s390/include/asm/irqflags.h @@ -8,8 +8,6 @@ #include <linux/types.h> -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) - /* store then or system mask. */ #define __raw_local_irq_stosm(__or) \ ({ \ @@ -36,40 +34,6 @@ asm volatile("ssm %0" : : "Q" (__mask) : "memory"); \ }) -#else /* __GNUC__ */ - -/* store then or system mask. */ -#define __raw_local_irq_stosm(__or) \ -({ \ - unsigned long __mask; \ - asm volatile( \ - " stosm 0(%1),%2" \ - : "=m" (__mask) \ - : "a" (&__mask), "i" (__or) : "memory"); \ - __mask; \ -}) - -/* store then and system mask. */ -#define __raw_local_irq_stnsm(__and) \ -({ \ - unsigned long __mask; \ - asm volatile( \ - " stnsm 0(%1),%2" \ - : "=m" (__mask) \ - : "a" (&__mask), "i" (__and) : "memory"); \ - __mask; \ -}) - -/* set system mask. */ -#define __raw_local_irq_ssm(__mask) \ -({ \ - asm volatile( \ - " ssm 0(%0)" \ - : : "a" (&__mask), "m" (__mask) : "memory"); \ -}) - -#endif /* __GNUC__ */ - /* interrupt control.. */ static inline unsigned long raw_local_irq_enable(void) { diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h index f2ef4b619ce1..05527c040b7a 100644 --- a/arch/s390/include/asm/lowcore.h +++ b/arch/s390/include/asm/lowcore.h @@ -1,141 +1,16 @@ /* - * include/asm-s390/lowcore.h - * - * S390 version - * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation - * Author(s): Hartmut Penner (hp@de.ibm.com), - * Martin Schwidefsky (schwidefsky@de.ibm.com), - * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) + * Copyright IBM Corp. 1999,2010 + * Author(s): Hartmut Penner <hp@de.ibm.com>, + * Martin Schwidefsky <schwidefsky@de.ibm.com>, + * Denis Joseph Barrow, */ #ifndef _ASM_S390_LOWCORE_H #define _ASM_S390_LOWCORE_H -#define __LC_IPL_PARMBLOCK_PTR 0x0014 -#define __LC_EXT_PARAMS 0x0080 -#define __LC_CPU_ADDRESS 0x0084 -#define __LC_EXT_INT_CODE 0x0086 - -#define __LC_SVC_ILC 0x0088 -#define __LC_SVC_INT_CODE 0x008a -#define __LC_PGM_ILC 0x008c -#define __LC_PGM_INT_CODE 0x008e - -#define __LC_PER_ATMID 0x0096 -#define __LC_PER_ADDRESS 0x0098 -#define __LC_PER_ACCESS_ID 0x00a1 -#define __LC_AR_MODE_ID 0x00a3 - -#define __LC_SUBCHANNEL_ID 0x00b8 -#define __LC_SUBCHANNEL_NR 0x00ba -#define __LC_IO_INT_PARM 0x00bc -#define __LC_IO_INT_WORD 0x00c0 -#define __LC_STFL_FAC_LIST 0x00c8 -#define __LC_MCCK_CODE 0x00e8 - -#define __LC_DUMP_REIPL 0x0e00 - -#ifndef __s390x__ -#define __LC_EXT_OLD_PSW 0x0018 -#define __LC_SVC_OLD_PSW 0x0020 -#define __LC_PGM_OLD_PSW 0x0028 -#define __LC_MCK_OLD_PSW 0x0030 -#define __LC_IO_OLD_PSW 0x0038 -#define __LC_EXT_NEW_PSW 0x0058 -#define __LC_SVC_NEW_PSW 0x0060 -#define __LC_PGM_NEW_PSW 0x0068 -#define __LC_MCK_NEW_PSW 0x0070 -#define __LC_IO_NEW_PSW 0x0078 -#define __LC_SAVE_AREA 0x0200 -#define __LC_RETURN_PSW 0x0240 -#define __LC_RETURN_MCCK_PSW 0x0248 -#define __LC_SYNC_ENTER_TIMER 0x0250 -#define __LC_ASYNC_ENTER_TIMER 0x0258 -#define __LC_EXIT_TIMER 0x0260 -#define __LC_USER_TIMER 0x0268 -#define __LC_SYSTEM_TIMER 0x0270 -#define __LC_STEAL_TIMER 0x0278 -#define __LC_LAST_UPDATE_TIMER 0x0280 -#define __LC_LAST_UPDATE_CLOCK 0x0288 -#define __LC_CURRENT 0x0290 -#define __LC_THREAD_INFO 0x0294 -#define __LC_KERNEL_STACK 0x0298 -#define __LC_ASYNC_STACK 0x029c -#define __LC_PANIC_STACK 0x02a0 -#define __LC_KERNEL_ASCE 0x02a4 -#define __LC_USER_ASCE 0x02a8 -#define __LC_USER_EXEC_ASCE 0x02ac -#define __LC_CPUID 0x02b0 -#define __LC_INT_CLOCK 0x02c8 -#define __LC_MACHINE_FLAGS 0x02d8 -#define __LC_FTRACE_FUNC 0x02dc -#define __LC_IRB 0x0300 -#define __LC_PFAULT_INTPARM 0x0080 -#define __LC_CPU_TIMER_SAVE_AREA 0x00d8 -#define __LC_CLOCK_COMP_SAVE_AREA 0x00e0 -#define __LC_PSW_SAVE_AREA 0x0100 -#define __LC_PREFIX_SAVE_AREA 0x0108 -#define __LC_AREGS_SAVE_AREA 0x0120 -#define __LC_FPREGS_SAVE_AREA 0x0160 -#define __LC_GPREGS_SAVE_AREA 0x0180 -#define __LC_CREGS_SAVE_AREA 0x01c0 -#else /* __s390x__ */ -#define __LC_LAST_BREAK 0x0110 -#define __LC_EXT_OLD_PSW 0x0130 -#define __LC_SVC_OLD_PSW 0x0140 -#define __LC_PGM_OLD_PSW 0x0150 -#define __LC_MCK_OLD_PSW 0x0160 -#define __LC_IO_OLD_PSW 0x0170 -#define __LC_RESTART_PSW 0x01a0 -#define __LC_EXT_NEW_PSW 0x01b0 -#define __LC_SVC_NEW_PSW 0x01c0 -#define __LC_PGM_NEW_PSW 0x01d0 -#define __LC_MCK_NEW_PSW 0x01e0 -#define __LC_IO_NEW_PSW 0x01f0 -#define __LC_SAVE_AREA 0x0200 -#define __LC_RETURN_PSW 0x0280 -#define __LC_RETURN_MCCK_PSW 0x0290 -#define __LC_SYNC_ENTER_TIMER 0x02a0 -#define __LC_ASYNC_ENTER_TIMER 0x02a8 -#define __LC_EXIT_TIMER 0x02b0 -#define __LC_USER_TIMER 0x02b8 -#define __LC_SYSTEM_TIMER 0x02c0 -#define __LC_STEAL_TIMER 0x02c8 -#define __LC_LAST_UPDATE_TIMER 0x02d0 -#define __LC_LAST_UPDATE_CLOCK 0x02d8 -#define __LC_CURRENT 0x02e0 -#define __LC_THREAD_INFO 0x02e8 -#define __LC_KERNEL_STACK 0x02f0 -#define __LC_ASYNC_STACK 0x02f8 -#define __LC_PANIC_STACK 0x0300 -#define __LC_KERNEL_ASCE 0x0308 -#define __LC_USER_ASCE 0x0310 -#define __LC_USER_EXEC_ASCE 0x0318 -#define __LC_CPUID 0x0320 -#define __LC_INT_CLOCK 0x0340 -#define __LC_VDSO_PER_CPU 0x0350 -#define __LC_MACHINE_FLAGS 0x0358 -#define __LC_FTRACE_FUNC 0x0360 -#define __LC_IRB 0x0380 -#define __LC_PASTE 0x03c0 -#define __LC_PFAULT_INTPARM 0x11b8 -#define __LC_FPREGS_SAVE_AREA 0x1200 -#define __LC_GPREGS_SAVE_AREA 0x1280 -#define __LC_PSW_SAVE_AREA 0x1300 -#define __LC_PREFIX_SAVE_AREA 0x1318 -#define __LC_FP_CREG_SAVE_AREA 0x131c -#define __LC_TODREG_SAVE_AREA 0x1324 -#define __LC_CPU_TIMER_SAVE_AREA 0x1328 -#define __LC_CLOCK_COMP_SAVE_AREA 0x1331 -#define __LC_AREGS_SAVE_AREA 0x1340 -#define __LC_CREGS_SAVE_AREA 0x1380 -#endif /* __s390x__ */ - -#ifndef __ASSEMBLY__ - -#include <asm/cpu.h> -#include <asm/ptrace.h> #include <linux/types.h> +#include <asm/ptrace.h> +#include <asm/cpu.h> void restart_int_handler(void); void ext_int_handler(void); @@ -144,7 +19,12 @@ void pgm_check_handler(void); void mcck_int_handler(void); void io_int_handler(void); -struct save_area_s390 { +#ifdef CONFIG_32BIT + +#define LC_ORDER 0 +#define LC_PAGES 1 + +struct save_area { u32 ext_save; u64 timer; u64 clk_cmp; @@ -156,54 +36,13 @@ struct save_area_s390 { u64 fp_regs[4]; u32 gp_regs[16]; u32 ctrl_regs[16]; -} __attribute__((packed)); - -struct save_area_s390x { - u64 fp_regs[16]; - u64 gp_regs[16]; - u8 psw[16]; - u8 pad1[8]; - u32 pref_reg; - u32 fp_ctrl_reg; - u8 pad2[4]; - u32 tod_reg; - u64 timer; - u64 clk_cmp; - u8 pad3[8]; - u32 acc_regs[16]; - u64 ctrl_regs[16]; -} __attribute__((packed)); - -union save_area { - struct save_area_s390 s390; - struct save_area_s390x s390x; -}; - -#define SAVE_AREA_BASE_S390 0xd4 -#define SAVE_AREA_BASE_S390X 0x1200 - -#ifndef __s390x__ -#define SAVE_AREA_SIZE sizeof(struct save_area_s390) -#define SAVE_AREA_BASE SAVE_AREA_BASE_S390 -#else -#define SAVE_AREA_SIZE sizeof(struct save_area_s390x) -#define SAVE_AREA_BASE SAVE_AREA_BASE_S390X -#endif - -#ifndef __s390x__ -#define LC_ORDER 0 -#else -#define LC_ORDER 1 -#endif - -#define LC_PAGES (1UL << LC_ORDER) +} __packed; -struct _lowcore -{ -#ifndef __s390x__ - /* 0x0000 - 0x01ff: defined by architecture */ +struct _lowcore { psw_t restart_psw; /* 0x0000 */ - __u32 ccw2[4]; /* 0x0008 */ + psw_t restart_old_psw; /* 0x0008 */ + __u8 pad_0x0010[0x0014-0x0010]; /* 0x0010 */ + __u32 ipl_parmblock_ptr; /* 0x0014 */ psw_t external_old_psw; /* 0x0018 */ psw_t svc_old_psw; /* 0x0020 */ psw_t program_old_psw; /* 0x0028 */ @@ -229,7 +68,9 @@ struct _lowcore __u32 monitor_code; /* 0x009c */ __u8 exc_access_id; /* 0x00a0 */ __u8 per_access_id; /* 0x00a1 */ - __u8 pad_0x00a2[0x00b8-0x00a2]; /* 0x00a2 */ + __u8 op_access_id; /* 0x00a2 */ + __u8 ar_access_id; /* 0x00a3 */ + __u8 pad_0x00a4[0x00b8-0x00a4]; /* 0x00a4 */ __u16 subchannel_id; /* 0x00b8 */ __u16 subchannel_nr; /* 0x00ba */ __u32 io_int_parm; /* 0x00bc */ @@ -245,8 +86,9 @@ struct _lowcore __u32 external_damage_code; /* 0x00f4 */ __u32 failing_storage_address; /* 0x00f8 */ __u8 pad_0x00fc[0x0100-0x00fc]; /* 0x00fc */ - __u32 st_status_fixed_logout[4]; /* 0x0100 */ - __u8 pad_0x0110[0x0120-0x0110]; /* 0x0110 */ + psw_t psw_save_area; /* 0x0100 */ + __u32 prefixreg_save_area; /* 0x0108 */ + __u8 pad_0x010c[0x0120-0x010c]; /* 0x010c */ /* CPU register save area: defined by architecture */ __u32 access_regs_save_area[16]; /* 0x0120 */ @@ -293,12 +135,12 @@ struct _lowcore __u64 clock_comparator; /* 0x02d0 */ __u32 machine_flags; /* 0x02d8 */ __u32 ftrace_func; /* 0x02dc */ - __u8 pad_0x02f0[0x0300-0x02f0]; /* 0x02f0 */ + __u8 pad_0x02e0[0x0300-0x02e0]; /* 0x02e0 */ /* Interrupt response block */ __u8 irb[64]; /* 0x0300 */ - __u8 pad_0x0400[0x0e00-0x0400]; /* 0x0400 */ + __u8 pad_0x0340[0x0e00-0x0340]; /* 0x0340 */ /* * 0xe00 contains the address of the IPL Parameter Information @@ -310,10 +152,32 @@ struct _lowcore /* Align to the top 1k of prefix area */ __u8 pad_0x0e08[0x1000-0x0e08]; /* 0x0e08 */ -#else /* !__s390x__ */ - /* 0x0000 - 0x01ff: defined by architecture */ - __u32 ccw1[2]; /* 0x0000 */ - __u32 ccw2[4]; /* 0x0008 */ +} __packed; + +#else /* CONFIG_32BIT */ + +#define LC_ORDER 1 +#define LC_PAGES 2 + +struct save_area { + u64 fp_regs[16]; + u64 gp_regs[16]; + u8 psw[16]; + u8 pad1[8]; + u32 pref_reg; + u32 fp_ctrl_reg; + u8 pad2[4]; + u32 tod_reg; + u64 timer; + u64 clk_cmp; + u8 pad3[8]; + u32 acc_regs[16]; + u64 ctrl_regs[16]; +} __packed; + +struct _lowcore { + __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */ + __u32 ipl_parmblock_ptr; /* 0x0014 */ __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */ __u32 ext_params; /* 0x0080 */ __u16 cpu_addr; /* 0x0084 */ @@ -344,7 +208,9 @@ struct _lowcore __u8 pad_0x00f0[0x00f4-0x00f0]; /* 0x00f0 */ __u32 external_damage_code; /* 0x00f4 */ addr_t failing_storage_address; /* 0x00f8 */ - __u8 pad_0x0100[0x0120-0x0100]; /* 0x0100 */ + __u8 pad_0x0100[0x0110-0x0100]; /* 0x0100 */ + __u64 breaking_event_addr; /* 0x0110 */ + __u8 pad_0x0118[0x0120-0x0118]; /* 0x0118 */ psw_t restart_old_psw; /* 0x0120 */ psw_t external_old_psw; /* 0x0130 */ psw_t svc_old_psw; /* 0x0140 */ @@ -425,7 +291,7 @@ struct _lowcore /* CPU register save area: defined by architecture */ __u64 floating_pt_save_area[16]; /* 0x1200 */ __u64 gpregs_save_area[16]; /* 0x1280 */ - __u32 st_status_fixed_logout[4]; /* 0x1300 */ + psw_t psw_save_area; /* 0x1300 */ __u8 pad_0x1310[0x1318-0x1310]; /* 0x1310 */ __u32 prefixreg_save_area; /* 0x1318 */ __u32 fpt_creg_save_area; /* 0x131c */ @@ -439,10 +305,12 @@ struct _lowcore /* align to the top of the prefix area */ __u8 pad_0x1400[0x2000-0x1400]; /* 0x1400 */ -#endif /* !__s390x__ */ -} __attribute__((packed)); /* End structure*/ +} __packed; + +#endif /* CONFIG_32BIT */ #define S390_lowcore (*((struct _lowcore *) 0)) + extern struct _lowcore *lowcore_ptr[]; static inline void set_prefix(__u32 address) @@ -458,6 +326,4 @@ static inline __u32 store_prefix(void) return address; } -#endif - -#endif +#endif /* _ASM_S390_LOWCORE_H */ diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index 5e9daf5d7f22..af650fb47206 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -107,9 +107,6 @@ typedef pte_t *pgtable_t; #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) -/* default storage key used for all pages */ -extern unsigned int default_storage_key; - static inline void page_set_storage_key(unsigned long addr, unsigned int skey) { diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index e2fa79cf0614..9b5b9189c15e 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -43,7 +43,7 @@ extern void vmem_map_init(void); * The S390 doesn't have any external MMU info: the kernel page * tables contain all the necessary information. */ -#define update_mmu_cache(vma, address, pte) do { } while (0) +#define update_mmu_cache(vma, address, ptep) do { } while (0) /* * ZERO_PAGE is a global shared page that is always zero: used diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h index b42715458312..73e259834e10 100644 --- a/arch/s390/include/asm/processor.h +++ b/arch/s390/include/asm/processor.h @@ -28,7 +28,7 @@ static inline void get_cpu_id(struct cpuid *ptr) { - asm volatile("stidp 0(%1)" : "=m" (*ptr) : "a" (ptr)); + asm volatile("stidp %0" : "=Q" (*ptr)); } extern void s390_adjust_jiffies(void); @@ -184,9 +184,9 @@ static inline void psw_set_key(unsigned int key) static inline void __load_psw(psw_t psw) { #ifndef __s390x__ - asm volatile("lpsw 0(%0)" : : "a" (&psw), "m" (psw) : "cc"); + asm volatile("lpsw %0" : : "Q" (psw) : "cc"); #else - asm volatile("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc"); + asm volatile("lpswe %0" : : "Q" (psw) : "cc"); #endif } @@ -206,17 +206,17 @@ static inline void __load_psw_mask (unsigned long mask) asm volatile( " basr %0,0\n" "0: ahi %0,1f-0b\n" - " st %0,4(%1)\n" - " lpsw 0(%1)\n" + " st %0,%O1+4(%R1)\n" + " lpsw %1\n" "1:" - : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc"); + : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); #else /* __s390x__ */ asm volatile( " larl %0,1f\n" - " stg %0,8(%1)\n" - " lpswe 0(%1)\n" + " stg %0,%O1+8(%R1)\n" + " lpswe %1\n" "1:" - : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc"); + : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); #endif /* __s390x__ */ } diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h index 95dcf183a28d..dd2d913afcae 100644 --- a/arch/s390/include/asm/ptrace.h +++ b/arch/s390/include/asm/ptrace.h @@ -492,13 +492,24 @@ struct user_regs_struct struct task_struct; extern void user_enable_single_step(struct task_struct *); extern void user_disable_single_step(struct task_struct *); +extern void show_regs(struct pt_regs * regs); #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0) #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN) #define user_stack_pointer(regs)((regs)->gprs[15]) #define regs_return_value(regs)((regs)->gprs[2]) #define profile_pc(regs) instruction_pointer(regs) -extern void show_regs(struct pt_regs * regs); + +int regs_query_register_offset(const char *name); +const char *regs_query_register_name(unsigned int offset); +unsigned long regs_get_register(struct pt_regs *regs, unsigned int offset); +unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n); + +static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) +{ + return regs->gprs[15] & PSW_ADDR_INSN; +} + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index 79d849f014f0..c666bfe5e984 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -13,7 +13,8 @@ #include <asm/cio.h> #include <asm/ccwdev.h> -#define QDIO_MAX_QUEUES_PER_IRQ 32 +/* only use 4 queues to save some cachelines */ +#define QDIO_MAX_QUEUES_PER_IRQ 4 #define QDIO_MAX_BUFFERS_PER_Q 128 #define QDIO_MAX_BUFFERS_MASK (QDIO_MAX_BUFFERS_PER_Q - 1) #define QDIO_MAX_ELEMENTS_PER_BUFFER 16 diff --git a/arch/s390/include/asm/rwsem.h b/arch/s390/include/asm/rwsem.h index 9d2a17971805..423fdda2322d 100644 --- a/arch/s390/include/asm/rwsem.h +++ b/arch/s390/include/asm/rwsem.h @@ -124,21 +124,21 @@ static inline void __down_read(struct rw_semaphore *sem) asm volatile( #ifndef __s390x__ - " l %0,0(%3)\n" + " l %0,%2\n" "0: lr %1,%0\n" - " ahi %1,%5\n" - " cs %0,%1,0(%3)\n" + " ahi %1,%4\n" + " cs %0,%1,%2\n" " jl 0b" #else /* __s390x__ */ - " lg %0,0(%3)\n" + " lg %0,%2\n" "0: lgr %1,%0\n" - " aghi %1,%5\n" - " csg %0,%1,0(%3)\n" + " aghi %1,%4\n" + " csg %0,%1,%2\n" " jl 0b" #endif /* __s390x__ */ - : "=&d" (old), "=&d" (new), "=m" (sem->count) - : "a" (&sem->count), "m" (sem->count), - "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory"); + : "=&d" (old), "=&d" (new), "=Q" (sem->count) + : "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS) + : "cc", "memory"); if (old < 0) rwsem_down_read_failed(sem); } @@ -152,25 +152,25 @@ static inline int __down_read_trylock(struct rw_semaphore *sem) asm volatile( #ifndef __s390x__ - " l %0,0(%3)\n" + " l %0,%2\n" "0: ltr %1,%0\n" " jm 1f\n" - " ahi %1,%5\n" - " cs %0,%1,0(%3)\n" + " ahi %1,%4\n" + " cs %0,%1,%2\n" " jl 0b\n" "1:" #else /* __s390x__ */ - " lg %0,0(%3)\n" + " lg %0,%2\n" "0: ltgr %1,%0\n" " jm 1f\n" - " aghi %1,%5\n" - " csg %0,%1,0(%3)\n" + " aghi %1,%4\n" + " csg %0,%1,%2\n" " jl 0b\n" "1:" #endif /* __s390x__ */ - : "=&d" (old), "=&d" (new), "=m" (sem->count) - : "a" (&sem->count), "m" (sem->count), - "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory"); + : "=&d" (old), "=&d" (new), "=Q" (sem->count) + : "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS) + : "cc", "memory"); return old >= 0 ? 1 : 0; } @@ -184,20 +184,20 @@ static inline void __down_write_nested(struct rw_semaphore *sem, int subclass) tmp = RWSEM_ACTIVE_WRITE_BIAS; asm volatile( #ifndef __s390x__ - " l %0,0(%3)\n" + " l %0,%2\n" "0: lr %1,%0\n" - " a %1,%5\n" - " cs %0,%1,0(%3)\n" + " a %1,%4\n" + " cs %0,%1,%2\n" " jl 0b" #else /* __s390x__ */ - " lg %0,0(%3)\n" + " lg %0,%2\n" "0: lgr %1,%0\n" - " ag %1,%5\n" - " csg %0,%1,0(%3)\n" + " ag %1,%4\n" + " csg %0,%1,%2\n" " jl 0b" #endif /* __s390x__ */ - : "=&d" (old), "=&d" (new), "=m" (sem->count) - : "a" (&sem->count), "m" (sem->count), "m" (tmp) + : "=&d" (old), "=&d" (new), "=Q" (sem->count) + : "Q" (sem->count), "m" (tmp) : "cc", "memory"); if (old != 0) rwsem_down_write_failed(sem); @@ -217,22 +217,22 @@ static inline int __down_write_trylock(struct rw_semaphore *sem) asm volatile( #ifndef __s390x__ - " l %0,0(%2)\n" + " l %0,%1\n" "0: ltr %0,%0\n" " jnz 1f\n" - " cs %0,%4,0(%2)\n" + " cs %0,%3,%1\n" " jl 0b\n" #else /* __s390x__ */ - " lg %0,0(%2)\n" + " lg %0,%1\n" "0: ltgr %0,%0\n" " jnz 1f\n" - " csg %0,%4,0(%2)\n" + " csg %0,%3,%1\n" " jl 0b\n" #endif /* __s390x__ */ "1:" - : "=&d" (old), "=m" (sem->count) - : "a" (&sem->count), "m" (sem->count), - "d" (RWSEM_ACTIVE_WRITE_BIAS) : "cc", "memory"); + : "=&d" (old), "=Q" (sem->count) + : "Q" (sem->count), "d" (RWSEM_ACTIVE_WRITE_BIAS) + : "cc", "memory"); return (old == RWSEM_UNLOCKED_VALUE) ? 1 : 0; } @@ -245,21 +245,20 @@ static inline void __up_read(struct rw_semaphore *sem) asm volatile( #ifndef __s390x__ - " l %0,0(%3)\n" + " l %0,%2\n" "0: lr %1,%0\n" - " ahi %1,%5\n" - " cs %0,%1,0(%3)\n" + " ahi %1,%4\n" + " cs %0,%1,%2\n" " jl 0b" #else /* __s390x__ */ - " lg %0,0(%3)\n" + " lg %0,%2\n" "0: lgr %1,%0\n" - " aghi %1,%5\n" - " csg %0,%1,0(%3)\n" + " aghi %1,%4\n" + " csg %0,%1,%2\n" " jl 0b" #endif /* __s390x__ */ - : "=&d" (old), "=&d" (new), "=m" (sem->count) - : "a" (&sem->count), "m" (sem->count), - "i" (-RWSEM_ACTIVE_READ_BIAS) + : "=&d" (old), "=&d" (new), "=Q" (sem->count) + : "Q" (sem->count), "i" (-RWSEM_ACTIVE_READ_BIAS) : "cc", "memory"); if (new < 0) if ((new & RWSEM_ACTIVE_MASK) == 0) @@ -276,20 +275,20 @@ static inline void __up_write(struct rw_semaphore *sem) tmp = -RWSEM_ACTIVE_WRITE_BIAS; asm volatile( #ifndef __s390x__ - " l %0,0(%3)\n" + " l %0,%2\n" "0: lr %1,%0\n" - " a %1,%5\n" - " cs %0,%1,0(%3)\n" + " a %1,%4\n" + " cs %0,%1,%2\n" " jl 0b" #else /* __s390x__ */ - " lg %0,0(%3)\n" + " lg %0,%2\n" "0: lgr %1,%0\n" - " ag %1,%5\n" - " csg %0,%1,0(%3)\n" + " ag %1,%4\n" + " csg %0,%1,%2\n" " jl 0b" #endif /* __s390x__ */ - : "=&d" (old), "=&d" (new), "=m" (sem->count) - : "a" (&sem->count), "m" (sem->count), "m" (tmp) + : "=&d" (old), "=&d" (new), "=Q" (sem->count) + : "Q" (sem->count), "m" (tmp) : "cc", "memory"); if (new < 0) if ((new & RWSEM_ACTIVE_MASK) == 0) @@ -306,20 +305,20 @@ static inline void __downgrade_write(struct rw_semaphore *sem) tmp = -RWSEM_WAITING_BIAS; asm volatile( #ifndef __s390x__ - " l %0,0(%3)\n" + " l %0,%2\n" "0: lr %1,%0\n" - " a %1,%5\n" - " cs %0,%1,0(%3)\n" + " a %1,%4\n" + " cs %0,%1,%2\n" " jl 0b" #else /* __s390x__ */ - " lg %0,0(%3)\n" + " lg %0,%2\n" "0: lgr %1,%0\n" - " ag %1,%5\n" - " csg %0,%1,0(%3)\n" + " ag %1,%4\n" + " csg %0,%1,%2\n" " jl 0b" #endif /* __s390x__ */ - : "=&d" (old), "=&d" (new), "=m" (sem->count) - : "a" (&sem->count), "m" (sem->count), "m" (tmp) + : "=&d" (old), "=&d" (new), "=Q" (sem->count) + : "Q" (sem->count), "m" (tmp) : "cc", "memory"); if (new > 1) rwsem_downgrade_wake(sem); @@ -334,20 +333,20 @@ static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem) asm volatile( #ifndef __s390x__ - " l %0,0(%3)\n" + " l %0,%2\n" "0: lr %1,%0\n" - " ar %1,%5\n" - " cs %0,%1,0(%3)\n" + " ar %1,%4\n" + " cs %0,%1,%2\n" " jl 0b" #else /* __s390x__ */ - " lg %0,0(%3)\n" + " lg %0,%2\n" "0: lgr %1,%0\n" - " agr %1,%5\n" - " csg %0,%1,0(%3)\n" + " agr %1,%4\n" + " csg %0,%1,%2\n" " jl 0b" #endif /* __s390x__ */ - : "=&d" (old), "=&d" (new), "=m" (sem->count) - : "a" (&sem->count), "m" (sem->count), "d" (delta) + : "=&d" (old), "=&d" (new), "=Q" (sem->count) + : "Q" (sem->count), "d" (delta) : "cc", "memory"); } @@ -360,20 +359,20 @@ static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem) asm volatile( #ifndef __s390x__ - " l %0,0(%3)\n" + " l %0,%2\n" "0: lr %1,%0\n" - " ar %1,%5\n" - " cs %0,%1,0(%3)\n" + " ar %1,%4\n" + " cs %0,%1,%2\n" " jl 0b" #else /* __s390x__ */ - " lg %0,0(%3)\n" + " lg %0,%2\n" "0: lgr %1,%0\n" - " agr %1,%5\n" - " csg %0,%1,0(%3)\n" + " agr %1,%4\n" + " csg %0,%1,%2\n" " jl 0b" #endif /* __s390x__ */ - : "=&d" (old), "=&d" (new), "=m" (sem->count) - : "a" (&sem->count), "m" (sem->count), "d" (delta) + : "=&d" (old), "=&d" (new), "=Q" (sem->count) + : "Q" (sem->count), "d" (delta) : "cc", "memory"); return new; } diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h index 52a779c337e8..9ab6bd3a65d1 100644 --- a/arch/s390/include/asm/setup.h +++ b/arch/s390/include/asm/setup.h @@ -14,14 +14,14 @@ #ifdef __KERNEL__ -#include <asm/lowcore.h> -#include <asm/types.h> - #define PARMAREA 0x10400 #define MEMORY_CHUNKS 256 #ifndef __ASSEMBLY__ +#include <asm/lowcore.h> +#include <asm/types.h> + #ifndef __s390x__ #define IPL_DEVICE (*(unsigned long *) (0x10404)) #define INITRD_START (*(unsigned long *) (0x1040C)) @@ -71,9 +71,12 @@ extern unsigned int user_mode; #define MACHINE_FLAG_KVM (1UL << 9) #define MACHINE_FLAG_HPAGE (1UL << 10) #define MACHINE_FLAG_PFMF (1UL << 11) +#define MACHINE_FLAG_LPAR (1UL << 12) #define MACHINE_IS_VM (S390_lowcore.machine_flags & MACHINE_FLAG_VM) #define MACHINE_IS_KVM (S390_lowcore.machine_flags & MACHINE_FLAG_KVM) +#define MACHINE_IS_LPAR (S390_lowcore.machine_flags & MACHINE_FLAG_LPAR) + #define MACHINE_HAS_DIAG9C (S390_lowcore.machine_flags & MACHINE_FLAG_DIAG9C) #ifndef __s390x__ diff --git a/arch/s390/include/asm/sigp.h b/arch/s390/include/asm/sigp.h index f72d611f7e13..e3bffd4e2d66 100644 --- a/arch/s390/include/asm/sigp.h +++ b/arch/s390/include/asm/sigp.h @@ -1,24 +1,19 @@ /* - * include/asm-s390/sigp.h + * Routines and structures for signalling other processors. * - * S390 version - * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation - * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), - * Martin Schwidefsky (schwidefsky@de.ibm.com) - * Heiko Carstens (heiko.carstens@de.ibm.com) - * - * sigp.h by D.J. Barrow (c) IBM 1999 - * contains routines / structures for signalling other S/390 processors in an - * SMP configuration. + * Copyright IBM Corp. 1999,2010 + * Author(s): Denis Joseph Barrow, + * Martin Schwidefsky <schwidefsky@de.ibm.com>, + * Heiko Carstens <heiko.carstens@de.ibm.com>, */ -#ifndef __SIGP__ -#define __SIGP__ +#ifndef __ASM_SIGP_H +#define __ASM_SIGP_H #include <asm/system.h> -/* get real cpu address from logical cpu number */ -extern int __cpu_logical_map[]; +/* Get real cpu address from logical cpu number. */ +extern unsigned short __cpu_logical_map[]; static inline int cpu_logical_map(int cpu) { @@ -29,107 +24,108 @@ static inline int cpu_logical_map(int cpu) #endif } -typedef enum -{ - sigp_unassigned=0x0, - sigp_sense, - sigp_external_call, - sigp_emergency_signal, - sigp_start, - sigp_stop, - sigp_restart, - sigp_unassigned1, - sigp_unassigned2, - sigp_stop_and_store_status, - sigp_unassigned3, - sigp_initial_cpu_reset, - sigp_cpu_reset, - sigp_set_prefix, - sigp_store_status_at_address, - sigp_store_extended_status_at_address -} sigp_order_code; - -typedef __u32 sigp_status_word; - -typedef enum -{ - sigp_order_code_accepted=0, - sigp_status_stored, - sigp_busy, - sigp_not_operational -} sigp_ccode; - +enum { + sigp_sense = 1, + sigp_external_call = 2, + sigp_emergency_signal = 3, + sigp_start = 4, + sigp_stop = 5, + sigp_restart = 6, + sigp_stop_and_store_status = 9, + sigp_initial_cpu_reset = 11, + sigp_cpu_reset = 12, + sigp_set_prefix = 13, + sigp_store_status_at_address = 14, + sigp_store_extended_status_at_address = 15, + sigp_set_architecture = 18, + sigp_conditional_emergency_signal = 19, + sigp_sense_running = 21, +}; + +enum { + sigp_order_code_accepted = 0, + sigp_status_stored = 1, + sigp_busy = 2, + sigp_not_operational = 3, +}; /* - * Definitions for the external call + * Definitions for external call. */ - -/* 'Bit' signals, asynchronous */ -typedef enum -{ - ec_schedule=0, +enum { + ec_schedule = 0, ec_call_function, ec_call_function_single, - ec_bit_last -} ec_bit_sig; +}; /* - * Signal processor + * Signal processor. */ -static inline sigp_ccode -signal_processor(__u16 cpu_addr, sigp_order_code order_code) +static inline int raw_sigp(u16 cpu, int order) { register unsigned long reg1 asm ("1") = 0; - sigp_ccode ccode; + int ccode; asm volatile( " sigp %1,%2,0(%3)\n" " ipm %0\n" " srl %0,28\n" : "=d" (ccode) - : "d" (reg1), "d" (cpu_logical_map(cpu_addr)), - "a" (order_code) : "cc" , "memory"); + : "d" (reg1), "d" (cpu), + "a" (order) : "cc" , "memory"); return ccode; } /* - * Signal processor with parameter + * Signal processor with parameter. */ -static inline sigp_ccode -signal_processor_p(__u32 parameter, __u16 cpu_addr, sigp_order_code order_code) +static inline int raw_sigp_p(u32 parameter, u16 cpu, int order) { register unsigned int reg1 asm ("1") = parameter; - sigp_ccode ccode; + int ccode; asm volatile( " sigp %1,%2,0(%3)\n" " ipm %0\n" " srl %0,28\n" : "=d" (ccode) - : "d" (reg1), "d" (cpu_logical_map(cpu_addr)), - "a" (order_code) : "cc" , "memory"); + : "d" (reg1), "d" (cpu), + "a" (order) : "cc" , "memory"); return ccode; } /* - * Signal processor with parameter and return status + * Signal processor with parameter and return status. */ -static inline sigp_ccode -signal_processor_ps(__u32 *statusptr, __u32 parameter, __u16 cpu_addr, - sigp_order_code order_code) +static inline int raw_sigp_ps(u32 *status, u32 parm, u16 cpu, int order) { - register unsigned int reg1 asm ("1") = parameter; - sigp_ccode ccode; + register unsigned int reg1 asm ("1") = parm; + int ccode; asm volatile( " sigp %1,%2,0(%3)\n" " ipm %0\n" " srl %0,28\n" : "=d" (ccode), "+d" (reg1) - : "d" (cpu_logical_map(cpu_addr)), "a" (order_code) + : "d" (cpu), "a" (order) : "cc" , "memory"); - *statusptr = reg1; + *status = reg1; return ccode; } -#endif /* __SIGP__ */ +static inline int sigp(int cpu, int order) +{ + return raw_sigp(cpu_logical_map(cpu), order); +} + +static inline int sigp_p(u32 parameter, int cpu, int order) +{ + return raw_sigp_p(parameter, cpu_logical_map(cpu), order); +} + +static inline int sigp_ps(u32 *status, u32 parm, int cpu, int order) +{ + return raw_sigp_ps(status, parm, cpu_logical_map(cpu), order); +} + +#endif /* __ASM_SIGP_H */ diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h index 2ab1141eeb50..edc03cb9cd79 100644 --- a/arch/s390/include/asm/smp.h +++ b/arch/s390/include/asm/smp.h @@ -29,7 +29,43 @@ extern int smp_cpu_polarization[]; extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); -extern union save_area *zfcpdump_save_areas[NR_CPUS + 1]; +extern struct save_area *zfcpdump_save_areas[NR_CPUS + 1]; + +extern void smp_switch_to_ipl_cpu(void (*func)(void *), void *); +extern void smp_switch_to_cpu(void (*)(void *), void *, unsigned long sp, + int from, int to); +extern void smp_restart_cpu(void); + +/* + * returns 1 if (virtual) cpu is scheduled + * returns 0 otherwise + */ +static inline int smp_vcpu_scheduled(int cpu) +{ + u32 status; + + switch (sigp_ps(&status, 0, cpu, sigp_sense_running)) { + case sigp_status_stored: + /* Check for running status */ + if (status & 0x400) + return 0; + break; + case sigp_not_operational: + return 0; + default: + break; + } + return 1; +} + +#else /* CONFIG_SMP */ + +static inline void smp_switch_to_ipl_cpu(void (*func)(void *), void *data) +{ + func(data); +} + +#define smp_vcpu_scheduled (1) #endif /* CONFIG_SMP */ diff --git a/arch/s390/include/asm/spinlock.h b/arch/s390/include/asm/spinlock.h index a587907d77f3..56612fc8186e 100644 --- a/arch/s390/include/asm/spinlock.h +++ b/arch/s390/include/asm/spinlock.h @@ -13,8 +13,6 @@ #include <linux/smp.h> -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) - static inline int _raw_compare_and_swap(volatile unsigned int *lock, unsigned int old, unsigned int new) @@ -27,22 +25,6 @@ _raw_compare_and_swap(volatile unsigned int *lock, return old; } -#else /* __GNUC__ */ - -static inline int -_raw_compare_and_swap(volatile unsigned int *lock, - unsigned int old, unsigned int new) -{ - asm volatile( - " cs %0,%3,0(%4)" - : "=d" (old), "=m" (*lock) - : "0" (old), "d" (new), "a" (lock), "m" (*lock) - : "cc", "memory" ); - return old; -} - -#endif /* __GNUC__ */ - /* * Simple spin lock operations. There are two variants, one clears IRQ's * on the local processor, one does not. diff --git a/arch/s390/include/asm/swab.h b/arch/s390/include/asm/swab.h index eb18dc1f327b..6bdee21c077e 100644 --- a/arch/s390/include/asm/swab.h +++ b/arch/s390/include/asm/swab.h @@ -47,11 +47,11 @@ static inline __u32 __arch_swab32p(const __u32 *x) asm volatile( #ifndef __s390x__ - " icm %0,8,3(%1)\n" - " icm %0,4,2(%1)\n" - " icm %0,2,1(%1)\n" - " ic %0,0(%1)" - : "=&d" (result) : "a" (x), "m" (*x) : "cc"); + " icm %0,8,%O1+3(%R1)\n" + " icm %0,4,%O1+2(%R1)\n" + " icm %0,2,%O1+1(%R1)\n" + " ic %0,%1" + : "=&d" (result) : "Q" (*x) : "cc"); #else /* __s390x__ */ " lrv %0,%1" : "=d" (result) : "m" (*x)); @@ -77,9 +77,9 @@ static inline __u16 __arch_swab16p(const __u16 *x) asm volatile( #ifndef __s390x__ - " icm %0,2,1(%1)\n" - " ic %0,0(%1)\n" - : "=&d" (result) : "a" (x), "m" (*x) : "cc"); + " icm %0,2,%O+1(%R1)\n" + " ic %0,%1\n" + : "=&d" (result) : "Q" (*x) : "cc"); #else /* __s390x__ */ " lrvh %0,%1" : "=d" (result) : "m" (*x)); diff --git a/arch/s390/include/asm/syscall.h b/arch/s390/include/asm/syscall.h index e0a73d3eb837..8429686951f9 100644 --- a/arch/s390/include/asm/syscall.h +++ b/arch/s390/include/asm/syscall.h @@ -15,6 +15,13 @@ #include <linux/sched.h> #include <asm/ptrace.h> +/* + * The syscall table always contains 32 bit pointers since we know that the + * address of the function to be called is (way) below 4GB. So the "int" + * type here is what we want [need] for both 32 bit and 64 bit systems. + */ +extern const unsigned int sys_call_table[]; + static inline long syscall_get_nr(struct task_struct *task, struct pt_regs *regs) { diff --git a/arch/s390/include/asm/sysinfo.h b/arch/s390/include/asm/sysinfo.h index 9d70057d828c..22bdb2a0ee5f 100644 --- a/arch/s390/include/asm/sysinfo.h +++ b/arch/s390/include/asm/sysinfo.h @@ -87,7 +87,8 @@ struct sysinfo_2_2_2 { struct sysinfo_3_2_2 { char reserved_0[31]; - unsigned char count; + unsigned char :4; + unsigned char count:4; struct { char reserved_0[4]; unsigned short cpus_total; diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h index 379661d2f81a..67ee6c3c6bb3 100644 --- a/arch/s390/include/asm/system.h +++ b/arch/s390/include/asm/system.h @@ -24,65 +24,65 @@ extern struct task_struct *__switch_to(void *, void *); static inline void save_fp_regs(s390_fp_regs *fpregs) { asm volatile( - " std 0,8(%1)\n" - " std 2,24(%1)\n" - " std 4,40(%1)\n" - " std 6,56(%1)" - : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory"); + " std 0,%O0+8(%R0)\n" + " std 2,%O0+24(%R0)\n" + " std 4,%O0+40(%R0)\n" + " std 6,%O0+56(%R0)" + : "=Q" (*fpregs) : "Q" (*fpregs)); if (!MACHINE_HAS_IEEE) return; asm volatile( - " stfpc 0(%1)\n" - " std 1,16(%1)\n" - " std 3,32(%1)\n" - " std 5,48(%1)\n" - " std 7,64(%1)\n" - " std 8,72(%1)\n" - " std 9,80(%1)\n" - " std 10,88(%1)\n" - " std 11,96(%1)\n" - " std 12,104(%1)\n" - " std 13,112(%1)\n" - " std 14,120(%1)\n" - " std 15,128(%1)\n" - : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory"); + " stfpc %0\n" + " std 1,%O0+16(%R0)\n" + " std 3,%O0+32(%R0)\n" + " std 5,%O0+48(%R0)\n" + " std 7,%O0+64(%R0)\n" + " std 8,%O0+72(%R0)\n" + " std 9,%O0+80(%R0)\n" + " std 10,%O0+88(%R0)\n" + " std 11,%O0+96(%R0)\n" + " std 12,%O0+104(%R0)\n" + " std 13,%O0+112(%R0)\n" + " std 14,%O0+120(%R0)\n" + " std 15,%O0+128(%R0)\n" + : "=Q" (*fpregs) : "Q" (*fpregs)); } static inline void restore_fp_regs(s390_fp_regs *fpregs) { asm volatile( - " ld 0,8(%0)\n" - " ld 2,24(%0)\n" - " ld 4,40(%0)\n" - " ld 6,56(%0)" - : : "a" (fpregs), "m" (*fpregs)); + " ld 0,%O0+8(%R0)\n" + " ld 2,%O0+24(%R0)\n" + " ld 4,%O0+40(%R0)\n" + " ld 6,%O0+56(%R0)" + : : "Q" (*fpregs)); if (!MACHINE_HAS_IEEE) return; asm volatile( - " lfpc 0(%0)\n" - " ld 1,16(%0)\n" - " ld 3,32(%0)\n" - " ld 5,48(%0)\n" - " ld 7,64(%0)\n" - " ld 8,72(%0)\n" - " ld 9,80(%0)\n" - " ld 10,88(%0)\n" - " ld 11,96(%0)\n" - " ld 12,104(%0)\n" - " ld 13,112(%0)\n" - " ld 14,120(%0)\n" - " ld 15,128(%0)\n" - : : "a" (fpregs), "m" (*fpregs)); + " lfpc %0\n" + " ld 1,%O0+16(%R0)\n" + " ld 3,%O0+32(%R0)\n" + " ld 5,%O0+48(%R0)\n" + " ld 7,%O0+64(%R0)\n" + " ld 8,%O0+72(%R0)\n" + " ld 9,%O0+80(%R0)\n" + " ld 10,%O0+88(%R0)\n" + " ld 11,%O0+96(%R0)\n" + " ld 12,%O0+104(%R0)\n" + " ld 13,%O0+112(%R0)\n" + " ld 14,%O0+120(%R0)\n" + " ld 15,%O0+128(%R0)\n" + : : "Q" (*fpregs)); } static inline void save_access_regs(unsigned int *acrs) { - asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory"); + asm volatile("stam 0,15,%0" : "=Q" (*acrs)); } static inline void restore_access_regs(unsigned int *acrs) { - asm volatile("lam 0,15,0(%0)" : : "a" (acrs)); + asm volatile("lam 0,15,%0" : : "Q" (*acrs)); } #define switch_to(prev,next,last) do { \ @@ -139,48 +139,48 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size) shift = (3 ^ (addr & 3)) << 3; addr ^= addr & 3; asm volatile( - " l %0,0(%4)\n" + " l %0,%4\n" "0: lr 0,%0\n" " nr 0,%3\n" " or 0,%2\n" - " cs %0,0,0(%4)\n" + " cs %0,0,%4\n" " jl 0b\n" - : "=&d" (old), "=m" (*(int *) addr) - : "d" (x << shift), "d" (~(255 << shift)), "a" (addr), - "m" (*(int *) addr) : "memory", "cc", "0"); + : "=&d" (old), "=Q" (*(int *) addr) + : "d" (x << shift), "d" (~(255 << shift)), + "Q" (*(int *) addr) : "memory", "cc", "0"); return old >> shift; case 2: addr = (unsigned long) ptr; shift = (2 ^ (addr & 2)) << 3; addr ^= addr & 2; asm volatile( - " l %0,0(%4)\n" + " l %0,%4\n" "0: lr 0,%0\n" " nr 0,%3\n" " or 0,%2\n" - " cs %0,0,0(%4)\n" + " cs %0,0,%4\n" " jl 0b\n" - : "=&d" (old), "=m" (*(int *) addr) - : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr), - "m" (*(int *) addr) : "memory", "cc", "0"); + : "=&d" (old), "=Q" (*(int *) addr) + : "d" (x << shift), "d" (~(65535 << shift)), + "Q" (*(int *) addr) : "memory", "cc", "0"); return old >> shift; case 4: asm volatile( - " l %0,0(%3)\n" - "0: cs %0,%2,0(%3)\n" + " l %0,%3\n" + "0: cs %0,%2,%3\n" " jl 0b\n" - : "=&d" (old), "=m" (*(int *) ptr) - : "d" (x), "a" (ptr), "m" (*(int *) ptr) + : "=&d" (old), "=Q" (*(int *) ptr) + : "d" (x), "Q" (*(int *) ptr) : "memory", "cc"); return old; #ifdef __s390x__ case 8: asm volatile( - " lg %0,0(%3)\n" - "0: csg %0,%2,0(%3)\n" + " lg %0,%3\n" + "0: csg %0,%2,%3\n" " jl 0b\n" : "=&d" (old), "=m" (*(long *) ptr) - : "d" (x), "a" (ptr), "m" (*(long *) ptr) + : "d" (x), "Q" (*(long *) ptr) : "memory", "cc"); return old; #endif /* __s390x__ */ @@ -215,20 +215,20 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) shift = (3 ^ (addr & 3)) << 3; addr ^= addr & 3; asm volatile( - " l %0,0(%4)\n" + " l %0,%2\n" "0: nr %0,%5\n" " lr %1,%0\n" " or %0,%2\n" " or %1,%3\n" - " cs %0,%1,0(%4)\n" + " cs %0,%1,%2\n" " jnl 1f\n" " xr %1,%0\n" " nr %1,%5\n" " jnz 0b\n" "1:" - : "=&d" (prev), "=&d" (tmp) - : "d" (old << shift), "d" (new << shift), "a" (ptr), - "d" (~(255 << shift)) + : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr) + : "d" (old << shift), "d" (new << shift), + "d" (~(255 << shift)), "Q" (*(int *) ptr) : "memory", "cc"); return prev >> shift; case 2: @@ -236,33 +236,35 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) shift = (2 ^ (addr & 2)) << 3; addr ^= addr & 2; asm volatile( - " l %0,0(%4)\n" + " l %0,%2\n" "0: nr %0,%5\n" " lr %1,%0\n" " or %0,%2\n" " or %1,%3\n" - " cs %0,%1,0(%4)\n" + " cs %0,%1,%2\n" " jnl 1f\n" " xr %1,%0\n" " nr %1,%5\n" " jnz 0b\n" "1:" - : "=&d" (prev), "=&d" (tmp) - : "d" (old << shift), "d" (new << shift), "a" (ptr), - "d" (~(65535 << shift)) + : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr) + : "d" (old << shift), "d" (new << shift), + "d" (~(65535 << shift)), "Q" (*(int *) ptr) : "memory", "cc"); return prev >> shift; case 4: asm volatile( - " cs %0,%2,0(%3)\n" - : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr) + " cs %0,%3,%1\n" + : "=&d" (prev), "=Q" (*(int *) ptr) + : "0" (old), "d" (new), "Q" (*(int *) ptr) : "memory", "cc"); return prev; #ifdef __s390x__ case 8: asm volatile( - " csg %0,%2,0(%3)\n" - : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr) + " csg %0,%3,%1\n" + : "=&d" (prev), "=Q" (*(long *) ptr) + : "0" (old), "d" (new), "Q" (*(long *) ptr) : "memory", "cc"); return prev; #endif /* __s390x__ */ @@ -302,17 +304,17 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) #define __ctl_load(array, low, high) ({ \ typedef struct { char _[sizeof(array)]; } addrtype; \ asm volatile( \ - " lctlg %1,%2,0(%0)\n" \ - : : "a" (&array), "i" (low), "i" (high), \ - "m" (*(addrtype *)(&array))); \ + " lctlg %1,%2,%0\n" \ + : : "Q" (*(addrtype *)(&array)), \ + "i" (low), "i" (high)); \ }) #define __ctl_store(array, low, high) ({ \ typedef struct { char _[sizeof(array)]; } addrtype; \ asm volatile( \ - " stctg %2,%3,0(%1)\n" \ - : "=m" (*(addrtype *)(&array)) \ - : "a" (&array), "i" (low), "i" (high)); \ + " stctg %1,%2,%0\n" \ + : "=Q" (*(addrtype *)(&array)) \ + : "i" (low), "i" (high)); \ }) #else /* __s390x__ */ @@ -320,17 +322,17 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) #define __ctl_load(array, low, high) ({ \ typedef struct { char _[sizeof(array)]; } addrtype; \ asm volatile( \ - " lctl %1,%2,0(%0)\n" \ - : : "a" (&array), "i" (low), "i" (high), \ - "m" (*(addrtype *)(&array))); \ + " lctl %1,%2,%0\n" \ + : : "Q" (*(addrtype *)(&array)), \ + "i" (low), "i" (high)); \ }) #define __ctl_store(array, low, high) ({ \ typedef struct { char _[sizeof(array)]; } addrtype; \ asm volatile( \ - " stctl %2,%3,0(%1)\n" \ - : "=m" (*(addrtype *)(&array)) \ - : "a" (&array), "i" (low), "i" (high)); \ + " stctl %1,%2,%0\n" \ + : "=Q" (*(addrtype *)(&array)) \ + : "i" (low), "i" (high)); \ }) #endif /* __s390x__ */ diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h index 66069e736842..34f0873d6525 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -73,7 +73,7 @@ struct thread_info { /* how to get the thread information struct from C */ static inline struct thread_info *current_thread_info(void) { - return (struct thread_info *)((*(unsigned long *) __LC_KERNEL_STACK)-THREAD_SIZE); + return (struct thread_info *)(S390_lowcore.kernel_stack - THREAD_SIZE); } #define THREAD_SIZE_ORDER THREAD_ORDER diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h index 68d9fea34b4b..f174bdaa6b59 100644 --- a/arch/s390/include/asm/timex.h +++ b/arch/s390/include/asm/timex.h @@ -20,10 +20,10 @@ static inline int set_clock(__u64 time) int cc; asm volatile( - " sck 0(%2)\n" + " sck %1\n" " ipm %0\n" " srl %0,28\n" - : "=d" (cc) : "m" (time), "a" (&time) : "cc"); + : "=d" (cc) : "Q" (time) : "cc"); return cc; } @@ -32,21 +32,21 @@ static inline int store_clock(__u64 *time) int cc; asm volatile( - " stck 0(%2)\n" + " stck %1\n" " ipm %0\n" " srl %0,28\n" - : "=d" (cc), "=m" (*time) : "a" (time) : "cc"); + : "=d" (cc), "=Q" (*time) : : "cc"); return cc; } static inline void set_clock_comparator(__u64 time) { - asm volatile("sckc 0(%1)" : : "m" (time), "a" (&time)); + asm volatile("sckc %0" : : "Q" (time)); } static inline void store_clock_comparator(__u64 *time) { - asm volatile("stckc 0(%1)" : "=m" (*time) : "a" (time)); + asm volatile("stckc %0" : "=Q" (*time)); } #define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ @@ -57,11 +57,7 @@ static inline unsigned long long get_clock (void) { unsigned long long clk; -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) asm volatile("stck %0" : "=Q" (clk) : : "cc"); -#else /* __GNUC__ */ - asm volatile("stck 0(%1)" : "=m" (clk) : "a" (&clk) : "cc"); -#endif /* __GNUC__ */ return clk; } @@ -69,13 +65,7 @@ static inline unsigned long long get_clock_xt(void) { unsigned char clk[16]; -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) asm volatile("stcke %0" : "=Q" (clk) : : "cc"); -#else /* __GNUC__ */ - asm volatile("stcke 0(%1)" : "=m" (clk) - : "a" (clk) : "cc"); -#endif /* __GNUC__ */ - return *((unsigned long long *)&clk[1]); } diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h index cbf0a8745bf4..d6b1ed0ec52b 100644 --- a/arch/s390/include/asm/uaccess.h +++ b/arch/s390/include/asm/uaccess.h @@ -265,6 +265,12 @@ __copy_from_user(void *to, const void __user *from, unsigned long n) return uaccess.copy_from_user(n, from, to); } +extern void copy_from_user_overflow(void) +#ifdef CONFIG_DEBUG_STRICT_USER_COPY_CHECKS +__compiletime_warning("copy_from_user() buffer size is not provably correct") +#endif +; + /** * copy_from_user: - Copy a block of data from user space. * @to: Destination address, in kernel space. @@ -284,7 +290,13 @@ __copy_from_user(void *to, const void __user *from, unsigned long n) static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) { + unsigned int sz = __compiletime_object_size(to); + might_fault(); + if (unlikely(sz != -1 && sz < n)) { + copy_from_user_overflow(); + return n; + } if (access_ok(VERIFY_READ, from, n)) n = __copy_from_user(to, from, n); else diff --git a/arch/s390/include/asm/vdso.h b/arch/s390/include/asm/vdso.h index 7bdd7c8ebc91..4a76d9480cce 100644 --- a/arch/s390/include/asm/vdso.h +++ b/arch/s390/include/asm/vdso.h @@ -7,7 +7,7 @@ #define VDSO32_LBASE 0 #define VDSO64_LBASE 0 -#define VDSO_VERSION_STRING LINUX_2.6.26 +#define VDSO_VERSION_STRING LINUX_2.6.29 #ifndef __ASSEMBLY__ |