diff options
Diffstat (limited to '')
572 files changed, 43973 insertions, 5568 deletions
diff --git a/arch/arm/configs/da830_omapl137_defconfig b/arch/arm/configs/da830_omapl137_defconfig new file mode 100644 index 000000000000..7c8e38f5c5ab --- /dev/null +++ b/arch/arm/configs/da830_omapl137_defconfig @@ -0,0 +1,1254 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc2-davinci1 +# Wed May 13 15:33:29 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +CONFIG_ARCH_DAVINCI=y +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set +CONFIG_CP_INTC=y + +# +# TI DaVinci Implementations +# + +# +# DaVinci Core Type +# +# CONFIG_ARCH_DAVINCI_DM644x is not set +# CONFIG_ARCH_DAVINCI_DM646x is not set +# CONFIG_ARCH_DAVINCI_DM355 is not set +CONFIG_ARCH_DAVINCI_DA830=y + +# +# DaVinci Board Type +# +CONFIG_MACH_DAVINCI_DA830_EVM=y +CONFIG_DAVINCI_MUX=y +# CONFIG_DAVINCI_MUX_DEBUG is not set +# CONFIG_DAVINCI_MUX_WARNINGS is not set +CONFIG_DAVINCI_RESET_CLOCKS=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_CPU_DCACHE_WRITETHROUGH=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_LXT_PHY=y +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +CONFIG_LSI_ET1011C_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +CONFIG_TI_DAVINCI_EMAC=y +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=m +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_XTKBD=m +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_DAVINCI=y +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +CONFIG_GPIO_PCF857X=m + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_DAVINCI_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_SOC=m +CONFIG_SND_DAVINCI_SOC=m +CONFIG_SND_SOC_I2C_AND_SPI=m +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MUSB_PERIPHERAL is not set +# CONFIG_USB_MUSB_OTG is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/da850_omapl138_defconfig b/arch/arm/configs/da850_omapl138_defconfig new file mode 100644 index 000000000000..842a70b079bf --- /dev/null +++ b/arch/arm/configs/da850_omapl138_defconfig @@ -0,0 +1,1229 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-davinci1 +# Mon Jun 29 07:54:15 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +CONFIG_ARCH_DAVINCI=y +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set +CONFIG_CP_INTC=y + +# +# TI DaVinci Implementations +# + +# +# DaVinci Core Type +# +# CONFIG_ARCH_DAVINCI_DM644x is not set +# CONFIG_ARCH_DAVINCI_DM355 is not set +# CONFIG_ARCH_DAVINCI_DM646x is not set +# CONFIG_ARCH_DAVINCI_DA830 is not set +CONFIG_ARCH_DAVINCI_DA850=y +CONFIG_ARCH_DAVINCI_DA8XX=y +# CONFIG_ARCH_DAVINCI_DM365 is not set + +# +# DaVinci Board Type +# +CONFIG_MACH_DAVINCI_DA850_EVM=y +CONFIG_DAVINCI_MUX=y +# CONFIG_DAVINCI_MUX_DEBUG is not set +# CONFIG_DAVINCI_MUX_WARNINGS is not set +CONFIG_DAVINCI_RESET_CLOCKS=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_LXT_PHY=y +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +CONFIG_LSI_ET1011C_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_TI_DAVINCI_EMAC is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=m +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_XTKBD=m +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_DAVINCI=y +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +CONFIG_GPIO_PCF857X=m + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_DAVINCI_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_SOC=m +CONFIG_SND_DAVINCI_SOC=m +CONFIG_SND_SOC_I2C_AND_SPI=m +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index ac18662f38cc..ddffe39d9f87 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc7 -# Tue May 26 07:24:28 2009 +# Linux kernel version: 2.6.31-rc3-davinci1 +# Fri Jul 17 08:26:52 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -9,7 +9,6 @@ CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y @@ -18,14 +17,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -62,8 +60,7 @@ CONFIG_FAIR_GROUP_SCHED=y CONFIG_USER_SCHED=y # CONFIG_CGROUP_SCHED is not set # CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y @@ -80,7 +77,6 @@ CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -93,8 +89,13 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y + +# +# Performance Counters +# CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y +# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -106,6 +107,11 @@ CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set # CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y @@ -118,7 +124,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y -# CONFIG_LBD is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -145,13 +151,14 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -160,26 +167,27 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MSM is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set CONFIG_ARCH_DAVINCI=y # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_W90X900 is not set CONFIG_AINTC=y +CONFIG_ARCH_DAVINCI_DMx=y # # TI DaVinci Implementations @@ -191,6 +199,9 @@ CONFIG_AINTC=y CONFIG_ARCH_DAVINCI_DM644x=y CONFIG_ARCH_DAVINCI_DM355=y CONFIG_ARCH_DAVINCI_DM646x=y +# CONFIG_ARCH_DAVINCI_DA830 is not set +# CONFIG_ARCH_DAVINCI_DA850 is not set +CONFIG_ARCH_DAVINCI_DM365=y # # DaVinci Board Type @@ -200,6 +211,7 @@ CONFIG_MACH_SFFSDR=y CONFIG_MACH_DAVINCI_DM355_EVM=y CONFIG_MACH_DM355_LEOPARD=y CONFIG_MACH_DAVINCI_DM6467_EVM=y +CONFIG_MACH_DAVINCI_DM365_EVM=y CONFIG_DAVINCI_MUX=y CONFIG_DAVINCI_MUX_DEBUG=y CONFIG_DAVINCI_MUX_WARNINGS=y @@ -227,7 +239,6 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_CPU_CACHE_ROUND_ROBIN is not set -# CONFIG_OUTER_CACHE is not set CONFIG_COMMON_CLKDEV=y # @@ -252,7 +263,6 @@ CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set @@ -268,12 +278,13 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096 CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y CONFIG_HAVE_MLOCK=y CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_LEDS=y # CONFIG_LEDS_CPU is not set CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set # # Boot options @@ -415,6 +426,7 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set @@ -553,6 +565,7 @@ CONFIG_BLK_DEV_RAM_SIZE=32768 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -564,6 +577,7 @@ CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_AT24=y # CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y CONFIG_IDE=m @@ -609,10 +623,6 @@ CONFIG_BLK_DEV_SD=m # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -637,7 +647,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -684,6 +693,7 @@ CONFIG_DM9000_DEBUGLEVEL=4 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set +# CONFIG_KS8842 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -748,18 +758,21 @@ CONFIG_INPUT_EVBUG=m # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ATKBD=m -# CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_STOWAWAY is not set -CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_XTKBD=m # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_AD7879_I2C is not set # CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_EETI is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set @@ -773,6 +786,7 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set # CONFIG_INPUT_MISC is not set # @@ -832,6 +846,7 @@ CONFIG_I2C_HELPER_AUTO=y # I2C system bus drivers (mostly embedded / system-on-chip) # CONFIG_I2C_DAVINCI=y +# CONFIG_I2C_DESIGNWARE is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_SIMTEC is not set @@ -854,7 +869,6 @@ CONFIG_I2C_DAVINCI=y # # CONFIG_DS1682 is not set # CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -935,6 +949,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set @@ -986,52 +1001,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_PCF50633 is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=y - -# -# Multimedia drivers -# -# CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=y -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=y -CONFIG_MEDIA_TUNER_TDA8290=y -CONFIG_MEDIA_TUNER_TDA9887=y -CONFIG_MEDIA_TUNER_TEA5761=y -CONFIG_MEDIA_TUNER_TEA5767=y -CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_XC2028=y -CONFIG_MEDIA_TUNER_XC5000=y -CONFIG_MEDIA_TUNER_MC44S803=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_SOC_CAMERA is not set -# CONFIG_V4L_USB_DRIVERS is not set -# CONFIG_RADIO_ADAPTERS is not set -CONFIG_DAB=y -# CONFIG_USB_DABUSB is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support @@ -1102,6 +1073,11 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set # CONFIG_SND_MTPAV is not set @@ -1112,9 +1088,16 @@ CONFIG_SND_USB=y # CONFIG_SND_USB_AUDIO is not set # CONFIG_SND_USB_CAIAQ is not set CONFIG_SND_SOC=m -# CONFIG_SND_DAVINCI_SOC is not set +CONFIG_SND_DAVINCI_SOC=m +CONFIG_SND_DAVINCI_SOC_I2S=m +CONFIG_SND_DAVINCI_SOC_MCASP=m +CONFIG_SND_DAVINCI_SOC_EVM=m +CONFIG_SND_DM6467_SOC_EVM=m +# CONFIG_SND_DAVINCI_SOC_SFFSDR is not set CONFIG_SND_SOC_I2C_AND_SPI=m # CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TLV320AIC3X=m # CONFIG_SOUND_PRIME is not set CONFIG_HID_SUPPORT=y CONFIG_HID=m @@ -1143,7 +1126,7 @@ CONFIG_HID_BELKIN=m CONFIG_HID_CHERRY=m CONFIG_HID_CHICONY=m CONFIG_HID_CYPRESS=m -# CONFIG_DRAGONRISE_FF is not set +# CONFIG_HID_DRAGONRISE is not set CONFIG_HID_EZKEY=m # CONFIG_HID_KYE is not set CONFIG_HID_GYRATION=m @@ -1160,10 +1143,11 @@ CONFIG_HID_PETALYNX=m CONFIG_HID_SAMSUNG=m CONFIG_HID_SONY=m CONFIG_HID_SUNPLUS=m -# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set # CONFIG_HID_TOPSEED is not set -# CONFIG_THRUSTMASTER_FF is not set -# CONFIG_ZEROPLUS_FF is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set @@ -1266,6 +1250,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set @@ -1285,17 +1270,20 @@ CONFIG_USB_GADGET_SELECTED=y # CONFIG_USB_GADGET_OMAP is not set # CONFIG_USB_GADGET_PXA25X is not set # CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set # CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set # CONFIG_USB_GADGET_M66592 is not set # CONFIG_USB_GADGET_AMD5536UDC is not set # CONFIG_USB_GADGET_FSL_QE is not set # CONFIG_USB_GADGET_CI13XXX is not set # CONFIG_USB_GADGET_NET2280 is not set # CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set CONFIG_USB_ETH=m CONFIG_USB_ETH_RNDIS=y CONFIG_USB_GADGETFS=m @@ -1311,7 +1299,7 @@ CONFIG_USB_CDC_COMPOSITE=m # CONFIG_USB_OTG_UTILS=y # CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set +CONFIG_NOP_USB_XCEIV=m CONFIG_MMC=m # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set @@ -1328,7 +1316,6 @@ CONFIG_MMC_BLOCK=m # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_DAVINCI is not set # CONFIG_MEMSTICK is not set # CONFIG_ACCESSIBILITY is not set CONFIG_NEW_LEDS=y @@ -1340,7 +1327,7 @@ CONFIG_LEDS_CLASS=m # CONFIG_LEDS_PCA9532 is not set CONFIG_LEDS_GPIO=m CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_BD2802 is not set @@ -1386,6 +1373,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers @@ -1433,14 +1421,16 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set -CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set # CONFIG_XFS_RT is not set # CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1623,6 +1613,7 @@ CONFIG_TIMER_STATS=y # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set CONFIG_DEBUG_PREEMPT=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_PI_LIST=y @@ -1654,18 +1645,16 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_PAGE_POISONING is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# +CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set # CONFIG_STACK_TRACER is not set # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig new file mode 100644 index 000000000000..8da75dede52e --- /dev/null +++ b/arch/arm/configs/n8x0_defconfig @@ -0,0 +1,1104 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31-rc5 +# Thu Aug 6 22:17:23 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +# CONFIG_CLASSIC_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y + +# +# TI OMAP Implementations +# +CONFIG_ARCH_OMAP_OTG=y +# CONFIG_ARCH_OMAP1 is not set +CONFIG_ARCH_OMAP2=y +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set + +# +# OMAP Feature Selections +# +# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set +# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set +CONFIG_OMAP_RESET_CLOCKS=y +# CONFIG_OMAP_MUX is not set +# CONFIG_OMAP_MCBSP is not set +CONFIG_OMAP_MBOX_FWK=y +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_32K_TIMER_HZ=128 +CONFIG_OMAP_DM_TIMER=y +# CONFIG_OMAP_LL_DEBUG_UART1 is not set +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +CONFIG_OMAP_LL_DEBUG_UART3=y +# CONFIG_MACH_OMAP_GENERIC is not set + +# +# OMAP Core Type +# +CONFIG_ARCH_OMAP24XX=y +CONFIG_ARCH_OMAP2420=y +# CONFIG_ARCH_OMAP2430 is not set + +# +# OMAP Board Type +# +CONFIG_MACH_OMAP2_TUSB6010=y +# CONFIG_MACH_OMAP_H4 is not set +# CONFIG_MACH_OMAP_APOLLON is not set +# CONFIG_MACH_OMAP_2430SDP is not set +CONFIG_MACH_NOKIA_N8X0=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_ARM_ERRATA_411920 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=128 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_LEDS=y +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x10C08000 +CONFIG_ZBOOT_ROM_BSS=0x10200000 +# CONFIG_ZBOOT_ROM is not set +CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 console=ttyS0,115200n8" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_OLD_REGULATORY is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +CONFIG_HAVE_MTD_OTP=y +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +CONFIG_MTD_ONENAND=y +# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set +# CONFIG_MTD_ONENAND_GENERIC is not set +CONFIG_MTD_ONENAND_OMAP2=y +CONFIG_MTD_ONENAND_OTP=y +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set +# CONFIG_MTD_ONENAND_SIM is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_OMAP24XX=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_TUSB6010=y +# CONFIG_USB_MUSB_HOST is not set +CONFIG_USB_MUSB_PERIPHERAL=y +# CONFIG_USB_MUSB_OTG is not set +CONFIG_USB_GADGET_MUSB_HDRC=y +# CONFIG_MUSB_PIO_ONLY is not set +# CONFIG_USB_INVENTRA_DMA is not set +# CONFIG_USB_TI_CPPI_DMA is not set +CONFIG_USB_TUSB_OMAP_DMA=y +CONFIG_USB_MUSB_DEBUG=y + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=y +# CONFIG_USB_ETH_RNDIS is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +CONFIG_NOP_USB_XCEIV=y +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig index 4c6fb7e959df..51c0fa8897cd 100644 --- a/arch/arm/configs/omap3_beagle_defconfig +++ b/arch/arm/configs/omap3_beagle_defconfig @@ -128,6 +128,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y # # System Type @@ -236,6 +237,7 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y # CONFIG_OUTER_CACHE is not set +CONFIG_COMMON_CLKDEV=y # # Bus support @@ -317,7 +319,12 @@ CONFIG_BINFMT_MISC=y # # Power management options # -# CONFIG_PM is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y @@ -713,6 +720,7 @@ CONFIG_GPIOLIB=y # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +CONFIG_GPIO_TWL4030=y # # PCI GPIO expanders: @@ -741,6 +749,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +CONFIG_TWL4030_CORE=y # CONFIG_UCB1400_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set @@ -787,7 +796,7 @@ CONFIG_DUMMY_CONSOLE=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set @@ -798,7 +807,8 @@ CONFIG_USB=y CONFIG_USB_DEVICEFS=y CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y @@ -806,6 +816,8 @@ CONFIG_USB_MON=y # # USB Host Controller Drivers # +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y # CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set @@ -818,10 +830,10 @@ CONFIG_USB_MUSB_SOC=y # # OMAP 343x high speed USB support # -CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_PERIPHERAL is not set -# CONFIG_USB_MUSB_OTG is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y CONFIG_USB_MUSB_HDRC_HCD=y # CONFIG_MUSB_PIO_ONLY is not set CONFIG_USB_INVENTRA_DMA=y @@ -887,8 +899,8 @@ CONFIG_USB_GADGET_SELECTED=y # CONFIG_USB_GADGET_FSL_USB2 is not set # CONFIG_USB_GADGET_NET2280 is not set # CONFIG_USB_GADGET_PXA25X is not set -CONFIG_USB_GADGET_M66592=y -CONFIG_USB_M66592=y +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_M66592 is not set # CONFIG_USB_GADGET_PXA27X is not set # CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LH7A40X is not set @@ -906,6 +918,15 @@ CONFIG_USB_ETH_RNDIS=y # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set # CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_ISP1301_OMAP is not set +CONFIG_TWL4030_USB=y +# CONFIG_NOP_USB_XCEIV is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set @@ -923,6 +944,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # # CONFIG_MMC_SDHCI is not set # CONFIG_MMC_OMAP is not set +CONFIG_MMC_OMAP_HS=y # CONFIG_MEMSTICK is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_NEW_LEDS is not set @@ -981,10 +1003,11 @@ CONFIG_RTC_INTF_DEV=y # # Voltage and Current regulators # -# CONFIG_REGULATOR is not set +CONFIG_REGULATOR=y # CONFIG_REGULATOR_FIXED_VOLTAGE is not set # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_BQ24022 is not set +CONFIG_REGULATOR_TWL4030=y # CONFIG_UIO is not set # diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig index 8fb918d9ba65..9a510eab75a6 100644 --- a/arch/arm/configs/omap_3430sdp_defconfig +++ b/arch/arm/configs/omap_3430sdp_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.29-rc8 -# Fri Mar 13 14:17:01 2009 +# Linux kernel version: 2.6.30-omap1 +# Tue Jun 23 10:36:45 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -197,9 +197,9 @@ CONFIG_OMAP_MCBSP=y CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set +CONFIG_OMAP_LL_DEBUG_UART1=y # CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y +# CONFIG_OMAP_LL_DEBUG_UART3 is not set CONFIG_OMAP_SERIAL_WAKE=y CONFIG_ARCH_OMAP34XX=y CONFIG_ARCH_OMAP3430=y @@ -207,10 +207,10 @@ CONFIG_ARCH_OMAP3430=y # # OMAP Board Type # -CONFIG_MACH_OMAP3_BEAGLE=y -CONFIG_MACH_OMAP_LDP=y -CONFIG_MACH_OVERO=y -CONFIG_MACH_OMAP3_PANDORA=y +# CONFIG_MACH_OMAP3_BEAGLE is not set +# CONFIG_MACH_OMAP_LDP is not set +# CONFIG_MACH_OVERO is not set +# CONFIG_MACH_OMAP3_PANDORA is not set CONFIG_MACH_OMAP_3430SDP=y # @@ -950,7 +950,7 @@ CONFIG_SPI_OMAP24XX=y # CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y -CONFIG_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y # @@ -1370,7 +1370,7 @@ CONFIG_SND_OMAP_SOC=y CONFIG_SND_OMAP_SOC_MCBSP=y # CONFIG_SND_OMAP_SOC_OVERO is not set CONFIG_SND_OMAP_SOC_SDP3430=y -CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y +# CONFIG_SND_OMAP_SOC_OMAP3_PANDORA is not set CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ALL_CODECS is not set CONFIG_SND_SOC_TWL4030=y diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig index 213fe9c5eaae..f1739fae7ed4 100644 --- a/arch/arm/configs/omap_zoom2_defconfig +++ b/arch/arm/configs/omap_zoom2_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc5 -# Fri Oct 10 11:49:41 2008 +# Linux kernel version: 2.6.30-omap1 +# Fri Jun 12 17:25:46 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -22,8 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_SUPPORTS_AOUT=y -CONFIG_ZONE_DMA=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -39,44 +37,61 @@ CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set CONFIG_GROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y # CONFIG_RT_GROUP_SCHED is not set CONFIG_USER_SCHED=y # CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_UID16=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_EXTRA_PASS=y +# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -84,19 +99,13 @@ CONFIG_SLAB=y # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -104,11 +113,8 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -124,7 +130,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" -CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y # # System Type @@ -134,10 +140,10 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set @@ -158,14 +164,17 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_ORION5X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MMP is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_MSM7X00A is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set # # TI OMAP Implementations @@ -174,6 +183,7 @@ CONFIG_ARCH_OMAP_OTG=y # CONFIG_ARCH_OMAP1 is not set # CONFIG_ARCH_OMAP2 is not set CONFIG_ARCH_OMAP3=y +# CONFIG_ARCH_OMAP4 is not set # # OMAP Feature Selections @@ -185,6 +195,7 @@ CONFIG_OMAP_MUX=y CONFIG_OMAP_MUX_DEBUG=y CONFIG_OMAP_MUX_WARNINGS=y CONFIG_OMAP_MCBSP=y +# CONFIG_OMAP_MBOX_FWK is not set # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 @@ -192,25 +203,20 @@ CONFIG_OMAP_DM_TIMER=y # CONFIG_OMAP_LL_DEBUG_UART1 is not set # CONFIG_OMAP_LL_DEBUG_UART2 is not set CONFIG_OMAP_LL_DEBUG_UART3=y -CONFIG_OMAP_SERIAL_WAKE=y CONFIG_ARCH_OMAP34XX=y CONFIG_ARCH_OMAP3430=y # # OMAP Board Type # -# CONFIG_MACH_OMAP3_BEAGLE is not set +# CONFIG_MACH_NOKIA_RX51 is not set # CONFIG_MACH_OMAP_LDP is not set -CONFIG_MACH_OMAP_ZOOM2=y +# CONFIG_MACH_OMAP_3430SDP is not set +# CONFIG_MACH_OMAP3EVM is not set +# CONFIG_MACH_OMAP3_BEAGLE is not set # CONFIG_MACH_OVERO is not set - -# -# Boot options -# - -# -# Power management -# +# CONFIG_MACH_OMAP3_PANDORA is not set +CONFIG_MACH_OMAP_ZOOM2=y # # Processor Type @@ -239,6 +245,10 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y # CONFIG_OUTER_CACHE is not set +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y # # Bus support @@ -254,26 +264,32 @@ CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 # CONFIG_PREEMPT is not set CONFIG_HZ=128 CONFIG_AEABI=y CONFIG_OABI_COMPAT=y -CONFIG_ARCH_FLATMEM_HAS_HOLES=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y # CONFIG_LEDS is not set CONFIG_ALIGNMENT_TRAP=y @@ -287,9 +303,10 @@ CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.16 # CONFIG_KEXEC is not set # -# CPU Frequency scaling +# CPU Power Management # # CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set # # Floating point emulation @@ -309,13 +326,23 @@ CONFIG_VFPv3=y # Userspace binary formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_MISC=y # # Power management options # -# CONFIG_PM is not set +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_VERBOSE=y +CONFIG_CAN_PM_TRACE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y @@ -378,7 +405,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set # # Network testing @@ -389,8 +418,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_PHONET is not set # CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -416,14 +445,28 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set CONFIG_MISC_DEVICES=y -# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_OMAP_STI is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -461,14 +504,20 @@ CONFIG_SCSI_WAIT_SCAN=m # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -501,8 +550,10 @@ CONFIG_MII=y # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set # CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set # CONFIG_SMC911X is not set CONFIG_SMSC911X=y +# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -519,7 +570,10 @@ CONFIG_NETDEV_10000=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# # # USB Network Adapters @@ -561,17 +615,25 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=y +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set # CONFIG_TOUCHSCREEN_PENMOUNT is not set # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC210X is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set # CONFIG_INPUT_MISC is not set # @@ -607,13 +669,15 @@ CONFIG_SERIAL_8250_RSA=y # # Non-8250 serial port support # +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y -# CONFIG_NVRAM is not set +# CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set @@ -639,6 +703,7 @@ CONFIG_I2C_OMAP=y # # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set # # Other I2C/SMBus bus drivers @@ -650,14 +715,11 @@ CONFIG_I2C_OMAP=y # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_LEGACY is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_ISP1301_OMAP is not set -# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_MADC is not set +# CONFIG_TWL4030_POWEROFF is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set @@ -672,12 +734,12 @@ CONFIG_SPI_MASTER=y # SPI Master Controller Drivers # # CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set CONFIG_SPI_OMAP24XX=y # # SPI Protocol Masters # -# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y @@ -686,11 +748,16 @@ CONFIG_GPIOLIB=y # CONFIG_GPIO_SYSFS is not set # +# Memory mapped GPIO expanders: +# + +# # I2C GPIO expanders: # # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +CONFIG_GPIO_TWL4030=y # # PCI GPIO expanders: @@ -702,26 +769,34 @@ CONFIG_GPIOLIB=y # CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MCP23S08 is not set CONFIG_W1=y +CONFIG_W1_CON=y # # 1-wire Bus Masters # +# CONFIG_W1_MASTER_DS2490 is not set # CONFIG_W1_MASTER_DS2482 is not set # CONFIG_W1_MASTER_DS1WM is not set # CONFIG_W1_MASTER_GPIO is not set +# CONFIG_HDQ_MASTER_OMAP is not set # # 1-wire Slaves # # CONFIG_W1_SLAVE_THERM is not set # CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2431 is not set # CONFIG_W1_SLAVE_DS2433 is not set # CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set # CONFIG_PDA_POWER is not set # CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_BQ27x00 is not set # CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_NOWAYOUT=y @@ -729,11 +804,17 @@ CONFIG_WATCHDOG_NOWAYOUT=y # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set +# CONFIG_OMAP_WATCHDOG is not set # -# Sonics Silicon Backplane +# USB-based Watchdog Cards # +# CONFIG_USBPCWATCHDOG is not set CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# # CONFIG_SSB is not set # @@ -741,12 +822,19 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +CONFIG_TWL4030_CORE=y # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set # # Multimedia devices @@ -756,12 +844,14 @@ CONFIG_SSB_POSSIBLE=y # Multimedia core support # # CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set # CONFIG_VIDEO_MEDIA is not set # # Multimedia drivers # CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set # # Graphics support @@ -782,10 +872,12 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set CONFIG_SND=y # CONFIG_SND_SEQUENCER is not set # CONFIG_SND_MIXER_OSS is not set # CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set # CONFIG_SND_DYNAMIC_MINORS is not set CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y @@ -798,19 +890,197 @@ CONFIG_SND_DRIVERS=y # CONFIG_SND_MPU401 is not set CONFIG_SND_ARM=y CONFIG_SND_SPI=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set # CONFIG_SND_SOC is not set # CONFIG_SOUND_PRIME is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set -# CONFIG_USB_SUPPORT is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SOC=y + +# +# OMAP 343x high speed USB support +# +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MUSB_PERIPHERAL is not set +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_MUSB_HDRC_HCD=y +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_USB_INVENTRA_DMA=y +# CONFIG_USB_TI_CPPI_DMA is not set +CONFIG_USB_MUSB_DEBUG=y + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=y +# CONFIG_USB_ZERO_HNPTEST is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_ISP1301_OMAP is not set +CONFIG_TWL4030_USB=y +# CONFIG_NOP_USB_XCEIV is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set # -# MMC/SD Card Drivers +# MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y @@ -818,11 +1088,13 @@ CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_MMC_TEST is not set # -# MMC/SD Host Controller Drivers +# MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set +CONFIG_MMC_OMAP_HS=y # CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_NEW_LEDS is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y @@ -852,43 +1124,55 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_TWL4030 is not set # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set # # SPI RTC drivers # # CONFIG_RTC_DRV_M41T94 is not set # CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set # # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # # CONFIG_DMADEVICES is not set - -# -# Voltage and Current regulators -# -# CONFIG_REGULATOR is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set # CONFIG_REGULATOR_FIXED_VOLTAGE is not set # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_BQ24022 is not set +CONFIG_REGULATOR_TWL4030=y # CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# CBUS support +# +# CONFIG_CBUS is not set # # File systems @@ -897,18 +1181,24 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_QUOTA_TREE=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y @@ -917,6 +1207,11 @@ CONFIG_QUOTACTL=y # CONFIG_FUSE_FS is not set # +# Caches +# +# CONFIG_FSCACHE is not set + +# # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set @@ -937,15 +1232,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -954,6 +1247,7 @@ CONFIG_TMPFS=y # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -962,6 +1256,7 @@ CONFIG_TMPFS=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y @@ -975,7 +1270,6 @@ CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1045,6 +1339,7 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set # # Kernel hacking @@ -1062,6 +1357,9 @@ CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set @@ -1084,21 +1382,36 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y # CONFIG_DEBUG_USER is not set # CONFIG_DEBUG_ERRORS is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -1110,17 +1423,28 @@ CONFIG_DEBUG_LL=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set @@ -1152,7 +1476,7 @@ CONFIG_CRYPTO_PCBC=m # # Digest # -# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set @@ -1189,15 +1513,21 @@ CONFIG_CRYPTO_DES=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1205,7 +1535,9 @@ CONFIG_CRC_T10DIF=y CONFIG_CRC32=y # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y -CONFIG_PLIST=y +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig index f238df66efd4..e7e31332c62a 100644 --- a/arch/arm/configs/rx51_defconfig +++ b/arch/arm/configs/rx51_defconfig @@ -1006,6 +1006,7 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set CONFIG_OMAP_WATCHDOG=m +CONFIG_TWL4030_WATCHDOG=m # # USB-based Watchdog Cards diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index be747f5c6cd8..40866c643f13 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -6,6 +6,9 @@ config AINTC config CP_INTC bool +config ARCH_DAVINCI_DMx + bool + menu "TI DaVinci Implementations" comment "DaVinci Core Type" @@ -13,20 +16,41 @@ comment "DaVinci Core Type" config ARCH_DAVINCI_DM644x bool "DaVinci 644x based system" select AINTC + select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM355 bool "DaVinci 355 based system" select AINTC + select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM646x bool "DaVinci 646x based system" select AINTC + select ARCH_DAVINCI_DMx + +config ARCH_DAVINCI_DA830 + bool "DA830/OMAP-L137 based system" + select CP_INTC + select ARCH_DAVINCI_DA8XX + +config ARCH_DAVINCI_DA850 + bool "DA850/OMAP-L138 based system" + select CP_INTC + select ARCH_DAVINCI_DA8XX + +config ARCH_DAVINCI_DA8XX + bool + +config ARCH_DAVINCI_DM365 + bool "DaVinci 365 based system" + select AINTC + select ARCH_DAVINCI_DMx comment "DaVinci Board Type" config MACH_DAVINCI_EVM bool "TI DM644x EVM" - default y + default ARCH_DAVINCI_DM644x depends on ARCH_DAVINCI_DM644x help Configure this option to specify the whether the board used @@ -41,6 +65,7 @@ config MACH_SFFSDR config MACH_DAVINCI_DM355_EVM bool "TI DM355 EVM" + default ARCH_DAVINCI_DM355 depends on ARCH_DAVINCI_DM355 help Configure this option to specify the whether the board used @@ -55,11 +80,33 @@ config MACH_DM355_LEOPARD config MACH_DAVINCI_DM6467_EVM bool "TI DM6467 EVM" + default ARCH_DAVINCI_DM646x depends on ARCH_DAVINCI_DM646x help Configure this option to specify the whether the board used for development is a DM6467 EVM +config MACH_DAVINCI_DM365_EVM + bool "TI DM365 EVM" + default ARCH_DAVINCI_DM365 + depends on ARCH_DAVINCI_DM365 + help + Configure this option to specify whether the board used + for development is a DM365 EVM + +config MACH_DAVINCI_DA830_EVM + bool "TI DA830/OMAP-L137 Reference Platform" + default ARCH_DAVINCI_DA830 + depends on ARCH_DAVINCI_DA830 + help + Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. + +config MACH_DAVINCI_DA850_EVM + bool "TI DA850/OMAP-L138 Reference Platform" + default ARCH_DAVINCI_DA850 + depends on ARCH_DAVINCI_DA850 + help + Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. config DAVINCI_MUX bool "DAVINCI multiplexing support" diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 059ab78084ba..2e11e847313b 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,14 +5,17 @@ # Common objects obj-y := time.o clock.o serial.o io.o psc.o \ - gpio.o devices.o dma.o usb.o common.o sram.o + gpio.o dma.o usb.o common.o sram.o obj-$(CONFIG_DAVINCI_MUX) += mux.o # Chip specific -obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o -obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o -obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o +obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o +obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o +obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o +obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o +obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o @@ -23,3 +26,6 @@ obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o +obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o +obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o +obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot index e1dd366f836b..db97ef2c6477 100644 --- a/arch/arm/mach-davinci/Makefile.boot +++ b/arch/arm/mach-davinci/Makefile.boot @@ -1,3 +1,13 @@ +ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y) +ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y) +$(error Cannot enable DaVinci and DA8XX platforms concurrently) +else + zreladdr-y := 0xc0008000 +params_phys-y := 0xc0000100 +initrd_phys-y := 0xc0800000 +endif +else zreladdr-y := 0x80008000 params_phys-y := 0x80000100 initrd_phys-y := 0x80800000 +endif diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c new file mode 100644 index 000000000000..bfbb63936f33 --- /dev/null +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -0,0 +1,157 @@ +/* + * TI DA830/OMAP L137 EVM board + * + * Author: Mark A. Greer <mgreer@mvista.com> + * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/i2c.h> +#include <linux/i2c/at24.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/common.h> +#include <mach/irqs.h> +#include <mach/cp_intc.h> +#include <mach/da8xx.h> +#include <mach/asp.h> + +#define DA830_EVM_PHY_MASK 0x0 +#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ + +static struct at24_platform_data da830_evm_i2c_eeprom_info = { + .byte_len = SZ_256K / 8, + .page_size = 64, + .flags = AT24_FLAG_ADDR16, + .setup = davinci_get_mac_addr, + .context = (void *)0x7f00, +}; + +static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { + { + I2C_BOARD_INFO("24c256", 0x50), + .platform_data = &da830_evm_i2c_eeprom_info, + }, + { + I2C_BOARD_INFO("tlv320aic3x", 0x18), + } +}; + +static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +static struct davinci_uart_config da830_evm_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static u8 da830_iis_serializer_direction[] = { + RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct snd_platform_data da830_evm_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), + .tdm_slots = 2, + .serial_dir = da830_iis_serializer_direction, + .eventq_no = EVENTQ_0, + .version = MCASP_VERSION_2, + .txnumevt = 1, + .rxnumevt = 1, +}; + +static __init void da830_evm_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + int ret; + + ret = da8xx_register_edma(); + if (ret) + pr_warning("da830_evm_init: edma registration failed: %d\n", + ret); + + ret = da8xx_pinmux_setup(da830_i2c0_pins); + if (ret) + pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n", + ret); + + ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata); + if (ret) + pr_warning("da830_evm_init: i2c0 registration failed: %d\n", + ret); + + soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK; + soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->rmii_en = 1; + + ret = da8xx_pinmux_setup(da830_cpgmac_pins); + if (ret) + pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n", + ret); + + ret = da8xx_register_emac(); + if (ret) + pr_warning("da830_evm_init: emac registration failed: %d\n", + ret); + + ret = da8xx_register_watchdog(); + if (ret) + pr_warning("da830_evm_init: watchdog registration failed: %d\n", + ret); + + davinci_serial_init(&da830_evm_uart_config); + i2c_register_board_info(1, da830_evm_i2c_devices, + ARRAY_SIZE(da830_evm_i2c_devices)); + + ret = da8xx_pinmux_setup(da830_mcasp1_pins); + if (ret) + pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n", + ret); + + da8xx_init_mcasp(1, &da830_evm_snd_data); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init da830_evm_console_init(void) +{ + return add_preferred_console("ttyS", 2, "115200"); +} +console_initcall(da830_evm_console_init); +#endif + +static __init void da830_evm_irq_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ, + soc_info->intc_irq_prios); +} + +static void __init da830_evm_map_io(void) +{ + da830_init(); +} + +MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP L137 EVM") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = da830_evm_map_io, + .init_irq = da830_evm_irq_init, + .timer = &davinci_timer, + .init_machine = da830_evm_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c new file mode 100644 index 000000000000..c759d72494e0 --- /dev/null +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -0,0 +1,415 @@ +/* + * TI DA850/OMAP-L138 EVM board + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/board-da830-evm.c + * Original Copyrights follow: + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/i2c.h> +#include <linux/i2c/at24.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/common.h> +#include <mach/irqs.h> +#include <mach/cp_intc.h> +#include <mach/da8xx.h> +#include <mach/nand.h> + +#define DA850_EVM_PHY_MASK 0x1 +#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ + +#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) +#define DA850_LCD_PWR_PIN GPIO_TO_PIN(8, 10) + +#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) +#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) + +static struct mtd_partition da850_evm_norflash_partition[] = { + { + .name = "NOR filesystem", + .offset = 0, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct physmap_flash_data da850_evm_norflash_data = { + .width = 2, + .parts = da850_evm_norflash_partition, + .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition), +}; + +static struct resource da850_evm_norflash_resource[] = { + { + .start = DA8XX_AEMIF_CS2_BASE, + .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da850_evm_norflash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &da850_evm_norflash_data, + }, + .num_resources = 1, + .resource = da850_evm_norflash_resource, +}; + +/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash + * (128K blocks). It may be used instead of the (default) SPI flash + * to boot, using TI's tools to install the secondary boot loader + * (UBL) and U-Boot. + */ +struct mtd_partition da850_evm_nandflash_partition[] = { + { + .name = "u-boot env", + .offset = 0, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "UBL", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "u-boot", + .offset = MTDPART_OFS_APPEND, + .size = 4 * SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = 0x200000, + .size = SZ_2M, + .mask_flags = 0, + }, + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_nand_pdata da850_evm_nandflash_data = { + .parts = da850_evm_nandflash_partition, + .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT, +}; + +static struct resource da850_evm_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da850_evm_nandflash_device = { + .name = "davinci_nand", + .id = 1, + .dev = { + .platform_data = &da850_evm_nandflash_data, + }, + .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource), + .resource = da850_evm_nandflash_resource, +}; + +static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { + { + I2C_BOARD_INFO("tlv320aic3x", 0x18), + } +}; + +static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +static struct davinci_uart_config da850_evm_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static struct platform_device *da850_evm_devices[] __initdata = { + &da850_evm_nandflash_device, + &da850_evm_norflash_device, +}; + +/* davinci da850 evm audio machine driver */ +static u8 da850_iis_serializer_direction[] = { + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE, + RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct snd_platform_data da850_evm_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), + .tdm_slots = 2, + .serial_dir = da850_iis_serializer_direction, + .eventq_no = EVENTQ_1, + .version = MCASP_VERSION_2, + .txnumevt = 1, + .rxnumevt = 1, +}; + +static int da850_evm_mmc_get_ro(int index) +{ + return gpio_get_value(DA850_MMCSD_WP_PIN); +} + +static int da850_evm_mmc_get_cd(int index) +{ + return !gpio_get_value(DA850_MMCSD_CD_PIN); +} + +static struct davinci_mmc_config da850_mmc_config = { + .get_ro = da850_evm_mmc_get_ro, + .get_cd = da850_evm_mmc_get_cd, + .wires = 4, + .version = MMC_CTLR_VERSION_2, +}; + +static int da850_lcd_hw_init(void) +{ + int status; + + status = gpio_request(DA850_LCD_BL_PIN, "lcd bl\n"); + if (status < 0) + return status; + + status = gpio_request(DA850_LCD_PWR_PIN, "lcd pwr\n"); + if (status < 0) { + gpio_free(DA850_LCD_BL_PIN); + return status; + } + + gpio_direction_output(DA850_LCD_BL_PIN, 0); + gpio_direction_output(DA850_LCD_PWR_PIN, 0); + + /* disable lcd backlight */ + gpio_set_value(DA850_LCD_BL_PIN, 0); + + /* disable lcd power */ + gpio_set_value(DA850_LCD_PWR_PIN, 0); + + /* enable lcd power */ + gpio_set_value(DA850_LCD_PWR_PIN, 1); + + /* enable lcd backlight */ + gpio_set_value(DA850_LCD_BL_PIN, 1); + + return 0; +} + +#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10 +#define DA8XX_AEMIF_ASIZE_16BIT 0x1 + +static void __init da850_evm_init_nor(void) +{ + void __iomem *aemif_addr; + + aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K); + + /* Configure data bus width of CS2 to 16 bit */ + writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) | + DA8XX_AEMIF_ASIZE_16BIT, + aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET); + + iounmap(aemif_addr); +} + +#if defined(CONFIG_MTD_PHYSMAP) || \ + defined(CONFIG_MTD_PHYSMAP_MODULE) +#define HAS_NOR 1 +#else +#define HAS_NOR 0 +#endif + +#if defined(CONFIG_MMC_DAVINCI) || \ + defined(CONFIG_MMC_DAVINCI_MODULE) +#define HAS_MMC 1 +#else +#define HAS_MMC 0 +#endif + +static __init void da850_evm_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + int ret; + + ret = da8xx_pinmux_setup(da850_nand_pins); + if (ret) + pr_warning("da850_evm_init: nand mux setup failed: %d\n", + ret); + + ret = da8xx_pinmux_setup(da850_nor_pins); + if (ret) + pr_warning("da850_evm_init: nor mux setup failed: %d\n", + ret); + + da850_evm_init_nor(); + + platform_add_devices(da850_evm_devices, + ARRAY_SIZE(da850_evm_devices)); + + ret = da8xx_register_edma(); + if (ret) + pr_warning("da850_evm_init: edma registration failed: %d\n", + ret); + + ret = da8xx_pinmux_setup(da850_i2c0_pins); + if (ret) + pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n", + ret); + + ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata); + if (ret) + pr_warning("da850_evm_init: i2c0 registration failed: %d\n", + ret); + + soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; + soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->rmii_en = 0; + + ret = da8xx_pinmux_setup(da850_cpgmac_pins); + if (ret) + pr_warning("da850_evm_init: cpgmac mux setup failed: %d\n", + ret); + + ret = da8xx_register_emac(); + if (ret) + pr_warning("da850_evm_init: emac registration failed: %d\n", + ret); + + ret = da8xx_register_watchdog(); + if (ret) + pr_warning("da830_evm_init: watchdog registration failed: %d\n", + ret); + + if (HAS_MMC) { + if (HAS_NOR) + pr_warning("WARNING: both NOR Flash and MMC/SD are " + "enabled, but they share AEMIF pins.\n" + "\tDisable one of them.\n"); + + ret = da8xx_pinmux_setup(da850_mmcsd0_pins); + if (ret) + pr_warning("da850_evm_init: mmcsd0 mux setup failed:" + " %d\n", ret); + + ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); + if (ret) + pr_warning("da850_evm_init: can not open GPIO %d\n", + DA850_MMCSD_CD_PIN); + gpio_direction_input(DA850_MMCSD_CD_PIN); + + ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); + if (ret) + pr_warning("da850_evm_init: can not open GPIO %d\n", + DA850_MMCSD_WP_PIN); + gpio_direction_input(DA850_MMCSD_WP_PIN); + + ret = da8xx_register_mmcsd0(&da850_mmc_config); + if (ret) + pr_warning("da850_evm_init: mmcsd0 registration failed:" + " %d\n", ret); + } + + davinci_serial_init(&da850_evm_uart_config); + + i2c_register_board_info(1, da850_evm_i2c_devices, + ARRAY_SIZE(da850_evm_i2c_devices)); + + /* + * shut down uart 0 and 1; they are not used on the board and + * accessing them causes endless "too much work in irq53" messages + * with arago fs + */ + __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); + __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); + + ret = da8xx_pinmux_setup(da850_mcasp_pins); + if (ret) + pr_warning("da850_evm_init: mcasp mux setup failed: %d\n", + ret); + + da8xx_init_mcasp(0, &da850_evm_snd_data); + + ret = da8xx_pinmux_setup(da850_lcdcntl_pins); + if (ret) + pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n", + ret); + + ret = da850_lcd_hw_init(); + if (ret) + pr_warning("da850_evm_init: lcd initialization failed: %d\n", + ret); + + ret = da8xx_register_lcdc(); + if (ret) + pr_warning("da850_evm_init: lcdc registration failed: %d\n", + ret); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init da850_evm_console_init(void) +{ + return add_preferred_console("ttyS", 2, "115200"); +} +console_initcall(da850_evm_console_init); +#endif + +static __init void da850_evm_irq_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ, + soc_info->intc_irq_prios); +} + +static void __init da850_evm_map_io(void) +{ + da850_init(); +} + +MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = da850_evm_map_io, + .init_irq = da850_evm_irq_init, + .timer = &davinci_timer, + .init_machine = da850_evm_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index d6ab64ccd496..77e806798822 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -20,6 +20,8 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/clk.h> +#include <linux/videodev2.h> +#include <media/tvp514x.h> #include <linux/spi/spi.h> #include <linux/spi/eeprom.h> @@ -117,6 +119,8 @@ static struct davinci_i2c_platform_data i2c_pdata = { .bus_delay = 0 /* usec */, }; +static struct snd_platform_data dm355_evm_snd_data; + static int dm355evm_mmc_gpios = -EINVAL; static void dm355evm_mmcsd_gpios(unsigned gpio) @@ -134,11 +138,11 @@ static void dm355evm_mmcsd_gpios(unsigned gpio) } static struct i2c_board_info dm355evm_i2c_info[] = { - { I2C_BOARD_INFO("dm355evm_msp", 0x25), + { I2C_BOARD_INFO("dm355evm_msp", 0x25), .platform_data = dm355evm_mmcsd_gpios, - /* plus irq */ }, - /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ - /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ + }, + /* { plus irq }, */ + { I2C_BOARD_INFO("tlv320aic33", 0x1b), }, }; static void __init evm_init_i2c(void) @@ -177,6 +181,72 @@ static struct platform_device dm355evm_dm9000 = { .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc), }; +static struct tvp514x_platform_data tvp5146_pdata = { + .clk_polarity = 0, + .hs_polarity = 1, + .vs_polarity = 1 +}; + +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) +/* Inputs available at the TVP5146 */ +static struct v4l2_input tvp5146_inputs[] = { + { + .index = 0, + .name = "Composite", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, + { + .index = 1, + .name = "S-Video", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, +}; + +/* + * this is the route info for connecting each input to decoder + * ouput that goes to vpfe. There is a one to one correspondence + * with tvp5146_inputs + */ +static struct vpfe_route tvp5146_routes[] = { + { + .input = INPUT_CVBS_VI2B, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + }, + { + .input = INPUT_SVIDEO_VI2C_VI1C, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + }, +}; + +static struct vpfe_subdev_info vpfe_sub_devs[] = { + { + .name = "tvp5146", + .grp_id = 0, + .num_inputs = ARRAY_SIZE(tvp5146_inputs), + .inputs = tvp5146_inputs, + .routes = tvp5146_routes, + .can_route = 1, + .ccdc_if_params = { + .if_type = VPFE_BT656, + .hdpol = VPFE_PINPOL_POSITIVE, + .vdpol = VPFE_PINPOL_POSITIVE, + }, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5d), + .platform_data = &tvp5146_pdata, + }, + } +}; + +static struct vpfe_config vpfe_cfg = { + .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), + .sub_devs = vpfe_sub_devs, + .card_name = "DM355 EVM", + .ccdc = "DM355 CCDC", +}; + static struct platform_device *davinci_evm_devices[] __initdata = { &dm355evm_dm9000, &davinci_nand_device, @@ -188,6 +258,8 @@ static struct davinci_uart_config uart_config __initdata = { static void __init dm355_evm_map_io(void) { + /* setup input configuration for VPFE input devices */ + dm355_set_vpfe_config(&vpfe_cfg); dm355_init(); } @@ -279,6 +351,9 @@ static __init void dm355_evm_init(void) dm355_init_spi0(BIT(0), dm355_evm_spi_info, ARRAY_SIZE(dm355_evm_spi_info)); + + /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */ + dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data); } static __init void dm355_evm_irq_init(void) diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c new file mode 100644 index 000000000000..a1d5e7dac741 --- /dev/null +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -0,0 +1,492 @@ +/* + * TI DaVinci DM365 EVM board support + * + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/dma-mapping.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/i2c/at24.h> +#include <linux/leds.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/mux.h> +#include <mach/hardware.h> +#include <mach/dm365.h> +#include <mach/psc.h> +#include <mach/common.h> +#include <mach/i2c.h> +#include <mach/serial.h> +#include <mach/common.h> +#include <mach/mmc.h> +#include <mach/nand.h> + + +static inline int have_imager(void) +{ + /* REVISIT when it's supported, trigger via Kconfig */ + return 0; +} + +static inline int have_tvp7002(void) +{ + /* REVISIT when it's supported, trigger via Kconfig */ + return 0; +} + + +#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000 +#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 +#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 + +#define DM365_EVM_PHY_MASK (0x2) +#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ + +/* + * A MAX-II CPLD is used for various board control functions. + */ +#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3)) + +#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */ +#define CPLD_TEST CPLD_OFFSET(0,1) +#define CPLD_LEDS CPLD_OFFSET(0,2) +#define CPLD_MUX CPLD_OFFSET(0,3) +#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */ +#define CPLD_POWER CPLD_OFFSET(1,1) +#define CPLD_VIDEO CPLD_OFFSET(1,2) +#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */ + +#define CPLD_DILC_OUT CPLD_OFFSET(2,0) +#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */ + +#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2) +#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3) +#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0) +#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1) +#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2) +#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3) +#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0) +#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1) +#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2) + +#define CPLD_RESETS CPLD_OFFSET(4,3) + +#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0) +#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1) +#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2) +#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3) +#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0) +#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1) + +static void __iomem *cpld; + + +/* NOTE: this is geared for the standard config, with a socketed + * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you + * swap chips with a different block size, partitioning will + * need to be changed. This NAND chip MT29F16G08FAA is the default + * NAND shipped with the Spectrum Digital DM365 EVM + */ +#define NAND_BLOCK_SIZE SZ_128K + +static struct mtd_partition davinci_nand_partitions[] = { + { + /* UBL (a few copies) plus U-Boot */ + .name = "bootloader", + .offset = 0, + .size = 28 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot environment */ + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = 2 * NAND_BLOCK_SIZE, + .mask_flags = 0, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "filesystem1", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512M, + .mask_flags = 0, + }, { + .name = "filesystem2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* two blocks with bad block table (and mirror) at the end */ +}; + +static struct davinci_nand_pdata davinci_nand_data = { + .mask_chipsel = BIT(14), + .parts = davinci_nand_partitions, + .nr_parts = ARRAY_SIZE(davinci_nand_partitions), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT, +}; + +static struct resource davinci_nand_resources[] = { + { + .start = DM365_ASYNC_EMIF_DATA_CE0_BASE, + .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, + }, { + .start = DM365_ASYNC_EMIF_CONTROL_BASE, + .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device davinci_nand_device = { + .name = "davinci_nand", + .id = 0, + .num_resources = ARRAY_SIZE(davinci_nand_resources), + .resource = davinci_nand_resources, + .dev = { + .platform_data = &davinci_nand_data, + }, +}; + +static struct at24_platform_data eeprom_info = { + .byte_len = (256*1024) / 8, + .page_size = 64, + .flags = AT24_FLAG_ADDR16, + .setup = davinci_get_mac_addr, + .context = (void *)0x7f00, +}; + +static struct i2c_board_info i2c_info[] = { + { + I2C_BOARD_INFO("24c256", 0x50), + .platform_data = &eeprom_info, + }, +}; + +static struct davinci_i2c_platform_data i2c_pdata = { + .bus_freq = 400 /* kHz */, + .bus_delay = 0 /* usec */, +}; + +static int cpld_mmc_get_cd(int module) +{ + if (!cpld) + return -ENXIO; + + /* low == card present */ + return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0)); +} + +static int cpld_mmc_get_ro(int module) +{ + if (!cpld) + return -ENXIO; + + /* high == card's write protect switch active */ + return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1)); +} + +static struct davinci_mmc_config dm365evm_mmc_config = { + .get_cd = cpld_mmc_get_cd, + .get_ro = cpld_mmc_get_ro, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_2, +}; + +static void dm365evm_emac_configure(void) +{ + /* + * EMAC pins are multiplexed with GPIO and UART + * Further details are available at the DM365 ARM + * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127 + */ + davinci_cfg_reg(DM365_EMAC_TX_EN); + davinci_cfg_reg(DM365_EMAC_TX_CLK); + davinci_cfg_reg(DM365_EMAC_COL); + davinci_cfg_reg(DM365_EMAC_TXD3); + davinci_cfg_reg(DM365_EMAC_TXD2); + davinci_cfg_reg(DM365_EMAC_TXD1); + davinci_cfg_reg(DM365_EMAC_TXD0); + davinci_cfg_reg(DM365_EMAC_RXD3); + davinci_cfg_reg(DM365_EMAC_RXD2); + davinci_cfg_reg(DM365_EMAC_RXD1); + davinci_cfg_reg(DM365_EMAC_RXD0); + davinci_cfg_reg(DM365_EMAC_RX_CLK); + davinci_cfg_reg(DM365_EMAC_RX_DV); + davinci_cfg_reg(DM365_EMAC_RX_ER); + davinci_cfg_reg(DM365_EMAC_CRS); + davinci_cfg_reg(DM365_EMAC_MDIO); + davinci_cfg_reg(DM365_EMAC_MDCLK); + + /* + * EMAC interrupts are multiplexed with GPIO interrupts + * Details are available at the DM365 ARM + * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 + */ + davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH); + davinci_cfg_reg(DM365_INT_EMAC_RXPULSE); + davinci_cfg_reg(DM365_INT_EMAC_TXPULSE); + davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE); +} + +static void dm365evm_mmc_configure(void) +{ + /* + * MMC/SD pins are multiplexed with GPIO and EMIF + * Further details are available at the DM365 ARM + * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131 + */ + davinci_cfg_reg(DM365_SD1_CLK); + davinci_cfg_reg(DM365_SD1_CMD); + davinci_cfg_reg(DM365_SD1_DATA3); + davinci_cfg_reg(DM365_SD1_DATA2); + davinci_cfg_reg(DM365_SD1_DATA1); + davinci_cfg_reg(DM365_SD1_DATA0); +} + +static void __init evm_init_i2c(void) +{ + davinci_init_i2c(&i2c_pdata); + i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); +} + +static struct platform_device *dm365_evm_nand_devices[] __initdata = { + &davinci_nand_device, +}; + +static inline int have_leds(void) +{ +#ifdef CONFIG_LEDS_CLASS + return 1; +#else + return 0; +#endif +} + +struct cpld_led { + struct led_classdev cdev; + u8 mask; +}; + +static const struct { + const char *name; + const char *trigger; +} cpld_leds[] = { + { "dm365evm::ds2", }, + { "dm365evm::ds3", }, + { "dm365evm::ds4", }, + { "dm365evm::ds5", }, + { "dm365evm::ds6", "nand-disk", }, + { "dm365evm::ds7", "mmc1", }, + { "dm365evm::ds8", "mmc0", }, + { "dm365evm::ds9", "heartbeat", }, +}; + +static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b) +{ + struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); + u8 reg = __raw_readb(cpld + CPLD_LEDS); + + if (b != LED_OFF) + reg &= ~led->mask; + else + reg |= led->mask; + __raw_writeb(reg, cpld + CPLD_LEDS); +} + +static enum led_brightness cpld_led_get(struct led_classdev *cdev) +{ + struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); + u8 reg = __raw_readb(cpld + CPLD_LEDS); + + return (reg & led->mask) ? LED_OFF : LED_FULL; +} + +static int __init cpld_leds_init(void) +{ + int i; + + if (!have_leds() || !cpld) + return 0; + + /* setup LEDs */ + __raw_writeb(0xff, cpld + CPLD_LEDS); + for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) { + struct cpld_led *led; + + led = kzalloc(sizeof(*led), GFP_KERNEL); + if (!led) + break; + + led->cdev.name = cpld_leds[i].name; + led->cdev.brightness_set = cpld_led_set; + led->cdev.brightness_get = cpld_led_get; + led->cdev.default_trigger = cpld_leds[i].trigger; + led->mask = BIT(i); + + if (led_classdev_register(NULL, &led->cdev) < 0) { + kfree(led); + break; + } + } + + return 0; +} +/* run after subsys_initcall() for LEDs */ +fs_initcall(cpld_leds_init); + + +static void __init evm_init_cpld(void) +{ + u8 mux, resets; + const char *label; + struct clk *aemif_clk; + + /* Make sure we can configure the CPLD through CS1. Then + * leave it on for later access to MMC and LED registers. + */ + aemif_clk = clk_get(NULL, "aemif"); + if (IS_ERR(aemif_clk)) + return; + clk_enable(aemif_clk); + + if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE, + "cpld") == NULL) + goto fail; + cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE); + if (!cpld) { + release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, + SECTION_SIZE); +fail: + pr_err("ERROR: can't map CPLD\n"); + clk_disable(aemif_clk); + return; + } + + /* External muxing for some signals */ + mux = 0; + + /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read). + * NOTE: SW4 bus width setting must match! + */ + if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) { + /* external keypad mux */ + mux |= BIT(7); + + platform_add_devices(dm365_evm_nand_devices, + ARRAY_SIZE(dm365_evm_nand_devices)); + } else { + /* no OneNAND support yet */ + } + + /* Leave external chips in reset when unused. */ + resets = BIT(3) | BIT(2) | BIT(1) | BIT(0); + + /* Static video input config with SN74CBT16214 1-of-3 mux: + * - port b1 == tvp7002 (mux lowbits == 1 or 6) + * - port b2 == imager (mux lowbits == 2 or 7) + * - port b3 == tvp5146 (mux lowbits == 5) + * + * Runtime switching could work too, with limitations. + */ + if (have_imager()) { + label = "HD imager"; + mux |= 1; + + /* externally mux MMC1/ENET/AIC33 to imager */ + mux |= BIT(6) | BIT(5) | BIT(3); + } else { + struct davinci_soc_info *soc_info = &davinci_soc_info; + + /* we can use MMC1 ... */ + dm365evm_mmc_configure(); + davinci_setup_mmc(1, &dm365evm_mmc_config); + + /* ... and ENET ... */ + dm365evm_emac_configure(); + soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK; + soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY; + resets &= ~BIT(3); + + /* ... and AIC33 */ + resets &= ~BIT(1); + + if (have_tvp7002()) { + mux |= 2; + resets &= ~BIT(2); + label = "tvp7002 HD"; + } else { + /* default to tvp5146 */ + mux |= 5; + resets &= ~BIT(0); + label = "tvp5146 SD"; + } + } + __raw_writeb(mux, cpld + CPLD_MUX); + __raw_writeb(resets, cpld + CPLD_RESETS); + pr_info("EVM: %s video input\n", label); + + /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ +} + +static struct davinci_uart_config uart_config __initdata = { + .enabled_uarts = (1 << 0), +}; + +static void __init dm365_evm_map_io(void) +{ + dm365_init(); +} + +static __init void dm365_evm_init(void) +{ + evm_init_i2c(); + davinci_serial_init(&uart_config); + + dm365evm_emac_configure(); + dm365evm_mmc_configure(); + + davinci_setup_mmc(0, &dm365evm_mmc_config); + + /* maybe setup mmc1/etc ... _after_ mmc0 */ + evm_init_cpld(); +} + +static __init void dm365_evm_irq_init(void) +{ + davinci_irq_init(); +} + +MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (0x80000100), + .map_io = dm365_evm_map_io, + .init_irq = dm365_evm_irq_init, + .timer = &davinci_timer, + .init_machine = dm365_evm_init, +MACHINE_END + diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 56c8cd01de9a..1213a0087ad4 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -28,6 +28,9 @@ #include <linux/io.h> #include <linux/phy.h> #include <linux/clk.h> +#include <linux/videodev2.h> + +#include <media/tvp514x.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -194,6 +197,72 @@ static struct platform_device davinci_fb_device = { .num_resources = 0, }; +static struct tvp514x_platform_data tvp5146_pdata = { + .clk_polarity = 0, + .hs_polarity = 1, + .vs_polarity = 1 +}; + +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) +/* Inputs available at the TVP5146 */ +static struct v4l2_input tvp5146_inputs[] = { + { + .index = 0, + .name = "Composite", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, + { + .index = 1, + .name = "S-Video", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, +}; + +/* + * this is the route info for connecting each input to decoder + * ouput that goes to vpfe. There is a one to one correspondence + * with tvp5146_inputs + */ +static struct vpfe_route tvp5146_routes[] = { + { + .input = INPUT_CVBS_VI2B, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + }, + { + .input = INPUT_SVIDEO_VI2C_VI1C, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + }, +}; + +static struct vpfe_subdev_info vpfe_sub_devs[] = { + { + .name = "tvp5146", + .grp_id = 0, + .num_inputs = ARRAY_SIZE(tvp5146_inputs), + .inputs = tvp5146_inputs, + .routes = tvp5146_routes, + .can_route = 1, + .ccdc_if_params = { + .if_type = VPFE_BT656, + .hdpol = VPFE_PINPOL_POSITIVE, + .vdpol = VPFE_PINPOL_POSITIVE, + }, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5d), + .platform_data = &tvp5146_pdata, + }, + }, +}; + +static struct vpfe_config vpfe_cfg = { + .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), + .sub_devs = vpfe_sub_devs, + .card_name = "DM6446 EVM", + .ccdc = "DM6446 CCDC", +}; + static struct platform_device rtc_dev = { .name = "rtc_davinci_evm", .id = -1, @@ -225,6 +294,8 @@ static struct platform_device ide_dev = { }, }; +static struct snd_platform_data dm644x_evm_snd_data; + /*----------------------------------------------------------------------*/ /* @@ -557,10 +628,9 @@ static struct i2c_board_info __initdata i2c_info[] = { I2C_BOARD_INFO("24c256", 0x50), .platform_data = &eeprom_info, }, - /* ALSO: - * - tvl320aic33 audio codec (0x1b) - * - tvp5146 video decoder (0x5d) - */ + { + I2C_BOARD_INFO("tlv320aic33", 0x1b), + }, }; /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz), @@ -590,6 +660,8 @@ static struct davinci_uart_config uart_config __initdata = { static void __init davinci_evm_map_io(void) { + /* setup input configuration for VPFE input devices */ + dm644x_set_vpfe_config(&vpfe_cfg); dm644x_init(); } @@ -666,6 +738,7 @@ static __init void davinci_evm_init(void) davinci_setup_mmc(0, &dm6446evm_mmc_config); davinci_serial_init(&uart_config); + dm644x_init_asp(&dm644x_evm_snd_data); soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY; diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 8657e72debc1..24e0e13b1492 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -34,6 +34,8 @@ #include <linux/i2c/pcf857x.h> #include <linux/etherdevice.h> +#include <media/tvp514x.h> + #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -48,13 +50,89 @@ #include <mach/mmc.h> #include <mach/emac.h> +#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ + defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) +#define HAS_ATA 1 +#else +#define HAS_ATA 0 +#endif + +/* CPLD Register 0 bits to control ATA */ +#define DM646X_EVM_ATA_RST BIT(0) +#define DM646X_EVM_ATA_PWD BIT(1) + #define DM646X_EVM_PHY_MASK (0x2) #define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ +#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38) +#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c) +#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8)) +#define VCH2CLK_SYSCLK8 (BIT(9)) +#define VCH2CLK_AUXCLK (BIT(9) | BIT(8)) +#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12)) +#define VCH3CLK_SYSCLK8 (BIT(13)) +#define VCH3CLK_AUXCLK (BIT(14) | BIT(13)) + +#define VIDCH2CLK (BIT(10)) +#define VIDCH3CLK (BIT(11)) +#define VIDCH1CLK (BIT(4)) +#define TVP7002_INPUT (BIT(4)) +#define TVP5147_INPUT (~BIT(4)) +#define VPIF_INPUT_ONE_CHANNEL (BIT(5)) +#define VPIF_INPUT_TWO_CHANNEL (~BIT(5)) +#define TVP5147_CH0 "tvp514x-0" +#define TVP5147_CH1 "tvp514x-1" + +static void __iomem *vpif_vidclkctl_reg; +static void __iomem *vpif_vsclkdis_reg; +/* spin lock for updating above registers */ +static spinlock_t vpif_reg_lock; + static struct davinci_uart_config uart_config __initdata = { .enabled_uarts = (1 << 0), }; +/* CPLD Register 0 Client: used for I/O Control */ +static int cpld_reg0_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + if (HAS_ATA) { + u8 data; + struct i2c_msg msg[2] = { + { + .addr = client->addr, + .flags = I2C_M_RD, + .len = 1, + .buf = &data, + }, + { + .addr = client->addr, + .flags = 0, + .len = 1, + .buf = &data, + }, + }; + + /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */ + i2c_transfer(client->adapter, msg, 1); + data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD); + i2c_transfer(client->adapter, msg + 1, 1); + } + + return 0; +} + +static const struct i2c_device_id cpld_reg_ids[] = { + { "cpld_reg0", 0, }, + { }, +}; + +static struct i2c_driver dm6467evm_cpld_driver = { + .driver.name = "cpld_reg0", + .id_table = cpld_reg_ids, + .probe = cpld_reg0_probe, +}; + /* LEDS */ static struct gpio_led evm_leds[] = { @@ -206,6 +284,69 @@ static struct at24_platform_data eeprom_info = { .context = (void *)0x7f00, }; +static u8 dm646x_iis_serializer_direction[] = { + TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static u8 dm646x_dit_serializer_direction[] = { + TX_MODE, +}; + +static struct snd_platform_data dm646x_evm_snd_data[] = { + { + .tx_dma_offset = 0x400, + .rx_dma_offset = 0x400, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction), + .tdm_slots = 2, + .serial_dir = dm646x_iis_serializer_direction, + .eventq_no = EVENTQ_0, + }, + { + .tx_dma_offset = 0x400, + .rx_dma_offset = 0, + .op_mode = DAVINCI_MCASP_DIT_MODE, + .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction), + .tdm_slots = 32, + .serial_dir = dm646x_dit_serializer_direction, + .eventq_no = EVENTQ_0, + }, +}; + +static struct i2c_client *cpld_client; + +static int cpld_video_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + cpld_client = client; + return 0; +} + +static int __devexit cpld_video_remove(struct i2c_client *client) +{ + cpld_client = NULL; + return 0; +} + +static const struct i2c_device_id cpld_video_id[] = { + { "cpld_video", 0 }, + { } +}; + +static struct i2c_driver cpld_video_driver = { + .driver = { + .name = "cpld_video", + }, + .probe = cpld_video_probe, + .remove = cpld_video_remove, + .id_table = cpld_video_id, +}; + +static void evm_init_cpld(void) +{ + i2c_add_driver(&cpld_video_driver); +} + static struct i2c_board_info __initdata i2c_info[] = { { I2C_BOARD_INFO("24c256", 0x50), @@ -215,6 +356,15 @@ static struct i2c_board_info __initdata i2c_info[] = { I2C_BOARD_INFO("pcf8574a", 0x38), .platform_data = &pcf_data, }, + { + I2C_BOARD_INFO("cpld_reg0", 0x3a), + }, + { + I2C_BOARD_INFO("tlv320aic33", 0x18), + }, + { + I2C_BOARD_INFO("cpld_video", 0x3b), + }, }; static struct davinci_i2c_platform_data i2c_pdata = { @@ -222,10 +372,265 @@ static struct davinci_i2c_platform_data i2c_pdata = { .bus_delay = 0 /* usec */, }; +static int set_vpif_clock(int mux_mode, int hd) +{ + unsigned long flags; + unsigned int value; + int val = 0; + int err = 0; + + if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client) + return -ENXIO; + + /* disable the clock */ + spin_lock_irqsave(&vpif_reg_lock, flags); + value = __raw_readl(vpif_vsclkdis_reg); + value |= (VIDCH3CLK | VIDCH2CLK); + __raw_writel(value, vpif_vsclkdis_reg); + spin_unlock_irqrestore(&vpif_reg_lock, flags); + + val = i2c_smbus_read_byte(cpld_client); + if (val < 0) + return val; + + if (mux_mode == 1) + val &= ~0x40; + else + val |= 0x40; + + err = i2c_smbus_write_byte(cpld_client, val); + if (err) + return err; + + value = __raw_readl(vpif_vidclkctl_reg); + value &= ~(VCH2CLK_MASK); + value &= ~(VCH3CLK_MASK); + + if (hd >= 1) + value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8); + else + value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK); + + __raw_writel(value, vpif_vidclkctl_reg); + + spin_lock_irqsave(&vpif_reg_lock, flags); + value = __raw_readl(vpif_vsclkdis_reg); + /* enable the clock */ + value &= ~(VIDCH3CLK | VIDCH2CLK); + __raw_writel(value, vpif_vsclkdis_reg); + spin_unlock_irqrestore(&vpif_reg_lock, flags); + + return 0; +} + +static struct vpif_subdev_info dm646x_vpif_subdev[] = { + { + .name = "adv7343", + .board_info = { + I2C_BOARD_INFO("adv7343", 0x2a), + }, + }, + { + .name = "ths7303", + .board_info = { + I2C_BOARD_INFO("ths7303", 0x2c), + }, + }, +}; + +static const char *output[] = { + "Composite", + "Component", + "S-Video", +}; + +static struct vpif_display_config dm646x_vpif_display_config = { + .set_clock = set_vpif_clock, + .subdevinfo = dm646x_vpif_subdev, + .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev), + .output = output, + .output_count = ARRAY_SIZE(output), + .card_name = "DM646x EVM", +}; + +/** + * setup_vpif_input_path() + * @channel: channel id (0 - CH0, 1 - CH1) + * @sub_dev_name: ptr sub device name + * + * This will set vpif input to capture data from tvp514x or + * tvp7002. + */ +static int setup_vpif_input_path(int channel, const char *sub_dev_name) +{ + int err = 0; + int val; + + /* for channel 1, we don't do anything */ + if (channel != 0) + return 0; + + if (!cpld_client) + return -ENXIO; + + val = i2c_smbus_read_byte(cpld_client); + if (val < 0) + return val; + + if (!strcmp(sub_dev_name, TVP5147_CH0) || + !strcmp(sub_dev_name, TVP5147_CH1)) + val &= TVP5147_INPUT; + else + val |= TVP7002_INPUT; + + err = i2c_smbus_write_byte(cpld_client, val); + if (err) + return err; + return 0; +} + +/** + * setup_vpif_input_channel_mode() + * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel + * + * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147) + */ +static int setup_vpif_input_channel_mode(int mux_mode) +{ + unsigned long flags; + int err = 0; + int val; + u32 value; + + if (!vpif_vsclkdis_reg || !cpld_client) + return -ENXIO; + + val = i2c_smbus_read_byte(cpld_client); + if (val < 0) + return val; + + spin_lock_irqsave(&vpif_reg_lock, flags); + value = __raw_readl(vpif_vsclkdis_reg); + if (mux_mode) { + val &= VPIF_INPUT_TWO_CHANNEL; + value |= VIDCH1CLK; + } else { + val |= VPIF_INPUT_ONE_CHANNEL; + value &= ~VIDCH1CLK; + } + __raw_writel(value, vpif_vsclkdis_reg); + spin_unlock_irqrestore(&vpif_reg_lock, flags); + + err = i2c_smbus_write_byte(cpld_client, val); + if (err) + return err; + + return 0; +} + +static struct tvp514x_platform_data tvp5146_pdata = { + .clk_polarity = 0, + .hs_polarity = 1, + .vs_polarity = 1 +}; + +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) + +static struct vpif_subdev_info vpif_capture_sdev_info[] = { + { + .name = TVP5147_CH0, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5d), + .platform_data = &tvp5146_pdata, + }, + .input = INPUT_CVBS_VI2B, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .can_route = 1, + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, + }, + { + .name = TVP5147_CH1, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5c), + .platform_data = &tvp5146_pdata, + }, + .input = INPUT_SVIDEO_VI2C_VI1C, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .can_route = 1, + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, + }, +}; + +static const struct vpif_input dm6467_ch0_inputs[] = { + { + .input = { + .index = 0, + .name = "Composite", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, + .subdev_name = TVP5147_CH0, + }, +}; + +static const struct vpif_input dm6467_ch1_inputs[] = { + { + .input = { + .index = 0, + .name = "S-Video", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, + .subdev_name = TVP5147_CH1, + }, +}; + +static struct vpif_capture_config dm646x_vpif_capture_cfg = { + .setup_input_path = setup_vpif_input_path, + .setup_input_channel_mode = setup_vpif_input_channel_mode, + .subdev_info = vpif_capture_sdev_info, + .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info), + .chan_config[0] = { + .inputs = dm6467_ch0_inputs, + .input_count = ARRAY_SIZE(dm6467_ch0_inputs), + }, + .chan_config[1] = { + .inputs = dm6467_ch1_inputs, + .input_count = ARRAY_SIZE(dm6467_ch1_inputs), + }, +}; + +static void __init evm_init_video(void) +{ + vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4); + vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4); + if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) { + pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n"); + return; + } + spin_lock_init(&vpif_reg_lock); + + dm646x_setup_vpif(&dm646x_vpif_display_config, + &dm646x_vpif_capture_cfg); +} + static void __init evm_init_i2c(void) { davinci_init_i2c(&i2c_pdata); + i2c_add_driver(&dm6467evm_cpld_driver); i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); + evm_init_cpld(); + evm_init_video(); } static void __init davinci_map_io(void) @@ -239,6 +644,11 @@ static __init void evm_init(void) evm_init_i2c(); davinci_serial_init(&uart_config); + dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); + dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); + + if (HAS_ATA) + dm646x_init_ide(); soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 39bf321d70a2..83d54d50b5ea 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -227,7 +227,10 @@ static void __init clk_pll_init(struct clk *clk) if (ctrl & PLLCTL_PLLEN) { bypass = 0; mult = __raw_readl(pll->base + PLLM); - mult = (mult & PLLM_PLLM_MASK) + 1; + if (cpu_is_davinci_dm365()) + mult = 2 * (mult & PLLM_PLLM_MASK); + else + mult = (mult & PLLM_PLLM_MASK) + 1; } else bypass = 1; diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c new file mode 100644 index 000000000000..19b2748357fc --- /dev/null +++ b/arch/arm/mach-davinci/da830.c @@ -0,0 +1,1205 @@ +/* + * TI DA830/OMAP L137 chip specific setup + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <asm/mach/map.h> + +#include <mach/clock.h> +#include <mach/psc.h> +#include <mach/mux.h> +#include <mach/irqs.h> +#include <mach/cputype.h> +#include <mach/common.h> +#include <mach/time.h> +#include <mach/da8xx.h> +#include <mach/asp.h> + +#include "clock.h" +#include "mux.h" + +/* Offsets of the 8 compare registers on the da830 */ +#define DA830_CMP12_0 0x60 +#define DA830_CMP12_1 0x64 +#define DA830_CMP12_2 0x68 +#define DA830_CMP12_3 0x6c +#define DA830_CMP12_4 0x70 +#define DA830_CMP12_5 0x74 +#define DA830_CMP12_6 0x78 +#define DA830_CMP12_7 0x7c + +#define DA830_REF_FREQ 24000000 + +static struct pll_data pll0_data = { + .num = 1, + .phys_base = DA8XX_PLL0_BASE, + .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DA830_REF_FREQ, +}; + +static struct clk pll0_clk = { + .name = "pll0", + .parent = &ref_clk, + .pll_data = &pll0_data, + .flags = CLK_PLL, +}; + +static struct clk pll0_aux_clk = { + .name = "pll0_aux_clk", + .parent = &pll0_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll0_sysclk2 = { + .name = "pll0_sysclk2", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll0_sysclk3 = { + .name = "pll0_sysclk3", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll0_sysclk4 = { + .name = "pll0_sysclk4", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll0_sysclk5 = { + .name = "pll0_sysclk5", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll0_sysclk6 = { + .name = "pll0_sysclk6", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll0_sysclk7 = { + .name = "pll0_sysclk7", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk i2c0_clk = { + .name = "i2c0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_0_clk = { + .name = "timer0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_1_clk = { + .name = "timer1", + .parent = &pll0_aux_clk, +}; + +static struct clk arm_rom_clk = { + .name = "arm_rom", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk scr0_ss_clk = { + .name = "scr0_ss", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_SCR0_SS, + .flags = ALWAYS_ENABLED, +}; + +static struct clk scr1_ss_clk = { + .name = "scr1_ss", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_SCR1_SS, + .flags = ALWAYS_ENABLED, +}; + +static struct clk scr2_ss_clk = { + .name = "scr2_ss", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_SCR2_SS, + .flags = ALWAYS_ENABLED, +}; + +static struct clk dmax_clk = { + .name = "dmax", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_DMAX, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tpcc_clk = { + .name = "tpcc", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPCC, + .flags = ALWAYS_ENABLED | CLK_PSC, +}; + +static struct clk tptc0_clk = { + .name = "tptc0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tptc1_clk = { + .name = "tptc1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk mmcsd_clk = { + .name = "mmcsd", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_MMC_SD, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART1, + .psc_ctlr = 1, +}; + +static struct clk uart2_clk = { + .name = "uart2", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART2, + .psc_ctlr = 1, +}; + +static struct clk spi0_clk = { + .name = "spi0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_SPI0, +}; + +static struct clk spi1_clk = { + .name = "spi1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_SPI1, + .psc_ctlr = 1, +}; + +static struct clk ecap0_clk = { + .name = "ecap0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_ECAP, + .psc_ctlr = 1, +}; + +static struct clk ecap1_clk = { + .name = "ecap1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_ECAP, + .psc_ctlr = 1, +}; + +static struct clk ecap2_clk = { + .name = "ecap2", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_ECAP, + .psc_ctlr = 1, +}; + +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_PWM, + .psc_ctlr = 1, +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_PWM, + .psc_ctlr = 1, +}; + +static struct clk pwm2_clk = { + .name = "pwm2", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_PWM, + .psc_ctlr = 1, +}; + +static struct clk eqep0_clk = { + .name = "eqep0", + .parent = &pll0_sysclk2, + .lpsc = DA830_LPSC1_EQEP, + .psc_ctlr = 1, +}; + +static struct clk eqep1_clk = { + .name = "eqep1", + .parent = &pll0_sysclk2, + .lpsc = DA830_LPSC1_EQEP, + .psc_ctlr = 1, +}; + +static struct clk lcdc_clk = { + .name = "lcdc", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_LCDC, + .psc_ctlr = 1, +}; + +static struct clk mcasp0_clk = { + .name = "mcasp0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_McASP0, + .psc_ctlr = 1, +}; + +static struct clk mcasp1_clk = { + .name = "mcasp1", + .parent = &pll0_sysclk2, + .lpsc = DA830_LPSC1_McASP1, + .psc_ctlr = 1, +}; + +static struct clk mcasp2_clk = { + .name = "mcasp2", + .parent = &pll0_sysclk2, + .lpsc = DA830_LPSC1_McASP2, + .psc_ctlr = 1, +}; + +static struct clk usb20_clk = { + .name = "usb20", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_USB20, + .psc_ctlr = 1, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll0_sysclk3, + .lpsc = DA8XX_LPSC0_EMIF25, + .flags = ALWAYS_ENABLED, +}; + +static struct clk aintc_clk = { + .name = "aintc", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC0_AINTC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk secu_mgr_clk = { + .name = "secu_mgr", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC0_SECU_MGR, + .flags = ALWAYS_ENABLED, +}; + +static struct clk emac_clk = { + .name = "emac", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_CPGMAC, + .psc_ctlr = 1, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_GPIO, + .psc_ctlr = 1, +}; + +static struct clk i2c1_clk = { + .name = "i2c1", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_I2C, + .psc_ctlr = 1, +}; + +static struct clk usb11_clk = { + .name = "usb11", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_USB11, + .psc_ctlr = 1, +}; + +static struct clk emif3_clk = { + .name = "emif3", + .parent = &pll0_sysclk5, + .lpsc = DA8XX_LPSC1_EMIF3C, + .flags = ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk arm_clk = { + .name = "arm", + .parent = &pll0_sysclk6, + .lpsc = DA8XX_LPSC0_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk rmii_clk = { + .name = "rmii", + .parent = &pll0_sysclk7, +}; + +static struct davinci_clk da830_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll0", &pll0_clk), + CLK(NULL, "pll0_aux", &pll0_aux_clk), + CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), + CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), + CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), + CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), + CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), + CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), + CLK("i2c_davinci.1", NULL, &i2c0_clk), + CLK(NULL, "timer0", &timerp64_0_clk), + CLK("watchdog", NULL, &timerp64_1_clk), + CLK(NULL, "arm_rom", &arm_rom_clk), + CLK(NULL, "scr0_ss", &scr0_ss_clk), + CLK(NULL, "scr1_ss", &scr1_ss_clk), + CLK(NULL, "scr2_ss", &scr2_ss_clk), + CLK(NULL, "dmax", &dmax_clk), + CLK(NULL, "tpcc", &tpcc_clk), + CLK(NULL, "tptc0", &tptc0_clk), + CLK(NULL, "tptc1", &tptc1_clk), + CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK(NULL, "uart2", &uart2_clk), + CLK("dm_spi.0", NULL, &spi0_clk), + CLK("dm_spi.1", NULL, &spi1_clk), + CLK(NULL, "ecap0", &ecap0_clk), + CLK(NULL, "ecap1", &ecap1_clk), + CLK(NULL, "ecap2", &ecap2_clk), + CLK(NULL, "pwm0", &pwm0_clk), + CLK(NULL, "pwm1", &pwm1_clk), + CLK(NULL, "pwm2", &pwm2_clk), + CLK("eqep.0", NULL, &eqep0_clk), + CLK("eqep.1", NULL, &eqep1_clk), + CLK("da830_lcdc", NULL, &lcdc_clk), + CLK("davinci-mcasp.0", NULL, &mcasp0_clk), + CLK("davinci-mcasp.1", NULL, &mcasp1_clk), + CLK("davinci-mcasp.2", NULL, &mcasp2_clk), + CLK("musb_hdrc", NULL, &usb20_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK(NULL, "aintc", &aintc_clk), + CLK(NULL, "secu_mgr", &secu_mgr_clk), + CLK("davinci_emac.1", NULL, &emac_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK("i2c_davinci.2", NULL, &i2c1_clk), + CLK(NULL, "usb11", &usb11_clk), + CLK(NULL, "emif3", &emif3_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "rmii", &rmii_clk), + CLK(NULL, NULL, NULL), +}; + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config da830_pins[] = { +#ifdef CONFIG_DAVINCI_MUX + MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false) + MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false) + MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false) + MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false) + MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false) + MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false) + MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false) + MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false) + MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false) + MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false) + MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false) + MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false) + MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false) + MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false) + MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false) + MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false) + MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false) + MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false) + MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false) + MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false) + MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false) + MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false) + MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false) + MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false) + MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false) + MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false) + MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false) + MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false) + MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false) + MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false) + MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false) + MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false) + MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false) + MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false) + MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false) + MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false) + MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false) + MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false) + MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false) + MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false) + MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false) + MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false) + MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false) + MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false) + MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false) + MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false) + MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false) + MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false) + MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false) + MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false) + MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false) + MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false) + MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false) + MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false) + MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false) + MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false) + MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false) + MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false) + MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false) + MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false) + MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false) + MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false) + MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false) + MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false) + MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false) + MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false) + MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false) + MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false) + MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false) + MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false) + MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false) + MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false) + MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false) + MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false) + MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false) + MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false) + MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false) + MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false) + MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false) + MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false) + MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false) + MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false) + MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false) + MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false) + MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false) + MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false) + MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false) + MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false) + MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false) + MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false) + MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false) + MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false) + MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false) + MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false) + MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false) + MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false) + MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false) + MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false) + MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false) + MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false) + MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false) + MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false) + MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false) + MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false) + MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false) + MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false) + MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false) + MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false) + MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false) + MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false) + MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false) + MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false) + MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false) + MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false) + MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false) + MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false) + MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false) + MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false) + MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false) + MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false) + MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false) + MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false) + MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false) + MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false) + MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false) + MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false) + MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false) + MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false) + MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false) + MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false) + MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false) + MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false) + MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false) + MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false) + MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false) +#endif +}; + +const short da830_emif25_pins[] __initdata = { + DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, + DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, + DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, + DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15, + DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, + DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, + DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, + DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK, + DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE, + DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, + DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0, + -1 +}; + +const short da830_spi0_pins[] __initdata = { + DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, + DA830_NSPI0_SCS_0, + -1 +}; + +const short da830_spi1_pins[] __initdata = { + DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, + DA830_NSPI1_SCS_0, + -1 +}; + +const short da830_mmc_sd_pins[] __initdata = { + DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, + DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, + DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, + DA830_MMCSD_CMD, + -1 +}; + +const short da830_uart0_pins[] __initdata = { + DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, + -1 +}; + +const short da830_uart1_pins[] __initdata = { + DA830_UART1_RXD, DA830_UART1_TXD, + -1 +}; + +const short da830_uart2_pins[] __initdata = { + DA830_UART2_RXD, DA830_UART2_TXD, + -1 +}; + +const short da830_usb20_pins[] __initdata = { + DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, + -1 +}; + +const short da830_usb11_pins[] __initdata = { + DA830_USB_REFCLKIN, + -1 +}; + +const short da830_uhpi_pins[] __initdata = { + DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, + DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, + DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, + DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15, + DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW, + DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2, + DA830_NUHPI_HINT, DA830_NUHPI_HRDY, + -1 +}; + +const short da830_cpgmac_pins[] __initdata = { + DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, + DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, + DA830_MDIO_D, + -1 +}; + +const short da830_emif3c_pins[] __initdata = { + DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, + DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, + DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, + DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6, + DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10, + DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3, + DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2, + DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6, + DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10, + DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14, + DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18, + DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22, + DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26, + DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30, + DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0, + -1 +}; + +const short da830_mcasp0_pins[] __initdata = { + DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, + DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, + DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, + DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7, + DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11, + DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15, + -1 +}; + +const short da830_mcasp1_pins[] __initdata = { + DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, + DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, + DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, + DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7, + DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11, + -1 +}; + +const short da830_mcasp2_pins[] __initdata = { + DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, + DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, + DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, + -1 +}; + +const short da830_i2c0_pins[] __initdata = { + DA830_I2C0_SDA, DA830_I2C0_SCL, + -1 +}; + +const short da830_i2c1_pins[] __initdata = { + DA830_I2C1_SCL, DA830_I2C1_SDA, + -1 +}; + +const short da830_lcdcntl_pins[] __initdata = { + DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, + DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, + DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, + DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15, + DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS, + DA830_LCD_MCLK, + -1 +}; + +const short da830_pwm_pins[] __initdata = { + DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, + DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, + DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, + -1 +}; + +const short da830_ecap0_pins[] __initdata = { + DA830_ECAP0_APWM0, + -1 +}; + +const short da830_ecap1_pins[] __initdata = { + DA830_ECAP1_APWM1, + -1 +}; + +const short da830_ecap2_pins[] __initdata = { + DA830_ECAP2_APWM2, + -1 +}; + +const short da830_eqep0_pins[] __initdata = { + DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, + -1 +}; + +const short da830_eqep1_pins[] __initdata = { + DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, + -1 +}; + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { + [IRQ_DA8XX_COMMTX] = 7, + [IRQ_DA8XX_COMMRX] = 7, + [IRQ_DA8XX_NINT] = 7, + [IRQ_DA8XX_EVTOUT0] = 7, + [IRQ_DA8XX_EVTOUT1] = 7, + [IRQ_DA8XX_EVTOUT2] = 7, + [IRQ_DA8XX_EVTOUT3] = 7, + [IRQ_DA8XX_EVTOUT4] = 7, + [IRQ_DA8XX_EVTOUT5] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT7] = 7, + [IRQ_DA8XX_CCINT0] = 7, + [IRQ_DA8XX_CCERRINT] = 7, + [IRQ_DA8XX_TCERRINT0] = 7, + [IRQ_DA8XX_AEMIFINT] = 7, + [IRQ_DA8XX_I2CINT0] = 7, + [IRQ_DA8XX_MMCSDINT0] = 7, + [IRQ_DA8XX_MMCSDINT1] = 7, + [IRQ_DA8XX_ALLINT0] = 7, + [IRQ_DA8XX_RTC] = 7, + [IRQ_DA8XX_SPINT0] = 7, + [IRQ_DA8XX_TINT12_0] = 7, + [IRQ_DA8XX_TINT34_0] = 7, + [IRQ_DA8XX_TINT12_1] = 7, + [IRQ_DA8XX_TINT34_1] = 7, + [IRQ_DA8XX_UARTINT0] = 7, + [IRQ_DA8XX_KEYMGRINT] = 7, + [IRQ_DA8XX_SECINT] = 7, + [IRQ_DA8XX_SECKEYERR] = 7, + [IRQ_DA830_MPUERR] = 7, + [IRQ_DA830_IOPUERR] = 7, + [IRQ_DA830_BOOTCFGERR] = 7, + [IRQ_DA8XX_CHIPINT0] = 7, + [IRQ_DA8XX_CHIPINT1] = 7, + [IRQ_DA8XX_CHIPINT2] = 7, + [IRQ_DA8XX_CHIPINT3] = 7, + [IRQ_DA8XX_TCERRINT1] = 7, + [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C0_RX_PULSE] = 7, + [IRQ_DA8XX_C0_TX_PULSE] = 7, + [IRQ_DA8XX_C0_MISC_PULSE] = 7, + [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C1_RX_PULSE] = 7, + [IRQ_DA8XX_C1_TX_PULSE] = 7, + [IRQ_DA8XX_C1_MISC_PULSE] = 7, + [IRQ_DA8XX_MEMERR] = 7, + [IRQ_DA8XX_GPIO0] = 7, + [IRQ_DA8XX_GPIO1] = 7, + [IRQ_DA8XX_GPIO2] = 7, + [IRQ_DA8XX_GPIO3] = 7, + [IRQ_DA8XX_GPIO4] = 7, + [IRQ_DA8XX_GPIO5] = 7, + [IRQ_DA8XX_GPIO6] = 7, + [IRQ_DA8XX_GPIO7] = 7, + [IRQ_DA8XX_GPIO8] = 7, + [IRQ_DA8XX_I2CINT1] = 7, + [IRQ_DA8XX_LCDINT] = 7, + [IRQ_DA8XX_UARTINT1] = 7, + [IRQ_DA8XX_MCASPINT] = 7, + [IRQ_DA8XX_ALLINT1] = 7, + [IRQ_DA8XX_SPINT1] = 7, + [IRQ_DA8XX_UHPI_INT1] = 7, + [IRQ_DA8XX_USB_INT] = 7, + [IRQ_DA8XX_IRQN] = 7, + [IRQ_DA8XX_RWAKEUP] = 7, + [IRQ_DA8XX_UARTINT2] = 7, + [IRQ_DA8XX_DFTSSINT] = 7, + [IRQ_DA8XX_EHRPWM0] = 7, + [IRQ_DA8XX_EHRPWM0TZ] = 7, + [IRQ_DA8XX_EHRPWM1] = 7, + [IRQ_DA8XX_EHRPWM1TZ] = 7, + [IRQ_DA830_EHRPWM2] = 7, + [IRQ_DA830_EHRPWM2TZ] = 7, + [IRQ_DA8XX_ECAP0] = 7, + [IRQ_DA8XX_ECAP1] = 7, + [IRQ_DA8XX_ECAP2] = 7, + [IRQ_DA830_EQEP0] = 7, + [IRQ_DA830_EQEP1] = 7, + [IRQ_DA830_T12CMPINT0_0] = 7, + [IRQ_DA830_T12CMPINT1_0] = 7, + [IRQ_DA830_T12CMPINT2_0] = 7, + [IRQ_DA830_T12CMPINT3_0] = 7, + [IRQ_DA830_T12CMPINT4_0] = 7, + [IRQ_DA830_T12CMPINT5_0] = 7, + [IRQ_DA830_T12CMPINT6_0] = 7, + [IRQ_DA830_T12CMPINT7_0] = 7, + [IRQ_DA830_T12CMPINT0_1] = 7, + [IRQ_DA830_T12CMPINT1_1] = 7, + [IRQ_DA830_T12CMPINT2_1] = 7, + [IRQ_DA830_T12CMPINT3_1] = 7, + [IRQ_DA830_T12CMPINT4_1] = 7, + [IRQ_DA830_T12CMPINT5_1] = 7, + [IRQ_DA830_T12CMPINT6_1] = 7, + [IRQ_DA830_T12CMPINT7_1] = 7, + [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, +}; + +static struct map_desc da830_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = DA8XX_CP_INTC_VIRT, + .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), + .length = DA8XX_CP_INTC_SIZE, + .type = MT_DEVICE + }, +}; + +static void __iomem *da830_psc_bases[] = { + IO_ADDRESS(DA8XX_PSC0_BASE), + IO_ADDRESS(DA8XX_PSC1_BASE), +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id da830_ids[] = { + { + .variant = 0x0, + .part_no = 0xb7df, + .manufacturer = 0x017, /* 0x02f >> 1 */ + .cpu_id = DAVINCI_CPU_ID_DA830, + .name = "da830/omap l137", + }, +}; + +static struct davinci_timer_instance da830_timer_instance[2] = { + { + .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_0, + .top_irq = IRQ_DA8XX_TINT34_0, + .cmp_off = DA830_CMP12_0, + .cmp_irq = IRQ_DA830_T12CMPINT0_0, + }, + { + .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_1, + .top_irq = IRQ_DA8XX_TINT34_1, + .cmp_off = DA830_CMP12_0, + .cmp_irq = IRQ_DA830_T12CMPINT0_1, + }, +}; + +/* + * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource + * T0_TOP: Timer 0, top : Used by DSP + * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer + */ +static struct davinci_timer_info da830_timer_info = { + .timers = da830_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_BOT, +}; + +static struct davinci_soc_info davinci_soc_info_da830 = { + .io_desc = da830_io_desc, + .io_desc_num = ARRAY_SIZE(da830_io_desc), + .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG), + .ids = da830_ids, + .ids_num = ARRAY_SIZE(da830_ids), + .cpu_clks = da830_clks, + .psc_bases = da830_psc_bases, + .psc_bases_num = ARRAY_SIZE(da830_psc_bases), + .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), + .pinmux_pins = da830_pins, + .pinmux_pins_num = ARRAY_SIZE(da830_pins), + .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, + .intc_type = DAVINCI_INTC_TYPE_CP_INTC, + .intc_irq_prios = da830_default_priorities, + .intc_irq_num = DA830_N_CP_INTC_IRQ, + .timer_info = &da830_timer_info, + .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), + .gpio_num = 128, + .gpio_irq = IRQ_DA8XX_GPIO0, + .serial_dev = &da8xx_serial_device, + .emac_pdata = &da8xx_emac_pdata, +}; + +void __init da830_init(void) +{ + davinci_common_init(&davinci_soc_info_da830); +} diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c new file mode 100644 index 000000000000..192d719a47df --- /dev/null +++ b/arch/arm/mach-davinci/da850.c @@ -0,0 +1,820 @@ +/* + * TI DA850/OMAP-L138 chip specific setup + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/da830.c + * Original Copyrights follow: + * + * 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <asm/mach/map.h> + +#include <mach/clock.h> +#include <mach/psc.h> +#include <mach/mux.h> +#include <mach/irqs.h> +#include <mach/cputype.h> +#include <mach/common.h> +#include <mach/time.h> +#include <mach/da8xx.h> + +#include "clock.h" +#include "mux.h" + +#define DA850_PLL1_BASE 0x01e1a000 +#define DA850_TIMER64P2_BASE 0x01f0c000 +#define DA850_TIMER64P3_BASE 0x01f0d000 + +#define DA850_REF_FREQ 24000000 + +static struct pll_data pll0_data = { + .num = 1, + .phys_base = DA8XX_PLL0_BASE, + .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DA850_REF_FREQ, +}; + +static struct clk pll0_clk = { + .name = "pll0", + .parent = &ref_clk, + .pll_data = &pll0_data, + .flags = CLK_PLL, +}; + +static struct clk pll0_aux_clk = { + .name = "pll0_aux_clk", + .parent = &pll0_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll0_sysclk2 = { + .name = "pll0_sysclk2", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll0_sysclk3 = { + .name = "pll0_sysclk3", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll0_sysclk4 = { + .name = "pll0_sysclk4", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll0_sysclk5 = { + .name = "pll0_sysclk5", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll0_sysclk6 = { + .name = "pll0_sysclk6", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll0_sysclk7 = { + .name = "pll0_sysclk7", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct pll_data pll1_data = { + .num = 2, + .phys_base = DA850_PLL1_BASE, + .flags = PLL_HAS_POSTDIV, +}; + +static struct clk pll1_clk = { + .name = "pll1", + .parent = &ref_clk, + .pll_data = &pll1_data, + .flags = CLK_PLL, +}; + +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll1_sysclk4 = { + .name = "pll1_sysclk4", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll1_sysclk6 = { + .name = "pll0_sysclk6", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll1_sysclk7 = { + .name = "pll1_sysclk7", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk i2c0_clk = { + .name = "i2c0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_0_clk = { + .name = "timer0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_1_clk = { + .name = "timer1", + .parent = &pll0_aux_clk, +}; + +static struct clk arm_rom_clk = { + .name = "arm_rom", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tpcc0_clk = { + .name = "tpcc0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPCC, + .flags = ALWAYS_ENABLED | CLK_PSC, +}; + +static struct clk tptc0_clk = { + .name = "tptc0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tptc1_clk = { + .name = "tptc1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tpcc1_clk = { + .name = "tpcc1", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_TPCC1, + .flags = CLK_PSC | ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk tptc2_clk = { + .name = "tptc2", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_TPTC2, + .flags = ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART1, + .psc_ctlr = 1, +}; + +static struct clk uart2_clk = { + .name = "uart2", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART2, + .psc_ctlr = 1, +}; + +static struct clk aintc_clk = { + .name = "aintc", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC0_AINTC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_GPIO, + .psc_ctlr = 1, +}; + +static struct clk i2c1_clk = { + .name = "i2c1", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_I2C, + .psc_ctlr = 1, +}; + +static struct clk emif3_clk = { + .name = "emif3", + .parent = &pll0_sysclk5, + .lpsc = DA8XX_LPSC1_EMIF3C, + .flags = ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk arm_clk = { + .name = "arm", + .parent = &pll0_sysclk6, + .lpsc = DA8XX_LPSC0_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk rmii_clk = { + .name = "rmii", + .parent = &pll0_sysclk7, +}; + +static struct clk emac_clk = { + .name = "emac", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_CPGMAC, + .psc_ctlr = 1, +}; + +static struct clk mcasp_clk = { + .name = "mcasp", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_McASP0, + .psc_ctlr = 1, +}; + +static struct clk lcdc_clk = { + .name = "lcdc", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_LCDC, + .psc_ctlr = 1, +}; + +static struct clk mmcsd_clk = { + .name = "mmcsd", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_MMC_SD, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll0_sysclk3, + .lpsc = DA8XX_LPSC0_EMIF25, + .flags = ALWAYS_ENABLED, +}; + +static struct davinci_clk da850_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll0", &pll0_clk), + CLK(NULL, "pll0_aux", &pll0_aux_clk), + CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), + CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), + CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), + CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), + CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), + CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_aux", &pll1_aux_clk), + CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), + CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), + CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), + CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), + CLK("i2c_davinci.1", NULL, &i2c0_clk), + CLK(NULL, "timer0", &timerp64_0_clk), + CLK("watchdog", NULL, &timerp64_1_clk), + CLK(NULL, "arm_rom", &arm_rom_clk), + CLK(NULL, "tpcc0", &tpcc0_clk), + CLK(NULL, "tptc0", &tptc0_clk), + CLK(NULL, "tptc1", &tptc1_clk), + CLK(NULL, "tpcc1", &tpcc1_clk), + CLK(NULL, "tptc2", &tptc2_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK(NULL, "uart2", &uart2_clk), + CLK(NULL, "aintc", &aintc_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK("i2c_davinci.2", NULL, &i2c1_clk), + CLK(NULL, "emif3", &emif3_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "rmii", &rmii_clk), + CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci-mcasp.0", NULL, &mcasp_clk), + CLK("da8xx_lcdc.0", NULL, &lcdc_clk), + CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK(NULL, NULL, NULL), +}; + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config da850_pins[] = { +#ifdef CONFIG_DAVINCI_MUX + /* UART0 function */ + MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) + MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) + MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) + MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) + /* UART1 function */ + MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) + MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) + /* UART2 function */ + MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) + MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) + /* I2C1 function */ + MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) + MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) + /* I2C0 function */ + MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) + MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) + /* EMAC function */ + MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) + MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) + MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) + MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) + MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) + MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) + MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) + MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) + MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) + MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) + MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) + MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) + MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) + MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) + MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) + MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) + MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) + /* McASP function */ + MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) + MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) + MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) + MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) + MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) + MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) + MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) + MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) + MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) + MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) + MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) + MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) + MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) + MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) + MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) + MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) + MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) + MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) + MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) + MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) + MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) + MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) + MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) + /* LCD function */ + MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) + MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) + MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) + MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) + MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) + MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) + MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) + MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) + MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) + MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) + MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) + MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) + MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) + MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) + MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) + MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) + MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) + MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) + MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) + MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) + /* MMC/SD0 function */ + MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) + MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) + MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) + /* EMIF2.5/EMIFA function */ + MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) + MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) + MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) + MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) + MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) + MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) + MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) + MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) + MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) + MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) + MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) + MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) + MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) + MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) + MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) + MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) + MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) + MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) + MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) + MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) + MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) + MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) + MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) + /* GPIO function */ + MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) + MUX_CFG(DA850, GPIO8_10, 18, 28, 15, 8, false) + MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) + MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) +#endif +}; + +const short da850_uart0_pins[] __initdata = { + DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD, + -1 +}; + +const short da850_uart1_pins[] __initdata = { + DA850_UART1_RXD, DA850_UART1_TXD, + -1 +}; + +const short da850_uart2_pins[] __initdata = { + DA850_UART2_RXD, DA850_UART2_TXD, + -1 +}; + +const short da850_i2c0_pins[] __initdata = { + DA850_I2C0_SDA, DA850_I2C0_SCL, + -1 +}; + +const short da850_i2c1_pins[] __initdata = { + DA850_I2C1_SCL, DA850_I2C1_SDA, + -1 +}; + +const short da850_cpgmac_pins[] __initdata = { + DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, + DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, + DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, + DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + +const short da850_mcasp_pins[] __initdata = { + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, + DA850_AXR_11, DA850_AXR_12, + -1 +}; + +const short da850_lcdcntl_pins[] __initdata = { + DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4, + DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8, + DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, DA850_LCD_D_12, + DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, DA850_LCD_PCLK, + DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, DA850_GPIO2_15, + DA850_GPIO8_10, + -1 +}; + +const short da850_mmcsd0_pins[] __initdata = { + DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, + DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, + DA850_GPIO4_0, DA850_GPIO4_1, + -1 +}; + +const short da850_nand_pins[] __initdata = { + DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4, + DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0, + DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, + DA850_NEMA_WE, DA850_NEMA_OE, + -1 +}; + +const short da850_nor_pins[] __initdata = { + DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, + DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, + DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, + DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, + DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, + DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, + DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, + DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, + DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, + DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, + DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, + DA850_EMA_A_22, DA850_EMA_A_23, + -1 +}; + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { + [IRQ_DA8XX_COMMTX] = 7, + [IRQ_DA8XX_COMMRX] = 7, + [IRQ_DA8XX_NINT] = 7, + [IRQ_DA8XX_EVTOUT0] = 7, + [IRQ_DA8XX_EVTOUT1] = 7, + [IRQ_DA8XX_EVTOUT2] = 7, + [IRQ_DA8XX_EVTOUT3] = 7, + [IRQ_DA8XX_EVTOUT4] = 7, + [IRQ_DA8XX_EVTOUT5] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT7] = 7, + [IRQ_DA8XX_CCINT0] = 7, + [IRQ_DA8XX_CCERRINT] = 7, + [IRQ_DA8XX_TCERRINT0] = 7, + [IRQ_DA8XX_AEMIFINT] = 7, + [IRQ_DA8XX_I2CINT0] = 7, + [IRQ_DA8XX_MMCSDINT0] = 7, + [IRQ_DA8XX_MMCSDINT1] = 7, + [IRQ_DA8XX_ALLINT0] = 7, + [IRQ_DA8XX_RTC] = 7, + [IRQ_DA8XX_SPINT0] = 7, + [IRQ_DA8XX_TINT12_0] = 7, + [IRQ_DA8XX_TINT34_0] = 7, + [IRQ_DA8XX_TINT12_1] = 7, + [IRQ_DA8XX_TINT34_1] = 7, + [IRQ_DA8XX_UARTINT0] = 7, + [IRQ_DA8XX_KEYMGRINT] = 7, + [IRQ_DA8XX_SECINT] = 7, + [IRQ_DA8XX_SECKEYERR] = 7, + [IRQ_DA850_MPUADDRERR0] = 7, + [IRQ_DA850_MPUPROTERR0] = 7, + [IRQ_DA850_IOPUADDRERR0] = 7, + [IRQ_DA850_IOPUPROTERR0] = 7, + [IRQ_DA850_IOPUADDRERR1] = 7, + [IRQ_DA850_IOPUPROTERR1] = 7, + [IRQ_DA850_IOPUADDRERR2] = 7, + [IRQ_DA850_IOPUPROTERR2] = 7, + [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7, + [IRQ_DA850_BOOTCFG_PROT_ERR] = 7, + [IRQ_DA850_MPUADDRERR1] = 7, + [IRQ_DA850_MPUPROTERR1] = 7, + [IRQ_DA850_IOPUADDRERR3] = 7, + [IRQ_DA850_IOPUPROTERR3] = 7, + [IRQ_DA850_IOPUADDRERR4] = 7, + [IRQ_DA850_IOPUPROTERR4] = 7, + [IRQ_DA850_IOPUADDRERR5] = 7, + [IRQ_DA850_IOPUPROTERR5] = 7, + [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7, + [IRQ_DA8XX_CHIPINT0] = 7, + [IRQ_DA8XX_CHIPINT1] = 7, + [IRQ_DA8XX_CHIPINT2] = 7, + [IRQ_DA8XX_CHIPINT3] = 7, + [IRQ_DA8XX_TCERRINT1] = 7, + [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C0_RX_PULSE] = 7, + [IRQ_DA8XX_C0_TX_PULSE] = 7, + [IRQ_DA8XX_C0_MISC_PULSE] = 7, + [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C1_RX_PULSE] = 7, + [IRQ_DA8XX_C1_TX_PULSE] = 7, + [IRQ_DA8XX_C1_MISC_PULSE] = 7, + [IRQ_DA8XX_MEMERR] = 7, + [IRQ_DA8XX_GPIO0] = 7, + [IRQ_DA8XX_GPIO1] = 7, + [IRQ_DA8XX_GPIO2] = 7, + [IRQ_DA8XX_GPIO3] = 7, + [IRQ_DA8XX_GPIO4] = 7, + [IRQ_DA8XX_GPIO5] = 7, + [IRQ_DA8XX_GPIO6] = 7, + [IRQ_DA8XX_GPIO7] = 7, + [IRQ_DA8XX_GPIO8] = 7, + [IRQ_DA8XX_I2CINT1] = 7, + [IRQ_DA8XX_LCDINT] = 7, + [IRQ_DA8XX_UARTINT1] = 7, + [IRQ_DA8XX_MCASPINT] = 7, + [IRQ_DA8XX_ALLINT1] = 7, + [IRQ_DA8XX_SPINT1] = 7, + [IRQ_DA8XX_UHPI_INT1] = 7, + [IRQ_DA8XX_USB_INT] = 7, + [IRQ_DA8XX_IRQN] = 7, + [IRQ_DA8XX_RWAKEUP] = 7, + [IRQ_DA8XX_UARTINT2] = 7, + [IRQ_DA8XX_DFTSSINT] = 7, + [IRQ_DA8XX_EHRPWM0] = 7, + [IRQ_DA8XX_EHRPWM0TZ] = 7, + [IRQ_DA8XX_EHRPWM1] = 7, + [IRQ_DA8XX_EHRPWM1TZ] = 7, + [IRQ_DA850_SATAINT] = 7, + [IRQ_DA850_TINT12_2] = 7, + [IRQ_DA850_TINT34_2] = 7, + [IRQ_DA850_TINTALL_2] = 7, + [IRQ_DA8XX_ECAP0] = 7, + [IRQ_DA8XX_ECAP1] = 7, + [IRQ_DA8XX_ECAP2] = 7, + [IRQ_DA850_MMCSDINT0_1] = 7, + [IRQ_DA850_MMCSDINT1_1] = 7, + [IRQ_DA850_T12CMPINT0_2] = 7, + [IRQ_DA850_T12CMPINT1_2] = 7, + [IRQ_DA850_T12CMPINT2_2] = 7, + [IRQ_DA850_T12CMPINT3_2] = 7, + [IRQ_DA850_T12CMPINT4_2] = 7, + [IRQ_DA850_T12CMPINT5_2] = 7, + [IRQ_DA850_T12CMPINT6_2] = 7, + [IRQ_DA850_T12CMPINT7_2] = 7, + [IRQ_DA850_T12CMPINT0_3] = 7, + [IRQ_DA850_T12CMPINT1_3] = 7, + [IRQ_DA850_T12CMPINT2_3] = 7, + [IRQ_DA850_T12CMPINT3_3] = 7, + [IRQ_DA850_T12CMPINT4_3] = 7, + [IRQ_DA850_T12CMPINT5_3] = 7, + [IRQ_DA850_T12CMPINT6_3] = 7, + [IRQ_DA850_T12CMPINT7_3] = 7, + [IRQ_DA850_RPIINT] = 7, + [IRQ_DA850_VPIFINT] = 7, + [IRQ_DA850_CCINT1] = 7, + [IRQ_DA850_CCERRINT1] = 7, + [IRQ_DA850_TCERRINT2] = 7, + [IRQ_DA850_TINT12_3] = 7, + [IRQ_DA850_TINT34_3] = 7, + [IRQ_DA850_TINTALL_3] = 7, + [IRQ_DA850_MCBSP0RINT] = 7, + [IRQ_DA850_MCBSP0XINT] = 7, + [IRQ_DA850_MCBSP1RINT] = 7, + [IRQ_DA850_MCBSP1XINT] = 7, + [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, +}; + +static struct map_desc da850_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = DA8XX_CP_INTC_VIRT, + .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), + .length = DA8XX_CP_INTC_SIZE, + .type = MT_DEVICE + }, +}; + +static void __iomem *da850_psc_bases[] = { + IO_ADDRESS(DA8XX_PSC0_BASE), + IO_ADDRESS(DA8XX_PSC1_BASE), +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id da850_ids[] = { + { + .variant = 0x0, + .part_no = 0xb7d1, + .manufacturer = 0x017, /* 0x02f >> 1 */ + .cpu_id = DAVINCI_CPU_ID_DA850, + .name = "da850/omap-l138", + }, +}; + +static struct davinci_timer_instance da850_timer_instance[4] = { + { + .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_0, + .top_irq = IRQ_DA8XX_TINT34_0, + }, + { + .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_1, + .top_irq = IRQ_DA8XX_TINT34_1, + }, + { + .base = IO_ADDRESS(DA850_TIMER64P2_BASE), + .bottom_irq = IRQ_DA850_TINT12_2, + .top_irq = IRQ_DA850_TINT34_2, + }, + { + .base = IO_ADDRESS(DA850_TIMER64P3_BASE), + .bottom_irq = IRQ_DA850_TINT12_3, + .top_irq = IRQ_DA850_TINT34_3, + }, +}; + +/* + * T0_BOT: Timer 0, bottom : Used for clock_event + * T0_TOP: Timer 0, top : Used for clocksource + * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer + */ +static struct davinci_timer_info da850_timer_info = { + .timers = da850_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +static struct davinci_soc_info davinci_soc_info_da850 = { + .io_desc = da850_io_desc, + .io_desc_num = ARRAY_SIZE(da850_io_desc), + .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG), + .ids = da850_ids, + .ids_num = ARRAY_SIZE(da850_ids), + .cpu_clks = da850_clks, + .psc_bases = da850_psc_bases, + .psc_bases_num = ARRAY_SIZE(da850_psc_bases), + .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), + .pinmux_pins = da850_pins, + .pinmux_pins_num = ARRAY_SIZE(da850_pins), + .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, + .intc_type = DAVINCI_INTC_TYPE_CP_INTC, + .intc_irq_prios = da850_default_priorities, + .intc_irq_num = DA850_N_CP_INTC_IRQ, + .timer_info = &da850_timer_info, + .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), + .gpio_num = 144, + .gpio_irq = IRQ_DA8XX_GPIO0, + .serial_dev = &da8xx_serial_device, + .emac_pdata = &da8xx_emac_pdata, +}; + +void __init da850_init(void) +{ + davinci_common_init(&davinci_soc_info_da850); +} diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c new file mode 100644 index 000000000000..58ad5b66fd60 --- /dev/null +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -0,0 +1,450 @@ +/* + * DA8XX/OMAP L1XX platform device data + * + * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> + * Derived from code that was: + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/serial_8250.h> + +#include <mach/cputype.h> +#include <mach/common.h> +#include <mach/time.h> +#include <mach/da8xx.h> +#include <video/da8xx-fb.h> + +#include "clock.h" + +#define DA8XX_TPCC_BASE 0x01c00000 +#define DA8XX_TPTC0_BASE 0x01c08000 +#define DA8XX_TPTC1_BASE 0x01c08400 +#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ +#define DA8XX_I2C0_BASE 0x01c22000 +#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 +#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 +#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 +#define DA8XX_EMAC_MDIO_BASE 0x01e24000 +#define DA8XX_GPIO_BASE 0x01e26000 +#define DA8XX_I2C1_BASE 0x01e28000 + +#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 +#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 +#define DA8XX_EMAC_RAM_OFFSET 0x0000 +#define DA8XX_MDIO_REG_OFFSET 0x4000 +#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K + +static struct plat_serial8250_port da8xx_serial_pdata[] = { + { + .mapbase = DA8XX_UART0_BASE, + .irq = IRQ_DA8XX_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DA8XX_UART1_BASE, + .irq = IRQ_DA8XX_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DA8XX_UART2_BASE, + .irq = IRQ_DA8XX_UARTINT2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .flags = 0, + }, +}; + +struct platform_device da8xx_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = da8xx_serial_pdata, + }, +}; + +static const s8 da8xx_dma_chan_no_event[] = { + 20, 21, + -1 +}; + +static const s8 da8xx_queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1} +}; + +static const s8 da8xx_queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1} +}; + +static struct edma_soc_info da8xx_edma_info[] = { + { + .n_channel = 32, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .noevent = da8xx_dma_chan_no_event, + .queue_tc_mapping = da8xx_queue_tc_mapping, + .queue_priority_mapping = da8xx_queue_priority_mapping, + }, +}; + +static struct resource da8xx_edma_resources[] = { + { + .name = "edma_cc0", + .start = DA8XX_TPCC_BASE, + .end = DA8XX_TPCC_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = DA8XX_TPTC0_BASE, + .end = DA8XX_TPTC0_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = DA8XX_TPTC1_BASE, + .end = DA8XX_TPTC1_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma0", + .start = IRQ_DA8XX_CCINT0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "edma0_err", + .start = IRQ_DA8XX_CCERRINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_edma_device = { + .name = "edma", + .id = -1, + .dev = { + .platform_data = da8xx_edma_info, + }, + .num_resources = ARRAY_SIZE(da8xx_edma_resources), + .resource = da8xx_edma_resources, +}; + +int __init da8xx_register_edma(void) +{ + return platform_device_register(&da8xx_edma_device); +} + +static struct resource da8xx_i2c_resources0[] = { + { + .start = DA8XX_I2C0_BASE, + .end = DA8XX_I2C0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_I2CINT0, + .end = IRQ_DA8XX_I2CINT0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_i2c_device0 = { + .name = "i2c_davinci", + .id = 1, + .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), + .resource = da8xx_i2c_resources0, +}; + +static struct resource da8xx_i2c_resources1[] = { + { + .start = DA8XX_I2C1_BASE, + .end = DA8XX_I2C1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_I2CINT1, + .end = IRQ_DA8XX_I2CINT1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_i2c_device1 = { + .name = "i2c_davinci", + .id = 2, + .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), + .resource = da8xx_i2c_resources1, +}; + +int __init da8xx_register_i2c(int instance, + struct davinci_i2c_platform_data *pdata) +{ + struct platform_device *pdev; + + if (instance == 0) + pdev = &da8xx_i2c_device0; + else if (instance == 1) + pdev = &da8xx_i2c_device1; + else + return -EINVAL; + + pdev->dev.platform_data = pdata; + return platform_device_register(pdev); +} + +static struct resource da8xx_watchdog_resources[] = { + { + .start = DA8XX_WDOG_BASE, + .end = DA8XX_WDOG_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device davinci_wdt_device = { + .name = "watchdog", + .id = -1, + .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), + .resource = da8xx_watchdog_resources, +}; + +int __init da8xx_register_watchdog(void) +{ + return platform_device_register(&davinci_wdt_device); +} + +static struct resource da8xx_emac_resources[] = { + { + .start = DA8XX_EMAC_CPPI_PORT_BASE, + .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, + .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_C0_RX_PULSE, + .end = IRQ_DA8XX_C0_RX_PULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_C0_TX_PULSE, + .end = IRQ_DA8XX_C0_TX_PULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_C0_MISC_PULSE, + .end = IRQ_DA8XX_C0_MISC_PULSE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct emac_platform_data da8xx_emac_pdata = { + .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, + .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, + .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, + .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET, + .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, + .version = EMAC_VERSION_2, +}; + +static struct platform_device da8xx_emac_device = { + .name = "davinci_emac", + .id = 1, + .dev = { + .platform_data = &da8xx_emac_pdata, + }, + .num_resources = ARRAY_SIZE(da8xx_emac_resources), + .resource = da8xx_emac_resources, +}; + +static struct resource da830_mcasp1_resources[] = { + { + .name = "mcasp1", + .start = DAVINCI_DA830_MCASP1_REG_BASE, + .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, + .flags = IORESOURCE_MEM, + }, + /* TX event */ + { + .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, + .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, + .flags = IORESOURCE_DMA, + }, + /* RX event */ + { + .start = DAVINCI_DA830_DMA_MCASP1_AREVT, + .end = DAVINCI_DA830_DMA_MCASP1_AREVT, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da830_mcasp1_device = { + .name = "davinci-mcasp", + .id = 1, + .num_resources = ARRAY_SIZE(da830_mcasp1_resources), + .resource = da830_mcasp1_resources, +}; + +static struct resource da850_mcasp_resources[] = { + { + .name = "mcasp", + .start = DAVINCI_DA8XX_MCASP0_REG_BASE, + .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, + .flags = IORESOURCE_MEM, + }, + /* TX event */ + { + .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, + .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, + .flags = IORESOURCE_DMA, + }, + /* RX event */ + { + .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, + .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da850_mcasp_device = { + .name = "davinci-mcasp", + .id = 0, + .num_resources = ARRAY_SIZE(da850_mcasp_resources), + .resource = da850_mcasp_resources, +}; + +int __init da8xx_register_emac(void) +{ + return platform_device_register(&da8xx_emac_device); +} + +void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata) +{ + /* DA830/OMAP-L137 has 3 instances of McASP */ + if (cpu_is_davinci_da830() && id == 1) { + da830_mcasp1_device.dev.platform_data = pdata; + platform_device_register(&da830_mcasp1_device); + } else if (cpu_is_davinci_da850()) { + da850_mcasp_device.dev.platform_data = pdata; + platform_device_register(&da850_mcasp_device); + } +} + +static const struct display_panel disp_panel = { + QVGA, + 16, + 16, + COLOR_ACTIVE, +}; + +static struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 255, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static struct da8xx_lcdc_platform_data da850_evm_lcdc_pdata = { + .manu_name = "sharp", + .controller_data = &lcd_cfg, + .type = "Sharp_LK043T1DG01", +}; + +static struct resource da8xx_lcdc_resources[] = { + [0] = { /* registers */ + .start = DA8XX_LCD_CNTRL_BASE, + .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { /* interrupt */ + .start = IRQ_DA8XX_LCDINT, + .end = IRQ_DA8XX_LCDINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da850_lcdc_device = { + .name = "da8xx_lcdc", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), + .resource = da8xx_lcdc_resources, + .dev = { + .platform_data = &da850_evm_lcdc_pdata, + } +}; + +int __init da8xx_register_lcdc(void) +{ + return platform_device_register(&da850_lcdc_device); +} + +static struct resource da8xx_mmcsd0_resources[] = { + { /* registers */ + .start = DA8XX_MMCSD0_BASE, + .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* interrupt */ + .start = IRQ_DA8XX_MMCSDINT0, + .end = IRQ_DA8XX_MMCSDINT0, + .flags = IORESOURCE_IRQ, + }, + { /* DMA RX */ + .start = EDMA_CTLR_CHAN(0, 16), + .end = EDMA_CTLR_CHAN(0, 16), + .flags = IORESOURCE_DMA, + }, + { /* DMA TX */ + .start = EDMA_CTLR_CHAN(0, 17), + .end = EDMA_CTLR_CHAN(0, 17), + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da8xx_mmcsd0_device = { + .name = "davinci_mmc", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), + .resource = da8xx_mmcsd0_resources, +}; + +int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) +{ + da8xx_mmcsd0_device.dev.platform_data = config; + return platform_device_register(&da8xx_mmcsd0_device); +} diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index de16f347566a..a55b650db71e 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -31,6 +31,8 @@ #define DAVINCI_MMCSD0_BASE 0x01E10000 #define DM355_MMCSD0_BASE 0x01E11000 #define DM355_MMCSD1_BASE 0x01E00000 +#define DM365_MMCSD0_BASE 0x01D11000 +#define DM365_MMCSD1_BASE 0x01D00000 static struct resource i2c_resources[] = { { @@ -82,10 +84,10 @@ static struct resource mmcsd0_resources[] = { }, /* DMA channels: RX, then TX */ { - .start = DAVINCI_DMA_MMCRXEVT, + .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT), .flags = IORESOURCE_DMA, }, { - .start = DAVINCI_DMA_MMCTXEVT, + .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT), .flags = IORESOURCE_DMA, }, }; @@ -119,10 +121,10 @@ static struct resource mmcsd1_resources[] = { }, /* DMA channels: RX, then TX */ { - .start = 30, /* rx */ + .start = EDMA_CTLR_CHAN(0, 30), /* rx */ .flags = IORESOURCE_DMA, }, { - .start = 31, /* tx */ + .start = EDMA_CTLR_CHAN(0, 31), /* tx */ .flags = IORESOURCE_DMA, }, }; @@ -154,19 +156,31 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) */ switch (module) { case 1: - if (!cpu_is_davinci_dm355()) + if (cpu_is_davinci_dm355()) { + /* REVISIT we may not need all these pins if e.g. this + * is a hard-wired SDIO device... + */ + davinci_cfg_reg(DM355_SD1_CMD); + davinci_cfg_reg(DM355_SD1_CLK); + davinci_cfg_reg(DM355_SD1_DATA0); + davinci_cfg_reg(DM355_SD1_DATA1); + davinci_cfg_reg(DM355_SD1_DATA2); + davinci_cfg_reg(DM355_SD1_DATA3); + } else if (cpu_is_davinci_dm365()) { + void __iomem *pupdctl1 = + IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); + + /* Configure pull down control */ + __raw_writel((__raw_readl(pupdctl1) & ~0x400), + pupdctl1); + + mmcsd1_resources[0].start = DM365_MMCSD1_BASE; + mmcsd1_resources[0].end = DM365_MMCSD1_BASE + + SZ_4K - 1; + mmcsd0_resources[2].start = IRQ_DM365_SDIOINT1; + } else break; - /* REVISIT we may not need all these pins if e.g. this - * is a hard-wired SDIO device... - */ - davinci_cfg_reg(DM355_SD1_CMD); - davinci_cfg_reg(DM355_SD1_CLK); - davinci_cfg_reg(DM355_SD1_DATA0); - davinci_cfg_reg(DM355_SD1_DATA1); - davinci_cfg_reg(DM355_SD1_DATA2); - davinci_cfg_reg(DM355_SD1_DATA3); - pdev = &davinci_mmcsd1_device; break; case 0: @@ -180,9 +194,12 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) /* enable RX EDMA */ davinci_cfg_reg(DM355_EVT26_MMC0_RX); - } - - else if (cpu_is_davinci_dm644x()) { + } else if (cpu_is_davinci_dm365()) { + mmcsd0_resources[0].start = DM365_MMCSD0_BASE; + mmcsd0_resources[0].end = DM365_MMCSD0_BASE + + SZ_4K - 1; + mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0; + } else if (cpu_is_davinci_dm644x()) { /* REVISIT: should this be in board-init code? */ void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); @@ -216,6 +233,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) static struct resource wdt_resources[] = { { + .start = DAVINCI_WDOG_BASE, + .end = DAVINCI_WDOG_BASE + SZ_1K - 1, .flags = IORESOURCE_MEM, }, }; @@ -229,11 +248,6 @@ struct platform_device davinci_wdt_device = { static void davinci_init_wdt(void) { - struct davinci_soc_info *soc_info = &davinci_soc_info; - - wdt_resources[0].start = (resource_size_t)soc_info->wdt_base; - wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1; - platform_device_register(&davinci_wdt_device); } diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index baaaf328de2e..059670018aff 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -30,6 +30,7 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <mach/asp.h> #include "clock.h" #include "mux.h" @@ -360,8 +361,8 @@ static struct davinci_clk dm355_clks[] = { CLK(NULL, "uart1", &uart1_clk), CLK(NULL, "uart2", &uart2_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("soc-audio.0", NULL, &asp0_clk), - CLK("soc-audio.1", NULL, &asp1_clk), + CLK("davinci-asp.0", NULL, &asp0_clk), + CLK("davinci-asp.1", NULL, &asp1_clk), CLK("davinci_mmc.0", NULL, &mmcsd0_clk), CLK("davinci_mmc.1", NULL, &mmcsd1_clk), CLK(NULL, "spi0", &spi0_clk), @@ -481,6 +482,20 @@ INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false) EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) + +MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false) +MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false) +MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false) +MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) +MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) + +MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false) +MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false) +MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false) +MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false) +MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false) +MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false) +MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false) #endif }; @@ -558,17 +573,38 @@ static const s8 dma_chan_dm355_no_event[] = { -1 }; -static struct edma_soc_info dm355_edma_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .noevent = dma_chan_dm355_no_event, +static const s8 +queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1}, +}; + +static const s8 +queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1}, +}; + +static struct edma_soc_info dm355_edma_info[] = { + { + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .noevent = dma_chan_dm355_no_event, + .queue_tc_mapping = queue_tc_mapping, + .queue_priority_mapping = queue_priority_mapping, + }, }; static struct resource edma_resources[] = { { - .name = "edma_cc", + .name = "edma_cc0", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, @@ -586,10 +622,12 @@ static struct resource edma_resources[] = { .flags = IORESOURCE_MEM, }, { + .name = "edma0", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { + .name = "edma0_err", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -598,12 +636,98 @@ static struct resource edma_resources[] = { static struct platform_device dm355_edma_device = { .name = "edma", - .id = -1, - .dev.platform_data = &dm355_edma_info, + .id = 0, + .dev.platform_data = dm355_edma_info, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; +static struct resource dm355_asp1_resources[] = { + { + .start = DAVINCI_ASP1_BASE, + .end = DAVINCI_ASP1_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DAVINCI_DMA_ASP1_TX, + .end = DAVINCI_DMA_ASP1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = DAVINCI_DMA_ASP1_RX, + .end = DAVINCI_DMA_ASP1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device dm355_asp1_device = { + .name = "davinci-asp", + .id = 1, + .num_resources = ARRAY_SIZE(dm355_asp1_resources), + .resource = dm355_asp1_resources, +}; + +static struct resource dm355_vpss_resources[] = { + { + /* VPSS BL Base address */ + .name = "vpss", + .start = 0x01c70800, + .end = 0x01c70800 + 0xff, + .flags = IORESOURCE_MEM, + }, + { + /* VPSS CLK Base address */ + .name = "vpss", + .start = 0x01c70000, + .end = 0x01c70000 + 0xf, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm355_vpss_device = { + .name = "vpss", + .id = -1, + .dev.platform_data = "dm355_vpss", + .num_resources = ARRAY_SIZE(dm355_vpss_resources), + .resource = dm355_vpss_resources, +}; + +static struct resource vpfe_resources[] = { + { + .start = IRQ_VDINT0, + .end = IRQ_VDINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_VDINT1, + .end = IRQ_VDINT1, + .flags = IORESOURCE_IRQ, + }, + /* CCDC Base address */ + { + .flags = IORESOURCE_MEM, + .start = 0x01c70600, + .end = 0x01c70600 + 0x1ff, + }, +}; + +static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); +static struct platform_device vpfe_capture_dev = { + .name = CAPTURE_DRV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(vpfe_resources), + .resource = vpfe_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void dm355_set_vpfe_config(struct vpfe_config *cfg) +{ + vpfe_capture_dev.dev.platform_data = cfg; +} + /*----------------------------------------------------------------------*/ static struct map_desc dm355_io_desc[] = { @@ -704,7 +828,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { .intc_irq_prios = dm355_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm355_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), .gpio_num = 104, .gpio_irq = IRQ_DM355_GPIOBNK0, @@ -713,6 +836,19 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { .sram_len = SZ_32K, }; +void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) +{ + /* we don't use ASP1 IRQs, or we'd need to mux them ... */ + if (evt_enable & ASP1_TX_EVT_EN) + davinci_cfg_reg(DM355_EVT8_ASP1_TX); + + if (evt_enable & ASP1_RX_EVT_EN) + davinci_cfg_reg(DM355_EVT9_ASP1_RX); + + dm355_asp1_device.dev.platform_data = pdata; + platform_device_register(&dm355_asp1_device); +} + void __init dm355_init(void) { davinci_common_init(&davinci_soc_info_dm355); @@ -725,6 +861,20 @@ static int __init dm355_init_devices(void) davinci_cfg_reg(DM355_INT_EDMA_CC); platform_device_register(&dm355_edma_device); + platform_device_register(&dm355_vpss_device); + /* + * setup Mux configuration for vpfe input and register + * vpfe capture platform device + */ + davinci_cfg_reg(DM355_VIN_PCLK); + davinci_cfg_reg(DM355_VIN_CAM_WEN); + davinci_cfg_reg(DM355_VIN_CAM_VD); + davinci_cfg_reg(DM355_VIN_CAM_HD); + davinci_cfg_reg(DM355_VIN_YIN_EN); + davinci_cfg_reg(DM355_VIN_CINL_EN); + davinci_cfg_reg(DM355_VIN_CINH_EN); + platform_device_register(&vpfe_capture_dev); + return 0; } postcore_initcall(dm355_init_devices); diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c new file mode 100644 index 000000000000..e81517434703 --- /dev/null +++ b/arch/arm/mach-davinci/dm365.c @@ -0,0 +1,926 @@ +/* + * TI DaVinci DM365 chip specific setup + * + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/serial_8250.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/gpio.h> + +#include <asm/mach/map.h> + +#include <mach/dm365.h> +#include <mach/clock.h> +#include <mach/cputype.h> +#include <mach/edma.h> +#include <mach/psc.h> +#include <mach/mux.h> +#include <mach/irqs.h> +#include <mach/time.h> +#include <mach/serial.h> +#include <mach/common.h> + +#include "clock.h" +#include "mux.h" + +#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ + +static struct pll_data pll1_data = { + .num = 1, + .phys_base = DAVINCI_PLL1_BASE, + .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, +}; + +static struct pll_data pll2_data = { + .num = 2, + .phys_base = DAVINCI_PLL2_BASE, + .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DM365_REF_FREQ, +}; + +static struct clk pll1_clk = { + .name = "pll1", + .parent = &ref_clk, + .flags = CLK_PLL, + .pll_data = &pll1_data, +}; + +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk clkout0_clk = { + .name = "clkout0", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclk1 = { + .name = "pll1_sysclk1", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll1_sysclk4 = { + .name = "pll1_sysclk4", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll1_sysclk6 = { + .name = "pll1_sysclk6", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll1_sysclk7 = { + .name = "pll1_sysclk7", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk pll1_sysclk8 = { + .name = "pll1_sysclk8", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV8, +}; + +static struct clk pll1_sysclk9 = { + .name = "pll1_sysclk9", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV9, +}; + +static struct clk pll2_clk = { + .name = "pll2", + .parent = &ref_clk, + .flags = CLK_PLL, + .pll_data = &pll2_data, +}; + +static struct clk pll2_aux_clk = { + .name = "pll2_aux_clk", + .parent = &pll2_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk clkout1_clk = { + .name = "clkout1", + .parent = &pll2_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll2_sysclk1 = { + .name = "pll2_sysclk1", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll2_sysclk2 = { + .name = "pll2_sysclk2", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll2_sysclk3 = { + .name = "pll2_sysclk3", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll2_sysclk4 = { + .name = "pll2_sysclk4", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll2_sysclk5 = { + .name = "pll2_sysclk5", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll2_sysclk6 = { + .name = "pll2_sysclk6", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll2_sysclk7 = { + .name = "pll2_sysclk7", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk pll2_sysclk8 = { + .name = "pll2_sysclk8", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV8, +}; + +static struct clk pll2_sysclk9 = { + .name = "pll2_sysclk9", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV9, +}; + +static struct clk vpss_dac_clk = { + .name = "vpss_dac", + .parent = &pll1_sysclk3, + .lpsc = DM365_LPSC_DAC_CLK, +}; + +static struct clk vpss_master_clk = { + .name = "vpss_master", + .parent = &pll1_sysclk5, + .lpsc = DM365_LPSC_VPSSMSTR, + .flags = CLK_PSC, +}; + +static struct clk arm_clk = { + .name = "arm_clk", + .parent = &pll2_sysclk2, + .lpsc = DAVINCI_LPSC_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_UART1, +}; + +static struct clk i2c_clk = { + .name = "i2c", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_I2C, +}; + +static struct clk mmcsd0_clk = { + .name = "mmcsd0", + .parent = &pll1_sysclk8, + .lpsc = DAVINCI_LPSC_MMC_SD, +}; + +static struct clk mmcsd1_clk = { + .name = "mmcsd1", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_MMC_SD1, +}; + +static struct clk spi0_clk = { + .name = "spi0", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_SPI, +}; + +static struct clk spi1_clk = { + .name = "spi1", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_SPI1, +}; + +static struct clk spi2_clk = { + .name = "spi2", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_SPI2, +}; + +static struct clk spi3_clk = { + .name = "spi3", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_SPI3, +}; + +static struct clk spi4_clk = { + .name = "spi4", + .parent = &pll1_aux_clk, + .lpsc = DM365_LPSC_SPI4, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_GPIO, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_AEMIF, +}; + +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM0, +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM1, +}; + +static struct clk pwm2_clk = { + .name = "pwm2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM2, +}; + +static struct clk pwm3_clk = { + .name = "pwm3", + .parent = &ref_clk, + .lpsc = DM365_LPSC_PWM3, +}; + +static struct clk timer0_clk = { + .name = "timer0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER0, +}; + +static struct clk timer1_clk = { + .name = "timer1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER1, +}; + +static struct clk timer2_clk = { + .name = "timer2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER2, + .usecount = 1, +}; + +static struct clk timer3_clk = { + .name = "timer3", + .parent = &pll1_aux_clk, + .lpsc = DM365_LPSC_TIMER3, +}; + +static struct clk usb_clk = { + .name = "usb", + .parent = &pll2_sysclk1, + .lpsc = DAVINCI_LPSC_USB, +}; + +static struct clk emac_clk = { + .name = "emac", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_EMAC, +}; + +static struct clk voicecodec_clk = { + .name = "voice_codec", + .parent = &pll2_sysclk4, + .lpsc = DM365_LPSC_VOICE_CODEC, +}; + +static struct clk asp0_clk = { + .name = "asp0", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_McBSP1, +}; + +static struct clk rto_clk = { + .name = "rto", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_RTO, +}; + +static struct clk mjcp_clk = { + .name = "mjcp", + .parent = &pll1_sysclk3, + .lpsc = DM365_LPSC_MJCP, +}; + +static struct davinci_clk dm365_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_aux", &pll1_aux_clk), + CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), + CLK(NULL, "clkout0", &clkout0_clk), + CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), + CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), + CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), + CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), + CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), + CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), + CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), + CLK(NULL, "pll2", &pll2_clk), + CLK(NULL, "pll2_aux", &pll2_aux_clk), + CLK(NULL, "clkout1", &clkout1_clk), + CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), + CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), + CLK(NULL, "pll2_sysclk3", &pll2_sysclk3), + CLK(NULL, "pll2_sysclk4", &pll2_sysclk4), + CLK(NULL, "pll2_sysclk5", &pll2_sysclk5), + CLK(NULL, "pll2_sysclk6", &pll2_sysclk6), + CLK(NULL, "pll2_sysclk7", &pll2_sysclk7), + CLK(NULL, "pll2_sysclk8", &pll2_sysclk8), + CLK(NULL, "pll2_sysclk9", &pll2_sysclk9), + CLK(NULL, "vpss_dac", &vpss_dac_clk), + CLK(NULL, "vpss_master", &vpss_master_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK("i2c_davinci.1", NULL, &i2c_clk), + CLK("davinci_mmc.0", NULL, &mmcsd0_clk), + CLK("davinci_mmc.1", NULL, &mmcsd1_clk), + CLK("spi_davinci.0", NULL, &spi0_clk), + CLK("spi_davinci.1", NULL, &spi1_clk), + CLK("spi_davinci.2", NULL, &spi2_clk), + CLK("spi_davinci.3", NULL, &spi3_clk), + CLK("spi_davinci.4", NULL, &spi4_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK(NULL, "pwm0", &pwm0_clk), + CLK(NULL, "pwm1", &pwm1_clk), + CLK(NULL, "pwm2", &pwm2_clk), + CLK(NULL, "pwm3", &pwm3_clk), + CLK(NULL, "timer0", &timer0_clk), + CLK(NULL, "timer1", &timer1_clk), + CLK("watchdog", NULL, &timer2_clk), + CLK(NULL, "timer3", &timer3_clk), + CLK(NULL, "usb", &usb_clk), + CLK("davinci_emac.1", NULL, &emac_clk), + CLK("voice_codec", NULL, &voicecodec_clk), + CLK("soc-audio.0", NULL, &asp0_clk), + CLK(NULL, "rto", &rto_clk), + CLK(NULL, "mjcp", &mjcp_clk), + CLK(NULL, NULL, NULL), +}; + +/*----------------------------------------------------------------------*/ + +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define INTMUX 0x18 +#define EVTMUX 0x1c + + +static const struct mux_config dm365_pins[] = { +#ifdef CONFIG_DAVINCI_MUX +MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false) + +MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false) +MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false) +MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false) +MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false) +MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false) +MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false) + +MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) +MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) + +MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false) +MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) +MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) +MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) +MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) + +MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) +MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) +MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false) +MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false) +MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false) +MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false) + +MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false) +MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false) +MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false) +MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false) +MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false) + +MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false) +MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false) +MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false) +MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false) +MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false) +MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false) + +MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false) +MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false) +MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false) +MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false) +MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false) +MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false) +MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false) +MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false) +MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false) +MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false) +MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false) +MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false) +MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false) +MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false) +MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false) +MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false) +MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false) + +MUX_CFG(DM365, KEYPAD, 2, 0, 0x3f, 0x3f, false) + +MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false) +MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false) +MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false) +MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false) +MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false) +MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false) +MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false) +MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false) +MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false) +MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false) +MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false) +MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false) + +MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false) +MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false) +MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false) +MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false) +MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false) + +MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false) +MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false) +MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false) +MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false) +MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false) + +MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false) +MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false) +MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false) +MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false) +MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false) + +MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false) +MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false) +MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false) +MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) +MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) + +MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) +MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) +MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) + +MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) +MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) +MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false) +MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) +MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) +MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false) +MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false) +MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false) +MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false) +MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false) + +INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false) +INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false) +INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false) +INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false) +INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false) +INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false) +INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false) +INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false) +INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false) +INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false) +INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false) +INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false) +INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false) +INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false) +INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false) +INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false) +INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false) +INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false) +#endif +}; + +static struct emac_platform_data dm365_emac_pdata = { + .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, + .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, + .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET, + .mdio_reg_offset = DM365_EMAC_MDIO_OFFSET, + .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE, + .version = EMAC_VERSION_2, +}; + +static struct resource dm365_emac_resources[] = { + { + .start = DM365_EMAC_BASE, + .end = DM365_EMAC_BASE + 0x47ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DM365_EMAC_RXTHRESH, + .end = IRQ_DM365_EMAC_RXTHRESH, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM365_EMAC_RXPULSE, + .end = IRQ_DM365_EMAC_RXPULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM365_EMAC_TXPULSE, + .end = IRQ_DM365_EMAC_TXPULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM365_EMAC_MISCPULSE, + .end = IRQ_DM365_EMAC_MISCPULSE, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dm365_emac_device = { + .name = "davinci_emac", + .id = 1, + .dev = { + .platform_data = &dm365_emac_pdata, + }, + .num_resources = ARRAY_SIZE(dm365_emac_resources), + .resource = dm365_emac_resources, +}; + +static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_VDINT0] = 2, + [IRQ_VDINT1] = 6, + [IRQ_VDINT2] = 6, + [IRQ_HISTINT] = 6, + [IRQ_H3AINT] = 6, + [IRQ_PRVUINT] = 6, + [IRQ_RSZINT] = 6, + [IRQ_DM365_INSFINT] = 7, + [IRQ_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_DM365_IMCOPINT] = 4, + [IRQ_USBINT] = 4, + [IRQ_DM365_RTOINT] = 7, + [IRQ_DM365_TINT5] = 7, + [IRQ_DM365_TINT6] = 5, + [IRQ_CCINT0] = 5, + [IRQ_CCERRINT] = 5, + [IRQ_TCERRINT0] = 5, + [IRQ_TCERRINT] = 7, + [IRQ_PSCIN] = 4, + [IRQ_DM365_SPINT2_1] = 7, + [IRQ_DM365_TINT7] = 7, + [IRQ_DM365_SDIOINT0] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_DM365_MMCINT1] = 7, + [IRQ_DM365_PWMINT3] = 7, + [IRQ_DDRINT] = 4, + [IRQ_AEMIFINT] = 2, + [IRQ_DM365_SDIOINT1] = 2, + [IRQ_TINT0_TINT12] = 7, + [IRQ_TINT0_TINT34] = 7, + [IRQ_TINT1_TINT12] = 7, + [IRQ_TINT1_TINT34] = 7, + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 3, + [IRQ_PWMINT2] = 3, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_DM365_SPIINT0_0] = 3, + [IRQ_DM365_SPIINT3_0] = 3, + [IRQ_DM365_GPIO0] = 3, + [IRQ_DM365_GPIO1] = 7, + [IRQ_DM365_GPIO2] = 4, + [IRQ_DM365_GPIO3] = 4, + [IRQ_DM365_GPIO4] = 7, + [IRQ_DM365_GPIO5] = 7, + [IRQ_DM365_GPIO6] = 7, + [IRQ_DM365_GPIO7] = 7, + [IRQ_DM365_EMAC_RXTHRESH] = 7, + [IRQ_DM365_EMAC_RXPULSE] = 7, + [IRQ_DM365_EMAC_TXPULSE] = 7, + [IRQ_DM365_EMAC_MISCPULSE] = 7, + [IRQ_DM365_GPIO12] = 7, + [IRQ_DM365_GPIO13] = 7, + [IRQ_DM365_GPIO14] = 7, + [IRQ_DM365_GPIO15] = 7, + [IRQ_DM365_KEYINT] = 7, + [IRQ_DM365_TCERRINT2] = 7, + [IRQ_DM365_TCERRINT3] = 7, + [IRQ_DM365_EMUINT] = 7, +}; + +/* Four Transfer Controllers on DM365 */ +static const s8 +dm365_queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {2, 2}, + {3, 3}, + {-1, -1}, +}; + +static const s8 +dm365_queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 7}, + {1, 7}, + {2, 7}, + {3, 0}, + {-1, -1}, +}; + +static struct edma_soc_info dm365_edma_info[] = { + { + .n_channel = 64, + .n_region = 4, + .n_slot = 256, + .n_tc = 4, + .n_cc = 1, + .queue_tc_mapping = dm365_queue_tc_mapping, + .queue_priority_mapping = dm365_queue_priority_mapping, + .default_queue = EVENTQ_2, + }, +}; + +static struct resource edma_resources[] = { + { + .name = "edma_cc0", + .start = 0x01c00000, + .end = 0x01c00000 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = 0x01c10000, + .end = 0x01c10000 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = 0x01c10400, + .end = 0x01c10400 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc2", + .start = 0x01c10800, + .end = 0x01c10800 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc3", + .start = 0x01c10c00, + .end = 0x01c10c00 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma0", + .start = IRQ_CCINT0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "edma0_err", + .start = IRQ_CCERRINT, + .flags = IORESOURCE_IRQ, + }, + /* not using TC*_ERR */ +}; + +static struct platform_device dm365_edma_device = { + .name = "edma", + .id = 0, + .dev.platform_data = dm365_edma_info, + .num_resources = ARRAY_SIZE(edma_resources), + .resource = edma_resources, +}; + +static struct map_desc dm365_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = SRAM_VIRT, + .pfn = __phys_to_pfn(0x00010000), + .length = SZ_32K, + /* MT_MEMORY_NONCACHED requires supersection alignment */ + .type = MT_DEVICE, + }, +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id dm365_ids[] = { + { + .variant = 0x0, + .part_no = 0xb83e, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DM365, + .name = "dm365_rev1.1", + }, + { + .variant = 0x8, + .part_no = 0xb83e, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DM365, + .name = "dm365_rev1.2", + }, +}; + +static void __iomem *dm365_psc_bases[] = { + IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), +}; + +struct davinci_timer_info dm365_timer_info = { + .timers = davinci_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +static struct plat_serial8250_port dm365_serial_platform_data[] = { + { + .mapbase = DAVINCI_UART0_BASE, + .irq = IRQ_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART1_BASE, + .irq = IRQ_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .flags = 0 + }, +}; + +static struct platform_device dm365_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm365_serial_platform_data, + }, +}; + +static struct davinci_soc_info davinci_soc_info_dm365 = { + .io_desc = dm365_io_desc, + .io_desc_num = ARRAY_SIZE(dm365_io_desc), + .jtag_id_base = IO_ADDRESS(0x01c40028), + .ids = dm365_ids, + .ids_num = ARRAY_SIZE(dm365_ids), + .cpu_clks = dm365_clks, + .psc_bases = dm365_psc_bases, + .psc_bases_num = ARRAY_SIZE(dm365_psc_bases), + .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_pins = dm365_pins, + .pinmux_pins_num = ARRAY_SIZE(dm365_pins), + .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_type = DAVINCI_INTC_TYPE_AINTC, + .intc_irq_prios = dm365_default_priorities, + .intc_irq_num = DAVINCI_N_AINTC_IRQ, + .timer_info = &dm365_timer_info, + .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), + .gpio_num = 104, + .gpio_irq = IRQ_DM365_GPIO0, + .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ + .serial_dev = &dm365_serial_device, + .emac_pdata = &dm365_emac_pdata, + .sram_dma = 0x00010000, + .sram_len = SZ_32K, +}; + +void __init dm365_init(void) +{ + davinci_common_init(&davinci_soc_info_dm365); +} + +static int __init dm365_init_devices(void) +{ + if (!cpu_is_davinci_dm365()) + return 0; + + davinci_cfg_reg(DM365_INT_EDMA_CC); + platform_device_register(&dm365_edma_device); + platform_device_register(&dm365_emac_device); + + return 0; +} +postcore_initcall(dm365_init_devices); diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index fb5449b3c97b..d6e0fa5a8d8a 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -27,6 +27,7 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <mach/asp.h> #include "clock.h" #include "mux.h" @@ -303,7 +304,7 @@ struct davinci_clk dm644x_clks[] = { CLK("davinci_emac.1", NULL, &emac_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK("palm_bk3710", NULL, &ide_clk), - CLK("soc-audio.0", NULL, &asp_clk), + CLK("davinci-asp", NULL, &asp_clk), CLK("davinci_mmc.0", NULL, &mmcsd_clk), CLK(NULL, "spi", &spi_clk), CLK(NULL, "gpio", &gpio_clk), @@ -484,17 +485,38 @@ static const s8 dma_chan_dm644x_no_event[] = { -1 }; -static struct edma_soc_info dm644x_edma_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .noevent = dma_chan_dm644x_no_event, +static const s8 +queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1}, +}; + +static const s8 +queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1}, +}; + +static struct edma_soc_info dm644x_edma_info[] = { + { + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .noevent = dma_chan_dm644x_no_event, + .queue_tc_mapping = queue_tc_mapping, + .queue_priority_mapping = queue_priority_mapping, + }, }; static struct resource edma_resources[] = { { - .name = "edma_cc", + .name = "edma_cc0", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, @@ -512,10 +534,12 @@ static struct resource edma_resources[] = { .flags = IORESOURCE_MEM, }, { + .name = "edma0", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { + .name = "edma0_err", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -524,12 +548,91 @@ static struct resource edma_resources[] = { static struct platform_device dm644x_edma_device = { .name = "edma", - .id = -1, - .dev.platform_data = &dm644x_edma_info, + .id = 0, + .dev.platform_data = dm644x_edma_info, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; +/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ +static struct resource dm644x_asp_resources[] = { + { + .start = DAVINCI_ASP0_BASE, + .end = DAVINCI_ASP0_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DAVINCI_DMA_ASP0_TX, + .end = DAVINCI_DMA_ASP0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = DAVINCI_DMA_ASP0_RX, + .end = DAVINCI_DMA_ASP0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device dm644x_asp_device = { + .name = "davinci-asp", + .id = -1, + .num_resources = ARRAY_SIZE(dm644x_asp_resources), + .resource = dm644x_asp_resources, +}; + +static struct resource dm644x_vpss_resources[] = { + { + /* VPSS Base address */ + .name = "vpss", + .start = 0x01c73400, + .end = 0x01c73400 + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm644x_vpss_device = { + .name = "vpss", + .id = -1, + .dev.platform_data = "dm644x_vpss", + .num_resources = ARRAY_SIZE(dm644x_vpss_resources), + .resource = dm644x_vpss_resources, +}; + +static struct resource vpfe_resources[] = { + { + .start = IRQ_VDINT0, + .end = IRQ_VDINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_VDINT1, + .end = IRQ_VDINT1, + .flags = IORESOURCE_IRQ, + }, + { + .start = 0x01c70400, + .end = 0x01c70400 + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); +static struct platform_device vpfe_capture_dev = { + .name = CAPTURE_DRV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(vpfe_resources), + .resource = vpfe_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void dm644x_set_vpfe_config(struct vpfe_config *cfg) +{ + vpfe_capture_dev.dev.platform_data = cfg; +} + /*----------------------------------------------------------------------*/ static struct map_desc dm644x_io_desc[] = { @@ -557,6 +660,13 @@ static struct davinci_id dm644x_ids[] = { .cpu_id = DAVINCI_CPU_ID_DM6446, .name = "dm6446", }, + { + .variant = 0x1, + .part_no = 0xb700, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DM6446, + .name = "dm6446a", + }, }; static void __iomem *dm644x_psc_bases[] = { @@ -630,7 +740,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { .intc_irq_prios = dm644x_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm644x_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), .gpio_num = 71, .gpio_irq = IRQ_GPIOBNK0, @@ -640,6 +749,13 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { .sram_len = SZ_16K, }; +void __init dm644x_init_asp(struct snd_platform_data *pdata) +{ + davinci_cfg_reg(DM644X_MCBSP); + dm644x_asp_device.dev.platform_data = pdata; + platform_device_register(&dm644x_asp_device); +} + void __init dm644x_init(void) { davinci_common_init(&davinci_soc_info_dm644x); @@ -652,6 +768,9 @@ static int __init dm644x_init_devices(void) platform_device_register(&dm644x_edma_device); platform_device_register(&dm644x_emac_device); + platform_device_register(&dm644x_vpss_device); + platform_device_register(&vpfe_capture_dev); + return 0; } postcore_initcall(dm644x_init_devices); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 334f0711e0f5..0976049c7b3b 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -27,10 +27,20 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <mach/asp.h> #include "clock.h" #include "mux.h" +#define DAVINCI_VPIF_BASE (0x01C12000) +#define VDD3P3V_PWDN_OFFSET (0x48) +#define VSCLKDIS_OFFSET (0x6C) + +#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\ + BIT_MASK(0)) +#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\ + BIT_MASK(8)) + /* * Device specific clocks */ @@ -162,6 +172,41 @@ static struct clk arm_clk = { .flags = ALWAYS_ENABLED, }; +static struct clk edma_cc_clk = { + .name = "edma_cc", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPCC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc0_clk = { + .name = "edma_tc0", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc1_clk = { + .name = "edma_tc1", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc2_clk = { + .name = "edma_tc2", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC2, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc3_clk = { + .name = "edma_tc3", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC3, + .flags = ALWAYS_ENABLED, +}; + static struct clk uart0_clk = { .name = "uart0", .parent = &aux_clkin, @@ -192,6 +237,18 @@ static struct clk gpio_clk = { .lpsc = DM646X_LPSC_GPIO, }; +static struct clk mcasp0_clk = { + .name = "mcasp0", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_McASP0, +}; + +static struct clk mcasp1_clk = { + .name = "mcasp1", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_McASP1, +}; + static struct clk aemif_clk = { .name = "aemif", .parent = &pll1_sysclk3, @@ -237,6 +294,13 @@ static struct clk timer2_clk = { .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ }; + +static struct clk ide_clk = { + .name = "ide", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_ATA, +}; + static struct clk vpif0_clk = { .name = "vpif0", .parent = &ref_clk, @@ -269,11 +333,18 @@ struct davinci_clk dm646x_clks[] = { CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), CLK(NULL, "dsp", &dsp_clk), CLK(NULL, "arm", &arm_clk), + CLK(NULL, "edma_cc", &edma_cc_clk), + CLK(NULL, "edma_tc0", &edma_tc0_clk), + CLK(NULL, "edma_tc1", &edma_tc1_clk), + CLK(NULL, "edma_tc2", &edma_tc2_clk), + CLK(NULL, "edma_tc3", &edma_tc3_clk), CLK(NULL, "uart0", &uart0_clk), CLK(NULL, "uart1", &uart1_clk), CLK(NULL, "uart2", &uart2_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK(NULL, "gpio", &gpio_clk), + CLK("davinci-mcasp.0", NULL, &mcasp0_clk), + CLK("davinci-mcasp.1", NULL, &mcasp1_clk), CLK(NULL, "aemif", &aemif_clk), CLK("davinci_emac.1", NULL, &emac_clk), CLK(NULL, "pwm0", &pwm0_clk), @@ -281,6 +352,7 @@ struct davinci_clk dm646x_clks[] = { CLK(NULL, "timer0", &timer0_clk), CLK(NULL, "timer1", &timer1_clk), CLK("watchdog", NULL, &timer2_clk), + CLK("palm_bk3710", NULL, &ide_clk), CLK(NULL, "vpif0", &vpif0_clk), CLK(NULL, "vpif1", &vpif1_clk), CLK(NULL, NULL, NULL), @@ -344,7 +416,7 @@ static struct platform_device dm646x_emac_device = { */ static const struct mux_config dm646x_pins[] = { #ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true) +MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true) MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) @@ -451,17 +523,43 @@ static const s8 dma_chan_dm646x_no_event[] = { -1 }; -static struct edma_soc_info dm646x_edma_info = { - .n_channel = 64, - .n_region = 6, /* 0-1, 4-7 */ - .n_slot = 512, - .n_tc = 4, - .noevent = dma_chan_dm646x_no_event, +/* Four Transfer Controllers on DM646x */ +static const s8 +dm646x_queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {2, 2}, + {3, 3}, + {-1, -1}, +}; + +static const s8 +dm646x_queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 4}, + {1, 0}, + {2, 5}, + {3, 1}, + {-1, -1}, +}; + +static struct edma_soc_info dm646x_edma_info[] = { + { + .n_channel = 64, + .n_region = 6, /* 0-1, 4-7 */ + .n_slot = 512, + .n_tc = 4, + .n_cc = 1, + .noevent = dma_chan_dm646x_no_event, + .queue_tc_mapping = dm646x_queue_tc_mapping, + .queue_priority_mapping = dm646x_queue_priority_mapping, + }, }; static struct resource edma_resources[] = { { - .name = "edma_cc", + .name = "edma_cc0", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, @@ -491,10 +589,12 @@ static struct resource edma_resources[] = { .flags = IORESOURCE_MEM, }, { + .name = "edma0", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { + .name = "edma0_err", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -503,12 +603,167 @@ static struct resource edma_resources[] = { static struct platform_device dm646x_edma_device = { .name = "edma", - .id = -1, - .dev.platform_data = &dm646x_edma_info, + .id = 0, + .dev.platform_data = dm646x_edma_info, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; +static struct resource ide_resources[] = { + { + .start = DM646X_ATA_REG_BASE, + .end = DM646X_ATA_REG_BASE + 0x7ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DM646X_IDE, + .end = IRQ_DM646X_IDE, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ide_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device ide_dev = { + .name = "palm_bk3710", + .id = -1, + .resource = ide_resources, + .num_resources = ARRAY_SIZE(ide_resources), + .dev = { + .dma_mask = &ide_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dm646x_mcasp0_resources[] = { + { + .name = "mcasp0", + .start = DAVINCI_DM646X_MCASP0_REG_BASE, + .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, + .flags = IORESOURCE_MEM, + }, + /* first TX, then RX */ + { + .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, + .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, + .flags = IORESOURCE_DMA, + }, + { + .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0, + .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource dm646x_mcasp1_resources[] = { + { + .name = "mcasp1", + .start = DAVINCI_DM646X_MCASP1_REG_BASE, + .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, + .flags = IORESOURCE_MEM, + }, + /* DIT mode, only TX event */ + { + .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, + .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, + .flags = IORESOURCE_DMA, + }, + /* DIT mode, dummy entry */ + { + .start = -1, + .end = -1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device dm646x_mcasp0_device = { + .name = "davinci-mcasp", + .id = 0, + .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources), + .resource = dm646x_mcasp0_resources, +}; + +static struct platform_device dm646x_mcasp1_device = { + .name = "davinci-mcasp", + .id = 1, + .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources), + .resource = dm646x_mcasp1_resources, +}; + +static struct platform_device dm646x_dit_device = { + .name = "spdif-dit", + .id = -1, +}; + +static u64 vpif_dma_mask = DMA_BIT_MASK(32); + +static struct resource vpif_resource[] = { + { + .start = DAVINCI_VPIF_BASE, + .end = DAVINCI_VPIF_BASE + 0x03ff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device vpif_dev = { + .name = "vpif", + .id = -1, + .dev = { + .dma_mask = &vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = vpif_resource, + .num_resources = ARRAY_SIZE(vpif_resource), +}; + +static struct resource vpif_display_resource[] = { + { + .start = IRQ_DM646X_VP_VERTINT2, + .end = IRQ_DM646X_VP_VERTINT2, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM646X_VP_VERTINT3, + .end = IRQ_DM646X_VP_VERTINT3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vpif_display_dev = { + .name = "vpif_display", + .id = -1, + .dev = { + .dma_mask = &vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = vpif_display_resource, + .num_resources = ARRAY_SIZE(vpif_display_resource), +}; + +static struct resource vpif_capture_resource[] = { + { + .start = IRQ_DM646X_VP_VERTINT0, + .end = IRQ_DM646X_VP_VERTINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM646X_VP_VERTINT1, + .end = IRQ_DM646X_VP_VERTINT1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vpif_capture_dev = { + .name = "vpif_capture", + .id = -1, + .dev = { + .dma_mask = &vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = vpif_capture_resource, + .num_resources = ARRAY_SIZE(vpif_capture_resource), +}; + /*----------------------------------------------------------------------*/ static struct map_desc dm646x_io_desc[] = { @@ -609,7 +864,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { .intc_irq_prios = dm646x_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm646x_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), .gpio_num = 43, /* Only 33 usable */ .gpio_irq = IRQ_DM646X_GPIOBNK0, @@ -619,6 +873,51 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { .sram_len = SZ_32K, }; +void __init dm646x_init_ide() +{ + davinci_cfg_reg(DM646X_ATAEN); + platform_device_register(&ide_dev); +} + +void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) +{ + dm646x_mcasp0_device.dev.platform_data = pdata; + platform_device_register(&dm646x_mcasp0_device); +} + +void __init dm646x_init_mcasp1(struct snd_platform_data *pdata) +{ + dm646x_mcasp1_device.dev.platform_data = pdata; + platform_device_register(&dm646x_mcasp1_device); + platform_device_register(&dm646x_dit_device); +} + +void dm646x_setup_vpif(struct vpif_display_config *display_config, + struct vpif_capture_config *capture_config) +{ + unsigned int value; + void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); + + value = __raw_readl(base + VSCLKDIS_OFFSET); + value &= ~VSCLKDIS_MASK; + __raw_writel(value, base + VSCLKDIS_OFFSET); + + value = __raw_readl(base + VDD3P3V_PWDN_OFFSET); + value &= ~VDD3P3V_VID_MASK; + __raw_writel(value, base + VDD3P3V_PWDN_OFFSET); + + davinci_cfg_reg(DM646X_STSOMUX_DISABLE); + davinci_cfg_reg(DM646X_STSIMUX_DISABLE); + davinci_cfg_reg(DM646X_PTSOMUX_DISABLE); + davinci_cfg_reg(DM646X_PTSIMUX_DISABLE); + + vpif_display_dev.dev.platform_data = display_config; + vpif_capture_dev.dev.platform_data = capture_config; + platform_device_register(&vpif_dev); + platform_device_register(&vpif_display_dev); + platform_device_register(&vpif_capture_dev); +} + void __init dm646x_init(void) { davinci_common_init(&davinci_soc_info_dm646x); diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 15e9eb158bb7..f2e57d272958 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -100,132 +100,158 @@ #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ #define EDMA_PARM 0x4000 /* 128 param entries */ -#define DAVINCI_DMA_3PCC_BASE 0x01C00000 - #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) +#define EDMA_DCHMAP 0x0100 /* 64 registers */ +#define CHMAP_EXIST BIT(24) + #define EDMA_MAX_DMACH 64 #define EDMA_MAX_PARAMENTRY 512 -#define EDMA_MAX_EVQUE 2 /* FIXME too small */ +#define EDMA_MAX_CC 2 /*****************************************************************************/ -static void __iomem *edmacc_regs_base; +static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; -static inline unsigned int edma_read(int offset) +static inline unsigned int edma_read(unsigned ctlr, int offset) { - return (unsigned int)__raw_readl(edmacc_regs_base + offset); + return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); } -static inline void edma_write(int offset, int val) +static inline void edma_write(unsigned ctlr, int offset, int val) { - __raw_writel(val, edmacc_regs_base + offset); + __raw_writel(val, edmacc_regs_base[ctlr] + offset); } -static inline void edma_modify(int offset, unsigned and, unsigned or) +static inline void edma_modify(unsigned ctlr, int offset, unsigned and, + unsigned or) { - unsigned val = edma_read(offset); + unsigned val = edma_read(ctlr, offset); val &= and; val |= or; - edma_write(offset, val); + edma_write(ctlr, offset, val); } -static inline void edma_and(int offset, unsigned and) +static inline void edma_and(unsigned ctlr, int offset, unsigned and) { - unsigned val = edma_read(offset); + unsigned val = edma_read(ctlr, offset); val &= and; - edma_write(offset, val); + edma_write(ctlr, offset, val); } -static inline void edma_or(int offset, unsigned or) +static inline void edma_or(unsigned ctlr, int offset, unsigned or) { - unsigned val = edma_read(offset); + unsigned val = edma_read(ctlr, offset); val |= or; - edma_write(offset, val); + edma_write(ctlr, offset, val); } -static inline unsigned int edma_read_array(int offset, int i) +static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) { - return edma_read(offset + (i << 2)); + return edma_read(ctlr, offset + (i << 2)); } -static inline void edma_write_array(int offset, int i, unsigned val) +static inline void edma_write_array(unsigned ctlr, int offset, int i, + unsigned val) { - edma_write(offset + (i << 2), val); + edma_write(ctlr, offset + (i << 2), val); } -static inline void edma_modify_array(int offset, int i, +static inline void edma_modify_array(unsigned ctlr, int offset, int i, unsigned and, unsigned or) { - edma_modify(offset + (i << 2), and, or); + edma_modify(ctlr, offset + (i << 2), and, or); } -static inline void edma_or_array(int offset, int i, unsigned or) +static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) { - edma_or(offset + (i << 2), or); + edma_or(ctlr, offset + (i << 2), or); } -static inline void edma_or_array2(int offset, int i, int j, unsigned or) +static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, + unsigned or) { - edma_or(offset + ((i*2 + j) << 2), or); + edma_or(ctlr, offset + ((i*2 + j) << 2), or); } -static inline void edma_write_array2(int offset, int i, int j, unsigned val) +static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, + unsigned val) { - edma_write(offset + ((i*2 + j) << 2), val); + edma_write(ctlr, offset + ((i*2 + j) << 2), val); } -static inline unsigned int edma_shadow0_read(int offset) +static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) { - return edma_read(EDMA_SHADOW0 + offset); + return edma_read(ctlr, EDMA_SHADOW0 + offset); } -static inline unsigned int edma_shadow0_read_array(int offset, int i) +static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, + int i) { - return edma_read(EDMA_SHADOW0 + offset + (i << 2)); + return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); } -static inline void edma_shadow0_write(int offset, unsigned val) +static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) { - edma_write(EDMA_SHADOW0 + offset, val); + edma_write(ctlr, EDMA_SHADOW0 + offset, val); } -static inline void edma_shadow0_write_array(int offset, int i, unsigned val) +static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, + unsigned val) { - edma_write(EDMA_SHADOW0 + offset + (i << 2), val); + edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); } -static inline unsigned int edma_parm_read(int offset, int param_no) +static inline unsigned int edma_parm_read(unsigned ctlr, int offset, + int param_no) { - return edma_read(EDMA_PARM + offset + (param_no << 5)); + return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); } -static inline void edma_parm_write(int offset, int param_no, unsigned val) +static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, + unsigned val) { - edma_write(EDMA_PARM + offset + (param_no << 5), val); + edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); } -static inline void edma_parm_modify(int offset, int param_no, +static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, unsigned and, unsigned or) { - edma_modify(EDMA_PARM + offset + (param_no << 5), and, or); + edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); } -static inline void edma_parm_and(int offset, int param_no, unsigned and) +static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, + unsigned and) { - edma_and(EDMA_PARM + offset + (param_no << 5), and); + edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); } -static inline void edma_parm_or(int offset, int param_no, unsigned or) +static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, + unsigned or) { - edma_or(EDMA_PARM + offset + (param_no << 5), or); + edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); } /*****************************************************************************/ /* actual number of DMA channels and slots on this silicon */ -static unsigned num_channels; -static unsigned num_slots; +struct edma { + /* how many dma resources of each type */ + unsigned num_channels; + unsigned num_region; + unsigned num_slots; + unsigned num_tc; + unsigned num_cc; + enum dma_event_q default_queue; + + /* list of channels with no even trigger; terminated by "-1" */ + const s8 *noevent; + + /* The edma_inuse bit for each PaRAM slot is clear unless the + * channel is in use ... by ARM or DSP, for QDMA, or whatever. + */ + DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); -static struct dma_interrupt_data { - void (*callback)(unsigned channel, unsigned short ch_status, - void *data); - void *data; -} intr_data[EDMA_MAX_DMACH]; + /* The edma_noevent bit for each channel is clear unless + * it doesn't trigger DMA events on this platform. It uses a + * bit of SOC-specific initialization code. + */ + DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); -/* The edma_inuse bit for each PaRAM slot is clear unless the - * channel is in use ... by ARM or DSP, for QDMA, or whatever. - */ -static DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + unsigned irq_res_start; + unsigned irq_res_end; -/* The edma_noevent bit for each channel is clear unless - * it doesn't trigger DMA events on this platform. It uses a - * bit of SOC-specific initialization code. - */ -static DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); + struct dma_interrupt_data { + void (*callback)(unsigned channel, unsigned short ch_status, + void *data); + void *data; + } intr_data[EDMA_MAX_DMACH]; +}; + +static struct edma *edma_info[EDMA_MAX_CC]; /* dummy param set used to (re)initialize parameter RAM slots */ static const struct edmacc_param dummy_paramset = { @@ -233,47 +259,52 @@ static const struct edmacc_param dummy_paramset = { .ccnt = 1, }; -static const int __initconst -queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = { -/* {event queue no, TC no} */ - {0, 0}, - {1, 1}, - {-1, -1} -}; - -static const int __initconst -queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = { - /* {event queue no, Priority} */ - {0, 3}, - {1, 7}, - {-1, -1} -}; - /*****************************************************************************/ -static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no) +static void map_dmach_queue(unsigned ctlr, unsigned ch_no, + enum dma_event_q queue_no) { int bit = (ch_no & 0x7) * 4; /* default to low priority queue */ if (queue_no == EVENTQ_DEFAULT) - queue_no = EVENTQ_1; + queue_no = edma_info[ctlr]->default_queue; queue_no &= 7; - edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3), + edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), ~(0x7 << bit), queue_no << bit); } -static void __init map_queue_tc(int queue_no, int tc_no) +static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no) { int bit = queue_no * 4; - edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); + edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); } -static void __init assign_priority_to_queue(int queue_no, int priority) +static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, + int priority) { int bit = queue_no * 4; - edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); + edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), + ((priority & 0x7) << bit)); +} + +/** + * map_dmach_param - Maps channel number to param entry number + * + * This maps the dma channel number to param entry numberter. In + * other words using the DMA channel mapping registers a param entry + * can be mapped to any channel + * + * Callers are responsible for ensuring the channel mapping logic is + * included in that particular EDMA variant (Eg : dm646x) + * + */ +static void __init map_dmach_param(unsigned ctlr) +{ + int i; + for (i = 0; i < EDMA_MAX_DMACH; i++) + edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); } static inline void @@ -281,22 +312,39 @@ setup_dma_interrupt(unsigned lch, void (*callback)(unsigned channel, u16 ch_status, void *data), void *data) { + unsigned ctlr; + + ctlr = EDMA_CTLR(lch); + lch = EDMA_CHAN_SLOT(lch); + if (!callback) { - edma_shadow0_write_array(SH_IECR, lch >> 5, + edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, (1 << (lch & 0x1f))); } - intr_data[lch].callback = callback; - intr_data[lch].data = data; + edma_info[ctlr]->intr_data[lch].callback = callback; + edma_info[ctlr]->intr_data[lch].data = data; if (callback) { - edma_shadow0_write_array(SH_ICR, lch >> 5, + edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, (1 << (lch & 0x1f))); - edma_shadow0_write_array(SH_IESR, lch >> 5, + edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, (1 << (lch & 0x1f))); } } +static int irq2ctlr(int irq) +{ + if (irq >= edma_info[0]->irq_res_start && + irq <= edma_info[0]->irq_res_end) + return 0; + else if (irq >= edma_info[1]->irq_res_start && + irq <= edma_info[1]->irq_res_end) + return 1; + + return -1; +} + /****************************************************************************** * * DMA interrupt handler @@ -305,32 +353,39 @@ setup_dma_interrupt(unsigned lch, static irqreturn_t dma_irq_handler(int irq, void *data) { int i; + unsigned ctlr; unsigned int cnt = 0; + ctlr = irq2ctlr(irq); + dev_dbg(data, "dma_irq_handler\n"); - if ((edma_shadow0_read_array(SH_IPR, 0) == 0) - && (edma_shadow0_read_array(SH_IPR, 1) == 0)) + if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) + && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) return IRQ_NONE; while (1) { int j; - if (edma_shadow0_read_array(SH_IPR, 0)) + if (edma_shadow0_read_array(ctlr, SH_IPR, 0)) j = 0; - else if (edma_shadow0_read_array(SH_IPR, 1)) + else if (edma_shadow0_read_array(ctlr, SH_IPR, 1)) j = 1; else break; dev_dbg(data, "IPR%d %08x\n", j, - edma_shadow0_read_array(SH_IPR, j)); + edma_shadow0_read_array(ctlr, SH_IPR, j)); for (i = 0; i < 32; i++) { int k = (j << 5) + i; - if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) { + if (edma_shadow0_read_array(ctlr, SH_IPR, j) & + (1 << i)) { /* Clear the corresponding IPR bits */ - edma_shadow0_write_array(SH_ICR, j, (1 << i)); - if (intr_data[k].callback) { - intr_data[k].callback(k, DMA_COMPLETE, - intr_data[k].data); + edma_shadow0_write_array(ctlr, SH_ICR, j, + (1 << i)); + if (edma_info[ctlr]->intr_data[k].callback) { + edma_info[ctlr]->intr_data[k].callback( + k, DMA_COMPLETE, + edma_info[ctlr]->intr_data[k]. + data); } } } @@ -338,7 +393,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) if (cnt > 10) break; } - edma_shadow0_write(SH_IEVAL, 1); + edma_shadow0_write(ctlr, SH_IEVAL, 1); return IRQ_HANDLED; } @@ -350,78 +405,87 @@ static irqreturn_t dma_irq_handler(int irq, void *data) static irqreturn_t dma_ccerr_handler(int irq, void *data) { int i; + unsigned ctlr; unsigned int cnt = 0; + ctlr = irq2ctlr(irq); + dev_dbg(data, "dma_ccerr_handler\n"); - if ((edma_read_array(EDMA_EMR, 0) == 0) && - (edma_read_array(EDMA_EMR, 1) == 0) && - (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0)) + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && + (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && + (edma_read(ctlr, EDMA_QEMR) == 0) && + (edma_read(ctlr, EDMA_CCERR) == 0)) return IRQ_NONE; while (1) { int j = -1; - if (edma_read_array(EDMA_EMR, 0)) + if (edma_read_array(ctlr, EDMA_EMR, 0)) j = 0; - else if (edma_read_array(EDMA_EMR, 1)) + else if (edma_read_array(ctlr, EDMA_EMR, 1)) j = 1; if (j >= 0) { dev_dbg(data, "EMR%d %08x\n", j, - edma_read_array(EDMA_EMR, j)); + edma_read_array(ctlr, EDMA_EMR, j)); for (i = 0; i < 32; i++) { int k = (j << 5) + i; - if (edma_read_array(EDMA_EMR, j) & (1 << i)) { + if (edma_read_array(ctlr, EDMA_EMR, j) & + (1 << i)) { /* Clear the corresponding EMR bits */ - edma_write_array(EDMA_EMCR, j, 1 << i); + edma_write_array(ctlr, EDMA_EMCR, j, + 1 << i); /* Clear any SER */ - edma_shadow0_write_array(SH_SECR, j, - (1 << i)); - if (intr_data[k].callback) { - intr_data[k].callback(k, - DMA_CC_ERROR, - intr_data - [k].data); + edma_shadow0_write_array(ctlr, SH_SECR, + j, (1 << i)); + if (edma_info[ctlr]->intr_data[k]. + callback) { + edma_info[ctlr]->intr_data[k]. + callback(k, + DMA_CC_ERROR, + edma_info[ctlr]->intr_data + [k].data); } } } - } else if (edma_read(EDMA_QEMR)) { + } else if (edma_read(ctlr, EDMA_QEMR)) { dev_dbg(data, "QEMR %02x\n", - edma_read(EDMA_QEMR)); + edma_read(ctlr, EDMA_QEMR)); for (i = 0; i < 8; i++) { - if (edma_read(EDMA_QEMR) & (1 << i)) { + if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) { /* Clear the corresponding IPR bits */ - edma_write(EDMA_QEMCR, 1 << i); - edma_shadow0_write(SH_QSECR, (1 << i)); + edma_write(ctlr, EDMA_QEMCR, 1 << i); + edma_shadow0_write(ctlr, SH_QSECR, + (1 << i)); /* NOTE: not reported!! */ } } - } else if (edma_read(EDMA_CCERR)) { + } else if (edma_read(ctlr, EDMA_CCERR)) { dev_dbg(data, "CCERR %08x\n", - edma_read(EDMA_CCERR)); + edma_read(ctlr, EDMA_CCERR)); /* FIXME: CCERR.BIT(16) ignored! much better * to just write CCERRCLR with CCERR value... */ for (i = 0; i < 8; i++) { - if (edma_read(EDMA_CCERR) & (1 << i)) { + if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) { /* Clear the corresponding IPR bits */ - edma_write(EDMA_CCERRCLR, 1 << i); + edma_write(ctlr, EDMA_CCERRCLR, 1 << i); /* NOTE: not reported!! */ } } } - if ((edma_read_array(EDMA_EMR, 0) == 0) - && (edma_read_array(EDMA_EMR, 1) == 0) - && (edma_read(EDMA_QEMR) == 0) - && (edma_read(EDMA_CCERR) == 0)) { + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) + && (edma_read_array(ctlr, EDMA_EMR, 1) == 0) + && (edma_read(ctlr, EDMA_QEMR) == 0) + && (edma_read(ctlr, EDMA_CCERR) == 0)) { break; } cnt++; if (cnt > 10) break; } - edma_write(EDMA_EEVAL, 1); + edma_write(ctlr, EDMA_EEVAL, 1); return IRQ_HANDLED; } @@ -445,6 +509,45 @@ static irqreturn_t dma_tc1err_handler(int irq, void *data) return IRQ_HANDLED; } +static int reserve_contiguous_params(int ctlr, unsigned int id, + unsigned int num_params, + unsigned int start_param) +{ + int i, j; + unsigned int count = num_params; + + for (i = start_param; i < edma_info[ctlr]->num_slots; ++i) { + j = EDMA_CHAN_SLOT(i); + if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) + count--; + if (count == 0) + break; + else if (id == EDMA_CONT_PARAMS_FIXED_EXACT) + break; + else + count = num_params; + } + + /* + * We have to clear any bits that we set + * if we run out parameter RAMs, i.e we do find a set + * of contiguous parameter RAMs but do not find the exact number + * requested as we may reach the total number of parameter RAMs + */ + if (count) { + for (j = i - num_params + count + 1; j <= i ; ++j) + clear_bit(j, edma_info[ctlr]->edma_inuse); + + return -EBUSY; + } + + for (j = i - num_params + 1; j <= i; ++j) + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), + &dummy_paramset, PARM_SIZE); + + return EDMA_CTLR_CHAN(ctlr, i - num_params + 1); +} + /*-----------------------------------------------------------------------*/ /* Resource alloc/free: dma channels, parameter RAM slots */ @@ -484,35 +587,53 @@ int edma_alloc_channel(int channel, void *data, enum dma_event_q eventq_no) { + unsigned i, done, ctlr = 0; + + if (channel >= 0) { + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + } + if (channel < 0) { - channel = 0; - for (;;) { - channel = find_next_bit(edma_noevent, - num_channels, channel); - if (channel == num_channels) - return -ENOMEM; - if (!test_and_set_bit(channel, edma_inuse)) + for (i = 0; i < EDMA_MAX_CC; i++) { + channel = 0; + for (;;) { + channel = find_next_bit(edma_info[i]-> + edma_noevent, + edma_info[i]->num_channels, + channel); + if (channel == edma_info[i]->num_channels) + return -ENOMEM; + if (!test_and_set_bit(channel, + edma_info[i]->edma_inuse)) { + done = 1; + ctlr = i; + break; + } + channel++; + } + if (done) break; - channel++; } - } else if (channel >= num_channels) { + } else if (channel >= edma_info[ctlr]->num_channels) { return -EINVAL; - } else if (test_and_set_bit(channel, edma_inuse)) { + } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { return -EBUSY; } /* ensure access through shadow region 0 */ - edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); + edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); /* ensure no events are pending */ - edma_stop(channel); - memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), + edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), &dummy_paramset, PARM_SIZE); if (callback) - setup_dma_interrupt(channel, callback, data); + setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), + callback, data); - map_dmach_queue(channel, eventq_no); + map_dmach_queue(ctlr, channel, eventq_no); return channel; } @@ -532,15 +653,20 @@ EXPORT_SYMBOL(edma_alloc_channel); */ void edma_free_channel(unsigned channel) { - if (channel >= num_channels) + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel >= edma_info[ctlr]->num_channels) return; setup_dma_interrupt(channel, NULL, NULL); /* REVISIT should probably take out of shadow region 0 */ - memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), &dummy_paramset, PARM_SIZE); - clear_bit(channel, edma_inuse); + clear_bit(channel, edma_info[ctlr]->edma_inuse); } EXPORT_SYMBOL(edma_free_channel); @@ -558,28 +684,33 @@ EXPORT_SYMBOL(edma_free_channel); * * Returns the number of the slot, else negative errno. */ -int edma_alloc_slot(int slot) +int edma_alloc_slot(unsigned ctlr, int slot) { + if (slot >= 0) + slot = EDMA_CHAN_SLOT(slot); + if (slot < 0) { - slot = num_channels; + slot = edma_info[ctlr]->num_channels; for (;;) { - slot = find_next_zero_bit(edma_inuse, - num_slots, slot); - if (slot == num_slots) + slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse, + edma_info[ctlr]->num_slots, slot); + if (slot == edma_info[ctlr]->num_slots) return -ENOMEM; - if (!test_and_set_bit(slot, edma_inuse)) + if (!test_and_set_bit(slot, + edma_info[ctlr]->edma_inuse)) break; } - } else if (slot < num_channels || slot >= num_slots) { + } else if (slot < edma_info[ctlr]->num_channels || + slot >= edma_info[ctlr]->num_slots) { return -EINVAL; - } else if (test_and_set_bit(slot, edma_inuse)) { + } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) { return -EBUSY; } - memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE); - return slot; + return EDMA_CTLR_CHAN(ctlr, slot); } EXPORT_SYMBOL(edma_alloc_slot); @@ -593,15 +724,119 @@ EXPORT_SYMBOL(edma_alloc_slot); */ void edma_free_slot(unsigned slot) { - if (slot < num_channels || slot >= num_slots) + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_channels || + slot >= edma_info[ctlr]->num_slots) return; - memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE); - clear_bit(slot, edma_inuse); + clear_bit(slot, edma_info[ctlr]->edma_inuse); } EXPORT_SYMBOL(edma_free_slot); + +/** + * edma_alloc_cont_slots- alloc contiguous parameter RAM slots + * The API will return the starting point of a set of + * contiguous PARAM's that have been requested + * + * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT + * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT + * @count: number of contiguous Paramter RAM's + * @param - the start value of Parameter RAM that should be passed if id + * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT + * + * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of + * contiguous Parameter RAMs from parameter RAM 64 in the case of DaVinci SOCs + * and 32 in the case of Primus + * + * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a + * set of contiguous parameter RAMs from the "param" that is passed as an + * argument to the API. + * + * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries + * starts looking for a set of contiguous parameter RAMs from the "param" + * that is passed as an argument to the API. On failure the API will try to + * find a set of contiguous Parameter RAMs in the remaining Parameter RAMs + */ +int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) +{ + /* + * The start slot requested should be greater than + * the number of channels and lesser than the total number + * of slots + */ + if (slot < edma_info[ctlr]->num_channels || + slot >= edma_info[ctlr]->num_slots) + return -EINVAL; + + /* + * The number of parameter RAMs requested cannot be less than 1 + * and cannot be more than the number of slots minus the number of + * channels + */ + if (count < 1 || count > + (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels)) + return -EINVAL; + + switch (id) { + case EDMA_CONT_PARAMS_ANY: + return reserve_contiguous_params(ctlr, id, count, + edma_info[ctlr]->num_channels); + case EDMA_CONT_PARAMS_FIXED_EXACT: + case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: + return reserve_contiguous_params(ctlr, id, count, slot); + default: + return -EINVAL; + } + +} +EXPORT_SYMBOL(edma_alloc_cont_slots); + +/** + * edma_free_cont_slots - deallocate DMA parameter RAMs + * @slot: first parameter RAM of a set of parameter RAMs to be freed + * @count: the number of contiguous parameter RAMs to be freed + * + * This deallocates the parameter RAM slots allocated by + * edma_alloc_cont_slots. + * Callers/applications need to keep track of sets of contiguous + * parameter RAMs that have been allocated using the edma_alloc_cont_slots + * API. + * Callers are responsible for ensuring the slots are inactive, and will + * not be activated. + */ +int edma_free_cont_slots(unsigned slot, int count) +{ + unsigned ctlr; + int i; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_channels || + slot >= edma_info[ctlr]->num_slots || + count < 1) + return -EINVAL; + + for (i = slot; i < slot + count; ++i) { + ctlr = EDMA_CTLR(i); + slot = EDMA_CHAN_SLOT(i); + + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), + &dummy_paramset, PARM_SIZE); + clear_bit(slot, edma_info[ctlr]->edma_inuse); + } + + return 0; +} +EXPORT_SYMBOL(edma_free_cont_slots); + /*-----------------------------------------------------------------------*/ /* Parameter RAM operations (i) -- read/write partial slots */ @@ -620,8 +855,13 @@ EXPORT_SYMBOL(edma_free_slot); void edma_set_src(unsigned slot, dma_addr_t src_port, enum address_mode mode, enum fifo_width width) { - if (slot < num_slots) { - unsigned int i = edma_parm_read(PARM_OPT, slot); + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); if (mode) { /* set SAM and program FWID */ @@ -630,11 +870,11 @@ void edma_set_src(unsigned slot, dma_addr_t src_port, /* clear SAM */ i &= ~SAM; } - edma_parm_write(PARM_OPT, slot, i); + edma_parm_write(ctlr, PARM_OPT, slot, i); /* set the source port address in source register of param structure */ - edma_parm_write(PARM_SRC, slot, src_port); + edma_parm_write(ctlr, PARM_SRC, slot, src_port); } } EXPORT_SYMBOL(edma_set_src); @@ -653,8 +893,13 @@ EXPORT_SYMBOL(edma_set_src); void edma_set_dest(unsigned slot, dma_addr_t dest_port, enum address_mode mode, enum fifo_width width) { - if (slot < num_slots) { - unsigned int i = edma_parm_read(PARM_OPT, slot); + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); if (mode) { /* set DAM and program FWID */ @@ -663,10 +908,10 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port, /* clear DAM */ i &= ~DAM; } - edma_parm_write(PARM_OPT, slot, i); + edma_parm_write(ctlr, PARM_OPT, slot, i); /* set the destination port address in dest register of param structure */ - edma_parm_write(PARM_DST, slot, dest_port); + edma_parm_write(ctlr, PARM_DST, slot, dest_port); } } EXPORT_SYMBOL(edma_set_dest); @@ -683,8 +928,12 @@ EXPORT_SYMBOL(edma_set_dest); void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) { struct edmacc_param temp; + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - edma_read_slot(slot, &temp); + edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); if (src != NULL) *src = temp.src; if (dst != NULL) @@ -704,10 +953,15 @@ EXPORT_SYMBOL(edma_get_position); */ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) { - if (slot < num_slots) { - edma_parm_modify(PARM_SRC_DST_BIDX, slot, + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 0xffff0000, src_bidx); - edma_parm_modify(PARM_SRC_DST_CIDX, slot, + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, 0xffff0000, src_cidx); } } @@ -725,10 +979,15 @@ EXPORT_SYMBOL(edma_set_src_index); */ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) { - if (slot < num_slots) { - edma_parm_modify(PARM_SRC_DST_BIDX, slot, + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 0x0000ffff, dest_bidx << 16); - edma_parm_modify(PARM_SRC_DST_CIDX, slot, + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, 0x0000ffff, dest_cidx << 16); } } @@ -767,16 +1026,21 @@ void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, u16 bcnt_rld, enum sync_dimension sync_mode) { - if (slot < num_slots) { - edma_parm_modify(PARM_LINK_BCNTRLD, slot, + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, 0x0000ffff, bcnt_rld << 16); if (sync_mode == ASYNC) - edma_parm_and(PARM_OPT, slot, ~SYNCDIM); + edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); else - edma_parm_or(PARM_OPT, slot, SYNCDIM); + edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); /* Set the acount, bcount, ccount registers */ - edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt); - edma_parm_write(PARM_CCNT, slot, ccnt); + edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); + edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); } } EXPORT_SYMBOL(edma_set_transfer_params); @@ -790,11 +1054,19 @@ EXPORT_SYMBOL(edma_set_transfer_params); */ void edma_link(unsigned from, unsigned to) { - if (from >= num_slots) + unsigned ctlr_from, ctlr_to; + + ctlr_from = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); + ctlr_to = EDMA_CTLR(to); + to = EDMA_CHAN_SLOT(to); + + if (from >= edma_info[ctlr_from]->num_slots) return; - if (to >= num_slots) + if (to >= edma_info[ctlr_to]->num_slots) return; - edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to)); + edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); } EXPORT_SYMBOL(edma_link); @@ -807,9 +1079,14 @@ EXPORT_SYMBOL(edma_link); */ void edma_unlink(unsigned from) { - if (from >= num_slots) + unsigned ctlr; + + ctlr = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); + + if (from >= edma_info[ctlr]->num_slots) return; - edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff); + edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); } EXPORT_SYMBOL(edma_unlink); @@ -829,9 +1106,15 @@ EXPORT_SYMBOL(edma_unlink); */ void edma_write_slot(unsigned slot, const struct edmacc_param *param) { - if (slot >= num_slots) + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot >= edma_info[ctlr]->num_slots) return; - memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE); + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, + PARM_SIZE); } EXPORT_SYMBOL(edma_write_slot); @@ -845,9 +1128,15 @@ EXPORT_SYMBOL(edma_write_slot); */ void edma_read_slot(unsigned slot, struct edmacc_param *param) { - if (slot >= num_slots) + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot >= edma_info[ctlr]->num_slots) return; - memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE); + memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), + PARM_SIZE); } EXPORT_SYMBOL(edma_read_slot); @@ -864,10 +1153,15 @@ EXPORT_SYMBOL(edma_read_slot); */ void edma_pause(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { unsigned int mask = (1 << (channel & 0x1f)); - edma_shadow0_write_array(SH_EECR, channel >> 5, mask); + edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); } } EXPORT_SYMBOL(edma_pause); @@ -880,10 +1174,15 @@ EXPORT_SYMBOL(edma_pause); */ void edma_resume(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { unsigned int mask = (1 << (channel & 0x1f)); - edma_shadow0_write_array(SH_EESR, channel >> 5, mask); + edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); } } EXPORT_SYMBOL(edma_resume); @@ -901,28 +1200,33 @@ EXPORT_SYMBOL(edma_resume); */ int edma_start(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { int j = channel >> 5; unsigned int mask = (1 << (channel & 0x1f)); /* EDMA channels without event association */ - if (test_bit(channel, edma_noevent)) { + if (test_bit(channel, edma_info[ctlr]->edma_noevent)) { pr_debug("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(SH_ESR, j)); - edma_shadow0_write_array(SH_ESR, j, mask); + edma_shadow0_read_array(ctlr, SH_ESR, j)); + edma_shadow0_write_array(ctlr, SH_ESR, j, mask); return 0; } /* EDMA channel with event association */ pr_debug("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(SH_ER, j)); + edma_shadow0_read_array(ctlr, SH_ER, j)); /* Clear any pending error */ - edma_write_array(EDMA_EMCR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); /* Clear any SER */ - edma_shadow0_write_array(SH_SECR, j, mask); - edma_shadow0_write_array(SH_EESR, j, mask); + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_shadow0_write_array(ctlr, SH_EESR, j, mask); pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(SH_EER, j)); + edma_shadow0_read_array(ctlr, SH_EER, j)); return 0; } @@ -941,17 +1245,22 @@ EXPORT_SYMBOL(edma_start); */ void edma_stop(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { int j = channel >> 5; unsigned int mask = (1 << (channel & 0x1f)); - edma_shadow0_write_array(SH_EECR, j, mask); - edma_shadow0_write_array(SH_ECR, j, mask); - edma_shadow0_write_array(SH_SECR, j, mask); - edma_write_array(EDMA_EMCR, j, mask); + edma_shadow0_write_array(ctlr, SH_EECR, j, mask); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(SH_EER, j)); + edma_shadow0_read_array(ctlr, SH_EER, j)); /* REVISIT: consider guarding against inappropriate event * chaining by overwriting with dummy_paramset. @@ -975,18 +1284,23 @@ EXPORT_SYMBOL(edma_stop); void edma_clean_channel(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { int j = (channel >> 5); unsigned int mask = 1 << (channel & 0x1f); pr_debug("EDMA: EMR%d %08x\n", j, - edma_read_array(EDMA_EMR, j)); - edma_shadow0_write_array(SH_ECR, j, mask); + edma_read_array(ctlr, EDMA_EMR, j)); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); /* Clear the corresponding EMR bits */ - edma_write_array(EDMA_EMCR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); /* Clear any SER */ - edma_shadow0_write_array(SH_SECR, j, mask); - edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3); + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3); } } EXPORT_SYMBOL(edma_clean_channel); @@ -998,12 +1312,17 @@ EXPORT_SYMBOL(edma_clean_channel); */ void edma_clear_event(unsigned channel) { - if (channel >= num_channels) + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel >= edma_info[ctlr]->num_channels) return; if (channel < 32) - edma_write(EDMA_ECR, 1 << channel); + edma_write(ctlr, EDMA_ECR, 1 << channel); else - edma_write(EDMA_ECRH, 1 << (channel - 32)); + edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32)); } EXPORT_SYMBOL(edma_clear_event); @@ -1012,62 +1331,133 @@ EXPORT_SYMBOL(edma_clear_event); static int __init edma_probe(struct platform_device *pdev) { struct edma_soc_info *info = pdev->dev.platform_data; - int i; - int status; + const s8 (*queue_priority_mapping)[2]; + const s8 (*queue_tc_mapping)[2]; + int i, j, found = 0; + int status = -1; const s8 *noevent; - int irq = 0, err_irq = 0; - struct resource *r; - resource_size_t len; + int irq[EDMA_MAX_CC] = {0, 0}; + int err_irq[EDMA_MAX_CC] = {0, 0}; + struct resource *r[EDMA_MAX_CC] = {NULL}; + resource_size_t len[EDMA_MAX_CC]; + char res_name[10]; + char irq_name[10]; if (!info) return -ENODEV; - r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma_cc"); - if (!r) - return -ENODEV; + for (j = 0; j < EDMA_MAX_CC; j++) { + sprintf(res_name, "edma_cc%d", j); + r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, + res_name); + if (!r[j]) { + if (found) + break; + else + return -ENODEV; + } else + found = 1; + + len[j] = resource_size(r[j]); + + r[j] = request_mem_region(r[j]->start, len[j], + dev_name(&pdev->dev)); + if (!r[j]) { + status = -EBUSY; + goto fail1; + } - len = r->end - r->start + 1; + edmacc_regs_base[j] = ioremap(r[j]->start, len[j]); + if (!edmacc_regs_base[j]) { + status = -EBUSY; + goto fail1; + } - r = request_mem_region(r->start, len, r->name); - if (!r) - return -EBUSY; + edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); + if (!edma_info[j]) { + status = -ENOMEM; + goto fail1; + } + memset(edma_info[j], 0, sizeof(struct edma)); + + edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel, + EDMA_MAX_DMACH); + edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot, + EDMA_MAX_PARAMENTRY); + edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc, + EDMA_MAX_CC); + + edma_info[j]->default_queue = info[j].default_queue; + if (!edma_info[j]->default_queue) + edma_info[j]->default_queue = EVENTQ_1; + + dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", + edmacc_regs_base[j]); + + for (i = 0; i < edma_info[j]->num_slots; i++) + memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), + &dummy_paramset, PARM_SIZE); + + noevent = info[j].noevent; + if (noevent) { + while (*noevent != -1) + set_bit(*noevent++, edma_info[j]->edma_noevent); + } - edmacc_regs_base = ioremap(r->start, len); - if (!edmacc_regs_base) { - status = -EBUSY; - goto fail1; - } + sprintf(irq_name, "edma%d", j); + irq[j] = platform_get_irq_byname(pdev, irq_name); + edma_info[j]->irq_res_start = irq[j]; + status = request_irq(irq[j], dma_irq_handler, 0, "edma", + &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + irq[j], status); + goto fail; + } - num_channels = min_t(unsigned, info->n_channel, EDMA_MAX_DMACH); - num_slots = min_t(unsigned, info->n_slot, EDMA_MAX_PARAMENTRY); + sprintf(irq_name, "edma%d_err", j); + err_irq[j] = platform_get_irq_byname(pdev, irq_name); + edma_info[j]->irq_res_end = err_irq[j]; + status = request_irq(err_irq[j], dma_ccerr_handler, 0, + "edma_error", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + err_irq[j], status); + goto fail; + } - dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base); + /* Everything lives on transfer controller 1 until otherwise + * specified. This way, long transfers on the low priority queue + * started by the codec engine will not cause audio defects. + */ + for (i = 0; i < edma_info[j]->num_channels; i++) + map_dmach_queue(j, i, EVENTQ_1); - for (i = 0; i < num_slots; i++) - memcpy_toio(edmacc_regs_base + PARM_OFFSET(i), - &dummy_paramset, PARM_SIZE); + queue_tc_mapping = info[j].queue_tc_mapping; + queue_priority_mapping = info[j].queue_priority_mapping; - noevent = info->noevent; - if (noevent) { - while (*noevent != -1) - set_bit(*noevent++, edma_noevent); - } + /* Event queue to TC mapping */ + for (i = 0; queue_tc_mapping[i][0] != -1; i++) + map_queue_tc(j, queue_tc_mapping[i][0], + queue_tc_mapping[i][1]); - irq = platform_get_irq(pdev, 0); - status = request_irq(irq, dma_irq_handler, 0, "edma", &pdev->dev); - if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", - irq, status); - goto fail; - } + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(j, + queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + /* Map the channel to param entry if channel mapping logic + * exist + */ + if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(j); - err_irq = platform_get_irq(pdev, 1); - status = request_irq(err_irq, dma_ccerr_handler, 0, - "edma_error", &pdev->dev); - if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", - err_irq, status); - goto fail; + for (i = 0; i < info[j].n_region; i++) { + edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); + edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); + edma_write_array(j, EDMA_QRAE, i, 0x0); + } } if (tc_errs_handled) { @@ -1087,38 +1477,23 @@ static int __init edma_probe(struct platform_device *pdev) } } - /* Everything lives on transfer controller 1 until otherwise specified. - * This way, long transfers on the low priority queue - * started by the codec engine will not cause audio defects. - */ - for (i = 0; i < num_channels; i++) - map_dmach_queue(i, EVENTQ_1); - - /* Event queue to TC mapping */ - for (i = 0; queue_tc_mapping[i][0] != -1; i++) - map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]); - - /* Event queue priority mapping */ - for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(queue_priority_mapping[i][0], - queue_priority_mapping[i][1]); - - for (i = 0; i < info->n_region; i++) { - edma_write_array2(EDMA_DRAE, i, 0, 0x0); - edma_write_array2(EDMA_DRAE, i, 1, 0x0); - edma_write_array(EDMA_QRAE, i, 0x0); - } - return 0; fail: - if (err_irq) - free_irq(err_irq, NULL); - if (irq) - free_irq(irq, NULL); - iounmap(edmacc_regs_base); + for (i = 0; i < EDMA_MAX_CC; i++) { + if (err_irq[i]) + free_irq(err_irq[i], &pdev->dev); + if (irq[i]) + free_irq(irq[i], &pdev->dev); + } fail1: - release_mem_region(r->start, len); + for (i = 0; i < EDMA_MAX_CC; i++) { + if (r[i]) + release_mem_region(r[i]->start, len[i]); + if (edmacc_regs_base[i]) + iounmap(edmacc_regs_base[i]); + kfree(edma_info[i]); + } return status; } diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 1b6532159c58..f6ea9db11f41 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -34,6 +34,7 @@ static DEFINE_SPINLOCK(gpio_lock); struct davinci_gpio { struct gpio_chip chip; struct gpio_controller *__iomem regs; + int irq_base; }; static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; @@ -161,8 +162,7 @@ pure_initcall(davinci_gpio_setup); * used as output pins ... which is convenient for testing. * * NOTE: The first few GPIOs also have direct INTC hookups in addition - * to their GPIOBNK0 irq, with a bit less overhead but less flexibility - * on triggering (e.g. no edge options). We don't try to use those. + * to their GPIOBNK0 irq, with a bit less overhead. * * All those INTC hookups (direct, plus several IRQ banks) can also * serve as EDMA event triggers. @@ -171,7 +171,7 @@ pure_initcall(davinci_gpio_setup); static void gpio_irq_disable(unsigned irq) { struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = __gpio_mask(irq_to_gpio(irq)); + u32 mask = (u32) get_irq_data(irq); __raw_writel(mask, &g->clr_falling); __raw_writel(mask, &g->clr_rising); @@ -180,7 +180,7 @@ static void gpio_irq_disable(unsigned irq) static void gpio_irq_enable(unsigned irq) { struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = __gpio_mask(irq_to_gpio(irq)); + u32 mask = (u32) get_irq_data(irq); unsigned status = irq_desc[irq].status; status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; @@ -196,7 +196,7 @@ static void gpio_irq_enable(unsigned irq) static int gpio_irq_type(unsigned irq, unsigned trigger) { struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = __gpio_mask(irq_to_gpio(irq)); + u32 mask = (u32) get_irq_data(irq); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; @@ -260,6 +260,45 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) /* now it may re-trigger */ } +static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); + + if (d->irq_base >= 0) + return d->irq_base + offset; + else + return -ENODEV; +} + +static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + /* NOTE: we assume for now that only irqs in the first gpio_chip + * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). + */ + if (offset < soc_info->gpio_unbanked) + return soc_info->gpio_irq + offset; + else + return -ENODEV; +} + +static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) +{ + struct gpio_controller *__iomem g = get_irq_chip_data(irq); + u32 mask = (u32) get_irq_data(irq); + + if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + return -EINVAL; + + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) + ? &g->set_falling : &g->clr_falling); + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) + ? &g->set_rising : &g->clr_rising); + + return 0; +} + /* * NOTE: for suspend/resume, probably best to make a platform_device with * suspend_late/resume_resume calls hooking into results of the set_wake() @@ -275,6 +314,7 @@ static int __init davinci_gpio_irq_setup(void) u32 binten = 0; unsigned ngpio, bank_irq; struct davinci_soc_info *soc_info = &davinci_soc_info; + struct gpio_controller *__iomem g; ngpio = soc_info->gpio_num; @@ -292,12 +332,63 @@ static int __init davinci_gpio_irq_setup(void) } clk_enable(clk); + /* Arrange gpio_to_irq() support, handling either direct IRQs or + * banked IRQs. Having GPIOs in the first GPIO bank use direct + * IRQs, while the others use banked IRQs, would need some setup + * tweaks to recognize hardware which can do that. + */ + for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { + chips[bank].chip.to_irq = gpio_to_irq_banked; + chips[bank].irq_base = soc_info->gpio_unbanked + ? -EINVAL + : (soc_info->intc_irq_num + gpio); + } + + /* + * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO + * controller only handling trigger modes. We currently assume no + * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. + */ + if (soc_info->gpio_unbanked) { + static struct irq_chip gpio_irqchip_unbanked; + + /* pass "bank 0" GPIO IRQs to AINTC */ + chips[0].chip.to_irq = gpio_to_irq_unbanked; + binten = BIT(0); + + /* AINTC handles mask/unmask; GPIO handles triggering */ + irq = bank_irq; + gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); + gpio_irqchip_unbanked.name = "GPIO-AINTC"; + gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked; + + /* default trigger: both edges */ + g = gpio2controller(0); + __raw_writel(~0, &g->set_falling); + __raw_writel(~0, &g->set_rising); + + /* set the direct IRQs up to use that irqchip */ + for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { + set_irq_chip(irq, &gpio_irqchip_unbanked); + set_irq_data(irq, (void *) __gpio_mask(gpio)); + set_irq_chip_data(irq, g); + irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; + } + + goto done; + } + + /* + * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we + * then chain through our own handler. + */ for (gpio = 0, irq = gpio_to_irq(0), bank = 0; gpio < ngpio; bank++, bank_irq++) { - struct gpio_controller *__iomem g = gpio2controller(gpio); unsigned i; + /* disabled by default, enabled only as needed */ + g = gpio2controller(gpio); __raw_writel(~0, &g->clr_falling); __raw_writel(~0, &g->clr_rising); @@ -309,6 +400,7 @@ static int __init davinci_gpio_irq_setup(void) for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { set_irq_chip(irq, &gpio_irqchip); set_irq_chip_data(irq, g); + set_irq_data(irq, (void *) __gpio_mask(gpio)); set_irq_handler(irq, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); } @@ -316,6 +408,7 @@ static int __init davinci_gpio_irq_setup(void) binten |= BIT(bank); } +done: /* BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index e0abc437d796..18e4ce34ece6 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -5,21 +5,73 @@ #define __ASM_ARCH_DAVINCI_ASP_H #include <mach/irqs.h> +#include <mach/edma.h> -/* Bases of register banks */ +/* Bases of dm644x and dm355 register banks */ #define DAVINCI_ASP0_BASE 0x01E02000 #define DAVINCI_ASP1_BASE 0x01E04000 -/* EDMA channels */ +/* Bases of dm646x register banks */ +#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 +#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 + +/* Bases of da850/da830 McASP0 register banks */ +#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 + +/* Bases of da830 McASP1 register banks */ +#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 + +/* EDMA channels of dm644x and dm355 */ #define DAVINCI_DMA_ASP0_TX 2 #define DAVINCI_DMA_ASP0_RX 3 #define DAVINCI_DMA_ASP1_TX 8 #define DAVINCI_DMA_ASP1_RX 9 +/* EDMA channels of dm646x */ +#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 +#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 +#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 + +/* EDMA channels of da850/da830 McASP0 */ +#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 +#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 + +/* EDMA channels of da830 McASP1 */ +#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 +#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 + /* Interrupts */ #define DAVINCI_ASP0_RX_INT IRQ_MBRINT #define DAVINCI_ASP0_TX_INT IRQ_MBXINT #define DAVINCI_ASP1_RX_INT IRQ_MBRINT #define DAVINCI_ASP1_TX_INT IRQ_MBXINT +struct snd_platform_data { + u32 tx_dma_offset; + u32 rx_dma_offset; + enum dma_event_q eventq_no; /* event queue number */ + unsigned int codec_fmt; + + /* McASP specific fields */ + int tdm_slots; + u8 op_mode; + u8 num_serializer; + u8 *serial_dir; + u8 version; + u8 txnumevt; + u8 rxnumevt; +}; + +enum { + MCASP_VERSION_1 = 0, /* DM646x */ + MCASP_VERSION_2, /* DA8xx/OMAPL1x */ +}; + +#define INACTIVE_MODE 0 +#define TX_MODE 1 +#define RX_MODE 2 + +#define DAVINCI_MCASP_IIS_MODE 0 +#define DAVINCI_MCASP_DIT_MODE 1 + #endif /* __ASM_ARCH_DAVINCI_ASP_H */ diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index a1f03b606d8f..1fd3917cae4e 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -60,10 +60,10 @@ struct davinci_soc_info { u8 *intc_irq_prios; unsigned long intc_irq_num; struct davinci_timer_info *timer_info; - void __iomem *wdt_base; void __iomem *gpio_base; unsigned gpio_num; unsigned gpio_irq; + unsigned gpio_unbanked; struct platform_device *serial_dev; struct emac_platform_data *emac_pdata; dma_addr_t sram_dma; diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index d12a5ed2959a..189b1ff13642 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -30,6 +30,9 @@ struct davinci_id { #define DAVINCI_CPU_ID_DM6446 0x64460000 #define DAVINCI_CPU_ID_DM6467 0x64670000 #define DAVINCI_CPU_ID_DM355 0x03550000 +#define DAVINCI_CPU_ID_DM365 0x03650000 +#define DAVINCI_CPU_ID_DA830 0x08300000 +#define DAVINCI_CPU_ID_DA850 0x08500000 #define IS_DAVINCI_CPU(type, id) \ static inline int is_davinci_ ##type(void) \ @@ -40,6 +43,9 @@ static inline int is_davinci_ ##type(void) \ IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) +IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) +IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) +IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() @@ -59,4 +65,22 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) #define cpu_is_davinci_dm355() 0 #endif +#ifdef CONFIG_ARCH_DAVINCI_DM365 +#define cpu_is_davinci_dm365() is_davinci_dm365() +#else +#define cpu_is_davinci_dm365() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DA830 +#define cpu_is_davinci_da830() is_davinci_da830() +#else +#define cpu_is_davinci_da830() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DA850 +#define cpu_is_davinci_da850() is_davinci_da850() +#else +#define cpu_is_davinci_da850() 0 +#endif + #endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h new file mode 100644 index 000000000000..d4095d0572c6 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -0,0 +1,121 @@ +/* + * Chip specific defines for DA8XX/OMAP L1XX SoC + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_DA8XX_H +#define __ASM_ARCH_DAVINCI_DA8XX_H + +#include <mach/serial.h> +#include <mach/edma.h> +#include <mach/i2c.h> +#include <mach/emac.h> +#include <mach/asp.h> +#include <mach/mmc.h> + +/* + * The cp_intc interrupt controller for the da8xx isn't in the same + * chunk of physical memory space as the other registers (like it is + * on the davincis) so it needs to be mapped separately. It will be + * mapped early on when the I/O space is mapped and we'll put it just + * before the I/O space in the processor's virtual memory space. + */ +#define DA8XX_CP_INTC_BASE 0xfffee000 +#define DA8XX_CP_INTC_SIZE SZ_8K +#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) + +#define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000) + +#define DA8XX_PSC0_BASE 0x01c10000 +#define DA8XX_PLL0_BASE 0x01c11000 +#define DA8XX_JTAG_ID_REG 0x01c14018 +#define DA8XX_TIMER64P0_BASE 0x01c20000 +#define DA8XX_TIMER64P1_BASE 0x01c21000 +#define DA8XX_GPIO_BASE 0x01e26000 +#define DA8XX_PSC1_BASE 0x01e27000 +#define DA8XX_LCD_CNTRL_BASE 0x01e13000 +#define DA8XX_MMCSD0_BASE 0x01c40000 +#define DA8XX_AEMIF_CS2_BASE 0x60000000 +#define DA8XX_AEMIF_CS3_BASE 0x62000000 +#define DA8XX_AEMIF_CTL_BASE 0x68000000 + +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define PINMUX5 0x14 +#define PINMUX6 0x18 +#define PINMUX7 0x1c +#define PINMUX8 0x20 +#define PINMUX9 0x24 +#define PINMUX10 0x28 +#define PINMUX11 0x2c +#define PINMUX12 0x30 +#define PINMUX13 0x34 +#define PINMUX14 0x38 +#define PINMUX15 0x3c +#define PINMUX16 0x40 +#define PINMUX17 0x44 +#define PINMUX18 0x48 +#define PINMUX19 0x4c + +void __init da830_init(void); +void __init da850_init(void); + +int da8xx_register_edma(void); +int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); +int da8xx_register_watchdog(void); +int da8xx_register_emac(void); +int da8xx_register_lcdc(void); +int da8xx_register_mmcsd0(struct davinci_mmc_config *config); +void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata); + +extern struct platform_device da8xx_serial_device; +extern struct emac_platform_data da8xx_emac_pdata; + +extern const short da830_emif25_pins[]; +extern const short da830_spi0_pins[]; +extern const short da830_spi1_pins[]; +extern const short da830_mmc_sd_pins[]; +extern const short da830_uart0_pins[]; +extern const short da830_uart1_pins[]; +extern const short da830_uart2_pins[]; +extern const short da830_usb20_pins[]; +extern const short da830_usb11_pins[]; +extern const short da830_uhpi_pins[]; +extern const short da830_cpgmac_pins[]; +extern const short da830_emif3c_pins[]; +extern const short da830_mcasp0_pins[]; +extern const short da830_mcasp1_pins[]; +extern const short da830_mcasp2_pins[]; +extern const short da830_i2c0_pins[]; +extern const short da830_i2c1_pins[]; +extern const short da830_lcdcntl_pins[]; +extern const short da830_pwm_pins[]; +extern const short da830_ecap0_pins[]; +extern const short da830_ecap1_pins[]; +extern const short da830_ecap2_pins[]; +extern const short da830_eqep0_pins[]; +extern const short da830_eqep1_pins[]; + +extern const short da850_uart0_pins[]; +extern const short da850_uart1_pins[]; +extern const short da850_uart2_pins[]; +extern const short da850_i2c0_pins[]; +extern const short da850_i2c1_pins[]; +extern const short da850_cpgmac_pins[]; +extern const short da850_mcasp_pins[]; +extern const short da850_lcdcntl_pins[]; +extern const short da850_mmcsd0_pins[]; +extern const short da850_nand_pins[]; +extern const short da850_nor_pins[]; + +int da8xx_pinmux_setup(const short pins[]); + +#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index de3fc2182b47..17ab5236da66 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -24,7 +24,15 @@ tst \rx, #1 @ MMU enabled? moveq \rx, #0x01000000 @ physical base address movne \rx, #0xfe000000 @ virtual base +#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) +#error Cannot enable DaVinci and DA8XX platforms concurrently +#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) + orr \rx, \rx, #0x00d00000 @ physical base address + orr \rx, \rx, #0x0000d000 @ of UART 2 +#else orr \rx, \rx, #0x00c20000 @ UART 0 +#endif .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h index 54903b72438e..85536d8e8336 100644 --- a/arch/arm/mach-davinci/include/mach/dm355.h +++ b/arch/arm/mach-davinci/include/mach/dm355.h @@ -12,11 +12,18 @@ #define __ASM_ARCH_DM355_H #include <mach/hardware.h> +#include <mach/asp.h> +#include <media/davinci/vpfe_capture.h> + +#define ASP1_TX_EVT_EN 1 +#define ASP1_RX_EVT_EN 2 struct spi_board_info; void __init dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, struct spi_board_info *info, unsigned len); +void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); +void dm355_set_vpfe_config(struct vpfe_config *cfg); #endif /* __ASM_ARCH_DM355_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h new file mode 100644 index 000000000000..09db4343bb4c --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ASM_ARCH_DM365_H +#define __ASM_ARCH_DM665_H + +#include <linux/platform_device.h> +#include <mach/hardware.h> +#include <mach/emac.h> + +#define DM365_EMAC_BASE (0x01D07000) +#define DM365_EMAC_CNTRL_OFFSET (0x0000) +#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) +#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) +#define DM365_EMAC_MDIO_OFFSET (0x4000) +#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) + +void __init dm365_init(void); + +#endif /* __ASM_ARCH_DM365_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 15d42b92a8c9..0efb73852c2c 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -25,6 +25,8 @@ #include <linux/platform_device.h> #include <mach/hardware.h> #include <mach/emac.h> +#include <mach/asp.h> +#include <media/davinci/vpfe_capture.h> #define DM644X_EMAC_BASE (0x01C80000) #define DM644X_EMAC_CNTRL_OFFSET (0x0000) @@ -34,5 +36,7 @@ #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) void __init dm644x_init(void); +void __init dm644x_init_asp(struct snd_platform_data *pdata); +void dm644x_set_vpfe_config(struct vpfe_config *cfg); #endif /* __ASM_ARCH_DM644X_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 1fc764c8646e..8cec746ae9d2 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -13,6 +13,9 @@ #include <mach/hardware.h> #include <mach/emac.h> +#include <mach/asp.h> +#include <linux/i2c.h> +#include <linux/videodev2.h> #define DM646X_EMAC_BASE (0x01C80000) #define DM646X_EMAC_CNTRL_OFFSET (0x0000) @@ -21,6 +24,68 @@ #define DM646X_EMAC_MDIO_OFFSET (0x4000) #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) +#define DM646X_ATA_REG_BASE (0x01C66000) + void __init dm646x_init(void); +void __init dm646x_init_ide(void); +void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); +void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); + +void dm646x_video_init(void); + +enum vpif_if_type { + VPIF_IF_BT656, + VPIF_IF_BT1120, + VPIF_IF_RAW_BAYER +}; + +struct vpif_interface { + enum vpif_if_type if_type; + unsigned hd_pol:1; + unsigned vd_pol:1; + unsigned fid_pol:1; +}; + +struct vpif_subdev_info { + const char *name; + struct i2c_board_info board_info; + u32 input; + u32 output; + unsigned can_route:1; + struct vpif_interface vpif_if; +}; + +struct vpif_display_config { + int (*set_clock)(int, int); + struct vpif_subdev_info *subdevinfo; + int subdev_count; + const char **output; + int output_count; + const char *card_name; +}; + +struct vpif_input { + struct v4l2_input input; + const char *subdev_name; +}; + +#define VPIF_CAPTURE_MAX_CHANNELS 2 + +struct vpif_capture_chan_config { + const struct vpif_input *inputs; + int input_count; +}; + +struct vpif_capture_config { + int (*setup_input_channel_mode)(int); + int (*setup_input_path)(int, const char *); + struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS]; + struct vpif_subdev_info *subdev_info; + int subdev_count; + const char *card_name; +}; + +void dm646x_setup_vpif(struct vpif_display_config *, + struct vpif_capture_config *); #endif /* __ASM_ARCH_DM646X_H */ diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index 24a379239d7f..eb8bfd7925e7 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -139,6 +139,54 @@ struct edmacc_param { #define DAVINCI_DMA_PWM1 53 #define DAVINCI_DMA_PWM2 54 +/* DA830 specific EDMA3 information */ +#define EDMA_DA830_NUM_DMACH 32 +#define EDMA_DA830_NUM_TCC 32 +#define EDMA_DA830_NUM_PARAMENTRY 128 +#define EDMA_DA830_NUM_EVQUE 2 +#define EDMA_DA830_NUM_TC 2 +#define EDMA_DA830_CHMAP_EXIST 0 +#define EDMA_DA830_NUM_REGIONS 4 +#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu +#define DA830_DMACH2EVENT_MAP1 0x00000000u +#define DA830_EDMA_ARM_OWN 0x30FFCCFFu + +/* DA830 specific EDMA3 Events Information */ +enum DA830_edma_ch { + DA830_DMACH_MCASP0_RX, + DA830_DMACH_MCASP0_TX, + DA830_DMACH_MCASP1_RX, + DA830_DMACH_MCASP1_TX, + DA830_DMACH_MCASP2_RX, + DA830_DMACH_MCASP2_TX, + DA830_DMACH_GPIO_BNK0INT, + DA830_DMACH_GPIO_BNK1INT, + DA830_DMACH_UART0_RX, + DA830_DMACH_UART0_TX, + DA830_DMACH_TMR64P0_EVTOUT12, + DA830_DMACH_TMR64P0_EVTOUT34, + DA830_DMACH_UART1_RX, + DA830_DMACH_UART1_TX, + DA830_DMACH_SPI0_RX, + DA830_DMACH_SPI0_TX, + DA830_DMACH_MMCSD_RX, + DA830_DMACH_MMCSD_TX, + DA830_DMACH_SPI1_RX, + DA830_DMACH_SPI1_TX, + DA830_DMACH_DMAX_EVTOUT6, + DA830_DMACH_DMAX_EVTOUT7, + DA830_DMACH_GPIO_BNK2INT, + DA830_DMACH_GPIO_BNK3INT, + DA830_DMACH_I2C0_RX, + DA830_DMACH_I2C0_TX, + DA830_DMACH_I2C1_RX, + DA830_DMACH_I2C1_TX, + DA830_DMACH_GPIO_BNK4INT, + DA830_DMACH_GPIO_BNK5INT, + DA830_DMACH_UART2_RX, + DA830_DMACH_UART2_TX +}; + /*ch_status paramater of callback function possible values*/ #define DMA_COMPLETE 1 #define DMA_CC_ERROR 2 @@ -162,6 +210,8 @@ enum fifo_width { enum dma_event_q { EVENTQ_0 = 0, EVENTQ_1 = 1, + EVENTQ_2 = 2, + EVENTQ_3 = 3, EVENTQ_DEFAULT = -1 }; @@ -170,8 +220,15 @@ enum sync_dimension { ABSYNC = 1 }; +#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) +#define EDMA_CTLR(i) ((i) >> 16) +#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) + #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ +#define EDMA_CONT_PARAMS_ANY 1001 +#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 +#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 /* alloc/free DMA channels and their dedicated parameter RAM slots */ int edma_alloc_channel(int channel, @@ -180,9 +237,13 @@ int edma_alloc_channel(int channel, void edma_free_channel(unsigned channel); /* alloc/free parameter RAM slots */ -int edma_alloc_slot(int slot); +int edma_alloc_slot(unsigned ctlr, int slot); void edma_free_slot(unsigned slot); +/* alloc/free a set of contiguous parameter RAM slots */ +int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); +int edma_free_cont_slots(unsigned slot, int count); + /* calls that operate on part of a parameter RAM slot */ void edma_set_src(unsigned slot, dma_addr_t src_port, enum address_mode mode, enum fifo_width); @@ -216,9 +277,13 @@ struct edma_soc_info { unsigned n_region; unsigned n_slot; unsigned n_tc; + unsigned n_cc; + enum dma_event_q default_queue; /* list of channels with no even trigger; terminated by "-1" */ const s8 *noevent; + const s8 (*queue_tc_mapping)[2]; + const s8 (*queue_priority_mapping)[2]; }; #endif diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index ae0745568316..f3b8ef878158 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -42,6 +42,9 @@ */ #define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */ +/* Convert GPIO signal to GPIO pin number */ +#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) + struct gpio_controller { u32 dir; u32 out_data; @@ -78,6 +81,8 @@ __gpio_to_controller(unsigned gpio) ptr = base + 0x60; else if (gpio < 32 * 4) ptr = base + 0x88; + else if (gpio < 32 * 5) + ptr = base + 0xb0; else ptr = NULL; return ptr; @@ -142,15 +147,13 @@ static inline int gpio_cansleep(unsigned gpio) static inline int gpio_to_irq(unsigned gpio) { - if (gpio >= DAVINCI_N_GPIO) - return -EINVAL; - return davinci_soc_info.intc_irq_num + gpio; + return __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned irq) { - /* caller guarantees gpio_to_irq() succeeded */ - return irq - davinci_soc_info.intc_irq_num; + /* don't support the reverse mapping */ + return -ENOSYS; } #endif /* __DAVINCI_GPIO_H */ diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index 48c77934d519..41c89386e39b 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -24,4 +24,21 @@ /* System control register offsets */ #define DM64XX_VDD3P3V_PWDN 0x48 +/* + * I/O mapping + */ +#define IO_PHYS 0x01c00000 +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define __IO_ADDRESS(x) ((x) + IO_OFFSET) +#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) + +#ifdef __ASSEMBLER__ +#define IOMEM(x) x +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h index 2479785405af..62b0a90309ad 100644 --- a/arch/arm/mach-davinci/include/mach/io.h +++ b/arch/arm/mach-davinci/include/mach/io.h @@ -14,18 +14,6 @@ #define IO_SPACE_LIMIT 0xffffffff /* - * ---------------------------------------------------------------------------- - * I/O mapping - * ---------------------------------------------------------------------------- - */ -#define IO_PHYS 0x01c00000 -#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ -#define IO_SIZE 0x00400000 -#define IO_VIRT (IO_PHYS + IO_OFFSET) -#define io_v2p(va) ((va) - IO_OFFSET) -#define __IO_ADDRESS(x) ((x) + IO_OFFSET) - -/* * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... */ @@ -33,19 +21,12 @@ #define __mem_pci(a) (a) #define __mem_isa(a) (a) -#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) - -#ifdef __ASSEMBLER__ -#define IOMEM(x) x -#else -#define IOMEM(x) ((void __force __iomem *)(x)) - +#ifndef __ASSEMBLER__ #define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t) #define __arch_iounmap(v) davinci_iounmap(v) void __iomem *davinci_ioremap(unsigned long phys, size_t size, unsigned int type); void davinci_iounmap(volatile void __iomem *addr); - -#endif /* __ASSEMBLER__ */ +#endif #endif /* __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index bc5d6aaa69a3..3c918a772619 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -99,9 +99,6 @@ #define IRQ_EMUINT 63 #define DAVINCI_N_AINTC_IRQ 64 -#define DAVINCI_N_GPIO 104 - -#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 @@ -206,4 +203,206 @@ #define IRQ_DM355_GPIOBNK5 59 #define IRQ_DM355_GPIOBNK6 60 +/* DaVinci DM365-specific Interrupts */ +#define IRQ_DM365_INSFINT 7 +#define IRQ_DM365_IMXINT1 8 +#define IRQ_DM365_IMXINT0 10 +#define IRQ_DM365_KLD_ARMINT 10 +#define IRQ_DM365_IMCOPINT 11 +#define IRQ_DM365_RTOINT 13 +#define IRQ_DM365_TINT5 14 +#define IRQ_DM365_TINT6 15 +#define IRQ_DM365_SPINT2_1 21 +#define IRQ_DM365_TINT7 22 +#define IRQ_DM365_SDIOINT0 23 +#define IRQ_DM365_MMCINT1 27 +#define IRQ_DM365_PWMINT3 28 +#define IRQ_DM365_SDIOINT1 31 +#define IRQ_DM365_SPIINT0_0 42 +#define IRQ_DM365_SPIINT3_0 43 +#define IRQ_DM365_GPIO0 44 +#define IRQ_DM365_GPIO1 45 +#define IRQ_DM365_GPIO2 46 +#define IRQ_DM365_GPIO3 47 +#define IRQ_DM365_GPIO4 48 +#define IRQ_DM365_GPIO5 49 +#define IRQ_DM365_GPIO6 50 +#define IRQ_DM365_GPIO7 51 +#define IRQ_DM365_EMAC_RXTHRESH 52 +#define IRQ_DM365_EMAC_RXPULSE 53 +#define IRQ_DM365_EMAC_TXPULSE 54 +#define IRQ_DM365_EMAC_MISCPULSE 55 +#define IRQ_DM365_GPIO12 56 +#define IRQ_DM365_GPIO13 57 +#define IRQ_DM365_GPIO14 58 +#define IRQ_DM365_GPIO15 59 +#define IRQ_DM365_ADCINT 59 +#define IRQ_DM365_KEYINT 60 +#define IRQ_DM365_TCERRINT2 61 +#define IRQ_DM365_TCERRINT3 62 +#define IRQ_DM365_EMUINT 63 + +/* DA8XX interrupts */ +#define IRQ_DA8XX_COMMTX 0 +#define IRQ_DA8XX_COMMRX 1 +#define IRQ_DA8XX_NINT 2 +#define IRQ_DA8XX_EVTOUT0 3 +#define IRQ_DA8XX_EVTOUT1 4 +#define IRQ_DA8XX_EVTOUT2 5 +#define IRQ_DA8XX_EVTOUT3 6 +#define IRQ_DA8XX_EVTOUT4 7 +#define IRQ_DA8XX_EVTOUT5 8 +#define IRQ_DA8XX_EVTOUT6 9 +#define IRQ_DA8XX_EVTOUT7 10 +#define IRQ_DA8XX_CCINT0 11 +#define IRQ_DA8XX_CCERRINT 12 +#define IRQ_DA8XX_TCERRINT0 13 +#define IRQ_DA8XX_AEMIFINT 14 +#define IRQ_DA8XX_I2CINT0 15 +#define IRQ_DA8XX_MMCSDINT0 16 +#define IRQ_DA8XX_MMCSDINT1 17 +#define IRQ_DA8XX_ALLINT0 18 +#define IRQ_DA8XX_RTC 19 +#define IRQ_DA8XX_SPINT0 20 +#define IRQ_DA8XX_TINT12_0 21 +#define IRQ_DA8XX_TINT34_0 22 +#define IRQ_DA8XX_TINT12_1 23 +#define IRQ_DA8XX_TINT34_1 24 +#define IRQ_DA8XX_UARTINT0 25 +#define IRQ_DA8XX_KEYMGRINT 26 +#define IRQ_DA8XX_SECINT 26 +#define IRQ_DA8XX_SECKEYERR 26 +#define IRQ_DA8XX_CHIPINT0 28 +#define IRQ_DA8XX_CHIPINT1 29 +#define IRQ_DA8XX_CHIPINT2 30 +#define IRQ_DA8XX_CHIPINT3 31 +#define IRQ_DA8XX_TCERRINT1 32 +#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33 +#define IRQ_DA8XX_C0_RX_PULSE 34 +#define IRQ_DA8XX_C0_TX_PULSE 35 +#define IRQ_DA8XX_C0_MISC_PULSE 36 +#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37 +#define IRQ_DA8XX_C1_RX_PULSE 38 +#define IRQ_DA8XX_C1_TX_PULSE 39 +#define IRQ_DA8XX_C1_MISC_PULSE 40 +#define IRQ_DA8XX_MEMERR 41 +#define IRQ_DA8XX_GPIO0 42 +#define IRQ_DA8XX_GPIO1 43 +#define IRQ_DA8XX_GPIO2 44 +#define IRQ_DA8XX_GPIO3 45 +#define IRQ_DA8XX_GPIO4 46 +#define IRQ_DA8XX_GPIO5 47 +#define IRQ_DA8XX_GPIO6 48 +#define IRQ_DA8XX_GPIO7 49 +#define IRQ_DA8XX_GPIO8 50 +#define IRQ_DA8XX_I2CINT1 51 +#define IRQ_DA8XX_LCDINT 52 +#define IRQ_DA8XX_UARTINT1 53 +#define IRQ_DA8XX_MCASPINT 54 +#define IRQ_DA8XX_ALLINT1 55 +#define IRQ_DA8XX_SPINT1 56 +#define IRQ_DA8XX_UHPI_INT1 57 +#define IRQ_DA8XX_USB_INT 58 +#define IRQ_DA8XX_IRQN 59 +#define IRQ_DA8XX_RWAKEUP 60 +#define IRQ_DA8XX_UARTINT2 61 +#define IRQ_DA8XX_DFTSSINT 62 +#define IRQ_DA8XX_EHRPWM0 63 +#define IRQ_DA8XX_EHRPWM0TZ 64 +#define IRQ_DA8XX_EHRPWM1 65 +#define IRQ_DA8XX_EHRPWM1TZ 66 +#define IRQ_DA8XX_ECAP0 69 +#define IRQ_DA8XX_ECAP1 70 +#define IRQ_DA8XX_ECAP2 71 +#define IRQ_DA8XX_ARMCLKSTOPREQ 90 + +/* DA830 specific interrupts */ +#define IRQ_DA830_MPUERR 27 +#define IRQ_DA830_IOPUERR 27 +#define IRQ_DA830_BOOTCFGERR 27 +#define IRQ_DA830_EHRPWM2 67 +#define IRQ_DA830_EHRPWM2TZ 68 +#define IRQ_DA830_EQEP0 72 +#define IRQ_DA830_EQEP1 73 +#define IRQ_DA830_T12CMPINT0_0 74 +#define IRQ_DA830_T12CMPINT1_0 75 +#define IRQ_DA830_T12CMPINT2_0 76 +#define IRQ_DA830_T12CMPINT3_0 77 +#define IRQ_DA830_T12CMPINT4_0 78 +#define IRQ_DA830_T12CMPINT5_0 79 +#define IRQ_DA830_T12CMPINT6_0 80 +#define IRQ_DA830_T12CMPINT7_0 81 +#define IRQ_DA830_T12CMPINT0_1 82 +#define IRQ_DA830_T12CMPINT1_1 83 +#define IRQ_DA830_T12CMPINT2_1 84 +#define IRQ_DA830_T12CMPINT3_1 85 +#define IRQ_DA830_T12CMPINT4_1 86 +#define IRQ_DA830_T12CMPINT5_1 87 +#define IRQ_DA830_T12CMPINT6_1 88 +#define IRQ_DA830_T12CMPINT7_1 89 + +#define DA830_N_CP_INTC_IRQ 96 + +/* DA850 speicific interrupts */ +#define IRQ_DA850_MPUADDRERR0 27 +#define IRQ_DA850_MPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR0 27 +#define IRQ_DA850_IOPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR1 27 +#define IRQ_DA850_IOPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR2 27 +#define IRQ_DA850_IOPUPROTERR2 27 +#define IRQ_DA850_BOOTCFG_ADDR_ERR 27 +#define IRQ_DA850_BOOTCFG_PROT_ERR 27 +#define IRQ_DA850_MPUADDRERR1 27 +#define IRQ_DA850_MPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR3 27 +#define IRQ_DA850_IOPUPROTERR3 27 +#define IRQ_DA850_IOPUADDRERR4 27 +#define IRQ_DA850_IOPUPROTERR4 27 +#define IRQ_DA850_IOPUADDRERR5 27 +#define IRQ_DA850_IOPUPROTERR5 27 +#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27 +#define IRQ_DA850_SATAINT 67 +#define IRQ_DA850_TINT12_2 68 +#define IRQ_DA850_TINT34_2 68 +#define IRQ_DA850_TINTALL_2 68 +#define IRQ_DA850_MMCSDINT0_1 72 +#define IRQ_DA850_MMCSDINT1_1 73 +#define IRQ_DA850_T12CMPINT0_2 74 +#define IRQ_DA850_T12CMPINT1_2 75 +#define IRQ_DA850_T12CMPINT2_2 76 +#define IRQ_DA850_T12CMPINT3_2 77 +#define IRQ_DA850_T12CMPINT4_2 78 +#define IRQ_DA850_T12CMPINT5_2 79 +#define IRQ_DA850_T12CMPINT6_2 80 +#define IRQ_DA850_T12CMPINT7_2 81 +#define IRQ_DA850_T12CMPINT0_3 82 +#define IRQ_DA850_T12CMPINT1_3 83 +#define IRQ_DA850_T12CMPINT2_3 84 +#define IRQ_DA850_T12CMPINT3_3 85 +#define IRQ_DA850_T12CMPINT4_3 86 +#define IRQ_DA850_T12CMPINT5_3 87 +#define IRQ_DA850_T12CMPINT6_3 88 +#define IRQ_DA850_T12CMPINT7_3 89 +#define IRQ_DA850_RPIINT 91 +#define IRQ_DA850_VPIFINT 92 +#define IRQ_DA850_CCINT1 93 +#define IRQ_DA850_CCERRINT1 94 +#define IRQ_DA850_TCERRINT2 95 +#define IRQ_DA850_TINT12_3 96 +#define IRQ_DA850_TINT34_3 96 +#define IRQ_DA850_TINTALL_3 96 +#define IRQ_DA850_MCBSP0RINT 97 +#define IRQ_DA850_MCBSP0XINT 98 +#define IRQ_DA850_MCBSP1RINT 99 +#define IRQ_DA850_MCBSP1XINT 100 + +#define DA850_N_CP_INTC_IRQ 101 + +/* da850 currently has the most gpio pins (144) */ +#define DAVINCI_N_GPIO 144 +/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ +#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO) + #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index c712c7cdf38f..80309aed534a 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -20,9 +20,16 @@ /************************************************************************** * Definitions **************************************************************************/ -#define DAVINCI_DDR_BASE 0x80000000 +#define DAVINCI_DDR_BASE 0x80000000 +#define DA8XX_DDR_BASE 0xc0000000 +#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) +#error Cannot enable DaVinci and DA8XX platforms concurrently +#elif defined(CONFIG_ARCH_DAVINCI_DA8XX) +#define PHYS_OFFSET DA8XX_DDR_BASE +#else #define PHYS_OFFSET DAVINCI_DDR_BASE +#endif /* * Increase size of DMA-consistent memory region diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 27378458542f..bb84893a4e83 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -154,6 +154,737 @@ enum davinci_dm355_index { DM355_EVT8_ASP1_TX, DM355_EVT9_ASP1_RX, DM355_EVT26_MMC0_RX, + + /* Video Out */ + DM355_VOUT_FIELD, + DM355_VOUT_FIELD_G70, + DM355_VOUT_HVSYNC, + DM355_VOUT_COUTL_EN, + DM355_VOUT_COUTH_EN, + + /* Video In Pin Mux */ + DM355_VIN_PCLK, + DM355_VIN_CAM_WEN, + DM355_VIN_CAM_VD, + DM355_VIN_CAM_HD, + DM355_VIN_YIN_EN, + DM355_VIN_CINL_EN, + DM355_VIN_CINH_EN, +}; + +enum davinci_dm365_index { + /* MMC/SD 0 */ + DM365_MMCSD0, + + /* MMC/SD 1 */ + DM365_SD1_CLK, + DM365_SD1_CMD, + DM365_SD1_DATA3, + DM365_SD1_DATA2, + DM365_SD1_DATA1, + DM365_SD1_DATA0, + + /* I2C */ + DM365_I2C_SDA, + DM365_I2C_SCL, + + /* AEMIF */ + DM365_AEMIF_AR, + DM365_AEMIF_A3, + DM365_AEMIF_A7, + DM365_AEMIF_D15_8, + DM365_AEMIF_CE0, + + /* ASP0 function */ + DM365_MCBSP0_BDX, + DM365_MCBSP0_X, + DM365_MCBSP0_BFSX, + DM365_MCBSP0_BDR, + DM365_MCBSP0_R, + DM365_MCBSP0_BFSR, + + /* SPI0 */ + DM365_SPI0_SCLK, + DM365_SPI0_SDI, + DM365_SPI0_SDO, + DM365_SPI0_SDENA0, + DM365_SPI0_SDENA1, + + /* UART */ + DM365_UART0_RXD, + DM365_UART0_TXD, + DM365_UART1_RXD, + DM365_UART1_TXD, + DM365_UART1_RTS, + DM365_UART1_CTS, + + /* EMAC */ + DM365_EMAC_TX_EN, + DM365_EMAC_TX_CLK, + DM365_EMAC_COL, + DM365_EMAC_TXD3, + DM365_EMAC_TXD2, + DM365_EMAC_TXD1, + DM365_EMAC_TXD0, + DM365_EMAC_RXD3, + DM365_EMAC_RXD2, + DM365_EMAC_RXD1, + DM365_EMAC_RXD0, + DM365_EMAC_RX_CLK, + DM365_EMAC_RX_DV, + DM365_EMAC_RX_ER, + DM365_EMAC_CRS, + DM365_EMAC_MDIO, + DM365_EMAC_MDCLK, + + /* Keypad */ + DM365_KEYPAD, + + /* PWM */ + DM365_PWM0, + DM365_PWM0_G23, + DM365_PWM1, + DM365_PWM1_G25, + DM365_PWM2_G87, + DM365_PWM2_G88, + DM365_PWM2_G89, + DM365_PWM2_G90, + DM365_PWM3_G80, + DM365_PWM3_G81, + DM365_PWM3_G85, + DM365_PWM3_G86, + + /* SPI1 */ + DM365_SPI1_SCLK, + DM365_SPI1_SDO, + DM365_SPI1_SDI, + DM365_SPI1_SDENA0, + DM365_SPI1_SDENA1, + + /* SPI2 */ + DM365_SPI2_SCLK, + DM365_SPI2_SDO, + DM365_SPI2_SDI, + DM365_SPI2_SDENA0, + DM365_SPI2_SDENA1, + + /* SPI3 */ + DM365_SPI3_SCLK, + DM365_SPI3_SDO, + DM365_SPI3_SDI, + DM365_SPI3_SDENA0, + DM365_SPI3_SDENA1, + + /* SPI4 */ + DM365_SPI4_SCLK, + DM365_SPI4_SDO, + DM365_SPI4_SDI, + DM365_SPI4_SDENA0, + DM365_SPI4_SDENA1, + + /* GPIO */ + DM365_GPIO20, + DM365_GPIO33, + DM365_GPIO40, + + /* Video */ + DM365_VOUT_FIELD, + DM365_VOUT_FIELD_G81, + DM365_VOUT_HVSYNC, + DM365_VOUT_COUTL_EN, + DM365_VOUT_COUTH_EN, + DM365_VIN_CAM_WEN, + DM365_VIN_CAM_VD, + DM365_VIN_CAM_HD, + DM365_VIN_YIN4_7_EN, + DM365_VIN_YIN0_3_EN, + + /* IRQ muxing */ + DM365_INT_EDMA_CC, + DM365_INT_EDMA_TC0_ERR, + DM365_INT_EDMA_TC1_ERR, + DM365_INT_EDMA_TC2_ERR, + DM365_INT_EDMA_TC3_ERR, + DM365_INT_PRTCSS, + DM365_INT_EMAC_RXTHRESH, + DM365_INT_EMAC_RXPULSE, + DM365_INT_EMAC_TXPULSE, + DM365_INT_EMAC_MISCPULSE, + DM365_INT_IMX0_ENABLE, + DM365_INT_IMX0_DISABLE, + DM365_INT_HDVICP_ENABLE, + DM365_INT_HDVICP_DISABLE, + DM365_INT_IMX1_ENABLE, + DM365_INT_IMX1_DISABLE, + DM365_INT_NSF_ENABLE, + DM365_INT_NSF_DISABLE, + + /* EDMA event muxing */ + DM365_EVT2_ASP_TX, + DM365_EVT3_ASP_RX, + DM365_EVT26_MMC0_RX, +}; + +enum da830_index { + DA830_GPIO7_14, + DA830_RTCK, + DA830_GPIO7_15, + DA830_EMU_0, + DA830_EMB_SDCKE, + DA830_EMB_CLK_GLUE, + DA830_EMB_CLK, + DA830_NEMB_CS_0, + DA830_NEMB_CAS, + DA830_NEMB_RAS, + DA830_NEMB_WE, + DA830_EMB_BA_1, + DA830_EMB_BA_0, + DA830_EMB_A_0, + DA830_EMB_A_1, + DA830_EMB_A_2, + DA830_EMB_A_3, + DA830_EMB_A_4, + DA830_EMB_A_5, + DA830_GPIO7_0, + DA830_GPIO7_1, + DA830_GPIO7_2, + DA830_GPIO7_3, + DA830_GPIO7_4, + DA830_GPIO7_5, + DA830_GPIO7_6, + DA830_GPIO7_7, + DA830_EMB_A_6, + DA830_EMB_A_7, + DA830_EMB_A_8, + DA830_EMB_A_9, + DA830_EMB_A_10, + DA830_EMB_A_11, + DA830_EMB_A_12, + DA830_EMB_D_31, + DA830_GPIO7_8, + DA830_GPIO7_9, + DA830_GPIO7_10, + DA830_GPIO7_11, + DA830_GPIO7_12, + DA830_GPIO7_13, + DA830_GPIO3_13, + DA830_EMB_D_30, + DA830_EMB_D_29, + DA830_EMB_D_28, + DA830_EMB_D_27, + DA830_EMB_D_26, + DA830_EMB_D_25, + DA830_EMB_D_24, + DA830_EMB_D_23, + DA830_EMB_D_22, + DA830_EMB_D_21, + DA830_EMB_D_20, + DA830_EMB_D_19, + DA830_EMB_D_18, + DA830_EMB_D_17, + DA830_EMB_D_16, + DA830_NEMB_WE_DQM_3, + DA830_NEMB_WE_DQM_2, + DA830_EMB_D_0, + DA830_EMB_D_1, + DA830_EMB_D_2, + DA830_EMB_D_3, + DA830_EMB_D_4, + DA830_EMB_D_5, + DA830_EMB_D_6, + DA830_GPIO6_0, + DA830_GPIO6_1, + DA830_GPIO6_2, + DA830_GPIO6_3, + DA830_GPIO6_4, + DA830_GPIO6_5, + DA830_GPIO6_6, + DA830_EMB_D_7, + DA830_EMB_D_8, + DA830_EMB_D_9, + DA830_EMB_D_10, + DA830_EMB_D_11, + DA830_EMB_D_12, + DA830_EMB_D_13, + DA830_EMB_D_14, + DA830_GPIO6_7, + DA830_GPIO6_8, + DA830_GPIO6_9, + DA830_GPIO6_10, + DA830_GPIO6_11, + DA830_GPIO6_12, + DA830_GPIO6_13, + DA830_GPIO6_14, + DA830_EMB_D_15, + DA830_NEMB_WE_DQM_1, + DA830_NEMB_WE_DQM_0, + DA830_SPI0_SOMI_0, + DA830_SPI0_SIMO_0, + DA830_SPI0_CLK, + DA830_NSPI0_ENA, + DA830_NSPI0_SCS_0, + DA830_EQEP0I, + DA830_EQEP0S, + DA830_EQEP1I, + DA830_NUART0_CTS, + DA830_NUART0_RTS, + DA830_EQEP0A, + DA830_EQEP0B, + DA830_GPIO6_15, + DA830_GPIO5_14, + DA830_GPIO5_15, + DA830_GPIO5_0, + DA830_GPIO5_1, + DA830_GPIO5_2, + DA830_GPIO5_3, + DA830_GPIO5_4, + DA830_SPI1_SOMI_0, + DA830_SPI1_SIMO_0, + DA830_SPI1_CLK, + DA830_UART0_RXD, + DA830_UART0_TXD, + DA830_AXR1_10, + DA830_AXR1_11, + DA830_NSPI1_ENA, + DA830_I2C1_SCL, + DA830_I2C1_SDA, + DA830_EQEP1S, + DA830_I2C0_SDA, + DA830_I2C0_SCL, + DA830_UART2_RXD, + DA830_TM64P0_IN12, + DA830_TM64P0_OUT12, + DA830_GPIO5_5, + DA830_GPIO5_6, + DA830_GPIO5_7, + DA830_GPIO5_8, + DA830_GPIO5_9, + DA830_GPIO5_10, + DA830_GPIO5_11, + DA830_GPIO5_12, + DA830_NSPI1_SCS_0, + DA830_USB0_DRVVBUS, + DA830_AHCLKX0, + DA830_ACLKX0, + DA830_AFSX0, + DA830_AHCLKR0, + DA830_ACLKR0, + DA830_AFSR0, + DA830_UART2_TXD, + DA830_AHCLKX2, + DA830_ECAP0_APWM0, + DA830_RMII_MHZ_50_CLK, + DA830_ECAP1_APWM1, + DA830_USB_REFCLKIN, + DA830_GPIO5_13, + DA830_GPIO4_15, + DA830_GPIO2_11, + DA830_GPIO2_12, + DA830_GPIO2_13, + DA830_GPIO2_14, + DA830_GPIO2_15, + DA830_GPIO3_12, + DA830_AMUTE0, + DA830_AXR0_0, + DA830_AXR0_1, + DA830_AXR0_2, + DA830_AXR0_3, + DA830_AXR0_4, + DA830_AXR0_5, + DA830_AXR0_6, + DA830_RMII_TXD_0, + DA830_RMII_TXD_1, + DA830_RMII_TXEN, + DA830_RMII_CRS_DV, + DA830_RMII_RXD_0, + DA830_RMII_RXD_1, + DA830_RMII_RXER, + DA830_AFSR2, + DA830_ACLKX2, + DA830_AXR2_3, + DA830_AXR2_2, + DA830_AXR2_1, + DA830_AFSX2, + DA830_ACLKR2, + DA830_NRESETOUT, + DA830_GPIO3_0, + DA830_GPIO3_1, + DA830_GPIO3_2, + DA830_GPIO3_3, + DA830_GPIO3_4, + DA830_GPIO3_5, + DA830_GPIO3_6, + DA830_AXR0_7, + DA830_AXR0_8, + DA830_UART1_RXD, + DA830_UART1_TXD, + DA830_AXR0_11, + DA830_AHCLKX1, + DA830_ACLKX1, + DA830_AFSX1, + DA830_MDIO_CLK, + DA830_MDIO_D, + DA830_AXR0_9, + DA830_AXR0_10, + DA830_EPWM0B, + DA830_EPWM0A, + DA830_EPWMSYNCI, + DA830_AXR2_0, + DA830_EPWMSYNC0, + DA830_GPIO3_7, + DA830_GPIO3_8, + DA830_GPIO3_9, + DA830_GPIO3_10, + DA830_GPIO3_11, + DA830_GPIO3_14, + DA830_GPIO3_15, + DA830_GPIO4_10, + DA830_AHCLKR1, + DA830_ACLKR1, + DA830_AFSR1, + DA830_AMUTE1, + DA830_AXR1_0, + DA830_AXR1_1, + DA830_AXR1_2, + DA830_AXR1_3, + DA830_ECAP2_APWM2, + DA830_EHRPWMGLUETZ, + DA830_EQEP1A, + DA830_GPIO4_11, + DA830_GPIO4_12, + DA830_GPIO4_13, + DA830_GPIO4_14, + DA830_GPIO4_0, + DA830_GPIO4_1, + DA830_GPIO4_2, + DA830_GPIO4_3, + DA830_AXR1_4, + DA830_AXR1_5, + DA830_AXR1_6, + DA830_AXR1_7, + DA830_AXR1_8, + DA830_AXR1_9, + DA830_EMA_D_0, + DA830_EMA_D_1, + DA830_EQEP1B, + DA830_EPWM2B, + DA830_EPWM2A, + DA830_EPWM1B, + DA830_EPWM1A, + DA830_MMCSD_DAT_0, + DA830_MMCSD_DAT_1, + DA830_UHPI_HD_0, + DA830_UHPI_HD_1, + DA830_GPIO4_4, + DA830_GPIO4_5, + DA830_GPIO4_6, + DA830_GPIO4_7, + DA830_GPIO4_8, + DA830_GPIO4_9, + DA830_GPIO0_0, + DA830_GPIO0_1, + DA830_EMA_D_2, + DA830_EMA_D_3, + DA830_EMA_D_4, + DA830_EMA_D_5, + DA830_EMA_D_6, + DA830_EMA_D_7, + DA830_EMA_D_8, + DA830_EMA_D_9, + DA830_MMCSD_DAT_2, + DA830_MMCSD_DAT_3, + DA830_MMCSD_DAT_4, + DA830_MMCSD_DAT_5, + DA830_MMCSD_DAT_6, + DA830_MMCSD_DAT_7, + DA830_UHPI_HD_8, + DA830_UHPI_HD_9, + DA830_UHPI_HD_2, + DA830_UHPI_HD_3, + DA830_UHPI_HD_4, + DA830_UHPI_HD_5, + DA830_UHPI_HD_6, + DA830_UHPI_HD_7, + DA830_LCD_D_8, + DA830_LCD_D_9, + DA830_GPIO0_2, + DA830_GPIO0_3, + DA830_GPIO0_4, + DA830_GPIO0_5, + DA830_GPIO0_6, + DA830_GPIO0_7, + DA830_GPIO0_8, + DA830_GPIO0_9, + DA830_EMA_D_10, + DA830_EMA_D_11, + DA830_EMA_D_12, + DA830_EMA_D_13, + DA830_EMA_D_14, + DA830_EMA_D_15, + DA830_EMA_A_0, + DA830_EMA_A_1, + DA830_UHPI_HD_10, + DA830_UHPI_HD_11, + DA830_UHPI_HD_12, + DA830_UHPI_HD_13, + DA830_UHPI_HD_14, + DA830_UHPI_HD_15, + DA830_LCD_D_7, + DA830_MMCSD_CLK, + DA830_LCD_D_10, + DA830_LCD_D_11, + DA830_LCD_D_12, + DA830_LCD_D_13, + DA830_LCD_D_14, + DA830_LCD_D_15, + DA830_UHPI_HCNTL0, + DA830_GPIO0_10, + DA830_GPIO0_11, + DA830_GPIO0_12, + DA830_GPIO0_13, + DA830_GPIO0_14, + DA830_GPIO0_15, + DA830_GPIO1_0, + DA830_GPIO1_1, + DA830_EMA_A_2, + DA830_EMA_A_3, + DA830_EMA_A_4, + DA830_EMA_A_5, + DA830_EMA_A_6, + DA830_EMA_A_7, + DA830_EMA_A_8, + DA830_EMA_A_9, + DA830_MMCSD_CMD, + DA830_LCD_D_6, + DA830_LCD_D_3, + DA830_LCD_D_2, + DA830_LCD_D_1, + DA830_LCD_D_0, + DA830_LCD_PCLK, + DA830_LCD_HSYNC, + DA830_UHPI_HCNTL1, + DA830_GPIO1_2, + DA830_GPIO1_3, + DA830_GPIO1_4, + DA830_GPIO1_5, + DA830_GPIO1_6, + DA830_GPIO1_7, + DA830_GPIO1_8, + DA830_GPIO1_9, + DA830_EMA_A_10, + DA830_EMA_A_11, + DA830_EMA_A_12, + DA830_EMA_BA_1, + DA830_EMA_BA_0, + DA830_EMA_CLK, + DA830_EMA_SDCKE, + DA830_NEMA_CAS, + DA830_LCD_VSYNC, + DA830_NLCD_AC_ENB_CS, + DA830_LCD_MCLK, + DA830_LCD_D_5, + DA830_LCD_D_4, + DA830_OBSCLK, + DA830_NEMA_CS_4, + DA830_UHPI_HHWIL, + DA830_AHCLKR2, + DA830_GPIO1_10, + DA830_GPIO1_11, + DA830_GPIO1_12, + DA830_GPIO1_13, + DA830_GPIO1_14, + DA830_GPIO1_15, + DA830_GPIO2_0, + DA830_GPIO2_1, + DA830_NEMA_RAS, + DA830_NEMA_WE, + DA830_NEMA_CS_0, + DA830_NEMA_CS_2, + DA830_NEMA_CS_3, + DA830_NEMA_OE, + DA830_NEMA_WE_DQM_1, + DA830_NEMA_WE_DQM_0, + DA830_NEMA_CS_5, + DA830_UHPI_HRNW, + DA830_NUHPI_HAS, + DA830_NUHPI_HCS, + DA830_NUHPI_HDS1, + DA830_NUHPI_HDS2, + DA830_NUHPI_HINT, + DA830_AXR0_12, + DA830_AMUTE2, + DA830_AXR0_13, + DA830_AXR0_14, + DA830_AXR0_15, + DA830_GPIO2_2, + DA830_GPIO2_3, + DA830_GPIO2_4, + DA830_GPIO2_5, + DA830_GPIO2_6, + DA830_GPIO2_7, + DA830_GPIO2_8, + DA830_GPIO2_9, + DA830_EMA_WAIT_0, + DA830_NUHPI_HRDY, + DA830_GPIO2_10, +}; + +enum davinci_da850_index { + /* UART0 function */ + DA850_NUART0_CTS, + DA850_NUART0_RTS, + DA850_UART0_RXD, + DA850_UART0_TXD, + + /* UART1 function */ + DA850_NUART1_CTS, + DA850_NUART1_RTS, + DA850_UART1_RXD, + DA850_UART1_TXD, + + /* UART2 function */ + DA850_NUART2_CTS, + DA850_NUART2_RTS, + DA850_UART2_RXD, + DA850_UART2_TXD, + + /* I2C1 function */ + DA850_I2C1_SCL, + DA850_I2C1_SDA, + + /* I2C0 function */ + DA850_I2C0_SDA, + DA850_I2C0_SCL, + + /* EMAC function */ + DA850_MII_TXEN, + DA850_MII_TXCLK, + DA850_MII_COL, + DA850_MII_TXD_3, + DA850_MII_TXD_2, + DA850_MII_TXD_1, + DA850_MII_TXD_0, + DA850_MII_RXER, + DA850_MII_CRS, + DA850_MII_RXCLK, + DA850_MII_RXDV, + DA850_MII_RXD_3, + DA850_MII_RXD_2, + DA850_MII_RXD_1, + DA850_MII_RXD_0, + DA850_MDIO_CLK, + DA850_MDIO_D, + + /* McASP function */ + DA850_ACLKR, + DA850_ACLKX, + DA850_AFSR, + DA850_AFSX, + DA850_AHCLKR, + DA850_AHCLKX, + DA850_AMUTE, + DA850_AXR_15, + DA850_AXR_14, + DA850_AXR_13, + DA850_AXR_12, + DA850_AXR_11, + DA850_AXR_10, + DA850_AXR_9, + DA850_AXR_8, + DA850_AXR_7, + DA850_AXR_6, + DA850_AXR_5, + DA850_AXR_4, + DA850_AXR_3, + DA850_AXR_2, + DA850_AXR_1, + DA850_AXR_0, + + /* LCD function */ + DA850_LCD_D_7, + DA850_LCD_D_6, + DA850_LCD_D_5, + DA850_LCD_D_4, + DA850_LCD_D_3, + DA850_LCD_D_2, + DA850_LCD_D_1, + DA850_LCD_D_0, + DA850_LCD_D_15, + DA850_LCD_D_14, + DA850_LCD_D_13, + DA850_LCD_D_12, + DA850_LCD_D_11, + DA850_LCD_D_10, + DA850_LCD_D_9, + DA850_LCD_D_8, + DA850_LCD_PCLK, + DA850_LCD_HSYNC, + DA850_LCD_VSYNC, + DA850_NLCD_AC_ENB_CS, + + /* MMC/SD0 function */ + DA850_MMCSD0_DAT_0, + DA850_MMCSD0_DAT_1, + DA850_MMCSD0_DAT_2, + DA850_MMCSD0_DAT_3, + DA850_MMCSD0_CLK, + DA850_MMCSD0_CMD, + + /* EMIF2.5/EMIFA function */ + DA850_EMA_D_7, + DA850_EMA_D_6, + DA850_EMA_D_5, + DA850_EMA_D_4, + DA850_EMA_D_3, + DA850_EMA_D_2, + DA850_EMA_D_1, + DA850_EMA_D_0, + DA850_EMA_A_1, + DA850_EMA_A_2, + DA850_NEMA_CS_3, + DA850_NEMA_CS_4, + DA850_NEMA_WE, + DA850_NEMA_OE, + DA850_EMA_D_15, + DA850_EMA_D_14, + DA850_EMA_D_13, + DA850_EMA_D_12, + DA850_EMA_D_11, + DA850_EMA_D_10, + DA850_EMA_D_9, + DA850_EMA_D_8, + DA850_EMA_A_0, + DA850_EMA_A_3, + DA850_EMA_A_4, + DA850_EMA_A_5, + DA850_EMA_A_6, + DA850_EMA_A_7, + DA850_EMA_A_8, + DA850_EMA_A_9, + DA850_EMA_A_10, + DA850_EMA_A_11, + DA850_EMA_A_12, + DA850_EMA_A_13, + DA850_EMA_A_14, + DA850_EMA_A_15, + DA850_EMA_A_16, + DA850_EMA_A_17, + DA850_EMA_A_18, + DA850_EMA_A_19, + DA850_EMA_A_20, + DA850_EMA_A_21, + DA850_EMA_A_22, + DA850_EMA_A_23, + DA850_EMA_BA_1, + DA850_EMA_CLK, + DA850_EMA_WAIT_1, + DA850_NEMA_CS_2, + + /* GPIO function */ + DA850_GPIO2_15, + DA850_GPIO8_10, + DA850_GPIO4_0, + DA850_GPIO4_1, }; #ifdef CONFIG_DAVINCI_MUX diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index ab8a2586d1cc..171173c1dbad 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -81,6 +81,24 @@ #define DM355_LPSC_RTO 12 #define DM355_LPSC_VPSS_DAC 41 +/* DM365 */ +#define DM365_LPSC_TIMER3 5 +#define DM365_LPSC_SPI1 6 +#define DM365_LPSC_MMC_SD1 7 +#define DM365_LPSC_McBSP1 8 +#define DM365_LPSC_PWM3 10 +#define DM365_LPSC_SPI2 11 +#define DM365_LPSC_RTO 12 +#define DM365_LPSC_TIMER4 17 +#define DM365_LPSC_SPI0 22 +#define DM365_LPSC_SPI3 38 +#define DM365_LPSC_SPI4 39 +#define DM365_LPSC_EMAC 40 +#define DM365_LPSC_VOICE_CODEC 44 +#define DM365_LPSC_DAC_CLK 46 +#define DM365_LPSC_VPSSMSTR 47 +#define DM365_LPSC_MJCP 50 + /* * LPSC Assignments */ @@ -118,6 +136,50 @@ #define DM646X_LPSC_TIMER1 35 #define DM646X_LPSC_ARM_INTC 45 +/* PSC0 defines */ +#define DA8XX_LPSC0_TPCC 0 +#define DA8XX_LPSC0_TPTC0 1 +#define DA8XX_LPSC0_TPTC1 2 +#define DA8XX_LPSC0_EMIF25 3 +#define DA8XX_LPSC0_SPI0 4 +#define DA8XX_LPSC0_MMC_SD 5 +#define DA8XX_LPSC0_AINTC 6 +#define DA8XX_LPSC0_ARM_RAM_ROM 7 +#define DA8XX_LPSC0_SECU_MGR 8 +#define DA8XX_LPSC0_UART0 9 +#define DA8XX_LPSC0_SCR0_SS 10 +#define DA8XX_LPSC0_SCR1_SS 11 +#define DA8XX_LPSC0_SCR2_SS 12 +#define DA8XX_LPSC0_DMAX 13 +#define DA8XX_LPSC0_ARM 14 +#define DA8XX_LPSC0_GEM 15 + +/* PSC1 defines */ +#define DA850_LPSC1_TPCC1 0 +#define DA8XX_LPSC1_USB20 1 +#define DA8XX_LPSC1_USB11 2 +#define DA8XX_LPSC1_GPIO 3 +#define DA8XX_LPSC1_UHPI 4 +#define DA8XX_LPSC1_CPGMAC 5 +#define DA8XX_LPSC1_EMIF3C 6 +#define DA8XX_LPSC1_McASP0 7 +#define DA830_LPSC1_McASP1 8 +#define DA850_LPSC1_SATA 8 +#define DA830_LPSC1_McASP2 9 +#define DA8XX_LPSC1_SPI1 10 +#define DA8XX_LPSC1_I2C 11 +#define DA8XX_LPSC1_UART1 12 +#define DA8XX_LPSC1_UART2 13 +#define DA8XX_LPSC1_LCDC 16 +#define DA8XX_LPSC1_PWM 17 +#define DA8XX_LPSC1_ECAP 20 +#define DA830_LPSC1_EQEP 21 +#define DA850_LPSC1_TPTC2 21 +#define DA8XX_LPSC1_SCR_P0_SS 24 +#define DA8XX_LPSC1_SCR_P1_SS 25 +#define DA8XX_LPSC1_CR_P3_SS 26 +#define DA8XX_LPSC1_L3_CBA_RAM 31 + extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, char enable); diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 794fa5cf93c1..a584697a9e70 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -11,13 +11,17 @@ #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H -#include <mach/io.h> +#include <mach/hardware.h> #define DAVINCI_MAX_NR_UARTS 3 #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) +#define DA8XX_UART0_BASE (IO_PHYS + 0x042000) +#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) +#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) + /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c #define UART_DM646X_SCR 0x10 diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h index b7e7036674fa..8e4f10fe1263 100644 --- a/arch/arm/mach-davinci/include/mach/system.h +++ b/arch/arm/mach-davinci/include/mach/system.h @@ -16,12 +16,12 @@ extern void davinci_watchdog_reset(void); -static void arch_idle(void) +static inline void arch_idle(void) { cpu_do_idle(); } -static void arch_reset(char mode, const char *cmd) +static inline void arch_reset(char mode, const char *cmd) { davinci_watchdog_reset(); } diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 1e27475f9a23..33796b4db17f 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -21,8 +21,11 @@ static u32 *uart; static u32 *get_uart_base(void) { - /* Add logic here for new platforms, using __macine_arch_type */ - return (u32 *)DAVINCI_UART0_BASE; + if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM || + __machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) + return (u32 *)DA8XX_UART2_BASE; + else + return (u32 *)DAVINCI_UART0_BASE; } /* PORT_16C550A, in polled non-fifo mode */ diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h index ad51625b6609..d49646a8e206 100644 --- a/arch/arm/mach-davinci/include/mach/vmalloc.h +++ b/arch/arm/mach-davinci/include/mach/vmalloc.h @@ -8,7 +8,7 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ -#include <mach/io.h> +#include <mach/hardware.h> /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ #define VMALLOC_END (IO_VIRT - (2<<20)) diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c index d310f579aa85..898905e48946 100644 --- a/arch/arm/mach-davinci/mux.c +++ b/arch/arm/mach-davinci/mux.c @@ -91,3 +91,17 @@ int __init_or_module davinci_cfg_reg(const unsigned long index) return 0; } EXPORT_SYMBOL(davinci_cfg_reg); + +int da8xx_pinmux_setup(const short pins[]) +{ + int i, error = -EINVAL; + + if (pins) + for (i = 0; pins[i] >= 0; i++) { + error = davinci_cfg_reg(pins[i]); + if (error) + break; + } + + return error; +} diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c index db54b2a66b4d..4f1fc9b318b3 100644 --- a/arch/arm/mach-davinci/sram.c +++ b/arch/arm/mach-davinci/sram.c @@ -60,7 +60,7 @@ static int __init sram_init(void) int status = 0; if (len) { - len = min(len, SRAM_SIZE); + len = min_t(unsigned, len, SRAM_SIZE); sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1); if (!sram_pool) status = -ENOMEM; diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 0884ca57bfb0..0d1b6d407b46 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -406,11 +406,11 @@ struct sys_timer davinci_timer = { void davinci_watchdog_reset(void) { u32 tgcr, wdtcr; - struct davinci_soc_info *soc_info = &davinci_soc_info; - void __iomem *base = soc_info->wdt_base; + struct platform_device *pdev = &davinci_wdt_device; + void __iomem *base = IO_ADDRESS(pdev->resource[0].start); struct clk *wd_clk; - wd_clk = clk_get(&davinci_wdt_device.dev, NULL); + wd_clk = clk_get(&pdev->dev, NULL); if (WARN_ON(IS_ERR(wd_clk))) return; clk_enable(wd_clk); @@ -420,11 +420,11 @@ void davinci_watchdog_reset(void) /* reset timer, set mode to 64-bit watchdog, and unreset */ tgcr = 0; - __raw_writel(tgcr, base + TCR); + __raw_writel(tgcr, base + TGCR); tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - __raw_writel(tgcr, base + TCR); + __raw_writel(tgcr, base + TGCR); /* clear counter and period regs */ __raw_writel(0, base + TIM12); @@ -432,12 +432,8 @@ void davinci_watchdog_reset(void) __raw_writel(0, base + PRD12); __raw_writel(0, base + PRD34); - /* enable */ - wdtcr = __raw_readl(base + WDTCR); - wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; - __raw_writel(wdtcr, base + WDTCR); - /* put watchdog in pre-active state */ + wdtcr = __raw_readl(base + WDTCR); wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); __raw_writel(wdtcr, base + WDTCR); diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index abedb6337182..06f55931620c 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c @@ -13,6 +13,7 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/irqs.h> +#include <mach/cputype.h> #define DAVINCI_USB_OTG_BASE 0x01C64000 @@ -64,6 +65,10 @@ static struct resource usb_resources[] = { .start = IRQ_USBINT, .flags = IORESOURCE_IRQ, }, + { + /* placeholder for the dedicated CPPI IRQ */ + .flags = IORESOURCE_IRQ, + }, }; static u64 usb_dmamask = DMA_BIT_MASK(32); @@ -84,6 +89,14 @@ void __init setup_usb(unsigned mA, unsigned potpgt_msec) { usb_data.power = mA / 2; usb_data.potpgt = potpgt_msec / 2; + + if (cpu_is_davinci_dm646x()) { + /* Override the defaults as DM6467 uses different IRQs. */ + usb_dev.resource[1].start = IRQ_DM646X_USBINT; + usb_dev.resource[2].start = IRQ_DM646X_USBDMAINT; + } else /* other devices don't have dedicated CPPI IRQ */ + usb_dev.num_resources = 2; + platform_device_register(&usb_dev); } diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 8b40aace9db4..42920f9c1a11 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -15,8 +15,11 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/input.h> +#include <linux/interrupt.h> #include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <asm/serial.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -162,10 +165,6 @@ static struct omap_lcd_config ams_delta_lcd_config __initdata = { .ctrl_name = "internal", }; -static struct omap_uart_config ams_delta_uart_config __initdata = { - .enabled_uarts = 1, -}; - static struct omap_usb_config ams_delta_usb_config __initdata = { .register_host = 1, .hmc_mode = 16, @@ -174,7 +173,6 @@ static struct omap_usb_config ams_delta_usb_config __initdata = { static struct omap_board_config_kernel ams_delta_config[] = { { OMAP_TAG_LCD, &ams_delta_lcd_config }, - { OMAP_TAG_UART, &ams_delta_uart_config }, }; static struct resource ams_delta_kp_resources[] = { @@ -235,6 +233,41 @@ static void __init ams_delta_init(void) platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); } +static struct plat_serial8250_port ams_delta_modem_ports[] = { + { + .membase = (void *) AMS_DELTA_MODEM_VIRT, + .mapbase = AMS_DELTA_MODEM_PHYS, + .irq = -EINVAL, /* changed later */ + .flags = UPF_BOOT_AUTOCONF, + .irqflags = IRQF_TRIGGER_RISING, + .iotype = UPIO_MEM, + .regshift = 1, + .uartclk = BASE_BAUD * 16, + }, + { }, +}; + +static struct platform_device ams_delta_modem_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = ams_delta_modem_ports, + }, +}; + +static int __init ams_delta_modem_init(void) +{ + omap_cfg_reg(M14_1510_GPIO2); + ams_delta_modem_ports[0].irq = gpio_to_irq(2); + + ams_delta_latch2_write( + AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC, + AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC); + + return platform_device_register(&ams_delta_modem_device); +} +arch_initcall(ams_delta_modem_init); + static void __init ams_delta_map_io(void) { omap1_map_common_io(); diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 19e0e9232336..a7ead1b93226 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -240,16 +240,11 @@ static int nand_dev_ready(struct omap_nand_platform_data *data) return gpio_get_value(P2_NAND_RB_GPIO_PIN); } -static struct omap_uart_config fsample_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1)), -}; - static struct omap_lcd_config fsample_lcd_config __initdata = { .ctrl_name = "internal", }; static struct omap_board_config_kernel fsample_config[] = { - { OMAP_TAG_UART, &fsample_uart_config }, { OMAP_TAG_LCD, &fsample_lcd_config }, }; diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index e724940e86f2..fb47239da72f 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -57,12 +57,7 @@ static struct omap_usb_config generic1610_usb_config __initdata = { }; #endif -static struct omap_uart_config generic_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct omap_board_config_kernel generic_config[] __initdata = { - { OMAP_TAG_UART, &generic_uart_config }, }; static void __init omap_generic_init(void) diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index f695aa053ac8..aab860307dca 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -360,16 +360,11 @@ static struct omap_usb_config h2_usb_config __initdata = { .pins[1] = 3, }; -static struct omap_uart_config h2_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct omap_lcd_config h2_lcd_config __initdata = { .ctrl_name = "internal", }; static struct omap_board_config_kernel h2_config[] __initdata = { - { OMAP_TAG_UART, &h2_uart_config }, { OMAP_TAG_LCD, &h2_lcd_config }, }; diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index f597968733b4..89586b80b8d5 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -313,16 +313,11 @@ static struct omap_usb_config h3_usb_config __initdata = { .pins[1] = 3, }; -static struct omap_uart_config h3_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct omap_lcd_config h3_lcd_config __initdata = { .ctrl_name = "internal", }; static struct omap_board_config_kernel h3_config[] __initdata = { - { OMAP_TAG_UART, &h3_uart_config }, { OMAP_TAG_LCD, &h3_lcd_config }, }; diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 2fd98260ea49..cc2abbb2d0f4 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -368,13 +368,8 @@ static inline void innovator_mmc_init(void) } #endif -static struct omap_uart_config innovator_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct omap_board_config_kernel innovator_config[] = { { OMAP_TAG_LCD, NULL }, - { OMAP_TAG_UART, &innovator_uart_config }, }; static void __init innovator_init(void) diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index cf3247b15f87..ed891b8a6b15 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -293,10 +293,6 @@ static struct omap_usb_config osk_usb_config __initdata = { .pins[0] = 2, }; -static struct omap_uart_config osk_uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - #ifdef CONFIG_OMAP_OSK_MISTRAL static struct omap_lcd_config osk_lcd_config __initdata = { .ctrl_name = "internal", @@ -304,7 +300,6 @@ static struct omap_lcd_config osk_lcd_config __initdata = { #endif static struct omap_board_config_kernel osk_config[] __initdata = { - { OMAP_TAG_UART, &osk_uart_config }, #ifdef CONFIG_OMAP_OSK_MISTRAL { OMAP_TAG_LCD, &osk_lcd_config }, #endif diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 886b4c0569bd..90dd0431b0dc 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -212,10 +212,6 @@ static struct omap_lcd_config palmte_lcd_config __initdata = { .ctrl_name = "internal", }; -static struct omap_uart_config palmte_uart_config __initdata = { - .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), -}; - #ifdef CONFIG_APM /* * Values measured in 10 minute intervals averaged over 10 samples. @@ -302,7 +298,6 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery) static struct omap_board_config_kernel palmte_config[] __initdata = { { OMAP_TAG_LCD, &palmte_lcd_config }, - { OMAP_TAG_UART, &palmte_uart_config }, }; static struct spi_board_info palmte_spi_info[] __initdata = { diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 4f1b44831d37..8256139891ff 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -274,13 +274,8 @@ static struct omap_lcd_config palmtt_lcd_config __initdata = { .ctrl_name = "internal", }; -static struct omap_uart_config palmtt_uart_config __initdata = { - .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), -}; - static struct omap_board_config_kernel palmtt_config[] __initdata = { { OMAP_TAG_LCD, &palmtt_lcd_config }, - { OMAP_TAG_UART, &palmtt_uart_config }, }; static void __init omap_mpu_wdt_mode(int mode) { diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 9a55c3c58218..81b6bde1c5a3 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -244,13 +244,8 @@ static struct omap_lcd_config palmz71_lcd_config __initdata = { .ctrl_name = "internal", }; -static struct omap_uart_config palmz71_uart_config __initdata = { - .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), -}; - static struct omap_board_config_kernel palmz71_config[] __initdata = { {OMAP_TAG_LCD, &palmz71_lcd_config}, - {OMAP_TAG_UART, &palmz71_uart_config}, }; static irqreturn_t diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 3b9f907aa899..83406699f310 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -208,16 +208,11 @@ static int nand_dev_ready(struct omap_nand_platform_data *data) return gpio_get_value(P2_NAND_RB_GPIO_PIN); } -static struct omap_uart_config perseus2_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1)), -}; - static struct omap_lcd_config perseus2_lcd_config __initdata = { .ctrl_name = "internal", }; static struct omap_board_config_kernel perseus2_config[] __initdata = { - { OMAP_TAG_UART, &perseus2_uart_config }, { OMAP_TAG_LCD, &perseus2_lcd_config }, }; diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index c096577695fe..02c85ca2e1df 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -369,13 +369,8 @@ static struct platform_device *sx1_devices[] __initdata = { }; /*-----------------------------------------*/ -static struct omap_uart_config sx1_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct omap_board_config_kernel sx1_config[] __initdata = { { OMAP_TAG_LCD, &sx1_lcd_config }, - { OMAP_TAG_UART, &sx1_uart_config }, }; /*-----------------------------------------*/ diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 98275e03dad1..c06e7a553472 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -140,12 +140,7 @@ static struct omap_usb_config voiceblue_usb_config __initdata = { .pins[2] = 6, }; -static struct omap_uart_config voiceblue_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct omap_board_config_kernel voiceblue_config[] = { - { OMAP_TAG_UART, &voiceblue_uart_config }, }; static void __init voiceblue_init_irq(void) diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index bbbaeb0abcd3..06808434ea04 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -71,7 +71,7 @@ static inline void omap_init_rtc(void) {} # define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1 #endif -#define OMAP1_MBOX_BASE IO_ADDRESS(OMAP16XX_MAILBOX_BASE) +#define OMAP1_MBOX_BASE OMAP1_IO_ADDRESS(OMAP16XX_MAILBOX_BASE) static struct resource mbox_resources[] = { { diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 3afe540149f7..7030f9281ea1 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -29,9 +29,9 @@ extern void omapfb_reserve_sdram(void); */ static struct map_desc omap_io_desc[] __initdata = { { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, + .virtual = OMAP1_IO_VIRT, + .pfn = __phys_to_pfn(OMAP1_IO_PHYS), + .length = OMAP1_IO_SIZE, .type = MT_DEVICE } }; diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h index 9ed5e2c1de4d..c4f05bdcf8a6 100644 --- a/arch/arm/mach-omap1/pm.h +++ b/arch/arm/mach-omap1/pm.h @@ -39,11 +39,11 @@ * Register and offset definitions to be used in PM assembler code * ---------------------------------------------------------------------------- */ -#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00) +#define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00) #define ARM_IDLECT1_ASM_OFFSET 0x04 #define ARM_IDLECT2_ASM_OFFSET 0x08 -#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00) +#define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00) #define EMIFS_CONFIG_ASM_OFFSET 0x0c #define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index f754cee4f3c3..d496e50fec40 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -64,7 +64,7 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p) static struct plat_serial8250_port serial_platform_data[] = { { - .membase = IO_ADDRESS(OMAP_UART1_BASE), + .membase = OMAP1_IO_ADDRESS(OMAP_UART1_BASE), .mapbase = OMAP_UART1_BASE, .irq = INT_UART1, .flags = UPF_BOOT_AUTOCONF, @@ -73,7 +73,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .uartclk = OMAP16XX_BASE_BAUD * 16, }, { - .membase = IO_ADDRESS(OMAP_UART2_BASE), + .membase = OMAP1_IO_ADDRESS(OMAP_UART2_BASE), .mapbase = OMAP_UART2_BASE, .irq = INT_UART2, .flags = UPF_BOOT_AUTOCONF, @@ -82,7 +82,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .uartclk = OMAP16XX_BASE_BAUD * 16, }, { - .membase = IO_ADDRESS(OMAP_UART3_BASE), + .membase = OMAP1_IO_ADDRESS(OMAP_UART3_BASE), .mapbase = OMAP_UART3_BASE, .irq = INT_UART3, .flags = UPF_BOOT_AUTOCONF, @@ -109,7 +109,6 @@ static struct platform_device serial_device = { void __init omap_serial_init(void) { int i; - const struct omap_uart_config *info; if (cpu_is_omap730()) { serial_platform_data[0].regshift = 0; @@ -131,19 +130,9 @@ void __init omap_serial_init(void) serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16; } - info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config); - if (info == NULL) - return; - for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { unsigned char reg; - if (!((1 << i) & info->enabled_uarts)) { - serial_platform_data[i].membase = NULL; - serial_platform_data[i].mapbase = 0; - continue; - } - switch (i) { case 0: uart1_ck = clk_get(NULL, "uart1_ck"); diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S index 261cdc48228b..7724e520d07c 100644 --- a/arch/arm/mach-omap1/sram.S +++ b/arch/arm/mach-omap1/sram.S @@ -21,13 +21,13 @@ ENTRY(omap1_sram_reprogram_clock) stmfd sp!, {r0 - r12, lr} @ save registers on stack - mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000 - orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x00ff0000 - orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x0000ff00 + mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000 + orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000 + orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00 - mov r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000 - orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 - orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 + mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000 + orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 + orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 tst r0, #1 << 4 @ want lock mode? beq newck @ nope diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 4d56408d3cff..1be6a214d88d 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -62,8 +62,8 @@ typedef struct { u32 read_tim; /* READ_TIM, R */ } omap_mpu_timer_regs_t; -#define omap_mpu_timer_base(n) \ -((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ +#define omap_mpu_timer_base(n) \ +((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ (n)*OMAP_MPU_TIMER_OFFSET)) static inline unsigned long omap_mpu_timer_read(int nr) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index a755eb5e2361..75b1c7efae7e 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -31,6 +31,11 @@ config MACH_OMAP_GENERIC bool "Generic OMAP board" depends on ARCH_OMAP2 && ARCH_OMAP24XX +config MACH_OMAP2_TUSB6010 + bool + depends on ARCH_OMAP2 && ARCH_OMAP2420 + default y if MACH_NOKIA_N8X0 + config MACH_OMAP_H4 bool "OMAP 2420 H4 board" depends on ARCH_OMAP2 && ARCH_OMAP24XX @@ -68,6 +73,10 @@ config MACH_OMAP_3430SDP bool "OMAP 3430 SDP board" depends on ARCH_OMAP3 && ARCH_OMAP34XX +config MACH_NOKIA_N8X0 + bool "Nokia N800/N810" + depends on ARCH_OMAP2420 + config MACH_NOKIA_RX51 bool "Nokia RX-51 board" depends on ARCH_OMAP3 && ARCH_OMAP34XX diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 735bae5b0dec..8cb16777661a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -5,7 +5,7 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o -omap-2-3-common = irq.o sdrc.o +omap-2-3-common = irq.o sdrc.o omap_hwmod.o prcm-common = prcm.o powerdomain.o clock-common = clock.o clockdomain.o @@ -35,6 +35,11 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o endif +# PRCM +obj-$(CONFIG_ARCH_OMAP2) += cm.o +obj-$(CONFIG_ARCH_OMAP3) += cm.o +obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o + # Clock framework obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o @@ -62,7 +67,7 @@ obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ mmc-twl4030.o obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ mmc-twl4030.o - +obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ board-rx51-peripherals.o \ mmc-twl4030.o @@ -74,6 +79,7 @@ obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o # Platform specific device init code obj-y += usb-musb.o +obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o obj-y += $(onenand-m) $(onenand-y) diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 8ec2a132904d..42217b32f835 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -139,23 +139,19 @@ static inline void board_smc91x_init(void) #endif +static struct omap_board_config_kernel sdp2430_config[] = { + {OMAP_TAG_LCD, &sdp2430_lcd_config}, +}; + static void __init omap_2430sdp_init_irq(void) { + omap_board_config = sdp2430_config; + omap_board_config_size = ARRAY_SIZE(sdp2430_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); omap_gpio_init(); } -static struct omap_uart_config sdp2430_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - -static struct omap_board_config_kernel sdp2430_config[] = { - {OMAP_TAG_UART, &sdp2430_uart_config}, - {OMAP_TAG_LCD, &sdp2430_lcd_config}, -}; - - static struct twl4030_gpio_platform_data sdp2430_gpio_data = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, @@ -205,8 +201,6 @@ static void __init omap_2430sdp_init(void) omap2430_i2c_init(); platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); - omap_board_config = sdp2430_config; - omap_board_config_size = ARRAY_SIZE(sdp2430_config); omap_serial_init(); twl4030_mmc_init(mmc); usb_musb_init(); diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index ac262cd74503..bd57ec76dc5e 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -167,26 +167,23 @@ static struct platform_device *sdp3430_devices[] __initdata = { &sdp3430_lcd_device, }; -static void __init omap_3430sdp_init_irq(void) -{ - omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL); - omap_init_irq(); - omap_gpio_init(); -} - -static struct omap_uart_config sdp3430_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct omap_lcd_config sdp3430_lcd_config __initdata = { .ctrl_name = "internal", }; static struct omap_board_config_kernel sdp3430_config[] __initdata = { - { OMAP_TAG_UART, &sdp3430_uart_config }, { OMAP_TAG_LCD, &sdp3430_lcd_config }, }; +static void __init omap_3430sdp_init_irq(void) +{ + omap_board_config = sdp3430_config; + omap_board_config_size = ARRAY_SIZE(sdp3430_config); + omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL); + omap_init_irq(); + omap_gpio_init(); +} + static int sdp3430_batt_table[] = { /* 0 C*/ 30800, 29500, 28300, 27100, @@ -478,12 +475,15 @@ static inline void board_smc91x_init(void) #endif +static void enable_board_wakeup_source(void) +{ + omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */ +} + static void __init omap_3430sdp_init(void) { omap3430_i2c_init(); platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); - omap_board_config = sdp3430_config; - omap_board_config_size = ARRAY_SIZE(sdp3430_config); if (omap_rev() > OMAP3430_REV_ES1_0) ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2; else @@ -495,6 +495,7 @@ static void __init omap_3430sdp_init(void) omap_serial_init(); usb_musb_init(); board_smc91x_init(); + enable_board_wakeup_source(); } static void __init omap_3430sdp_map_io(void) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 1b223076ceb7..eb37c40ea83a 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -47,14 +47,13 @@ static struct omap_lcd_config sdp4430_lcd_config __initdata = { }; static struct omap_board_config_kernel sdp4430_config[] __initdata = { - { OMAP_TAG_UART, &sdp4430_uart_config }, { OMAP_TAG_LCD, &sdp4430_lcd_config }, }; static void __init gic_init_irq(void) { - gic_dist_init(0, IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29); - gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); + gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29); + gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); } static void __init omap_4430sdp_init_irq(void) diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index dcfc20d03894..7a2b54c7291a 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -248,18 +248,6 @@ out: clk_put(gpmc_fck); } -static void __init omap_apollon_init_irq(void) -{ - omap2_init_common_hw(NULL, NULL); - omap_init_irq(); - omap_gpio_init(); - apollon_init_smc91x(); -} - -static struct omap_uart_config apollon_uart_config __initdata = { - .enabled_uarts = (1 << 0) | (0 << 1) | (0 << 2), -}; - static struct omap_usb_config apollon_usb_config __initdata = { .register_dev = 1, .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */ @@ -272,10 +260,19 @@ static struct omap_lcd_config apollon_lcd_config __initdata = { }; static struct omap_board_config_kernel apollon_config[] = { - { OMAP_TAG_UART, &apollon_uart_config }, { OMAP_TAG_LCD, &apollon_lcd_config }, }; +static void __init omap_apollon_init_irq(void) +{ + omap_board_config = apollon_config; + omap_board_config_size = ARRAY_SIZE(apollon_config); + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); + apollon_init_smc91x(); +} + static void __init apollon_led_init(void) { /* LED0 - AA10 */ @@ -324,8 +321,6 @@ static void __init omap_apollon_init(void) * if not needed. */ platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices)); - omap_board_config = apollon_config; - omap_board_config_size = ARRAY_SIZE(apollon_config); omap_serial_init(); } diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index fd00aa03690c..2e09a1c444cb 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -31,24 +31,19 @@ #include <mach/board.h> #include <mach/common.h> +static struct omap_board_config_kernel generic_config[] = { +}; + static void __init omap_generic_init_irq(void) { + omap_board_config = generic_config; + omap_board_config_size = ARRAY_SIZE(generic_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); } -static struct omap_uart_config generic_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - -static struct omap_board_config_kernel generic_config[] = { - { OMAP_TAG_UART, &generic_uart_config }, -}; - static void __init omap_generic_init(void) { - omap_board_config = generic_config; - omap_board_config_size = ARRAY_SIZE(generic_config); omap_serial_init(); } diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 7b1d61d5bb2c..eaa02d012c5c 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -268,18 +268,6 @@ static void __init h4_init_flash(void) h4_flash_resource.end = base + SZ_64M - 1; } -static void __init omap_h4_init_irq(void) -{ - omap2_init_common_hw(NULL, NULL); - omap_init_irq(); - omap_gpio_init(); - h4_init_flash(); -} - -static struct omap_uart_config h4_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct omap_lcd_config h4_lcd_config __initdata = { .ctrl_name = "internal", }; @@ -318,10 +306,19 @@ static struct omap_usb_config h4_usb_config __initdata = { }; static struct omap_board_config_kernel h4_config[] = { - { OMAP_TAG_UART, &h4_uart_config }, { OMAP_TAG_LCD, &h4_lcd_config }, }; +static void __init omap_h4_init_irq(void) +{ + omap_board_config = h4_config; + omap_board_config_size = ARRAY_SIZE(h4_config); + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); + h4_init_flash(); +} + static struct at24_platform_data m24c01 = { .byte_len = SZ_1K / 8, .page_size = 16, @@ -366,8 +363,6 @@ static void __init omap_h4_init(void) ARRAY_SIZE(h4_i2c_board_info)); platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); - omap_board_config = h4_config; - omap_board_config_size = ARRAY_SIZE(h4_config); omap_usb_init(&h4_usb_config); omap_serial_init(); } diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index ea383f88cb1b..ec6854cbdd9f 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -268,18 +268,6 @@ static inline void __init ldp_init_smsc911x(void) gpio_direction_input(eth_gpio); } -static void __init omap_ldp_init_irq(void) -{ - omap2_init_common_hw(NULL, NULL); - omap_init_irq(); - omap_gpio_init(); - ldp_init_smsc911x(); -} - -static struct omap_uart_config ldp_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct platform_device ldp_lcd_device = { .name = "ldp_lcd", .id = -1, @@ -290,10 +278,19 @@ static struct omap_lcd_config ldp_lcd_config __initdata = { }; static struct omap_board_config_kernel ldp_config[] __initdata = { - { OMAP_TAG_UART, &ldp_uart_config }, { OMAP_TAG_LCD, &ldp_lcd_config }, }; +static void __init omap_ldp_init_irq(void) +{ + omap_board_config = ldp_config; + omap_board_config_size = ARRAY_SIZE(ldp_config); + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); + ldp_init_smsc911x(); +} + static struct twl4030_usb_data ldp_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; @@ -377,8 +374,6 @@ static void __init omap_ldp_init(void) { omap_i2c_init(); platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); - omap_board_config = ldp_config; - omap_board_config_size = ARRAY_SIZE(ldp_config); ts_gpio = 54; ldp_spi_board_info[0].irq = gpio_to_irq(ts_gpio); spi_register_board_info(ldp_spi_board_info, diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c new file mode 100644 index 000000000000..8341632d260b --- /dev/null +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -0,0 +1,150 @@ +/* + * linux/arch/arm/mach-omap2/board-n8x0.c + * + * Copyright (C) 2005-2009 Nokia Corporation + * Author: Juha Yrjola <juha.yrjola@nokia.com> + * + * Modified from mach-omap2/board-generic.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/stddef.h> +#include <linux/spi/spi.h> +#include <linux/usb/musb.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <mach/board.h> +#include <mach/common.h> +#include <mach/irqs.h> +#include <mach/mcspi.h> +#include <mach/onenand.h> +#include <mach/serial.h> + +static struct omap2_mcspi_device_config p54spi_mcspi_config = { + .turbo_mode = 0, + .single_channel = 1, +}; + +static struct spi_board_info n800_spi_board_info[] __initdata = { + { + .modalias = "p54spi", + .bus_num = 2, + .chip_select = 0, + .max_speed_hz = 48000000, + .controller_data = &p54spi_mcspi_config, + }, +}; + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) + +static struct mtd_partition onenand_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x20000, + .mask_flags = MTD_WRITEABLE, /* Force read-only */ + }, + { + .name = "config", + .offset = MTDPART_OFS_APPEND, + .size = 0x60000, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 0x200000, + }, + { + .name = "initfs", + .offset = MTDPART_OFS_APPEND, + .size = 0x400000, + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct omap_onenand_platform_data board_onenand_data = { + .cs = 0, + .gpio_irq = 26, + .parts = onenand_partitions, + .nr_parts = ARRAY_SIZE(onenand_partitions), + .flags = ONENAND_SYNC_READ, +}; + +static void __init n8x0_onenand_init(void) +{ + gpmc_onenand_init(&board_onenand_data); +} + +#else + +static void __init n8x0_onenand_init(void) {} + +#endif + +static void __init n8x0_map_io(void) +{ + omap2_set_globals_242x(); + omap2_map_common_io(); +} + +static void __init n8x0_init_irq(void) +{ + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); +} + +static void __init n8x0_init_machine(void) +{ + /* FIXME: add n810 spi devices */ + spi_register_board_info(n800_spi_board_info, + ARRAY_SIZE(n800_spi_board_info)); + + omap_serial_init(); + n8x0_onenand_init(); +} + +MACHINE_START(NOKIA_N800, "Nokia N800") + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = n8x0_map_io, + .init_irq = n8x0_init_irq, + .init_machine = n8x0_init_machine, + .timer = &omap_timer, +MACHINE_END + +MACHINE_START(NOKIA_N810, "Nokia N810") + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = n8x0_map_io, + .init_irq = n8x0_init_irq, + .init_machine = n8x0_init_machine, + .timer = &omap_timer, +MACHINE_END + +MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = n8x0_map_io, + .init_irq = n8x0_init_irq, + .init_machine = n8x0_init_machine, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index e00ba128cece..500c9956876d 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -108,10 +108,6 @@ static struct platform_device omap3beagle_nand_device = { #include "sdram-micron-mt46h32m32lf-6.h" -static struct omap_uart_config omap3_beagle_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct twl4030_hsmmc_info mmc[] = { { .mmc = 1, @@ -249,11 +245,16 @@ static struct regulator_init_data beagle_vpll2 = { .consumer_supplies = &beagle_vdvi_supply, }; +static struct twl4030_usb_data beagle_usb_data = { + .usb_mode = T2_USB_MODE_ULPI, +}; + static struct twl4030_platform_data beagle_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, /* platform_data for children goes here */ + .usb = &beagle_usb_data, .gpio = &beagle_gpio_data, .vmmc1 = &beagle_vmmc1, .vsim = &beagle_vsim, @@ -280,17 +281,6 @@ static int __init omap3_beagle_i2c_init(void) return 0; } -static void __init omap3_beagle_init_irq(void) -{ - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - omap_init_irq(); -#ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(12); -#endif - omap_gpio_init(); -} - static struct gpio_led gpio_leds[] = { { .name = "beagleboard::usr0", @@ -345,10 +335,22 @@ static struct platform_device keys_gpio = { }; static struct omap_board_config_kernel omap3_beagle_config[] __initdata = { - { OMAP_TAG_UART, &omap3_beagle_uart_config }, { OMAP_TAG_LCD, &omap3_beagle_lcd_config }, }; +static void __init omap3_beagle_init_irq(void) +{ + omap_board_config = omap3_beagle_config; + omap_board_config_size = ARRAY_SIZE(omap3_beagle_config); + omap2_init_common_hw(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); + omap_init_irq(); +#ifdef CONFIG_OMAP_32K_TIMER + omap2_gp_clockevent_set_gptimer(12); +#endif + omap_gpio_init(); +} + static struct platform_device *omap3_beagle_devices[] __initdata = { &omap3_beagle_lcd_device, &leds_gpio, @@ -398,8 +400,6 @@ static void __init omap3_beagle_init(void) omap3_beagle_i2c_init(); platform_add_devices(omap3_beagle_devices, ARRAY_SIZE(omap3_beagle_devices)); - omap_board_config = omap3_beagle_config; - omap_board_config_size = ARRAY_SIZE(omap3_beagle_config); omap_serial_init(); omap_cfg_reg(J25_34XX_GPIO170); diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index c4b144647dc5..d50b9be90580 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -92,10 +92,6 @@ static inline void __init omap3evm_init_smc911x(void) gpio_direction_input(OMAP3EVM_ETHR_GPIO_IRQ); } -static struct omap_uart_config omap3_evm_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct twl4030_hsmmc_info mmc[] = { { .mmc = 1, @@ -278,19 +274,20 @@ struct spi_board_info omap3evm_spi_board_info[] = { }, }; +static struct omap_board_config_kernel omap3_evm_config[] __initdata = { + { OMAP_TAG_LCD, &omap3_evm_lcd_config }, +}; + static void __init omap3_evm_init_irq(void) { + omap_board_config = omap3_evm_config; + omap_board_config_size = ARRAY_SIZE(omap3_evm_config); omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL); omap_init_irq(); omap_gpio_init(); omap3evm_init_smc911x(); } -static struct omap_board_config_kernel omap3_evm_config[] __initdata = { - { OMAP_TAG_UART, &omap3_evm_uart_config }, - { OMAP_TAG_LCD, &omap3_evm_lcd_config }, -}; - static struct platform_device *omap3_evm_devices[] __initdata = { &omap3_evm_lcd_device, &omap3evm_smc911x_device, @@ -301,8 +298,6 @@ static void __init omap3_evm_init(void) omap3_evm_i2c_init(); platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices)); - omap_board_config = omap3_evm_config; - omap_board_config_size = ARRAY_SIZE(omap3_evm_config); spi_register_board_info(omap3evm_spi_board_info, ARRAY_SIZE(omap3evm_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 864ee3d021f7..b43f6e36b6d9 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -213,10 +213,6 @@ static struct twl4030_hsmmc_info omap3pandora_mmc[] = { {} /* Terminator */ }; -static struct omap_uart_config omap3pandora_uart_config __initdata = { - .enabled_uarts = (1 << 2), /* UART3 */ -}; - static struct regulator_consumer_supply pandora_vmmc1_supply = { .supply = "vmmc", }; @@ -309,14 +305,6 @@ static int __init omap3pandora_i2c_init(void) return 0; } -static void __init omap3pandora_init_irq(void) -{ - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - omap_init_irq(); - omap_gpio_init(); -} - static void __init omap3pandora_ads7846_init(void) { int gpio = OMAP3_PANDORA_TS_GPIO; @@ -376,10 +364,19 @@ static struct omap_lcd_config omap3pandora_lcd_config __initdata = { }; static struct omap_board_config_kernel omap3pandora_config[] __initdata = { - { OMAP_TAG_UART, &omap3pandora_uart_config }, { OMAP_TAG_LCD, &omap3pandora_lcd_config }, }; +static void __init omap3pandora_init_irq(void) +{ + omap_board_config = omap3pandora_config; + omap_board_config_size = ARRAY_SIZE(omap3pandora_config); + omap2_init_common_hw(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); + omap_init_irq(); + omap_gpio_init(); +} + static struct platform_device *omap3pandora_devices[] __initdata = { &omap3pandora_lcd_device, &pandora_leds_gpio, @@ -391,8 +388,6 @@ static void __init omap3pandora_init(void) omap3pandora_i2c_init(); platform_add_devices(omap3pandora_devices, ARRAY_SIZE(omap3pandora_devices)); - omap_board_config = omap3pandora_config; - omap_board_config_size = ARRAY_SIZE(omap3pandora_config); omap_serial_init(); spi_register_board_info(omap3pandora_spi_board_info, ARRAY_SIZE(omap3pandora_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 6bce23004aa4..9917d2fddc2f 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -271,9 +271,6 @@ static void __init overo_flash_init(void) printk(KERN_ERR "Unable to register NAND device\n"); } } -static struct omap_uart_config overo_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; static struct twl4030_hsmmc_info mmc[] = { { @@ -360,14 +357,6 @@ static int __init overo_i2c_init(void) return 0; } -static void __init overo_init_irq(void) -{ - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - omap_init_irq(); - omap_gpio_init(); -} - static struct platform_device overo_lcd_device = { .name = "overo_lcd", .id = -1, @@ -378,10 +367,19 @@ static struct omap_lcd_config overo_lcd_config __initdata = { }; static struct omap_board_config_kernel overo_config[] __initdata = { - { OMAP_TAG_UART, &overo_uart_config }, { OMAP_TAG_LCD, &overo_lcd_config }, }; +static void __init overo_init_irq(void) +{ + omap_board_config = overo_config; + omap_board_config_size = ARRAY_SIZE(overo_config); + omap2_init_common_hw(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); + omap_init_irq(); + omap_gpio_init(); +} + static struct platform_device *overo_devices[] __initdata = { &overo_lcd_device, }; @@ -390,8 +388,6 @@ static void __init overo_init(void) { overo_i2c_init(); platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); - omap_board_config = overo_config; - omap_board_config_size = ARRAY_SIZE(overo_config); omap_serial_init(); overo_flash_init(); usb_musb_init(); diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 56d931a425f7..e70baa799018 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap2/board-rx51-flash.c + * linux/arch/arm/mach-omap2/board-rx51-peripherals.c * * Copyright (C) 2008-2009 Nokia * @@ -282,7 +282,124 @@ static struct twl4030_usb_data rx51_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static struct twl4030_platform_data rx51_twldata = { +static struct twl4030_ins sleep_on_seq[] __initdata = { +/* + * Turn off VDD1 and VDD2. + */ + {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4}, + {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2}, +/* + * And also turn off the OMAP3 PLLs and the sysclk output. + */ + {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3}, + {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_OFF), 3}, +}; + +static struct twl4030_script sleep_on_script __initdata = { + .script = sleep_on_seq, + .size = ARRAY_SIZE(sleep_on_seq), + .flags = TWL4030_SLEEP_SCRIPT, +}; + +static struct twl4030_ins wakeup_seq[] __initdata = { +/* + * Reenable the OMAP3 PLLs. + * Wakeup VDD1 and VDD2. + * Reenable sysclk output. + */ + {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30}, + {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30}, + {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37}, + {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3}, +}; + +static struct twl4030_script wakeup_script __initdata = { + .script = wakeup_seq, + .size = ARRAY_SIZE(wakeup_seq), + .flags = TWL4030_WAKEUP12_SCRIPT, +}; + +static struct twl4030_ins wakeup_p3_seq[] __initdata = { +/* + * Wakeup VDD1 (dummy to be able to insert a delay) + * Enable CLKEN + */ + {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_ACTIVE), 3}, +}; + +static struct twl4030_script wakeup_p3_script __initdata = { + .script = wakeup_p3_seq, + .size = ARRAY_SIZE(wakeup_p3_seq), + .flags = TWL4030_WAKEUP3_SCRIPT, +}; + +static struct twl4030_ins wrst_seq[] __initdata = { +/* + * Reset twl4030. + * Reset VDD1 regulator. + * Reset VDD2 regulator. + * Reset VPLL1 regulator. + * Enable sysclk output. + * Reenable twl4030. + */ + {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2}, + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE), + 0x13}, + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 2, RES_STATE_WRST), 0x13}, + {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13}, + {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13}, + {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13}, + {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35}, + {MSG_SINGULAR(DEV_GRP_P1, RES_HFCLKOUT, RES_STATE_ACTIVE), 2}, + {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2}, +}; + +static struct twl4030_script wrst_script __initdata = { + .script = wrst_seq, + .size = ARRAY_SIZE(wrst_seq), + .flags = TWL4030_WRST_SCRIPT, +}; + +static struct twl4030_script *twl4030_scripts[] __initdata = { + /* wakeup12 script should be loaded before sleep script, otherwise a + board might hit retention before loading of wakeup script is + completed. This can cause boot failures depending on timing issues. + */ + &wakeup_script, + &sleep_on_script, + &wakeup_p3_script, + &wrst_script, +}; + +static struct twl4030_resconfig twl4030_rconfig[] __initdata = { + { .resource = RES_VINTANA1, .devgroup = -1, .type = -1, .type2 = 1 }, + { .resource = RES_VINTANA2, .devgroup = -1, .type = -1, .type2 = 1 }, + { .resource = RES_VINTDIG, .devgroup = -1, .type = -1, .type2 = 1 }, + { .resource = RES_VMMC1, .devgroup = -1, .type = -1, .type2 = 3}, + { .resource = RES_VMMC2, .devgroup = DEV_GRP_NULL, .type = -1, + .type2 = 3}, + { .resource = RES_VAUX1, .devgroup = -1, .type = -1, .type2 = 3}, + { .resource = RES_VAUX2, .devgroup = -1, .type = -1, .type2 = 3}, + { .resource = RES_VAUX3, .devgroup = -1, .type = -1, .type2 = 3}, + { .resource = RES_VAUX4, .devgroup = -1, .type = -1, .type2 = 3}, + { .resource = RES_VPLL2, .devgroup = -1, .type = -1, .type2 = 3}, + { .resource = RES_VDAC, .devgroup = -1, .type = -1, .type2 = 3}, + { .resource = RES_VSIM, .devgroup = DEV_GRP_NULL, .type = -1, + .type2 = 3}, + { .resource = RES_CLKEN, .devgroup = DEV_GRP_P3, .type = -1, + .type2 = 1 }, + { 0, 0}, +}; + +static struct twl4030_power_data rx51_t2scripts_data __initdata = { + .scripts = twl4030_scripts, + .num = ARRAY_SIZE(twl4030_scripts), + .resource_config = twl4030_rconfig, +}; + + + +static struct twl4030_platform_data rx51_twldata __initdata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -291,6 +408,7 @@ static struct twl4030_platform_data rx51_twldata = { .keypad = &rx51_kp_data, .madc = &rx51_madc_data, .usb = &rx51_usb_data, + .power = &rx51_t2scripts_data, .vaux1 = &rx51_vaux1, .vaux2 = &rx51_vaux2, diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 1c9e07fe8266..f9196c3b1a7b 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -31,10 +31,6 @@ #include <mach/gpmc.h> #include <mach/usb.h> -static struct omap_uart_config rx51_uart_config = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), -}; - static struct omap_lcd_config rx51_lcd_config = { .ctrl_name = "internal", }; @@ -52,7 +48,6 @@ static struct omap_fbmem_config rx51_fbmem2_config = { }; static struct omap_board_config_kernel rx51_config[] = { - { OMAP_TAG_UART, &rx51_uart_config }, { OMAP_TAG_FBMEM, &rx51_fbmem0_config }, { OMAP_TAG_FBMEM, &rx51_fbmem1_config }, { OMAP_TAG_FBMEM, &rx51_fbmem2_config }, @@ -61,6 +56,8 @@ static struct omap_board_config_kernel rx51_config[] = { static void __init rx51_init_irq(void) { + omap_board_config = rx51_config; + omap_board_config_size = ARRAY_SIZE(rx51_config); omap2_init_common_hw(NULL, NULL); omap_init_irq(); omap_gpio_init(); @@ -70,8 +67,6 @@ extern void __init rx51_peripherals_init(void); static void __init rx51_init(void) { - omap_board_config = rx51_config; - omap_board_config_size = ARRAY_SIZE(rx51_config); omap_serial_init(); usb_musb_init(); rx51_peripherals_init(); diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c index bac5c4321ff7..1f13e2a1f322 100644 --- a/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -12,6 +12,7 @@ #include <linux/gpio.h> #include <linux/serial_8250.h> #include <linux/smsc911x.h> +#include <linux/interrupt.h> #include <mach/gpmc.h> @@ -84,6 +85,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .mapbase = 0x10000000, .irq = OMAP_GPIO_IRQ(102), .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ, + .irqflags = IRQF_SHARED | IRQF_TRIGGER_RISING, .iotype = UPIO_MEM, .regshift = 1, .uartclk = QUART_CLK, @@ -94,7 +96,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device zoom2_debugboard_serial_device = { .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, + .id = 3, .dev = { .platform_data = serial_platform_data, }, @@ -127,6 +129,7 @@ static inline void __init zoom2_init_quaduart(void) static inline int omap_zoom2_debugboard_detect(void) { int debug_board_detect = 0; + int ret = 1; debug_board_detect = ZOOM2_SMSC911X_GPIO; @@ -138,10 +141,10 @@ static inline int omap_zoom2_debugboard_detect(void) gpio_direction_input(debug_board_detect); if (!gpio_get_value(debug_board_detect)) { - gpio_free(debug_board_detect); - return 0; + ret = 0; } - return 1; + gpio_free(debug_board_detect); + return ret; } static struct platform_device *zoom2_devices[] __initdata = { diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 427b7b8b1237..324009edbd53 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -12,36 +12,217 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/input.h> #include <linux/gpio.h> #include <linux/i2c/twl4030.h> +#include <linux/regulator/machine.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/common.h> #include <mach/usb.h> +#include <mach/keypad.h> #include "mmc-twl4030.h" -static void __init omap_zoom2_init_irq(void) +/* Zoom2 has Qwerty keyboard*/ +static int zoom2_twl4030_keymap[] = { + KEY(0, 0, KEY_E), + KEY(1, 0, KEY_R), + KEY(2, 0, KEY_T), + KEY(3, 0, KEY_HOME), + KEY(6, 0, KEY_I), + KEY(7, 0, KEY_LEFTSHIFT), + KEY(0, 1, KEY_D), + KEY(1, 1, KEY_F), + KEY(2, 1, KEY_G), + KEY(3, 1, KEY_SEND), + KEY(6, 1, KEY_K), + KEY(7, 1, KEY_ENTER), + KEY(0, 2, KEY_X), + KEY(1, 2, KEY_C), + KEY(2, 2, KEY_V), + KEY(3, 2, KEY_END), + KEY(6, 2, KEY_DOT), + KEY(7, 2, KEY_CAPSLOCK), + KEY(0, 3, KEY_Z), + KEY(1, 3, KEY_KPPLUS), + KEY(2, 3, KEY_B), + KEY(3, 3, KEY_F1), + KEY(6, 3, KEY_O), + KEY(7, 3, KEY_SPACE), + KEY(0, 4, KEY_W), + KEY(1, 4, KEY_Y), + KEY(2, 4, KEY_U), + KEY(3, 4, KEY_F2), + KEY(4, 4, KEY_VOLUMEUP), + KEY(6, 4, KEY_L), + KEY(7, 4, KEY_LEFT), + KEY(0, 5, KEY_S), + KEY(1, 5, KEY_H), + KEY(2, 5, KEY_J), + KEY(3, 5, KEY_F3), + KEY(5, 5, KEY_VOLUMEDOWN), + KEY(6, 5, KEY_M), + KEY(4, 5, KEY_ENTER), + KEY(7, 5, KEY_RIGHT), + KEY(0, 6, KEY_Q), + KEY(1, 6, KEY_A), + KEY(2, 6, KEY_N), + KEY(3, 6, KEY_BACKSPACE), + KEY(6, 6, KEY_P), + KEY(7, 6, KEY_UP), + KEY(6, 7, KEY_SELECT), + KEY(7, 7, KEY_DOWN), + KEY(0, 7, KEY_PROG1), /*MACRO 1 <User defined> */ + KEY(1, 7, KEY_PROG2), /*MACRO 2 <User defined> */ + KEY(2, 7, KEY_PROG3), /*MACRO 3 <User defined> */ + KEY(3, 7, KEY_PROG4), /*MACRO 4 <User defined> */ + 0 +}; + +static struct twl4030_keypad_data zoom2_kp_twl4030_data = { + .rows = 8, + .cols = 8, + .keymap = zoom2_twl4030_keymap, + .keymapsize = ARRAY_SIZE(zoom2_twl4030_keymap), + .rep = 1, +}; + +static struct omap_board_config_kernel zoom2_config[] __initdata = { +}; + +static struct regulator_consumer_supply zoom2_vmmc1_supply = { + .supply = "vmmc", +}; + +static struct regulator_consumer_supply zoom2_vsim_supply = { + .supply = "vmmc_aux", +}; + +static struct regulator_consumer_supply zoom2_vmmc2_supply = { + .supply = "vmmc", +}; + +/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ +static struct regulator_init_data zoom2_vmmc1 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom2_vmmc1_supply, +}; + +/* VMMC2 for MMC2 card */ +static struct regulator_init_data zoom2_vmmc2 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 1850000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom2_vmmc2_supply, +}; + +/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ +static struct regulator_init_data zoom2_vsim = { + .constraints = { + .min_uV = 1800000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom2_vsim_supply, +}; + +static struct twl4030_hsmmc_info mmc[] __initdata = { + { + .mmc = 1, + .wires = 4, + .gpio_wp = -EINVAL, + }, + { + .mmc = 2, + .wires = 4, + .gpio_wp = -EINVAL, + }, + {} /* Terminator */ +}; + +static int zoom2_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) { - omap2_init_common_hw(NULL, NULL); - omap_init_irq(); - omap_gpio_init(); + /* gpio + 0 is "mmc0_cd" (input/IRQ), + * gpio + 1 is "mmc1_cd" (input/IRQ) + */ + mmc[0].gpio_cd = gpio + 0; + mmc[1].gpio_cd = gpio + 1; + twl4030_mmc_init(mmc); + + /* link regulators to MMC adapters ... we "know" the + * regulators will be set up only *after* we return. + */ + zoom2_vmmc1_supply.dev = mmc[0].dev; + zoom2_vsim_supply.dev = mmc[0].dev; + zoom2_vmmc2_supply.dev = mmc[1].dev; + + return 0; } -static struct omap_uart_config zoom2_uart_config __initdata = { - .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), + +static int zoom2_batt_table[] = { +/* 0 C*/ +30800, 29500, 28300, 27100, +26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900, +17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100, +11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310, +8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830, +5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170, +4040, 3910, 3790, 3670, 3550 }; -static struct omap_board_config_kernel zoom2_config[] __initdata = { - { OMAP_TAG_UART, &zoom2_uart_config }, +static struct twl4030_bci_platform_data zoom2_bci_data = { + .battery_tmp_tbl = zoom2_batt_table, + .tblsize = ARRAY_SIZE(zoom2_batt_table), }; +static struct twl4030_usb_data zoom2_usb_data = { + .usb_mode = T2_USB_MODE_ULPI, +}; + +static void __init omap_zoom2_init_irq(void) +{ + omap_board_config = zoom2_config; + omap_board_config_size = ARRAY_SIZE(zoom2_config); + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); +} + static struct twl4030_gpio_platform_data zoom2_gpio_data = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, + .setup = zoom2_twl_gpio_setup, +}; + +static struct twl4030_madc_platform_data zoom2_madc_data = { + .irq_line = 1, }; static struct twl4030_platform_data zoom2_twldata = { @@ -49,7 +230,15 @@ static struct twl4030_platform_data zoom2_twldata = { .irq_end = TWL4030_IRQ_END, /* platform_data for children goes here */ + .bci = &zoom2_bci_data, + .madc = &zoom2_madc_data, + .usb = &zoom2_usb_data, .gpio = &zoom2_gpio_data, + .keypad = &zoom2_kp_twl4030_data, + .vmmc1 = &zoom2_vmmc1, + .vmmc2 = &zoom2_vmmc2, + .vsim = &zoom2_vsim, + }; static struct i2c_board_info __initdata zoom2_i2c_boardinfo[] = { @@ -70,26 +259,13 @@ static int __init omap_i2c_init(void) return 0; } -static struct twl4030_hsmmc_info mmc[] __initdata = { - { - .mmc = 1, - .wires = 4, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - }, - {} /* Terminator */ -}; - extern int __init omap_zoom2_debugboard_init(void); static void __init omap_zoom2_init(void) { omap_i2c_init(); - omap_board_config = zoom2_config; - omap_board_config_size = ARRAY_SIZE(zoom2_config); omap_serial_init(); omap_zoom2_debugboard_init(); - twl4030_mmc_init(mmc); usb_musb_init(); } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 456e2ad5f621..f2a92d614f0f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -1043,5 +1043,7 @@ void omap2_clk_disable_unused(struct clk *clk) omap2_clk_disable(clk); } else _omap2_clk_disable(clk); + if (clk->clkdm != NULL) + pwrdm_clkdm_state_switch(clk->clkdm); } #endif diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index cd7819cc0c9e..fafcd32e6907 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -27,6 +27,7 @@ #include <linux/limits.h> #include <linux/bitops.h> +#include <mach/cpu.h> #include <mach/clock.h> #include <mach/sram.h> #include <asm/div64.h> @@ -1067,17 +1068,17 @@ static int __init omap2_clk_arch_init(void) return -EINVAL; /* REVISIT: not yet ready for 343x */ -#if 0 - if (clk_set_rate(&virt_prcm_set, mpurate)) - printk(KERN_ERR "Could not find matching MPU rate\n"); -#endif + if (clk_set_rate(&dpll1_ck, mpurate)) + printk(KERN_ERR "*** Unable to set MPU rate\n"); recalculate_root_clocks(); - printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): " + printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): " "%ld.%01ld/%ld/%ld MHz\n", - (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, - (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ; + (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10), + (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ; + + calibrate_delay(); return 0; } @@ -1136,7 +1137,7 @@ int __init omap2_clk_init(void) recalculate_root_clocks(); - printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): " + printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " "%ld.%01ld/%ld/%ld MHz\n", (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 57cc2725b923..c8119781e00a 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -1020,6 +1020,7 @@ static struct clk arm_fck = { .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = arm_fck_clksel, + .clkdm_name = "mpu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1155,7 +1156,6 @@ static struct clk gfx_cg1_ck = { .name = "gfx_cg1_ck", .ops = &clkops_omap2_dflt_wait, .parent = &gfx_l3_fck, /* REVISIT: correct? */ - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_2D_SHIFT, .clkdm_name = "gfx_3430es1_clkdm", @@ -1166,7 +1166,6 @@ static struct clk gfx_cg2_ck = { .name = "gfx_cg2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &gfx_l3_fck, /* REVISIT: correct? */ - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_3D_SHIFT, .clkdm_name = "gfx_3430es1_clkdm", @@ -1210,7 +1209,6 @@ static struct clk sgx_ick = { .name = "sgx_ick", .ops = &clkops_omap2_dflt_wait, .parent = &l3_ick, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, .clkdm_name = "sgx_clkdm", @@ -1223,7 +1221,6 @@ static struct clk d2d_26m_fck = { .name = "d2d_26m_fck", .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, .clkdm_name = "d2d_clkdm", @@ -1234,7 +1231,6 @@ static struct clk modem_fck = { .name = "modem_fck", .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MODEM_SHIFT, .clkdm_name = "d2d_clkdm", @@ -1622,7 +1618,6 @@ static struct clk core_l3_ick = { .name = "core_l3_ick", .ops = &clkops_null, .parent = &l3_ick, - .init = &omap2_init_clk_clkdm, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; @@ -1691,7 +1686,6 @@ static struct clk core_l4_ick = { .name = "core_l4_ick", .ops = &clkops_null, .parent = &l4_ick, - .init = &omap2_init_clk_clkdm, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2089,7 +2083,6 @@ static struct clk dss_tv_fck = { .name = "dss_tv_fck", .ops = &clkops_omap2_dflt, .parent = &omap_54m_fck, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, .clkdm_name = "dss_clkdm", @@ -2100,7 +2093,6 @@ static struct clk dss_96m_fck = { .name = "dss_96m_fck", .ops = &clkops_omap2_dflt, .parent = &omap_96m_fck, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, .clkdm_name = "dss_clkdm", @@ -2111,7 +2103,6 @@ static struct clk dss2_alwon_fck = { .name = "dss2_alwon_fck", .ops = &clkops_omap2_dflt, .parent = &sys_ck, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS2_SHIFT, .clkdm_name = "dss_clkdm", @@ -2123,7 +2114,6 @@ static struct clk dss_ick_3430es1 = { .name = "dss_ick", .ops = &clkops_omap2_dflt, .parent = &l4_ick, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, .clkdm_name = "dss_clkdm", @@ -2135,7 +2125,6 @@ static struct clk dss_ick_3430es2 = { .name = "dss_ick", .ops = &clkops_omap3430es2_dss_usbhost_wait, .parent = &l4_ick, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, .clkdm_name = "dss_clkdm", @@ -2159,7 +2148,6 @@ static struct clk cam_ick = { .name = "cam_ick", .ops = &clkops_omap2_dflt, .parent = &l4_ick, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, .clkdm_name = "cam_clkdm", @@ -2170,7 +2158,6 @@ static struct clk csi2_96m_fck = { .name = "csi2_96m_fck", .ops = &clkops_omap2_dflt, .parent = &core_96m_fck, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CSI2_SHIFT, .clkdm_name = "cam_clkdm", @@ -2183,7 +2170,6 @@ static struct clk usbhost_120m_fck = { .name = "usbhost_120m_fck", .ops = &clkops_omap2_dflt, .parent = &dpll5_m2_ck, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, .clkdm_name = "usbhost_clkdm", @@ -2194,7 +2180,6 @@ static struct clk usbhost_48m_fck = { .name = "usbhost_48m_fck", .ops = &clkops_omap3430es2_dss_usbhost_wait, .parent = &omap_48m_fck, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, .clkdm_name = "usbhost_clkdm", @@ -2206,7 +2191,6 @@ static struct clk usbhost_ick = { .name = "usbhost_ick", .ops = &clkops_omap3430es2_dss_usbhost_wait, .parent = &l4_ick, - .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, .clkdm_name = "usbhost_clkdm", @@ -2268,7 +2252,6 @@ static struct clk gpt1_fck = { static struct clk wkup_32k_fck = { .name = "wkup_32k_fck", .ops = &clkops_null, - .init = &omap2_init_clk_clkdm, .parent = &omap_32k_fck, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, @@ -2383,7 +2366,6 @@ static struct clk per_96m_fck = { .name = "per_96m_fck", .ops = &clkops_null, .parent = &omap_96m_alwon_fck, - .init = &omap2_init_clk_clkdm, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2392,7 +2374,6 @@ static struct clk per_48m_fck = { .name = "per_48m_fck", .ops = &clkops_null, .parent = &omap_48m_fck, - .init = &omap2_init_clk_clkdm, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 0e7d501865b6..4ef7b4f5474e 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -299,7 +299,8 @@ struct clockdomain *clkdm_lookup(const char *name) * anything else to indicate failure; or -EINVAL if the function pointer * is null. */ -int clkdm_for_each(int (*fn)(struct clockdomain *clkdm)) +int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), + void *user) { struct clockdomain *clkdm; int ret = 0; @@ -309,7 +310,7 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm)) mutex_lock(&clkdm_mutex); list_for_each_entry(clkdm, &clkdm_list, node) { - ret = (*fn)(clkdm); + ret = (*fn)(clkdm, user); if (ret) break; } @@ -484,6 +485,8 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) v << __ffs(clkdm->clktrctrl_mask), clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); + + pwrdm_clkdm_state_switch(clkdm); } /** @@ -572,6 +575,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) omap2_clkdm_wakeup(clkdm); pwrdm_wait_transition(clkdm->pwrdm.ptr); + pwrdm_clkdm_state_switch(clkdm); return 0; } @@ -624,6 +628,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) else omap2_clkdm_sleep(clkdm); + pwrdm_clkdm_state_switch(clkdm); + return 0; } diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c new file mode 100644 index 000000000000..8eb2dab8c7db --- /dev/null +++ b/arch/arm/mach-omap2/cm.c @@ -0,0 +1,70 @@ +/* + * OMAP2/3 CM module functions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/spinlock.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <asm/atomic.h> + +#include "cm.h" +#include "cm-regbits-24xx.h" +#include "cm-regbits-34xx.h" + +/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */ +#define MAX_MODULE_READY_TIME 20000 + +static const u8 cm_idlest_offs[] = { + CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 +}; + +/** + * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby + * @prcm_mod: PRCM module offset + * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) + * @idlest_shift: shift of the bit in the CM_IDLEST* register to check + * + * XXX document + */ +int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) +{ + int ena = 0, i = 0; + u8 cm_idlest_reg; + u32 mask; + + if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) + return -EINVAL; + + cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; + + if (cpu_is_omap24xx()) + ena = idlest_shift; + else if (cpu_is_omap34xx()) + ena = 0; + else + BUG(); + + mask = 1 << idlest_shift; + + /* XXX should be OMAP2 CM */ + while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) && + (i++ < MAX_MODULE_READY_TIME)) + udelay(1); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; +} + diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index f3c91a1ca391..cfd0b726ba44 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -17,11 +17,11 @@ #include "prcm-common.h" #define OMAP2420_CM_REGADDR(module, reg) \ - IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) + OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) #define OMAP2430_CM_REGADDR(module, reg) \ - IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) + OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) #define OMAP34XX_CM_REGADDR(module, reg) \ - IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) + OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) /* * Architecture-specific global CM registers @@ -98,6 +98,10 @@ extern u32 cm_read_mod_reg(s16 module, u16 idx); extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, + u8 idlest_shift); +extern int omap4_cm_wait_module_ready(u32 prcm_mod, u8 prcm_dev_offs); + static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) { return cm_rmw_mod_reg_bits(bits, bits, module, idx); diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c new file mode 100644 index 000000000000..e4ebd6d53135 --- /dev/null +++ b/arch/arm/mach-omap2/cm4xxx.c @@ -0,0 +1,68 @@ +/* + * OMAP4 CM module functions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/spinlock.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <asm/atomic.h> + +#include "cm.h" +#include "cm-regbits-4xxx.h" + +/* XXX move this to cm.h */ +/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */ +#define MAX_MODULE_READY_TIME 20000 + +/* + * OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK: isolates the IDLEST field in the + * CM_CLKCTRL register. + */ +#define OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK (0x2 << 16) + +/* + * OMAP4 prcm_mod u32 fields contain packed data: the CM ID in bit 16 and + * the PRCM module offset address (from the CM module base) in bits 15-0. + */ +#define OMAP4_PRCM_MOD_CM_ID_SHIFT 16 +#define OMAP4_PRCM_MOD_OFFS_MASK 0xffff + +/** + * omap4_cm_wait_idlest_ready - wait for a module to leave idle or standby + * @prcm_mod: PRCM module offset (XXX example) + * @prcm_dev_offs: PRCM device offset (e.g. MCASP XXX example) + * + * XXX document + */ +int omap4_cm_wait_idlest_ready(u32 prcm_mod, u8 prcm_dev_offs) +{ + int i = 0; + u8 cm_id; + u16 prcm_mod_offs; + u32 mask = OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK; + + cm_id = prcm_mod >> OMAP4_PRCM_MOD_CM_ID_SHIFT; + prcm_mod_offs = prcm_mod & OMAP4_PRCM_MOD_OFFS_MASK; + + while (((omap4_cm_read_mod_reg(cm_id, prcm_mod_offs, prcm_dev_offs, + OMAP4_CM_CLKCTRL_DREG) & mask) != 0) && + (i++ < MAX_MODULE_READY_TIME)) + udelay(1); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; +} + diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 894cc355818a..a2e915639b72 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -513,6 +513,47 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); } } + + if (cpu_is_omap3430()) { + if (controller_nr == 0) { + omap_cfg_reg(N28_3430_MMC1_CLK); + omap_cfg_reg(M27_3430_MMC1_CMD); + omap_cfg_reg(N27_3430_MMC1_DAT0); + if (mmc_controller->slots[0].wires == 4 || + mmc_controller->slots[0].wires == 8) { + omap_cfg_reg(N26_3430_MMC1_DAT1); + omap_cfg_reg(N25_3430_MMC1_DAT2); + omap_cfg_reg(P28_3430_MMC1_DAT3); + } + if (mmc_controller->slots[0].wires == 8) { + omap_cfg_reg(P27_3430_MMC1_DAT4); + omap_cfg_reg(P26_3430_MMC1_DAT5); + omap_cfg_reg(R27_3430_MMC1_DAT6); + omap_cfg_reg(R25_3430_MMC1_DAT7); + } + } + if (controller_nr == 1) { + /* MMC2 */ + omap_cfg_reg(AE2_3430_MMC2_CLK); + omap_cfg_reg(AG5_3430_MMC2_CMD); + omap_cfg_reg(AH5_3430_MMC2_DAT0); + + /* + * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed + * in the board-*.c files + */ + if (mmc_controller->slots[0].wires == 4 || + mmc_controller->slots[0].wires == 8) { + omap_cfg_reg(AH4_3430_MMC2_DAT1); + omap_cfg_reg(AG4_3430_MMC2_DAT2); + omap_cfg_reg(AF4_3430_MMC2_DAT3); + } + } + + /* + * For MMC3 the pins need to be muxed in the board-*.c files + */ + } } void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index e9b9bcb19b4e..7574b6f20e8e 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -32,17 +32,23 @@ #include <mach/sram.h> #include <mach/sdrc.h> #include <mach/gpmc.h> +#include <mach/serial.h> #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */ #include "clock.h" +#include <mach/omap-pm.h> #include <mach/powerdomain.h> - #include "powerdomains.h" #include <mach/clockdomain.h> #include "clockdomains.h" #endif +#include <mach/omap_hwmod.h> +#include "omap_hwmod_2420.h" +#include "omap_hwmod_2430.h" +#include "omap_hwmod_34xx.h" + /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. @@ -279,11 +285,26 @@ static int __init _omap2_init_reprogram_sdrc(void) void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { + struct omap_hwmod **hwmods = NULL; + + if (cpu_is_omap2420()) + hwmods = omap2420_hwmods; + else if (cpu_is_omap2430()) + hwmods = omap2430_hwmods; + else if (cpu_is_omap34xx()) + hwmods = omap34xx_hwmods; + + omap_hwmod_init(hwmods); omap2_mux_init(); #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ + /* The OPP tables have to be registered before a clk init */ + omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); omap2_clk_init(); + omap_serial_early_init(); + omap_hwmod_late_init(); + omap_pm_if_init(); omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); #endif diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index 015f22a53ead..2d9b5cc981cd 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -217,10 +217,19 @@ static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) } #define pr_reg(name) \ - p += sprintf(p, "%20s: %08x\n", \ - __stringify(name), iommu_read_reg(obj, MMU_##name)); - -static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf) + do { \ + ssize_t bytes; \ + const char *str = "%20s: %08x\n"; \ + const int maxcol = 32; \ + bytes = snprintf(p, maxcol, str, __stringify(name), \ + iommu_read_reg(obj, MMU_##name)); \ + p += bytes; \ + len -= bytes; \ + if (len < maxcol) \ + goto out; \ + } while (0) + +static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len) { char *p = buf; @@ -242,7 +251,7 @@ static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf) pr_reg(READ_CAM); pr_reg(READ_RAM); pr_reg(EMU_FAULT_AD); - +out: return p - buf; } diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 43d6b92b65f2..2daa595aaff4 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -492,6 +492,61 @@ MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT) MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT) + +/* MMC1 */ +MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) + +/* MMC2 */ +MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) + +/* MMC3 */ +MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) + +/* SYS_NIRQ T2 INT1 */ +MUX_CFG_34XX("AF26_34XX_SYS_NIRQ", 0x1E0, + OMAP3_WAKEUP_EN | OMAP34XX_PIN_INPUT_PULLUP | + OMAP34XX_MUX_MODE0) }; #define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 8fe8d230f21b..48ee295db275 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -54,7 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * for us: do so */ - gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); + gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); /* * Synchronise with the boot thread. diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c new file mode 100644 index 000000000000..d2e0f1c95961 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -0,0 +1,1554 @@ +/* + * omap_hwmod implementation for OMAP2/3/4 + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * With fixes and testing from Kevin Hilman + * + * Created in collaboration with (alphabetical order): Benoit Cousson, + * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari + * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This code manages "OMAP modules" (on-chip devices) and their + * integration with Linux device driver and bus code. + * + * References: + * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) + * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) + * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) + * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) + * - Open Core Protocol Specification 2.2 + * + * To do: + * - pin mux handling + * - handle IO mapping + * - bus throughput & module latency measurement code + * + * XXX add tests at the beginning of each function to ensure the hwmod is + * in the appropriate state + * XXX error return values should be checked to ensure that they are + * appropriate + */ +#undef DEBUG + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/list.h> +#include <linux/mutex.h> +#include <linux/bootmem.h> + +#include <mach/cpu.h> +#include <mach/clockdomain.h> +#include <mach/powerdomain.h> +#include <mach/clock.h> +#include <mach/omap_hwmod.h> + +#include "cm.h" + +/* Maximum microseconds to wait for OMAP module to reset */ +#define MAX_MODULE_RESET_WAIT 10000 + +/* Name of the OMAP hwmod for the MPU */ +#define MPU_INITIATOR_NAME "mpu_hwmod" + +/* omap_hwmod_list contains all registered struct omap_hwmods */ +static LIST_HEAD(omap_hwmod_list); + +static DEFINE_MUTEX(omap_hwmod_mutex); + +/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ +static struct omap_hwmod *mpu_oh; + +/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */ +static u8 inited; + + +/* Private functions */ + +/** + * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy + * @oh: struct omap_hwmod * + * + * Load the current value of the hwmod OCP_SYSCONFIG register into the + * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no + * OCP_SYSCONFIG register or 0 upon success. + */ +static int _update_sysc_cache(struct omap_hwmod *oh) +{ + if (!oh->sysconfig) { + WARN(!oh->sysconfig, "omap_hwmod: %s: cannot read " + "OCP_SYSCONFIG: not defined on hwmod\n", oh->name); + return -EINVAL; + } + + /* XXX ensure module interface clock is up */ + + oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); + + oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; + + return 0; +} + +/** + * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register + * @v: OCP_SYSCONFIG value to write + * @oh: struct omap_hwmod * + * + * Write @v into the module OCP_SYSCONFIG register, if it has one. No + * return value. + */ +static void _write_sysconfig(u32 v, struct omap_hwmod *oh) +{ + if (!oh->sysconfig) { + WARN(!oh->sysconfig, "omap_hwmod: %s: cannot write " + "OCP_SYSCONFIG: not defined on hwmod\n", oh->name); + return; + } + + /* XXX ensure module interface clock is up */ + + if (oh->_sysc_cache != v) { + oh->_sysc_cache = v; + omap_hwmod_writel(v, oh, oh->sysconfig->sysc_offs); + } +} + +/** + * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v + * @oh: struct omap_hwmod * + * @standbymode: MIDLEMODE field bits + * @v: pointer to register contents to modify + * + * Update the master standby mode bits in @v to be @standbymode for + * the @oh hwmod. Does not write to the hardware. Returns -EINVAL + * upon error or 0 upon success. + */ +static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, + u32 *v) +{ + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)) + return -EINVAL; + + *v &= ~SYSC_MIDLEMODE_MASK; + *v |= __ffs(standbymode) << SYSC_MIDLEMODE_SHIFT; + + return 0; +} + +/** + * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v + * @oh: struct omap_hwmod * + * @idlemode: SIDLEMODE field bits + * @v: pointer to register contents to modify + * + * Update the slave idle mode bits in @v to be @idlemode for the @oh + * hwmod. Does not write to the hardware. Returns -EINVAL upon error + * or 0 upon success. + */ +static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) +{ + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE)) + return -EINVAL; + + *v &= ~SYSC_SIDLEMODE_MASK; + *v |= __ffs(idlemode) << SYSC_SIDLEMODE_SHIFT; + + return 0; +} + +/** + * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v + * @oh: struct omap_hwmod * + * @clockact: CLOCKACTIVITY field bits + * @v: pointer to register contents to modify + * + * Update the clockactivity mode bits in @v to be @clockact for the + * @oh hwmod. Used for additional powersaving on some modules. Does + * not write to the hardware. Returns -EINVAL upon error or 0 upon + * success. + */ +static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) +{ + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) + return -EINVAL; + + *v &= ~SYSC_CLOCKACTIVITY_MASK; + *v |= clockact << SYSC_CLOCKACTIVITY_SHIFT; + + return 0; +} + +/** + * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v + * @oh: struct omap_hwmod * + * @v: pointer to register contents to modify + * + * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon + * error or 0 upon success. + */ +static int _set_softreset(struct omap_hwmod *oh, u32 *v) +{ + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET)) + return -EINVAL; + + *v |= SYSC_SOFTRESET_MASK; + + return 0; +} + +/** + * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware + * @oh: struct omap_hwmod * + * + * Allow the hardware module @oh to send wakeups. Returns -EINVAL + * upon error or 0 upon success. + */ +static int _enable_wakeup(struct omap_hwmod *oh) +{ + u32 v; + + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) + return -EINVAL; + + v = oh->_sysc_cache; + v |= SYSC_ENAWAKEUP_MASK; + _write_sysconfig(v, oh); + + /* XXX test pwrdm_get_wken for this hwmod's subsystem */ + + oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; + + return 0; +} + +/** + * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware + * @oh: struct omap_hwmod * + * + * Prevent the hardware module @oh to send wakeups. Returns -EINVAL + * upon error or 0 upon success. + */ +static int _disable_wakeup(struct omap_hwmod *oh) +{ + u32 v; + + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) + return -EINVAL; + + v = oh->_sysc_cache; + v &= ~SYSC_ENAWAKEUP_MASK; + _write_sysconfig(v, oh); + + /* XXX test pwrdm_get_wken for this hwmod's subsystem */ + + oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; + + return 0; +} + +/** + * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active + * @oh: struct omap_hwmod * + * + * Prevent the hardware module @oh from entering idle while the + * hardare module initiator @init_oh is active. Useful when a module + * will be accessed by a particular initiator (e.g., if a module will + * be accessed by the IVA, there should be a sleepdep between the IVA + * initiator and the module). Only applies to modules in smart-idle + * mode. Returns -EINVAL upon error or passes along + * pwrdm_add_sleepdep() value upon success. + */ +static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) +{ + if (!oh->_clk) + return -EINVAL; + + return pwrdm_add_sleepdep(oh->_clk->clkdm->pwrdm.ptr, + init_oh->_clk->clkdm->pwrdm.ptr); +} + +/** + * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active + * @oh: struct omap_hwmod * + * + * Allow the hardware module @oh to enter idle while the hardare + * module initiator @init_oh is active. Useful when a module will not + * be accessed by a particular initiator (e.g., if a module will not + * be accessed by the IVA, there should be no sleepdep between the IVA + * initiator and the module). Only applies to modules in smart-idle + * mode. Returns -EINVAL upon error or passes along + * pwrdm_add_sleepdep() value upon success. + */ +static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) +{ + if (!oh->_clk) + return -EINVAL; + + return pwrdm_del_sleepdep(oh->_clk->clkdm->pwrdm.ptr, + init_oh->_clk->clkdm->pwrdm.ptr); +} + +/** + * _init_main_clk - get a struct clk * for the the hwmod's main functional clk + * @oh: struct omap_hwmod * + * + * Called from _init_clocks(). Populates the @oh _clk (main + * functional clock pointer) if a main_clk is present. Returns 0 on + * success or -EINVAL on error. + */ +static int _init_main_clk(struct omap_hwmod *oh) +{ + struct clk *c; + int ret = 0; + + if (!oh->clkdev_con_id) + return 0; + + c = clk_get_sys(oh->clkdev_dev_id, oh->clkdev_con_id); + WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s.%s\n", + oh->name, oh->clkdev_dev_id, oh->clkdev_con_id); + if (IS_ERR(c)) + ret = -EINVAL; + oh->_clk = c; + + return ret; +} + +/** + * _init_interface_clk - get a struct clk * for the the hwmod's interface clks + * @oh: struct omap_hwmod * + * + * Called from _init_clocks(). Populates the @oh OCP slave interface + * clock pointers. Returns 0 on success or -EINVAL on error. + */ +static int _init_interface_clks(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + struct clk *c; + int i; + int ret = 0; + + if (oh->slaves_cnt == 0) + return 0; + + for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + if (!os->clkdev_con_id) + continue; + + c = clk_get_sys(os->clkdev_dev_id, os->clkdev_con_id); + WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get " + "interface_clk %s.%s\n", oh->name, + os->clkdev_dev_id, os->clkdev_con_id); + if (IS_ERR(c)) + ret = -EINVAL; + os->_clk = c; + } + + return ret; +} + +/** + * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks + * @oh: struct omap_hwmod * + * + * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk + * clock pointers. Returns 0 on success or -EINVAL on error. + */ +static int _init_opt_clks(struct omap_hwmod *oh) +{ + struct omap_hwmod_opt_clk *oc; + struct clk *c; + int i; + int ret = 0; + + for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { + c = clk_get_sys(oc->clkdev_dev_id, oc->clkdev_con_id); + WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk " + "%s.%s\n", oh->name, oc->clkdev_dev_id, + oc->clkdev_con_id); + if (IS_ERR(c)) + ret = -EINVAL; + oc->_clk = c; + } + + return ret; +} + +/** + * _enable_clocks - enable hwmod main clock and interface clocks + * @oh: struct omap_hwmod * + * + * Enables all clocks necessary for register reads and writes to succeed + * on the hwmod @oh. Returns 0. + */ +static int _enable_clocks(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + int i; + + pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); + + if (oh->_clk && !IS_ERR(oh->_clk)) + clk_enable(oh->_clk); + + if (oh->slaves_cnt > 0) { + for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + struct clk *c = os->_clk; + + if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE)) + clk_enable(c); + } + } + + /* The opt clocks are controlled by the device driver. */ + + return 0; +} + +/** + * _disable_clocks - disable hwmod main clock and interface clocks + * @oh: struct omap_hwmod * + * + * Disables the hwmod @oh main functional and interface clocks. Returns 0. + */ +static int _disable_clocks(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + int i; + + pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); + + if (oh->_clk && !IS_ERR(oh->_clk)) + clk_disable(oh->_clk); + + if (oh->slaves_cnt > 0) { + for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + struct clk *c = os->_clk; + + if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE)) + clk_disable(c); + } + } + + /* The opt clocks are controlled by the device driver. */ + + return 0; +} + +/** + * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use + * @oh: struct omap_hwmod * + * + * Returns the array index of the OCP slave port that the MPU + * addresses the device on, or -EINVAL upon error or not found. + */ +static int _find_mpu_port_index(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + int i; + int found = 0; + + if (!oh || oh->slaves_cnt == 0) + return -EINVAL; + + for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + if (os->user & OCP_USER_MPU) { + found = 1; + break; + } + } + + if (found) + pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", + oh->name, i); + else + pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", + oh->name); + + return (found) ? i : -EINVAL; +} + +/** + * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU + * @oh: struct omap_hwmod * + * + * Return the virtual address of the base of the register target of + * device @oh, or NULL on error. + */ +static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) +{ + struct omap_hwmod_ocp_if *os; + struct omap_hwmod_addr_space *mem; + int i; + int found = 0; + + if (!oh || oh->slaves_cnt == 0) + return NULL; + + os = *oh->slaves + index; + + for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { + if (mem->flags & ADDR_TYPE_RT) { + found = 1; + break; + } + } + + /* XXX use ioremap() instead? */ + + if (found) + pr_debug("omap_hwmod: %s: MPU register target at va %p\n", + oh->name, OMAP2_IO_ADDRESS(mem->pa_start)); + else + pr_debug("omap_hwmod: %s: no MPU register target found\n", + oh->name); + + return (found) ? OMAP2_IO_ADDRESS(mem->pa_start) : NULL; +} + +/** + * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG + * @oh: struct omap_hwmod * + * + * If module is marked as SWSUP_SIDLE, force the module out of slave + * idle; otherwise, configure it for smart-idle. If module is marked + * as SWSUP_MSUSPEND, force the module out of master standby; + * otherwise, configure it for smart-standby. No return value. + */ +static void _sysc_enable(struct omap_hwmod *oh) +{ + u8 idlemode; + u32 v; + + if (!oh->sysconfig) + return; + + v = oh->_sysc_cache; + + if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) { + idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? + HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; + _set_slave_idlemode(oh, idlemode, &v); + } + + if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) { + idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? + HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; + _set_master_standbymode(oh, idlemode, &v); + } + + /* XXX OCP AUTOIDLE bit? */ + + if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT && + oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY) + _set_clockactivity(oh, oh->sysconfig->clockact, &v); + + _write_sysconfig(v, oh); +} + +/** + * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG + * @oh: struct omap_hwmod * + * + * If module is marked as SWSUP_SIDLE, force the module into slave + * idle; otherwise, configure it for smart-idle. If module is marked + * as SWSUP_MSUSPEND, force the module into master standby; otherwise, + * configure it for smart-standby. No return value. + */ +static void _sysc_idle(struct omap_hwmod *oh) +{ + u8 idlemode; + u32 v; + + if (!oh->sysconfig) + return; + + v = oh->_sysc_cache; + + if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) { + idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? + HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; + _set_slave_idlemode(oh, idlemode, &v); + } + + if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) { + idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? + HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; + _set_master_standbymode(oh, idlemode, &v); + } + + _write_sysconfig(v, oh); +} + +/** + * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG + * @oh: struct omap_hwmod * + * + * Force the module into slave idle and master suspend. No return + * value. + */ +static void _sysc_shutdown(struct omap_hwmod *oh) +{ + u32 v; + + if (!oh->sysconfig) + return; + + v = oh->_sysc_cache; + + if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) + _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); + + if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) + _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); + + /* XXX clear OCP AUTOIDLE bit? */ + + _write_sysconfig(v, oh); +} + +/** + * _lookup - find an omap_hwmod by name + * @name: find an omap_hwmod by name + * + * Return a pointer to an omap_hwmod by name, or NULL if not found. + * Caller must hold omap_hwmod_mutex. + */ +static struct omap_hwmod *_lookup(const char *name) +{ + struct omap_hwmod *oh, *temp_oh; + + oh = NULL; + + list_for_each_entry(temp_oh, &omap_hwmod_list, node) { + if (!strcmp(name, temp_oh->name)) { + oh = temp_oh; + break; + } + } + + return oh; +} + +/** + * _init_clocks - clk_get() all clocks associated with this hwmod + * @oh: struct omap_hwmod * + * + * Called by omap_hwmod_late_init() (after omap2_clk_init()). + * Resolves all clock names embedded in the hwmod. Must be called + * with omap_hwmod_mutex held. Returns -EINVAL if the omap_hwmod + * has not yet been registered or if the clocks have already been + * initialized, 0 on success, or a non-zero error on failure. + */ +static int _init_clocks(struct omap_hwmod *oh) +{ + int ret = 0; + + if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) + return -EINVAL; + + pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); + + ret |= _init_main_clk(oh); + ret |= _init_interface_clks(oh); + ret |= _init_opt_clks(oh); + + oh->_state = _HWMOD_STATE_CLKS_INITED; + + return ret; +} + +/** + * _wait_target_ready - wait for a module to leave slave idle + * @oh: struct omap_hwmod * + * + * Wait for a module @oh to leave slave idle. Returns 0 if the module + * does not have an IDLEST bit or if the module successfully leaves + * slave idle; otherwise, pass along the return value of the + * appropriate *_cm_wait_module_ready() function. + */ +static int _wait_target_ready(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + int ret; + + if (!oh) + return -EINVAL; + + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return 0; + + os = *oh->slaves + oh->_mpu_port_index; + + if (!(os->flags & OCPIF_HAS_IDLEST)) + return 0; + + /* XXX check module SIDLEMODE */ + + /* XXX check clock enable states */ + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, + oh->prcm.omap2.idlest_reg_id, + oh->prcm.omap2.idlest_idle_bit); +#if 0 + } else if (cpu_is_omap44xx()) { + ret = omap4_cm_wait_module_ready(oh->prcm.omap4.module_offs, + oh->prcm.omap4.device_offs); +#endif + } else { + BUG(); + }; + + return ret; +} + +/** + * _reset - reset an omap_hwmod + * @oh: struct omap_hwmod * + * + * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be + * enabled for this to work. Must be called with omap_hwmod_mutex + * held. Returns -EINVAL if the hwmod cannot be reset this way or if + * the hwmod is in the wrong state, -ETIMEDOUT if the module did not + * reset in time, or 0 upon success. + */ +static int _reset(struct omap_hwmod *oh) +{ + u32 r, v; + int c; + + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) || + (oh->sysconfig->sysc_flags & SYSS_MISSING)) + return -EINVAL; + + /* clocks must be on for this operation */ + if (oh->_state != _HWMOD_STATE_ENABLED) { + WARN(1, "omap_hwmod: %s: reset can only be entered from " + "enabled state\n", oh->name); + return -EINVAL; + } + + pr_debug("omap_hwmod: %s: resetting\n", oh->name); + + v = oh->_sysc_cache; + r = _set_softreset(oh, &v); + if (r) + return r; + _write_sysconfig(v, oh); + + c = 0; + while (c < MAX_MODULE_RESET_WAIT && + !(omap_hwmod_readl(oh, oh->sysconfig->syss_offs) & + SYSS_RESETDONE_MASK)) { + udelay(1); + c++; + } + + if (c == MAX_MODULE_RESET_WAIT) + WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", + oh->name, MAX_MODULE_RESET_WAIT); + else + pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c); + + /* + * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from + * _wait_target_ready() or _reset() + */ + + return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0; +} + +/** + * _enable - enable an omap_hwmod + * @oh: struct omap_hwmod * + * + * Enables an omap_hwmod @oh such that the MPU can access the hwmod's + * register target. Must be called with omap_hwmod_mutex held. + * Returns -EINVAL if the hwmod is in the wrong state or passes along + * the return value of _wait_target_ready(). + */ +static int _enable(struct omap_hwmod *oh) +{ + int r; + + if (oh->_state != _HWMOD_STATE_INITIALIZED && + oh->_state != _HWMOD_STATE_IDLE && + oh->_state != _HWMOD_STATE_DISABLED) { + WARN(1, "omap_hwmod: %s: enabled state can only be entered " + "from initialized, idle, or disabled state\n", oh->name); + return -EINVAL; + } + + pr_debug("omap_hwmod: %s: enabling\n", oh->name); + + /* XXX mux balls */ + + _add_initiator_dep(oh, mpu_oh); + _enable_clocks(oh); + + if (oh->sysconfig) { + if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) + _update_sysc_cache(oh); + _sysc_enable(oh); + } + + r = _wait_target_ready(oh); + if (!r) + oh->_state = _HWMOD_STATE_ENABLED; + + return r; +} + +/** + * _idle - idle an omap_hwmod + * @oh: struct omap_hwmod * + * + * Idles an omap_hwmod @oh. This should be called once the hwmod has + * no further work. Returns -EINVAL if the hwmod is in the wrong + * state or returns 0. + */ +static int _idle(struct omap_hwmod *oh) +{ + if (oh->_state != _HWMOD_STATE_ENABLED) { + WARN(1, "omap_hwmod: %s: idle state can only be entered from " + "enabled state\n", oh->name); + return -EINVAL; + } + + pr_debug("omap_hwmod: %s: idling\n", oh->name); + + if (oh->sysconfig) + _sysc_idle(oh); + _del_initiator_dep(oh, mpu_oh); + _disable_clocks(oh); + + oh->_state = _HWMOD_STATE_IDLE; + + return 0; +} + +/** + * _shutdown - shutdown an omap_hwmod + * @oh: struct omap_hwmod * + * + * Shut down an omap_hwmod @oh. This should be called when the driver + * used for the hwmod is removed or unloaded or if the driver is not + * used by the system. Returns -EINVAL if the hwmod is in the wrong + * state or returns 0. + */ +static int _shutdown(struct omap_hwmod *oh) +{ + if (oh->_state != _HWMOD_STATE_IDLE && + oh->_state != _HWMOD_STATE_ENABLED) { + WARN(1, "omap_hwmod: %s: disabled state can only be entered " + "from idle, or enabled state\n", oh->name); + return -EINVAL; + } + + pr_debug("omap_hwmod: %s: disabling\n", oh->name); + + if (oh->sysconfig) + _sysc_shutdown(oh); + _del_initiator_dep(oh, mpu_oh); + /* XXX what about the other system initiators here? DMA, tesla, d2d */ + _disable_clocks(oh); + /* XXX Should this code also force-disable the optional clocks? */ + + /* XXX mux any associated balls to safe mode */ + + oh->_state = _HWMOD_STATE_DISABLED; + + return 0; +} + +/** + * _write_clockact_lock - set the module's clockactivity bits + * @oh: struct omap_hwmod * + * @clockact: CLOCKACTIVITY field bits + * + * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh + * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the + * wrong state or returns 0. + */ +static int _write_clockact_lock(struct omap_hwmod *oh, u8 clockact) +{ + u32 v; + + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + v = oh->_sysc_cache; + _set_clockactivity(oh, clockact, &v); + _write_sysconfig(v, oh); + mutex_unlock(&omap_hwmod_mutex); + + return 0; +} + + +/** + * _setup - do initial configuration of omap_hwmod + * @oh: struct omap_hwmod * + * + * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh + * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex + * held. Returns -EINVAL if the hwmod is in the wrong state or returns + * 0. + */ +static int _setup(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + int i; + + if (!oh) + return -EINVAL; + + /* Set iclk autoidle mode */ + if (oh->slaves_cnt > 0) { + for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { + struct clk *c = os->_clk; + + if (!c || IS_ERR(c)) + continue; + + if (os->flags & OCPIF_SWSUP_IDLE) { + /* XXX omap_iclk_deny_idle(c); */ + } else { + /* XXX omap_iclk_allow_idle(c); */ + clk_enable(c); + } + } + } + + oh->_state = _HWMOD_STATE_INITIALIZED; + + _enable(oh); + + if (!(oh->flags & HWMOD_INIT_NO_RESET)) + _reset(oh); + + /* XXX OCP AUTOIDLE bit? */ + /* XXX OCP ENAWAKEUP bit? */ + + if (!(oh->flags & HWMOD_INIT_NO_IDLE)) + _idle(oh); + + return 0; +} + + + +/* Public functions */ + +u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs) +{ + return __raw_readl(oh->_rt_va + reg_offs); +} + +void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) +{ + __raw_writel(v, oh->_rt_va + reg_offs); +} + +/** + * omap_hwmod_register - register a struct omap_hwmod + * @oh: struct omap_hwmod * + * + * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod already + * has been registered by the same name; -EINVAL if the omap_hwmod is in the + * wrong state, or 0 on success. + * + * XXX The data should be copied into bootmem, so the original data + * should be marked __initdata and freed after init. This would allow + * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note + * that the copy process would be relatively complex due to the large number + * of substructures. + */ +int omap_hwmod_register(struct omap_hwmod *oh) +{ + int ret, ms_id; + + if (!oh || (oh->_state != _HWMOD_STATE_UNKNOWN)) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + + pr_debug("omap_hwmod: %s: registering\n", oh->name); + + if (_lookup(oh->name)) { + ret = -EEXIST; + goto ohr_unlock; + } + + ms_id = _find_mpu_port_index(oh); + if (!IS_ERR_VALUE(ms_id)) { + oh->_mpu_port_index = ms_id; + oh->_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); + } else { + oh->_int_flags |= _HWMOD_NO_MPU_PORT; + } + + list_add_tail(&oh->node, &omap_hwmod_list); + + oh->_state = _HWMOD_STATE_REGISTERED; + + ret = 0; + +ohr_unlock: + mutex_unlock(&omap_hwmod_mutex); + return ret; +} + +/** + * omap_hwmod_lookup - look up a registered omap_hwmod by name + * @name: name of the omap_hwmod to look up + * + * Given a @name of an omap_hwmod, return a pointer to the registered + * struct omap_hwmod *, or NULL upon error. + */ +struct omap_hwmod *omap_hwmod_lookup(const char *name) +{ + struct omap_hwmod *oh; + + if (!name) + return NULL; + + mutex_lock(&omap_hwmod_mutex); + oh = _lookup(name); + mutex_unlock(&omap_hwmod_mutex); + + return oh; +} + +/** + * omap_hwmod_for_each - call function for each registered omap_hwmod + * @fn: pointer to a callback function + * + * Call @fn for each registered omap_hwmod, passing @data to each + * function. @fn must return 0 for success or any other value for + * failure. If @fn returns non-zero, the iteration across omap_hwmods + * will stop and the non-zero return value will be passed to the + * caller of omap_hwmod_for_each(). @fn is called with + * omap_hwmod_for_each() held. + */ +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)) +{ + struct omap_hwmod *temp_oh; + int ret; + + if (!fn) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + list_for_each_entry(temp_oh, &omap_hwmod_list, node) { + ret = (*fn)(temp_oh); + if (ret) + break; + } + mutex_unlock(&omap_hwmod_mutex); + + return ret; +} + + +/** + * omap_hwmod_init - init omap_hwmod code and register hwmods + * @ohs: pointer to an array of omap_hwmods to register + * + * Intended to be called early in boot before the clock framework is + * initialized. If @ohs is not null, will register all omap_hwmods + * listed in @ohs that are valid for this chip. Returns -EINVAL if + * omap_hwmod_init() has already been called or 0 otherwise. + */ +int omap_hwmod_init(struct omap_hwmod **ohs) +{ + struct omap_hwmod *oh; + int r; + + if (inited) + return -EINVAL; + + inited = 1; + + if (!ohs) + return 0; + + oh = *ohs; + while (oh) { + if (omap_chip_is(oh->omap_chip)) { + r = omap_hwmod_register(oh); + WARN(r, "omap_hwmod: %s: omap_hwmod_register returned " + "%d\n", oh->name, r); + } + oh = *++ohs; + } + + return 0; +} + +/** + * omap_hwmod_late_init - do some post-clock framework initialization + * + * Must be called after omap2_clk_init(). Resolves the struct clk names + * to struct clk pointers for each registered omap_hwmod. Also calls + * _setup() on each hwmod. Returns 0. + */ +int omap_hwmod_late_init(void) +{ + int r; + + /* XXX check return value */ + r = omap_hwmod_for_each(_init_clocks); + WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); + + mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); + WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", + MPU_INITIATOR_NAME); + + omap_hwmod_for_each(_setup); + + return 0; +} + +/** + * omap_hwmod_unregister - unregister an omap_hwmod + * @oh: struct omap_hwmod * + * + * Unregisters a previously-registered omap_hwmod @oh. There's probably + * no use case for this, so it is likely to be removed in a later version. + * + * XXX Free all of the bootmem-allocated structures here when that is + * implemented. Make it clear that core code is the only code that is + * expected to unregister modules. + */ +int omap_hwmod_unregister(struct omap_hwmod *oh) +{ + if (!oh) + return -EINVAL; + + pr_debug("omap_hwmod: %s: unregistering\n", oh->name); + + mutex_lock(&omap_hwmod_mutex); + list_del(&oh->node); + mutex_unlock(&omap_hwmod_mutex); + + return 0; +} + +/** + * omap_hwmod_enable - enable an omap_hwmod + * @oh: struct omap_hwmod * + * + * Enable an omap_hwomd @oh. Intended to be called by omap_device_enable(). + * Returns -EINVAL on error or passes along the return value from _enable(). + */ +int omap_hwmod_enable(struct omap_hwmod *oh) +{ + int r; + + if (!oh) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + r = _enable(oh); + mutex_unlock(&omap_hwmod_mutex); + + return r; +} + +/** + * omap_hwmod_idle - idle an omap_hwmod + * @oh: struct omap_hwmod * + * + * Idle an omap_hwomd @oh. Intended to be called by omap_device_idle(). + * Returns -EINVAL on error or passes along the return value from _idle(). + */ +int omap_hwmod_idle(struct omap_hwmod *oh) +{ + if (!oh) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + _idle(oh); + mutex_unlock(&omap_hwmod_mutex); + + return 0; +} + +/** + * omap_hwmod_shutdown - shutdown an omap_hwmod + * @oh: struct omap_hwmod * + * + * Shutdown an omap_hwomd @oh. Intended to be called by + * omap_device_shutdown(). Returns -EINVAL on error or passes along + * the return value from _shutdown(). + */ +int omap_hwmod_shutdown(struct omap_hwmod *oh) +{ + if (!oh) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + _shutdown(oh); + mutex_unlock(&omap_hwmod_mutex); + + return 0; +} + +/** + * omap_hwmod_enable_clocks - enable main_clk, all interface clocks + * @oh: struct omap_hwmod *oh + * + * Intended to be called by the omap_device code. + */ +int omap_hwmod_enable_clocks(struct omap_hwmod *oh) +{ + mutex_lock(&omap_hwmod_mutex); + _enable_clocks(oh); + mutex_unlock(&omap_hwmod_mutex); + + return 0; +} + +/** + * omap_hwmod_disable_clocks - disable main_clk, all interface clocks + * @oh: struct omap_hwmod *oh + * + * Intended to be called by the omap_device code. + */ +int omap_hwmod_disable_clocks(struct omap_hwmod *oh) +{ + mutex_lock(&omap_hwmod_mutex); + _disable_clocks(oh); + mutex_unlock(&omap_hwmod_mutex); + + return 0; +} + +/** + * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete + * @oh: struct omap_hwmod *oh + * + * Intended to be called by drivers and core code when all posted + * writes to a device must complete before continuing further + * execution (for example, after clearing some device IRQSTATUS + * register bits) + * + * XXX what about targets with multiple OCP threads? + */ +void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) +{ + BUG_ON(!oh); + + if (!oh->sysconfig || !oh->sysconfig->sysc_flags) { + WARN(1, "omap_device: %s: OCP barrier impossible due to " + "device configuration\n", oh->name); + return; + } + + /* + * Forces posted writes to complete on the OCP thread handling + * register writes + */ + omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); +} + +/** + * omap_hwmod_reset - reset the hwmod + * @oh: struct omap_hwmod * + * + * Under some conditions, a driver may wish to reset the entire device. + * Called from omap_device code. Returns -EINVAL on error or passes along + * the return value from _reset()/_enable(). + */ +int omap_hwmod_reset(struct omap_hwmod *oh) +{ + int r; + + if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED)) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + r = _reset(oh); + if (!r) + r = _enable(oh); + mutex_unlock(&omap_hwmod_mutex); + + return r; +} + +/** + * omap_hwmod_count_resources - count number of struct resources needed by hwmod + * @oh: struct omap_hwmod * + * @res: pointer to the first element of an array of struct resource to fill + * + * Count the number of struct resource array elements necessary to + * contain omap_hwmod @oh resources. Intended to be called by code + * that registers omap_devices. Intended to be used to determine the + * size of a dynamically-allocated struct resource array, before + * calling omap_hwmod_fill_resources(). Returns the number of struct + * resource array elements needed. + * + * XXX This code is not optimized. It could attempt to merge adjacent + * resource IDs. + * + */ +int omap_hwmod_count_resources(struct omap_hwmod *oh) +{ + int ret, i; + + ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt; + + for (i = 0; i < oh->slaves_cnt; i++) + ret += (*oh->slaves + i)->addr_cnt; + + return ret; +} + +/** + * omap_hwmod_fill_resources - fill struct resource array with hwmod data + * @oh: struct omap_hwmod * + * @res: pointer to the first element of an array of struct resource to fill + * + * Fill the struct resource array @res with resource data from the + * omap_hwmod @oh. Intended to be called by code that registers + * omap_devices. See also omap_hwmod_count_resources(). Returns the + * number of array elements filled. + */ +int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) +{ + int i, j; + int r = 0; + + /* For each IRQ, DMA, memory area, fill in array.*/ + + for (i = 0; i < oh->mpu_irqs_cnt; i++) { + (res + r)->start = *(oh->mpu_irqs + i); + (res + r)->end = *(oh->mpu_irqs + i); + (res + r)->flags = IORESOURCE_IRQ; + r++; + } + + for (i = 0; i < oh->sdma_chs_cnt; i++) { + (res + r)->name = (oh->sdma_chs + i)->name; + (res + r)->start = (oh->sdma_chs + i)->dma_ch; + (res + r)->end = (oh->sdma_chs + i)->dma_ch; + (res + r)->flags = IORESOURCE_DMA; + r++; + } + + for (i = 0; i < oh->slaves_cnt; i++) { + struct omap_hwmod_ocp_if *os; + + os = *oh->slaves + i; + + for (j = 0; j < os->addr_cnt; j++) { + (res + r)->start = (os->addr + j)->pa_start; + (res + r)->end = (os->addr + j)->pa_end; + (res + r)->flags = IORESOURCE_MEM; + r++; + } + } + + return r; +} + +/** + * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain + * @oh: struct omap_hwmod * + * + * Return the powerdomain pointer associated with the OMAP module + * @oh's main clock. If @oh does not have a main clk, return the + * powerdomain associated with the interface clock associated with the + * module's MPU port. (XXX Perhaps this should use the SDMA port + * instead?) Returns NULL on error, or a struct powerdomain * on + * success. + */ +struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) +{ + struct clk *c; + + if (!oh) + return NULL; + + if (oh->_clk) { + c = oh->_clk; + } else { + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return NULL; + c = oh->slaves[oh->_mpu_port_index]->_clk; + } + + return c->clkdm->pwrdm.ptr; + +} + +/** + * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh + * @oh: struct omap_hwmod * + * @init_oh: struct omap_hwmod * (initiator) + * + * Add a sleep dependency between the initiator @init_oh and @oh. + * Intended to be called by DSP/Bridge code via platform_data for the + * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge + * code needs to add/del initiator dependencies dynamically + * before/after accessing a device. Returns the return value from + * _add_initiator_dep(). + * + * XXX Keep a usecount in the clockdomain code + */ +int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, + struct omap_hwmod *init_oh) +{ + return _add_initiator_dep(oh, init_oh); +} + +/* + * XXX what about functions for drivers to save/restore ocp_sysconfig + * for context save/restore operations? + */ + +/** + * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh + * @oh: struct omap_hwmod * + * @init_oh: struct omap_hwmod * (initiator) + * + * Remove a sleep dependency between the initiator @init_oh and @oh. + * Intended to be called by DSP/Bridge code via platform_data for the + * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge + * code needs to add/del initiator dependencies dynamically + * before/after accessing a device. Returns the return value from + * _del_initiator_dep(). + * + * XXX Keep a usecount in the clockdomain code + */ +int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, + struct omap_hwmod *init_oh) +{ + return _del_initiator_dep(oh, init_oh); +} + +/** + * omap_hwmod_set_clockact_none - set clockactivity test to BOTH + * @oh: struct omap_hwmod * + * + * On some modules, this function can affect the wakeup latency vs. + * power consumption balance. Intended to be called by the + * omap_device layer. Passes along the return value from + * _write_clockact_lock(). + */ +int omap_hwmod_set_clockact_both(struct omap_hwmod *oh) +{ + return _write_clockact_lock(oh, CLOCKACT_TEST_BOTH); +} + +/** + * omap_hwmod_set_clockact_none - set clockactivity test to MAIN + * @oh: struct omap_hwmod * + * + * On some modules, this function can affect the wakeup latency vs. + * power consumption balance. Intended to be called by the + * omap_device layer. Passes along the return value from + * _write_clockact_lock(). + */ +int omap_hwmod_set_clockact_main(struct omap_hwmod *oh) +{ + return _write_clockact_lock(oh, CLOCKACT_TEST_MAIN); +} + +/** + * omap_hwmod_set_clockact_none - set clockactivity test to ICLK + * @oh: struct omap_hwmod * + * + * On some modules, this function can affect the wakeup latency vs. + * power consumption balance. Intended to be called by the + * omap_device layer. Passes along the return value from + * _write_clockact_lock(). + */ +int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh) +{ + return _write_clockact_lock(oh, CLOCKACT_TEST_ICLK); +} + +/** + * omap_hwmod_set_clockact_none - set clockactivity test to NONE + * @oh: struct omap_hwmod * + * + * On some modules, this function can affect the wakeup latency vs. + * power consumption balance. Intended to be called by the + * omap_device layer. Passes along the return value from + * _write_clockact_lock(). + */ +int omap_hwmod_set_clockact_none(struct omap_hwmod *oh) +{ + return _write_clockact_lock(oh, CLOCKACT_TEST_NONE); +} + +/** + * omap_hwmod_enable_wakeup - allow device to wake up the system + * @oh: struct omap_hwmod * + * + * Sets the module OCP socket ENAWAKEUP bit to allow the module to + * send wakeups to the PRCM. Eventually this should sets PRCM wakeup + * registers to cause the PRCM to receive wakeup events from the + * module. Does not set any wakeup routing registers beyond this + * point - if the module is to wake up any other module or subsystem, + * that must be set separately. Called by omap_device code. Returns + * -EINVAL on error or 0 upon success. + */ +int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) +{ + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + _enable_wakeup(oh); + mutex_unlock(&omap_hwmod_mutex); + + return 0; +} + +/** + * omap_hwmod_disable_wakeup - prevent device from waking the system + * @oh: struct omap_hwmod * + * + * Clears the module OCP socket ENAWAKEUP bit to prevent the module + * from sending wakeups to the PRCM. Eventually this should clear + * PRCM wakeup registers to cause the PRCM to ignore wakeup events + * from the module. Does not set any wakeup routing registers beyond + * this point - if the module is to wake up any other module or + * subsystem, that must be set separately. Called by omap_device + * code. Returns -EINVAL on error or 0 upon success. + */ +int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) +{ + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + _disable_wakeup(oh); + mutex_unlock(&omap_hwmod_mutex); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap_hwmod_2420.h b/arch/arm/mach-omap2/omap_hwmod_2420.h new file mode 100644 index 000000000000..767e4965ac4e --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_2420.h @@ -0,0 +1,141 @@ +/* + * omap_hwmod_2420.h - hardware modules present on the OMAP2420 chips + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX handle crossbar/shared link difference for L3? + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H + +#ifdef CONFIG_ARCH_OMAP2420 + +#include <mach/omap_hwmod.h> +#include <mach/irqs.h> +#include <mach/cpu.h> +#include <mach/dma.h> + +#include "prm-regbits-24xx.h" + +static struct omap_hwmod omap2420_mpu_hwmod; +static struct omap_hwmod omap2420_l3_hwmod; +static struct omap_hwmod omap2420_l4_core_hwmod; + +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap2420_l3__l4_core = { + .master = &omap2420_l3_hwmod, + .slave = &omap2420_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap2420_mpu__l3 = { + .master = &omap2420_mpu_hwmod, + .slave = &omap2420_l3_hwmod, + .user = OCP_USER_MPU, +}; + +/* Slave interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l3_slaves[] = { + &omap2420_mpu__l3, +}; + +/* Master interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = { + &omap2420_l3__l4_core, +}; + +/* L3 */ +static struct omap_hwmod omap2420_l3_hwmod = { + .name = "l3_hwmod", + .masters = omap2420_l3_masters, + .masters_cnt = ARRAY_SIZE(omap2420_l3_masters), + .slaves = omap2420_l3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_l3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +static struct omap_hwmod omap2420_l4_wkup_hwmod; + +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* Slave interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { + &omap2420_l3__l4_core, +}; + +/* Master interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { + &omap2420_l4_core__l4_wkup, +}; + +/* L4 CORE */ +static struct omap_hwmod omap2420_l4_core_hwmod = { + .name = "l4_core_hwmod", + .masters = omap2420_l4_core_masters, + .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), + .slaves = omap2420_l4_core_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* Slave interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { + &omap2420_l4_core__l4_wkup, +}; + +/* Master interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { +}; + +/* L4 WKUP */ +static struct omap_hwmod omap2420_l4_wkup_hwmod = { + .name = "l4_wkup_hwmod", + .masters = omap2420_l4_wkup_masters, + .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), + .slaves = omap2420_l4_wkup_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* Master interfaces on the MPU device */ +static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { + &omap2420_mpu__l3, +}; + +/* MPU */ +static struct omap_hwmod omap2420_mpu_hwmod = { + .name = "mpu_hwmod", + .clkdev_dev_id = NULL, + .clkdev_con_id = "mpu_ck", + .masters = omap2420_mpu_masters, + .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +static __initdata struct omap_hwmod *omap2420_hwmods[] = { + &omap2420_l3_hwmod, + &omap2420_l4_core_hwmod, + &omap2420_l4_wkup_hwmod, + &omap2420_mpu_hwmod, + NULL, +}; + +#else +# define omap2420_hwmods 0 +#endif + +#endif + + diff --git a/arch/arm/mach-omap2/omap_hwmod_2430.h b/arch/arm/mach-omap2/omap_hwmod_2430.h new file mode 100644 index 000000000000..a412be6420ec --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_2430.h @@ -0,0 +1,143 @@ +/* + * omap_hwmod_2430.h - hardware modules present on the OMAP2430 chips + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX handle crossbar/shared link difference for L3? + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H + +#ifdef CONFIG_ARCH_OMAP2430 + +#include <mach/omap_hwmod.h> +#include <mach/irqs.h> +#include <mach/cpu.h> +#include <mach/dma.h> + +#include "prm-regbits-24xx.h" + +static struct omap_hwmod omap2430_mpu_hwmod; +static struct omap_hwmod omap2430_l3_hwmod; +static struct omap_hwmod omap2430_l4_core_hwmod; + +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap2430_l3__l4_core = { + .master = &omap2430_l3_hwmod, + .slave = &omap2430_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap2430_mpu__l3 = { + .master = &omap2430_mpu_hwmod, + .slave = &omap2430_l3_hwmod, + .user = OCP_USER_MPU, +}; + +/* Slave interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l3_slaves[] = { + &omap2430_mpu__l3, +}; + +/* Master interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = { + &omap2430_l3__l4_core, +}; + +/* L3 */ +static struct omap_hwmod omap2430_l3_hwmod = { + .name = "l3_hwmod", + .masters = omap2430_l3_masters, + .masters_cnt = ARRAY_SIZE(omap2430_l3_masters), + .slaves = omap2430_l3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_l3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +static struct omap_hwmod omap2430_l4_wkup_hwmod; +static struct omap_hwmod omap2430_mmc1_hwmod; +static struct omap_hwmod omap2430_mmc2_hwmod; + +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* Slave interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { + &omap2430_l3__l4_core, +}; + +/* Master interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { + &omap2430_l4_core__l4_wkup, +}; + +/* L4 CORE */ +static struct omap_hwmod omap2430_l4_core_hwmod = { + .name = "l4_core_hwmod", + .masters = omap2430_l4_core_masters, + .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), + .slaves = omap2430_l4_core_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* Slave interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { + &omap2430_l4_core__l4_wkup, +}; + +/* Master interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { +}; + +/* L4 WKUP */ +static struct omap_hwmod omap2430_l4_wkup_hwmod = { + .name = "l4_wkup_hwmod", + .masters = omap2430_l4_wkup_masters, + .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), + .slaves = omap2430_l4_wkup_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* Master interfaces on the MPU device */ +static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { + &omap2430_mpu__l3, +}; + +/* MPU */ +static struct omap_hwmod omap2430_mpu_hwmod = { + .name = "mpu_hwmod", + .clkdev_dev_id = NULL, + .clkdev_con_id = "mpu_ck", + .masters = omap2430_mpu_masters, + .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +static __initdata struct omap_hwmod *omap2430_hwmods[] = { + &omap2430_l3_hwmod, + &omap2430_l4_core_hwmod, + &omap2430_l4_wkup_hwmod, + &omap2430_mpu_hwmod, + NULL, +}; + +#else +# define omap2430_hwmods 0 +#endif + +#endif + + diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h new file mode 100644 index 000000000000..1e069f831575 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_34xx.h @@ -0,0 +1,168 @@ +/* + * omap_hwmod_34xx.h - hardware modules present on the OMAP34xx chips + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H + +#ifdef CONFIG_ARCH_OMAP34XX + +#include <mach/omap_hwmod.h> +#include <mach/irqs.h> +#include <mach/cpu.h> +#include <mach/dma.h> + +#include "prm-regbits-34xx.h" + +static struct omap_hwmod omap34xx_mpu_hwmod; +static struct omap_hwmod omap34xx_l3_hwmod; +static struct omap_hwmod omap34xx_l4_core_hwmod; +static struct omap_hwmod omap34xx_l4_per_hwmod; + +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap34xx_l3__l4_core = { + .master = &omap34xx_l3_hwmod, + .slave = &omap34xx_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L3 -> L4_PER interface */ +static struct omap_hwmod_ocp_if omap34xx_l3__l4_per = { + .master = &omap34xx_l3_hwmod, + .slave = &omap34xx_l4_per_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap34xx_mpu__l3 = { + .master = &omap34xx_mpu_hwmod, + .slave = &omap34xx_l3_hwmod, + .user = OCP_USER_MPU, +}; + +/* Slave interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap34xx_l3_slaves[] = { + &omap34xx_mpu__l3, +}; + +/* Master interfaces on the L3 interconnect */ +static struct omap_hwmod_ocp_if *omap34xx_l3_masters[] = { + &omap34xx_l3__l4_core, + &omap34xx_l3__l4_per, +}; + +/* L3 */ +static struct omap_hwmod omap34xx_l3_hwmod = { + .name = "l3_hwmod", + .masters = omap34xx_l3_masters, + .masters_cnt = ARRAY_SIZE(omap34xx_l3_masters), + .slaves = omap34xx_l3_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_l3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +static struct omap_hwmod omap34xx_l4_wkup_hwmod; + +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__l4_wkup = { + .master = &omap34xx_l4_core_hwmod, + .slave = &omap34xx_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* Slave interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap34xx_l4_core_slaves[] = { + &omap34xx_l3__l4_core, +}; + +/* Master interfaces on the L4_CORE interconnect */ +static struct omap_hwmod_ocp_if *omap34xx_l4_core_masters[] = { + &omap34xx_l4_core__l4_wkup, +}; + +/* L4 CORE */ +static struct omap_hwmod omap34xx_l4_core_hwmod = { + .name = "l4_core_hwmod", + .masters = omap34xx_l4_core_masters, + .masters_cnt = ARRAY_SIZE(omap34xx_l4_core_masters), + .slaves = omap34xx_l4_core_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_l4_core_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* Slave interfaces on the L4_PER interconnect */ +static struct omap_hwmod_ocp_if *omap34xx_l4_per_slaves[] = { + &omap34xx_l3__l4_per, +}; + +/* Master interfaces on the L4_PER interconnect */ +static struct omap_hwmod_ocp_if *omap34xx_l4_per_masters[] = { +}; + +/* L4 PER */ +static struct omap_hwmod omap34xx_l4_per_hwmod = { + .name = "l4_per_hwmod", + .masters = omap34xx_l4_per_masters, + .masters_cnt = ARRAY_SIZE(omap34xx_l4_per_masters), + .slaves = omap34xx_l4_per_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_l4_per_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* Slave interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_slaves[] = { + &omap34xx_l4_core__l4_wkup, +}; + +/* Master interfaces on the L4_WKUP interconnect */ +static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_masters[] = { +}; + +/* L4 WKUP */ +static struct omap_hwmod omap34xx_l4_wkup_hwmod = { + .name = "l4_wkup_hwmod", + .masters = omap34xx_l4_wkup_masters, + .masters_cnt = ARRAY_SIZE(omap34xx_l4_wkup_masters), + .slaves = omap34xx_l4_wkup_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_l4_wkup_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* Master interfaces on the MPU device */ +static struct omap_hwmod_ocp_if *omap34xx_mpu_masters[] = { + &omap34xx_mpu__l3, +}; + +/* MPU */ +static struct omap_hwmod omap34xx_mpu_hwmod = { + .name = "mpu_hwmod", + .clkdev_dev_id = NULL, + .clkdev_con_id = "arm_fck", + .masters = omap34xx_mpu_masters, + .masters_cnt = ARRAY_SIZE(omap34xx_mpu_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +static __initdata struct omap_hwmod *omap34xx_hwmods[] = { + &omap34xx_l3_hwmod, + &omap34xx_l4_core_hwmod, + &omap34xx_l4_per_hwmod, + &omap34xx_l4_wkup_hwmod, + &omap34xx_mpu_hwmod, + NULL, +}; + +#else +# define omap34xx_hwmods 0 +#endif + +#endif + + diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 6cc375a275be..1b4c1600f8d8 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -20,13 +20,16 @@ */ #include <linux/kernel.h> -#include <linux/timer.h> +#include <linux/sched.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/module.h> #include <mach/clock.h> #include <mach/board.h> +#include <mach/powerdomain.h> +#include <mach/clockdomain.h> #include "prm.h" #include "cm.h" @@ -48,7 +51,9 @@ int omap2_pm_debug; regs[reg_count++].val = __raw_readl(reg) #define DUMP_INTC_REG(reg, off) \ regs[reg_count].name = #reg; \ - regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off))) + regs[reg_count++].val = __raw_readl(OMAP2_IO_ADDRESS(0x480fe000 + (off))) + +static int __init pm_dbg_init(void); void omap2_pm_dump(int mode, int resume, unsigned int us) { @@ -150,3 +155,425 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) for (i = 0; i < reg_count; i++) printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val); } + +#ifdef CONFIG_DEBUG_FS +#include <linux/debugfs.h> +#include <linux/seq_file.h> + +static void pm_dbg_regset_store(u32 *ptr); + +struct dentry *pm_dbg_dir; + +static int pm_dbg_init_done; + +enum { + DEBUG_FILE_COUNTERS = 0, + DEBUG_FILE_TIMERS, +}; + +struct pm_module_def { + char name[8]; /* Name of the module */ + short type; /* CM or PRM */ + unsigned short offset; + int low; /* First register address on this module */ + int high; /* Last register address on this module */ +}; + +#define MOD_CM 0 +#define MOD_PRM 1 + +static const struct pm_module_def *pm_dbg_reg_modules; +static const struct pm_module_def omap3_pm_reg_modules[] = { + { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c }, + { "OCP", MOD_CM, OCP_MOD, 0, 0x10 }, + { "MPU", MOD_CM, MPU_MOD, 4, 0x4c }, + { "CORE", MOD_CM, CORE_MOD, 0, 0x4c }, + { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c }, + { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 }, + { "CCR", MOD_CM, PLL_MOD, 0, 0x70 }, + { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c }, + { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c }, + { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c }, + { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 }, + { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 }, + { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c }, + + { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc }, + { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c }, + { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 }, + { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 }, + { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 }, + { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 }, + { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 }, + { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 }, + { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 }, + { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 }, + { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 }, + { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 }, + { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 }, + { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 }, + { "", 0, 0, 0, 0 }, +}; + +#define PM_DBG_MAX_REG_SETS 4 + +static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS]; + +static int pm_dbg_get_regset_size(void) +{ + static int regset_size; + + if (regset_size == 0) { + int i = 0; + + while (pm_dbg_reg_modules[i].name[0] != 0) { + regset_size += pm_dbg_reg_modules[i].high + + 4 - pm_dbg_reg_modules[i].low; + i++; + } + } + return regset_size; +} + +static int pm_dbg_show_regs(struct seq_file *s, void *unused) +{ + int i, j; + unsigned long val; + int reg_set = (int)s->private; + u32 *ptr; + void *store = NULL; + int regs; + int linefeed; + + if (reg_set == 0) { + store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL); + ptr = store; + pm_dbg_regset_store(ptr); + } else { + ptr = pm_dbg_reg_set[reg_set - 1]; + } + + i = 0; + + while (pm_dbg_reg_modules[i].name[0] != 0) { + regs = 0; + linefeed = 0; + if (pm_dbg_reg_modules[i].type == MOD_CM) + seq_printf(s, "MOD: CM_%s (%08x)\n", + pm_dbg_reg_modules[i].name, + (u32)(OMAP3430_CM_BASE + + pm_dbg_reg_modules[i].offset)); + else + seq_printf(s, "MOD: PRM_%s (%08x)\n", + pm_dbg_reg_modules[i].name, + (u32)(OMAP3430_PRM_BASE + + pm_dbg_reg_modules[i].offset)); + + for (j = pm_dbg_reg_modules[i].low; + j <= pm_dbg_reg_modules[i].high; j += 4) { + val = *(ptr++); + if (val != 0) { + regs++; + if (linefeed) { + seq_printf(s, "\n"); + linefeed = 0; + } + seq_printf(s, " %02x => %08lx", j, val); + if (regs % 4 == 0) + linefeed = 1; + } + } + seq_printf(s, "\n"); + i++; + } + + if (store != NULL) + kfree(store); + + return 0; +} + +static void pm_dbg_regset_store(u32 *ptr) +{ + int i, j; + u32 val; + + i = 0; + + while (pm_dbg_reg_modules[i].name[0] != 0) { + for (j = pm_dbg_reg_modules[i].low; + j <= pm_dbg_reg_modules[i].high; j += 4) { + if (pm_dbg_reg_modules[i].type == MOD_CM) + val = cm_read_mod_reg( + pm_dbg_reg_modules[i].offset, j); + else + val = prm_read_mod_reg( + pm_dbg_reg_modules[i].offset, j); + *(ptr++) = val; + } + i++; + } +} + +int pm_dbg_regset_save(int reg_set) +{ + if (pm_dbg_reg_set[reg_set-1] == NULL) + return -EINVAL; + + pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]); + + return 0; +} + +static const char pwrdm_state_names[][4] = { + "OFF", + "RET", + "INA", + "ON" +}; + +void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) +{ + s64 t; + + if (!pm_dbg_init_done) + return ; + + /* Update timer for previous state */ + t = sched_clock(); + + pwrdm->state_timer[prev] += t - pwrdm->timer; + + pwrdm->timer = t; +} + +static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user) +{ + struct seq_file *s = (struct seq_file *)user; + + if (strcmp(clkdm->name, "emu_clkdm") == 0 || + strcmp(clkdm->name, "wkup_clkdm") == 0 || + strncmp(clkdm->name, "dpll", 4) == 0) + return 0; + + seq_printf(s, "%s->%s (%d)", clkdm->name, + clkdm->pwrdm.ptr->name, + atomic_read(&clkdm->usecount)); + seq_printf(s, "\n"); + + return 0; +} + +static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user) +{ + struct seq_file *s = (struct seq_file *)user; + int i; + + if (strcmp(pwrdm->name, "emu_pwrdm") == 0 || + strcmp(pwrdm->name, "wkup_pwrdm") == 0 || + strncmp(pwrdm->name, "dpll", 4) == 0) + return 0; + + if (pwrdm->state != pwrdm_read_pwrst(pwrdm)) + printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n", + pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm)); + + seq_printf(s, "%s (%s)", pwrdm->name, + pwrdm_state_names[pwrdm->state]); + for (i = 0; i < 4; i++) + seq_printf(s, ",%s:%d", pwrdm_state_names[i], + pwrdm->state_counter[i]); + + seq_printf(s, "\n"); + + return 0; +} + +static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user) +{ + struct seq_file *s = (struct seq_file *)user; + int i; + + if (strcmp(pwrdm->name, "emu_pwrdm") == 0 || + strcmp(pwrdm->name, "wkup_pwrdm") == 0 || + strncmp(pwrdm->name, "dpll", 4) == 0) + return 0; + + pwrdm_state_switch(pwrdm); + + seq_printf(s, "%s (%s)", pwrdm->name, + pwrdm_state_names[pwrdm->state]); + + for (i = 0; i < 4; i++) + seq_printf(s, ",%s:%lld", pwrdm_state_names[i], + pwrdm->state_timer[i]); + + seq_printf(s, "\n"); + return 0; +} + +static int pm_dbg_show_counters(struct seq_file *s, void *unused) +{ + pwrdm_for_each(pwrdm_dbg_show_counter, s); + clkdm_for_each(clkdm_dbg_show_counter, s); + + return 0; +} + +static int pm_dbg_show_timers(struct seq_file *s, void *unused) +{ + pwrdm_for_each(pwrdm_dbg_show_timer, s); + return 0; +} + +static int pm_dbg_open(struct inode *inode, struct file *file) +{ + switch ((int)inode->i_private) { + case DEBUG_FILE_COUNTERS: + return single_open(file, pm_dbg_show_counters, + &inode->i_private); + case DEBUG_FILE_TIMERS: + default: + return single_open(file, pm_dbg_show_timers, + &inode->i_private); + }; +} + +static int pm_dbg_reg_open(struct inode *inode, struct file *file) +{ + return single_open(file, pm_dbg_show_regs, inode->i_private); +} + +static const struct file_operations debug_fops = { + .open = pm_dbg_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations debug_reg_fops = { + .open = pm_dbg_reg_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +int pm_dbg_regset_init(int reg_set) +{ + char name[2]; + + if (!pm_dbg_init_done) + pm_dbg_init(); + + if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS || + pm_dbg_reg_set[reg_set-1] != NULL) + return -EINVAL; + + pm_dbg_reg_set[reg_set-1] = + kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL); + + if (pm_dbg_reg_set[reg_set-1] == NULL) + return -ENOMEM; + + if (pm_dbg_dir != NULL) { + sprintf(name, "%d", reg_set); + + (void) debugfs_create_file(name, S_IRUGO, + pm_dbg_dir, (void *)reg_set, &debug_reg_fops); + } + + return 0; +} + +static int pwrdm_suspend_get(void *data, u64 *val) +{ + *val = omap3_pm_get_suspend_state((struct powerdomain *)data); + + if (*val >= 0) + return 0; + return *val; +} + +static int pwrdm_suspend_set(void *data, u64 val) +{ + return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val); +} + +DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get, + pwrdm_suspend_set, "%llu\n"); + +static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir) +{ + int i; + s64 t; + struct dentry *d; + + t = sched_clock(); + + for (i = 0; i < 4; i++) + pwrdm->state_timer[i] = 0; + + pwrdm->timer = t; + + if (strncmp(pwrdm->name, "dpll", 4) == 0) + return 0; + + d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir); + + (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d, + (void *)pwrdm, &pwrdm_suspend_fops); + + return 0; +} + +static int __init pm_dbg_init(void) +{ + int i; + struct dentry *d; + char name[2]; + + if (pm_dbg_init_done) + return 0; + + if (cpu_is_omap34xx()) + pm_dbg_reg_modules = omap3_pm_reg_modules; + else { + printk(KERN_ERR "%s: only OMAP3 supported\n", __func__); + return -ENODEV; + } + + d = debugfs_create_dir("pm_debug", NULL); + if (IS_ERR(d)) + return PTR_ERR(d); + + (void) debugfs_create_file("count", S_IRUGO, + d, (void *)DEBUG_FILE_COUNTERS, &debug_fops); + (void) debugfs_create_file("time", S_IRUGO, + d, (void *)DEBUG_FILE_TIMERS, &debug_fops); + + pwrdm_for_each(pwrdms_setup, (void *)d); + + pm_dbg_dir = debugfs_create_dir("registers", d); + if (IS_ERR(pm_dbg_dir)) + return PTR_ERR(pm_dbg_dir); + + (void) debugfs_create_file("current", S_IRUGO, + pm_dbg_dir, (void *)0, &debug_reg_fops); + + for (i = 0; i < PM_DBG_MAX_REG_SETS; i++) + if (pm_dbg_reg_set[i] != NULL) { + sprintf(name, "%d", i+1); + (void) debugfs_create_file(name, S_IRUGO, + pm_dbg_dir, (void *)(i+1), &debug_reg_fops); + + } + + pm_dbg_init_done = 1; + + return 0; +} +arch_initcall(pm_dbg_init); + +#else +void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {} +#endif diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 21201cd4117b..8400f5768923 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -11,12 +11,23 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PM_H #define __ARCH_ARM_MACH_OMAP2_PM_H +#include <mach/powerdomain.h> + +extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); +extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); + #ifdef CONFIG_PM_DEBUG extern void omap2_pm_dump(int mode, int resume, unsigned int us); extern int omap2_pm_debug; +extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); +extern int pm_dbg_regset_save(int reg_set); +extern int pm_dbg_regset_init(int reg_set); #else #define omap2_pm_dump(mode, resume, us) do {} while (0); #define omap2_pm_debug 0 +#define pm_dbg_update_time(pwrdm, prev) do {} while (0); +#define pm_dbg_regset_save(reg_set) do {} while (0); +#define pm_dbg_regset_init(reg_set) do {} while (0); #endif /* CONFIG_PM_DEBUG */ extern void omap24xx_idle_loop_suspend(void); diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 528dbdc26e23..bff5c4e89742 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -333,7 +333,7 @@ static struct platform_suspend_ops omap_pm_ops = { .valid = suspend_valid_only_mem, }; -static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm) +static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused) { omap2_clkdm_allow_idle(clkdm); return 0; @@ -385,7 +385,7 @@ static void __init prcm_setup_regs(void) omap2_clkdm_sleep(gfx_clkdm); /* Enable clockdomain hardware-supervised control for all clkdms */ - clkdm_for_each(_pm_clkdm_enable_hwsup); + clkdm_for_each(_pm_clkdm_enable_hwsup, NULL); /* Enable clock autoidle for all domains */ cm_write_mod_reg(OMAP24XX_AUTO_CAM | diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 488d595d8e4b..0ff5a6c53aa0 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -170,6 +170,8 @@ static void omap_sram_idle(void) printk(KERN_ERR "Invalid mpu state in sram_idle\n"); return; } + pwrdm_pre_transition(); + omap2_gpio_prepare_for_retention(); omap_uart_prepare_idle(0); omap_uart_prepare_idle(1); @@ -182,6 +184,9 @@ static void omap_sram_idle(void) omap_uart_resume_idle(1); omap_uart_resume_idle(0); omap2_gpio_resume_after_retention(); + + pwrdm_post_transition(); + } /* @@ -271,6 +276,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) if (sleep_switch) { omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); pwrdm_wait_transition(pwrdm); + pwrdm_state_switch(pwrdm); } err: @@ -658,14 +664,38 @@ static void __init prcm_setup_regs(void) omap3_d2d_idle(); } -static int __init pwrdms_setup(struct powerdomain *pwrdm) +int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) +{ + struct power_state *pwrst; + + list_for_each_entry(pwrst, &pwrst_list, node) { + if (pwrst->pwrdm == pwrdm) + return pwrst->next_state; + } + return -EINVAL; +} + +int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) +{ + struct power_state *pwrst; + + list_for_each_entry(pwrst, &pwrst_list, node) { + if (pwrst->pwrdm == pwrdm) { + pwrst->next_state = state; + return 0; + } + } + return -EINVAL; +} + +static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) { struct power_state *pwrst; if (!pwrdm->pwrsts) return 0; - pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL); + pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); if (!pwrst) return -ENOMEM; pwrst->pwrdm = pwrdm; @@ -683,7 +713,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm) * supported. Initiate sleep transition for other clockdomains, if * they are not used */ -static int __init clkdms_setup(struct clockdomain *clkdm) +static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) { if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) omap2_clkdm_allow_idle(clkdm); @@ -716,13 +746,13 @@ static int __init omap3_pm_init(void) goto err1; } - ret = pwrdm_for_each(pwrdms_setup); + ret = pwrdm_for_each(pwrdms_setup, NULL); if (ret) { printk(KERN_ERR "Failed to setup powerdomains\n"); goto err2; } - (void) clkdm_for_each(clkdms_setup); + (void) clkdm_for_each(clkdms_setup, NULL); mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); if (mpu_pwrdm == NULL) { diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 983f1cb676be..2594cbff3947 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -35,6 +35,13 @@ #include <mach/powerdomain.h> #include <mach/clockdomain.h> +#include "pm.h" + +enum { + PWRDM_STATE_NOW = 0, + PWRDM_STATE_PREV, +}; + /* pwrdm_list contains all registered struct powerdomains */ static LIST_HEAD(pwrdm_list); @@ -83,7 +90,7 @@ static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm, if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip)) return ERR_PTR(-EINVAL); - for (pd = deps; pd; pd++) { + for (pd = deps; pd->pwrdm_name; pd++) { if (!omap_chip_is(pd->omap_chip)) continue; @@ -96,12 +103,71 @@ static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm, } - if (!pd) + if (!pd->pwrdm_name) return ERR_PTR(-ENOENT); return pd->pwrdm; } +static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) +{ + + int prev; + int state; + + if (pwrdm == NULL) + return -EINVAL; + + state = pwrdm_read_pwrst(pwrdm); + + switch (flag) { + case PWRDM_STATE_NOW: + prev = pwrdm->state; + break; + case PWRDM_STATE_PREV: + prev = pwrdm_read_prev_pwrst(pwrdm); + if (pwrdm->state != prev) + pwrdm->state_counter[prev]++; + break; + default: + return -EINVAL; + } + + if (state != prev) + pwrdm->state_counter[state]++; + + pm_dbg_update_time(pwrdm, prev); + + pwrdm->state = state; + + return 0; +} + +static int _pwrdm_pre_transition_cb(struct powerdomain *pwrdm, void *unused) +{ + pwrdm_clear_all_prev_pwrst(pwrdm); + _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW); + return 0; +} + +static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) +{ + _pwrdm_state_switch(pwrdm, PWRDM_STATE_PREV); + return 0; +} + +static __init void _pwrdm_setup(struct powerdomain *pwrdm) +{ + int i; + + for (i = 0; i < 4; i++) + pwrdm->state_counter[i] = 0; + + pwrdm_wait_transition(pwrdm); + pwrdm->state = pwrdm_read_pwrst(pwrdm); + pwrdm->state_counter[pwrdm->state] = 1; + +} /* Public functions */ @@ -117,9 +183,12 @@ void pwrdm_init(struct powerdomain **pwrdm_list) { struct powerdomain **p = NULL; - if (pwrdm_list) - for (p = pwrdm_list; *p; p++) + if (pwrdm_list) { + for (p = pwrdm_list; *p; p++) { pwrdm_register(*p); + _pwrdm_setup(*p); + } + } } /** @@ -217,7 +286,8 @@ struct powerdomain *pwrdm_lookup(const char *name) * anything else to indicate failure; or -EINVAL if the function * pointer is null. */ -int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm)) +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), + void *user) { struct powerdomain *temp_pwrdm; unsigned long flags; @@ -228,7 +298,7 @@ int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm)) read_lock_irqsave(&pwrdm_rwlock, flags); list_for_each_entry(temp_pwrdm, &pwrdm_list, node) { - ret = (*fn)(temp_pwrdm); + ret = (*fn)(temp_pwrdm, user); if (ret) break; } @@ -1110,4 +1180,36 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) return 0; } +int pwrdm_state_switch(struct powerdomain *pwrdm) +{ + return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW); +} + +int pwrdm_clkdm_state_switch(struct clockdomain *clkdm) +{ + if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) { + pwrdm_wait_transition(clkdm->pwrdm.ptr); + return pwrdm_state_switch(clkdm->pwrdm.ptr); + } + + return -EINVAL; +} +int pwrdm_clk_state_switch(struct clk *clk) +{ + if (clk != NULL && clk->clkdm != NULL) + return pwrdm_clkdm_state_switch(clk->clkdm); + return -EINVAL; +} + +int pwrdm_pre_transition(void) +{ + pwrdm_for_each(_pwrdm_pre_transition_cb, NULL); + return 0; +} + +int pwrdm_post_transition(void) +{ + pwrdm_for_each(_pwrdm_post_transition_cb, NULL); + return 0; +} diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 9937e2814696..03c467c35f54 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -17,11 +17,11 @@ #include "prcm-common.h" #define OMAP2420_PRM_REGADDR(module, reg) \ - IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) + OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) #define OMAP2430_PRM_REGADDR(module, reg) \ - IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) + OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) #define OMAP34XX_PRM_REGADDR(module, reg) \ - IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) + OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) /* * Architecture-specific global PRM registers diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index 1a8bbd094066..0837eda5f2b6 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h @@ -48,9 +48,9 @@ static inline u32 sms_read_reg(u16 reg) return __raw_readl(OMAP_SMS_REGADDR(reg)); } #else -#define OMAP242X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) -#define OMAP243X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) -#define OMAP34XX_SDRC_REGADDR(reg) IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) +#define OMAP242X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) +#define OMAP243X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) +#define OMAP34XX_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) #endif /* __ASSEMBLER__ */ #endif diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index ce22344b94e7..3a529c77daa8 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -73,7 +73,7 @@ static LIST_HEAD(uart_list); static struct plat_serial8250_port serial_platform_data0[] = { { - .membase = IO_ADDRESS(OMAP_UART1_BASE), + .membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE), .mapbase = OMAP_UART1_BASE, .irq = 72, .flags = UPF_BOOT_AUTOCONF, @@ -87,7 +87,7 @@ static struct plat_serial8250_port serial_platform_data0[] = { static struct plat_serial8250_port serial_platform_data1[] = { { - .membase = IO_ADDRESS(OMAP_UART2_BASE), + .membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE), .mapbase = OMAP_UART2_BASE, .irq = 73, .flags = UPF_BOOT_AUTOCONF, @@ -101,7 +101,7 @@ static struct plat_serial8250_port serial_platform_data1[] = { static struct plat_serial8250_port serial_platform_data2[] = { { - .membase = IO_ADDRESS(OMAP_UART3_BASE), + .membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE), .mapbase = OMAP_UART3_BASE, .irq = 74, .flags = UPF_BOOT_AUTOCONF, @@ -123,6 +123,21 @@ static struct plat_serial8250_port serial_platform_data2[] = { } }; +#ifdef CONFIG_ARCH_OMAP4 +static struct plat_serial8250_port serial_platform_data3[] = { + { + .membase = IO_ADDRESS(OMAP_UART4_BASE), + .mapbase = OMAP_UART4_BASE, + .irq = 70, + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = OMAP24XX_BASE_BAUD * 16, + }, { + .flags = 0 + } +}; +#endif static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, int offset) { @@ -470,7 +485,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) uart->padconf = 0; } - p->flags |= UPF_SHARE_IRQ; + p->irqflags |= IRQF_SHARED; ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, "serial idle", (void *)uart); WARN_ON(ret); @@ -560,12 +575,22 @@ static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = { }, }, }, +#ifdef CONFIG_ARCH_OMAP4 + { + .pdev = { + .name = "serial8250", + .id = 3 + .dev = { + .platform_data = serial_platform_data3, + }, + }, + }, +#endif }; -void __init omap_serial_init(void) +void __init omap_serial_early_init(void) { int i; - const struct omap_uart_config *info; char name[16]; /* @@ -574,23 +599,12 @@ void __init omap_serial_init(void) * if not needed. */ - info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config); - - if (info == NULL) - return; - for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { struct omap_uart_state *uart = &omap_uart[i]; struct platform_device *pdev = &uart->pdev; struct device *dev = &pdev->dev; struct plat_serial8250_port *p = dev->platform_data; - if (!(info->enabled_uarts & (1 << i))) { - p->membase = NULL; - p->mapbase = 0; - continue; - } - sprintf(name, "uart%d_ick", i+1); uart->ick = clk_get(NULL, name); if (IS_ERR(uart->ick)) { @@ -605,8 +619,11 @@ void __init omap_serial_init(void) uart->fck = NULL; } - if (!uart->ick || !uart->fck) - continue; + /* FIXME: Remove this once the clkdev is ready */ + if (!cpu_is_omap44xx()) { + if (!uart->ick || !uart->fck) + continue; + } uart->num = i; p->private_data = uart; @@ -617,6 +634,18 @@ void __init omap_serial_init(void) p->irq += 32; omap_uart_enable_clocks(uart); + } +} + +void __init omap_serial_init(void) +{ + int i; + + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { + struct omap_uart_state *uart = &omap_uart[i]; + struct platform_device *pdev = &uart->pdev; + struct device *dev = &pdev->dev; + omap_uart_reset(uart); omap_uart_idle_init(uart); diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index bb299851116d..9b62208658bc 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S @@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl: prcm_mask_val: .word 0xFFFF3FFC omap242x_sdi_timer_32ksynct_cr: - .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) + .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) ENTRY(omap242x_sram_ddr_init_sz) .word . - omap242x_sram_ddr_init @@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl: ddr_prcm_mask_val: .word 0xFFFF3FFC omap242x_srs_timer_32ksynct: - .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) + .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) ENTRY(omap242x_sram_reprogram_sdrc_sz) .word . - omap242x_sram_reprogram_sdrc diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index 9955abcaeb31..df2cd9277c00 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl: prcm_mask_val: .word 0xFFFF3FFC omap243x_sdi_timer_32ksynct_cr: - .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) + .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) ENTRY(omap243x_sram_ddr_init_sz) .word . - omap243x_sram_ddr_init @@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl: ddr_prcm_mask_val: .word 0xFFFF3FFC omap243x_srs_timer_32ksynct: - .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) + .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) ENTRY(omap243x_sram_reprogram_sdrc_sz) .word . - omap243x_sram_reprogram_sdrc diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 97eeeebcb066..e2338c0aebcf 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -231,7 +231,7 @@ static void __init omap2_gp_clocksource_init(void) static void __init omap2_gp_timer_init(void) { #ifdef CONFIG_LOCAL_TIMERS - twd_base = IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE); + twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE); #endif omap_dm_timer_init(); diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 739e59e8025c..1145a2562b0f 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -31,15 +31,6 @@ #include <mach/mux.h> #include <mach/usb.h> -#define OTG_SYSCONFIG (OMAP34XX_HSUSB_OTG_BASE + 0x404) - -static void __init usb_musb_pm_init(void) -{ - /* Ensure force-idle mode for OTG controller */ - if (cpu_is_omap34xx()) - omap_writel(0, OTG_SYSCONFIG); -} - #ifdef CONFIG_USB_MUSB_SOC static struct resource musb_resources[] = { @@ -173,13 +164,10 @@ void __init usb_musb_init(void) printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); return; } - - usb_musb_pm_init(); } #else void __init usb_musb_init(void) { - usb_musb_pm_init(); } #endif /* CONFIG_USB_MUSB_SOC */ diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index efe85d095190..64b3f52bd9b2 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -120,6 +120,10 @@ config OMAP_MBOX_FWK config OMAP_IOMMU tristate +config OMAP_IOMMU_DEBUG + depends on OMAP_IOMMU + tristate + choice prompt "System timer" default OMAP_MPU_TIMER @@ -183,6 +187,19 @@ config OMAP_SERIAL_WAKE to data on the serial RX line. This allows you to wake the system from serial console. +choice + prompt "OMAP PM layer selection" + depends on ARCH_OMAP + default OMAP_PM_NOOP + +config OMAP_PM_NONE + bool "No PM layer" + +config OMAP_PM_NOOP + bool "No-op/debug PM layer" + +endchoice + endmenu endif diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index a83279523958..98f01910c2cf 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -12,8 +12,13 @@ obj- := # OCPI interconnect support for 1710, 1610 and 5912 obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o +# omap_device support (OMAP2+ only at the moment) +obj-$(CONFIG_ARCH_OMAP2) += omap_device.o +obj-$(CONFIG_ARCH_OMAP3) += omap_device.o + obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o +obj-$(CONFIG_OMAP_IOMMU_DEBUG) += iommu-debug.o obj-$(CONFIG_CPU_FREQ) += cpu-omap.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o @@ -25,3 +30,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) # OMAP mailbox framework obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o +obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
\ No newline at end of file diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index e8c327a45a55..bf880e966d3b 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -488,7 +488,7 @@ static int __init clk_debugfs_init(void) } return 0; err_out: - debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */ + debugfs_remove_recursive(clk_debugfs_root); return err; } late_initcall(clk_debugfs_init); diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index ebcf006406f9..3a4768d55895 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -54,50 +54,6 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) struct omap_board_config_kernel *kinfo = NULL; int i; -#ifdef CONFIG_OMAP_BOOT_TAG - struct omap_board_config_entry *info = NULL; - - if (omap_bootloader_tag_len > 4) - info = (struct omap_board_config_entry *) omap_bootloader_tag; - while (info != NULL) { - u8 *next; - - if (info->tag == tag) { - if (skip == 0) - break; - skip--; - } - - if ((info->len & 0x03) != 0) { - /* We bail out to avoid an alignment fault */ - printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n", - info->len, info->tag); - return NULL; - } - next = (u8 *) info + sizeof(*info) + info->len; - if (next >= omap_bootloader_tag + omap_bootloader_tag_len) - info = NULL; - else - info = (struct omap_board_config_entry *) next; - } - if (info != NULL) { - /* Check the length as a lame attempt to check for - * binary inconsistency. */ - if (len != NO_LENGTH_CHECK) { - /* Word-align len */ - if (len & 0x03) - len = (len + 3) & ~0x03; - if (info->len != len) { - printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n", - tag, len, info->len); - return NULL; - } - } - if (len_out != NULL) - *len_out = info->len; - return info->data; - } -#endif /* Try to find the config from the board-specific structures * in the kernel. */ for (i = 0; i < omap_board_config_size; i++) { @@ -127,50 +83,6 @@ const void *omap_get_var_config(u16 tag, size_t *len) } EXPORT_SYMBOL(omap_get_var_config); -static int __init omap_add_serial_console(void) -{ - const struct omap_serial_console_config *con_info; - const struct omap_uart_config *uart_info; - static char speed[11], *opt = NULL; - int line, i, uart_idx; - - uart_info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config); - con_info = omap_get_config(OMAP_TAG_SERIAL_CONSOLE, - struct omap_serial_console_config); - if (uart_info == NULL || con_info == NULL) - return 0; - - if (con_info->console_uart == 0) - return 0; - - if (con_info->console_speed) { - snprintf(speed, sizeof(speed), "%u", con_info->console_speed); - opt = speed; - } - - uart_idx = con_info->console_uart - 1; - if (uart_idx >= OMAP_MAX_NR_PORTS) { - printk(KERN_INFO "Console: external UART#%d. " - "Not adding it as console this time.\n", - uart_idx + 1); - return 0; - } - if (!(uart_info->enabled_uarts & (1 << uart_idx))) { - printk(KERN_ERR "Console: Selected UART#%d is " - "not enabled for this platform\n", - uart_idx + 1); - return -1; - } - line = 0; - for (i = 0; i < uart_idx; i++) { - if (uart_info->enabled_uarts & (1 << i)) - line++; - } - return add_preferred_console("ttyS", line, opt); -} -console_initcall(omap_add_serial_console); - - /* * 32KHz clocksource ... always available, on pretty most chips except * OMAP 730 and 1510. Other timers could be used as clocksources, with @@ -253,11 +165,8 @@ static struct clocksource clocksource_32k = { */ unsigned long long sched_clock(void) { - unsigned long long ret; - - ret = (unsigned long long)clocksource_32k.read(&clocksource_32k); - ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift; - return ret; + return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k), + clocksource_32k.mult, clocksource_32k.shift); } static int __init omap_init_clocksource_32k(void) diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 9b00f4cbc903..fd3154ae69b1 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -2347,16 +2347,16 @@ static int __init omap_init_dma(void) int ch, r; if (cpu_class_is_omap1()) { - omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE); + omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE); dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; } else if (cpu_is_omap24xx()) { - omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE); + omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE); dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; } else if (cpu_is_omap34xx()) { - omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE); + omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE); dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; } else if (cpu_is_omap44xx()) { - omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE); + omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE); dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; } else { pr_err("DMA init failed for unsupported omap\n"); diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 7f50b6103dee..d325b54daeb5 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -774,7 +774,10 @@ int __init omap_dm_timer_init(void) for (i = 0; i < dm_timer_count; i++) { timer = &dm_timers[i]; - timer->io_base = IO_ADDRESS(timer->phys_base); + if (cpu_class_is_omap1()) + timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base); + else + timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base); #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ defined(CONFIG_ARCH_OMAP4) if (cpu_class_is_omap2()) { diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 176c86e5531d..693839c89ad0 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -31,7 +31,7 @@ /* * OMAP1510 GPIO registers */ -#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000) +#define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000) #define OMAP1510_GPIO_DATA_INPUT 0x00 #define OMAP1510_GPIO_DATA_OUTPUT 0x04 #define OMAP1510_GPIO_DIR_CONTROL 0x08 @@ -45,10 +45,10 @@ /* * OMAP1610 specific GPIO registers */ -#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400) -#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00) -#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400) -#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00) +#define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400) +#define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00) +#define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400) +#define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00) #define OMAP1610_GPIO_REVISION 0x0000 #define OMAP1610_GPIO_SYSCONFIG 0x0010 #define OMAP1610_GPIO_SYSSTATUS 0x0014 @@ -70,12 +70,12 @@ /* * OMAP730 specific GPIO registers */ -#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000) -#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800) -#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000) -#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800) -#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000) -#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800) +#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) +#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) +#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) +#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) +#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) +#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) #define OMAP730_GPIO_DATA_INPUT 0x00 #define OMAP730_GPIO_DATA_OUTPUT 0x04 #define OMAP730_GPIO_DIR_CONTROL 0x08 @@ -86,12 +86,12 @@ /* * OMAP850 specific GPIO registers */ -#define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000) -#define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800) -#define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000) -#define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800) -#define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000) -#define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800) +#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) +#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) +#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) +#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) +#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) +#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) #define OMAP850_GPIO_DATA_INPUT 0x00 #define OMAP850_GPIO_DATA_OUTPUT 0x04 #define OMAP850_GPIO_DIR_CONTROL 0x08 @@ -99,19 +99,21 @@ #define OMAP850_GPIO_INT_MASK 0x10 #define OMAP850_GPIO_INT_STATUS 0x14 +#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE) + /* * omap24xx specific GPIO registers */ -#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) -#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000) -#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000) -#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000) +#define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000) +#define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000) +#define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000) +#define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000) -#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000) -#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000) -#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000) -#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000) -#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000) +#define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000) +#define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000) +#define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000) +#define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000) +#define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000) #define OMAP24XX_GPIO_REVISION 0x0000 #define OMAP24XX_GPIO_SYSCONFIG 0x0010 @@ -168,24 +170,22 @@ * omap34xx specific GPIO registers */ -#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000) -#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000) -#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000) -#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000) -#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000) -#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000) +#define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000) +#define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000) +#define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000) +#define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000) +#define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000) +#define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000) /* * OMAP44XX specific GPIO registers */ -#define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000) -#define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000) -#define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000) -#define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000) -#define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000) -#define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000) - -#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE) +#define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000) +#define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000) +#define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000) +#define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000) +#define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000) +#define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000) struct gpio_bank { void __iomem *base; @@ -221,7 +221,7 @@ struct gpio_bank { #ifdef CONFIG_ARCH_OMAP16XX static struct gpio_bank gpio_bank_1610[5] = { - { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, + { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, @@ -231,14 +231,14 @@ static struct gpio_bank gpio_bank_1610[5] = { #ifdef CONFIG_ARCH_OMAP15XX static struct gpio_bank gpio_bank_1510[2] = { - { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, + { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } }; #endif #ifdef CONFIG_ARCH_OMAP730 static struct gpio_bank gpio_bank_730[7] = { - { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, + { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, @@ -250,7 +250,7 @@ static struct gpio_bank gpio_bank_730[7] = { #ifdef CONFIG_ARCH_OMAP850 static struct gpio_bank gpio_bank_850[7] = { - { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, + { OMAP1_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, @@ -2032,7 +2032,7 @@ void omap2_gpio_resume_after_retention(void) return; for (i = 0; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l; + u32 l, gen, gen0, gen1; if (!(bank->enabled_non_wakeup_gpios)) continue; @@ -2056,13 +2056,32 @@ void omap2_gpio_resume_after_retention(void) * this silicon bug. */ l ^= bank->saved_datain; l &= bank->non_wakeup_gpios; - if (l) { + + /* + * No need to generate IRQs for the rising edge for gpio IRQs + * configured with falling edge only; and vice versa. + */ + gen0 = l & bank->saved_fallingdetect; + gen0 &= bank->saved_datain; + + gen1 = l & bank->saved_risingdetect; + gen1 &= ~(bank->saved_datain); + + /* FIXME: Consider GPIO IRQs with level detections properly! */ + gen = l & (~(bank->saved_fallingdetect) & + ~(bank->saved_risingdetect)); + /* Consider all GPIO IRQs needed to be updated */ + gen |= gen0 | gen1; + + if (gen) { u32 old0, old1; #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); - __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); - __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); + __raw_writel(old0 | gen, bank->base + + OMAP24XX_GPIO_LEVELDETECT0); + __raw_writel(old1 | gen, bank->base + + OMAP24XX_GPIO_LEVELDETECT1); __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); #endif diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h index 50ea79a0efa2..8e913c322810 100644 --- a/arch/arm/plat-omap/include/mach/board.h +++ b/arch/arm/plat-omap/include/mach/board.h @@ -16,10 +16,8 @@ /* Different peripheral ids */ #define OMAP_TAG_CLOCK 0x4f01 -#define OMAP_TAG_SERIAL_CONSOLE 0x4f03 #define OMAP_TAG_LCD 0x4f05 #define OMAP_TAG_GPIO_SWITCH 0x4f06 -#define OMAP_TAG_UART 0x4f07 #define OMAP_TAG_FBMEM 0x4f08 #define OMAP_TAG_STI_CONSOLE 0x4f09 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h index b9d0dd2da89b..99ebd886f134 100644 --- a/arch/arm/plat-omap/include/mach/clockdomain.h +++ b/arch/arm/plat-omap/include/mach/clockdomain.h @@ -95,7 +95,8 @@ int clkdm_register(struct clockdomain *clkdm); int clkdm_unregister(struct clockdomain *clkdm); struct clockdomain *clkdm_lookup(const char *name); -int clkdm_for_each(int (*fn)(struct clockdomain *clkdm)); +int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), + void *user); struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); void omap2_clkdm_allow_idle(struct clockdomain *clkdm); diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h index 8140dbccb7bc..826d317cdbec 100644 --- a/arch/arm/plat-omap/include/mach/control.h +++ b/arch/arm/plat-omap/include/mach/control.h @@ -20,15 +20,15 @@ #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ - IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) + OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) #define OMAP243X_CTRL_REGADDR(reg) \ - IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) + OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) #define OMAP343X_CTRL_REGADDR(reg) \ - IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) + OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) #else -#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) -#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) -#define OMAP343X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) +#define OMAP242X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) +#define OMAP243X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) +#define OMAP343X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) #endif /* __ASSEMBLY__ */ /* diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S index 56426ed45ef4..a5592991634d 100644 --- a/arch/arm/plat-omap/include/mach/entry-macro.S +++ b/arch/arm/plat-omap/include/mach/entry-macro.S @@ -41,7 +41,7 @@ .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =IO_ADDRESS(OMAP_IH1_BASE) + ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE) ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET] mov \irqstat, #0xffffffff @@ -53,7 +53,7 @@ cmp \irqnr, #0 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] cmpeq \irqnr, #INT_IH2_IRQ - ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE) + ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE) ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] addeqs \irqnr, \irqnr, #32 1510: @@ -68,9 +68,9 @@ /* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ #if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) -#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) +#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE) #elif defined(CONFIG_ARCH_OMAP34XX) -#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) +#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE) #endif #if defined(CONFIG_ARCH_OMAP4) #include <mach/omap44xx.h> diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h index 2b22a8799bc6..633ff688b928 100644 --- a/arch/arm/plat-omap/include/mach/gpio.h +++ b/arch/arm/plat-omap/include/mach/gpio.h @@ -29,7 +29,7 @@ #include <linux/io.h> #include <mach/irqs.h> -#define OMAP_MPUIO_BASE 0xfffb5000 +#define OMAP1_MPUIO_BASE 0xfffb5000 #if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)) diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h index 21fb0efdda86..8d32df32b0b1 100644 --- a/arch/arm/plat-omap/include/mach/io.h +++ b/arch/arm/plat-omap/include/mach/io.h @@ -54,17 +54,33 @@ * ---------------------------------------------------------------------------- */ -#if defined(CONFIG_ARCH_OMAP1) +#ifdef __ASSEMBLER__ +#define IOMEM(x) (x) +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + +#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ +#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) + +#define OMAP2_IO_OFFSET 0x90000000 +#define OMAP2_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */ + +/* + * ---------------------------------------------------------------------------- + * Omap1 specific IO mapping + * ---------------------------------------------------------------------------- + */ -#define IO_PHYS 0xFFFB0000 -#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ -#define IO_SIZE 0x40000 -#define IO_VIRT (IO_PHYS - IO_OFFSET) -#define __IO_ADDRESS(pa) ((pa) - IO_OFFSET) -#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET) -#define io_v2p(va) ((va) + IO_OFFSET) +#define OMAP1_IO_PHYS 0xFFFB0000 +#define OMAP1_IO_SIZE 0x40000 +#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET) -#elif defined(CONFIG_ARCH_OMAP2) +/* + * ---------------------------------------------------------------------------- + * Omap2 specific IO mapping + * ---------------------------------------------------------------------------- + */ /* We map both L3 and L4 on OMAP2 */ #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */ @@ -87,11 +103,6 @@ #define OMAP243X_SMS_VIRT 0xFC000000 #define OMAP243X_SMS_SIZE SZ_1M -#define IO_OFFSET 0x90000000 -#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ -#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ -#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ - /* DSP */ #define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ #define DSP_MEM_24XX_VIRT 0xe0000000 @@ -103,7 +114,11 @@ #define DSP_MMU_24XX_VIRT 0xe2000000 #define DSP_MMU_24XX_SIZE SZ_4K -#elif defined(CONFIG_ARCH_OMAP3) +/* + * ---------------------------------------------------------------------------- + * Omap3 specific IO mapping + * ---------------------------------------------------------------------------- + */ /* We map both L3 and L4 on OMAP3 */ #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */ @@ -143,12 +158,6 @@ #define OMAP343X_SDRC_VIRT 0xFD000000 #define OMAP343X_SDRC_SIZE SZ_1M - -#define IO_OFFSET 0x90000000 -#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ -#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ -#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ - /* DSP */ #define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */ #define DSP_MEM_34XX_VIRT 0xe0000000 @@ -160,8 +169,12 @@ #define DSP_MMU_34XX_VIRT 0xe2000000 #define DSP_MMU_34XX_SIZE SZ_4K +/* + * ---------------------------------------------------------------------------- + * Omap4 specific IO mapping + * ---------------------------------------------------------------------------- + */ -#elif defined(CONFIG_ARCH_OMAP4) /* We map both L3 and L4 on OMAP4 */ #define L3_44XX_PHYS L3_44XX_BASE #define L3_44XX_VIRT 0xd4000000 @@ -189,38 +202,24 @@ #define OMAP44XX_GPMC_SIZE SZ_1M -#define IO_OFFSET 0x90000000 -#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ -#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ -#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ - -#endif - -#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) -#define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa)) -#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa)) +/* + * ---------------------------------------------------------------------------- + * Omap specific register access + * ---------------------------------------------------------------------------- + */ -#ifdef __ASSEMBLER__ -#define IOMEM(x) (x) -#else -#define IOMEM(x) ((void __force __iomem *)(x)) +#ifndef __ASSEMBLER__ /* - * Functions to access the OMAP IO region - * - * NOTE: - Use omap_read/write[bwl] for physical register addresses - * - Use __raw_read/write[bwl]() for virtual register addresses - * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses - * - DO NOT use hardcoded virtual addresses to allow changing the - * IO address space again if needed + * NOTE: Please use ioremap + __raw_read/write where possible instead of these */ -#define omap_readb(a) __raw_readb(IO_ADDRESS(a)) -#define omap_readw(a) __raw_readw(IO_ADDRESS(a)) -#define omap_readl(a) __raw_readl(IO_ADDRESS(a)) -#define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a)) -#define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a)) -#define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a)) +extern u8 omap_readb(u32 pa); +extern u16 omap_readw(u32 pa); +extern u32 omap_readl(u32 pa); +extern void omap_writeb(u8 v, u32 pa); +extern void omap_writew(u16 v, u32 pa); +extern void omap_writel(u32 v, u32 pa); struct omap_sdrc_params; diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h index 769b00b4c34a..46d41ac83dbf 100644 --- a/arch/arm/plat-omap/include/mach/iommu.h +++ b/arch/arm/plat-omap/include/mach/iommu.h @@ -95,7 +95,7 @@ struct iommu_functions { void (*save_ctx)(struct iommu *obj); void (*restore_ctx)(struct iommu *obj); - ssize_t (*dump_ctx)(struct iommu *obj, char *buf); + ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len); }; struct iommu_platform_data { @@ -162,7 +162,7 @@ extern void uninstall_iommu_arch(const struct iommu_functions *ops); extern int foreach_iommu_device(void *data, int (*fn)(struct device *, void *)); -extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf); -extern size_t dump_tlb_entries(struct iommu *obj, char *buf); +extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len); +extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len); #endif /* __MACH_IOMMU_H */ diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h index 39b591ff54bb..f82a8dcaad94 100644 --- a/arch/arm/plat-omap/include/mach/mtd-xip.h +++ b/arch/arm/plat-omap/include/mach/mtd-xip.h @@ -25,7 +25,7 @@ typedef struct { } xip_omap_mpu_timer_regs_t; #define xip_omap_mpu_timer_base(n) \ -((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ +((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ (n)*OMAP_MPU_TIMER_OFFSET)) static inline unsigned long xip_omap_mpu_timer_read(int nr) diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h index 80281c458baf..98dfab651dfc 100644 --- a/arch/arm/plat-omap/include/mach/mux.h +++ b/arch/arm/plat-omap/include/mach/mux.h @@ -857,6 +857,37 @@ enum omap34xx_index { /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */ H16_34XX_SDRC_CKE0, H17_34XX_SDRC_CKE1, + + /* MMC1 */ + N28_3430_MMC1_CLK, + M27_3430_MMC1_CMD, + N27_3430_MMC1_DAT0, + N26_3430_MMC1_DAT1, + N25_3430_MMC1_DAT2, + P28_3430_MMC1_DAT3, + P27_3430_MMC1_DAT4, + P26_3430_MMC1_DAT5, + R27_3430_MMC1_DAT6, + R25_3430_MMC1_DAT7, + + /* MMC2 */ + AE2_3430_MMC2_CLK, + AG5_3430_MMC2_CMD, + AH5_3430_MMC2_DAT0, + AH4_3430_MMC2_DAT1, + AG4_3430_MMC2_DAT2, + AF4_3430_MMC2_DAT3, + + /* MMC3 */ + AF10_3430_MMC3_CLK, + AC3_3430_MMC3_CMD, + AE11_3430_MMC3_DAT0, + AH9_3430_MMC3_DAT1, + AF13_3430_MMC3_DAT2, + AF13_3430_MMC3_DAT3, + + /* SYS_NIRQ T2 INT1 */ + AF26_34XX_SYS_NIRQ, }; struct omap_mux_cfg { diff --git a/arch/arm/plat-omap/include/mach/omap-pm.h b/arch/arm/plat-omap/include/mach/omap-pm.h new file mode 100644 index 000000000000..3ee41d711492 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/omap-pm.h @@ -0,0 +1,301 @@ +/* + * omap-pm.h - OMAP power management interface + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * Copyright (C) 2008-2009 Nokia Corporation + * Paul Walmsley + * + * Interface developed by (in alphabetical order): Karthik Dasu, Jouni + * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa, + * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, + * Richard Woodruff + */ + +#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H +#define ASM_ARM_ARCH_OMAP_OMAP_PM_H + +#include <linux/device.h> +#include <linux/cpufreq.h> + +#include "powerdomain.h" + +/** + * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU + * @rate: target clock rate + * @opp_id: OPP ID + * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP + * + * Operating performance point data. Can vary by OMAP chip and board. + */ +struct omap_opp { + unsigned long rate; + u8 opp_id; + u16 min_vdd; +}; + +extern struct omap_opp *mpu_opps; +extern struct omap_opp *dsp_opps; +extern struct omap_opp *l3_opps; + +/* + * agent_id values for use with omap_pm_set_min_bus_tput(): + * + * OCP_INITIATOR_AGENT is only valid for devices that can act as + * initiators -- it represents the device's L3 interconnect + * connection. OCP_TARGET_AGENT represents the device's L4 + * interconnect connection. + */ +#define OCP_TARGET_AGENT 1 +#define OCP_INITIATOR_AGENT 2 + +/** + * omap_pm_if_early_init - OMAP PM init code called before clock fw init + * @mpu_opp_table: array ptr to struct omap_opp for MPU + * @dsp_opp_table: array ptr to struct omap_opp for DSP + * @l3_opp_table : array ptr to struct omap_opp for CORE + * + * Initialize anything that must be configured before the clock + * framework starts. The "_if_" is to avoid name collisions with the + * PM idle-loop code. + */ +int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table, + struct omap_opp *dsp_opp_table, + struct omap_opp *l3_opp_table); + +/** + * omap_pm_if_init - OMAP PM init code called after clock fw init + * + * The main initialization code. OPP tables are passed in here. The + * "_if_" is to avoid name collisions with the PM idle-loop code. + */ +int __init omap_pm_if_init(void); + +/** + * omap_pm_if_exit - OMAP PM exit code + * + * Exit code; currently unused. The "_if_" is to avoid name + * collisions with the PM idle-loop code. + */ +void omap_pm_if_exit(void); + +/* + * Device-driver-originated constraints (via board-*.c files, platform_data) + */ + + +/** + * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency + * @dev: struct device * requesting the constraint + * @t: maximum MPU wakeup latency in microseconds + * + * Request that the maximum interrupt latency for the MPU to be no + * greater than 't' microseconds. "Interrupt latency" in this case is + * defined as the elapsed time from the occurrence of a hardware or + * timer interrupt to the time when the device driver's interrupt + * service routine has been entered by the MPU. + * + * It is intended that underlying PM code will use this information to + * determine what power state to put the MPU powerdomain into, and + * possibly the CORE powerdomain as well, since interrupt handling + * code currently runs from SDRAM. Advanced PM or board*.c code may + * also configure interrupt controller priorities, OCP bus priorities, + * CPU speed(s), etc. + * + * This function will not affect device wakeup latency, e.g., time + * elapsed from when a device driver enables a hardware device with + * clk_enable(), to when the device is ready for register access or + * other use. To control this device wakeup latency, use + * set_max_dev_wakeup_lat() + * + * Multiple calls to set_max_mpu_wakeup_lat() will replace the + * previous t value. To remove the latency target for the MPU, call + * with t = -1. + * + * No return value. + */ +void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); + + +/** + * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device + * @dev: struct device * requesting the constraint + * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT) + * @r: minimum throughput (in KiB/s) + * + * Request that the minimum data throughput on the OCP interconnect + * attached to device 'dev' interconnect agent 'tbus_id' be no less + * than 'r' KiB/s. + * + * It is expected that the OMAP PM or bus code will use this + * information to set the interconnect clock to run at the lowest + * possible speed that satisfies all current system users. The PM or + * bus code will adjust the estimate based on its model of the bus, so + * device driver authors should attempt to specify an accurate + * quantity for their device use case, and let the PM or bus code + * overestimate the numbers as necessary to handle request/response + * latency, other competing users on the system, etc. On OMAP2/3, if + * a driver requests a minimum L4 interconnect speed constraint, the + * code will also need to add an minimum L3 interconnect speed + * constraint, + * + * Multiple calls to set_min_bus_tput() will replace the previous rate + * value for this device. To remove the interconnect throughput + * restriction for this device, call with r = 0. + * + * No return value. + */ +void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); + + +/** + * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency + * @dev: struct device * + * @t: maximum device wakeup latency in microseconds + * + * Request that the maximum amount of time necessary for a device to + * become accessible after its clocks are enabled should be no greater + * than 't' microseconds. Specifically, this represents the time from + * when a device driver enables device clocks with clk_enable(), to + * when the register reads and writes on the device will succeed. + * This function should be called before clk_disable() is called, + * since the power state transition decision may be made during + * clk_disable(). + * + * It is intended that underlying PM code will use this information to + * determine what power state to put the powerdomain enclosing this + * device into. + * + * Multiple calls to set_max_dev_wakeup_lat() will replace the + * previous wakeup latency values for this device. To remove the wakeup + * latency restriction for this device, call with t = -1. + * + * No return value. + */ +void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); + + +/** + * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency + * @dev: struct device * + * @t: maximum DMA transfer start latency in microseconds + * + * Request that the maximum system DMA transfer start latency for this + * device 'dev' should be no greater than 't' microseconds. "DMA + * transfer start latency" here is defined as the elapsed time from + * when a device (e.g., McBSP) requests that a system DMA transfer + * start or continue, to the time at which data starts to flow into + * that device from the system DMA controller. + * + * It is intended that underlying PM code will use this information to + * determine what power state to put the CORE powerdomain into. + * + * Since system DMA transfers may not involve the MPU, this function + * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do + * so. Similarly, this function will not affect device wakeup latency + * -- use set_max_dev_wakeup_lat() to affect that. + * + * Multiple calls to set_max_sdma_lat() will replace the previous t + * value for this device. To remove the maximum DMA latency for this + * device, call with t = -1. + * + * No return value. + */ +void omap_pm_set_max_sdma_lat(struct device *dev, long t); + + +/* + * DSP Bridge-specific constraints + */ + +/** + * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table + * + * Intended for use by DSPBridge. Returns an array of OPP->DSP clock + * frequency entries. The final item in the array should have .rate = + * .opp_id = 0. + */ +const struct omap_opp *omap_pm_dsp_get_opp_table(void); + +/** + * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge + * @opp_id: target DSP OPP ID + * + * Set a minimum OPP ID for the DSP. This is intended to be called + * only from the DSP Bridge MPU-side driver. Unfortunately, the only + * information that code receives from the DSP/BIOS load estimator is the + * target OPP ID; hence, this interface. No return value. + */ +void omap_pm_dsp_set_min_opp(u8 opp_id); + +/** + * omap_pm_dsp_get_opp - report the current DSP OPP ID + * + * Report the current OPP for the DSP. Since on OMAP3, the DSP and + * MPU share a single voltage domain, the OPP ID returned back may + * represent a higher DSP speed than the OPP requested via + * omap_pm_dsp_set_min_opp(). + * + * Returns the current VDD1 OPP ID, or 0 upon error. + */ +u8 omap_pm_dsp_get_opp(void); + + +/* + * CPUFreq-originated constraint + * + * In the future, this should be handled by custom OPP clocktype + * functions. + */ + +/** + * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr + * + * Provide a frequency table usable by CPUFreq for the current chip/board. + * Returns a pointer to a struct cpufreq_frequency_table array or NULL + * upon error. + */ +struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void); + +/** + * omap_pm_cpu_set_freq - set the current minimum MPU frequency + * @f: MPU frequency in Hz + * + * Set the current minimum CPU frequency. The actual CPU frequency + * used could end up higher if the DSP requested a higher OPP. + * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No + * return value. + */ +void omap_pm_cpu_set_freq(unsigned long f); + +/** + * omap_pm_cpu_get_freq - report the current CPU frequency + * + * Returns the current MPU frequency, or 0 upon error. + */ +unsigned long omap_pm_cpu_get_freq(void); + + +/* + * Device context loss tracking + */ + +/** + * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx + * @dev: struct device * + * + * This function returns the number of times that the device @dev has + * lost its internal context. This generally occurs on a powerdomain + * transition to OFF. Drivers use this as an optimization to avoid restoring + * context if the device hasn't lost it. To use, drivers should initially + * call this in their context save functions and store the result. Early in + * the driver's context restore function, the driver should call this function + * again, and compare the result to the stored counter. If they differ, the + * driver must restore device context. If the number of context losses + * exceeds the maximum positive integer, the function will wrap to 0 and + * continue counting. Returns the number of context losses for this device, + * or -EINVAL upon error. + */ +int omap_pm_get_dev_context_loss_count(struct device *dev); + + +#endif diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h index 15dec7f1c7c0..b3ba5ac7b4a4 100644 --- a/arch/arm/plat-omap/include/mach/omap44xx.h +++ b/arch/arm/plat-omap/include/mach/omap44xx.h @@ -33,14 +33,14 @@ #define IRQ_SIR_IRQ 0x0040 #define OMAP44XX_GIC_DIST_BASE 0x48241000 #define OMAP44XX_GIC_CPU_BASE 0x48240100 -#define OMAP44XX_VA_GIC_CPU_BASE IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) +#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) #define OMAP44XX_SCU_BASE 0x48240000 -#define OMAP44XX_VA_SCU_BASE IO_ADDRESS(OMAP44XX_SCU_BASE) +#define OMAP44XX_VA_SCU_BASE OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE) #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 -#define OMAP44XX_VA_LOCAL_TWD_BASE IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE) +#define OMAP44XX_VA_LOCAL_TWD_BASE OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE) #define OMAP44XX_LOCAL_TWD_SIZE 0x00000100 #define OMAP44XX_WKUPGEN_BASE 0x48281000 -#define OMAP44XX_VA_WKUPGEN_BASE IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) +#define OMAP44XX_VA_WKUPGEN_BASE OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) #endif /* __ASM_ARCH_OMAP44XX_H */ diff --git a/arch/arm/plat-omap/include/mach/omap_device.h b/arch/arm/plat-omap/include/mach/omap_device.h new file mode 100644 index 000000000000..bd0e136db337 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/omap_device.h @@ -0,0 +1,141 @@ +/* + * omap_device headers + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * Developed in collaboration with (alphabetical order): Benoit + * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram + * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard + * Woodruff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Eventually this type of functionality should either be + * a) implemented via arch-specific pointers in platform_device + * or + * b) implemented as a proper omap_bus/omap_device in Linux, no more + * platform_device + * + * omap_device differs from omap_hwmod in that it includes external + * (e.g., board- and system-level) integration details. omap_hwmod + * stores hardware data that is invariant for a given OMAP chip. + * + * To do: + * - GPIO integration + * - regulator integration + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/omap_hwmod.h> + +/* omap_device._state values */ +#define OMAP_DEVICE_STATE_UNKNOWN 0 +#define OMAP_DEVICE_STATE_ENABLED 1 +#define OMAP_DEVICE_STATE_IDLE 2 +#define OMAP_DEVICE_STATE_SHUTDOWN 3 + +/** + * struct omap_device - omap_device wrapper for platform_devices + * @pdev: platform_device + * @hwmods: (one .. many per omap_device) + * @hwmods_cnt: ARRAY_SIZE() of @hwmods + * @pm_lats: ptr to an omap_device_pm_latency table + * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats + * @pm_lat_level: array index of the last odpl entry executed - -1 if never + * @dev_wakeup_lat: dev wakeup latency in microseconds + * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM + * @_state: one of OMAP_DEVICE_STATE_* (see above) + * @flags: device flags + * + * Integrates omap_hwmod data into Linux platform_device. + * + * Field names beginning with underscores are for the internal use of + * the omap_device code. + * + */ +struct omap_device { + struct platform_device pdev; + struct omap_hwmod **hwmods; + struct omap_device_pm_latency *pm_lats; + u32 dev_wakeup_lat; + u32 _dev_wakeup_lat_limit; + u8 pm_lats_cnt; + s8 pm_lat_level; + u8 hwmods_cnt; + u8 _state; +}; + +/* Device driver interface (call via platform_data fn ptrs) */ + +int omap_device_enable(struct platform_device *pdev); +int omap_device_idle(struct platform_device *pdev); +int omap_device_shutdown(struct platform_device *pdev); + +/* Core code interface */ + +int omap_device_count_resources(struct omap_device *od); +int omap_device_fill_resources(struct omap_device *od, struct resource *res); + +struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, + struct omap_hwmod *oh, void *pdata, + int pdata_len, + struct omap_device_pm_latency *pm_lats, + int pm_lats_cnt); + +struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, + struct omap_hwmod **oh, int oh_cnt, + void *pdata, int pdata_len, + struct omap_device_pm_latency *pm_lats, + int pm_lats_cnt); + +int omap_device_register(struct omap_device *od); + +/* OMAP PM interface */ +int omap_device_align_pm_lat(struct platform_device *pdev, + u32 new_wakeup_lat_limit); +struct powerdomain *omap_device_get_pwrdm(struct omap_device *od); + +/* Other */ + +int omap_device_idle_hwmods(struct omap_device *od); +int omap_device_enable_hwmods(struct omap_device *od); + +int omap_device_disable_clocks(struct omap_device *od); +int omap_device_enable_clocks(struct omap_device *od); + + +/* + * Entries should be kept in latency order ascending + * + * deact_lat is the maximum number of microseconds required to complete + * deactivate_func() at the device's slowest OPP. + * + * act_lat is the maximum number of microseconds required to complete + * activate_func() at the device's slowest OPP. + * + * This will result in some suboptimal power management decisions at fast + * OPPs, but avoids having to recompute all device power management decisions + * if the system shifts from a fast OPP to a slow OPP (in order to meet + * latency requirements). + * + * XXX should deactivate_func/activate_func() take platform_device pointers + * rather than omap_device pointers? + */ +struct omap_device_pm_latency { + u32 deactivate_lat; + int (*deactivate_func)(struct omap_device *od); + u32 activate_lat; + int (*activate_func)(struct omap_device *od); +}; + + +#endif + diff --git a/arch/arm/plat-omap/include/mach/omap_hwmod.h b/arch/arm/plat-omap/include/mach/omap_hwmod.h new file mode 100644 index 000000000000..1f79c20e2929 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/omap_hwmod.h @@ -0,0 +1,447 @@ +/* + * omap_hwmod macros, structures + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * Created in collaboration with (alphabetical order): Benoit Cousson, + * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari + * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * These headers and macros are used to define OMAP on-chip module + * data and their integration with other OMAP modules and Linux. + * + * References: + * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) + * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) + * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) + * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) + * - Open Core Protocol Specification 2.2 + * + * To do: + * - add interconnect error log structures + * - add pinmuxing + * - init_conn_id_bit (CONNID_BIT_VECTOR) + * - implement default hwmod SMS/SDRC flags? + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H + +#include <linux/kernel.h> +#include <linux/ioport.h> + +#include <mach/cpu.h> + +struct omap_device; + +/* OCP SYSCONFIG bit shifts/masks */ +#define SYSC_MIDLEMODE_SHIFT 12 +#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) +#define SYSC_CLOCKACTIVITY_SHIFT 8 +#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) +#define SYSC_SIDLEMODE_SHIFT 3 +#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) +#define SYSC_ENAWAKEUP_SHIFT 2 +#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) +#define SYSC_SOFTRESET_SHIFT 1 +#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) + +/* OCP SYSSTATUS bit shifts/masks */ +#define SYSS_RESETDONE_SHIFT 0 +#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) + +/* Master standby/slave idle mode flags */ +#define HWMOD_IDLEMODE_FORCE (1 << 0) +#define HWMOD_IDLEMODE_NO (1 << 1) +#define HWMOD_IDLEMODE_SMART (1 << 2) + + +/** + * struct omap_hwmod_dma_info - MPU address space handled by the hwmod + * @name: name of the DMA channel (module local name) + * @dma_ch: DMA channel ID + * + * @name should be something short, e.g., "tx" or "rx". It is for use + * by platform_get_resource_byname(). It is defined locally to the + * hwmod. + */ +struct omap_hwmod_dma_info { + const char *name; + u16 dma_ch; +}; + +/** + * struct omap_hwmod_opt_clk - optional clocks used by this hwmod + * @role: "sys", "32k", "tv", etc -- for use in clk_get() + * @clkdev_dev_id: opt clock: clkdev dev_id string + * @clkdev_con_id: opt clock: clkdev con_id string + * @_clk: pointer to the struct clk (filled in at runtime) + * + * The module's interface clock and main functional clock should not + * be added as optional clocks. + */ +struct omap_hwmod_opt_clk { + const char *role; + const char *clkdev_dev_id; + const char *clkdev_con_id; + struct clk *_clk; +}; + + +/* omap_hwmod_omap2_firewall.flags bits */ +#define OMAP_FIREWALL_L3 (1 << 0) +#define OMAP_FIREWALL_L4 (1 << 1) + +/** + * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data + * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_* + * @l4_fw_region: L4 firewall region ID + * @l4_prot_group: L4 protection group ID + * @flags: (see omap_hwmod_omap2_firewall.flags macros above) + */ +struct omap_hwmod_omap2_firewall { + u8 l3_perm_bit; + u8 l4_fw_region; + u8 l4_prot_group; + u8 flags; +}; + + +/* + * omap_hwmod_addr_space.flags bits + * + * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init. + * ADDR_TYPE_RT: Address space contains module register target data. + */ +#define ADDR_MAP_ON_INIT (1 << 0) +#define ADDR_TYPE_RT (1 << 1) + +/** + * struct omap_hwmod_addr_space - MPU address space handled by the hwmod + * @pa_start: starting physical address + * @pa_end: ending physical address + * @flags: (see omap_hwmod_addr_space.flags macros above) + * + * Address space doesn't necessarily follow physical interconnect + * structure. GPMC is one example. + */ +struct omap_hwmod_addr_space { + u32 pa_start; + u32 pa_end; + u8 flags; +}; + + +/* + * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this + * interface to interact with the hwmod. Used to add sleep dependencies + * when the module is enabled or disabled. + */ +#define OCP_USER_MPU (1 << 0) +#define OCP_USER_SDMA (1 << 1) + +/* omap_hwmod_ocp_if.flags bits */ +#define OCPIF_HAS_IDLEST (1 << 0) +#define OCPIF_SWSUP_IDLE (1 << 1) +#define OCPIF_CAN_BURST (1 << 2) + +/** + * struct omap_hwmod_ocp_if - OCP interface data + * @master: struct omap_hwmod that initiates OCP transactions on this link + * @slave: struct omap_hwmod that responds to OCP transactions on this link + * @addr: address space associated with this link + * @clkdev_dev_id: interface clock: clkdev dev_id string + * @clkdev_con_id: interface clock: clkdev con_id string + * @_clk: pointer to the interface struct clk (filled in at runtime) + * @fw: interface firewall data + * @addr_cnt: ARRAY_SIZE(@addr) + * @width: OCP data width + * @thread_cnt: number of threads + * @max_burst_len: maximum burst length in @width sized words (0 if unlimited) + * @user: initiators using this interface (see OCP_USER_* macros above) + * @flags: OCP interface flags (see OCPIF_* macros above) + * + * It may also be useful to add a tag_cnt field for OCP2.x devices. + * + * Parameter names beginning with an underscore are managed internally by + * the omap_hwmod code and should not be set during initialization. + */ +struct omap_hwmod_ocp_if { + struct omap_hwmod *master; + struct omap_hwmod *slave; + struct omap_hwmod_addr_space *addr; + const char *clkdev_dev_id; + const char *clkdev_con_id; + struct clk *_clk; + union { + struct omap_hwmod_omap2_firewall omap2; + } fw; + u8 addr_cnt; + u8 width; + u8 thread_cnt; + u8 max_burst_len; + u8 user; + u8 flags; +}; + + +/* Macros for use in struct omap_hwmod_sysconfig */ + +/* Flags for use in omap_hwmod_sysconfig.idlemodes */ +#define MASTER_STANDBY_SHIFT 2 +#define SLAVE_IDLE_SHIFT 0 +#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT) +#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT) +#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT) +#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) +#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) +#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) + +/* omap_hwmod_sysconfig.sysc_flags capability flags */ +#define SYSC_HAS_AUTOIDLE (1 << 0) +#define SYSC_HAS_SOFTRESET (1 << 1) +#define SYSC_HAS_ENAWAKEUP (1 << 2) +#define SYSC_HAS_EMUFREE (1 << 3) +#define SYSC_HAS_CLOCKACTIVITY (1 << 4) +#define SYSC_HAS_SIDLEMODE (1 << 5) +#define SYSC_HAS_MIDLEMODE (1 << 6) +#define SYSS_MISSING (1 << 7) + +/* omap_hwmod_sysconfig.clockact flags */ +#define CLOCKACT_TEST_BOTH 0x0 +#define CLOCKACT_TEST_MAIN 0x1 +#define CLOCKACT_TEST_ICLK 0x2 +#define CLOCKACT_TEST_NONE 0x3 + +/** + * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data + * @rev_offs: IP block revision register offset (from module base addr) + * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) + * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) + * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} + * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported + * @clockact: the default value of the module CLOCKACTIVITY bits + * + * @clockact describes to the module which clocks are likely to be + * disabled when the PRCM issues its idle request to the module. Some + * modules have separate clockdomains for the interface clock and main + * functional clock, and can check whether they should acknowledge the + * idle request based on the internal module functionality that has + * been associated with the clocks marked in @clockact. This field is + * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) + * + */ +struct omap_hwmod_sysconfig { + u16 rev_offs; + u16 sysc_offs; + u16 syss_offs; + u8 idlemodes; + u8 sysc_flags; + u8 clockact; +}; + +/** + * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data + * @module_offs: PRCM submodule offset from the start of the PRM/CM + * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3) + * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs + * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3) + * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit + * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit + * + * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST, + * WKEN, GRPSEL registers. In an ideal world, no extra information + * would be needed for IDLEST information, but alas, there are some + * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit + * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST) + */ +struct omap_hwmod_omap2_prcm { + s16 module_offs; + u8 prcm_reg_id; + u8 module_bit; + u8 idlest_reg_id; + u8 idlest_idle_bit; + u8 idlest_stdby_bit; +}; + + +/** + * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data + * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2 + * @device_offs: device register offset from @module_offs + * @submodule_wkdep_bit: bit shift of the WKDEP range + */ +struct omap_hwmod_omap4_prcm { + u32 module_offs; + u16 device_offs; + u8 submodule_wkdep_bit; +}; + + +/* + * omap_hwmod.flags definitions + * + * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out + * of idle, rather than relying on module smart-idle + * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out + * of standby, rather than relying on module smart-standby + * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for + * SDRAM controller, etc. + * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM + * controller, etc. + * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup + */ +#define HWMOD_SWSUP_SIDLE (1 << 0) +#define HWMOD_SWSUP_MSTANDBY (1 << 1) +#define HWMOD_INIT_NO_RESET (1 << 2) +#define HWMOD_INIT_NO_IDLE (1 << 3) +#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 4) + +/* + * omap_hwmod._int_flags definitions + * These are for internal use only and are managed by the omap_hwmod code. + * + * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module + * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP + * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached + */ +#define _HWMOD_NO_MPU_PORT (1 << 0) +#define _HWMOD_WAKEUP_ENABLED (1 << 1) +#define _HWMOD_SYSCONFIG_LOADED (1 << 2) + +/* + * omap_hwmod._state definitions + * + * INITIALIZED: reset (optionally), initialized, enabled, disabled + * (optionally) + * + * + */ +#define _HWMOD_STATE_UNKNOWN 0 +#define _HWMOD_STATE_REGISTERED 1 +#define _HWMOD_STATE_CLKS_INITED 2 +#define _HWMOD_STATE_INITIALIZED 3 +#define _HWMOD_STATE_ENABLED 4 +#define _HWMOD_STATE_IDLE 5 +#define _HWMOD_STATE_DISABLED 6 + +/** + * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) + * @name: name of the hwmod + * @od: struct omap_device currently associated with this hwmod (internal use) + * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) + * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) + * @prcm: PRCM data pertaining to this hwmod + * @clkdev_dev_id: main clock: clkdev dev_id string + * @clkdev_con_id: main clock: clkdev con_id string + * @_clk: pointer to the main struct clk (filled in at runtime) + * @opt_clks: other device clocks that drivers can request (0..*) + * @masters: ptr to array of OCP ifs that this hwmod can initiate on + * @slaves: ptr to array of OCP ifs that this hwmod can respond on + * @sysconfig: device SYSCONFIG/SYSSTATUS register data + * @dev_attr: arbitrary device attributes that can be passed to the driver + * @_sysc_cache: internal-use hwmod flags + * @_rt_va: cached register target start address (internal use) + * @_mpu_port_index: cached MPU register target slave ID (internal use) + * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) + * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift + * @mpu_irqs_cnt: number of @mpu_irqs + * @sdma_chs_cnt: number of @sdma_chs + * @opt_clks_cnt: number of @opt_clks + * @master_cnt: number of @master entries + * @slaves_cnt: number of @slave entries + * @response_lat: device OCP response latency (in interface clock cycles) + * @_int_flags: internal-use hwmod flags + * @_state: internal-use hwmod state + * @flags: hwmod flags (documented below) + * @omap_chip: OMAP chips this hwmod is present on + * @node: list node for hwmod list (internal use) + * + * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main + * clock," which for our purposes is defined as "the functional clock needed + * for register accesses to complete." Modules may not have a main clock if + * the interface clock also serves as a main clock. + * + * Parameter names beginning with an underscore are managed internally by + * the omap_hwmod code and should not be set during initialization. + */ +struct omap_hwmod { + const char *name; + struct omap_device *od; + u8 *mpu_irqs; + struct omap_hwmod_dma_info *sdma_chs; + union { + struct omap_hwmod_omap2_prcm omap2; + struct omap_hwmod_omap4_prcm omap4; + } prcm; + const char *clkdev_dev_id; + const char *clkdev_con_id; + struct clk *_clk; + struct omap_hwmod_opt_clk *opt_clks; + struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ + struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ + struct omap_hwmod_sysconfig *sysconfig; + void *dev_attr; + u32 _sysc_cache; + void __iomem *_rt_va; + struct list_head node; + u16 flags; + u8 _mpu_port_index; + u8 msuspendmux_reg_id; + u8 msuspendmux_shift; + u8 response_lat; + u8 mpu_irqs_cnt; + u8 sdma_chs_cnt; + u8 opt_clks_cnt; + u8 masters_cnt; + u8 slaves_cnt; + u8 hwmods_cnt; + u8 _int_flags; + u8 _state; + const struct omap_chip_id omap_chip; +}; + +int omap_hwmod_init(struct omap_hwmod **ohs); +int omap_hwmod_register(struct omap_hwmod *oh); +int omap_hwmod_unregister(struct omap_hwmod *oh); +struct omap_hwmod *omap_hwmod_lookup(const char *name); +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)); +int omap_hwmod_late_init(void); + +int omap_hwmod_enable(struct omap_hwmod *oh); +int omap_hwmod_idle(struct omap_hwmod *oh); +int omap_hwmod_shutdown(struct omap_hwmod *oh); + +int omap_hwmod_enable_clocks(struct omap_hwmod *oh); +int omap_hwmod_disable_clocks(struct omap_hwmod *oh); + +int omap_hwmod_reset(struct omap_hwmod *oh); +void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); + +void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs); +u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs); + +int omap_hwmod_count_resources(struct omap_hwmod *oh); +int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); + +struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); + +int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, + struct omap_hwmod *init_oh); +int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, + struct omap_hwmod *init_oh); + +int omap_hwmod_set_clockact_both(struct omap_hwmod *oh); +int omap_hwmod_set_clockact_main(struct omap_hwmod *oh); +int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh); +int omap_hwmod_set_clockact_none(struct omap_hwmod *oh); + +int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); +int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); + +#endif diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h index 69c9e675d8ee..6271d8556a40 100644 --- a/arch/arm/plat-omap/include/mach/powerdomain.h +++ b/arch/arm/plat-omap/include/mach/powerdomain.h @@ -117,6 +117,13 @@ struct powerdomain { struct list_head node; + int state; + unsigned state_counter[4]; + +#ifdef CONFIG_PM_DEBUG + s64 timer; + s64 state_timer[4]; +#endif }; @@ -126,7 +133,8 @@ int pwrdm_register(struct powerdomain *pwrdm); int pwrdm_unregister(struct powerdomain *pwrdm); struct powerdomain *pwrdm_lookup(const char *name); -int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm)); +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), + void *user); int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); @@ -164,4 +172,9 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); int pwrdm_wait_transition(struct powerdomain *pwrdm); +int pwrdm_state_switch(struct powerdomain *pwrdm); +int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); +int pwrdm_pre_transition(void); +int pwrdm_post_transition(void); + #endif diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h index 0be18e4ff182..1c09c78a48f2 100644 --- a/arch/arm/plat-omap/include/mach/sdrc.h +++ b/arch/arm/plat-omap/include/mach/sdrc.h @@ -21,19 +21,28 @@ /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ #define SDRC_SYSCONFIG 0x010 +#define SDRC_CS_CFG 0x040 +#define SDRC_SHARING 0x044 +#define SDRC_ERR_TYPE 0x04C #define SDRC_DLLA_CTRL 0x060 #define SDRC_DLLA_STATUS 0x064 #define SDRC_DLLB_CTRL 0x068 #define SDRC_DLLB_STATUS 0x06C #define SDRC_POWER 0x070 +#define SDRC_MCFG_0 0x080 #define SDRC_MR_0 0x084 +#define SDRC_EMR2_0 0x08c #define SDRC_ACTIM_CTRL_A_0 0x09c #define SDRC_ACTIM_CTRL_B_0 0x0a0 #define SDRC_RFR_CTRL_0 0x0a4 +#define SDRC_MANUAL_0 0x0a8 +#define SDRC_MCFG_1 0x0B0 #define SDRC_MR_1 0x0B4 +#define SDRC_EMR2_1 0x0BC #define SDRC_ACTIM_CTRL_A_1 0x0C4 #define SDRC_ACTIM_CTRL_B_1 0x0C8 #define SDRC_RFR_CTRL_1 0x0D4 +#define SDRC_MANUAL_1 0x0D8 /* * These values represent the number of memory clock cycles between @@ -71,11 +80,11 @@ */ #define OMAP242X_SMS_REGADDR(reg) \ - (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) + (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg) #define OMAP243X_SMS_REGADDR(reg) \ - (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) + (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg) #define OMAP343X_SMS_REGADDR(reg) \ - (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) + (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg) /* SMS register offsets - read/write with sms_{read,write}_reg() */ diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h index def0529c75eb..e249186d26e2 100644 --- a/arch/arm/plat-omap/include/mach/serial.h +++ b/arch/arm/plat-omap/include/mach/serial.h @@ -13,6 +13,8 @@ #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H +#include <linux/init.h> + #if defined(CONFIG_ARCH_OMAP1) /* OMAP1 serial ports */ #define OMAP_UART1_BASE 0xfffb0000 @@ -53,6 +55,7 @@ }) #ifndef __ASSEMBLER__ +extern void __init omap_serial_early_init(void); extern void omap_serial_init(void); extern int omap_uart_can_sleep(void); extern void omap_uart_check_wakeup(void); diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c index 9b42d72d96cf..b6defa23e77e 100644 --- a/arch/arm/plat-omap/io.c +++ b/arch/arm/plat-omap/io.c @@ -30,8 +30,8 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) { #ifdef CONFIG_ARCH_OMAP1 if (cpu_class_is_omap1()) { - if (BETWEEN(p, IO_PHYS, IO_SIZE)) - return XLATE(p, IO_PHYS, IO_VIRT); + if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) + return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT); } if (cpu_is_omap730()) { if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE)) @@ -132,3 +132,61 @@ void omap_iounmap(volatile void __iomem *addr) __iounmap(addr); } EXPORT_SYMBOL(omap_iounmap); + +/* + * NOTE: Please use ioremap + __raw_read/write where possible instead of these + */ + +u8 omap_readb(u32 pa) +{ + if (cpu_class_is_omap1()) + return __raw_readb(OMAP1_IO_ADDRESS(pa)); + else + return __raw_readb(OMAP2_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_readb); + +u16 omap_readw(u32 pa) +{ + if (cpu_class_is_omap1()) + return __raw_readw(OMAP1_IO_ADDRESS(pa)); + else + return __raw_readw(OMAP2_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_readw); + +u32 omap_readl(u32 pa) +{ + if (cpu_class_is_omap1()) + return __raw_readl(OMAP1_IO_ADDRESS(pa)); + else + return __raw_readl(OMAP2_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_readl); + +void omap_writeb(u8 v, u32 pa) +{ + if (cpu_class_is_omap1()) + __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); + else + __raw_writeb(v, OMAP2_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_writeb); + +void omap_writew(u16 v, u32 pa) +{ + if (cpu_class_is_omap1()) + __raw_writew(v, OMAP1_IO_ADDRESS(pa)); + else + __raw_writew(v, OMAP2_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_writew); + +void omap_writel(u32 v, u32 pa) +{ + if (cpu_class_is_omap1()) + __raw_writel(v, OMAP1_IO_ADDRESS(pa)); + else + __raw_writel(v, OMAP2_IO_ADDRESS(pa)); +} +EXPORT_SYMBOL(omap_writel); diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c new file mode 100644 index 000000000000..c799b3b0d709 --- /dev/null +++ b/arch/arm/plat-omap/iommu-debug.c @@ -0,0 +1,415 @@ +/* + * omap iommu: debugfs interface + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/uaccess.h> +#include <linux/platform_device.h> +#include <linux/debugfs.h> + +#include <mach/iommu.h> +#include <mach/iovmm.h> + +#include "iopgtable.h" + +#define MAXCOLUMN 100 /* for short messages */ + +static DEFINE_MUTEX(iommu_debug_lock); + +static struct dentry *iommu_debug_root; + +static ssize_t debug_read_ver(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + u32 ver = iommu_arch_version(); + char buf[MAXCOLUMN], *p = buf; + + p += sprintf(p, "H/W version: %d.%d\n", (ver >> 4) & 0xf , ver & 0xf); + + return simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); +} + +static ssize_t debug_read_regs(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct iommu *obj = file->private_data; + char *p, *buf; + ssize_t bytes; + + buf = kmalloc(count, GFP_KERNEL); + if (!buf) + return -ENOMEM; + p = buf; + + mutex_lock(&iommu_debug_lock); + + bytes = iommu_dump_ctx(obj, p, count); + bytes = simple_read_from_buffer(userbuf, count, ppos, buf, bytes); + + mutex_unlock(&iommu_debug_lock); + kfree(buf); + + return bytes; +} + +static ssize_t debug_read_tlb(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct iommu *obj = file->private_data; + char *p, *buf; + ssize_t bytes, rest; + + buf = kmalloc(count, GFP_KERNEL); + if (!buf) + return -ENOMEM; + p = buf; + + mutex_lock(&iommu_debug_lock); + + p += sprintf(p, "%8s %8s\n", "cam:", "ram:"); + p += sprintf(p, "-----------------------------------------\n"); + rest = count - (p - buf); + p += dump_tlb_entries(obj, p, rest); + + bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); + + mutex_unlock(&iommu_debug_lock); + kfree(buf); + + return bytes; +} + +static ssize_t debug_write_pagetable(struct file *file, + const char __user *userbuf, size_t count, loff_t *ppos) +{ + struct iotlb_entry e; + struct cr_regs cr; + int err; + struct iommu *obj = file->private_data; + char buf[MAXCOLUMN], *p = buf; + + count = min(count, sizeof(buf)); + + mutex_lock(&iommu_debug_lock); + if (copy_from_user(p, userbuf, count)) { + mutex_unlock(&iommu_debug_lock); + return -EFAULT; + } + + sscanf(p, "%x %x", &cr.cam, &cr.ram); + if (!cr.cam || !cr.ram) { + mutex_unlock(&iommu_debug_lock); + return -EINVAL; + } + + iotlb_cr_to_e(&cr, &e); + err = iopgtable_store_entry(obj, &e); + if (err) + dev_err(obj->dev, "%s: fail to store cr\n", __func__); + + mutex_unlock(&iommu_debug_lock); + return count; +} + +#define dump_ioptable_entry_one(lv, da, val) \ + ({ \ + int __err = 0; \ + ssize_t bytes; \ + const int maxcol = 22; \ + const char *str = "%d: %08x %08x\n"; \ + bytes = snprintf(p, maxcol, str, lv, da, val); \ + p += bytes; \ + len -= bytes; \ + if (len < maxcol) \ + __err = -ENOMEM; \ + __err; \ + }) + +static ssize_t dump_ioptable(struct iommu *obj, char *buf, ssize_t len) +{ + int i; + u32 *iopgd; + char *p = buf; + + spin_lock(&obj->page_table_lock); + + iopgd = iopgd_offset(obj, 0); + for (i = 0; i < PTRS_PER_IOPGD; i++, iopgd++) { + int j, err; + u32 *iopte; + u32 da; + + if (!*iopgd) + continue; + + if (!(*iopgd & IOPGD_TABLE)) { + da = i << IOPGD_SHIFT; + + err = dump_ioptable_entry_one(1, da, *iopgd); + if (err) + goto out; + continue; + } + + iopte = iopte_offset(iopgd, 0); + + for (j = 0; j < PTRS_PER_IOPTE; j++, iopte++) { + if (!*iopte) + continue; + + da = (i << IOPGD_SHIFT) + (j << IOPTE_SHIFT); + err = dump_ioptable_entry_one(2, da, *iopgd); + if (err) + goto out; + } + } +out: + spin_unlock(&obj->page_table_lock); + + return p - buf; +} + +static ssize_t debug_read_pagetable(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct iommu *obj = file->private_data; + char *p, *buf; + size_t bytes; + + buf = (char *)__get_free_page(GFP_KERNEL); + if (!buf) + return -ENOMEM; + p = buf; + + p += sprintf(p, "L: %8s %8s\n", "da:", "pa:"); + p += sprintf(p, "-----------------------------------------\n"); + + mutex_lock(&iommu_debug_lock); + + bytes = PAGE_SIZE - (p - buf); + p += dump_ioptable(obj, p, bytes); + + bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); + + mutex_unlock(&iommu_debug_lock); + free_page((unsigned long)buf); + + return bytes; +} + +static ssize_t debug_read_mmap(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct iommu *obj = file->private_data; + char *p, *buf; + struct iovm_struct *tmp; + int uninitialized_var(i); + ssize_t bytes; + + buf = (char *)__get_free_page(GFP_KERNEL); + if (!buf) + return -ENOMEM; + p = buf; + + p += sprintf(p, "%-3s %-8s %-8s %6s %8s\n", + "No", "start", "end", "size", "flags"); + p += sprintf(p, "-------------------------------------------------\n"); + + mutex_lock(&iommu_debug_lock); + + list_for_each_entry(tmp, &obj->mmap, list) { + size_t len; + const char *str = "%3d %08x-%08x %6x %8x\n"; + const int maxcol = 39; + + len = tmp->da_end - tmp->da_start; + p += snprintf(p, maxcol, str, + i, tmp->da_start, tmp->da_end, len, tmp->flags); + + if (PAGE_SIZE - (p - buf) < maxcol) + break; + i++; + } + + bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); + + mutex_unlock(&iommu_debug_lock); + free_page((unsigned long)buf); + + return bytes; +} + +static ssize_t debug_read_mem(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct iommu *obj = file->private_data; + char *p, *buf; + struct iovm_struct *area; + ssize_t bytes; + + count = min_t(ssize_t, count, PAGE_SIZE); + + buf = (char *)__get_free_page(GFP_KERNEL); + if (!buf) + return -ENOMEM; + p = buf; + + mutex_lock(&iommu_debug_lock); + + area = find_iovm_area(obj, (u32)ppos); + if (IS_ERR(area)) { + bytes = -EINVAL; + goto err_out; + } + memcpy(p, area->va, count); + p += count; + + bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); +err_out: + mutex_unlock(&iommu_debug_lock); + free_page((unsigned long)buf); + + return bytes; +} + +static ssize_t debug_write_mem(struct file *file, const char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct iommu *obj = file->private_data; + struct iovm_struct *area; + char *p, *buf; + + count = min_t(size_t, count, PAGE_SIZE); + + buf = (char *)__get_free_page(GFP_KERNEL); + if (!buf) + return -ENOMEM; + p = buf; + + mutex_lock(&iommu_debug_lock); + + if (copy_from_user(p, userbuf, count)) { + count = -EFAULT; + goto err_out; + } + + area = find_iovm_area(obj, (u32)ppos); + if (IS_ERR(area)) { + count = -EINVAL; + goto err_out; + } + memcpy(area->va, p, count); +err_out: + mutex_unlock(&iommu_debug_lock); + free_page((unsigned long)buf); + + return count; +} + +static int debug_open_generic(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +#define DEBUG_FOPS(name) \ + static const struct file_operations debug_##name##_fops = { \ + .open = debug_open_generic, \ + .read = debug_read_##name, \ + .write = debug_write_##name, \ + }; + +#define DEBUG_FOPS_RO(name) \ + static const struct file_operations debug_##name##_fops = { \ + .open = debug_open_generic, \ + .read = debug_read_##name, \ + }; + +DEBUG_FOPS_RO(ver); +DEBUG_FOPS_RO(regs); +DEBUG_FOPS_RO(tlb); +DEBUG_FOPS(pagetable); +DEBUG_FOPS_RO(mmap); +DEBUG_FOPS(mem); + +#define __DEBUG_ADD_FILE(attr, mode) \ + { \ + struct dentry *dent; \ + dent = debugfs_create_file(#attr, mode, parent, \ + obj, &debug_##attr##_fops); \ + if (!dent) \ + return -ENOMEM; \ + } + +#define DEBUG_ADD_FILE(name) __DEBUG_ADD_FILE(name, 600) +#define DEBUG_ADD_FILE_RO(name) __DEBUG_ADD_FILE(name, 400) + +static int iommu_debug_register(struct device *dev, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct iommu *obj = platform_get_drvdata(pdev); + struct dentry *d, *parent; + + if (!obj || !obj->dev) + return -EINVAL; + + d = debugfs_create_dir(obj->name, iommu_debug_root); + if (!d) + return -ENOMEM; + parent = d; + + d = debugfs_create_u8("nr_tlb_entries", 400, parent, + (u8 *)&obj->nr_tlb_entries); + if (!d) + return -ENOMEM; + + DEBUG_ADD_FILE_RO(ver); + DEBUG_ADD_FILE_RO(regs); + DEBUG_ADD_FILE_RO(tlb); + DEBUG_ADD_FILE(pagetable); + DEBUG_ADD_FILE_RO(mmap); + DEBUG_ADD_FILE(mem); + + return 0; +} + +static int __init iommu_debug_init(void) +{ + struct dentry *d; + int err; + + d = debugfs_create_dir("iommu", NULL); + if (!d) + return -ENOMEM; + iommu_debug_root = d; + + err = foreach_iommu_device(d, iommu_debug_register); + if (err) + goto err_out; + return 0; + +err_out: + debugfs_remove_recursive(iommu_debug_root); + return err; +} +module_init(iommu_debug_init) + +static void __exit iommu_debugfs_exit(void) +{ + debugfs_remove_recursive(iommu_debug_root); +} +module_exit(iommu_debugfs_exit) + +MODULE_DESCRIPTION("omap iommu: debugfs interface"); +MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 4a0301399013..4b6012707307 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -351,16 +351,14 @@ EXPORT_SYMBOL_GPL(flush_iotlb_all); #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) -ssize_t iommu_dump_ctx(struct iommu *obj, char *buf) +ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) { - ssize_t bytes; - if (!obj || !buf) return -EINVAL; clk_enable(obj->clk); - bytes = arch_iommu->dump_ctx(obj, buf); + bytes = arch_iommu->dump_ctx(obj, buf, bytes); clk_disable(obj->clk); @@ -368,7 +366,7 @@ ssize_t iommu_dump_ctx(struct iommu *obj, char *buf) } EXPORT_SYMBOL_GPL(iommu_dump_ctx); -static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs) +static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num) { int i; struct iotlb_lock saved, l; @@ -379,7 +377,7 @@ static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs) iotlb_lock_get(obj, &saved); memcpy(&l, &saved, sizeof(saved)); - for (i = 0; i < obj->nr_tlb_entries; i++) { + for (i = 0; i < num; i++) { struct cr_regs tmp; iotlb_lock_get(obj, &l); @@ -402,18 +400,21 @@ static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs) * @obj: target iommu * @buf: output buffer **/ -size_t dump_tlb_entries(struct iommu *obj, char *buf) +size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t bytes) { - int i, n; + int i, num; struct cr_regs *cr; char *p = buf; - cr = kcalloc(obj->nr_tlb_entries, sizeof(*cr), GFP_KERNEL); + num = bytes / sizeof(*cr); + num = min(obj->nr_tlb_entries, num); + + cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); if (!cr) return 0; - n = __dump_tlb_entries(obj, cr); - for (i = 0; i < n; i++) + num = __dump_tlb_entries(obj, cr, num); + for (i = 0; i < num; i++) p += iotlb_dump_cr(obj, cr + i, p); kfree(cr); diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c index 2fce2c151a95..6fc52fcbdc03 100644 --- a/arch/arm/plat-omap/iovmm.c +++ b/arch/arm/plat-omap/iovmm.c @@ -199,7 +199,7 @@ static void *vmap_sg(const struct sg_table *sgt) va += bytes; } - flush_cache_vmap(new->addr, total); + flush_cache_vmap(new->addr, new->addr + total); return new->addr; err_out: diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c new file mode 100644 index 000000000000..e98f0a2a6c26 --- /dev/null +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -0,0 +1,296 @@ +/* + * omap-pm-noop.c - OMAP power management interface - dummy version + * + * This code implements the OMAP power management interface to + * drivers, CPUIdle, CPUFreq, and DSP Bridge. It is strictly for + * debug/demonstration use, as it does nothing but printk() whenever a + * function is called (when DEBUG is defined, below) + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * Copyright (C) 2008-2009 Nokia Corporation + * Paul Walmsley + * + * Interface developed by (in alphabetical order): + * Karthik Dasu, Tony Lindgren, Rajendra Nayak, Sakari Poussa, Veeramanikandan + * Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, Richard Woodruff + */ + +#undef DEBUG + +#include <linux/init.h> +#include <linux/cpufreq.h> +#include <linux/device.h> + +/* Interface documentation is in mach/omap-pm.h */ +#include <mach/omap-pm.h> + +#include <mach/powerdomain.h> + +struct omap_opp *dsp_opps; +struct omap_opp *mpu_opps; +struct omap_opp *l3_opps; + +/* + * Device-driver-originated constraints (via board-*.c files) + */ + +void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) +{ + if (!dev || t < -1) { + WARN_ON(1); + return; + }; + + if (t == -1) + pr_debug("OMAP PM: remove max MPU wakeup latency constraint: " + "dev %s\n", dev_name(dev)); + else + pr_debug("OMAP PM: add max MPU wakeup latency constraint: " + "dev %s, t = %ld usec\n", dev_name(dev), t); + + /* + * For current Linux, this needs to map the MPU to a + * powerdomain, then go through the list of current max lat + * constraints on the MPU and find the smallest. If + * the latency constraint has changed, the code should + * recompute the state to enter for the next powerdomain + * state. + * + * TI CDP code can call constraint_set here. + */ +} + +void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) +{ + if (!dev || (agent_id != OCP_INITIATOR_AGENT && + agent_id != OCP_TARGET_AGENT)) { + WARN_ON(1); + return; + }; + + if (r == 0) + pr_debug("OMAP PM: remove min bus tput constraint: " + "dev %s for agent_id %d\n", dev_name(dev), agent_id); + else + pr_debug("OMAP PM: add min bus tput constraint: " + "dev %s for agent_id %d: rate %ld KiB\n", + dev_name(dev), agent_id, r); + + /* + * This code should model the interconnect and compute the + * required clock frequency, convert that to a VDD2 OPP ID, then + * set the VDD2 OPP appropriately. + * + * TI CDP code can call constraint_set here on the VDD2 OPP. + */ +} + +void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t) +{ + if (!dev || t < -1) { + WARN_ON(1); + return; + }; + + if (t == -1) + pr_debug("OMAP PM: remove max device latency constraint: " + "dev %s\n", dev_name(dev)); + else + pr_debug("OMAP PM: add max device latency constraint: " + "dev %s, t = %ld usec\n", dev_name(dev), t); + + /* + * For current Linux, this needs to map the device to a + * powerdomain, then go through the list of current max lat + * constraints on that powerdomain and find the smallest. If + * the latency constraint has changed, the code should + * recompute the state to enter for the next powerdomain + * state. Conceivably, this code should also determine + * whether to actually disable the device clocks or not, + * depending on how long it takes to re-enable the clocks. + * + * TI CDP code can call constraint_set here. + */ +} + +void omap_pm_set_max_sdma_lat(struct device *dev, long t) +{ + if (!dev || t < -1) { + WARN_ON(1); + return; + }; + + if (t == -1) + pr_debug("OMAP PM: remove max DMA latency constraint: " + "dev %s\n", dev_name(dev)); + else + pr_debug("OMAP PM: add max DMA latency constraint: " + "dev %s, t = %ld usec\n", dev_name(dev), t); + + /* + * For current Linux PM QOS params, this code should scan the + * list of maximum CPU and DMA latencies and select the + * smallest, then set cpu_dma_latency pm_qos_param + * accordingly. + * + * For future Linux PM QOS params, with separate CPU and DMA + * latency params, this code should just set the dma_latency param. + * + * TI CDP code can call constraint_set here. + */ + +} + + +/* + * DSP Bridge-specific constraints + */ + +const struct omap_opp *omap_pm_dsp_get_opp_table(void) +{ + pr_debug("OMAP PM: DSP request for OPP table\n"); + + /* + * Return DSP frequency table here: The final item in the + * array should have .rate = .opp_id = 0. + */ + + return NULL; +} + +void omap_pm_dsp_set_min_opp(u8 opp_id) +{ + if (opp_id == 0) { + WARN_ON(1); + return; + } + + pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id); + + /* + * + * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we + * can just test to see which is higher, the CPU's desired OPP + * ID or the DSP's desired OPP ID, and use whichever is + * highest. + * + * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP + * rate is keyed on MPU speed, not the OPP ID. So we need to + * map the OPP ID to the MPU speed for use with clk_set_rate() + * if it is higher than the current OPP clock rate. + * + */ +} + + +u8 omap_pm_dsp_get_opp(void) +{ + pr_debug("OMAP PM: DSP requests current DSP OPP ID\n"); + + /* + * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock + * + * CDP12.14+: + * Call clk_get_rate() on the OPP custom clock, map that to an + * OPP ID using the tables defined in board-*.c/chip-*.c files. + */ + + return 0; +} + +/* + * CPUFreq-originated constraint + * + * In the future, this should be handled by custom OPP clocktype + * functions. + */ + +struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void) +{ + pr_debug("OMAP PM: CPUFreq request for frequency table\n"); + + /* + * Return CPUFreq frequency table here: loop over + * all VDD1 clkrates, pull out the mpu_ck frequencies, build + * table + */ + + return NULL; +} + +void omap_pm_cpu_set_freq(unsigned long f) +{ + if (f == 0) { + WARN_ON(1); + return; + } + + pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n", + f); + + /* + * For l-o dev tree, determine whether MPU freq or DSP OPP id + * freq is higher. Find the OPP ID corresponding to the + * higher frequency. Call clk_round_rate() and clk_set_rate() + * on the OPP custom clock. + * + * CDP should just be able to set the VDD1 OPP clock rate here. + */ +} + +unsigned long omap_pm_cpu_get_freq(void) +{ + pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n"); + + /* + * Call clk_get_rate() on the mpu_ck. + */ + + return 0; +} + +/* + * Device context loss tracking + */ + +int omap_pm_get_dev_context_loss_count(struct device *dev) +{ + if (!dev) { + WARN_ON(1); + return -EINVAL; + }; + + pr_debug("OMAP PM: returning context loss count for dev %s\n", + dev_name(dev)); + + /* + * Map the device to the powerdomain. Return the powerdomain + * off counter. + */ + + return 0; +} + + +/* Should be called before clk framework init */ +int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table, + struct omap_opp *dsp_opp_table, + struct omap_opp *l3_opp_table) +{ + mpu_opps = mpu_opp_table; + dsp_opps = dsp_opp_table; + l3_opps = l3_opp_table; + return 0; +} + +/* Must be called after clock framework is initialized */ +int __init omap_pm_if_init(void) +{ + return 0; +} + +void omap_pm_if_exit(void) +{ + /* Deallocate CPUFreq frequency table here */ +} + diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c new file mode 100644 index 000000000000..2c409fc6dd21 --- /dev/null +++ b/arch/arm/plat-omap/omap_device.c @@ -0,0 +1,687 @@ +/* + * omap_device implementation + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * Developed in collaboration with (alphabetical order): Benoit + * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram + * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard + * Woodruff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This code provides a consistent interface for OMAP device drivers + * to control power management and interconnect properties of their + * devices. + * + * In the medium- to long-term, this code should either be + * a) implemented via arch-specific pointers in platform_data + * or + * b) implemented as a proper omap_bus/omap_device in Linux, no more + * platform_data func pointers + * + * + * Guidelines for usage by driver authors: + * + * 1. These functions are intended to be used by device drivers via + * function pointers in struct platform_data. As an example, + * omap_device_enable() should be passed to the driver as + * + * struct foo_driver_platform_data { + * ... + * int (*device_enable)(struct platform_device *pdev); + * ... + * } + * + * Note that the generic "device_enable" name is used, rather than + * "omap_device_enable". This is so other architectures can pass in their + * own enable/disable functions here. + * + * This should be populated during device setup: + * + * ... + * pdata->device_enable = omap_device_enable; + * ... + * + * 2. Drivers should first check to ensure the function pointer is not null + * before calling it, as in: + * + * if (pdata->device_enable) + * pdata->device_enable(pdev); + * + * This allows other architectures that don't use similar device_enable()/ + * device_shutdown() functions to execute normally. + * + * ... + * + * Suggested usage by device drivers: + * + * During device initialization: + * device_enable() + * + * During device idle: + * (save remaining device context if necessary) + * device_idle(); + * + * During device resume: + * device_enable(); + * (restore context if necessary) + * + * During device shutdown: + * device_shutdown() + * (device must be reinitialized at this point to use it again) + * + */ +#undef DEBUG + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <mach/omap_device.h> +#include <mach/omap_hwmod.h> + +/* These parameters are passed to _omap_device_{de,}activate() */ +#define USE_WAKEUP_LAT 0 +#define IGNORE_WAKEUP_LAT 1 + +/* XXX this should be moved into a separate file */ +#if defined(CONFIG_ARCH_OMAP2420) +# define OMAP_32KSYNCT_BASE 0x48004000 +#elif defined(CONFIG_ARCH_OMAP2430) +# define OMAP_32KSYNCT_BASE 0x49020000 +#elif defined(CONFIG_ARCH_OMAP3430) +# define OMAP_32KSYNCT_BASE 0x48320000 +#else +# error Unknown OMAP device +#endif + +/* Private functions */ + +/** + * _read_32ksynct - read the OMAP 32K sync timer + * + * Returns the current value of the 32KiHz synchronization counter. + * XXX this should be generalized to simply read the system clocksource. + * XXX this should be moved to a separate synctimer32k.c file + */ +static u32 _read_32ksynct(void) +{ + if (!cpu_class_is_omap2()) + BUG(); + + return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010)); +} + +/** + * _omap_device_activate - increase device readiness + * @od: struct omap_device * + * @ignore_lat: increase to latency target (0) or full readiness (1)? + * + * Increase readiness of omap_device @od (thus decreasing device + * wakeup latency, but consuming more power). If @ignore_lat is + * IGNORE_WAKEUP_LAT, make the omap_device fully active. Otherwise, + * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup + * latency is greater than the requested maximum wakeup latency, step + * backwards in the omap_device_pm_latency table to ensure the + * device's maximum wakeup latency is less than or equal to the + * requested maximum wakeup latency. Returns 0. + */ +static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) +{ + u32 a, b; + + pr_debug("omap_device: %s: activating\n", od->pdev.name); + + while (od->pm_lat_level > 0) { + struct omap_device_pm_latency *odpl; + int act_lat = 0; + + od->pm_lat_level--; + + odpl = od->pm_lats + od->pm_lat_level; + + if (!ignore_lat && + (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit)) + break; + + a = _read_32ksynct(); + + /* XXX check return code */ + odpl->activate_func(od); + + b = _read_32ksynct(); + + act_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */ + + pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " + "%d usec\n", od->pdev.name, od->pm_lat_level, act_lat); + + WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: " + "activate step %d took longer than expected (%d > %d)\n", + od->pdev.name, od->pdev.id, od->pm_lat_level, + act_lat, odpl->activate_lat); + + od->dev_wakeup_lat -= odpl->activate_lat; + } + + return 0; +} + +/** + * _omap_device_deactivate - decrease device readiness + * @od: struct omap_device * + * @ignore_lat: decrease to latency target (0) or full inactivity (1)? + * + * Decrease readiness of omap_device @od (thus increasing device + * wakeup latency, but conserving power). If @ignore_lat is + * IGNORE_WAKEUP_LAT, make the omap_device fully inactive. Otherwise, + * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup + * latency is less than the requested maximum wakeup latency, step + * forwards in the omap_device_pm_latency table to ensure the device's + * maximum wakeup latency is less than or equal to the requested + * maximum wakeup latency. Returns 0. + */ +static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) +{ + u32 a, b; + + pr_debug("omap_device: %s: deactivating\n", od->pdev.name); + + while (od->pm_lat_level < od->pm_lats_cnt) { + struct omap_device_pm_latency *odpl; + int deact_lat = 0; + + odpl = od->pm_lats + od->pm_lat_level; + + if (!ignore_lat && + ((od->dev_wakeup_lat + odpl->activate_lat) > + od->_dev_wakeup_lat_limit)) + break; + + a = _read_32ksynct(); + + /* XXX check return code */ + odpl->deactivate_func(od); + + b = _read_32ksynct(); + + deact_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */ + + pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " + "%d usec\n", od->pdev.name, od->pm_lat_level, + deact_lat); + + WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: " + "deactivate step %d took longer than expected (%d > %d)\n", + od->pdev.name, od->pdev.id, od->pm_lat_level, + deact_lat, odpl->deactivate_lat); + + od->dev_wakeup_lat += odpl->activate_lat; + + od->pm_lat_level++; + } + + return 0; +} + +static inline struct omap_device *_find_by_pdev(struct platform_device *pdev) +{ + return container_of(pdev, struct omap_device, pdev); +} + + +/* Public functions for use by core code */ + +/** + * omap_device_count_resources - count number of struct resource entries needed + * @od: struct omap_device * + * + * Count the number of struct resource entries needed for this + * omap_device @od. Used by omap_device_build_ss() to determine how + * much memory to allocate before calling + * omap_device_fill_resources(). Returns the count. + */ +int omap_device_count_resources(struct omap_device *od) +{ + struct omap_hwmod *oh; + int c = 0; + int i; + + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + c += omap_hwmod_count_resources(oh); + + pr_debug("omap_device: %s: counted %d total resources across %d " + "hwmods\n", od->pdev.name, c, od->hwmods_cnt); + + return c; +} + +/** + * omap_device_fill_resources - fill in array of struct resource + * @od: struct omap_device * + * @res: pointer to an array of struct resource to be filled in + * + * Populate one or more empty struct resource pointed to by @res with + * the resource data for this omap_device @od. Used by + * omap_device_build_ss() after calling omap_device_count_resources(). + * Ideally this function would not be needed at all. If omap_device + * replaces platform_device, then we can specify our own + * get_resource()/ get_irq()/etc functions that use the underlying + * omap_hwmod information. Or if platform_device is extended to use + * subarchitecture-specific function pointers, the various + * platform_device functions can simply call omap_device internal + * functions to get device resources. Hacking around the existing + * platform_device code wastes memory. Returns 0. + */ +int omap_device_fill_resources(struct omap_device *od, struct resource *res) +{ + struct omap_hwmod *oh; + int c = 0; + int i, r; + + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) { + r = omap_hwmod_fill_resources(oh, res); + res += r; + c += r; + } + + return 0; +} + +/** + * omap_device_build - build and register an omap_device with one omap_hwmod + * @pdev_name: name of the platform_device driver to use + * @pdev_id: this platform_device's connection ID + * @oh: ptr to the single omap_hwmod that backs this omap_device + * @pdata: platform_data ptr to associate with the platform_device + * @pdata_len: amount of memory pointed to by @pdata + * @pm_lats: pointer to a omap_device_pm_latency array for this device + * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats + * + * Convenience function for building and registering a single + * omap_device record, which in turn builds and registers a + * platform_device record. See omap_device_build_ss() for more + * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise, + * passes along the return value of omap_device_build_ss(). + */ +struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, + struct omap_hwmod *oh, void *pdata, + int pdata_len, + struct omap_device_pm_latency *pm_lats, + int pm_lats_cnt) +{ + struct omap_hwmod *ohs[] = { oh }; + + if (!oh) + return ERR_PTR(-EINVAL); + + return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata, + pdata_len, pm_lats, pm_lats_cnt); +} + +/** + * omap_device_build_ss - build and register an omap_device with multiple hwmods + * @pdev_name: name of the platform_device driver to use + * @pdev_id: this platform_device's connection ID + * @oh: ptr to the single omap_hwmod that backs this omap_device + * @pdata: platform_data ptr to associate with the platform_device + * @pdata_len: amount of memory pointed to by @pdata + * @pm_lats: pointer to a omap_device_pm_latency array for this device + * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats + * + * Convenience function for building and registering an omap_device + * subsystem record. Subsystem records consist of multiple + * omap_hwmods. This function in turn builds and registers a + * platform_device record. Returns an ERR_PTR() on error, or passes + * along the return value of omap_device_register(). + */ +struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, + struct omap_hwmod **ohs, int oh_cnt, + void *pdata, int pdata_len, + struct omap_device_pm_latency *pm_lats, + int pm_lats_cnt) +{ + int ret = -ENOMEM; + struct omap_device *od; + char *pdev_name2; + struct resource *res = NULL; + int res_count; + struct omap_hwmod **hwmods; + + if (!ohs || oh_cnt == 0 || !pdev_name) + return ERR_PTR(-EINVAL); + + if (!pdata && pdata_len > 0) + return ERR_PTR(-EINVAL); + + pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name, + oh_cnt); + + od = kzalloc(sizeof(struct omap_device), GFP_KERNEL); + if (!od) + return ERR_PTR(-ENOMEM); + + od->hwmods_cnt = oh_cnt; + + hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, + GFP_KERNEL); + if (!hwmods) + goto odbs_exit1; + + memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt); + od->hwmods = hwmods; + + pdev_name2 = kzalloc(strlen(pdev_name) + 1, GFP_KERNEL); + if (!pdev_name2) + goto odbs_exit2; + strcpy(pdev_name2, pdev_name); + + od->pdev.name = pdev_name2; + od->pdev.id = pdev_id; + + res_count = omap_device_count_resources(od); + if (res_count > 0) { + res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL); + if (!res) + goto odbs_exit3; + } + omap_device_fill_resources(od, res); + + od->pdev.num_resources = res_count; + od->pdev.resource = res; + + platform_device_add_data(&od->pdev, pdata, pdata_len); + + od->pm_lats = pm_lats; + od->pm_lats_cnt = pm_lats_cnt; + + ret = omap_device_register(od); + if (ret) + goto odbs_exit4; + + return od; + +odbs_exit4: + kfree(res); +odbs_exit3: + kfree(pdev_name2); +odbs_exit2: + kfree(hwmods); +odbs_exit1: + kfree(od); + + pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret); + + return ERR_PTR(ret); +} + +/** + * omap_device_register - register an omap_device with one omap_hwmod + * @od: struct omap_device * to register + * + * Register the omap_device structure. This currently just calls + * platform_device_register() on the underlying platform_device. + * Returns the return value of platform_device_register(). + */ +int omap_device_register(struct omap_device *od) +{ + pr_debug("omap_device: %s: registering\n", od->pdev.name); + + return platform_device_register(&od->pdev); +} + + +/* Public functions for use by device drivers through struct platform_data */ + +/** + * omap_device_enable - fully activate an omap_device + * @od: struct omap_device * to activate + * + * Do whatever is necessary for the hwmods underlying omap_device @od + * to be accessible and ready to operate. This generally involves + * enabling clocks, setting SYSCONFIG registers; and in the future may + * involve remuxing pins. Device drivers should call this function + * (through platform_data function pointers) where they would normally + * enable clocks, etc. Returns -EINVAL if called when the omap_device + * is already enabled, or passes along the return value of + * _omap_device_activate(). + */ +int omap_device_enable(struct platform_device *pdev) +{ + int ret; + struct omap_device *od; + + od = _find_by_pdev(pdev); + + if (od->_state == OMAP_DEVICE_STATE_ENABLED) { + WARN(1, "omap_device: %s.%d: omap_device_enable() called from " + "invalid state\n", od->pdev.name, od->pdev.id); + return -EINVAL; + } + + /* Enable everything if we're enabling this device from scratch */ + if (od->_state == OMAP_DEVICE_STATE_UNKNOWN) + od->pm_lat_level = od->pm_lats_cnt; + + ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT); + + od->dev_wakeup_lat = 0; + od->_dev_wakeup_lat_limit = INT_MAX; + od->_state = OMAP_DEVICE_STATE_ENABLED; + + return ret; +} + +/** + * omap_device_idle - idle an omap_device + * @od: struct omap_device * to idle + * + * Idle omap_device @od by calling as many .deactivate_func() entries + * in the omap_device's pm_lats table as is possible without exceeding + * the device's maximum wakeup latency limit, pm_lat_limit. Device + * drivers should call this function (through platform_data function + * pointers) where they would normally disable clocks after operations + * complete, etc.. Returns -EINVAL if the omap_device is not + * currently enabled, or passes along the return value of + * _omap_device_deactivate(). + */ +int omap_device_idle(struct platform_device *pdev) +{ + int ret; + struct omap_device *od; + + od = _find_by_pdev(pdev); + + if (od->_state != OMAP_DEVICE_STATE_ENABLED) { + WARN(1, "omap_device: %s.%d: omap_device_idle() called from " + "invalid state\n", od->pdev.name, od->pdev.id); + return -EINVAL; + } + + ret = _omap_device_deactivate(od, USE_WAKEUP_LAT); + + od->_state = OMAP_DEVICE_STATE_IDLE; + + return ret; +} + +/** + * omap_device_shutdown - shut down an omap_device + * @od: struct omap_device * to shut down + * + * Shut down omap_device @od by calling all .deactivate_func() entries + * in the omap_device's pm_lats table and then shutting down all of + * the underlying omap_hwmods. Used when a device is being "removed" + * or a device driver is being unloaded. Returns -EINVAL if the + * omap_device is not currently enabled or idle, or passes along the + * return value of _omap_device_deactivate(). + */ +int omap_device_shutdown(struct platform_device *pdev) +{ + int ret, i; + struct omap_device *od; + struct omap_hwmod *oh; + + od = _find_by_pdev(pdev); + + if (od->_state != OMAP_DEVICE_STATE_ENABLED && + od->_state != OMAP_DEVICE_STATE_IDLE) { + WARN(1, "omap_device: %s.%d: omap_device_shutdown() called " + "from invalid state\n", od->pdev.name, od->pdev.id); + return -EINVAL; + } + + ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT); + + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_shutdown(oh); + + od->_state = OMAP_DEVICE_STATE_SHUTDOWN; + + return ret; +} + +/** + * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim + * @od: struct omap_device * + * + * When a device's maximum wakeup latency limit changes, call some of + * the .activate_func or .deactivate_func function pointers in the + * omap_device's pm_lats array to ensure that the device's maximum + * wakeup latency is less than or equal to the new latency limit. + * Intended to be called by OMAP PM code whenever a device's maximum + * wakeup latency limit changes (e.g., via + * omap_pm_set_dev_wakeup_lat()). Returns 0 if nothing needs to be + * done (e.g., if the omap_device is not currently idle, or if the + * wakeup latency is already current with the new limit) or passes + * along the return value of _omap_device_deactivate() or + * _omap_device_activate(). + */ +int omap_device_align_pm_lat(struct platform_device *pdev, + u32 new_wakeup_lat_limit) +{ + int ret = -EINVAL; + struct omap_device *od; + + od = _find_by_pdev(pdev); + + if (new_wakeup_lat_limit == od->dev_wakeup_lat) + return 0; + + od->_dev_wakeup_lat_limit = new_wakeup_lat_limit; + + if (od->_state != OMAP_DEVICE_STATE_IDLE) + return 0; + else if (new_wakeup_lat_limit > od->dev_wakeup_lat) + ret = _omap_device_deactivate(od, USE_WAKEUP_LAT); + else if (new_wakeup_lat_limit < od->dev_wakeup_lat) + ret = _omap_device_activate(od, USE_WAKEUP_LAT); + + return ret; +} + +/** + * omap_device_get_pwrdm - return the powerdomain * associated with @od + * @od: struct omap_device * + * + * Return the powerdomain associated with the first underlying + * omap_hwmod for this omap_device. Intended for use by core OMAP PM + * code. Returns NULL on error or a struct powerdomain * upon + * success. + */ +struct powerdomain *omap_device_get_pwrdm(struct omap_device *od) +{ + /* + * XXX Assumes that all omap_hwmod powerdomains are identical. + * This may not necessarily be true. There should be a sanity + * check in here to WARN() if any difference appears. + */ + if (!od->hwmods_cnt) + return NULL; + + return omap_hwmod_get_pwrdm(od->hwmods[0]); +} + +/* + * Public functions intended for use in omap_device_pm_latency + * .activate_func and .deactivate_func function pointers + */ + +/** + * omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods + * @od: struct omap_device *od + * + * Enable all underlying hwmods. Returns 0. + */ +int omap_device_enable_hwmods(struct omap_device *od) +{ + struct omap_hwmod *oh; + int i; + + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_enable(oh); + + /* XXX pass along return value here? */ + return 0; +} + +/** + * omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods + * @od: struct omap_device *od + * + * Idle all underlying hwmods. Returns 0. + */ +int omap_device_idle_hwmods(struct omap_device *od) +{ + struct omap_hwmod *oh; + int i; + + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_idle(oh); + + /* XXX pass along return value here? */ + return 0; +} + +/** + * omap_device_disable_clocks - disable all main and interface clocks + * @od: struct omap_device *od + * + * Disable the main functional clock and interface clock for all of the + * omap_hwmods associated with the omap_device. Returns 0. + */ +int omap_device_disable_clocks(struct omap_device *od) +{ + struct omap_hwmod *oh; + int i; + + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_disable_clocks(oh); + + /* XXX pass along return value here? */ + return 0; +} + +/** + * omap_device_enable_clocks - enable all main and interface clocks + * @od: struct omap_device *od + * + * Enable the main functional clock and interface clock for all of the + * omap_hwmods associated with the omap_device. Returns 0. + */ +int omap_device_enable_clocks(struct omap_device *od) +{ + struct omap_hwmod *oh; + int i; + + for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) + omap_hwmod_enable_clocks(oh); + + /* XXX pass along return value here? */ + return 0; +} diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 5eae7876979c..925f64711c37 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -56,16 +56,16 @@ #define SRAM_BOOTLOADER_SZ 0x80 #endif -#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048) -#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050) -#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058) - -#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848) -#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850) -#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858) -#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880) -#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048) -#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0) +#define OMAP24XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68005048) +#define OMAP24XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68005050) +#define OMAP24XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68005058) + +#define OMAP34XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68012848) +#define OMAP34XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68012850) +#define OMAP34XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68012858) +#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_IO_ADDRESS(0x68012880) +#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_IO_ADDRESS(0x6C000048) +#define OMAP34XX_VA_CONTROL_STAT OMAP2_IO_ADDRESS(0x480022F0) #define GP_DEVICE 0x300 diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S index 7dbf41f68b52..cbe811fccfcc 100644 --- a/arch/frv/kernel/vmlinux.lds.S +++ b/arch/frv/kernel/vmlinux.lds.S @@ -35,50 +35,13 @@ SECTIONS #endif } _einittext = .; - .init.data : { INIT_DATA } - - . = ALIGN(8); - __setup_start = .; - .setup.init : { KEEP(*(.init.setup)) } - __setup_end = .; - - __initcall_start = .; - .initcall.init : { - INITCALLS - } - __initcall_end = .; - __con_initcall_start = .; - .con_initcall.init : { *(.con_initcall.init) } - __con_initcall_end = .; - SECURITY_INIT - . = ALIGN(4); - __alt_instructions = .; - .altinstructions : { *(.altinstructions) } - __alt_instructions_end = .; - .altinstr_replacement : { *(.altinstr_replacement) } + INIT_DATA_SECTION(8) PERCPU(4096) -#ifdef CONFIG_BLK_DEV_INITRD - . = ALIGN(4096); - __initramfs_start = .; - .init.ramfs : { *(.init.ramfs) } - __initramfs_end = .; -#endif - - . = ALIGN(THREAD_SIZE); + . = ALIGN(PAGE_SIZE); __init_end = .; - /* put sections together that have massive alignment issues */ - . = ALIGN(THREAD_SIZE); - .data.init_task : { - /* init task record & stack */ - *(.data.init_task) - } - - . = ALIGN(L1_CACHE_BYTES); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - .trap : { /* trap table management - read entry-table.S before modifying */ . = ALIGN(8192); @@ -124,13 +87,12 @@ SECTIONS } - . = ALIGN(8); /* Exception table */ - __start___ex_table = .; - __ex_table : { KEEP(*(__ex_table)) } - __stop___ex_table = .; + EXCEPTION_TABLE(8) _sdata = .; .data : { /* Data */ + INIT_TASK_DATA(THREAD_SIZE) + CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES) DATA_DATA *(.data.*) EXIT_DATA @@ -159,22 +121,8 @@ SECTIONS . = ALIGN(PAGE_SIZE); __kernel_image_end = .; - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - - .debug_line 0 : { *(.debug_line) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_frame 0 : { *(.debug_frame) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_str 0 : { *(.debug_str) } - .debug_ranges 0 : { *(.debug_ranges) } + STABS_DEBUG + DWARF_DEBUG .comment 0 : { *(.comment) } diff --git a/arch/ia64/include/asm/mca.h b/arch/ia64/include/asm/mca.h index 44a0b53df900..c171cdf0a789 100644 --- a/arch/ia64/include/asm/mca.h +++ b/arch/ia64/include/asm/mca.h @@ -145,12 +145,14 @@ extern void ia64_mca_ucmc_handler(struct pt_regs *, struct ia64_sal_os_state *); extern void ia64_init_handler(struct pt_regs *, struct switch_stack *, struct ia64_sal_os_state *); +extern void ia64_os_init_on_kdump(void); extern void ia64_monarch_init_handler(void); extern void ia64_slave_init_handler(void); extern void ia64_mca_cmc_vector_setup(void); extern int ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *)); extern void ia64_unreg_MCA_extension(void); extern unsigned long ia64_get_rnat(unsigned long *); +extern void ia64_set_psr_mc(void); extern void ia64_mca_printk(const char * fmt, ...) __attribute__ ((format (printf, 1, 2))); diff --git a/arch/ia64/kernel/crash.c b/arch/ia64/kernel/crash.c index f065093f8e9b..6631a9dfafdc 100644 --- a/arch/ia64/kernel/crash.c +++ b/arch/ia64/kernel/crash.c @@ -23,6 +23,7 @@ int kdump_status[NR_CPUS]; static atomic_t kdump_cpu_frozen; atomic_t kdump_in_progress; +static int kdump_freeze_monarch; static int kdump_on_init = 1; static int kdump_on_fatal_mca = 1; @@ -108,10 +109,38 @@ machine_crash_shutdown(struct pt_regs *pt) */ kexec_disable_iosapic(); #ifdef CONFIG_SMP + /* + * If kdump_on_init is set and an INIT is asserted here, kdump will + * be started again via INIT monarch. + */ + local_irq_disable(); + ia64_set_psr_mc(); /* mask MCA/INIT */ + if (atomic_inc_return(&kdump_in_progress) != 1) + unw_init_running(kdump_cpu_freeze, NULL); + + /* + * Now this cpu is ready for kdump. + * Stop all others by IPI or INIT. They could receive INIT from + * outside and might be INIT monarch, but only thing they have to + * do is falling into kdump_cpu_freeze(). + * + * If an INIT is asserted here: + * - All receivers might be slaves, since some of cpus could already + * be frozen and INIT might be masked on monarch. In this case, + * all slaves will be frozen soon since kdump_in_progress will let + * them into DIE_INIT_SLAVE_LEAVE. + * - One might be a monarch, but INIT rendezvous will fail since + * at least this cpu already have INIT masked so it never join + * to the rendezvous. In this case, all slaves and monarch will + * be frozen soon with no wait since the INIT rendezvous is skipped + * by kdump_in_progress. + */ kdump_smp_send_stop(); /* not all cpu response to IPI, send INIT to freeze them */ - if (kdump_wait_cpu_freeze() && kdump_on_init) { + if (kdump_wait_cpu_freeze()) { kdump_smp_send_init(); + /* wait again, don't go ahead if possible */ + kdump_wait_cpu_freeze(); } #endif } @@ -129,17 +158,17 @@ void kdump_cpu_freeze(struct unw_frame_info *info, void *arg) { int cpuid; + local_irq_disable(); cpuid = smp_processor_id(); crash_save_this_cpu(); current->thread.ksp = (__u64)info->sw - 16; + + ia64_set_psr_mc(); /* mask MCA/INIT and stop reentrance */ + atomic_inc(&kdump_cpu_frozen); kdump_status[cpuid] = 1; mb(); -#ifdef CONFIG_HOTPLUG_CPU - if (cpuid != 0) - ia64_jump_to_sal(&sal_boot_rendez_state[cpuid]); -#endif for (;;) cpu_relax(); } @@ -150,6 +179,20 @@ kdump_init_notifier(struct notifier_block *self, unsigned long val, void *data) struct ia64_mca_notify_die *nd; struct die_args *args = data; + if (atomic_read(&kdump_in_progress)) { + switch (val) { + case DIE_INIT_MONARCH_LEAVE: + if (!kdump_freeze_monarch) + break; + /* fall through */ + case DIE_INIT_SLAVE_LEAVE: + case DIE_INIT_MONARCH_ENTER: + case DIE_MCA_RENDZVOUS_LEAVE: + unw_init_running(kdump_cpu_freeze, NULL); + break; + } + } + if (!kdump_on_init && !kdump_on_fatal_mca) return NOTIFY_DONE; @@ -162,43 +205,31 @@ kdump_init_notifier(struct notifier_block *self, unsigned long val, void *data) } if (val != DIE_INIT_MONARCH_LEAVE && - val != DIE_INIT_SLAVE_LEAVE && val != DIE_INIT_MONARCH_PROCESS && - val != DIE_MCA_RENDZVOUS_LEAVE && val != DIE_MCA_MONARCH_LEAVE) return NOTIFY_DONE; nd = (struct ia64_mca_notify_die *)args->err; - /* Reason code 1 means machine check rendezvous*/ - if ((val == DIE_INIT_MONARCH_LEAVE || val == DIE_INIT_SLAVE_LEAVE - || val == DIE_INIT_MONARCH_PROCESS) && nd->sos->rv_rc == 1) - return NOTIFY_DONE; switch (val) { case DIE_INIT_MONARCH_PROCESS: - if (kdump_on_init) { - atomic_set(&kdump_in_progress, 1); - *(nd->monarch_cpu) = -1; + /* Reason code 1 means machine check rendezvous*/ + if (kdump_on_init && (nd->sos->rv_rc != 1)) { + if (atomic_inc_return(&kdump_in_progress) != 1) + kdump_freeze_monarch = 1; } break; case DIE_INIT_MONARCH_LEAVE: - if (kdump_on_init) + /* Reason code 1 means machine check rendezvous*/ + if (kdump_on_init && (nd->sos->rv_rc != 1)) machine_kdump_on_init(); break; - case DIE_INIT_SLAVE_LEAVE: - if (atomic_read(&kdump_in_progress)) - unw_init_running(kdump_cpu_freeze, NULL); - break; - case DIE_MCA_RENDZVOUS_LEAVE: - if (atomic_read(&kdump_in_progress)) - unw_init_running(kdump_cpu_freeze, NULL); - break; case DIE_MCA_MONARCH_LEAVE: /* *(nd->data) indicate if MCA is recoverable */ if (kdump_on_fatal_mca && !(*(nd->data))) { - atomic_set(&kdump_in_progress, 1); - *(nd->monarch_cpu) = -1; - machine_kdump_on_init(); + if (atomic_inc_return(&kdump_in_progress) == 1) + machine_kdump_on_init(); + /* We got fatal MCA while kdump!? No way!! */ } break; } diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S index 23f846de62d5..1a6e44515eb4 100644 --- a/arch/ia64/kernel/head.S +++ b/arch/ia64/kernel/head.S @@ -167,7 +167,7 @@ RestRR: \ mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \ mov rr[_tmp1]=_tmp2 - .section __special_page_section,"ax" + __PAGE_ALIGNED_DATA .global empty_zero_page empty_zero_page: @@ -181,7 +181,7 @@ swapper_pg_dir: halt_msg: stringz "Halting kernel\n" - .section .text.head,"ax" + __REF .global start_ap @@ -1242,7 +1242,7 @@ GLOBAL_ENTRY(ia64_jump_to_sal) movl r16=SAL_PSR_BITS_TO_SET;; mov cr.ipsr=r16 mov cr.ifs=r0;; - rfi;; + rfi;; // note: this unmask MCA/INIT (psr.mc) 1: /* * Invalidate all TLB data/inst diff --git a/arch/ia64/kernel/machine_kexec.c b/arch/ia64/kernel/machine_kexec.c index 0823de1f6ebe..3d3aeef46947 100644 --- a/arch/ia64/kernel/machine_kexec.c +++ b/arch/ia64/kernel/machine_kexec.c @@ -24,6 +24,8 @@ #include <asm/delay.h> #include <asm/meminit.h> #include <asm/processor.h> +#include <asm/sal.h> +#include <asm/mca.h> typedef NORET_TYPE void (*relocate_new_kernel_t)( unsigned long indirection_page, @@ -85,13 +87,26 @@ static void ia64_machine_kexec(struct unw_frame_info *info, void *arg) void *pal_addr = efi_get_pal_addr(); unsigned long code_addr = (unsigned long)page_address(image->control_code_page); int ii; + u64 fp, gp; + ia64_fptr_t *init_handler = (ia64_fptr_t *)ia64_os_init_on_kdump; BUG_ON(!image); if (image->type == KEXEC_TYPE_CRASH) { crash_save_this_cpu(); current->thread.ksp = (__u64)info->sw - 16; + + /* Register noop init handler */ + fp = ia64_tpa(init_handler->fp); + gp = ia64_tpa(ia64_getreg(_IA64_REG_GP)); + ia64_sal_set_vectors(SAL_VECTOR_OS_INIT, fp, gp, 0, fp, gp, 0); + } else { + /* Unregister init handlers of current kernel */ + ia64_sal_set_vectors(SAL_VECTOR_OS_INIT, 0, 0, 0, 0, 0, 0); } + /* Unregister mca handler - No more recovery on current kernel */ + ia64_sal_set_vectors(SAL_VECTOR_OS_MCA, 0, 0, 0, 0, 0, 0); + /* Interrupts aren't acceptable while we reboot */ local_irq_disable(); diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c index 7b30d21c5190..d2877a7bfe2e 100644 --- a/arch/ia64/kernel/mca.c +++ b/arch/ia64/kernel/mca.c @@ -1682,14 +1682,25 @@ ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw, if (!sos->monarch) { ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT; + +#ifdef CONFIG_KEXEC + while (monarch_cpu == -1 && !atomic_read(&kdump_in_progress)) + udelay(1000); +#else while (monarch_cpu == -1) - cpu_relax(); /* spin until monarch enters */ + cpu_relax(); /* spin until monarch enters */ +#endif NOTIFY_INIT(DIE_INIT_SLAVE_ENTER, regs, (long)&nd, 1); NOTIFY_INIT(DIE_INIT_SLAVE_PROCESS, regs, (long)&nd, 1); +#ifdef CONFIG_KEXEC + while (monarch_cpu != -1 && !atomic_read(&kdump_in_progress)) + udelay(1000); +#else while (monarch_cpu != -1) - cpu_relax(); /* spin until monarch leaves */ + cpu_relax(); /* spin until monarch leaves */ +#endif NOTIFY_INIT(DIE_INIT_SLAVE_LEAVE, regs, (long)&nd, 1); diff --git a/arch/ia64/kernel/mca_asm.S b/arch/ia64/kernel/mca_asm.S index a06d46548ff9..7461d2573d41 100644 --- a/arch/ia64/kernel/mca_asm.S +++ b/arch/ia64/kernel/mca_asm.S @@ -40,6 +40,7 @@ .global ia64_do_tlb_purge .global ia64_os_mca_dispatch + .global ia64_os_init_on_kdump .global ia64_os_init_dispatch_monarch .global ia64_os_init_dispatch_slave @@ -299,6 +300,25 @@ END(ia64_os_mca_virtual_begin) //StartMain//////////////////////////////////////////////////////////////////// // +// NOP init handler for kdump. In panic situation, we may receive INIT +// while kernel transition. Since we initialize registers on leave from +// current kernel, no longer monarch/slave handlers of current kernel in +// virtual mode are called safely. +// We can unregister these init handlers from SAL, however then the INIT +// will result in warmboot by SAL and we cannot retrieve the crashdump. +// Therefore register this NOP function to SAL, to prevent entering virtual +// mode and resulting warmboot by SAL. +// +ia64_os_init_on_kdump: + mov r8=r0 // IA64_INIT_RESUME + mov r9=r10 // SAL_GP + mov r22=r17 // *minstate + ;; + mov r10=r0 // return to same context + mov b0=r12 // SAL_CHECK return address + br b0 + +// // SAL to OS entry point for INIT on all processors. This has been defined for // registration purposes with SAL as a part of ia64_mca_init. Monarch and // slave INIT have identical processing, except for the value of the @@ -1073,3 +1093,30 @@ GLOBAL_ENTRY(ia64_get_rnat) mov ar.rsc=3 br.ret.sptk.many rp END(ia64_get_rnat) + + +// void ia64_set_psr_mc(void) +// +// Set psr.mc bit to mask MCA/INIT. +GLOBAL_ENTRY(ia64_set_psr_mc) + rsm psr.i | psr.ic // disable interrupts + ;; + srlz.d + ;; + mov r14 = psr // get psr{36:35,31:0} + movl r15 = 1f + ;; + dep r14 = -1, r14, PSR_MC, 1 // set psr.mc + ;; + dep r14 = -1, r14, PSR_IC, 1 // set psr.ic + ;; + dep r14 = -1, r14, PSR_BN, 1 // keep bank1 in use + ;; + mov cr.ipsr = r14 + mov cr.ifs = r0 + mov cr.iip = r15 + ;; + rfi +1: + br.ret.sptk.many rp +END(ia64_set_psr_mc) diff --git a/arch/ia64/kernel/relocate_kernel.S b/arch/ia64/kernel/relocate_kernel.S index 903babd22d62..32f6fc131fbe 100644 --- a/arch/ia64/kernel/relocate_kernel.S +++ b/arch/ia64/kernel/relocate_kernel.S @@ -52,7 +52,7 @@ GLOBAL_ENTRY(relocate_new_kernel) srlz.i ;; mov ar.rnat=r18 - rfi + rfi // note: this unmask MCA/INIT (psr.mc) ;; 1: //physical mode code begin diff --git a/arch/ia64/kernel/vmlinux.lds.S b/arch/ia64/kernel/vmlinux.lds.S index eb4214d1c5af..0a0c77b2c988 100644 --- a/arch/ia64/kernel/vmlinux.lds.S +++ b/arch/ia64/kernel/vmlinux.lds.S @@ -51,8 +51,6 @@ SECTIONS KPROBES_TEXT *(.gnu.linkonce.t*) } - .text.head : AT(ADDR(.text.head) - LOAD_OFFSET) - { *(.text.head) } .text2 : AT(ADDR(.text2) - LOAD_OFFSET) { *(.text2) } #ifdef CONFIG_SMP @@ -66,14 +64,7 @@ SECTIONS NOTES :code :note /* put .notes in text and mark in PT_NOTE */ code_continues : {} :code /* switch back to regular program... */ - /* Exception table */ - . = ALIGN(16); - __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) - { - __start___ex_table = .; - *(__ex_table) - __stop___ex_table = .; - } + EXCEPTION_TABLE(16) /* MCA table */ . = ALIGN(16); @@ -115,38 +106,9 @@ SECTIONS . = ALIGN(PAGE_SIZE); __init_begin = .; - .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) - { - _sinittext = .; - INIT_TEXT - _einittext = .; - } - - .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) - { INIT_DATA } -#ifdef CONFIG_BLK_DEV_INITRD - .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) - { - __initramfs_start = .; - *(.init.ramfs) - __initramfs_end = .; - } -#endif - - . = ALIGN(16); - .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) - { - __setup_start = .; - *(.init.setup) - __setup_end = .; - } - .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) - { - __initcall_start = .; - INITCALLS - __initcall_end = .; - } + INIT_TEXT_SECTION(PAGE_SIZE) + INIT_DATA_SECTION(16) .data.patch.vtop : AT(ADDR(.data.patch.vtop) - LOAD_OFFSET) { @@ -204,24 +166,13 @@ SECTIONS } #endif - . = ALIGN(8); - __con_initcall_start = .; - .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) - { *(.con_initcall.init) } - __con_initcall_end = .; - __security_initcall_start = .; - .security_initcall.init : AT(ADDR(.security_initcall.init) - LOAD_OFFSET) - { *(.security_initcall.init) } - __security_initcall_end = .; . = ALIGN(PAGE_SIZE); __init_end = .; - /* The initial task and kernel stack */ - .data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) - { *(.data.init_task) } - .data.page_aligned : AT(ADDR(.data.page_aligned) - LOAD_OFFSET) - { *(__special_page_section) + { + PAGE_ALIGNED_DATA(PAGE_SIZE) + . = ALIGN(PAGE_SIZE); __start_gate_section = .; *(.data.gate) __stop_gate_section = .; @@ -236,12 +187,6 @@ SECTIONS * kernel data */ - .data.read_mostly : AT(ADDR(.data.read_mostly) - LOAD_OFFSET) - { *(.data.read_mostly) } - - .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) - { *(.data.cacheline_aligned) } - /* Per-cpu data: */ . = ALIGN(PERCPU_PAGE_SIZE); PERCPU_VADDR(PERCPU_ADDR, :percpu) @@ -258,6 +203,9 @@ SECTIONS __cpu0_per_cpu = .; . = . + PERCPU_PAGE_SIZE; /* cpu0 per-cpu space */ #endif + INIT_TASK_DATA(PAGE_SIZE) + CACHELINE_ALIGNED_DATA(SMP_CACHE_BYTES) + READ_MOSTLY_DATA(SMP_CACHE_BYTES) DATA_DATA *(.data1) *(.gnu.linkonce.d*) @@ -274,48 +222,15 @@ SECTIONS .sdata : AT(ADDR(.sdata) - LOAD_OFFSET) { *(.sdata) *(.sdata1) *(.srdata) } _edata = .; - __bss_start = .; - .sbss : AT(ADDR(.sbss) - LOAD_OFFSET) - { *(.sbss) *(.scommon) } - .bss : AT(ADDR(.bss) - LOAD_OFFSET) - { *(.bss) *(COMMON) } - __bss_stop = .; + + BSS_SECTION(0, 0, 0) _end = .; code : { } :code - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } + + STABS_DEBUG + DWARF_DEBUG /* Default discards */ DISCARDS diff --git a/arch/ia64/sn/pci/pcibr/pcibr_ate.c b/arch/ia64/sn/pci/pcibr/pcibr_ate.c index 239b3cedcf2b..5bc34eac9e01 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_ate.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_ate.c @@ -54,6 +54,8 @@ static int find_free_ate(struct ate_resource *ate_resource, int start, break; } } + if (i >= ate_resource->num_ate) + return -1; } else index++; /* Try next ate */ } diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c index c2aa717de08a..a90acf5b0cde 100644 --- a/arch/m68knommu/kernel/time.c +++ b/arch/m68knommu/kernel/time.c @@ -72,9 +72,10 @@ static unsigned long read_rtc_mmss(void) return mktime(year, mon, day, hour, min, sec); } -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { - return read_rtc_mmss(); + ts->tv_sec = read_rtc_mmss(); + ts->tv_nsec = 0; } int update_persistent_clock(struct timespec now) diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index 463136e6685a..02f505f23c32 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -18,7 +18,7 @@ #include <asm/dec/ioasic.h> #include <asm/dec/machtype.h> -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { unsigned int year, mon, day, hour, min, sec, real_year; unsigned long flags; @@ -53,7 +53,8 @@ unsigned long read_persistent_clock(void) year += real_year - 72 + 2000; - return mktime(year, mon, day, hour, min, sec); + ts->tv_sec = mktime(year, mon, day, hour, min, sec); + ts->tv_nsec = 0; } /* diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c index 52cb1436a12a..c6fd96ff118d 100644 --- a/arch/mips/lasat/ds1603.c +++ b/arch/mips/lasat/ds1603.c @@ -135,7 +135,7 @@ static void rtc_end_op(void) lasat_ndelay(1000); } -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { unsigned long word; unsigned long flags; @@ -147,7 +147,8 @@ unsigned long read_persistent_clock(void) rtc_end_op(); spin_unlock_irqrestore(&rtc_lock, flags); - return word; + ts->tv_sec = word; + ts->tv_nsec = 0; } int rtc_mips_set_mmss(unsigned long time) diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index 8f88886feb12..3f04d4c406b7 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -92,10 +92,12 @@ static int rtctmp; int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, void *buffer, size_t *lenp, loff_t *ppos) { + struct timespec ts; int r; if (!write) { - rtctmp = read_persistent_clock(); + read_persistent_clock(&ts); + rtctmp = ts.tv_sec; /* check for time < 0 and set to 0 */ if (rtctmp < 0) rtctmp = 0; @@ -134,9 +136,11 @@ int sysctl_lasat_rtc(ctl_table *table, void *oldval, size_t *oldlenp, void *newval, size_t newlen) { + struct timespec ts; int r; - rtctmp = read_persistent_clock(); + read_persistent_clock(&ts); + rtctmp = ts.tv_sec; if (rtctmp < 0) rtctmp = 0; r = sysctl_intvec(table, oldval, oldlenp, newval, newlen); diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c index b13d17174654..6e08c8270abe 100644 --- a/arch/mips/loongson/common/time.c +++ b/arch/mips/loongson/common/time.c @@ -21,7 +21,8 @@ void __init plat_time_init(void) mips_hpt_frequency = cpu_clock_freq / 2; } -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { - return mc146818_get_cmos_time(); + ts->tv_sec = mc146818_get_cmos_time(); + ts->tv_nsec = 0; } diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 0b97d47691fc..3c6f190aa61c 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -100,9 +100,10 @@ static unsigned int __init estimate_cpu_frequency(void) return count; } -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { - return mc146818_get_cmos_time(); + ts->tv_sec = mc146818_get_cmos_time(); + ts->tv_nsec = 0; } static void __init plat_perf_setup(void) diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index 2d3c0dca275d..3498ac9c35af 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c @@ -70,7 +70,7 @@ void __init bus_error_init(void) } -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { unsigned int year, month, day, hour, min, sec; unsigned long flags; @@ -92,7 +92,8 @@ unsigned long read_persistent_clock(void) m48t37_base->control = 0x00; spin_unlock_irqrestore(&rtc_lock, flags); - return mktime(year, month, day, hour, min, sec); + ts->tv_sec = mktime(year, month, day, hour, min, sec); + ts->tv_nsec = 0; } int rtc_mips_set_time(unsigned long tim) diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 672e45d495a9..623ffc933c4c 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -87,19 +87,26 @@ enum swarm_rtc_type { enum swarm_rtc_type swarm_rtc_type; -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { + unsigned long sec; + switch (swarm_rtc_type) { case RTC_XICOR: - return xicor_get_time(); + sec = xicor_get_time(); + break; case RTC_M4LT81: - return m41t81_get_time(); + sec = m41t81_get_time(); + break; case RTC_NONE: default: - return mktime(2000, 1, 1, 0, 0, 0); + sec = mktime(2000, 1, 1, 0, 0, 0); + break; } + ts->tv_sec = sec; + tv->tv_nsec = 0; } int rtc_mips_set_time(unsigned long sec) diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 0d9ec1a5c24a..62df6a598e0a 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -182,7 +182,8 @@ void __init plat_time_init(void) setup_pit_timer(); } -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { - return -1; + ts->tv_sec = -1; + ts->tv_nsec = 0; } diff --git a/arch/mn10300/kernel/asm-offsets.c b/arch/mn10300/kernel/asm-offsets.c index 2646fcbd7d89..82b40079ad76 100644 --- a/arch/mn10300/kernel/asm-offsets.c +++ b/arch/mn10300/kernel/asm-offsets.c @@ -95,7 +95,7 @@ void foo(void) OFFSET(__iobase, mn10300_serial_port, _iobase); DEFINE(__UART_XMIT_SIZE, UART_XMIT_SIZE); - OFFSET(__xmit_buffer, uart_info, xmit.buf); - OFFSET(__xmit_head, uart_info, xmit.head); - OFFSET(__xmit_tail, uart_info, xmit.tail); + OFFSET(__xmit_buffer, uart_state, xmit.buf); + OFFSET(__xmit_head, uart_state, xmit.head); + OFFSET(__xmit_tail, uart_state, xmit.tail); } diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index a180b4f9a4f6..465e498bcb33 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -774,11 +774,12 @@ int update_persistent_clock(struct timespec now) return ppc_md.set_rtc_time(&tm); } -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { struct rtc_time tm; static int first = 1; + ts->tv_nsec = 0; /* XXX this is a litle fragile but will work okay in the short term */ if (first) { first = 0; @@ -786,14 +787,18 @@ unsigned long read_persistent_clock(void) timezone_offset = ppc_md.time_init(); /* get_boot_time() isn't guaranteed to be safe to call late */ - if (ppc_md.get_boot_time) - return ppc_md.get_boot_time() -timezone_offset; + if (ppc_md.get_boot_time) { + ts->tv_sec = ppc_md.get_boot_time() - timezone_offset; + return; + } + } + if (!ppc_md.get_rtc_time) { + ts->tv_sec = 0; + return; } - if (!ppc_md.get_rtc_time) - return 0; ppc_md.get_rtc_time(&tm); - return mktime(tm.tm_year+1900, tm.tm_mon+1, tm.tm_mday, - tm.tm_hour, tm.tm_min, tm.tm_sec); + ts->tv_sec = mktime(tm.tm_year+1900, tm.tm_mon+1, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec); } /* clocksource code */ diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c index c7ae4b17e0e3..e9d94f61d500 100644 --- a/arch/s390/kernel/sys_s390.c +++ b/arch/s390/kernel/sys_s390.c @@ -29,7 +29,6 @@ #include <linux/personality.h> #include <linux/unistd.h> #include <linux/ipc.h> -#include <linux/syscalls.h> #include <asm/uaccess.h> #include "entry.h" diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index e3dc28b8075d..34162a0b2caa 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -184,12 +184,14 @@ static void timing_alert_interrupt(__u16 code) static void etr_reset(void); static void stp_reset(void); -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { - struct timespec ts; + tod_to_timeval(get_clock() - TOD_UNIX_EPOCH, ts); +} - tod_to_timeval(get_clock() - TOD_UNIX_EPOCH, &ts); - return ts.tv_sec; +void read_boot_clock(struct timespec *ts) +{ + tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, ts); } static cycle_t read_tod_clock(struct clocksource *cs) @@ -207,6 +209,10 @@ static struct clocksource clocksource_tod = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +struct clocksource * __init clocksource_default_clock(void) +{ + return &clocksource_tod; +} void update_vsyscall(struct timespec *wall_time, struct clocksource *clock) { @@ -244,10 +250,6 @@ void update_vsyscall_tz(void) */ void __init time_init(void) { - struct timespec ts; - unsigned long flags; - cycle_t now; - /* Reset time synchronization interfaces. */ etr_reset(); stp_reset(); @@ -263,26 +265,6 @@ void __init time_init(void) if (clocksource_register(&clocksource_tod) != 0) panic("Could not register TOD clock source"); - /* - * The TOD clock is an accurate clock. The xtime should be - * initialized in a way that the difference between TOD and - * xtime is reasonably small. Too bad that timekeeping_init - * sets xtime.tv_nsec to zero. In addition the clock source - * change from the jiffies clock source to the TOD clock - * source add another error of up to 1/HZ second. The same - * function sets wall_to_monotonic to a value that is too - * small for /proc/uptime to be accurate. - * Reset xtime and wall_to_monotonic to sane values. - */ - write_seqlock_irqsave(&xtime_lock, flags); - now = get_clock(); - tod_to_timeval(now - TOD_UNIX_EPOCH, &xtime); - clocksource_tod.cycle_last = now; - clocksource_tod.raw_time = xtime; - tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, &ts); - set_normalized_timespec(&wall_to_monotonic, -ts.tv_sec, -ts.tv_nsec); - write_sequnlock_irqrestore(&xtime_lock, flags); - /* Enable TOD clock interrupts on the boot cpu. */ init_cpu_timer(); diff --git a/arch/score/Kconfig b/arch/score/Kconfig new file mode 100644 index 000000000000..55d413e6dcf2 --- /dev/null +++ b/arch/score/Kconfig @@ -0,0 +1,141 @@ +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/kconfig-language.txt. + +mainmenu "Linux/SCORE Kernel Configuration" + +menu "Machine selection" + +choice + prompt "System type" + default MACH_SPCT6600 + +config ARCH_SCORE7 + bool "SCORE7 processor" + select SYS_SUPPORTS_32BIT_KERNEL + select CPU_SCORE7 + select GENERIC_HAS_IOMAP + +config MACH_SPCT6600 + bool "SPCT6600 series based machines" + select SYS_SUPPORTS_32BIT_KERNEL + select CPU_SCORE7 + select GENERIC_HAS_IOMAP + +config SCORE_SIM + bool "Score simulator" + select SYS_SUPPORTS_32BIT_KERNEL + select CPU_SCORE7 + select GENERIC_HAS_IOMAP +endchoice + +endmenu + +config CPU_SCORE7 + bool + +config GENERIC_IOMAP + def_bool y + +config NO_DMA + bool + default y + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config GENERIC_FIND_NEXT_BIT + def_bool y + +config GENERIC_HWEIGHT + def_bool y + +config GENERIC_CALIBRATE_DELAY + def_bool y + +config GENERIC_CLOCKEVENTS + def_bool y + +config GENERIC_TIME + def_bool y + +config SCHED_NO_NO_OMIT_FRAME_POINTER + def_bool y + +config GENERIC_HARDIRQS_NO__DO_IRQ + def_bool y + +config GENERIC_SYSCALL_TABLE + def_bool y + +config SCORE_L1_CACHE_SHIFT + int + default "4" + +menu "Kernel type" + +config 32BIT + def_bool y + +config GENERIC_HARDIRQS + def_bool y + +config ARCH_FLATMEM_ENABLE + def_bool y + +config ARCH_POPULATES_NODE_MAP + def_bool y + +source "mm/Kconfig" + +config MEMORY_START + hex + default 0xa0000000 + +source "kernel/time/Kconfig" +source "kernel/Kconfig.hz" +source "kernel/Kconfig.preempt" + +endmenu + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config LOCKDEP_SUPPORT + def_bool y + +config STACKTRACE_SUPPORT + def_bool y + +source "init/Kconfig" + +config PROBE_INITRD_HEADER + bool "Probe initrd header created by addinitrd" + depends on BLK_DEV_INITRD + help + Probe initrd header at the last page of kernel image. + Say Y here if you are using arch/score/boot/addinitrd.c to + add initrd or initramfs image to the kernel image. + Otherwise, say N. + +config MMU + def_bool y + +menu "Executable file formats" + +source "fs/Kconfig.binfmt" + +endmenu + +source "net/Kconfig" + +source "drivers/Kconfig" + +source "fs/Kconfig" + +source "arch/score/Kconfig.debug" + +source "security/Kconfig" + +source "crypto/Kconfig" + +source "lib/Kconfig" diff --git a/arch/score/Kconfig.debug b/arch/score/Kconfig.debug new file mode 100644 index 000000000000..451ed54ce646 --- /dev/null +++ b/arch/score/Kconfig.debug @@ -0,0 +1,37 @@ +menu "Kernel hacking" + +config TRACE_IRQFLAGS_SUPPORT + bool + default y + +source "lib/Kconfig.debug" + +config CMDLINE + string "Default kernel command string" + default "" + help + On some platforms, there is currently no way for the boot loader to + pass arguments to the kernel. For these platforms, you can supply + some command-line options at build time by entering them here. In + other cases you can specify kernel args so that you don't have + to set them up in board prom initialization routines. + +config DEBUG_STACK_USAGE + bool "Enable stack utilization instrumentation" + depends on DEBUG_KERNEL + help + Enables the display of the minimum amount of free stack which each + task has ever had available in the sysrq-T and sysrq-P debug output. + + This option will slow down process creation somewhat. + +config RUNTIME_DEBUG + bool "Enable run-time debugging" + depends on DEBUG_KERNEL + help + If you say Y here, some debugging macros will do run-time checking. + If you say N here, those macros will mostly turn to no-ops. See + include/asm-score/debug.h for debuging macros. + If unsure, say N. + +endmenu diff --git a/arch/score/Makefile b/arch/score/Makefile new file mode 100644 index 000000000000..68e0cd06d5c9 --- /dev/null +++ b/arch/score/Makefile @@ -0,0 +1,43 @@ +# +# arch/score/Makefile +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# + +KBUILD_DEFCONFIG := spct6600_defconfig +CROSS_COMPILE := score-linux- + +# +# CPU-dependent compiler/assembler options for optimization. +# +cflags-y += -G0 -pipe -mel -mnhwloop -D__SCOREEL__ \ + -D__linux__ -ffunction-sections -ffreestanding + +# +# Board-dependent options and extra files +# +KBUILD_AFLAGS += $(cflags-y) +KBUILD_CFLAGS += $(cflags-y) +MODFLAGS += -mlong-calls +LDFLAGS += --oformat elf32-littlescore +LDFLAGS_vmlinux += -G0 -static -nostdlib + +head-y := arch/score/kernel/head.o +libs-y += arch/score/lib/ +core-y += arch/score/kernel/ arch/score/mm/ + +boot := arch/score/boot + +vmlinux.bin: vmlinux + $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ + +archclean: + @$(MAKE) $(clean)=$(boot) + +define archhelp + echo ' vmlinux.bin - Raw binary boot image' + echo + echo ' These will be default as apropriate for a configured platform.' +endef diff --git a/arch/score/boot/Makefile b/arch/score/boot/Makefile new file mode 100644 index 000000000000..0c5fbd0fb696 --- /dev/null +++ b/arch/score/boot/Makefile @@ -0,0 +1,15 @@ +# +# arch/score/boot/Makefile +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# + +targets := vmlinux.bin + +$(obj)/vmlinux.bin: vmlinux FORCE + $(call if_changed,objcopy) + @echo 'Kernel: $@ is ready' ' (#'`cat .version`')' + +clean-files += vmlinux.bin diff --git a/arch/score/configs/spct6600_defconfig b/arch/score/configs/spct6600_defconfig new file mode 100644 index 000000000000..e064943b13d4 --- /dev/null +++ b/arch/score/configs/spct6600_defconfig @@ -0,0 +1,717 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc5 +# Fri Jun 12 18:57:07 2009 +# + +# +# Machine selection +# +# CONFIG_ARCH_SCORE7 is not set +CONFIG_MACH_SPCT6600=y +# CONFIG_SCORE_SIM is not set +CONFIG_CPU_SCORE7=y +CONFIG_GENERIC_IOMAP=y +CONFIG_NO_DMA=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_GENERIC_SYSCALL_TABLE=y +CONFIG_SCORE_L1_CACHE_SHIFT=4 + +# +# Kernel type +# +CONFIG_32BIT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_MEMORY_START=0xa0000000 +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=12 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_PROBE_INITRD_HEADER is not set +CONFIG_MMU=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=y +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +CONFIG_ARPD=y +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +CONFIG_STALDRV=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFSD=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_CMDLINE="" + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_SECURITY_FILE_CAPABILITIES=y +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=y +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_NLATTR=y diff --git a/arch/score/include/asm/Kbuild b/arch/score/include/asm/Kbuild new file mode 100644 index 000000000000..b367abd4620f --- /dev/null +++ b/arch/score/include/asm/Kbuild @@ -0,0 +1,3 @@ +include include/asm-generic/Kbuild.asm + +header-y += diff --git a/arch/score/include/asm/asmmacro.h b/arch/score/include/asm/asmmacro.h new file mode 100644 index 000000000000..a04a54cea25d --- /dev/null +++ b/arch/score/include/asm/asmmacro.h @@ -0,0 +1,161 @@ +#ifndef _ASM_SCORE_ASMMACRO_H +#define _ASM_SCORE_ASMMACRO_H + +#include <asm/asm-offsets.h> + +#ifdef __ASSEMBLY__ + +.macro SAVE_ALL + mfcr r30, cr0 + mv r31, r0 + nop + /* if UMs == 1, change stack. */ + slli.c r30, r30, 28 + bpl 1f + la r31, kernelsp + lw r31, [r31] +1: + mv r30, r0 + addri r0, r31, -PT_SIZE + + sw r30, [r0, PT_R0] + .set r1 + sw r1, [r0, PT_R1] + .set nor1 + sw r2, [r0, PT_R2] + sw r3, [r0, PT_R3] + sw r4, [r0, PT_R4] + sw r5, [r0, PT_R5] + sw r6, [r0, PT_R6] + sw r7, [r0, PT_R7] + + sw r8, [r0, PT_R8] + sw r9, [r0, PT_R9] + sw r10, [r0, PT_R10] + sw r11, [r0, PT_R11] + sw r12, [r0, PT_R12] + sw r13, [r0, PT_R13] + sw r14, [r0, PT_R14] + sw r15, [r0, PT_R15] + + sw r16, [r0, PT_R16] + sw r17, [r0, PT_R17] + sw r18, [r0, PT_R18] + sw r19, [r0, PT_R19] + sw r20, [r0, PT_R20] + sw r21, [r0, PT_R21] + sw r22, [r0, PT_R22] + sw r23, [r0, PT_R23] + + sw r24, [r0, PT_R24] + sw r25, [r0, PT_R25] + sw r25, [r0, PT_R25] + sw r26, [r0, PT_R26] + sw r27, [r0, PT_R27] + + sw r28, [r0, PT_R28] + sw r29, [r0, PT_R29] + orri r28, r0, 0x1fff + li r31, 0x00001fff + xor r28, r28, r31 + + mfcehl r30, r31 + sw r30, [r0, PT_CEH] + sw r31, [r0, PT_CEL] + + mfcr r31, cr0 + sw r31, [r0, PT_PSR] + + mfcr r31, cr1 + sw r31, [r0, PT_CONDITION] + + mfcr r31, cr2 + sw r31, [r0, PT_ECR] + + mfcr r31, cr5 + srli r31, r31, 1 + slli r31, r31, 1 + sw r31, [r0, PT_EPC] +.endm + +.macro RESTORE_ALL_AND_RET + mfcr r30, cr0 + srli r30, r30, 1 + slli r30, r30, 1 + mtcr r30, cr0 + nop + nop + nop + nop + nop + + .set r1 + ldis r1, 0x00ff + and r30, r30, r1 + not r1, r1 + lw r31, [r0, PT_PSR] + and r31, r31, r1 + .set nor1 + or r31, r31, r30 + mtcr r31, cr0 + nop + nop + nop + nop + nop + + lw r30, [r0, PT_CONDITION] + mtcr r30, cr1 + nop + nop + nop + nop + nop + + lw r30, [r0, PT_CEH] + lw r31, [r0, PT_CEL] + mtcehl r30, r31 + + .set r1 + lw r1, [r0, PT_R1] + .set nor1 + lw r2, [r0, PT_R2] + lw r3, [r0, PT_R3] + lw r4, [r0, PT_R4] + lw r5, [r0, PT_R5] + lw r6, [r0, PT_R6] + lw r7, [r0, PT_R7] + + lw r8, [r0, PT_R8] + lw r9, [r0, PT_R9] + lw r10, [r0, PT_R10] + lw r11, [r0, PT_R11] + lw r12, [r0, PT_R12] + lw r13, [r0, PT_R13] + lw r14, [r0, PT_R14] + lw r15, [r0, PT_R15] + + lw r16, [r0, PT_R16] + lw r17, [r0, PT_R17] + lw r18, [r0, PT_R18] + lw r19, [r0, PT_R19] + lw r20, [r0, PT_R20] + lw r21, [r0, PT_R21] + lw r22, [r0, PT_R22] + lw r23, [r0, PT_R23] + + lw r24, [r0, PT_R24] + lw r25, [r0, PT_R25] + lw r26, [r0, PT_R26] + lw r27, [r0, PT_R27] + lw r28, [r0, PT_R28] + lw r29, [r0, PT_R29] + + lw r30, [r0, PT_EPC] + lw r0, [r0, PT_R0] + mtcr r30, cr5 + rte +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* _ASM_SCORE_ASMMACRO_H */ diff --git a/arch/score/include/asm/atomic.h b/arch/score/include/asm/atomic.h new file mode 100644 index 000000000000..84eb8ddf9f3f --- /dev/null +++ b/arch/score/include/asm/atomic.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_ATOMIC_H +#define _ASM_SCORE_ATOMIC_H + +#include <asm-generic/atomic.h> + +#endif /* _ASM_SCORE_ATOMIC_H */ diff --git a/arch/score/include/asm/auxvec.h b/arch/score/include/asm/auxvec.h new file mode 100644 index 000000000000..f69151565aee --- /dev/null +++ b/arch/score/include/asm/auxvec.h @@ -0,0 +1,4 @@ +#ifndef _ASM_SCORE_AUXVEC_H +#define _ASM_SCORE_AUXVEC_H + +#endif /* _ASM_SCORE_AUXVEC_H */ diff --git a/arch/score/include/asm/bitops.h b/arch/score/include/asm/bitops.h new file mode 100644 index 000000000000..2763b050fca8 --- /dev/null +++ b/arch/score/include/asm/bitops.h @@ -0,0 +1,16 @@ +#ifndef _ASM_SCORE_BITOPS_H +#define _ASM_SCORE_BITOPS_H + +#include <asm/byteorder.h> /* swab32 */ +#include <asm/system.h> /* save_flags */ + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +#include <asm-generic/bitops.h> +#include <asm-generic/bitops/__fls.h> + +#endif /* _ASM_SCORE_BITOPS_H */ diff --git a/arch/score/include/asm/bitsperlong.h b/arch/score/include/asm/bitsperlong.h new file mode 100644 index 000000000000..86ff337aa459 --- /dev/null +++ b/arch/score/include/asm/bitsperlong.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_BITSPERLONG_H +#define _ASM_SCORE_BITSPERLONG_H + +#include <asm-generic/bitsperlong.h> + +#endif /* _ASM_SCORE_BITSPERLONG_H */ diff --git a/arch/score/include/asm/bug.h b/arch/score/include/asm/bug.h new file mode 100644 index 000000000000..bb76a330bcf1 --- /dev/null +++ b/arch/score/include/asm/bug.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_BUG_H +#define _ASM_SCORE_BUG_H + +#include <asm-generic/bug.h> + +#endif /* _ASM_SCORE_BUG_H */ diff --git a/arch/score/include/asm/bugs.h b/arch/score/include/asm/bugs.h new file mode 100644 index 000000000000..a062e1056bb3 --- /dev/null +++ b/arch/score/include/asm/bugs.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_BUGS_H +#define _ASM_SCORE_BUGS_H + +#include <asm-generic/bugs.h> + +#endif /* _ASM_SCORE_BUGS_H */ diff --git a/arch/score/include/asm/byteorder.h b/arch/score/include/asm/byteorder.h new file mode 100644 index 000000000000..88cbebc79212 --- /dev/null +++ b/arch/score/include/asm/byteorder.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_BYTEORDER_H +#define _ASM_SCORE_BYTEORDER_H + +#include <linux/byteorder/little_endian.h> + +#endif /* _ASM_SCORE_BYTEORDER_H */ diff --git a/arch/score/include/asm/cache.h b/arch/score/include/asm/cache.h new file mode 100644 index 000000000000..ae3d59f2d2c4 --- /dev/null +++ b/arch/score/include/asm/cache.h @@ -0,0 +1,7 @@ +#ifndef _ASM_SCORE_CACHE_H +#define _ASM_SCORE_CACHE_H + +#define L1_CACHE_SHIFT 4 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#endif /* _ASM_SCORE_CACHE_H */ diff --git a/arch/score/include/asm/cacheflush.h b/arch/score/include/asm/cacheflush.h new file mode 100644 index 000000000000..07cc8fc457cd --- /dev/null +++ b/arch/score/include/asm/cacheflush.h @@ -0,0 +1,45 @@ +#ifndef _ASM_SCORE_CACHEFLUSH_H +#define _ASM_SCORE_CACHEFLUSH_H + +/* Keep includes the same across arches. */ +#include <linux/mm.h> + +extern void flush_cache_all(void); +extern void flush_cache_mm(struct mm_struct *mm); +extern void flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end); +extern void flush_cache_page(struct vm_area_struct *vma, + unsigned long page, unsigned long pfn); +extern void flush_cache_sigtramp(unsigned long addr); +extern void flush_icache_all(void); +extern void flush_icache_range(unsigned long start, unsigned long end); +extern void flush_dcache_range(unsigned long start, unsigned long end); + +#define flush_cache_dup_mm(mm) do {} while (0) +#define flush_dcache_page(page) do {} while (0) +#define flush_dcache_mmap_lock(mapping) do {} while (0) +#define flush_dcache_mmap_unlock(mapping) do {} while (0) +#define flush_cache_vmap(start, end) do {} while (0) +#define flush_cache_vunmap(start, end) do {} while (0) + +static inline void flush_icache_page(struct vm_area_struct *vma, + struct page *page) +{ + if (vma->vm_flags & VM_EXEC) { + void *v = page_address(page); + flush_icache_range((unsigned long) v, + (unsigned long) v + PAGE_SIZE); + } +} + +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) + +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ + do { \ + memcpy(dst, src, len); \ + if ((vma->vm_flags & VM_EXEC)) \ + flush_cache_page(vma, vaddr, page_to_pfn(page));\ + } while (0) + +#endif /* _ASM_SCORE_CACHEFLUSH_H */ diff --git a/arch/score/include/asm/checksum.h b/arch/score/include/asm/checksum.h new file mode 100644 index 000000000000..f909ac3144a4 --- /dev/null +++ b/arch/score/include/asm/checksum.h @@ -0,0 +1,235 @@ +#ifndef _ASM_SCORE_CHECKSUM_H +#define _ASM_SCORE_CHECKSUM_H + +#include <linux/in6.h> +#include <asm/uaccess.h> + +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +unsigned int csum_partial(const void *buff, int len, __wsum sum); +unsigned int csum_partial_copy_from_user(const char *src, char *dst, int len, + unsigned int sum, int *csum_err); +unsigned int csum_partial_copy(const char *src, char *dst, + int len, unsigned int sum); + +/* + * this is a new version of the above that records errors it finds in *errp, + * but continues and zeros the rest of the buffer. + */ + +/* + * Copy and checksum to user + */ +#define HAVE_CSUM_COPY_USER +static inline +__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len, + __wsum sum, int *err_ptr) +{ + sum = csum_partial(src, len, sum); + if (copy_to_user(dst, src, len)) { + *err_ptr = -EFAULT; + return (__force __wsum) -1; /* invalid checksum */ + } + return sum; +} + + +#define csum_partial_copy_nocheck csum_partial_copy +/* + * Fold a partial checksum without adding pseudo headers + */ + +static inline __sum16 csum_fold(__wsum sum) +{ + /* the while loop is unnecessary really, it's always enough with two + iterations */ + __asm__ __volatile__( + ".set volatile\n\t" + ".set\tr1\n\t" + "slli\tr1,%0, 16\n\t" + "add\t%0,%0, r1\n\t" + "cmp.c\tr1, %0\n\t" + "srli\t%0, %0, 16\n\t" + "bleu\t1f\n\t" + "addi\t%0, 0x1\n\t" + "1:ldi\tr30, 0xffff\n\t" + "xor\t%0, %0, r30\n\t" + "slli\t%0, %0, 16\n\t" + "srli\t%0, %0, 16\n\t" + ".set\tnor1\n\t" + ".set optimize\n\t" + : "=r" (sum) + : "0" (sum)); + return sum; +} + +/* + * This is a version of ip_compute_csum() optimized for IP headers, + * which always checksum on 4 octet boundaries. + * + * By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by + * Arnt Gulbrandsen. + */ +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) +{ + unsigned int sum; + unsigned long dummy; + + __asm__ __volatile__( + ".set volatile\n\t" + ".set\tnor1\n\t" + "lw\t%0, [%1]\n\t" + "subri\t%2, %2, 4\n\t" + "slli\t%2, %2, 2\n\t" + "lw\t%3, [%1, 4]\n\t" + "add\t%2, %2, %1\n\t" + "add\t%0, %0, %3\n\t" + "cmp.c\t%3, %0\n\t" + "lw\t%3, [%1, 8]\n\t" + "bleu\t1f\n\t" + "addi\t%0, 0x1\n\t" + "1:\n\t" + "add\t%0, %0, %3\n\t" + "cmp.c\t%3, %0\n\t" + "lw\t%3, [%1, 12]\n\t" + "bleu\t1f\n\t" + "addi\t%0, 0x1\n\t" + "1:add\t%0, %0, %3\n\t" + "cmp.c\t%3, %0\n\t" + "bleu\t1f\n\t" + "addi\t%0, 0x1\n" + + "1:\tlw\t%3, [%1, 16]\n\t" + "addi\t%1, 4\n\t" + "add\t%0, %0, %3\n\t" + "cmp.c\t%3, %0\n\t" + "bleu\t2f\n\t" + "addi\t%0, 0x1\n" + "2:cmp.c\t%2, %1\n\t" + "bne\t1b\n\t" + + ".set\tr1\n\t" + ".set optimize\n\t" + : "=&r" (sum), "=&r" (iph), "=&r" (ihl), "=&r" (dummy) + : "1" (iph), "2" (ihl)); + + return csum_fold(sum); +} + +static inline __wsum +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + unsigned long tmp = (ntohs(len) << 16) + proto * 256; + __asm__ __volatile__( + ".set volatile\n\t" + "add\t%0, %0, %2\n\t" + "cmp.c\t%2, %0\n\t" + "bleu\t1f\n\t" + "addi\t%0, 0x1\n\t" + "1:\n\t" + "add\t%0, %0, %3\n\t" + "cmp.c\t%3, %0\n\t" + "bleu\t1f\n\t" + "addi\t%0, 0x1\n\t" + "1:\n\t" + "add\t%0, %0, %4\n\t" + "cmp.c\t%4, %0\n\t" + "bleu\t1f\n\t" + "addi\t%0, 0x1\n\t" + "1:\n\t" + ".set optimize\n\t" + : "=r" (sum) + : "0" (daddr), "r"(saddr), + "r" (tmp), + "r" (sum)); + return sum; +} + +/* + * computes the checksum of the TCP/UDP pseudo-header + * returns a 16-bit checksum, already complemented + */ +static inline __sum16 +csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); +} + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ + +static inline unsigned short ip_compute_csum(const void *buff, int len) +{ + return csum_fold(csum_partial(buff, len, 0)); +} + +#define _HAVE_ARCH_IPV6_CSUM +static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr, + const struct in6_addr *daddr, + __u32 len, unsigned short proto, + __wsum sum) +{ + __asm__ __volatile__( + ".set\tnoreorder\t\t\t# csum_ipv6_magic\n\t" + ".set\tnoat\n\t" + "addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t" + "sltu\t$1, %0, %5\n\t" + "addu\t%0, $1\n\t" + "addu\t%0, %6\t\t\t# csum\n\t" + "sltu\t$1, %0, %6\n\t" + "lw\t%1, 0(%2)\t\t\t# four words source address\n\t" + "addu\t%0, $1\n\t" + "addu\t%0, %1\n\t" + "sltu\t$1, %0, %1\n\t" + "lw\t%1, 4(%2)\n\t" + "addu\t%0, $1\n\t" + "addu\t%0, %1\n\t" + "sltu\t$1, %0, %1\n\t" + "lw\t%1, 8(%2)\n\t" + "addu\t%0, $1\n\t" + "addu\t%0, %1\n\t" + "sltu\t$1, %0, %1\n\t" + "lw\t%1, 12(%2)\n\t" + "addu\t%0, $1\n\t" + "addu\t%0, %1\n\t" + "sltu\t$1, %0, %1\n\t" + "lw\t%1, 0(%3)\n\t" + "addu\t%0, $1\n\t" + "addu\t%0, %1\n\t" + "sltu\t$1, %0, %1\n\t" + "lw\t%1, 4(%3)\n\t" + "addu\t%0, $1\n\t" + "addu\t%0, %1\n\t" + "sltu\t$1, %0, %1\n\t" + "lw\t%1, 8(%3)\n\t" + "addu\t%0, $1\n\t" + "addu\t%0, %1\n\t" + "sltu\t$1, %0, %1\n\t" + "lw\t%1, 12(%3)\n\t" + "addu\t%0, $1\n\t" + "addu\t%0, %1\n\t" + "sltu\t$1, %0, %1\n\t" + "addu\t%0, $1\t\t\t# Add final carry\n\t" + ".set\tnoat\n\t" + ".set\tnoreorder" + : "=r" (sum), "=r" (proto) + : "r" (saddr), "r" (daddr), + "0" (htonl(len)), "1" (htonl(proto)), "r" (sum)); + + return csum_fold(sum); +} +#endif /* _ASM_SCORE_CHECKSUM_H */ diff --git a/arch/score/include/asm/cputime.h b/arch/score/include/asm/cputime.h new file mode 100644 index 000000000000..1fced99f0d67 --- /dev/null +++ b/arch/score/include/asm/cputime.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_CPUTIME_H +#define _ASM_SCORE_CPUTIME_H + +#include <asm-generic/cputime.h> + +#endif /* _ASM_SCORE_CPUTIME_H */ diff --git a/arch/score/include/asm/current.h b/arch/score/include/asm/current.h new file mode 100644 index 000000000000..16eae9cbaf1a --- /dev/null +++ b/arch/score/include/asm/current.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_CURRENT_H +#define _ASM_SCORE_CURRENT_H + +#include <asm-generic/current.h> + +#endif /* _ASM_SCORE_CURRENT_H */ diff --git a/arch/score/include/asm/delay.h b/arch/score/include/asm/delay.h new file mode 100644 index 000000000000..6726ec199dc0 --- /dev/null +++ b/arch/score/include/asm/delay.h @@ -0,0 +1,26 @@ +#ifndef _ASM_SCORE_DELAY_H +#define _ASM_SCORE_DELAY_H + +static inline void __delay(unsigned long loops) +{ + /* 3 cycles per loop. */ + __asm__ __volatile__ ( + "1:\tsubi\t%0, 3\n\t" + "cmpz.c\t%0\n\t" + "ble\t1b\n\t" + : "=r" (loops) + : "0" (loops)); +} + +static inline void __udelay(unsigned long usecs) +{ + unsigned long loops_per_usec; + + loops_per_usec = (loops_per_jiffy * HZ) / 1000000; + + __delay(usecs * loops_per_usec); +} + +#define udelay(usecs) __udelay(usecs) + +#endif /* _ASM_SCORE_DELAY_H */ diff --git a/arch/score/include/asm/device.h b/arch/score/include/asm/device.h new file mode 100644 index 000000000000..2dc7cc5d5ef9 --- /dev/null +++ b/arch/score/include/asm/device.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_DEVICE_H +#define _ASM_SCORE_DEVICE_H + +#include <asm-generic/device.h> + +#endif /* _ASM_SCORE_DEVICE_H */ diff --git a/arch/score/include/asm/div64.h b/arch/score/include/asm/div64.h new file mode 100644 index 000000000000..75fae19824eb --- /dev/null +++ b/arch/score/include/asm/div64.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_DIV64_H +#define _ASM_SCORE_DIV64_H + +#include <asm-generic/div64.h> + +#endif /* _ASM_SCORE_DIV64_H */ diff --git a/arch/score/include/asm/dma-mapping.h b/arch/score/include/asm/dma-mapping.h new file mode 100644 index 000000000000..f9c0193c7a53 --- /dev/null +++ b/arch/score/include/asm/dma-mapping.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_DMA_MAPPING_H +#define _ASM_SCORE_DMA_MAPPING_H + +#include <asm-generic/dma-mapping-broken.h> + +#endif /* _ASM_SCORE_DMA_MAPPING_H */ diff --git a/arch/score/include/asm/dma.h b/arch/score/include/asm/dma.h new file mode 100644 index 000000000000..9f44185298bf --- /dev/null +++ b/arch/score/include/asm/dma.h @@ -0,0 +1,8 @@ +#ifndef _ASM_SCORE_DMA_H +#define _ASM_SCORE_DMA_H + +#include <asm/io.h> + +#define MAX_DMA_ADDRESS (0) + +#endif /* _ASM_SCORE_DMA_H */ diff --git a/arch/score/include/asm/elf.h b/arch/score/include/asm/elf.h new file mode 100644 index 000000000000..43526d9fda93 --- /dev/null +++ b/arch/score/include/asm/elf.h @@ -0,0 +1,103 @@ +#ifndef _ASM_SCORE_ELF_H +#define _ASM_SCORE_ELF_H + +#include <linux/ptrace.h> + +#define EM_SCORE7 135 + +/* Relocation types. */ +#define R_SCORE_NONE 0 +#define R_SCORE_HI16 1 +#define R_SCORE_LO16 2 +#define R_SCORE_BCMP 3 +#define R_SCORE_24 4 +#define R_SCORE_PC19 5 +#define R_SCORE16_11 6 +#define R_SCORE16_PC8 7 +#define R_SCORE_ABS32 8 +#define R_SCORE_ABS16 9 +#define R_SCORE_DUMMY2 10 +#define R_SCORE_GP15 11 +#define R_SCORE_GNU_VTINHERIT 12 +#define R_SCORE_GNU_VTENTRY 13 +#define R_SCORE_GOT15 14 +#define R_SCORE_GOT_LO16 15 +#define R_SCORE_CALL15 16 +#define R_SCORE_GPREL32 17 +#define R_SCORE_REL32 18 +#define R_SCORE_DUMMY_HI16 19 +#define R_SCORE_IMM30 20 +#define R_SCORE_IMM32 21 + +/* ELF register definitions */ +typedef unsigned long elf_greg_t; + +#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* Score does not have fp regs. */ +typedef double elf_fpreg_t; +typedef elf_fpreg_t elf_fpregset_t; + +#define elf_check_arch(x) ((x)->e_machine == EM_SCORE7) + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_SCORE7 + +#define SET_PERSONALITY(ex) \ +do { \ + set_personality(PER_LINUX); \ +} while (0) + +struct task_struct; +struct pt_regs; + +#define CORE_DUMP_USE_REGSET +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE PAGE_SIZE + +/* This yields a mask that user programs can use to figure out what + instruction set this cpu supports. This could be done in userspace, + but it's not easy, and we've already done it here. */ + +#define ELF_HWCAP (0) + +/* This yields a string that ld.so will use to load implementation + specific libraries for optimization. This is more specific in + intent than poking at uname or /proc/cpuinfo. + + For the moment, we have only optimizations for the Intel generations, + but that could change... */ + +#define ELF_PLATFORM (NULL) + +#define ELF_PLAT_INIT(_r, load_addr) \ +do { \ + _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0; \ + _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0; \ + _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0; \ + _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0; \ + _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0; \ + _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0; \ + _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0; \ + _r->regs[30] = _r->regs[31] = 0; \ +} while (0) + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#ifndef ELF_ET_DYN_BASE +#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) +#endif + +#endif /* _ASM_SCORE_ELF_H */ diff --git a/arch/score/include/asm/emergency-restart.h b/arch/score/include/asm/emergency-restart.h new file mode 100644 index 000000000000..ca31e9803a8a --- /dev/null +++ b/arch/score/include/asm/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_EMERGENCY_RESTART_H +#define _ASM_SCORE_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_SCORE_EMERGENCY_RESTART_H */ diff --git a/arch/score/include/asm/errno.h b/arch/score/include/asm/errno.h new file mode 100644 index 000000000000..29ff39d5ab47 --- /dev/null +++ b/arch/score/include/asm/errno.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_ERRNO_H +#define _ASM_SCORE_ERRNO_H + +#include <asm-generic/errno.h> + +#endif /* _ASM_SCORE_ERRNO_H */ diff --git a/arch/score/include/asm/fcntl.h b/arch/score/include/asm/fcntl.h new file mode 100644 index 000000000000..03968a3103a4 --- /dev/null +++ b/arch/score/include/asm/fcntl.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_FCNTL_H +#define _ASM_SCORE_FCNTL_H + +#include <asm-generic/fcntl.h> + +#endif /* _ASM_SCORE_FCNTL_H */ diff --git a/arch/score/include/asm/fixmap.h b/arch/score/include/asm/fixmap.h new file mode 100644 index 000000000000..ee1676694024 --- /dev/null +++ b/arch/score/include/asm/fixmap.h @@ -0,0 +1,82 @@ +#ifndef _ASM_SCORE_FIXMAP_H +#define _ASM_SCORE_FIXMAP_H + +#include <asm/page.h> + +#define PHY_RAM_BASE 0x00000000 +#define PHY_IO_BASE 0x10000000 + +#define VIRTUAL_RAM_BASE 0xa0000000 +#define VIRTUAL_IO_BASE 0xb0000000 + +#define RAM_SPACE_SIZE 0x10000000 +#define IO_SPACE_SIZE 0x10000000 + +/* Kernel unmapped, cached 512MB */ +#define KSEG1 0xa0000000 + +/* + * Here we define all the compile-time 'special' virtual + * addresses. The point is to have a constant address at + * compile time, but to set the physical address only + * in the boot process. We allocate these special addresses + * from the end of virtual memory (0xfffff000) backwards. + * Also this lets us do fail-safe vmalloc(), we + * can guarantee that these special addresses and + * vmalloc()-ed addresses never overlap. + * + * these 'compile-time allocated' memory buffers are + * fixed-size 4k pages. (or larger if used with an increment + * highger than 1) use fixmap_set(idx,phys) to associate + * physical memory with fixmap indices. + * + * TLB entries of such buffers will not be flushed across + * task switches. + */ + +/* + * on UP currently we will have no trace of the fixmap mechanizm, + * no page table allocations, etc. This might change in the + * future, say framebuffers for the console driver(s) could be + * fix-mapped? + */ +enum fixed_addresses { +#define FIX_N_COLOURS 8 + FIX_CMAP_BEGIN, + FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS, + __end_of_fixed_addresses +}; + +/* + * used by vmalloc.c. + * + * Leave one empty page between vmalloc'ed areas and + * the start of the fixmap, and leave one page empty + * at the top of mem.. + */ +#define FIXADDR_TOP ((unsigned long)(long)(int)0xfefe0000) +#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) +#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) + +#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT)) +#define __virt_to_fix(x) \ + ((FIXADDR_TOP - ((x) & PAGE_MASK)) >> PAGE_SHIFT) + +extern void __this_fixmap_does_not_exist(void); + +/* + * 'index to address' translation. If anyone tries to use the idx + * directly without tranlation, we catch the bug with a NULL-deference + * kernel oops. Illegal ranges of incoming indices are caught too. + */ +static inline unsigned long fix_to_virt(const unsigned int idx) +{ + return __fix_to_virt(idx); +} + +static inline unsigned long virt_to_fix(const unsigned long vaddr) +{ + return __virt_to_fix(vaddr); +} + +#endif /* _ASM_SCORE_FIXMAP_H */ diff --git a/arch/score/include/asm/ftrace.h b/arch/score/include/asm/ftrace.h new file mode 100644 index 000000000000..79d6f10e1f5b --- /dev/null +++ b/arch/score/include/asm/ftrace.h @@ -0,0 +1,4 @@ +#ifndef _ASM_SCORE_FTRACE_H +#define _ASM_SCORE_FTRACE_H + +#endif /* _ASM_SCORE_FTRACE_H */ diff --git a/arch/score/include/asm/futex.h b/arch/score/include/asm/futex.h new file mode 100644 index 000000000000..1dca2420f8db --- /dev/null +++ b/arch/score/include/asm/futex.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_FUTEX_H +#define _ASM_SCORE_FUTEX_H + +#include <asm-generic/futex.h> + +#endif /* _ASM_SCORE_FUTEX_H */ diff --git a/arch/score/include/asm/hardirq.h b/arch/score/include/asm/hardirq.h new file mode 100644 index 000000000000..dc932c50d3ee --- /dev/null +++ b/arch/score/include/asm/hardirq.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_HARDIRQ_H +#define _ASM_SCORE_HARDIRQ_H + +#include <asm-generic/hardirq.h> + +#endif /* _ASM_SCORE_HARDIRQ_H */ diff --git a/arch/score/include/asm/hw_irq.h b/arch/score/include/asm/hw_irq.h new file mode 100644 index 000000000000..4caafb2b509a --- /dev/null +++ b/arch/score/include/asm/hw_irq.h @@ -0,0 +1,4 @@ +#ifndef _ASM_SCORE_HW_IRQ_H +#define _ASM_SCORE_HW_IRQ_H + +#endif /* _ASM_SCORE_HW_IRQ_H */ diff --git a/arch/score/include/asm/io.h b/arch/score/include/asm/io.h new file mode 100644 index 000000000000..fbbfd7132e3b --- /dev/null +++ b/arch/score/include/asm/io.h @@ -0,0 +1,9 @@ +#ifndef _ASM_SCORE_IO_H +#define _ASM_SCORE_IO_H + +#include <asm-generic/io.h> + +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +#endif /* _ASM_SCORE_IO_H */ diff --git a/arch/score/include/asm/ioctl.h b/arch/score/include/asm/ioctl.h new file mode 100644 index 000000000000..a351d2194bfd --- /dev/null +++ b/arch/score/include/asm/ioctl.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_IOCTL_H +#define _ASM_SCORE_IOCTL_H + +#include <asm-generic/ioctl.h> + +#endif /* _ASM_SCORE_IOCTL_H */ diff --git a/arch/score/include/asm/ioctls.h b/arch/score/include/asm/ioctls.h new file mode 100644 index 000000000000..ed01d2b9aeab --- /dev/null +++ b/arch/score/include/asm/ioctls.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_IOCTLS_H +#define _ASM_SCORE_IOCTLS_H + +#include <asm-generic/ioctls.h> + +#endif /* _ASM_SCORE_IOCTLS_H */ diff --git a/arch/score/include/asm/ipcbuf.h b/arch/score/include/asm/ipcbuf.h new file mode 100644 index 000000000000..e082ceff1818 --- /dev/null +++ b/arch/score/include/asm/ipcbuf.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_IPCBUF_H +#define _ASM_SCORE_IPCBUF_H + +#include <asm-generic/ipcbuf.h> + +#endif /* _ASM_SCORE_IPCBUF_H */ diff --git a/arch/score/include/asm/irq.h b/arch/score/include/asm/irq.h new file mode 100644 index 000000000000..c883f3df33fa --- /dev/null +++ b/arch/score/include/asm/irq.h @@ -0,0 +1,25 @@ +#ifndef _ASM_SCORE_IRQ_H +#define _ASM_SCORE_IRQ_H + +#define EXCEPTION_VECTOR_BASE_ADDR 0xa0000000 +#define VECTOR_ADDRESS_OFFSET_MODE4 0 +#define VECTOR_ADDRESS_OFFSET_MODE16 1 + +#define DEBUG_VECTOR_SIZE (0x4) +#define DEBUG_VECTOR_BASE_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x1fc) + +#define GENERAL_VECTOR_SIZE (0x10) +#define GENERAL_VECTOR_BASE_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x200) + +#define NR_IRQS 64 +#define IRQ_VECTOR_SIZE (0x10) +#define IRQ_VECTOR_BASE_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x210) +#define IRQ_VECTOR_END_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x5f0) + +#define irq_canonicalize(irq) (irq) + +#define IRQ_TIMER (7) /* Timer IRQ number of SPCT6600 */ + +extern void interrupt_exception_vector(void); + +#endif /* _ASM_SCORE_IRQ_H */ diff --git a/arch/score/include/asm/irq_regs.h b/arch/score/include/asm/irq_regs.h new file mode 100644 index 000000000000..b8e881c9a69f --- /dev/null +++ b/arch/score/include/asm/irq_regs.h @@ -0,0 +1,11 @@ +#ifndef _ASM_SCORE_IRQ_REGS_H +#define _ASM_SCORE_IRQ_REGS_H + +#include <linux/thread_info.h> + +static inline struct pt_regs *get_irq_regs(void) +{ + return current_thread_info()->regs; +} + +#endif /* _ASM_SCORE_IRQ_REGS_H */ diff --git a/arch/score/include/asm/irqflags.h b/arch/score/include/asm/irqflags.h new file mode 100644 index 000000000000..690a6cae7294 --- /dev/null +++ b/arch/score/include/asm/irqflags.h @@ -0,0 +1,109 @@ +#ifndef _ASM_SCORE_IRQFLAGS_H +#define _ASM_SCORE_IRQFLAGS_H + +#ifndef __ASSEMBLY__ + +#define raw_local_irq_save(x) \ +{ \ + __asm__ __volatile__( \ + "mfcr r8, cr0;" \ + "li r9, 0xfffffffe;" \ + "nop;" \ + "mv %0, r8;" \ + "and r8, r8, r9;" \ + "mtcr r8, cr0;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + : "=r" (x) \ + : \ + : "r8", "r9" \ + ); \ +} + +#define raw_local_irq_restore(x) \ +{ \ + __asm__ __volatile__( \ + "mfcr r8, cr0;" \ + "ldi r9, 0x1;" \ + "and %0, %0, r9;" \ + "or r8, r8, %0;" \ + "mtcr r8, cr0;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + : \ + : "r"(x) \ + : "r8", "r9" \ + ); \ +} + +#define raw_local_irq_enable(void) \ +{ \ + __asm__ __volatile__( \ + "mfcr\tr8,cr0;" \ + "nop;" \ + "nop;" \ + "ori\tr8,0x1;" \ + "mtcr\tr8,cr0;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + : \ + : \ + : "r8"); \ +} + +#define raw_local_irq_disable(void) \ +{ \ + __asm__ __volatile__( \ + "mfcr\tr8,cr0;" \ + "nop;" \ + "nop;" \ + "srli\tr8,r8,1;" \ + "slli\tr8,r8,1;" \ + "mtcr\tr8,cr0;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + : \ + : \ + : "r8"); \ +} + +#define raw_local_save_flags(x) \ +{ \ + __asm__ __volatile__( \ + "mfcr r8, cr0;" \ + "nop;" \ + "nop;" \ + "mv %0, r8;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "ldi r9, 0x1;" \ + "and %0, %0, r9;" \ + : "=r" (x) \ + : \ + : "r8", "r9" \ + ); \ +} + +static inline int raw_irqs_disabled_flags(unsigned long flags) +{ + return !(flags & 1); +} + +#endif + +#endif /* _ASM_SCORE_IRQFLAGS_H */ diff --git a/arch/score/include/asm/kdebug.h b/arch/score/include/asm/kdebug.h new file mode 100644 index 000000000000..a666e513f747 --- /dev/null +++ b/arch/score/include/asm/kdebug.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_KDEBUG_H +#define _ASM_SCORE_KDEBUG_H + +#include <asm-generic/kdebug.h> + +#endif /* _ASM_SCORE_KDEBUG_H */ diff --git a/arch/score/include/asm/kmap_types.h b/arch/score/include/asm/kmap_types.h new file mode 100644 index 000000000000..6c46eb5077d3 --- /dev/null +++ b/arch/score/include/asm/kmap_types.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_KMAP_TYPES_H +#define _ASM_SCORE_KMAP_TYPES_H + +#include <asm-generic/kmap_types.h> + +#endif /* _ASM_SCORE_KMAP_TYPES_H */ diff --git a/arch/score/include/asm/linkage.h b/arch/score/include/asm/linkage.h new file mode 100644 index 000000000000..2323a8ecf445 --- /dev/null +++ b/arch/score/include/asm/linkage.h @@ -0,0 +1,7 @@ +#ifndef _ASM_SCORE_LINKAGE_H +#define _ASM_SCORE_LINKAGE_H + +#define __ALIGN .align 2 +#define __ALIGN_STR ".align 2" + +#endif /* _ASM_SCORE_LINKAGE_H */ diff --git a/arch/score/include/asm/local.h b/arch/score/include/asm/local.h new file mode 100644 index 000000000000..7e02f13dbba8 --- /dev/null +++ b/arch/score/include/asm/local.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_LOCAL_H +#define _ASM_SCORE_LOCAL_H + +#include <asm-generic/local.h> + +#endif /* _ASM_SCORE_LOCAL_H */ diff --git a/arch/score/include/asm/mman.h b/arch/score/include/asm/mman.h new file mode 100644 index 000000000000..84d85ddfed8d --- /dev/null +++ b/arch/score/include/asm/mman.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_MMAN_H +#define _ASM_SCORE_MMAN_H + +#include <asm-generic/mman.h> + +#endif /* _ASM_SCORE_MMAN_H */ diff --git a/arch/score/include/asm/mmu.h b/arch/score/include/asm/mmu.h new file mode 100644 index 000000000000..676828e4c10a --- /dev/null +++ b/arch/score/include/asm/mmu.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_MMU_H +#define _ASM_SCORE_MMU_H + +typedef unsigned long mm_context_t; + +#endif /* _ASM_SCORE_MMU_H */ diff --git a/arch/score/include/asm/mmu_context.h b/arch/score/include/asm/mmu_context.h new file mode 100644 index 000000000000..2644577c96e8 --- /dev/null +++ b/arch/score/include/asm/mmu_context.h @@ -0,0 +1,113 @@ +#ifndef _ASM_SCORE_MMU_CONTEXT_H +#define _ASM_SCORE_MMU_CONTEXT_H + +#include <linux/errno.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <asm-generic/mm_hooks.h> + +#include <asm/cacheflush.h> +#include <asm/tlbflush.h> +#include <asm/scoreregs.h> + +/* + * For the fast tlb miss handlers, we keep a per cpu array of pointers + * to the current pgd for each processor. Also, the proc. id is stuffed + * into the context register. + */ +extern unsigned long asid_cache; +extern unsigned long pgd_current; + +#define TLBMISS_HANDLER_SETUP_PGD(pgd) (pgd_current = (unsigned long)(pgd)) + +#define TLBMISS_HANDLER_SETUP() \ +do { \ + write_c0_context(0); \ + TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) \ +} while (0) + +/* + * All unused by hardware upper bits will be considered + * as a software asid extension. + */ +#define ASID_VERSION_MASK 0xfffff000 +#define ASID_FIRST_VERSION 0x1000 + +/* PEVN --------- VPN ---------- --ASID--- -NA- */ +/* binary: 0000 0000 0000 0000 0000 0000 0001 0000 */ +/* binary: 0000 0000 0000 0000 0000 1111 1111 0000 */ +#define ASID_INC 0x10 +#define ASID_MASK 0xff0 + +static inline void enter_lazy_tlb(struct mm_struct *mm, + struct task_struct *tsk) +{} + +static inline void +get_new_mmu_context(struct mm_struct *mm) +{ + unsigned long asid = asid_cache + ASID_INC; + + if (!(asid & ASID_MASK)) { + local_flush_tlb_all(); /* start new asid cycle */ + if (!asid) /* fix version if needed */ + asid = ASID_FIRST_VERSION; + } + + mm->context = asid; + asid_cache = asid; +} + +/* + * Initialize the context related info for a new mm_struct + * instance. + */ +static inline int +init_new_context(struct task_struct *tsk, struct mm_struct *mm) +{ + mm->context = 0; + return 0; +} + +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + unsigned long flags; + + local_irq_save(flags); + if ((next->context ^ asid_cache) & ASID_VERSION_MASK) + get_new_mmu_context(next); + + pevn_set(next->context); + TLBMISS_HANDLER_SETUP_PGD(next->pgd); + local_irq_restore(flags); +} + +/* + * Destroy context related info for an mm_struct that is about + * to be put to rest. + */ +static inline void destroy_context(struct mm_struct *mm) +{} + +static inline void +deactivate_mm(struct task_struct *task, struct mm_struct *mm) +{} + +/* + * After we have set current->mm to a new value, this activates + * the context for the new mm so we see the new mappings. + */ +static inline void +activate_mm(struct mm_struct *prev, struct mm_struct *next) +{ + unsigned long flags; + + local_irq_save(flags); + get_new_mmu_context(next); + pevn_set(next->context); + TLBMISS_HANDLER_SETUP_PGD(next->pgd); + local_irq_restore(flags); +} + +#endif /* _ASM_SCORE_MMU_CONTEXT_H */ diff --git a/arch/score/include/asm/module.h b/arch/score/include/asm/module.h new file mode 100644 index 000000000000..f0b5dc0bd023 --- /dev/null +++ b/arch/score/include/asm/module.h @@ -0,0 +1,39 @@ +#ifndef _ASM_SCORE_MODULE_H +#define _ASM_SCORE_MODULE_H + +#include <linux/list.h> +#include <asm/uaccess.h> + +struct mod_arch_specific { + /* Data Bus Error exception tables */ + struct list_head dbe_list; + const struct exception_table_entry *dbe_start; + const struct exception_table_entry *dbe_end; +}; + +typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ + +#define Elf_Shdr Elf32_Shdr +#define Elf_Sym Elf32_Sym +#define Elf_Ehdr Elf32_Ehdr +#define Elf_Addr Elf32_Addr + +/* Given an address, look for it in the exception tables. */ +#ifdef CONFIG_MODULES +const struct exception_table_entry *search_module_dbetables(unsigned long addr); +#else +static inline const struct exception_table_entry +*search_module_dbetables(unsigned long addr) +{ + return NULL; +} +#endif + +#define MODULE_PROC_FAMILY "SCORE7" +#define MODULE_KERNEL_TYPE "32BIT " +#define MODULE_KERNEL_SMTC "" + +#define MODULE_ARCH_VERMAGIC \ + MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC + +#endif /* _ASM_SCORE_MODULE_H */ diff --git a/arch/score/include/asm/msgbuf.h b/arch/score/include/asm/msgbuf.h new file mode 100644 index 000000000000..7506721e29fa --- /dev/null +++ b/arch/score/include/asm/msgbuf.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_MSGBUF_H +#define _ASM_SCORE_MSGBUF_H + +#include <asm-generic/msgbuf.h> + +#endif /* _ASM_SCORE_MSGBUF_H */ diff --git a/arch/score/include/asm/mutex.h b/arch/score/include/asm/mutex.h new file mode 100644 index 000000000000..10d48fe4db97 --- /dev/null +++ b/arch/score/include/asm/mutex.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_MUTEX_H +#define _ASM_SCORE_MUTEX_H + +#include <asm-generic/mutex-dec.h> + +#endif /* _ASM_SCORE_MUTEX_H */ diff --git a/arch/score/include/asm/page.h b/arch/score/include/asm/page.h new file mode 100644 index 000000000000..ee5821042fcc --- /dev/null +++ b/arch/score/include/asm/page.h @@ -0,0 +1,92 @@ +#ifndef _ASM_SCORE_PAGE_H +#define _ASM_SCORE_PAGE_H + +#include <linux/pfn.h> + +/* PAGE_SHIFT determines the page size */ +#define PAGE_SHIFT (12) +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ + +#define PAGE_UP(addr) (((addr)+((PAGE_SIZE)-1))&(~((PAGE_SIZE)-1))) +#define PAGE_DOWN(addr) ((addr)&(~((PAGE_SIZE)-1))) + +/* align addr on a size boundary - adjust address up/down if needed */ +#define _ALIGN_UP(addr, size) (((addr)+((size)-1))&(~((size)-1))) +#define _ALIGN_DOWN(addr, size) ((addr)&(~((size)-1))) + +/* align addr on a size boundary - adjust address up if needed */ +#define _ALIGN(addr, size) _ALIGN_UP(addr, size) + +/* + * PAGE_OFFSET -- the first address of the first page of memory. When not + * using MMU this corresponds to the first free page in physical memory (aligned + * on a page boundary). + */ +#define PAGE_OFFSET (0xA0000000UL) + +#define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE) +#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE) + +#define clear_user_page(pgaddr, vaddr, page) memset((pgaddr), 0, PAGE_SIZE) +#define copy_user_page(vto, vfrom, vaddr, topg) \ + memcpy((vto), (vfrom), PAGE_SIZE) + +/* + * These are used to make use of C type-checking.. + */ + +typedef struct { unsigned long pte; } pte_t; /* page table entry */ +typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */ +typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; + +#define pte_val(x) ((x).pte) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) }) +#define __pgd(x) ((pgd_t) { (x) }) +#define __pgprot(x) ((pgprot_t) { (x) }) + +extern unsigned long max_low_pfn; +extern unsigned long min_low_pfn; +extern unsigned long max_pfn; + +#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET) +#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) + +#define phys_to_pfn(phys) (PFN_DOWN(phys)) +#define pfn_to_phys(pfn) (PFN_PHYS(pfn)) + +#define virt_to_pfn(vaddr) (phys_to_pfn((__pa(vaddr)))) +#define pfn_to_virt(pfn) __va(pfn_to_phys((pfn))) + +#define virt_to_page(vaddr) (pfn_to_page(virt_to_pfn(vaddr))) +#define page_to_virt(page) (pfn_to_virt(page_to_pfn(page))) + +#define page_to_phys(page) (pfn_to_phys(page_to_pfn(page))) +#define page_to_bus(page) (page_to_phys(page)) +#define phys_to_page(paddr) (pfn_to_page(phys_to_pfn(paddr))) + +#define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_mapnr) + +#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) + +#endif /* __ASSEMBLY__ */ + +#define virt_addr_valid(vaddr) (pfn_valid(virt_to_pfn(vaddr))) + +#endif /* __KERNEL__ */ + +#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#include <asm-generic/memory_model.h> +#include <asm-generic/getorder.h> + +#endif /* _ASM_SCORE_PAGE_H */ diff --git a/arch/score/include/asm/param.h b/arch/score/include/asm/param.h new file mode 100644 index 000000000000..916b8690b6aa --- /dev/null +++ b/arch/score/include/asm/param.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_PARAM_H +#define _ASM_SCORE_PARAM_H + +#include <asm-generic/param.h> + +#endif /* _ASM_SCORE_PARAM_H */ diff --git a/arch/score/include/asm/pci.h b/arch/score/include/asm/pci.h new file mode 100644 index 000000000000..3f3cfd82549c --- /dev/null +++ b/arch/score/include/asm/pci.h @@ -0,0 +1,4 @@ +#ifndef _ASM_SCORE_PCI_H +#define _ASM_SCORE_PCI_H + +#endif /* _ASM_SCORE_PCI_H */ diff --git a/arch/score/include/asm/percpu.h b/arch/score/include/asm/percpu.h new file mode 100644 index 000000000000..e7bd4e05b475 --- /dev/null +++ b/arch/score/include/asm/percpu.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_PERCPU_H +#define _ASM_SCORE_PERCPU_H + +#include <asm-generic/percpu.h> + +#endif /* _ASM_SCORE_PERCPU_H */ diff --git a/arch/score/include/asm/pgalloc.h b/arch/score/include/asm/pgalloc.h new file mode 100644 index 000000000000..059a61b7071b --- /dev/null +++ b/arch/score/include/asm/pgalloc.h @@ -0,0 +1,83 @@ +#ifndef _ASM_SCORE_PGALLOC_H +#define _ASM_SCORE_PGALLOC_H + +#include <linux/mm.h> + +static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, + pte_t *pte) +{ + set_pmd(pmd, __pmd((unsigned long)pte)); +} + +static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, + pgtable_t pte) +{ + set_pmd(pmd, __pmd((unsigned long)page_address(pte))); +} + +#define pmd_pgtable(pmd) pmd_page(pmd) + +static inline pgd_t *pgd_alloc(struct mm_struct *mm) +{ + pgd_t *ret, *init; + + ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER); + if (ret) { + init = pgd_offset(&init_mm, 0UL); + pgd_init((unsigned long)ret); + memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, + (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); + } + + return ret; +} + +static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) +{ + free_pages((unsigned long)pgd, PGD_ORDER); +} + +static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, + unsigned long address) +{ + pte_t *pte; + + pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, + PTE_ORDER); + + return pte; +} + +static inline struct page *pte_alloc_one(struct mm_struct *mm, + unsigned long address) +{ + struct page *pte; + + pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER); + if (pte) { + clear_highpage(pte); + pgtable_page_ctor(pte); + } + return pte; +} + +static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) +{ + free_pages((unsigned long)pte, PTE_ORDER); +} + +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) +{ + pgtable_page_dtor(pte); + __free_pages(pte, PTE_ORDER); +} + +#define __pte_free_tlb(tlb, pte, buf) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb), pte); \ +} while (0) + +#define check_pgt_cache() do {} while (0) + +#endif /* _ASM_SCORE_PGALLOC_H */ diff --git a/arch/score/include/asm/pgtable-bits.h b/arch/score/include/asm/pgtable-bits.h new file mode 100644 index 000000000000..7d65a96a82e5 --- /dev/null +++ b/arch/score/include/asm/pgtable-bits.h @@ -0,0 +1,25 @@ +#ifndef _ASM_SCORE_PGTABLE_BITS_H +#define _ASM_SCORE_PGTABLE_BITS_H + +#define _PAGE_ACCESSED (1<<5) /* implemented in software */ +#define _PAGE_READ (1<<6) /* implemented in software */ +#define _PAGE_WRITE (1<<7) /* implemented in software */ +#define _PAGE_PRESENT (1<<9) /* implemented in software */ +#define _PAGE_MODIFIED (1<<10) /* implemented in software */ +#define _PAGE_FILE (1<<10) + +#define _PAGE_GLOBAL (1<<0) +#define _PAGE_VALID (1<<1) +#define _PAGE_SILENT_READ (1<<1) /* synonym */ +#define _PAGE_DIRTY (1<<2) /* Write bit */ +#define _PAGE_SILENT_WRITE (1<<2) +#define _PAGE_CACHE (1<<3) /* cache */ +#define _CACHE_MASK (1<<3) +#define _PAGE_BUFFERABLE (1<<4) /*Fallow Spec. */ + +#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) +#define _PAGE_CHG_MASK \ + (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_CACHE) + +#endif /* _ASM_SCORE_PGTABLE_BITS_H */ diff --git a/arch/score/include/asm/pgtable.h b/arch/score/include/asm/pgtable.h new file mode 100644 index 000000000000..674934b40170 --- /dev/null +++ b/arch/score/include/asm/pgtable.h @@ -0,0 +1,287 @@ +#ifndef _ASM_SCORE_PGTABLE_H +#define _ASM_SCORE_PGTABLE_H + +#include <linux/const.h> +#include <asm-generic/pgtable-nopmd.h> + +#include <asm/fixmap.h> +#include <asm/setup.h> +#include <asm/pgtable-bits.h> + +extern void load_pgd(unsigned long pg_dir); +extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; + +/* PGDIR_SHIFT determines what a third-level page table entry can map */ +#define PGDIR_SHIFT 22 +#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE - 1)) + +/* + * Entries per page directory level: we use two-level, so + * we don't really have any PUD/PMD directory physically. + */ +#define PGD_ORDER 0 +#define PTE_ORDER 0 + +#define PTRS_PER_PGD 1024 +#define PTRS_PER_PTE 1024 + +#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) +#define FIRST_USER_ADDRESS 0 + +#define VMALLOC_START (0xc0000000UL) + +#define PKMAP_BASE (0xfd000000UL) + +#define VMALLOC_END (FIXADDR_START - 2*PAGE_SIZE) + +#define pte_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \ + __FILE__, __LINE__, pte_val(e)) +#define pgd_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ + __FILE__, __LINE__, pgd_val(e)) + +/* + * Empty pgd/pmd entries point to the invalid_pte_table. + */ +static inline int pmd_none(pmd_t pmd) +{ + return pmd_val(pmd) == (unsigned long) invalid_pte_table; +} + +#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) + +static inline int pmd_present(pmd_t pmd) +{ + return pmd_val(pmd) != (unsigned long) invalid_pte_table; +} + +static inline void pmd_clear(pmd_t *pmdp) +{ + pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); +} + +#define pte_page(x) pfn_to_page(pte_pfn(x)) +#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) +#define pfn_pte(pfn, prot) \ + __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) + +#define __pgd_offset(address) pgd_index(address) +#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) +#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) + +/* to find an entry in a kernel page-table-directory */ +#define pgd_offset_k(address) pgd_offset(&init_mm, address) +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) + +/* to find an entry in a page-table-directory */ +#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) + +/* Find an entry in the third-level page table.. */ +#define __pte_offset(address) \ + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_offset(dir, address) \ + ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) +#define pte_offset_kernel(dir, address) \ + ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) + +#define pte_offset_map(dir, address) \ + ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) +#define pte_offset_map_nested(dir, address) \ + ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) +#define pte_unmap(pte) ((void)(pte)) +#define pte_unmap_nested(pte) ((void)(pte)) + +/* + * Bits 9(_PAGE_PRESENT) and 10(_PAGE_FILE)are taken, + * split up 30 bits of offset into this range: + */ +#define PTE_FILE_MAX_BITS 30 +#define pte_to_pgoff(_pte) \ + (((_pte).pte & 0x1ff) | (((_pte).pte >> 11) << 9)) +#define pgoff_to_pte(off) \ + ((pte_t) {((off) & 0x1ff) | (((off) >> 9) << 11) | _PAGE_FILE}) +#define __pte_to_swp_entry(pte) \ + ((swp_entry_t) { pte_val(pte)}) +#define __swp_entry_to_pte(x) ((pte_t) {(x).val}) + +#define pmd_phys(pmd) __pa((void *)pmd_val(pmd)) +#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) +#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) +static inline pte_t pte_mkspecial(pte_t pte) { return pte; } + +#define set_pte(pteptr, pteval) (*(pteptr) = pteval) +#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) +#define pte_clear(mm, addr, xp) \ + do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) + +#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ + remap_pfn_range(vma, vaddr, pfn, size, prot) + +/* + * The "pgd_xxx()" functions here are trivial for a folded two-level + * setup: the pgd is never bad, and a pmd always exists (as it's folded + * into the pgd entry) + */ +#define pgd_present(pgd) (1) +#define pgd_none(pgd) (0) +#define pgd_bad(pgd) (0) +#define pgd_clear(pgdp) do { } while (0) + +#define kern_addr_valid(addr) (1) +#define pmd_page_vaddr(pmd) pmd_val(pmd) + +#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) +#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) + +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_CACHE) +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ + _PAGE_CACHE) +#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHE) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHE) +#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ + _PAGE_GLOBAL | _PAGE_CACHE) +#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ + __WRITEABLE | _PAGE_GLOBAL & ~_PAGE_CACHE) + +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY +#define __P101 PAGE_READONLY +#define __P110 PAGE_COPY +#define __P111 PAGE_COPY + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY +#define __S101 PAGE_READONLY +#define __S110 PAGE_SHARED +#define __S111 PAGE_SHARED + +#define pgprot_noncached pgprot_noncached + +static inline pgprot_t pgprot_noncached(pgprot_t _prot) +{ + unsigned long prot = pgprot_val(_prot); + + prot = (prot & ~_CACHE_MASK); + + return __pgprot(prot); +} + +#define __swp_type(x) ((x).val & 0x1f) +#define __swp_offset(x) ((x).val >> 11) +#define __swp_entry(type, offset) ((swp_entry_t){(type) | ((offset) << 11)}) + +extern unsigned long empty_zero_page; +extern unsigned long zero_page_mask; + +#define ZERO_PAGE(vaddr) \ + (virt_to_page((void *)(empty_zero_page + \ + (((unsigned long)(vaddr)) & zero_page_mask)))) + +#define pgtable_cache_init() do {} while (0) + +#define arch_enter_lazy_cpu_mode() do {} while (0) + +static inline int pte_write(pte_t pte) +{ + return pte_val(pte) & _PAGE_WRITE; +} + +static inline int pte_dirty(pte_t pte) +{ + return pte_val(pte) & _PAGE_MODIFIED; +} + +static inline int pte_young(pte_t pte) +{ + return pte_val(pte) & _PAGE_ACCESSED; +} + +static inline int pte_file(pte_t pte) +{ + return pte_val(pte) & _PAGE_FILE; +} + +#define pte_special(pte) (0) + +static inline pte_t pte_wrprotect(pte_t pte) +{ + pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); + return pte; +} + +static inline pte_t pte_mkclean(pte_t pte) +{ + pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); + return pte; +} + +static inline pte_t pte_mkold(pte_t pte) +{ + pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ); + return pte; +} + +static inline pte_t pte_mkwrite(pte_t pte) +{ + pte_val(pte) |= _PAGE_WRITE; + if (pte_val(pte) & _PAGE_MODIFIED) + pte_val(pte) |= _PAGE_SILENT_WRITE; + return pte; +} + +static inline pte_t pte_mkdirty(pte_t pte) +{ + pte_val(pte) |= _PAGE_MODIFIED; + if (pte_val(pte) & _PAGE_WRITE) + pte_val(pte) |= _PAGE_SILENT_WRITE; + return pte; +} + +static inline pte_t pte_mkyoung(pte_t pte) +{ + pte_val(pte) |= _PAGE_ACCESSED; + if (pte_val(pte) & _PAGE_READ) + pte_val(pte) |= _PAGE_SILENT_READ; + return pte; +} + +#define set_pmd(pmdptr, pmdval) \ + do { *(pmdptr) = (pmdval); } while (0) +#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) + +extern unsigned long pgd_current; +extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; +extern void paging_init(void); + +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ + return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); +} + +extern void __update_tlb(struct vm_area_struct *vma, + unsigned long address, pte_t pte); +extern void __update_cache(struct vm_area_struct *vma, + unsigned long address, pte_t pte); + +static inline void update_mmu_cache(struct vm_area_struct *vma, + unsigned long address, pte_t pte) +{ + __update_tlb(vma, address, pte); + __update_cache(vma, address, pte); +} + +#ifndef __ASSEMBLY__ +#include <asm-generic/pgtable.h> + +void setup_memory(void); +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_SCORE_PGTABLE_H */ diff --git a/arch/score/include/asm/poll.h b/arch/score/include/asm/poll.h new file mode 100644 index 000000000000..18532db02861 --- /dev/null +++ b/arch/score/include/asm/poll.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_POLL_H +#define _ASM_SCORE_POLL_H + +#include <asm-generic/poll.h> + +#endif /* _ASM_SCORE_POLL_H */ diff --git a/arch/score/include/asm/posix_types.h b/arch/score/include/asm/posix_types.h new file mode 100644 index 000000000000..b88acf80048a --- /dev/null +++ b/arch/score/include/asm/posix_types.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_POSIX_TYPES_H +#define _ASM_SCORE_POSIX_TYPES_H + +#include <asm-generic/posix_types.h> + +#endif /* _ASM_SCORE_POSIX_TYPES_H */ diff --git a/arch/score/include/asm/processor.h b/arch/score/include/asm/processor.h new file mode 100644 index 000000000000..7e22f216d771 --- /dev/null +++ b/arch/score/include/asm/processor.h @@ -0,0 +1,106 @@ +#ifndef _ASM_SCORE_PROCESSOR_H +#define _ASM_SCORE_PROCESSOR_H + +#include <linux/cpumask.h> +#include <linux/threads.h> + +#include <asm/segment.h> + +struct task_struct; + +/* + * System setup and hardware flags.. + */ +extern void (*cpu_wait)(void); + +extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); +extern unsigned long thread_saved_pc(struct task_struct *tsk); +extern void start_thread(struct pt_regs *regs, + unsigned long pc, unsigned long sp); +extern unsigned long get_wchan(struct task_struct *p); + +/* + * Return current * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l; }) + +#define cpu_relax() barrier() +#define release_thread(thread) do {} while (0) +#define prepare_to_copy(tsk) do {} while (0) + +/* + * User space process size: 2GB. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. + */ +#define TASK_SIZE 0x7fff8000UL + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE ((TASK_SIZE / 3) & ~(PAGE_SIZE)) + +#ifdef __KERNEL__ +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX TASK_SIZE +#endif + +/* + * If you change thread_struct remember to change the #defines below too! + */ +struct thread_struct { + unsigned long reg0, reg2, reg3; + unsigned long reg12, reg13, reg14, reg15, reg16; + unsigned long reg17, reg18, reg19, reg20, reg21; + + unsigned long cp0_psr; + unsigned long cp0_ema; /* Last user fault */ + unsigned long cp0_badvaddr; /* Last user fault */ + unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ + unsigned long error_code; + unsigned long trap_no; + + unsigned long mflags; + unsigned long reg29; + + unsigned long single_step; + unsigned long ss_nextcnt; + + unsigned long insn1_type; + unsigned long addr1; + unsigned long insn1; + + unsigned long insn2_type; + unsigned long addr2; + unsigned long insn2; + + mm_segment_t current_ds; +}; + +#define INIT_THREAD { \ + .reg0 = 0, \ + .reg2 = 0, \ + .reg3 = 0, \ + .reg12 = 0, \ + .reg13 = 0, \ + .reg14 = 0, \ + .reg15 = 0, \ + .reg16 = 0, \ + .reg17 = 0, \ + .reg18 = 0, \ + .reg19 = 0, \ + .reg20 = 0, \ + .reg21 = 0, \ + .cp0_psr = 0, \ + .error_code = 0, \ + .trap_no = 0, \ +} + +#define kstk_tos(tsk) \ + ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32) +#define task_pt_regs(tsk) ((struct pt_regs *)kstk_tos(tsk) - 1) + +#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc) +#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) + +#endif /* _ASM_SCORE_PROCESSOR_H */ diff --git a/arch/score/include/asm/ptrace.h b/arch/score/include/asm/ptrace.h new file mode 100644 index 000000000000..d40e691f23e2 --- /dev/null +++ b/arch/score/include/asm/ptrace.h @@ -0,0 +1,97 @@ +#ifndef _ASM_SCORE_PTRACE_H +#define _ASM_SCORE_PTRACE_H + +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 + +#define PC 32 +#define CONDITION 33 +#define ECR 34 +#define EMA 35 +#define CEH 36 +#define CEL 37 +#define COUNTER 38 +#define LDCR 39 +#define STCR 40 +#define PSR 41 + +#define SINGLESTEP16_INSN 0x7006 +#define SINGLESTEP32_INSN 0x840C8000 +#define BREAKPOINT16_INSN 0x7002 /* work on SPG300 */ +#define BREAKPOINT32_INSN 0x84048000 /* work on SPG300 */ + +/* Define instruction mask */ +#define INSN32_MASK 0x80008000 + +#define J32 0x88008000 /* 1_00010_0000000000_1_000000000000000 */ +#define J32M 0xFC008000 /* 1_11111_0000000000_1_000000000000000 */ + +#define B32 0x90008000 /* 1_00100_0000000000_1_000000000000000 */ +#define B32M 0xFC008000 +#define BL32 0x90008001 /* 1_00100_0000000000_1_000000000000001 */ +#define BL32M B32 +#define BR32 0x80008008 /* 1_00000_0000000000_1_00000000_000100_0 */ +#define BR32M 0xFFE0807E +#define BRL32 0x80008009 /* 1_00000_0000000000_1_00000000_000100_1 */ +#define BRL32M BR32M + +#define B32_SET (J32 | B32 | BL32 | BR32 | BRL32) + +#define J16 0x3000 /* 0_011_....... */ +#define J16M 0xF000 +#define B16 0x4000 /* 0_100_....... */ +#define B16M 0xF000 +#define BR16 0x0004 /* 0_000.......0100 */ +#define BR16M 0xF00F +#define B16_SET (J16 | B16 | BR16) + + +/* + * This struct defines the way the registers are stored on the stack during a + * system call/exception. As usual the registers k0/k1 aren't being saved. + */ +struct pt_regs { + unsigned long pad0[6]; /* stack arguments */ + unsigned long orig_r4; + unsigned long orig_r7; + long is_syscall; + + unsigned long regs[32]; + + unsigned long cel; + unsigned long ceh; + + unsigned long sr0; /* cnt */ + unsigned long sr1; /* lcr */ + unsigned long sr2; /* scr */ + + unsigned long cp0_epc; + unsigned long cp0_ema; + unsigned long cp0_psr; + unsigned long cp0_ecr; + unsigned long cp0_condition; +}; + +#ifdef __KERNEL__ + +struct task_struct; + +/* + * Does the process account for user or for system time? + */ +#define user_mode(regs) ((regs->cp0_psr & 8) == 8) + +#define instruction_pointer(regs) ((unsigned long)(regs)->cp0_epc) +#define profile_pc(regs) instruction_pointer(regs) + +extern void do_syscall_trace(struct pt_regs *regs, int entryexit); +extern int read_tsk_long(struct task_struct *, unsigned long, unsigned long *); +extern int read_tsk_short(struct task_struct *, unsigned long, + unsigned short *); + +#define arch_has_single_step() (1) +extern void user_enable_single_step(struct task_struct *); +extern void user_disable_single_step(struct task_struct *); +#endif /* __KERNEL__ */ + +#endif /* _ASM_SCORE_PTRACE_H */ diff --git a/arch/score/include/asm/resource.h b/arch/score/include/asm/resource.h new file mode 100644 index 000000000000..9ce22bc7b475 --- /dev/null +++ b/arch/score/include/asm/resource.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_RESOURCE_H +#define _ASM_SCORE_RESOURCE_H + +#include <asm-generic/resource.h> + +#endif /* _ASM_SCORE_RESOURCE_H */ diff --git a/arch/score/include/asm/scatterlist.h b/arch/score/include/asm/scatterlist.h new file mode 100644 index 000000000000..9f533b8362c7 --- /dev/null +++ b/arch/score/include/asm/scatterlist.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SCATTERLIST_H +#define _ASM_SCORE_SCATTERLIST_H + +#include <asm-generic/scatterlist.h> + +#endif /* _ASM_SCORE_SCATTERLIST_H */ diff --git a/arch/score/include/asm/scoreregs.h b/arch/score/include/asm/scoreregs.h new file mode 100644 index 000000000000..d0ad29204518 --- /dev/null +++ b/arch/score/include/asm/scoreregs.h @@ -0,0 +1,51 @@ +#ifndef _ASM_SCORE_SCOREREGS_H +#define _ASM_SCORE_SCOREREGS_H + +#include <linux/linkage.h> + +/* TIMER register */ +#define TIME0BASE 0x96080000 +#define P_TIMER0_CTRL (TIME0BASE + 0x00) +#define P_TIMER0_CPP_CTRL (TIME0BASE + 0x04) +#define P_TIMER0_PRELOAD (TIME0BASE + 0x08) +#define P_TIMER0_CPP_REG (TIME0BASE + 0x0C) +#define P_TIMER0_UPCNT (TIME0BASE + 0x10) + +/* Timer Controller Register */ +/* bit 0 Timer enable */ +#define TMR_DISABLE 0x0000 +#define TMR_ENABLE 0x0001 + +/* bit 1 Interrupt enable */ +#define TMR_IE_DISABLE 0x0000 +#define TMR_IE_ENABLE 0x0002 + +/* bit 2 Output enable */ +#define TMR_OE_DISABLE 0x0004 +#define TMR_OE_ENABLE 0x0000 + +/* bit4 Up/Down counting selection */ +#define TMR_UD_DOWN 0x0000 +#define TMR_UD_UP 0x0010 + +/* bit5 Up/Down counting control selection */ +#define TMR_UDS_UD 0x0000 +#define TMR_UDS_EXTUD 0x0020 + +/* bit6 Time output mode */ +#define TMR_OM_TOGGLE 0x0000 +#define TMR_OM_PILSE 0x0040 + +/* bit 8..9 External input active edge selection */ +#define TMR_ES_PE 0x0000 +#define TMR_ES_NE 0x0100 +#define TMR_ES_BOTH 0x0200 + +/* bit 10..11 Operating mode */ +#define TMR_M_FREE 0x0000 /* free running timer mode */ +#define TMR_M_PERIODIC 0x0400 /* periodic timer mode */ +#define TMR_M_FC 0x0800 /* free running counter mode */ +#define TMR_M_PC 0x0c00 /* periodic counter mode */ + +#define SYSTEM_CLOCK (27*1000000/4) /* 27 MHz */ +#endif /* _ASM_SCORE_SCOREREGS_H */ diff --git a/arch/score/include/asm/sections.h b/arch/score/include/asm/sections.h new file mode 100644 index 000000000000..9441d23af005 --- /dev/null +++ b/arch/score/include/asm/sections.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SECTIONS_H +#define _ASM_SCORE_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif /* _ASM_SCORE_SECTIONS_H */ diff --git a/arch/score/include/asm/segment.h b/arch/score/include/asm/segment.h new file mode 100644 index 000000000000..e16cf6afb495 --- /dev/null +++ b/arch/score/include/asm/segment.h @@ -0,0 +1,21 @@ +#ifndef _ASM_SCORE_SEGMENT_H +#define _ASM_SCORE_SEGMENT_H + +#ifndef __ASSEMBLY__ + +typedef struct { + unsigned long seg; +} mm_segment_t; + +#define KERNEL_DS ((mm_segment_t){0}) +#define USER_DS KERNEL_DS + +# define get_ds() (KERNEL_DS) +# define get_fs() (current_thread_info()->addr_limit) +# define set_fs(x) \ + do { current_thread_info()->addr_limit = (x); } while (0) + +# define segment_eq(a, b) ((a).seg == (b).seg) + +# endif /* __ASSEMBLY__ */ +#endif /* _ASM_SCORE_SEGMENT_H */ diff --git a/arch/score/include/asm/sembuf.h b/arch/score/include/asm/sembuf.h new file mode 100644 index 000000000000..dae5e835ce9e --- /dev/null +++ b/arch/score/include/asm/sembuf.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SEMBUF_H +#define _ASM_SCORE_SEMBUF_H + +#include <asm-generic/sembuf.h> + +#endif /* _ASM_SCORE_SEMBUF_H */ diff --git a/arch/score/include/asm/setup.h b/arch/score/include/asm/setup.h new file mode 100644 index 000000000000..3cb944dc68dc --- /dev/null +++ b/arch/score/include/asm/setup.h @@ -0,0 +1,41 @@ +#ifndef _ASM_SCORE_SETUP_H +#define _ASM_SCORE_SETUP_H + +#define COMMAND_LINE_SIZE 256 +#define MEMORY_START 0 +#define MEMORY_SIZE 0x2000000 + +#ifdef __KERNEL__ + +extern void pagetable_init(void); +extern void pgd_init(unsigned long page); + +extern void setup_early_printk(void); +extern void cpu_cache_init(void); +extern void tlb_init(void); + +extern void handle_nmi(void); +extern void handle_adelinsn(void); +extern void handle_adedata(void); +extern void handle_ibe(void); +extern void handle_pel(void); +extern void handle_sys(void); +extern void handle_ccu(void); +extern void handle_ri(void); +extern void handle_tr(void); +extern void handle_ades(void); +extern void handle_cee(void); +extern void handle_cpe(void); +extern void handle_dve(void); +extern void handle_dbe(void); +extern void handle_reserved(void); +extern void handle_tlb_refill(void); +extern void handle_tlb_invaild(void); +extern void handle_mod(void); +extern void debug_exception_vector(void); +extern void general_exception_vector(void); +extern void interrupt_exception_vector(void); + +#endif /* __KERNEL__ */ + +#endif /* _ASM_SCORE_SETUP_H */ diff --git a/arch/score/include/asm/shmbuf.h b/arch/score/include/asm/shmbuf.h new file mode 100644 index 000000000000..c85b2429ba21 --- /dev/null +++ b/arch/score/include/asm/shmbuf.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SHMBUF_H +#define _ASM_SCORE_SHMBUF_H + +#include <asm-generic/shmbuf.h> + +#endif /* _ASM_SCORE_SHMBUF_H */ diff --git a/arch/score/include/asm/shmparam.h b/arch/score/include/asm/shmparam.h new file mode 100644 index 000000000000..1d60813141b6 --- /dev/null +++ b/arch/score/include/asm/shmparam.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SHMPARAM_H +#define _ASM_SCORE_SHMPARAM_H + +#include <asm-generic/shmparam.h> + +#endif /* _ASM_SCORE_SHMPARAM_H */ diff --git a/arch/score/include/asm/sigcontext.h b/arch/score/include/asm/sigcontext.h new file mode 100644 index 000000000000..5ffda39ddb90 --- /dev/null +++ b/arch/score/include/asm/sigcontext.h @@ -0,0 +1,22 @@ +#ifndef _ASM_SCORE_SIGCONTEXT_H +#define _ASM_SCORE_SIGCONTEXT_H + +/* + * Keep this struct definition in sync with the sigcontext fragment + * in arch/score/tools/offset.c + */ +struct sigcontext { + unsigned int sc_regmask; + unsigned int sc_psr; + unsigned int sc_condition; + unsigned long sc_pc; + unsigned long sc_regs[32]; + unsigned int sc_ssflags; + unsigned int sc_mdceh; + unsigned int sc_mdcel; + unsigned int sc_ecr; + unsigned long sc_ema; + unsigned long sc_sigset[4]; +}; + +#endif /* _ASM_SCORE_SIGCONTEXT_H */ diff --git a/arch/score/include/asm/siginfo.h b/arch/score/include/asm/siginfo.h new file mode 100644 index 000000000000..87ca35607a28 --- /dev/null +++ b/arch/score/include/asm/siginfo.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SIGINFO_H +#define _ASM_SCORE_SIGINFO_H + +#include <asm-generic/siginfo.h> + +#endif /* _ASM_SCORE_SIGINFO_H */ diff --git a/arch/score/include/asm/signal.h b/arch/score/include/asm/signal.h new file mode 100644 index 000000000000..2605bc06b64f --- /dev/null +++ b/arch/score/include/asm/signal.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SIGNAL_H +#define _ASM_SCORE_SIGNAL_H + +#include <asm-generic/signal.h> + +#endif /* _ASM_SCORE_SIGNAL_H */ diff --git a/arch/score/include/asm/socket.h b/arch/score/include/asm/socket.h new file mode 100644 index 000000000000..612a70e385ba --- /dev/null +++ b/arch/score/include/asm/socket.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SOCKET_H +#define _ASM_SCORE_SOCKET_H + +#include <asm-generic/socket.h> + +#endif /* _ASM_SCORE_SOCKET_H */ diff --git a/arch/score/include/asm/sockios.h b/arch/score/include/asm/sockios.h new file mode 100644 index 000000000000..ba8256480189 --- /dev/null +++ b/arch/score/include/asm/sockios.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SOCKIOS_H +#define _ASM_SCORE_SOCKIOS_H + +#include <asm-generic/sockios.h> + +#endif /* _ASM_SCORE_SOCKIOS_H */ diff --git a/arch/score/include/asm/stat.h b/arch/score/include/asm/stat.h new file mode 100644 index 000000000000..5037055500a2 --- /dev/null +++ b/arch/score/include/asm/stat.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_STAT_H +#define _ASM_SCORE_STAT_H + +#include <asm-generic/stat.h> + +#endif /* _ASM_SCORE_STAT_H */ diff --git a/arch/score/include/asm/statfs.h b/arch/score/include/asm/statfs.h new file mode 100644 index 000000000000..36e41004e996 --- /dev/null +++ b/arch/score/include/asm/statfs.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_STATFS_H +#define _ASM_SCORE_STATFS_H + +#include <asm-generic/statfs.h> + +#endif /* _ASM_SCORE_STATFS_H */ diff --git a/arch/score/include/asm/string.h b/arch/score/include/asm/string.h new file mode 100644 index 000000000000..8a6bf5063aa5 --- /dev/null +++ b/arch/score/include/asm/string.h @@ -0,0 +1,8 @@ +#ifndef _ASM_SCORE_STRING_H +#define _ASM_SCORE_STRING_H + +extern void *memset(void *__s, int __c, size_t __count); +extern void *memcpy(void *__to, __const__ void *__from, size_t __n); +extern void *memmove(void *__dest, __const__ void *__src, size_t __n); + +#endif /* _ASM_SCORE_STRING_H */ diff --git a/arch/score/include/asm/swab.h b/arch/score/include/asm/swab.h new file mode 100644 index 000000000000..fadc3cc6d8a2 --- /dev/null +++ b/arch/score/include/asm/swab.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_SWAB_H +#define _ASM_SCORE_SWAB_H + +#include <asm-generic/swab.h> + +#endif /* _ASM_SCORE_SWAB_H */ diff --git a/arch/score/include/asm/syscalls.h b/arch/score/include/asm/syscalls.h new file mode 100644 index 000000000000..1dd5e0d6b0c3 --- /dev/null +++ b/arch/score/include/asm/syscalls.h @@ -0,0 +1,11 @@ +#ifndef _ASM_SCORE_SYSCALLS_H +#define _ASM_SCORE_SYSCALLS_H + +asmlinkage long score_clone(struct pt_regs *regs); +asmlinkage long score_execve(struct pt_regs *regs); +asmlinkage long score_sigaltstack(struct pt_regs *regs); +asmlinkage long score_rt_sigreturn(struct pt_regs *regs); + +#include <asm-generic/syscalls.h> + +#endif /* _ASM_SCORE_SYSCALLS_H */ diff --git a/arch/score/include/asm/system.h b/arch/score/include/asm/system.h new file mode 100644 index 000000000000..589d5c7e171c --- /dev/null +++ b/arch/score/include/asm/system.h @@ -0,0 +1,90 @@ +#ifndef _ASM_SCORE_SYSTEM_H +#define _ASM_SCORE_SYSTEM_H + +#include <linux/types.h> +#include <linux/irqflags.h> + +struct pt_regs; +struct task_struct; + +extern void *resume(void *last, void *next, void *next_ti); + +#define switch_to(prev, next, last) \ +do { \ + (last) = resume(prev, next, task_thread_info(next)); \ +} while (0) + +#define finish_arch_switch(prev) do {} while (0) + +typedef void (*vi_handler_t)(void); +extern unsigned long arch_align_stack(unsigned long sp); + +#define mb() barrier() +#define rmb() barrier() +#define wmb() barrier() +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() + +#define read_barrier_depends() do {} while (0) +#define smp_read_barrier_depends() do {} while (0) + +#define set_mb(var, value) do {var = value; wmb(); } while (0) + +#define __HAVE_ARCH_CMPXCHG 1 + +#include <asm-generic/cmpxchg-local.h> + +#ifndef __ASSEMBLY__ + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +static inline +unsigned long __xchg(volatile unsigned long *m, unsigned long val) +{ + unsigned long retval; + unsigned long flags; + + local_irq_save(flags); + retval = *m; + *m = val; + local_irq_restore(flags); + return retval; +} + +#define xchg(ptr, v) \ + ((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \ + (unsigned long)(v))) + +static inline unsigned long __cmpxchg(volatile unsigned long *m, + unsigned long old, unsigned long new) +{ + unsigned long retval; + unsigned long flags; + + local_irq_save(flags); + retval = *m; + if (retval == old) + *m = new; + local_irq_restore(flags); + return retval; +} + +#define cmpxchg(ptr, o, n) \ + ((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \ + (unsigned long)(o), \ + (unsigned long)(n))) + +extern void __die(const char *, struct pt_regs *, const char *, + const char *, unsigned long) __attribute__((noreturn)); +extern void __die_if_kernel(const char *, struct pt_regs *, const char *, + const char *, unsigned long); + +#define die(msg, regs) \ + __die(msg, regs, __FILE__ ":", __func__, __LINE__) +#define die_if_kernel(msg, regs) \ + __die_if_kernel(msg, regs, __FILE__ ":", __func__, __LINE__) + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASM_SCORE_SYSTEM_H */ diff --git a/arch/score/include/asm/termbits.h b/arch/score/include/asm/termbits.h new file mode 100644 index 000000000000..9a95c1412437 --- /dev/null +++ b/arch/score/include/asm/termbits.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_TERMBITS_H +#define _ASM_SCORE_TERMBITS_H + +#include <asm-generic/termbits.h> + +#endif /* _ASM_SCORE_TERMBITS_H */ diff --git a/arch/score/include/asm/termios.h b/arch/score/include/asm/termios.h new file mode 100644 index 000000000000..40984e811ad6 --- /dev/null +++ b/arch/score/include/asm/termios.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_TERMIOS_H +#define _ASM_SCORE_TERMIOS_H + +#include <asm-generic/termios.h> + +#endif /* _ASM_SCORE_TERMIOS_H */ diff --git a/arch/score/include/asm/thread_info.h b/arch/score/include/asm/thread_info.h new file mode 100644 index 000000000000..3a1122885528 --- /dev/null +++ b/arch/score/include/asm/thread_info.h @@ -0,0 +1,105 @@ +#ifndef _ASM_SCORE_THREAD_INFO_H +#define _ASM_SCORE_THREAD_INFO_H + +#ifdef __KERNEL__ + +#define KU_MASK 0x08 +#define KU_USER 0x08 +#define KU_KERN 0x00 + +#ifndef __ASSEMBLY__ + +#include <asm/processor.h> + +/* + * low level task data that entry.S needs immediate access to + * - this struct should fit entirely inside of one cache line + * - this struct shares the supervisor stack pages + * - if the contents of this structure are changed, the assembly constants + * must also be changed + */ +struct thread_info { + struct task_struct *task; /* main task structure */ + struct exec_domain *exec_domain; /* execution domain */ + unsigned long flags; /* low level flags */ + unsigned long tp_value; /* thread pointer */ + __u32 cpu; /* current CPU */ + + /* 0 => preemptable, < 0 => BUG */ + int preempt_count; + + /* + * thread address space: + * 0-0xBFFFFFFF for user-thead + * 0-0xFFFFFFFF for kernel-thread + */ + mm_segment_t addr_limit; + struct restart_block restart_block; + struct pt_regs *regs; +}; + +/* + * macros/functions for gaining access to the thread information structure + * + * preempt_count needs to be 1 initially, until the scheduler is functional. + */ +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .exec_domain = &default_exec_domain, \ + .cpu = 0, \ + .preempt_count = 1, \ + .addr_limit = KERNEL_DS, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ +} + +#define init_thread_info (init_thread_union.thread_info) +#define init_stack (init_thread_union.stack) + +/* How to get the thread information struct from C. */ +register struct thread_info *__current_thread_info __asm__("r28"); +#define current_thread_info() __current_thread_info + +/* thread information allocation */ +#define THREAD_SIZE_ORDER (1) +#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) +#define THREAD_MASK (THREAD_SIZE - 1UL) +#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR + +#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) +#define free_thread_info(info) kfree(info) + +#endif /* !__ASSEMBLY__ */ + +#define PREEMPT_ACTIVE 0x10000000 + +/* + * thread information flags + * - these are process state flags that various assembly files may need to + * access + * - pending work-to-be-done flags are in LSW + * - other flags in MSW + */ +#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */ +#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ +#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling + TIF_NEED_RESCHED */ +#define TIF_MEMDIE 18 + +#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) +#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) +#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) +#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) +#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) +#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) + +#define _TIF_WORK_MASK (0x0000ffff) + +#endif /* __KERNEL__ */ + +#endif /* _ASM_SCORE_THREAD_INFO_H */ diff --git a/arch/score/include/asm/timex.h b/arch/score/include/asm/timex.h new file mode 100644 index 000000000000..a524ae0c5e7b --- /dev/null +++ b/arch/score/include/asm/timex.h @@ -0,0 +1,8 @@ +#ifndef _ASM_SCORE_TIMEX_H +#define _ASM_SCORE_TIMEX_H + +#define CLOCK_TICK_RATE 27000000 /* Timer input freq. */ + +#include <asm-generic/timex.h> + +#endif /* _ASM_SCORE_TIMEX_H */ diff --git a/arch/score/include/asm/tlb.h b/arch/score/include/asm/tlb.h new file mode 100644 index 000000000000..46882ed524e6 --- /dev/null +++ b/arch/score/include/asm/tlb.h @@ -0,0 +1,17 @@ +#ifndef _ASM_SCORE_TLB_H +#define _ASM_SCORE_TLB_H + +/* + * SCORE doesn't need any special per-pte or per-vma handling, except + * we need to flush cache for area to be unmapped. + */ +#define tlb_start_vma(tlb, vma) do {} while (0) +#define tlb_end_vma(tlb, vma) do {} while (0) +#define __tlb_remove_tlb_entry(tlb, ptep, address) do {} while (0) +#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) + +extern void score7_FTLB_refill_Handler(void); + +#include <asm-generic/tlb.h> + +#endif /* _ASM_SCORE_TLB_H */ diff --git a/arch/score/include/asm/tlbflush.h b/arch/score/include/asm/tlbflush.h new file mode 100644 index 000000000000..9cce978367d5 --- /dev/null +++ b/arch/score/include/asm/tlbflush.h @@ -0,0 +1,142 @@ +#ifndef _ASM_SCORE_TLBFLUSH_H +#define _ASM_SCORE_TLBFLUSH_H + +#include <linux/mm.h> + +/* + * TLB flushing: + * + * - flush_tlb_all() flushes all processes TLB entries + * - flush_tlb_mm(mm) flushes the specified mm context TLB entries + * - flush_tlb_page(vma, vmaddr) flushes one page + * - flush_tlb_range(vma, start, end) flushes a range of pages + * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages + */ +extern void local_flush_tlb_all(void); +extern void local_flush_tlb_mm(struct mm_struct *mm); +extern void local_flush_tlb_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end); +extern void local_flush_tlb_kernel_range(unsigned long start, + unsigned long end); +extern void local_flush_tlb_page(struct vm_area_struct *vma, + unsigned long page); +extern void local_flush_tlb_one(unsigned long vaddr); + +#define flush_tlb_all() local_flush_tlb_all() +#define flush_tlb_mm(mm) local_flush_tlb_mm(mm) +#define flush_tlb_range(vma, vmaddr, end) \ + local_flush_tlb_range(vma, vmaddr, end) +#define flush_tlb_kernel_range(vmaddr, end) \ + local_flush_tlb_kernel_range(vmaddr, end) +#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page) +#define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr) + +#ifndef __ASSEMBLY__ + +static inline unsigned long pevn_get(void) +{ + unsigned long val; + + __asm__ __volatile__( + "mfcr %0, cr11\n" + "nop\nnop\n" + : "=r" (val)); + + return val; +} + +static inline void pevn_set(unsigned long val) +{ + __asm__ __volatile__( + "mtcr %0, cr11\n" + "nop\nnop\nnop\nnop\nnop\n" + : : "r" (val)); +} + +static inline void pectx_set(unsigned long val) +{ + __asm__ __volatile__( + "mtcr %0, cr12\n" + "nop\nnop\nnop\nnop\nnop\n" + : : "r" (val)); +} + +static inline unsigned long pectx_get(void) +{ + unsigned long val; + __asm__ __volatile__( + "mfcr %0, cr12\n" + "nop\nnop\n" + : "=r" (val)); + return val; +} +static inline unsigned long tlblock_get(void) +{ + unsigned long val; + + __asm__ __volatile__( + "mfcr %0, cr7\n" + "nop\nnop\n" + : "=r" (val)); + return val; +} +static inline void tlblock_set(unsigned long val) +{ + __asm__ __volatile__( + "mtcr %0, cr7\n" + "nop\nnop\nnop\nnop\nnop\n" + : : "r" (val)); +} + +static inline void tlbpt_set(unsigned long val) +{ + __asm__ __volatile__( + "mtcr %0, cr8\n" + "nop\nnop\nnop\nnop\nnop\n" + : : "r" (val)); +} + +static inline long tlbpt_get(void) +{ + long val; + + __asm__ __volatile__( + "mfcr %0, cr8\n" + "nop\nnop\n" + : "=r" (val)); + + return val; +} + +static inline void peaddr_set(unsigned long val) +{ + __asm__ __volatile__( + "mtcr %0, cr9\n" + "nop\nnop\nnop\nnop\nnop\n" + : : "r" (val)); +} + +/* TLB operations. */ +static inline void tlb_probe(void) +{ + __asm__ __volatile__("stlb;nop;nop;nop;nop;nop"); +} + +static inline void tlb_read(void) +{ + __asm__ __volatile__("mftlb;nop;nop;nop;nop;nop"); +} + +static inline void tlb_write_indexed(void) +{ + __asm__ __volatile__("mtptlb;nop;nop;nop;nop;nop"); +} + +static inline void tlb_write_random(void) +{ + __asm__ __volatile__("mtrtlb;nop;nop;nop;nop;nop"); +} + +#endif /* Not __ASSEMBLY__ */ + +#endif /* _ASM_SCORE_TLBFLUSH_H */ diff --git a/arch/score/include/asm/topology.h b/arch/score/include/asm/topology.h new file mode 100644 index 000000000000..425fba381f88 --- /dev/null +++ b/arch/score/include/asm/topology.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_TOPOLOGY_H +#define _ASM_SCORE_TOPOLOGY_H + +#include <asm-generic/topology.h> + +#endif /* _ASM_SCORE_TOPOLOGY_H */ diff --git a/arch/score/include/asm/types.h b/arch/score/include/asm/types.h new file mode 100644 index 000000000000..2140032778ee --- /dev/null +++ b/arch/score/include/asm/types.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_TYPES_H +#define _ASM_SCORE_TYPES_H + +#include <asm-generic/types.h> + +#endif /* _ASM_SCORE_TYPES_H */ diff --git a/arch/score/include/asm/uaccess.h b/arch/score/include/asm/uaccess.h new file mode 100644 index 000000000000..ab66ddde777b --- /dev/null +++ b/arch/score/include/asm/uaccess.h @@ -0,0 +1,424 @@ +#ifndef __SCORE_UACCESS_H +#define __SCORE_UACCESS_H + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/thread_info.h> + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +#define get_ds() (KERNEL_DS) +#define get_fs() (current_thread_info()->addr_limit) +#define segment_eq(a, b) ((a).seg == (b).seg) + +/* + * Is a address valid? This does a straighforward calculation rather + * than tests. + * + * Address valid if: + * - "addr" doesn't have any high-bits set + * - AND "size" doesn't have any high-bits set + * - AND "addr+size" doesn't have any high-bits set + * - OR we are in kernel mode. + * + * __ua_size() is a trick to avoid runtime checking of positive constant + * sizes; for those we already know at compile time that the size is ok. + */ +#define __ua_size(size) \ + ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size)) + +/* + * access_ok: - Checks if a user space pointer is valid + * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that + * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe + * to write to a block, it is always safe to read from it. + * @addr: User space pointer to start of block to check + * @size: Size of block to check + * + * Context: User context only. This function may sleep. + * + * Checks if a pointer to a block of memory in user space is valid. + * + * Returns true (nonzero) if the memory block may be valid, false (zero) + * if it is definitely invalid. + * + * Note that, depending on architecture, this function probably just + * checks that the pointer is in the user space range - after calling + * this function, memory access functions may still return -EFAULT. + */ + +#define __access_ok(addr, size) \ + (((long)((get_fs().seg) & \ + ((addr) | ((addr) + (size)) | \ + __ua_size(size)))) == 0) + +#define access_ok(type, addr, size) \ + likely(__access_ok((unsigned long)(addr), (size))) + +/* + * put_user: - Write a simple value into user space. + * @x: Value to copy to user space. + * @ptr: Destination address, in user space. + * + * Context: User context only. This function may sleep. + * + * This macro copies a single simple value from kernel space to user + * space. It supports simple types like char and int, but not larger + * data types like structures or arrays. + * + * @ptr must have pointer-to-simple-variable type, and @x must be assignable + * to the result of dereferencing @ptr. + * + * Returns zero on success, or -EFAULT on error. + */ +#define put_user(x, ptr) __put_user_check((x), (ptr), sizeof(*(ptr))) + +/* + * get_user: - Get a simple variable from user space. + * @x: Variable to store result. + * @ptr: Source address, in user space. + * + * Context: User context only. This function may sleep. + * + * This macro copies a single simple variable from user space to kernel + * space. It supports simple types like char and int, but not larger + * data types like structures or arrays. + * + * @ptr must have pointer-to-simple-variable type, and the result of + * dereferencing @ptr must be assignable to @x without a cast. + * + * Returns zero on success, or -EFAULT on error. + * On error, the variable @x is set to zero. + */ +#define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr))) + +/* + * __put_user: - Write a simple value into user space, with less checking. + * @x: Value to copy to user space. + * @ptr: Destination address, in user space. + * + * Context: User context only. This function may sleep. + * + * This macro copies a single simple value from kernel space to user + * space. It supports simple types like char and int, but not larger + * data types like structures or arrays. + * + * @ptr must have pointer-to-simple-variable type, and @x must be assignable + * to the result of dereferencing @ptr. + * + * Caller must check the pointer with access_ok() before calling this + * function. + * + * Returns zero on success, or -EFAULT on error. + */ +#define __put_user(x, ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr))) + +/* + * __get_user: - Get a simple variable from user space, with less checking. + * @x: Variable to store result. + * @ptr: Source address, in user space. + * + * Context: User context only. This function may sleep. + * + * This macro copies a single simple variable from user space to kernel + * space. It supports simple types like char and int, but not larger + * data types like structures or arrays. + * + * @ptr must have pointer-to-simple-variable type, and the result of + * dereferencing @ptr must be assignable to @x without a cast. + * + * Caller must check the pointer with access_ok() before calling this + * function. + * + * Returns zero on success, or -EFAULT on error. + * On error, the variable @x is set to zero. + */ +#define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr))) + +struct __large_struct { unsigned long buf[100]; }; +#define __m(x) (*(struct __large_struct __user *)(x)) + +/* + * Yuck. We need two variants, one for 64bit operation and one + * for 32 bit mode and old iron. + */ +extern void __get_user_unknown(void); + +#define __get_user_common(val, size, ptr) \ +do { \ + switch (size) { \ + case 1: \ + __get_user_asm(val, "lb", ptr); \ + break; \ + case 2: \ + __get_user_asm(val, "lh", ptr); \ + break; \ + case 4: \ + __get_user_asm(val, "lw", ptr); \ + break; \ + case 8: \ + if ((copy_from_user((void *)&val, ptr, 8)) == 0) \ + __gu_err = 0; \ + else \ + __gu_err = -EFAULT; \ + break; \ + default: \ + __get_user_unknown(); \ + break; \ + } \ +} while (0) + +#define __get_user_nocheck(x, ptr, size) \ +({ \ + long __gu_err = 0; \ + __get_user_common((x), size, ptr); \ + __gu_err; \ +}) + +#define __get_user_check(x, ptr, size) \ +({ \ + long __gu_err = -EFAULT; \ + const __typeof__(*(ptr)) __user *__gu_ptr = (ptr); \ + \ + if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ + __get_user_common((x), size, __gu_ptr); \ + \ + __gu_err; \ +}) + +#define __get_user_asm(val, insn, addr) \ +{ \ + long __gu_tmp; \ + \ + __asm__ __volatile__( \ + "1:" insn " %1, %3\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3:li %0, %4\n" \ + "j 2b\n" \ + ".previous\n" \ + ".section __ex_table,\"a\"\n" \ + ".word 1b, 3b\n" \ + ".previous\n" \ + : "=r" (__gu_err), "=r" (__gu_tmp) \ + : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \ + \ + (val) = (__typeof__(*(addr))) __gu_tmp; \ +} + +/* + * Yuck. We need two variants, one for 64bit operation and one + * for 32 bit mode and old iron. + */ +#define __put_user_nocheck(val, ptr, size) \ +({ \ + __typeof__(*(ptr)) __pu_val; \ + long __pu_err = 0; \ + \ + __pu_val = (val); \ + switch (size) { \ + case 1: \ + __put_user_asm("sb", ptr); \ + break; \ + case 2: \ + __put_user_asm("sh", ptr); \ + break; \ + case 4: \ + __put_user_asm("sw", ptr); \ + break; \ + case 8: \ + if ((__copy_to_user((void *)ptr, &__pu_val, 8)) == 0) \ + __pu_err = 0; \ + else \ + __pu_err = -EFAULT; \ + break; \ + default: \ + __put_user_unknown(); \ + break; \ + } \ + __pu_err; \ +}) + + +#define __put_user_check(val, ptr, size) \ +({ \ + __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ + __typeof__(*(ptr)) __pu_val = (val); \ + long __pu_err = -EFAULT; \ + \ + if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \ + switch (size) { \ + case 1: \ + __put_user_asm("sb", __pu_addr); \ + break; \ + case 2: \ + __put_user_asm("sh", __pu_addr); \ + break; \ + case 4: \ + __put_user_asm("sw", __pu_addr); \ + break; \ + case 8: \ + if ((__copy_to_user((void *)__pu_addr, &__pu_val, 8)) == 0)\ + __pu_err = 0; \ + else \ + __pu_err = -EFAULT; \ + break; \ + default: \ + __put_user_unknown(); \ + break; \ + } \ + } \ + __pu_err; \ +}) + +#define __put_user_asm(insn, ptr) \ + __asm__ __volatile__( \ + "1:" insn " %2, %3\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3:li %0, %4\n" \ + "j 2b\n" \ + ".previous\n" \ + ".section __ex_table,\"a\"\n" \ + ".word 1b, 3b\n" \ + ".previous\n" \ + : "=r" (__pu_err) \ + : "0" (0), "r" (__pu_val), "o" (__m(ptr)), \ + "i" (-EFAULT)); + +extern void __put_user_unknown(void); +extern int __copy_tofrom_user(void *to, const void *from, unsigned long len); + +static inline unsigned long +copy_from_user(void *to, const void *from, unsigned long len) +{ + unsigned long over; + + if (access_ok(VERIFY_READ, from, len)) + return __copy_tofrom_user(to, from, len); + + if ((unsigned long)from < TASK_SIZE) { + over = (unsigned long)from + len - TASK_SIZE; + return __copy_tofrom_user(to, from, len - over) + over; + } + return len; +} + +static inline unsigned long +copy_to_user(void *to, const void *from, unsigned long len) +{ + unsigned long over; + + if (access_ok(VERIFY_WRITE, to, len)) + return __copy_tofrom_user(to, from, len); + + if ((unsigned long)to < TASK_SIZE) { + over = (unsigned long)to + len - TASK_SIZE; + return __copy_tofrom_user(to, from, len - over) + over; + } + return len; +} + +#define __copy_from_user(to, from, len) \ + __copy_tofrom_user((to), (from), (len)) + +#define __copy_to_user(to, from, len) \ + __copy_tofrom_user((to), (from), (len)) + +static inline unsigned long +__copy_to_user_inatomic(void *to, const void *from, unsigned long len) +{ + return __copy_to_user(to, from, len); +} + +static inline unsigned long +__copy_from_user_inatomic(void *to, const void *from, unsigned long len) +{ + return __copy_from_user(to, from, len); +} + +#define __copy_in_user(to, from, len) __copy_from_user(to, from, len) + +static inline unsigned long +copy_in_user(void *to, const void *from, unsigned long len) +{ + if (access_ok(VERIFY_READ, from, len) && + access_ok(VERFITY_WRITE, to, len)) + return copy_from_user(to, from, len); +} + +/* + * __clear_user: - Zero a block of memory in user space, with less checking. + * @to: Destination address, in user space. + * @n: Number of bytes to zero. + * + * Zero a block of memory in user space. Caller must check + * the specified block with access_ok() before calling this function. + * + * Returns number of bytes that could not be cleared. + * On success, this will be zero. + */ +extern unsigned long __clear_user(void __user *src, unsigned long size); + +static inline unsigned long clear_user(char *src, unsigned long size) +{ + if (access_ok(VERIFY_WRITE, src, size)) + return __clear_user(src, size); + + return -EFAULT; +} +/* + * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking. + * @dst: Destination address, in kernel space. This buffer must be at + * least @count bytes long. + * @src: Source address, in user space. + * @count: Maximum number of bytes to copy, including the trailing NUL. + * + * Copies a NUL-terminated string from userspace to kernel space. + * Caller must check the specified block with access_ok() before calling + * this function. + * + * On success, returns the length of the string (not including the trailing + * NUL). + * + * If access to userspace fails, returns -EFAULT (some data may have been + * copied). + * + * If @count is smaller than the length of the string, copies @count bytes + * and returns @count. + */ +extern int __strncpy_from_user(char *dst, const char *src, long len); + +static inline int strncpy_from_user(char *dst, const char *src, long len) +{ + if (access_ok(VERIFY_READ, src, 1)) + return __strncpy_from_user(dst, src, len); + + return -EFAULT; +} + +extern int __strlen_user(const char *src); +static inline long strlen_user(const char __user *src) +{ + return __strlen_user(src); +} + +extern int __strnlen_user(const char *str, long len); +static inline long strnlen_user(const char __user *str, long len) +{ + if (!access_ok(VERIFY_READ, str, 0)) + return 0; + else + return __strnlen_user(str, len); +} + +struct exception_table_entry { + unsigned long insn; + unsigned long fixup; +}; + +extern int fixup_exception(struct pt_regs *regs); + +#endif /* __SCORE_UACCESS_H */ + diff --git a/arch/score/include/asm/ucontext.h b/arch/score/include/asm/ucontext.h new file mode 100644 index 000000000000..9bc07b9f30fb --- /dev/null +++ b/arch/score/include/asm/ucontext.h @@ -0,0 +1 @@ +#include <asm-generic/ucontext.h> diff --git a/arch/score/include/asm/unaligned.h b/arch/score/include/asm/unaligned.h new file mode 100644 index 000000000000..2fc06de51c62 --- /dev/null +++ b/arch/score/include/asm/unaligned.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SCORE_UNALIGNED_H +#define _ASM_SCORE_UNALIGNED_H + +#include <asm-generic/unaligned.h> + +#endif /* _ASM_SCORE_UNALIGNED_H */ diff --git a/arch/score/include/asm/unistd.h b/arch/score/include/asm/unistd.h new file mode 100644 index 000000000000..4aa957364d4d --- /dev/null +++ b/arch/score/include/asm/unistd.h @@ -0,0 +1,13 @@ +#if !defined(_ASM_SCORE_UNISTD_H) || defined(__SYSCALL) +#define _ASM_SCORE_UNISTD_H + +#define __ARCH_HAVE_MMU + +#define __ARCH_WANT_SYSCALL_NO_AT +#define __ARCH_WANT_SYSCALL_NO_FLAGS +#define __ARCH_WANT_SYSCALL_OFF_T +#define __ARCH_WANT_SYSCALL_DEPRECATED + +#include <asm-generic/unistd.h> + +#endif /* _ASM_SCORE_UNISTD_H */ diff --git a/arch/score/include/asm/user.h b/arch/score/include/asm/user.h new file mode 100644 index 000000000000..7bfb8e2c8054 --- /dev/null +++ b/arch/score/include/asm/user.h @@ -0,0 +1,21 @@ +#ifndef _ASM_SCORE_USER_H +#define _ASM_SCORE_USER_H + +struct user_regs_struct { + unsigned long regs[32]; + + unsigned long cel; + unsigned long ceh; + + unsigned long sr0; /* cnt */ + unsigned long sr1; /* lcr */ + unsigned long sr2; /* scr */ + + unsigned long cp0_epc; + unsigned long cp0_ema; + unsigned long cp0_psr; + unsigned long cp0_ecr; + unsigned long cp0_condition; +}; + +#endif /* _ASM_SCORE_USER_H */ diff --git a/arch/score/kernel/Makefile b/arch/score/kernel/Makefile new file mode 100644 index 000000000000..f218673b5d3d --- /dev/null +++ b/arch/score/kernel/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for the Linux/SCORE kernel. +# + +extra-y := head.o vmlinux.lds + +obj-y += entry.o init_task.o irq.o process.o ptrace.o \ + setup.o signal.o sys_score.o time.o traps.o \ + sys_call_table.o + +obj-$(CONFIG_MODULES) += module.o diff --git a/arch/score/kernel/asm-offsets.c b/arch/score/kernel/asm-offsets.c new file mode 100644 index 000000000000..57788f44c6fb --- /dev/null +++ b/arch/score/kernel/asm-offsets.c @@ -0,0 +1,216 @@ +/* + * arch/score/kernel/asm-offsets.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kbuild.h> +#include <linux/interrupt.h> +#include <linux/mm.h> +#include <linux/sched.h> + +#include <asm-generic/cmpxchg-local.h> + +void output_ptreg_defines(void) +{ + COMMENT("SCORE pt_regs offsets."); + OFFSET(PT_R0, pt_regs, regs[0]); + OFFSET(PT_R1, pt_regs, regs[1]); + OFFSET(PT_R2, pt_regs, regs[2]); + OFFSET(PT_R3, pt_regs, regs[3]); + OFFSET(PT_R4, pt_regs, regs[4]); + OFFSET(PT_R5, pt_regs, regs[5]); + OFFSET(PT_R6, pt_regs, regs[6]); + OFFSET(PT_R7, pt_regs, regs[7]); + OFFSET(PT_R8, pt_regs, regs[8]); + OFFSET(PT_R9, pt_regs, regs[9]); + OFFSET(PT_R10, pt_regs, regs[10]); + OFFSET(PT_R11, pt_regs, regs[11]); + OFFSET(PT_R12, pt_regs, regs[12]); + OFFSET(PT_R13, pt_regs, regs[13]); + OFFSET(PT_R14, pt_regs, regs[14]); + OFFSET(PT_R15, pt_regs, regs[15]); + OFFSET(PT_R16, pt_regs, regs[16]); + OFFSET(PT_R17, pt_regs, regs[17]); + OFFSET(PT_R18, pt_regs, regs[18]); + OFFSET(PT_R19, pt_regs, regs[19]); + OFFSET(PT_R20, pt_regs, regs[20]); + OFFSET(PT_R21, pt_regs, regs[21]); + OFFSET(PT_R22, pt_regs, regs[22]); + OFFSET(PT_R23, pt_regs, regs[23]); + OFFSET(PT_R24, pt_regs, regs[24]); + OFFSET(PT_R25, pt_regs, regs[25]); + OFFSET(PT_R26, pt_regs, regs[26]); + OFFSET(PT_R27, pt_regs, regs[27]); + OFFSET(PT_R28, pt_regs, regs[28]); + OFFSET(PT_R29, pt_regs, regs[29]); + OFFSET(PT_R30, pt_regs, regs[30]); + OFFSET(PT_R31, pt_regs, regs[31]); + + OFFSET(PT_ORIG_R4, pt_regs, orig_r4); + OFFSET(PT_ORIG_R7, pt_regs, orig_r7); + OFFSET(PT_CEL, pt_regs, cel); + OFFSET(PT_CEH, pt_regs, ceh); + OFFSET(PT_SR0, pt_regs, sr0); + OFFSET(PT_SR1, pt_regs, sr1); + OFFSET(PT_SR2, pt_regs, sr2); + OFFSET(PT_EPC, pt_regs, cp0_epc); + OFFSET(PT_EMA, pt_regs, cp0_ema); + OFFSET(PT_PSR, pt_regs, cp0_psr); + OFFSET(PT_ECR, pt_regs, cp0_ecr); + OFFSET(PT_CONDITION, pt_regs, cp0_condition); + OFFSET(PT_IS_SYSCALL, pt_regs, is_syscall); + + DEFINE(PT_SIZE, sizeof(struct pt_regs)); + BLANK(); +} + +void output_task_defines(void) +{ + COMMENT("SCORE task_struct offsets."); + OFFSET(TASK_STATE, task_struct, state); + OFFSET(TASK_THREAD_INFO, task_struct, stack); + OFFSET(TASK_FLAGS, task_struct, flags); + OFFSET(TASK_MM, task_struct, mm); + OFFSET(TASK_PID, task_struct, pid); + DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct)); + BLANK(); +} + +void output_thread_info_defines(void) +{ + COMMENT("SCORE thread_info offsets."); + OFFSET(TI_TASK, thread_info, task); + OFFSET(TI_EXEC_DOMAIN, thread_info, exec_domain); + OFFSET(TI_FLAGS, thread_info, flags); + OFFSET(TI_TP_VALUE, thread_info, tp_value); + OFFSET(TI_CPU, thread_info, cpu); + OFFSET(TI_PRE_COUNT, thread_info, preempt_count); + OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit); + OFFSET(TI_RESTART_BLOCK, thread_info, restart_block); + OFFSET(TI_REGS, thread_info, regs); + DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE); + DEFINE(KERNEL_STACK_MASK, THREAD_MASK); + BLANK(); +} + +void output_thread_defines(void) +{ + COMMENT("SCORE specific thread_struct offsets."); + OFFSET(THREAD_REG0, task_struct, thread.reg0); + OFFSET(THREAD_REG2, task_struct, thread.reg2); + OFFSET(THREAD_REG3, task_struct, thread.reg3); + OFFSET(THREAD_REG12, task_struct, thread.reg12); + OFFSET(THREAD_REG13, task_struct, thread.reg13); + OFFSET(THREAD_REG14, task_struct, thread.reg14); + OFFSET(THREAD_REG15, task_struct, thread.reg15); + OFFSET(THREAD_REG16, task_struct, thread.reg16); + OFFSET(THREAD_REG17, task_struct, thread.reg17); + OFFSET(THREAD_REG18, task_struct, thread.reg18); + OFFSET(THREAD_REG19, task_struct, thread.reg19); + OFFSET(THREAD_REG20, task_struct, thread.reg20); + OFFSET(THREAD_REG21, task_struct, thread.reg21); + OFFSET(THREAD_REG29, task_struct, thread.reg29); + + OFFSET(THREAD_PSR, task_struct, thread.cp0_psr); + OFFSET(THREAD_EMA, task_struct, thread.cp0_ema); + OFFSET(THREAD_BADUADDR, task_struct, thread.cp0_baduaddr); + OFFSET(THREAD_ECODE, task_struct, thread.error_code); + OFFSET(THREAD_TRAPNO, task_struct, thread.trap_no); + BLANK(); +} + +void output_mm_defines(void) +{ + COMMENT("Size of struct page"); + DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page)); + BLANK(); + COMMENT("Linux mm_struct offsets."); + OFFSET(MM_USERS, mm_struct, mm_users); + OFFSET(MM_PGD, mm_struct, pgd); + OFFSET(MM_CONTEXT, mm_struct, context); + BLANK(); + DEFINE(_PAGE_SIZE, PAGE_SIZE); + DEFINE(_PAGE_SHIFT, PAGE_SHIFT); + BLANK(); + DEFINE(_PGD_T_SIZE, sizeof(pgd_t)); + DEFINE(_PTE_T_SIZE, sizeof(pte_t)); + BLANK(); + DEFINE(_PGD_ORDER, PGD_ORDER); + DEFINE(_PTE_ORDER, PTE_ORDER); + BLANK(); + DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT); + BLANK(); + DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD); + DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE); + BLANK(); +} + +void output_sc_defines(void) +{ + COMMENT("Linux sigcontext offsets."); + OFFSET(SC_REGS, sigcontext, sc_regs); + OFFSET(SC_MDCEH, sigcontext, sc_mdceh); + OFFSET(SC_MDCEL, sigcontext, sc_mdcel); + OFFSET(SC_PC, sigcontext, sc_pc); + OFFSET(SC_PSR, sigcontext, sc_psr); + OFFSET(SC_ECR, sigcontext, sc_ecr); + OFFSET(SC_EMA, sigcontext, sc_ema); + BLANK(); +} + +void output_signal_defined(void) +{ + COMMENT("Linux signal numbers."); + DEFINE(_SIGHUP, SIGHUP); + DEFINE(_SIGINT, SIGINT); + DEFINE(_SIGQUIT, SIGQUIT); + DEFINE(_SIGILL, SIGILL); + DEFINE(_SIGTRAP, SIGTRAP); + DEFINE(_SIGIOT, SIGIOT); + DEFINE(_SIGABRT, SIGABRT); + DEFINE(_SIGFPE, SIGFPE); + DEFINE(_SIGKILL, SIGKILL); + DEFINE(_SIGBUS, SIGBUS); + DEFINE(_SIGSEGV, SIGSEGV); + DEFINE(_SIGSYS, SIGSYS); + DEFINE(_SIGPIPE, SIGPIPE); + DEFINE(_SIGALRM, SIGALRM); + DEFINE(_SIGTERM, SIGTERM); + DEFINE(_SIGUSR1, SIGUSR1); + DEFINE(_SIGUSR2, SIGUSR2); + DEFINE(_SIGCHLD, SIGCHLD); + DEFINE(_SIGPWR, SIGPWR); + DEFINE(_SIGWINCH, SIGWINCH); + DEFINE(_SIGURG, SIGURG); + DEFINE(_SIGIO, SIGIO); + DEFINE(_SIGSTOP, SIGSTOP); + DEFINE(_SIGTSTP, SIGTSTP); + DEFINE(_SIGCONT, SIGCONT); + DEFINE(_SIGTTIN, SIGTTIN); + DEFINE(_SIGTTOU, SIGTTOU); + DEFINE(_SIGVTALRM, SIGVTALRM); + DEFINE(_SIGPROF, SIGPROF); + DEFINE(_SIGXCPU, SIGXCPU); + DEFINE(_SIGXFSZ, SIGXFSZ); + BLANK(); +} diff --git a/arch/score/kernel/entry.S b/arch/score/kernel/entry.S new file mode 100644 index 000000000000..577abba3fac6 --- /dev/null +++ b/arch/score/kernel/entry.S @@ -0,0 +1,514 @@ +/* + * arch/score/kernel/entry.S + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/linkage.h> + +#include <asm/asmmacro.h> +#include <asm/thread_info.h> +#include <asm/unistd.h> + +/* + * disable interrupts. + */ +.macro disable_irq + mfcr r8, cr0 + srli r8, r8, 1 + slli r8, r8, 1 + mtcr r8, cr0 + nop + nop + nop + nop + nop +.endm + +/* + * enable interrupts. + */ +.macro enable_irq + mfcr r8, cr0 + ori r8, 1 + mtcr r8, cr0 + nop + nop + nop + nop + nop +.endm + +__INIT +ENTRY(debug_exception_vector) + nop! + nop! + nop! + nop! + nop! + nop! + nop! + nop! + +ENTRY(general_exception_vector) # should move to addr 0x200 + j general_exception + nop! + nop! + nop! + nop! + nop! + nop! + +ENTRY(interrupt_exception_vector) # should move to addr 0x210 + j interrupt_exception + nop! + nop! + nop! + nop! + nop! + nop! + + .section ".text", "ax" + .align 2; +general_exception: + mfcr r31, cr2 + nop + la r30, exception_handlers + andi r31, 0x1f # get ecr.exc_code + slli r31, r31, 2 + add r30, r30, r31 + lw r30, [r30] + br r30 + +interrupt_exception: + SAVE_ALL + mfcr r4, cr2 + nop + lw r16, [r28, TI_REGS] + sw r0, [r28, TI_REGS] + la r3, ret_from_irq + srli r4, r4, 18 # get ecr.ip[7:2], interrupt No. + mv r5, r0 + j do_IRQ + +ENTRY(handle_nmi) # NMI #1 + SAVE_ALL + mv r4, r0 + la r8, nmi_exception_handler + brl r8 + j restore_all + +ENTRY(handle_adelinsn) # AdEL-instruction #2 + SAVE_ALL + mfcr r8, cr6 + nop + nop + sw r8, [r0, PT_EMA] + mv r4, r0 + la r8, do_adelinsn + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_ibe) # BusEL-instruction #5 + SAVE_ALL + mv r4, r0 + la r8, do_be + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_pel) # P-EL #6 + SAVE_ALL + mv r4, r0 + la r8, do_pel + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_ccu) # CCU #8 + SAVE_ALL + mv r4, r0 + la r8, do_ccu + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_ri) # RI #9 + SAVE_ALL + mv r4, r0 + la r8, do_ri + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_tr) # Trap #10 + SAVE_ALL + mv r4, r0 + la r8, do_tr + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_adedata) # AdES-instruction #12 + SAVE_ALL + mfcr r8, cr6 + nop + nop + sw r8, [r0, PT_EMA] + mv r4, r0 + la r8, do_adedata + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_cee) # CeE #16 + SAVE_ALL + mv r4, r0 + la r8, do_cee + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_cpe) # CpE #17 + SAVE_ALL + mv r4, r0 + la r8, do_cpe + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_dbe) # BusEL-data #18 + SAVE_ALL + mv r4, r0 + la r8, do_be + brl r8 + mv r4, r0 + j ret_from_exception + nop + +ENTRY(handle_reserved) # others + SAVE_ALL + mv r4, r0 + la r8, do_reserved + brl r8 + mv r4, r0 + j ret_from_exception + nop + +#ifndef CONFIG_PREEMPT +#define resume_kernel restore_all +#else +#define __ret_from_irq ret_from_exception +#endif + + .align 2 +#ifndef CONFIG_PREEMPT +ENTRY(ret_from_exception) + disable_irq # preempt stop + nop + j __ret_from_irq + nop +#endif + +ENTRY(ret_from_irq) + sw r16, [r28, TI_REGS] + +ENTRY(__ret_from_irq) + lw r8, [r0, PT_PSR] # returning to kernel mode? + andri.c r8, r8, KU_USER + beq resume_kernel + +resume_userspace: + disable_irq + lw r6, [r28, TI_FLAGS] # current->work + li r8, _TIF_WORK_MASK + and.c r8, r8, r6 # ignoring syscall_trace + bne work_pending + nop + j restore_all + nop + +#ifdef CONFIG_PREEMPT +resume_kernel: + disable_irq + lw r8, [r28, TI_PRE_COUNT] + cmpz.c r8 + bne r8, restore_all +need_resched: + lw r8, [r28, TI_FLAGS] + andri.c r9, r8, _TIF_NEED_RESCHED + beq restore_all + lw r8, [r28, PT_PSR] # Interrupts off? + andri.c r8, r8, 1 + beq restore_all + bl preempt_schedule_irq + nop + j need_resched + nop +#endif + +ENTRY(ret_from_fork) + bl schedule_tail # r4=struct task_struct *prev + +ENTRY(syscall_exit) + nop + disable_irq + lw r6, [r28, TI_FLAGS] # current->work + li r8, _TIF_WORK_MASK + and.c r8, r6, r8 + bne syscall_exit_work + +ENTRY(restore_all) # restore full frame + RESTORE_ALL_AND_RET + +work_pending: + andri.c r8, r6, _TIF_NEED_RESCHED # r6 is preloaded with TI_FLAGS + beq work_notifysig +work_resched: + bl schedule + nop + disable_irq + lw r6, [r28, TI_FLAGS] + li r8, _TIF_WORK_MASK + and.c r8, r6, r8 # is there any work to be done + # other than syscall tracing? + beq restore_all + andri.c r8, r6, _TIF_NEED_RESCHED + bne work_resched + +work_notifysig: + mv r4, r0 + li r5, 0 + bl do_notify_resume # r6 already loaded + nop + j resume_userspace + nop + +ENTRY(syscall_exit_work) + li r8, _TIF_SYSCALL_TRACE + and.c r8, r8, r6 # r6 is preloaded with TI_FLAGS + beq work_pending # trace bit set? + nop + enable_irq + mv r4, r0 + li r5, 1 + bl do_syscall_trace + nop + b resume_userspace + nop + +.macro save_context reg + sw r12, [\reg, THREAD_REG12]; + sw r13, [\reg, THREAD_REG13]; + sw r14, [\reg, THREAD_REG14]; + sw r15, [\reg, THREAD_REG15]; + sw r16, [\reg, THREAD_REG16]; + sw r17, [\reg, THREAD_REG17]; + sw r18, [\reg, THREAD_REG18]; + sw r19, [\reg, THREAD_REG19]; + sw r20, [\reg, THREAD_REG20]; + sw r21, [\reg, THREAD_REG21]; + sw r29, [\reg, THREAD_REG29]; + sw r2, [\reg, THREAD_REG2]; + sw r0, [\reg, THREAD_REG0] +.endm + +.macro restore_context reg + lw r12, [\reg, THREAD_REG12]; + lw r13, [\reg, THREAD_REG13]; + lw r14, [\reg, THREAD_REG14]; + lw r15, [\reg, THREAD_REG15]; + lw r16, [\reg, THREAD_REG16]; + lw r17, [\reg, THREAD_REG17]; + lw r18, [\reg, THREAD_REG18]; + lw r19, [\reg, THREAD_REG19]; + lw r20, [\reg, THREAD_REG20]; + lw r21, [\reg, THREAD_REG21]; + lw r29, [\reg, THREAD_REG29]; + lw r0, [\reg, THREAD_REG0]; + lw r2, [\reg, THREAD_REG2]; + lw r3, [\reg, THREAD_REG3] +.endm + +/* + * task_struct *resume(task_struct *prev, task_struct *next, + * struct thread_info *next_ti) + */ +ENTRY(resume) + mfcr r9, cr0 + nop + nop + sw r9, [r4, THREAD_PSR] + save_context r4 + sw r3, [r4, THREAD_REG3] + + mv r28, r6 + restore_context r5 + mv r8, r6 + addi r8, KERNEL_STACK_SIZE + subi r8, 32 + la r9, kernelsp; + sw r8, [r9]; + + mfcr r9, cr0 + ldis r7, 0x00ff + nop + and r9, r9, r7 + lw r6, [r5, THREAD_PSR] + not r7, r7 + and r6, r6, r7 + or r6, r6, r9 + mtcr r6, cr0 + nop; nop; nop; nop; nop + br r3 + +ENTRY(handle_sys) + SAVE_ALL + sw r8, [r0, 16] # argument 5 from user r8 + sw r9, [r0, 20] # argument 6 from user r9 + enable_irq + + sw r4, [r0, PT_ORIG_R4] #for restart syscall + sw r7, [r0, PT_ORIG_R7] #for restart syscall + sw r27, [r0, PT_IS_SYSCALL] # it from syscall + + lw r9, [r0, PT_EPC] # skip syscall on return + addi r9, 4 + sw r9, [r0, PT_EPC] + + cmpi.c r27, __NR_syscalls # check syscall number + bgtu illegal_syscall + + slli r8, r27, 2 # get syscall routine + la r11, sys_call_table + add r11, r11, r8 + lw r10, [r11] # get syscall entry + + cmpz.c r10 + beq illegal_syscall + + lw r8, [r28, TI_FLAGS] + li r9, _TIF_SYSCALL_TRACE + and.c r8, r8, r9 + bne syscall_trace_entry + + brl r10 # Do The Real system call + + cmpi.c r4, 0 + blt 1f + ldi r8, 0 + sw r8, [r0, PT_R7] + b 2f +1: + cmpi.c r4, -MAX_ERRNO - 1 + ble 2f + ldi r8, 0x1; + sw r8, [r0, PT_R7] + neg r4, r4 +2: + sw r4, [r0, PT_R4] # save result + +syscall_return: + disable_irq + lw r6, [r28, TI_FLAGS] # current->work + li r8, _TIF_WORK_MASK + and.c r8, r6, r8 + bne syscall_return_work + j restore_all + +syscall_return_work: + j syscall_exit_work + +syscall_trace_entry: + mv r16, r10 + mv r4, r0 + li r5, 0 + bl do_syscall_trace + + mv r8, r16 + lw r4, [r0, PT_R4] # Restore argument registers + lw r5, [r0, PT_R5] + lw r6, [r0, PT_R6] + lw r7, [r0, PT_R7] + brl r8 + + li r8, -MAX_ERRNO - 1 + sw r8, [r0, PT_R7] # set error flag + + neg r4, r4 # error + sw r4, [r0, PT_R0] # set flag for syscall + # restarting +1: sw r4, [r0, PT_R2] # result + j syscall_exit + +illegal_syscall: + ldi r4, -ENOSYS # error + sw r4, [r0, PT_ORIG_R4] + sw r4, [r0, PT_R4] + ldi r9, 1 # set error flag + sw r9, [r0, PT_R7] + j syscall_return + +ENTRY(sys_execve) + mv r4, r0 + la r8, score_execve + br r8 + +ENTRY(sys_clone) + mv r4, r0 + la r8, score_clone + br r8 + +ENTRY(sys_rt_sigreturn) + mv r4, r0 + la r8, score_rt_sigreturn + br r8 + +ENTRY(sys_sigaltstack) + mv r4, r0 + la r8, score_sigaltstack + br r8 + +#ifdef __ARCH_WANT_SYSCALL_DEPRECATED +ENTRY(sys_fork) + mv r4, r0 + la r8, score_fork + br r8 + +ENTRY(sys_vfork) + mv r4, r0 + la r8, score_vfork + br r8 +#endif /* __ARCH_WANT_SYSCALL_DEPRECATED */ + diff --git a/arch/score/kernel/head.S b/arch/score/kernel/head.S new file mode 100644 index 000000000000..22a7e3c7292b --- /dev/null +++ b/arch/score/kernel/head.S @@ -0,0 +1,70 @@ +/* + * arch/score/kernel/head.S + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/init.h> +#include <linux/linkage.h> + +#include <asm/asm-offsets.h> + + .extern start_kernel + .global init_thread_union + .global kernelsp + +__INIT +ENTRY(_stext) + la r30, __bss_start /* initialize BSS segment. */ + la r31, _end + xor r8, r8, r8 + +1: cmp.c r31, r30 + beq 2f + + sw r8, [r30] /* clean memory. */ + addi r30, 4 + b 1b + +2: la r28, init_thread_union /* set kernel stack. */ + mv r0, r28 + addi r0, KERNEL_STACK_SIZE - 32 + la r30, kernelsp + sw r0, [r30] + subi r0, 4*4 + xor r30, r30, r30 + ori r30, 0x02 /* enable MMU. */ + mtcr r30, cr4 + nop + nop + nop + nop + nop + nop + nop + + /* there is no parameter */ + xor r4, r4, r4 + xor r5, r5, r5 + xor r6, r6, r6 + xor r7, r7, r7 + la r30, start_kernel /* jump to init_arch */ + br r30 diff --git a/arch/score/kernel/init_task.c b/arch/score/kernel/init_task.c new file mode 100644 index 000000000000..ff952f6c63fd --- /dev/null +++ b/arch/score/kernel/init_task.c @@ -0,0 +1,47 @@ +/* + * arch/score/kernel/init_task.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/init_task.h> +#include <linux/mqueue.h> + +static struct signal_struct init_signals = INIT_SIGNALS(init_signals); +static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); + +/* + * Initial thread structure. + * + * We need to make sure that this is THREAD_SIZE aligned due to the + * way process stacks are handled. This is done by having a special + * "init_task" linker map entry.. + */ +union thread_union init_thread_union + __attribute__((__section__(".data.init_task"), __aligned__(THREAD_SIZE))) = + { INIT_THREAD_INFO(init_task) }; + +/* + * Initial task structure. + * + * All other task structs will be allocated on slabs in fork.c + */ +struct task_struct init_task = INIT_TASK(init_task); +EXPORT_SYMBOL(init_task); diff --git a/arch/score/kernel/irq.c b/arch/score/kernel/irq.c new file mode 100644 index 000000000000..47647dde09ca --- /dev/null +++ b/arch/score/kernel/irq.c @@ -0,0 +1,148 @@ +/* + * arch/score/kernel/irq.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/interrupt.h> +#include <linux/kernel_stat.h> +#include <linux/seq_file.h> + +#include <asm/io.h> + +/* the interrupt controller is hardcoded at this address */ +#define SCORE_PIC ((u32 __iomem __force *)0x95F50000) + +#define INT_PNDL 0 +#define INT_PNDH 1 +#define INT_PRIORITY_M 2 +#define INT_PRIORITY_SG0 4 +#define INT_PRIORITY_SG1 5 +#define INT_PRIORITY_SG2 6 +#define INT_PRIORITY_SG3 7 +#define INT_MASKL 8 +#define INT_MASKH 9 + +/* + * handles all normal device IRQs + */ +asmlinkage void do_IRQ(int irq) +{ + irq_enter(); + generic_handle_irq(irq); + irq_exit(); +} + +static void score_mask(unsigned int irq_nr) +{ + unsigned int irq_source = 63 - irq_nr; + + if (irq_source < 32) + __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) | \ + (1 << irq_source)), SCORE_PIC + INT_MASKL); + else + __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) | \ + (1 << (irq_source - 32))), SCORE_PIC + INT_MASKH); +} + +static void score_unmask(unsigned int irq_nr) +{ + unsigned int irq_source = 63 - irq_nr; + + if (irq_source < 32) + __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \ + ~(1 << irq_source)), SCORE_PIC + INT_MASKL); + else + __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) & \ + ~(1 << (irq_source - 32))), SCORE_PIC + INT_MASKH); +} + +struct irq_chip score_irq_chip = { + .name = "Score7-level", + .mask = score_mask, + .mask_ack = score_mask, + .unmask = score_unmask, +}; + +/* + * initialise the interrupt system + */ +void __init init_IRQ(void) +{ + int index; + unsigned long target_addr; + + for (index = 0; index < NR_IRQS; ++index) + set_irq_chip_and_handler(index, &score_irq_chip, + handle_level_irq); + + for (target_addr = IRQ_VECTOR_BASE_ADDR; + target_addr <= IRQ_VECTOR_END_ADDR; + target_addr += IRQ_VECTOR_SIZE) + memcpy((void *)target_addr, \ + interrupt_exception_vector, IRQ_VECTOR_SIZE); + + __raw_writel(0xffffffff, SCORE_PIC + INT_MASKL); + __raw_writel(0xffffffff, SCORE_PIC + INT_MASKH); + + __asm__ __volatile__( + "mtcr %0, cr3\n\t" + : : "r" (EXCEPTION_VECTOR_BASE_ADDR | \ + VECTOR_ADDRESS_OFFSET_MODE16)); +} + +/* + * Generic, controller-independent functions: + */ +int show_interrupts(struct seq_file *p, void *v) +{ + int i = *(loff_t *)v, cpu; + struct irqaction *action; + unsigned long flags; + + if (i == 0) { + seq_puts(p, " "); + for_each_online_cpu(cpu) + seq_printf(p, "CPU%d ", cpu); + seq_putc(p, '\n'); + } + + if (i < NR_IRQS) { + spin_lock_irqsave(&irq_desc[i].lock, flags); + action = irq_desc[i].action; + if (!action) + goto unlock; + + seq_printf(p, "%3d: ", i); + seq_printf(p, "%10u ", kstat_irqs(i)); + seq_printf(p, " %8s", irq_desc[i].chip->name ? : "-"); + seq_printf(p, " %s", action->name); + for (action = action->next; action; action = action->next) + seq_printf(p, ", %s", action->name); + + seq_putc(p, '\n'); +unlock: + spin_unlock_irqrestore(&irq_desc[i].lock, flags); + } + + return 0; +} diff --git a/arch/score/kernel/module.c b/arch/score/kernel/module.c new file mode 100644 index 000000000000..4de8d47becd3 --- /dev/null +++ b/arch/score/kernel/module.c @@ -0,0 +1,165 @@ +/* + * arch/score/kernel/module.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/moduleloader.h> +#include <linux/module.h> +#include <linux/vmalloc.h> + +void *module_alloc(unsigned long size) +{ + return size ? vmalloc(size) : NULL; +} + +/* Free memory returned from module_alloc */ +void module_free(struct module *mod, void *module_region) +{ + vfree(module_region); +} + +int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, + char *secstrings, struct module *mod) +{ + return 0; +} + +int apply_relocate(Elf_Shdr *sechdrs, const char *strtab, + unsigned int symindex, unsigned int relindex, + struct module *me) +{ + Elf32_Shdr *symsec = sechdrs + symindex; + Elf32_Shdr *relsec = sechdrs + relindex; + Elf32_Shdr *dstsec = sechdrs + relsec->sh_info; + Elf32_Rel *rel = (void *)relsec->sh_addr; + unsigned int i; + + for (i = 0; i < relsec->sh_size / sizeof(Elf32_Rel); i++, rel++) { + unsigned long loc; + Elf32_Sym *sym; + s32 r_offset; + + r_offset = ELF32_R_SYM(rel->r_info); + if ((r_offset < 0) || + (r_offset > (symsec->sh_size / sizeof(Elf32_Sym)))) { + printk(KERN_ERR "%s: bad relocation, section %d reloc %d\n", + me->name, relindex, i); + return -ENOEXEC; + } + + sym = ((Elf32_Sym *)symsec->sh_addr) + r_offset; + + if ((rel->r_offset < 0) || + (rel->r_offset > dstsec->sh_size - sizeof(u32))) { + printk(KERN_ERR "%s: out of bounds relocation, " + "section %d reloc %d offset %d size %d\n", + me->name, relindex, i, rel->r_offset, + dstsec->sh_size); + return -ENOEXEC; + } + + loc = dstsec->sh_addr + rel->r_offset; + switch (ELF32_R_TYPE(rel->r_info)) { + case R_SCORE_NONE: + break; + case R_SCORE_ABS32: + *(unsigned long *)loc += sym->st_value; + break; + case R_SCORE_HI16: + break; + case R_SCORE_LO16: { + unsigned long hi16_offset, offset; + unsigned long uvalue; + unsigned long temp, temp_hi; + temp_hi = *((unsigned long *)loc - 1); + temp = *(unsigned long *)loc; + + hi16_offset = (((((temp_hi) >> 16) & 0x3) << 15) | + ((temp_hi) & 0x7fff)) >> 1; + offset = ((temp >> 16 & 0x03) << 15) | + ((temp & 0x7fff) >> 1); + offset = (hi16_offset << 16) | (offset & 0xffff); + uvalue = sym->st_value + offset; + hi16_offset = (uvalue >> 16) << 1; + + temp_hi = ((temp_hi) & (~(0x37fff))) | + (hi16_offset & 0x7fff) | + ((hi16_offset << 1) & 0x30000); + *((unsigned long *)loc - 1) = temp_hi; + + offset = (uvalue & 0xffff) << 1; + temp = (temp & (~(0x37fff))) | (offset & 0x7fff) | + ((offset << 1) & 0x30000); + *(unsigned long *)loc = temp; + break; + } + case R_SCORE_24: { + unsigned long hi16_offset, offset; + unsigned long uvalue; + unsigned long temp; + + temp = *(unsigned long *)loc; + offset = (temp & 0x03FF7FFE); + hi16_offset = (offset & 0xFFFF0000); + offset = (hi16_offset | ((offset & 0xFFFF) << 1)) >> 2; + + uvalue = (sym->st_value + offset) >> 1; + uvalue = uvalue & 0x00ffffff; + + temp = (temp & 0xfc008001) | + ((uvalue << 2) & 0x3ff0000) | + ((uvalue & 0x3fff) << 1); + *(unsigned long *)loc = temp; + break; + } + default: + printk(KERN_ERR "%s: unknown relocation: %u\n", + me->name, ELF32_R_TYPE(rel->r_info)); + return -ENOEXEC; + } + } + + return 0; +} + +int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, + unsigned int symindex, unsigned int relsec, + struct module *me) +{ + return 0; +} + +/* Given an address, look for it in the module exception tables. */ +const struct exception_table_entry *search_module_dbetables(unsigned long addr) +{ + return NULL; +} + +/* Put in dbe list if necessary. */ +int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, + struct module *me) +{ + return 0; +} + +void module_arch_cleanup(struct module *mod) {} diff --git a/arch/score/kernel/process.c b/arch/score/kernel/process.c new file mode 100644 index 000000000000..25d08030a883 --- /dev/null +++ b/arch/score/kernel/process.c @@ -0,0 +1,168 @@ +/* + * arch/score/kernel/process.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/module.h> +#include <linux/reboot.h> +#include <linux/elfcore.h> +#include <linux/pm.h> + +void (*pm_power_off)(void); +EXPORT_SYMBOL(pm_power_off); + +/* If or when software machine-restart is implemented, add code here. */ +void machine_restart(char *command) {} + +/* If or when software machine-halt is implemented, add code here. */ +void machine_halt(void) {} + +/* If or when software machine-power-off is implemented, add code here. */ +void machine_power_off(void) {} + +/* + * The idle thread. There's no useful work to be + * done, so just try to conserve power and have a + * low exit latency (ie sit in a loop waiting for + * somebody to say that they'd like to reschedule) + */ +void __noreturn cpu_idle(void) +{ + /* endless idle loop with no priority at all */ + while (1) { + while (!need_resched()) + barrier(); + + preempt_enable_no_resched(); + schedule(); + preempt_disable(); + } +} + +void ret_from_fork(void); + +void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp) +{ + unsigned long status; + + /* New thread loses kernel privileges. */ + status = regs->cp0_psr & ~(KU_MASK); + status |= KU_USER; + regs->cp0_psr = status; + regs->cp0_epc = pc; + regs->regs[0] = sp; +} + +void exit_thread(void) {} + +/* + * When a process does an "exec", machine state like FPU and debug + * registers need to be reset. This is a hook function for that. + * Currently we don't have any such state to reset, so this is empty. + */ +void flush_thread(void) {} + +/* + * set up the kernel stack and exception frames for a new process + */ +int copy_thread(unsigned long clone_flags, unsigned long usp, + unsigned long unused, + struct task_struct *p, struct pt_regs *regs) +{ + struct thread_info *ti = task_thread_info(p); + struct pt_regs *childregs = task_pt_regs(p); + + p->set_child_tid = NULL; + p->clear_child_tid = NULL; + + *childregs = *regs; + childregs->regs[7] = 0; /* Clear error flag */ + childregs->regs[4] = 0; /* Child gets zero as return value */ + regs->regs[4] = p->pid; + + if (childregs->cp0_psr & 0x8) { /* test kernel fork or user fork */ + childregs->regs[0] = usp; /* user fork */ + } else { + childregs->regs[28] = (unsigned long) ti; /* kernel fork */ + childregs->regs[0] = (unsigned long) childregs; + } + + p->thread.reg0 = (unsigned long) childregs; + p->thread.reg3 = (unsigned long) ret_from_fork; + p->thread.cp0_psr = 0; + + return 0; +} + +/* Fill in the fpu structure for a core dump. */ +int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r) +{ + return 1; +} + +static void __noreturn +kernel_thread_helper(void *unused0, int (*fn)(void *), + void *arg, void *unused1) +{ + do_exit(fn(arg)); +} + +/* + * Create a kernel thread. + */ +long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) +{ + struct pt_regs regs; + + memset(®s, 0, sizeof(regs)); + + regs.regs[6] = (unsigned long) arg; + regs.regs[5] = (unsigned long) fn; + regs.cp0_epc = (unsigned long) kernel_thread_helper; + regs.cp0_psr = (regs.cp0_psr & ~(0x1|0x4|0x8)) | \ + ((regs.cp0_psr & 0x3) << 2); + + return do_fork(flags | CLONE_VM | CLONE_UNTRACED, \ + 0, ®s, 0, NULL, NULL); +} + +unsigned long thread_saved_pc(struct task_struct *tsk) +{ + return task_pt_regs(tsk)->cp0_epc; +} + +unsigned long get_wchan(struct task_struct *task) +{ + if (!task || task == current || task->state == TASK_RUNNING) + return 0; + + if (!task_stack_page(task)) + return 0; + + return task_pt_regs(task)->cp0_epc; +} + +unsigned long arch_align_stack(unsigned long sp) +{ + return sp; +} diff --git a/arch/score/kernel/ptrace.c b/arch/score/kernel/ptrace.c new file mode 100644 index 000000000000..174c6422b096 --- /dev/null +++ b/arch/score/kernel/ptrace.c @@ -0,0 +1,382 @@ +/* + * arch/score/kernel/ptrace.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/elf.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/ptrace.h> +#include <linux/regset.h> + +#include <asm/uaccess.h> + +/* + * retrieve the contents of SCORE userspace general registers + */ +static int genregs_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + const struct pt_regs *regs = task_pt_regs(target); + int ret; + + /* skip 9 * sizeof(unsigned long) not use for pt_regs */ + ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, + 0, offsetof(struct pt_regs, regs)); + + /* r0 - r31, cel, ceh, sr0, sr1, sr2, epc, ema, psr, ecr, condition */ + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + regs->regs, + offsetof(struct pt_regs, regs), + offsetof(struct pt_regs, cp0_condition)); + + if (!ret) + ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, + sizeof(struct pt_regs), -1); + + return ret; +} + +/* + * update the contents of the SCORE userspace general registers + */ +static int genregs_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct pt_regs *regs = task_pt_regs(target); + int ret; + + /* skip 9 * sizeof(unsigned long) */ + ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, + 0, offsetof(struct pt_regs, regs)); + + /* r0 - r31, cel, ceh, sr0, sr1, sr2, epc, ema, psr, ecr, condition */ + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + regs->regs, + offsetof(struct pt_regs, regs), + offsetof(struct pt_regs, cp0_condition)); + + if (!ret) + ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, + sizeof(struct pt_regs), -1); + + return ret; +} + +/* + * Define the register sets available on the score7 under Linux + */ +enum score7_regset { + REGSET_GENERAL, +}; + +static const struct user_regset score7_regsets[] = { + [REGSET_GENERAL] = { + .core_note_type = NT_PRSTATUS, + .n = ELF_NGREG, + .size = sizeof(long), + .align = sizeof(long), + .get = genregs_get, + .set = genregs_set, + }, +}; + +static const struct user_regset_view user_score_native_view = { + .name = "score7", + .e_machine = EM_SCORE7, + .regsets = score7_regsets, + .n = ARRAY_SIZE(score7_regsets), +}; + +const struct user_regset_view *task_user_regset_view(struct task_struct *task) +{ + return &user_score_native_view; +} + +static int is_16bitinsn(unsigned long insn) +{ + if ((insn & INSN32_MASK) == INSN32_MASK) + return 0; + else + return 1; +} + +int +read_tsk_long(struct task_struct *child, + unsigned long addr, unsigned long *res) +{ + int copied; + + copied = access_process_vm(child, addr, res, sizeof(*res), 0); + + return copied != sizeof(*res) ? -EIO : 0; +} + +int +read_tsk_short(struct task_struct *child, + unsigned long addr, unsigned short *res) +{ + int copied; + + copied = access_process_vm(child, addr, res, sizeof(*res), 0); + + return copied != sizeof(*res) ? -EIO : 0; +} + +static int +write_tsk_short(struct task_struct *child, + unsigned long addr, unsigned short val) +{ + int copied; + + copied = access_process_vm(child, addr, &val, sizeof(val), 1); + + return copied != sizeof(val) ? -EIO : 0; +} + +static int +write_tsk_long(struct task_struct *child, + unsigned long addr, unsigned long val) +{ + int copied; + + copied = access_process_vm(child, addr, &val, sizeof(val), 1); + + return copied != sizeof(val) ? -EIO : 0; +} + +void user_enable_single_step(struct task_struct *child) +{ + /* far_epc is the target of branch */ + unsigned int epc, far_epc = 0; + unsigned long epc_insn, far_epc_insn; + int ninsn_type; /* next insn type 0=16b, 1=32b */ + unsigned int tmp, tmp2; + struct pt_regs *regs = task_pt_regs(child); + child->thread.single_step = 1; + child->thread.ss_nextcnt = 1; + epc = regs->cp0_epc; + + read_tsk_long(child, epc, &epc_insn); + + if (is_16bitinsn(epc_insn)) { + if ((epc_insn & J16M) == J16) { + tmp = epc_insn & 0xFFE; + epc = (epc & 0xFFFFF000) | tmp; + } else if ((epc_insn & B16M) == B16) { + child->thread.ss_nextcnt = 2; + tmp = (epc_insn & 0xFF) << 1; + tmp = tmp << 23; + tmp = (unsigned int)((int) tmp >> 23); + far_epc = epc + tmp; + epc += 2; + } else if ((epc_insn & BR16M) == BR16) { + child->thread.ss_nextcnt = 2; + tmp = (epc_insn >> 4) & 0xF; + far_epc = regs->regs[tmp]; + epc += 2; + } else + epc += 2; + } else { + if ((epc_insn & J32M) == J32) { + tmp = epc_insn & 0x03FFFFFE; + tmp2 = tmp & 0x7FFF; + tmp = (((tmp >> 16) & 0x3FF) << 15) | tmp2; + epc = (epc & 0xFFC00000) | tmp; + } else if ((epc_insn & B32M) == B32) { + child->thread.ss_nextcnt = 2; + tmp = epc_insn & 0x03FFFFFE; /* discard LK bit */ + tmp2 = tmp & 0x3FF; + tmp = (((tmp >> 16) & 0x3FF) << 10) | tmp2; /* 20bit */ + tmp = tmp << 12; + tmp = (unsigned int)((int) tmp >> 12); + far_epc = epc + tmp; + epc += 4; + } else if ((epc_insn & BR32M) == BR32) { + child->thread.ss_nextcnt = 2; + tmp = (epc_insn >> 16) & 0x1F; + far_epc = regs->regs[tmp]; + epc += 4; + } else + epc += 4; + } + + if (child->thread.ss_nextcnt == 1) { + read_tsk_long(child, epc, &epc_insn); + + if (is_16bitinsn(epc_insn)) { + write_tsk_short(child, epc, SINGLESTEP16_INSN); + ninsn_type = 0; + } else { + write_tsk_long(child, epc, SINGLESTEP32_INSN); + ninsn_type = 1; + } + + if (ninsn_type == 0) { /* 16bits */ + child->thread.insn1_type = 0; + child->thread.addr1 = epc; + /* the insn may have 32bit data */ + child->thread.insn1 = (short)epc_insn; + } else { + child->thread.insn1_type = 1; + child->thread.addr1 = epc; + child->thread.insn1 = epc_insn; + } + } else { + /* branch! have two target child->thread.ss_nextcnt=2 */ + read_tsk_long(child, epc, &epc_insn); + read_tsk_long(child, far_epc, &far_epc_insn); + if (is_16bitinsn(epc_insn)) { + write_tsk_short(child, epc, SINGLESTEP16_INSN); + ninsn_type = 0; + } else { + write_tsk_long(child, epc, SINGLESTEP32_INSN); + ninsn_type = 1; + } + + if (ninsn_type == 0) { /* 16bits */ + child->thread.insn1_type = 0; + child->thread.addr1 = epc; + /* the insn may have 32bit data */ + child->thread.insn1 = (short)epc_insn; + } else { + child->thread.insn1_type = 1; + child->thread.addr1 = epc; + child->thread.insn1 = epc_insn; + } + + if (is_16bitinsn(far_epc_insn)) { + write_tsk_short(child, far_epc, SINGLESTEP16_INSN); + ninsn_type = 0; + } else { + write_tsk_long(child, far_epc, SINGLESTEP32_INSN); + ninsn_type = 1; + } + + if (ninsn_type == 0) { /* 16bits */ + child->thread.insn2_type = 0; + child->thread.addr2 = far_epc; + /* the insn may have 32bit data */ + child->thread.insn2 = (short)far_epc_insn; + } else { + child->thread.insn2_type = 1; + child->thread.addr2 = far_epc; + child->thread.insn2 = far_epc_insn; + } + } +} + +void user_disable_single_step(struct task_struct *child) +{ + if (child->thread.insn1_type == 0) + write_tsk_short(child, child->thread.addr1, + child->thread.insn1); + + if (child->thread.insn1_type == 1) + write_tsk_long(child, child->thread.addr1, + child->thread.insn1); + + if (child->thread.ss_nextcnt == 2) { /* branch */ + if (child->thread.insn1_type == 0) + write_tsk_short(child, child->thread.addr1, + child->thread.insn1); + if (child->thread.insn1_type == 1) + write_tsk_long(child, child->thread.addr1, + child->thread.insn1); + if (child->thread.insn2_type == 0) + write_tsk_short(child, child->thread.addr2, + child->thread.insn2); + if (child->thread.insn2_type == 1) + write_tsk_long(child, child->thread.addr2, + child->thread.insn2); + } + + child->thread.single_step = 0; + child->thread.ss_nextcnt = 0; +} + +void ptrace_disable(struct task_struct *child) +{ + user_disable_single_step(child); +} + +long +arch_ptrace(struct task_struct *child, long request, long addr, long data) +{ + int ret; + unsigned long __user *datap = (void __user *)data; + + switch (request) { + case PTRACE_GETREGS: + ret = copy_regset_to_user(child, &user_score_native_view, + REGSET_GENERAL, + 0, sizeof(struct pt_regs), + (void __user *)datap); + break; + + case PTRACE_SETREGS: + ret = copy_regset_from_user(child, &user_score_native_view, + REGSET_GENERAL, + 0, sizeof(struct pt_regs), + (const void __user *)datap); + break; + + default: + ret = ptrace_request(child, request, addr, data); + break; + } + + return ret; +} + +/* + * Notification of system call entry/exit + * - triggered by current->work.syscall_trace + */ +asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) +{ + if (!(current->ptrace & PT_PTRACED)) + return; + + if (!test_thread_flag(TIF_SYSCALL_TRACE)) + return; + + /* The 0x80 provides a way for the tracing parent to distinguish + between a syscall stop and SIGTRAP delivery. */ + ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? + 0x80 : 0)); + + /* + * this isn't the same as continuing with a signal, but it will do + * for normal use. strace only continues with a signal if the + * stopping signal is not SIGTRAP. -brl + */ + if (current->exit_code) { + send_sig(current->exit_code, current, 1); + current->exit_code = 0; + } +} diff --git a/arch/score/kernel/setup.c b/arch/score/kernel/setup.c new file mode 100644 index 000000000000..6a2503c75c4e --- /dev/null +++ b/arch/score/kernel/setup.c @@ -0,0 +1,159 @@ +/* + * arch/score/kernel/setup.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/bootmem.h> +#include <linux/initrd.h> +#include <linux/ioport.h> +#include <linux/mm.h> +#include <linux/seq_file.h> +#include <linux/screen_info.h> + +#include <asm-generic/sections.h> +#include <asm/setup.h> + +struct screen_info screen_info; +unsigned long kernelsp; + +static char command_line[COMMAND_LINE_SIZE]; +static struct resource code_resource = { .name = "Kernel code",}; +static struct resource data_resource = { .name = "Kernel data",}; + +static void __init bootmem_init(void) +{ + unsigned long start_pfn, bootmap_size; + unsigned long size = initrd_end - initrd_start; + + start_pfn = PFN_UP(__pa(&_end)); + + min_low_pfn = PFN_UP(MEMORY_START); + max_low_pfn = PFN_UP(MEMORY_START + MEMORY_SIZE); + + /* Initialize the boot-time allocator with low memory only. */ + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn, + min_low_pfn, max_low_pfn); + add_active_range(0, min_low_pfn, max_low_pfn); + + free_bootmem(PFN_PHYS(start_pfn), + (max_low_pfn - start_pfn) << PAGE_SHIFT); + memory_present(0, start_pfn, max_low_pfn); + + /* Reserve space for the bootmem bitmap. */ + reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size, BOOTMEM_DEFAULT); + + if (size == 0) { + printk(KERN_INFO "Initrd not found or empty"); + goto disable; + } + + if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { + printk(KERN_ERR "Initrd extends beyond end of memory"); + goto disable; + } + + /* Reserve space for the initrd bitmap. */ + reserve_bootmem(__pa(initrd_start), size, BOOTMEM_DEFAULT); + initrd_below_start_ok = 1; + + pr_info("Initial ramdisk at: 0x%lx (%lu bytes)\n", + initrd_start, size); + return; +disable: + printk(KERN_CONT " - disabling initrd\n"); + initrd_start = 0; + initrd_end = 0; +} + +static void __init resource_init(void) +{ + struct resource *res; + + code_resource.start = __pa(&_text); + code_resource.end = __pa(&_etext) - 1; + data_resource.start = __pa(&_etext); + data_resource.end = __pa(&_edata) - 1; + + res = alloc_bootmem(sizeof(struct resource)); + res->name = "System RAM"; + res->start = MEMORY_START; + res->end = MEMORY_START + MEMORY_SIZE - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; + request_resource(&iomem_resource, res); + + request_resource(res, &code_resource); + request_resource(res, &data_resource); +} + +void __init setup_arch(char **cmdline_p) +{ + randomize_va_space = 0; + *cmdline_p = command_line; + + cpu_cache_init(); + tlb_init(); + bootmem_init(); + paging_init(); + resource_init(); +} + +static int show_cpuinfo(struct seq_file *m, void *v) +{ + unsigned long n = (unsigned long) v - 1; + + seq_printf(m, "processor\t\t: %ld\n", n); + seq_printf(m, "\n"); + + return 0; +} + +static void *c_start(struct seq_file *m, loff_t *pos) +{ + unsigned long i = *pos; + + return i < 1 ? (void *) (i + 1) : NULL; +} + +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return c_start(m, pos); +} + +static void c_stop(struct seq_file *m, void *v) +{ +} + +const struct seq_operations cpuinfo_op = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = show_cpuinfo, +}; + +static int __init topology_init(void) +{ + return 0; +} + +subsys_initcall(topology_init); diff --git a/arch/score/kernel/signal.c b/arch/score/kernel/signal.c new file mode 100644 index 000000000000..aa57440e4973 --- /dev/null +++ b/arch/score/kernel/signal.c @@ -0,0 +1,361 @@ +/* + * arch/score/kernel/signal.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/errno.h> +#include <linux/signal.h> +#include <linux/ptrace.h> +#include <linux/unistd.h> +#include <linux/uaccess.h> + +#include <asm/cacheflush.h> +#include <asm/syscalls.h> +#include <asm/ucontext.h> + +#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) + +struct rt_sigframe { + u32 rs_ass[4]; /* argument save space */ + u32 rs_code[2]; /* signal trampoline */ + struct siginfo rs_info; + struct ucontext rs_uc; +}; + +static int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) +{ + int err = 0; + unsigned long reg; + + reg = regs->cp0_epc; err |= __put_user(reg, &sc->sc_pc); + err |= __put_user(regs->cp0_psr, &sc->sc_psr); + err |= __put_user(regs->cp0_condition, &sc->sc_condition); + + +#define save_gp_reg(i) { \ + reg = regs->regs[i]; \ + err |= __put_user(reg, &sc->sc_regs[i]); \ +} while (0) + save_gp_reg(0); save_gp_reg(1); save_gp_reg(2); + save_gp_reg(3); save_gp_reg(4); save_gp_reg(5); + save_gp_reg(6); save_gp_reg(7); save_gp_reg(8); + save_gp_reg(9); save_gp_reg(10); save_gp_reg(11); + save_gp_reg(12); save_gp_reg(13); save_gp_reg(14); + save_gp_reg(15); save_gp_reg(16); save_gp_reg(17); + save_gp_reg(18); save_gp_reg(19); save_gp_reg(20); + save_gp_reg(21); save_gp_reg(22); save_gp_reg(23); + save_gp_reg(24); save_gp_reg(25); save_gp_reg(26); + save_gp_reg(27); save_gp_reg(28); save_gp_reg(29); +#undef save_gp_reg + + reg = regs->ceh; err |= __put_user(reg, &sc->sc_mdceh); + reg = regs->cel; err |= __put_user(reg, &sc->sc_mdcel); + err |= __put_user(regs->cp0_ecr, &sc->sc_ecr); + err |= __put_user(regs->cp0_ema, &sc->sc_ema); + + return err; +} + +static int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) +{ + int err = 0; + u32 reg; + + err |= __get_user(regs->cp0_epc, &sc->sc_pc); + err |= __get_user(regs->cp0_condition, &sc->sc_condition); + + err |= __get_user(reg, &sc->sc_mdceh); + regs->ceh = (int) reg; + err |= __get_user(reg, &sc->sc_mdcel); + regs->cel = (int) reg; + + err |= __get_user(reg, &sc->sc_psr); + regs->cp0_psr = (int) reg; + err |= __get_user(reg, &sc->sc_ecr); + regs->cp0_ecr = (int) reg; + err |= __get_user(reg, &sc->sc_ema); + regs->cp0_ema = (int) reg; + +#define restore_gp_reg(i) do { \ + err |= __get_user(reg, &sc->sc_regs[i]); \ + regs->regs[i] = reg; \ +} while (0) + restore_gp_reg(0); restore_gp_reg(1); restore_gp_reg(2); + restore_gp_reg(3); restore_gp_reg(4); restore_gp_reg(5); + restore_gp_reg(6); restore_gp_reg(7); restore_gp_reg(8); + restore_gp_reg(9); restore_gp_reg(10); restore_gp_reg(11); + restore_gp_reg(12); restore_gp_reg(13); restore_gp_reg(14); + restore_gp_reg(15); restore_gp_reg(16); restore_gp_reg(17); + restore_gp_reg(18); restore_gp_reg(19); restore_gp_reg(20); + restore_gp_reg(21); restore_gp_reg(22); restore_gp_reg(23); + restore_gp_reg(24); restore_gp_reg(25); restore_gp_reg(26); + restore_gp_reg(27); restore_gp_reg(28); restore_gp_reg(29); +#undef restore_gp_reg + + return err; +} + +/* + * Determine which stack to use.. + */ +static void __user *get_sigframe(struct k_sigaction *ka, + struct pt_regs *regs, size_t frame_size) +{ + unsigned long sp; + + /* Default to using normal stack */ + sp = regs->regs[0]; + sp -= 32; + + /* This is the X/Open sanctioned signal stack switching. */ + if ((ka->sa.sa_flags & SA_ONSTACK) && (!on_sig_stack(sp))) + sp = current->sas_ss_sp + current->sas_ss_size; + + return (void __user*)((sp - frame_size) & ~7); +} + +asmlinkage long +score_sigaltstack(struct pt_regs *regs) +{ + const stack_t __user *uss = (const stack_t __user *) regs->regs[4]; + stack_t __user *uoss = (stack_t __user *) regs->regs[5]; + unsigned long usp = regs->regs[0]; + + return do_sigaltstack(uss, uoss, usp); +} + +asmlinkage long +score_rt_sigreturn(struct pt_regs *regs) +{ + struct rt_sigframe __user *frame; + sigset_t set; + stack_t st; + int sig; + + frame = (struct rt_sigframe __user *) regs->regs[0]; + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__copy_from_user(&set, &frame->rs_uc.uc_sigmask, sizeof(set))) + goto badframe; + + sigdelsetmask(&set, ~_BLOCKABLE); + spin_lock_irq(¤t->sighand->siglock); + current->blocked = set; + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + + sig = restore_sigcontext(regs, &frame->rs_uc.uc_mcontext); + if (sig < 0) + goto badframe; + else if (sig) + force_sig(sig, current); + + if (__copy_from_user(&st, &frame->rs_uc.uc_stack, sizeof(st))) + goto badframe; + + /* It is more difficult to avoid calling this function than to + call it and ignore errors. */ + do_sigaltstack((stack_t __user *)&st, NULL, regs->regs[0]); + + __asm__ __volatile__( + "mv\tr0, %0\n\t" + "la\tr8, syscall_exit\n\t" + "br\tr8\n\t" + : : "r" (regs) : "r8"); + +badframe: + force_sig(SIGSEGV, current); + + return 0; +} + +static int setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs, + int signr, sigset_t *set, siginfo_t *info) +{ + struct rt_sigframe __user *frame; + int err = 0; + + frame = get_sigframe(ka, regs, sizeof(*frame)); + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + goto give_sigsegv; + + /* + * Set up the return code ... + * + * li v0, __NR_rt_sigreturn + * syscall + */ + err |= __put_user(0x87788000 + __NR_rt_sigreturn*2, + frame->rs_code + 0); + err |= __put_user(0x80008002, frame->rs_code + 1); + flush_cache_sigtramp((unsigned long) frame->rs_code); + + err |= copy_siginfo_to_user(&frame->rs_info, info); + err |= __put_user(0, &frame->rs_uc.uc_flags); + err |= __put_user(NULL, &frame->rs_uc.uc_link); + err |= __put_user((void __user *)current->sas_ss_sp, + &frame->rs_uc.uc_stack.ss_sp); + err |= __put_user(sas_ss_flags(regs->regs[0]), + &frame->rs_uc.uc_stack.ss_flags); + err |= __put_user(current->sas_ss_size, + &frame->rs_uc.uc_stack.ss_size); + err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext); + err |= __copy_to_user(&frame->rs_uc.uc_sigmask, set, sizeof(*set)); + + if (err) + goto give_sigsegv; + + regs->regs[0] = (unsigned long) frame; + regs->regs[3] = (unsigned long) frame->rs_code; + regs->regs[4] = signr; + regs->regs[5] = (unsigned long) &frame->rs_info; + regs->regs[6] = (unsigned long) &frame->rs_uc; + regs->regs[29] = (unsigned long) ka->sa.sa_handler; + regs->cp0_epc = (unsigned long) ka->sa.sa_handler; + + return 0; + +give_sigsegv: + if (signr == SIGSEGV) + ka->sa.sa_handler = SIG_DFL; + force_sig(SIGSEGV, current); + return -EFAULT; +} + +static int handle_signal(unsigned long sig, siginfo_t *info, + struct k_sigaction *ka, sigset_t *oldset, struct pt_regs *regs) +{ + int ret; + + if (regs->is_syscall) { + switch (regs->regs[4]) { + case ERESTART_RESTARTBLOCK: + case ERESTARTNOHAND: + regs->regs[4] = EINTR; + break; + case ERESTARTSYS: + if (!(ka->sa.sa_flags & SA_RESTART)) { + regs->regs[4] = EINTR; + break; + } + case ERESTARTNOINTR: + regs->regs[4] = regs->orig_r4; + regs->regs[7] = regs->orig_r7; + regs->cp0_epc -= 8; + } + + regs->is_syscall = 0; + } + + /* + * Set up the stack frame + */ + ret = setup_rt_frame(ka, regs, sig, oldset, info); + + spin_lock_irq(¤t->sighand->siglock); + sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); + if (!(ka->sa.sa_flags & SA_NODEFER)) + sigaddset(¤t->blocked, sig); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + + return ret; +} + +static void do_signal(struct pt_regs *regs) +{ + struct k_sigaction ka; + sigset_t *oldset; + siginfo_t info; + int signr; + + /* + * We want the common case to go fast, which is why we may in certain + * cases get here from kernel mode. Just return without doing anything + * if so. + */ + if (!user_mode(regs)) + return; + + if (test_thread_flag(TIF_RESTORE_SIGMASK)) + oldset = ¤t->saved_sigmask; + else + oldset = ¤t->blocked; + + signr = get_signal_to_deliver(&info, &ka, regs, NULL); + if (signr > 0) { + /* Actually deliver the signal. */ + if (handle_signal(signr, &info, &ka, oldset, regs) == 0) { + /* + * A signal was successfully delivered; the saved + * sigmask will have been stored in the signal frame, + * and will be restored by sigreturn, so we can simply + * clear the TIF_RESTORE_SIGMASK flag. + */ + if (test_thread_flag(TIF_RESTORE_SIGMASK)) + clear_thread_flag(TIF_RESTORE_SIGMASK); + } + + return; + } + + if (regs->is_syscall) { + if (regs->regs[4] == ERESTARTNOHAND || + regs->regs[4] == ERESTARTSYS || + regs->regs[4] == ERESTARTNOINTR) { + regs->regs[4] = regs->orig_r4; + regs->regs[7] = regs->orig_r7; + regs->cp0_epc -= 8; + } + + if (regs->regs[4] == ERESTART_RESTARTBLOCK) { + regs->regs[27] = __NR_restart_syscall; + regs->regs[4] = regs->orig_r4; + regs->regs[7] = regs->orig_r7; + regs->cp0_epc -= 8; + } + + regs->is_syscall = 0; /* Don't deal with this again. */ + } + + /* + * If there's no signal to deliver, we just put the saved sigmask + * back + */ + if (test_thread_flag(TIF_RESTORE_SIGMASK)) { + clear_thread_flag(TIF_RESTORE_SIGMASK); + sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); + } +} + +/* + * notification of userspace execution resumption + * - triggered by the TIF_WORK_MASK flags + */ +asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused, + __u32 thread_info_flags) +{ + /* deal with pending signal delivery */ + if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK)) + do_signal(regs); +} diff --git a/arch/score/kernel/sys_call_table.c b/arch/score/kernel/sys_call_table.c new file mode 100644 index 000000000000..287369b88c43 --- /dev/null +++ b/arch/score/kernel/sys_call_table.c @@ -0,0 +1,12 @@ +#include <linux/syscalls.h> +#include <linux/signal.h> +#include <linux/unistd.h> + +#include <asm/syscalls.h> + +#undef __SYSCALL +#define __SYSCALL(nr, call) [nr] = (call), + +void *sys_call_table[__NR_syscalls] = { +#include <asm/unistd.h> +}; diff --git a/arch/score/kernel/sys_score.c b/arch/score/kernel/sys_score.c new file mode 100644 index 000000000000..001249469866 --- /dev/null +++ b/arch/score/kernel/sys_score.c @@ -0,0 +1,151 @@ +/* + * arch/score/kernel/syscall.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/file.h> +#include <linux/fs.h> +#include <linux/mm.h> +#include <linux/mman.h> +#include <linux/module.h> +#include <linux/unistd.h> +#include <linux/syscalls.h> +#include <asm/syscalls.h> + +asmlinkage long +sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot, + unsigned long flags, unsigned long fd, unsigned long pgoff) +{ + int error = -EBADF; + struct file *file = NULL; + + if (pgoff & (~PAGE_MASK >> 12)) + return -EINVAL; + + flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); + if (!(flags & MAP_ANONYMOUS)) { + file = fget(fd); + if (!file) + return error; + } + + down_write(¤t->mm->mmap_sem); + error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff); + up_write(¤t->mm->mmap_sem); + + if (file) + fput(file); + + return error; +} + +asmlinkage long +sys_mmap(unsigned long addr, unsigned long len, unsigned long prot, + unsigned long flags, unsigned long fd, off_t pgoff) +{ + return sys_mmap2(addr, len, prot, flags, fd, pgoff >> PAGE_SHIFT); +} + +asmlinkage long +score_fork(struct pt_regs *regs) +{ + return do_fork(SIGCHLD, regs->regs[0], regs, 0, NULL, NULL); +} + +/* + * Clone a task - this clones the calling program thread. + * This is called indirectly via a small wrapper + */ +asmlinkage long +score_clone(struct pt_regs *regs) +{ + unsigned long clone_flags; + unsigned long newsp; + int __user *parent_tidptr, *child_tidptr; + + clone_flags = regs->regs[4]; + newsp = regs->regs[5]; + if (!newsp) + newsp = regs->regs[0]; + parent_tidptr = (int __user *)regs->regs[6]; + child_tidptr = (int __user *)regs->regs[8]; + + return do_fork(clone_flags, newsp, regs, 0, + parent_tidptr, child_tidptr); +} + +asmlinkage long +score_vfork(struct pt_regs *regs) +{ + return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, + regs->regs[0], regs, 0, NULL, NULL); +} + +/* + * sys_execve() executes a new program. + * This is called indirectly via a small wrapper + */ +asmlinkage long +score_execve(struct pt_regs *regs) +{ + int error; + char *filename; + + filename = getname((char __user*)regs->regs[4]); + error = PTR_ERR(filename); + if (IS_ERR(filename)) + return error; + + error = do_execve(filename, (char __user *__user*)regs->regs[5], + (char __user *__user *) regs->regs[6], regs); + + putname(filename); + return error; +} + +/* + * Do a system call from kernel instead of calling sys_execve so we + * end up with proper pt_regs. + */ +int kernel_execve(const char *filename, char *const argv[], char *const envp[]) +{ + register unsigned long __r4 asm("r4") = (unsigned long) filename; + register unsigned long __r5 asm("r5") = (unsigned long) argv; + register unsigned long __r6 asm("r6") = (unsigned long) envp; + register unsigned long __r7 asm("r7"); + + __asm__ __volatile__ (" \n" + "ldi r27, %5 \n" + "syscall \n" + "mv %0, r4 \n" + "mv %1, r7 \n" + : "=&r" (__r4), "=r" (__r7) + : "r" (__r4), "r" (__r5), "r" (__r6), "i" (__NR_execve) + : "r8", "r9", "r10", "r11", "r22", "r23", "r24", "r25", + "r26", "r27", "memory"); + + if (__r7 == 0) + return __r4; + + return -__r4; +} diff --git a/arch/score/kernel/time.c b/arch/score/kernel/time.c new file mode 100644 index 000000000000..f0a43affb201 --- /dev/null +++ b/arch/score/kernel/time.c @@ -0,0 +1,99 @@ +/* + * arch/score/kernel/time.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/clockchips.h> +#include <linux/interrupt.h> + +#include <asm/scoreregs.h> + +static irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evdev = dev_id; + + /* clear timer interrupt flag */ + outl(1, P_TIMER0_CPP_REG); + evdev->event_handler(evdev); + + return IRQ_HANDLED; +} + +static struct irqaction timer_irq = { + .handler = timer_interrupt, + .flags = IRQF_DISABLED | IRQF_TIMER, + .name = "timer", +}; + +static int score_timer_set_next_event(unsigned long delta, + struct clock_event_device *evdev) +{ + outl((TMR_M_PERIODIC | TMR_IE_ENABLE), P_TIMER0_CTRL); + outl(delta, P_TIMER0_PRELOAD); + outl(inl(P_TIMER0_CTRL) | TMR_ENABLE, P_TIMER0_CTRL); + + return 0; +} + +static void score_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evdev) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + outl((TMR_M_PERIODIC | TMR_IE_ENABLE), P_TIMER0_CTRL); + outl(SYSTEM_CLOCK/HZ, P_TIMER0_PRELOAD); + outl(inl(P_TIMER0_CTRL) | TMR_ENABLE, P_TIMER0_CTRL); + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_UNUSED: + break; + default: + BUG(); + } +} + +static struct clock_event_device score_clockevent = { + .name = "score_clockevent", + .features = CLOCK_EVT_FEAT_PERIODIC, + .shift = 16, + .set_next_event = score_timer_set_next_event, + .set_mode = score_timer_set_mode, +}; + +void __init time_init(void) +{ + timer_irq.dev_id = &score_clockevent; + setup_irq(IRQ_TIMER , &timer_irq); + + /* setup COMPARE clockevent */ + score_clockevent.mult = div_sc(SYSTEM_CLOCK, NSEC_PER_SEC, + score_clockevent.shift); + score_clockevent.max_delta_ns = clockevent_delta2ns((u32)~0, + &score_clockevent); + score_clockevent.min_delta_ns = clockevent_delta2ns(50, + &score_clockevent) + 1; + score_clockevent.cpumask = cpumask_of(0); + clockevents_register_device(&score_clockevent); +} diff --git a/arch/score/kernel/traps.c b/arch/score/kernel/traps.c new file mode 100644 index 000000000000..0e46fb19a848 --- /dev/null +++ b/arch/score/kernel/traps.c @@ -0,0 +1,349 @@ +/* + * arch/score/kernel/traps.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/module.h> +#include <linux/sched.h> + +#include <asm/cacheflush.h> +#include <asm/irq.h> +#include <asm/irq_regs.h> + +unsigned long exception_handlers[32]; + +/* + * The architecture-independent show_stack generator + */ +void show_stack(struct task_struct *task, unsigned long *sp) +{ + int i; + long stackdata; + + sp = sp ? sp : (unsigned long *)&sp; + + printk(KERN_NOTICE "Stack: "); + i = 1; + while ((long) sp & (PAGE_SIZE - 1)) { + if (i && ((i % 8) == 0)) + printk(KERN_NOTICE "\n"); + if (i > 40) { + printk(KERN_NOTICE " ..."); + break; + } + + if (__get_user(stackdata, sp++)) { + printk(KERN_NOTICE " (Bad stack address)"); + break; + } + + printk(KERN_NOTICE " %08lx", stackdata); + i++; + } + printk(KERN_NOTICE "\n"); +} + +static void show_trace(long *sp) +{ + int i; + long addr; + + sp = sp ? sp : (long *) &sp; + + printk(KERN_NOTICE "Call Trace: "); + i = 1; + while ((long) sp & (PAGE_SIZE - 1)) { + if (__get_user(addr, sp++)) { + if (i && ((i % 6) == 0)) + printk(KERN_NOTICE "\n"); + printk(KERN_NOTICE " (Bad stack address)\n"); + break; + } + + if (kernel_text_address(addr)) { + if (i && ((i % 6) == 0)) + printk(KERN_NOTICE "\n"); + if (i > 40) { + printk(KERN_NOTICE " ..."); + break; + } + + printk(KERN_NOTICE " [<%08lx>]", addr); + i++; + } + } + printk(KERN_NOTICE "\n"); +} + +static void show_code(unsigned int *pc) +{ + long i; + + printk(KERN_NOTICE "\nCode:"); + + for (i = -3; i < 6; i++) { + unsigned long insn; + if (__get_user(insn, pc + i)) { + printk(KERN_NOTICE " (Bad address in epc)\n"); + break; + } + printk(KERN_NOTICE "%c%08lx%c", (i ? ' ' : '<'), + insn, (i ? ' ' : '>')); + } +} + +/* + * FIXME: really the generic show_regs should take a const pointer argument. + */ +void show_regs(struct pt_regs *regs) +{ + printk("r0 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + regs->regs[0], regs->regs[1], regs->regs[2], regs->regs[3], + regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); + printk("r8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11], + regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]); + printk("r16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19], + regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]); + printk("r24: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + regs->regs[24], regs->regs[25], regs->regs[26], regs->regs[27], + regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]); + + printk("CEH : %08lx\n", regs->ceh); + printk("CEL : %08lx\n", regs->cel); + + printk("EMA:%08lx, epc:%08lx %s\nPSR: %08lx\nECR:%08lx\nCondition : %08lx\n", + regs->cp0_ema, regs->cp0_epc, print_tainted(), regs->cp0_psr, + regs->cp0_ecr, regs->cp0_condition); +} + +static void show_registers(struct pt_regs *regs) +{ + show_regs(regs); + printk(KERN_NOTICE "Process %s (pid: %d, stackpage=%08lx)\n", + current->comm, current->pid, (unsigned long) current); + show_stack(current_thread_info()->task, (long *) regs->regs[0]); + show_trace((long *) regs->regs[0]); + show_code((unsigned int *) regs->cp0_epc); + printk(KERN_NOTICE "\n"); +} + +/* + * The architecture-independent dump_stack generator + */ +void dump_stack(void) +{ + show_stack(current_thread_info()->task, + (long *) get_irq_regs()->regs[0]); +} +EXPORT_SYMBOL(dump_stack); + +void __die(const char *str, struct pt_regs *regs, const char *file, + const char *func, unsigned long line) +{ + console_verbose(); + printk("%s", str); + if (file && func) + printk(" in %s:%s, line %ld", file, func, line); + printk(":\n"); + show_registers(regs); + do_exit(SIGSEGV); +} + +void __die_if_kernel(const char *str, struct pt_regs *regs, + const char *file, const char *func, unsigned long line) +{ + if (!user_mode(regs)) + __die(str, regs, file, func, line); +} + +asmlinkage void do_adelinsn(struct pt_regs *regs) +{ + printk("do_ADE-linsn:ema:0x%08lx:epc:0x%08lx\n", + regs->cp0_ema, regs->cp0_epc); + die_if_kernel("do_ade execution Exception\n", regs); + force_sig(SIGBUS, current); +} + +asmlinkage void do_adedata(struct pt_regs *regs) +{ + const struct exception_table_entry *fixup; + fixup = search_exception_tables(regs->cp0_epc); + if (fixup) { + regs->cp0_epc = fixup->fixup; + return; + } + printk("do_ADE-data:ema:0x%08lx:epc:0x%08lx\n", + regs->cp0_ema, regs->cp0_epc); + die_if_kernel("do_ade execution Exception\n", regs); + force_sig(SIGBUS, current); +} + +asmlinkage void do_pel(struct pt_regs *regs) +{ + die_if_kernel("do_pel execution Exception", regs); + force_sig(SIGFPE, current); +} + +asmlinkage void do_cee(struct pt_regs *regs) +{ + die_if_kernel("do_cee execution Exception", regs); + force_sig(SIGFPE, current); +} + +asmlinkage void do_cpe(struct pt_regs *regs) +{ + die_if_kernel("do_cpe execution Exception", regs); + force_sig(SIGFPE, current); +} + +asmlinkage void do_be(struct pt_regs *regs) +{ + die_if_kernel("do_be execution Exception", regs); + force_sig(SIGBUS, current); +} + +asmlinkage void do_ov(struct pt_regs *regs) +{ + siginfo_t info; + + die_if_kernel("do_ov execution Exception", regs); + + info.si_code = FPE_INTOVF; + info.si_signo = SIGFPE; + info.si_errno = 0; + info.si_addr = (void *)regs->cp0_epc; + force_sig_info(SIGFPE, &info, current); +} + +asmlinkage void do_tr(struct pt_regs *regs) +{ + die_if_kernel("do_tr execution Exception", regs); + force_sig(SIGTRAP, current); +} + +asmlinkage void do_ri(struct pt_regs *regs) +{ + unsigned long epc_insn; + unsigned long epc = regs->cp0_epc; + + read_tsk_long(current, epc, &epc_insn); + if (current->thread.single_step == 1) { + if ((epc == current->thread.addr1) || + (epc == current->thread.addr2)) { + user_disable_single_step(current); + force_sig(SIGTRAP, current); + return; + } else + BUG(); + } else if ((epc_insn == BREAKPOINT32_INSN) || + ((epc_insn & 0x0000FFFF) == 0x7002) || + ((epc_insn & 0xFFFF0000) == 0x70020000)) { + force_sig(SIGTRAP, current); + return; + } else { + die_if_kernel("do_ri execution Exception", regs); + force_sig(SIGILL, current); + } +} + +asmlinkage void do_ccu(struct pt_regs *regs) +{ + die_if_kernel("do_ccu execution Exception", regs); + force_sig(SIGILL, current); +} + +asmlinkage void do_reserved(struct pt_regs *regs) +{ + /* + * Game over - no way to handle this if it ever occurs. Most probably + * caused by a new unknown cpu type or after another deadly + * hard/software error. + */ + die_if_kernel("do_reserved execution Exception", regs); + show_regs(regs); + panic("Caught reserved exception - should not happen."); +} + +/* + * NMI exception handler. + */ +void nmi_exception_handler(struct pt_regs *regs) +{ + die_if_kernel("nmi_exception_handler execution Exception", regs); + die("NMI", regs); +} + +/* Install CPU exception handler */ +void *set_except_vector(int n, void *addr) +{ + unsigned long handler = (unsigned long) addr; + unsigned long old_handler = exception_handlers[n]; + + exception_handlers[n] = handler; + return (void *)old_handler; +} + +void __init trap_init(void) +{ + int i; + + pgd_current = (unsigned long)init_mm.pgd; + /* DEBUG EXCEPTION */ + memcpy((void *)DEBUG_VECTOR_BASE_ADDR, + &debug_exception_vector, DEBUG_VECTOR_SIZE); + /* NMI EXCEPTION */ + memcpy((void *)GENERAL_VECTOR_BASE_ADDR, + &general_exception_vector, GENERAL_VECTOR_SIZE); + + /* + * Initialise exception handlers + */ + for (i = 0; i <= 31; i++) + set_except_vector(i, handle_reserved); + + set_except_vector(1, handle_nmi); + set_except_vector(2, handle_adelinsn); + set_except_vector(3, handle_tlb_refill); + set_except_vector(4, handle_tlb_invaild); + set_except_vector(5, handle_ibe); + set_except_vector(6, handle_pel); + set_except_vector(7, handle_sys); + set_except_vector(8, handle_ccu); + set_except_vector(9, handle_ri); + set_except_vector(10, handle_tr); + set_except_vector(11, handle_adedata); + set_except_vector(12, handle_adedata); + set_except_vector(13, handle_tlb_refill); + set_except_vector(14, handle_tlb_invaild); + set_except_vector(15, handle_mod); + set_except_vector(16, handle_cee); + set_except_vector(17, handle_cpe); + set_except_vector(18, handle_dbe); + flush_icache_range(DEBUG_VECTOR_BASE_ADDR, IRQ_VECTOR_BASE_ADDR); + + atomic_inc(&init_mm.mm_count); + current->active_mm = &init_mm; + cpu_cache_init(); +} diff --git a/arch/score/kernel/vmlinux.lds.S b/arch/score/kernel/vmlinux.lds.S new file mode 100644 index 000000000000..f85569831d5c --- /dev/null +++ b/arch/score/kernel/vmlinux.lds.S @@ -0,0 +1,148 @@ +/* + * arch/score/kernel/vmlinux.lds.S + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <asm-generic/vmlinux.lds.h> + +OUTPUT_ARCH(score) +ENTRY(_stext) + +jiffies = jiffies_64; + +SECTIONS +{ + . = CONFIG_MEMORY_START + 0x2000; + /* read-only */ + .text : { + _text = .; /* Text and read-only data */ + TEXT_TEXT + SCHED_TEXT + LOCK_TEXT + KPROBES_TEXT + *(.text.*) + *(.fixup) + . = ALIGN (4) ; + _etext = .; /* End of text section */ + } + + . = ALIGN(16); + RODATA + + /* Exception table */ + . = ALIGN(16); + __ex_table : { + __start___ex_table = .; + *(__ex_table) + __stop___ex_table = .; + } + + /* writeable */ + .data ALIGN (4096): { + *(.data.init_task) + + DATA_DATA + CONSTRUCTORS + } + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + . = ALIGN(8); + .sdata : { + *(.sdata) + } + + . = ALIGN(32); + .data.cacheline_aligned : { + *(.data.cacheline_aligned) + } + _edata = .; /* End of data section */ + + /* will be freed after init */ + . = ALIGN(4096); /* Init code and data */ + __init_begin = .; + + . = ALIGN(4096); + .init.text : { + _sinittext = .; + INIT_TEXT + _einittext = .; + } + .init.data : { + INIT_DATA + } + . = ALIGN(16); + .init.setup : { + __setup_start = .; + *(.init.setup) + __setup_end = .; + } + + .initcall.init : { + __initcall_start = .; + INITCALLS + __initcall_end = .; + } + + .con_initcall.init : { + __con_initcall_start = .; + *(.con_initcall.init) + __con_initcall_end = .; + } + SECURITY_INIT + + /* .exit.text is discarded at runtime, not link time, to deal with + * references from .rodata + */ + .exit.text : { + EXIT_TEXT + } + .exit.data : { + EXIT_DATA + } +#if defined(CONFIG_BLK_DEV_INITRD) + .init.ramfs ALIGN(4096): { + __initramfs_start = .; + *(.init.ramfs) + __initramfs_end = .; + . = ALIGN(4); + LONG(0); + } +#endif + . = ALIGN(4096); + __init_end = .; + /* freed after init ends here */ + + __bss_start = .; /* BSS */ + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + __bss_stop = .; + _end = .; +} diff --git a/arch/score/lib/Makefile b/arch/score/lib/Makefile new file mode 100644 index 000000000000..553e30e81faf --- /dev/null +++ b/arch/score/lib/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for SCORE-specific library files.. +# + +lib-y += string.o checksum.o checksum_copy.o + +# libgcc-style stuff needed in the kernel +obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/arch/score/lib/ashldi3.c b/arch/score/lib/ashldi3.c new file mode 100644 index 000000000000..15691a910431 --- /dev/null +++ b/arch/score/lib/ashldi3.c @@ -0,0 +1,46 @@ +/* + * arch/score/lib/ashldi3.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/module.h> +#include "libgcc.h" + +long long __ashldi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.low = 0; + w.s.high = (unsigned int) uu.s.low << -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.low >> bm; + + w.s.low = (unsigned int) uu.s.low << b; + w.s.high = ((unsigned int) uu.s.high << b) | carries; + } + + return w.ll; +} +EXPORT_SYMBOL(__ashldi3); diff --git a/arch/score/lib/ashrdi3.c b/arch/score/lib/ashrdi3.c new file mode 100644 index 000000000000..d9814a5d8d30 --- /dev/null +++ b/arch/score/lib/ashrdi3.c @@ -0,0 +1,48 @@ +/* + * arch/score/lib/ashrdi3.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/module.h> +#include "libgcc.h" + +long long __ashrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + /* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >> 31; + w.s.low = uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} +EXPORT_SYMBOL(__ashrdi3); diff --git a/arch/score/lib/checksum.S b/arch/score/lib/checksum.S new file mode 100644 index 000000000000..706157edc7d5 --- /dev/null +++ b/arch/score/lib/checksum.S @@ -0,0 +1,255 @@ +/* + * arch/score/lib/csum_partial.S + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Lennox Wu <lennox.wu@sunplusct.com> + * Chen Liqin <liqin.chen@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/linkage.h> + +#define ADDC(sum,reg) \ + add sum, sum, reg; \ + cmp.c reg, sum; \ + bleu 9f; \ + addi sum, 0x1; \ +9: + +#define CSUM_BIGCHUNK(src, offset, sum) \ + lw r8, [src, offset + 0x00]; \ + lw r9, [src, offset + 0x04]; \ + lw r10, [src, offset + 0x08]; \ + lw r11, [src, offset + 0x0c]; \ + ADDC(sum, r8); \ + ADDC(sum, r9); \ + ADDC(sum, r10); \ + ADDC(sum, r11); \ + lw r8, [src, offset + 0x10]; \ + lw r9, [src, offset + 0x14]; \ + lw r10, [src, offset + 0x18]; \ + lw r11, [src, offset + 0x1c]; \ + ADDC(sum, r8); \ + ADDC(sum, r9); \ + ADDC(sum, r10); \ + ADDC(sum, r11); \ + +#define src r4 +#define dest r5 +#define sum r27 + + .text +/* unknown src alignment and < 8 bytes to go */ +small_csumcpy: + mv r5, r10 + ldi r9, 0x0 + cmpi.c r25, 0x1 + beq pass_small_set_t7 /*already set, jump to pass_small_set_t7*/ + andri.c r25,r4 , 0x1 /*Is src 2 bytes aligned?*/ + +pass_small_set_t7: + beq aligned + cmpi.c r5, 0x0 + beq fold + lbu r9, [src] + slli r9,r9, 0x8 /*Little endian*/ + ADDC(sum, r9) + addi src, 0x1 + subi.c r5, 0x1 + + /*len still a full word */ +aligned: + andri.c r8, r5, 0x4 /*Len >= 4?*/ + beq len_less_4bytes + + /* Still a full word (4byte) to go,and the src is word aligned.*/ + andri.c r8, src, 0x3 /*src is 4bytes aligned, so use LW!!*/ + beq four_byte_aligned + lhu r9, [src] + addi src, 2 + ADDC(sum, r9) + lhu r9, [src] + addi src, 2 + ADDC(sum, r9) + b len_less_4bytes + +four_byte_aligned: /* Len >=4 and four byte aligned */ + lw r9, [src] + addi src, 4 + ADDC(sum, r9) + +len_less_4bytes: /* 2 byte aligned aligned and length<4B */ + andri.c r8, r5, 0x2 + beq len_less_2bytes + lhu r9, [src] + addi src, 0x2 /* src+=2 */ + ADDC(sum, r9) + +len_less_2bytes: /* len = 1 */ + andri.c r8, r5, 0x1 + beq fold /* less than 2 and not equal 1--> len=0 -> fold */ + lbu r9, [src] + +fold_ADDC: + ADDC(sum, r9) +fold: + /* fold checksum */ + slli r26, sum, 16 + add sum, sum, r26 + cmp.c r26, sum + srli sum, sum, 16 + bleu 1f /* if r26<=sum */ + addi sum, 0x1 /* r26>sum */ +1: + /* odd buffer alignment? r25 was set in csum_partial */ + cmpi.c r25, 0x0 + beq 1f + slli r26, sum, 8 + srli sum, sum, 8 + or sum, sum, r26 + andi sum, 0xffff +1: + .set optimize + /* Add the passed partial csum. */ + ADDC(sum, r6) + mv r4, sum + br r3 + .set volatile + + .align 5 +ENTRY(csum_partial) + ldi sum, 0 + ldi r25, 0 + mv r10, r5 + cmpi.c r5, 0x8 + blt small_csumcpy /* < 8(singed) bytes to copy */ + cmpi.c r5, 0x0 + beq out + andri.c r25, src, 0x1 /* odd buffer? */ + + beq word_align +hword_align: /* 1 byte */ + lbu r8, [src] + subi r5, 0x1 + slli r8, r8, 8 + ADDC(sum, r8) + addi src, 0x1 + +word_align: /* 2 bytes */ + andri.c r8, src, 0x2 /* 4bytes(dword)_aligned? */ + beq dword_align /* not, maybe dword_align */ + lhu r8, [src] + subi r5, 0x2 + ADDC(sum, r8) + addi src, 0x2 + +dword_align: /* 4bytes */ + mv r26, r5 /* maybe useless when len >=56 */ + ldi r8, 56 + cmp.c r8, r5 + bgtu do_end_words /* if a1(len)<t0(56) ,unsigned */ + andri.c r26, src, 0x4 + beq qword_align + lw r8, [src] + subi r5, 0x4 + ADDC(sum, r8) + addi src, 0x4 + +qword_align: /* 8 bytes */ + andri.c r26, src, 0x8 + beq oword_align + lw r8, [src, 0x0] + lw r9, [src, 0x4] + subi r5, 0x8 /* len-=0x8 */ + ADDC(sum, r8) + ADDC(sum, r9) + addi src, 0x8 + +oword_align: /* 16bytes */ + andri.c r26, src, 0x10 + beq begin_movement + lw r10, [src, 0x08] + lw r11, [src, 0x0c] + lw r8, [src, 0x00] + lw r9, [src, 0x04] + ADDC(sum, r10) + ADDC(sum, r11) + ADDC(sum, r8) + ADDC(sum, r9) + subi r5, 0x10 + addi src, 0x10 + +begin_movement: + srli.c r26, r5, 0x7 /* len>=128? */ + beq 1f /* len<128 */ + +/* r26 is the result that computed in oword_align */ +move_128bytes: + CSUM_BIGCHUNK(src, 0x00, sum) + CSUM_BIGCHUNK(src, 0x20, sum) + CSUM_BIGCHUNK(src, 0x40, sum) + CSUM_BIGCHUNK(src, 0x60, sum) + subi.c r26, 0x01 /* r26 equals len/128 */ + addi src, 0x80 + bne move_128bytes + +1: /* len<128,we process 64byte here */ + andri.c r10, r5, 0x40 + beq 1f + +move_64bytes: + CSUM_BIGCHUNK(src, 0x00, sum) + CSUM_BIGCHUNK(src, 0x20, sum) + addi src, 0x40 + +1: /* len<64 */ + andri r26, r5, 0x1c /* 0x1c=28 */ + andri.c r10, r5, 0x20 + beq do_end_words /* decided by andri */ + +move_32bytes: + CSUM_BIGCHUNK(src, 0x00, sum) + andri r26, r5, 0x1c + addri src, src, 0x20 + +do_end_words: /* len<32 */ + /* r26 was set already in dword_align */ + cmpi.c r26, 0x0 + beq maybe_end_cruft /* len<28 or len<56 */ + srli r26, r26, 0x2 + +end_words: + lw r8, [src] + subi.c r26, 0x1 /* unit is 4 byte */ + ADDC(sum, r8) + addi src, 0x4 + cmpi.c r26, 0x0 + bne end_words /* r26!=0 */ + +maybe_end_cruft: /* len<4 */ + andri r10, r5, 0x3 + +small_memcpy: + mv r5, r10 + j small_csumcpy + +out: + mv r4, sum + br r3 + +END(csum_partial) diff --git a/arch/score/lib/checksum_copy.c b/arch/score/lib/checksum_copy.c new file mode 100644 index 000000000000..04565dd3ded8 --- /dev/null +++ b/arch/score/lib/checksum_copy.c @@ -0,0 +1,52 @@ +/* + * arch/score/lib/csum_partial_copy.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Lennox Wu <lennox.wu@sunplusct.com> + * Chen Liqin <liqin.chen@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <net/checksum.h> + +#include <asm/uaccess.h> + +unsigned int csum_partial_copy(const char *src, char *dst, + int len, unsigned int sum) +{ + sum = csum_partial(src, len, sum); + memcpy(dst, src, len); + + return sum; +} + +unsigned int csum_partial_copy_from_user(const char *src, char *dst, + int len, unsigned int sum, + int *err_ptr) +{ + int missing; + + missing = copy_from_user(dst, src, len); + if (missing) { + memset(dst + len - missing, 0, missing); + *err_ptr = -EFAULT; + } + + return csum_partial(dst, len, sum); +} diff --git a/arch/score/lib/cmpdi2.c b/arch/score/lib/cmpdi2.c new file mode 100644 index 000000000000..1ed5290c66ed --- /dev/null +++ b/arch/score/lib/cmpdi2.c @@ -0,0 +1,44 @@ +/* + * arch/score/lib/cmpdi2.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/module.h> +#include "libgcc.h" + +word_type __cmpdi2(long long a, long long b) +{ + const DWunion au = { + .ll = a + }; + const DWunion bu = { + .ll = b + }; + + if (au.s.high < bu.s.high) + return 0; + else if (au.s.high > bu.s.high) + return 2; + + if ((unsigned int) au.s.low < (unsigned int) bu.s.low) + return 0; + else if ((unsigned int) au.s.low > (unsigned int) bu.s.low) + return 2; + + return 1; +} +EXPORT_SYMBOL(__cmpdi2); diff --git a/arch/score/lib/libgcc.h b/arch/score/lib/libgcc.h new file mode 100644 index 000000000000..0f12543d9f31 --- /dev/null +++ b/arch/score/lib/libgcc.h @@ -0,0 +1,37 @@ +/* + * arch/score/lib/libgcc.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__((mode(__word__))); + +struct DWstruct { + int low, high; +}; + +typedef union { + struct DWstruct s; + long long ll; +} DWunion; + +#endif /* __ASM_LIBGCC_H */ diff --git a/arch/score/lib/lshrdi3.c b/arch/score/lib/lshrdi3.c new file mode 100644 index 000000000000..ce21175fd791 --- /dev/null +++ b/arch/score/lib/lshrdi3.c @@ -0,0 +1,47 @@ +/* + * arch/score/lib/lshrdi3.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <linux/module.h> +#include "libgcc.h" + +long long __lshrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.high = 0; + w.s.low = (unsigned int) uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = (unsigned int) uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} +EXPORT_SYMBOL(__lshrdi3); diff --git a/arch/score/lib/string.S b/arch/score/lib/string.S new file mode 100644 index 000000000000..00b7d3a2fc60 --- /dev/null +++ b/arch/score/lib/string.S @@ -0,0 +1,184 @@ +/* + * arch/score/lib/string.S + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Chen Liqin <liqin.chen@sunplusct.com> + * Lennox Wu <lennox.wu@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/linkage.h> +#include <asm-generic/errno.h> + + .text + .align 2 +ENTRY(__strncpy_from_user) + cmpi.c r6, 0 + mv r9, r6 + ble .L2 +0: lbu r7, [r5] + ldi r8, 0 +1: sb r7, [r4] +2: lb r6, [r5] + cmp.c r6, r8 + beq .L2 + +.L5: + addi r8, 1 + cmp.c r8, r9 + beq .L7 +3: lbu r6, [r5, 1]+ +4: sb r6, [r4, 1]+ +5: lb r7, [r5] + cmpi.c r7, 0 + bne .L5 +.L7: + mv r4, r8 + br r3 +.L2: + ldi r8, 0 + mv r4, r8 + br r3 + .section .fixup, "ax" +99: + ldi r4, -EFAULT + br r3 + .previous + .section __ex_table, "a" + .align 2 + .word 0b ,99b + .word 1b ,99b + .word 2b ,99b + .word 3b ,99b + .word 4b ,99b + .word 5b ,99b + .previous + + .align 2 +ENTRY(__strnlen_user) + cmpi.c r5, 0 + ble .L11 +0: lb r6, [r4] + ldi r7, 0 + cmp.c r6, r7 + beq .L11 +.L15: + addi r7, 1 + cmp.c r7, r5 + beq .L23 +1: lb r6, [r4,1]+ + cmpi.c r6, 0 + bne .L15 +.L23: + addri r4, r7, 1 + br r3 + +.L11: + ldi r4, 1 + br r3 + .section .fixup, "ax" +99: + ldi r4, 0 + br r3 + + .section __ex_table,"a" + .align 2 + .word 0b, 99b + .word 1b, 99b + .previous + + .align 2 +ENTRY(__strlen_user) +0: lb r6, [r4] + mv r7, r4 + extsb r6, r6 + cmpi.c r6, 0 + mv r4, r6 + beq .L27 +.L28: +1: lb r6, [r7, 1]+ + addi r6, 1 + cmpi.c r6, 0 + bne .L28 +.L27: + br r3 + .section .fixup, "ax" + ldi r4, 0x0 + br r3 +99: + ldi r4, 0 + br r3 + .previous + .section __ex_table, "a" + .align 2 + .word 0b ,99b + .word 1b ,99b + .previous + + .align 2 +ENTRY(__copy_tofrom_user) + cmpi.c r6, 0 + mv r10,r6 + beq .L32 + ldi r9, 0 +.L34: + add r6, r5, r9 +0: lbu r8, [r6] + add r7, r4, r9 +1: sb r8, [r7] + addi r9, 1 + cmp.c r9, r10 + bne .L34 +.L32: + ldi r4, 0 + br r3 + .section .fixup, "ax" +99: + sub r4, r10, r9 + br r3 + .previous + .section __ex_table, "a" + .align 2 + .word 0b, 99b + .word 1b, 99b + .previous + + .align 2 +ENTRY(__clear_user) + cmpi.c r5, 0 + beq .L38 + ldi r6, 0 + mv r7, r6 +.L40: + addi r6, 1 +0: sb r7, [r4]+, 1 + cmp.c r6, r5 + bne .L40 +.L38: + ldi r4, 0 + br r3 + + .section .fixup, "ax" + br r3 + .previous + .section __ex_table, "a" + .align 2 +99: + .word 0b, 99b + .previous diff --git a/arch/score/lib/ucmpdi2.c b/arch/score/lib/ucmpdi2.c new file mode 100644 index 000000000000..b15241e0b079 --- /dev/null +++ b/arch/score/lib/ucmpdi2.c @@ -0,0 +1,38 @@ +/* + * arch/score/lib/ucmpdi2.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/module.h> +#include "libgcc.h" + +word_type __ucmpdi2(unsigned long long a, unsigned long long b) +{ + const DWunion au = {.ll = a}; + const DWunion bu = {.ll = b}; + + if ((unsigned int) au.s.high < (unsigned int) bu.s.high) + return 0; + else if ((unsigned int) au.s.high > (unsigned int) bu.s.high) + return 2; + if ((unsigned int) au.s.low < (unsigned int) bu.s.low) + return 0; + else if ((unsigned int) au.s.low > (unsigned int) bu.s.low) + return 2; + return 1; +} +EXPORT_SYMBOL(__ucmpdi2); diff --git a/arch/score/mm/Makefile b/arch/score/mm/Makefile new file mode 100644 index 000000000000..7b1e29b1f8cd --- /dev/null +++ b/arch/score/mm/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the Linux/SCORE-specific parts of the memory manager. +# + +obj-y += cache.o extable.o fault.o init.o \ + tlb-miss.o tlb-score.o pgtable.o diff --git a/arch/score/mm/cache.c b/arch/score/mm/cache.c new file mode 100644 index 000000000000..dbac9d9dfddd --- /dev/null +++ b/arch/score/mm/cache.c @@ -0,0 +1,257 @@ +/* + * arch/score/mm/cache.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Lennox Wu <lennox.wu@sunplusct.com> + * Chen Liqin <liqin.chen@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/init.h> +#include <linux/linkage.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/module.h> +#include <linux/sched.h> + +#include <asm/mmu_context.h> + +/* +Just flush entire Dcache!! +You must ensure the page doesn't include instructions, because +the function will not flush the Icache. +The addr must be cache aligned. +*/ +static void flush_data_cache_page(unsigned long addr) +{ + unsigned int i; + for (i = 0; i < (PAGE_SIZE / L1_CACHE_BYTES); i += L1_CACHE_BYTES) { + __asm__ __volatile__( + "cache 0x0e, [%0, 0]\n" + "cache 0x1a, [%0, 0]\n" + "nop\n" + : : "r" (addr)); + addr += L1_CACHE_BYTES; + } +} + +/* called by update_mmu_cache. */ +void __update_cache(struct vm_area_struct *vma, unsigned long address, + pte_t pte) +{ + struct page *page; + unsigned long pfn, addr; + int exec = (vma->vm_flags & VM_EXEC); + + pfn = pte_pfn(pte); + if (unlikely(!pfn_valid(pfn))) + return; + page = pfn_to_page(pfn); + if (page_mapping(page) && test_bit(PG_arch_1, &page->flags)) { + addr = (unsigned long) page_address(page); + if (exec) + flush_data_cache_page(addr); + clear_bit(PG_arch_1, &page->flags); + } +} + +static inline void setup_protection_map(void) +{ + protection_map[0] = PAGE_NONE; + protection_map[1] = PAGE_READONLY; + protection_map[2] = PAGE_COPY; + protection_map[3] = PAGE_COPY; + protection_map[4] = PAGE_READONLY; + protection_map[5] = PAGE_READONLY; + protection_map[6] = PAGE_COPY; + protection_map[7] = PAGE_COPY; + protection_map[8] = PAGE_NONE; + protection_map[9] = PAGE_READONLY; + protection_map[10] = PAGE_SHARED; + protection_map[11] = PAGE_SHARED; + protection_map[12] = PAGE_READONLY; + protection_map[13] = PAGE_READONLY; + protection_map[14] = PAGE_SHARED; + protection_map[15] = PAGE_SHARED; +} + +void __devinit cpu_cache_init(void) +{ + setup_protection_map(); +} + +void flush_icache_all(void) +{ + __asm__ __volatile__( + "la r8, flush_icache_all\n" + "cache 0x10, [r8, 0]\n" + "nop\nnop\nnop\nnop\nnop\nnop\n" + : : : "r8"); +} + +void flush_dcache_all(void) +{ + __asm__ __volatile__( + "la r8, flush_dcache_all\n" + "cache 0x1f, [r8, 0]\n" + "nop\nnop\nnop\nnop\nnop\nnop\n" + "cache 0x1a, [r8, 0]\n" + "nop\nnop\nnop\nnop\nnop\nnop\n" + : : : "r8"); +} + +void flush_cache_all(void) +{ + __asm__ __volatile__( + "la r8, flush_cache_all\n" + "cache 0x10, [r8, 0]\n" + "nop\nnop\nnop\nnop\nnop\nnop\n" + "cache 0x1f, [r8, 0]\n" + "nop\nnop\nnop\nnop\nnop\nnop\n" + "cache 0x1a, [r8, 0]\n" + "nop\nnop\nnop\nnop\nnop\nnop\n" + : : : "r8"); +} + +void flush_cache_mm(struct mm_struct *mm) +{ + if (!(mm->context)) + return; + flush_cache_all(); +} + +/*if we flush a range precisely , the processing may be very long. +We must check each page in the range whether present. If the page is present, +we can flush the range in the page. Be careful, the range may be cross two +page, a page is present and another is not present. +*/ +/* +The interface is provided in hopes that the port can find +a suitably efficient method for removing multiple page +sized regions from the cache. +*/ +void flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + int exec = vma->vm_flags & VM_EXEC; + pgd_t *pgdp; + pud_t *pudp; + pmd_t *pmdp; + pte_t *ptep; + + if (!(mm->context)) + return; + + pgdp = pgd_offset(mm, start); + pudp = pud_offset(pgdp, start); + pmdp = pmd_offset(pudp, start); + ptep = pte_offset(pmdp, start); + + while (start <= end) { + unsigned long tmpend; + pgdp = pgd_offset(mm, start); + pudp = pud_offset(pgdp, start); + pmdp = pmd_offset(pudp, start); + ptep = pte_offset(pmdp, start); + + if (!(pte_val(*ptep) & _PAGE_PRESENT)) { + start = (start + PAGE_SIZE) & ~(PAGE_SIZE - 1); + continue; + } + tmpend = (start | (PAGE_SIZE-1)) > end ? + end : (start | (PAGE_SIZE-1)); + + flush_dcache_range(start, tmpend); + if (exec) + flush_icache_range(start, tmpend); + start = (start + PAGE_SIZE) & ~(PAGE_SIZE - 1); + } +} + +void flush_cache_page(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn) +{ + int exec = vma->vm_flags & VM_EXEC; + unsigned long kaddr = 0xa0000000 | (pfn << PAGE_SHIFT); + + flush_dcache_range(kaddr, kaddr + PAGE_SIZE); + + if (exec) + flush_icache_range(kaddr, kaddr + PAGE_SIZE); +} + +void flush_cache_sigtramp(unsigned long addr) +{ + __asm__ __volatile__( + "cache 0x02, [%0, 0]\n" + "nop\nnop\nnop\nnop\nnop\n" + "cache 0x02, [%0, 0x4]\n" + "nop\nnop\nnop\nnop\nnop\n" + + "cache 0x0d, [%0, 0]\n" + "nop\nnop\nnop\nnop\nnop\n" + "cache 0x0d, [%0, 0x4]\n" + "nop\nnop\nnop\nnop\nnop\n" + + "cache 0x1a, [%0, 0]\n" + "nop\nnop\nnop\nnop\nnop\n" + : : "r" (addr)); +} + +/* +1. WB and invalid a cache line of Dcache +2. Drain Write Buffer +the range must be smaller than PAGE_SIZE +*/ +void flush_dcache_range(unsigned long start, unsigned long end) +{ + int size, i; + + start = start & ~(L1_CACHE_BYTES - 1); + end = end & ~(L1_CACHE_BYTES - 1); + size = end - start; + /* flush dcache to ram, and invalidate dcache lines. */ + for (i = 0; i < size; i += L1_CACHE_BYTES) { + __asm__ __volatile__( + "cache 0x0e, [%0, 0]\n" + "nop\nnop\nnop\nnop\nnop\n" + "cache 0x1a, [%0, 0]\n" + "nop\nnop\nnop\nnop\nnop\n" + : : "r" (start)); + start += L1_CACHE_BYTES; + } +} + +void flush_icache_range(unsigned long start, unsigned long end) +{ + int size, i; + start = start & ~(L1_CACHE_BYTES - 1); + end = end & ~(L1_CACHE_BYTES - 1); + + size = end - start; + /* invalidate icache lines. */ + for (i = 0; i < size; i += L1_CACHE_BYTES) { + __asm__ __volatile__( + "cache 0x02, [%0, 0]\n" + "nop\nnop\nnop\nnop\nnop\n" + : : "r" (start)); + start += L1_CACHE_BYTES; + } +} diff --git a/arch/score/mm/extable.c b/arch/score/mm/extable.c new file mode 100644 index 000000000000..01ff6445171c --- /dev/null +++ b/arch/score/mm/extable.c @@ -0,0 +1,38 @@ +/* + * arch/score/mm/extable.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Lennox Wu <lennox.wu@sunplusct.com> + * Chen Liqin <liqin.chen@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/module.h> + +int fixup_exception(struct pt_regs *regs) +{ + const struct exception_table_entry *fixup; + + fixup = search_exception_tables(regs->cp0_epc); + if (fixup) { + regs->cp0_epc = fixup->fixup; + return 1; + } + return 0; +} diff --git a/arch/score/mm/fault.c b/arch/score/mm/fault.c new file mode 100644 index 000000000000..47b600e4b2c5 --- /dev/null +++ b/arch/score/mm/fault.c @@ -0,0 +1,235 @@ +/* + * arch/score/mm/fault.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Lennox Wu <lennox.wu@sunplusct.com> + * Chen Liqin <liqin.chen@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/mman.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/string.h> +#include <linux/types.h> +#include <linux/ptrace.h> + +/* + * This routine handles page faults. It determines the address, + * and the problem, and then passes it off to one of the appropriate + * routines. + */ +asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, + unsigned long address) +{ + struct vm_area_struct *vma = NULL; + struct task_struct *tsk = current; + struct mm_struct *mm = tsk->mm; + const int field = sizeof(unsigned long) * 2; + siginfo_t info; + int fault; + + info.si_code = SEGV_MAPERR; + + /* + * We fault-in kernel-space virtual memory on-demand. The + * 'reference' page table is init_mm.pgd. + * + * NOTE! We MUST NOT take any locks for this case. We may + * be in an interrupt or a critical region, and should + * only copy the information from the master page table, + * nothing more. + */ + if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END)) + goto vmalloc_fault; +#ifdef MODULE_START + if (unlikely(address >= MODULE_START && address < MODULE_END)) + goto vmalloc_fault; +#endif + + /* + * If we're in an interrupt or have no user + * context, we must not take the fault.. + */ + if (in_atomic() || !mm) + goto bad_area_nosemaphore; + + down_read(&mm->mmap_sem); + vma = find_vma(mm, address); + if (!vma) + goto bad_area; + if (vma->vm_start <= address) + goto good_area; + if (!(vma->vm_flags & VM_GROWSDOWN)) + goto bad_area; + if (expand_stack(vma, address)) + goto bad_area; + /* + * Ok, we have a good vm_area for this memory access, so + * we can handle it.. + */ +good_area: + info.si_code = SEGV_ACCERR; + + if (write) { + if (!(vma->vm_flags & VM_WRITE)) + goto bad_area; + } else { + if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC))) + goto bad_area; + } + +survive: + /* + * If for any reason at all we couldn't handle the fault, + * make sure we exit gracefully rather than endlessly redo + * the fault. + */ + fault = handle_mm_fault(mm, vma, address, write); + if (unlikely(fault & VM_FAULT_ERROR)) { + if (fault & VM_FAULT_OOM) + goto out_of_memory; + else if (fault & VM_FAULT_SIGBUS) + goto do_sigbus; + BUG(); + } + if (fault & VM_FAULT_MAJOR) + tsk->maj_flt++; + else + tsk->min_flt++; + + up_read(&mm->mmap_sem); + return; + + /* + * Something tried to access memory that isn't in our memory map.. + * Fix it, but check if it's kernel or user first.. + */ +bad_area: + up_read(&mm->mmap_sem); + +bad_area_nosemaphore: + /* User mode accesses just cause a SIGSEGV */ + if (user_mode(regs)) { + tsk->thread.cp0_badvaddr = address; + tsk->thread.error_code = write; + info.si_signo = SIGSEGV; + info.si_errno = 0; + /* info.si_code has been set above */ + info.si_addr = (void __user *) address; + force_sig_info(SIGSEGV, &info, tsk); + return; + } + +no_context: + /* Are we prepared to handle this kernel fault? */ + if (fixup_exception(regs)) { + current->thread.cp0_baduaddr = address; + return; + } + + /* + * Oops. The kernel tried to access some bad page. We'll have to + * terminate things with extreme prejudice. + */ + bust_spinlocks(1); + + printk(KERN_ALERT "CPU %d Unable to handle kernel paging request at " + "virtual address %0*lx, epc == %0*lx, ra == %0*lx\n", + 0, field, address, field, regs->cp0_epc, + field, regs->regs[3]); + die("Oops", regs); + + /* + * We ran out of memory, or some other thing happened to us that made + * us unable to handle the page fault gracefully. + */ +out_of_memory: + up_read(&mm->mmap_sem); + if (is_global_init(tsk)) { + yield(); + down_read(&mm->mmap_sem); + goto survive; + } + printk("VM: killing process %s\n", tsk->comm); + if (user_mode(regs)) + do_group_exit(SIGKILL); + goto no_context; + +do_sigbus: + up_read(&mm->mmap_sem); + /* Kernel mode? Handle exceptions or die */ + if (!user_mode(regs)) + goto no_context; + else + /* + * Send a sigbus, regardless of whether we were in kernel + * or user mode. + */ + tsk->thread.cp0_badvaddr = address; + info.si_signo = SIGBUS; + info.si_errno = 0; + info.si_code = BUS_ADRERR; + info.si_addr = (void __user *) address; + force_sig_info(SIGBUS, &info, tsk); + return; +vmalloc_fault: + { + /* + * Synchronize this task's top level page-table + * with the 'reference' page table. + * + * Do _not_ use "tsk" here. We might be inside + * an interrupt in the middle of a task switch.. + */ + int offset = __pgd_offset(address); + pgd_t *pgd, *pgd_k; + pud_t *pud, *pud_k; + pmd_t *pmd, *pmd_k; + pte_t *pte_k; + + pgd = (pgd_t *) pgd_current + offset; + pgd_k = init_mm.pgd + offset; + + if (!pgd_present(*pgd_k)) + goto no_context; + set_pgd(pgd, *pgd_k); + + pud = pud_offset(pgd, address); + pud_k = pud_offset(pgd_k, address); + if (!pud_present(*pud_k)) + goto no_context; + + pmd = pmd_offset(pud, address); + pmd_k = pmd_offset(pud_k, address); + if (!pmd_present(*pmd_k)) + goto no_context; + set_pmd(pmd, *pmd_k); + + pte_k = pte_offset_kernel(pmd_k, address); + if (!pte_present(*pte_k)) + goto no_context; + return; + } +} diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c new file mode 100644 index 000000000000..4e3dcd0c4716 --- /dev/null +++ b/arch/score/mm/init.c @@ -0,0 +1,161 @@ +/* + * arch/score/mm/init.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Lennox Wu <lennox.wu@sunplusct.com> + * Chen Liqin <liqin.chen@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/errno.h> +#include <linux/bootmem.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/mman.h> +#include <linux/pagemap.h> +#include <linux/proc_fs.h> +#include <linux/sched.h> +#include <linux/initrd.h> + +#include <asm/sections.h> +#include <asm/tlb.h> + +DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); + +unsigned long empty_zero_page; +EXPORT_SYMBOL_GPL(empty_zero_page); + +static struct kcore_list kcore_mem, kcore_vmalloc; + +static unsigned long setup_zero_page(void) +{ + struct page *page; + + empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, 0); + if (!empty_zero_page) + panic("Oh boy, that early out of memory?"); + + page = virt_to_page((void *) empty_zero_page); + SetPageReserved(page); + + return 1UL; +} + +#ifndef CONFIG_NEED_MULTIPLE_NODES +static int __init page_is_ram(unsigned long pagenr) +{ + if (pagenr >= min_low_pfn && pagenr < max_low_pfn) + return 1; + else + return 0; +} + +void __init paging_init(void) +{ + unsigned long max_zone_pfns[MAX_NR_ZONES]; + unsigned long lastpfn; + + pagetable_init(); + max_zone_pfns[ZONE_NORMAL] = max_low_pfn; + lastpfn = max_low_pfn; + free_area_init_nodes(max_zone_pfns); +} + +void __init mem_init(void) +{ + unsigned long codesize, reservedpages, datasize, initsize; + unsigned long tmp, ram = 0; + + max_mapnr = max_low_pfn; + high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT); + totalram_pages += free_all_bootmem(); + totalram_pages -= setup_zero_page(); /* Setup zeroed pages. */ + reservedpages = 0; + + for (tmp = 0; tmp < max_low_pfn; tmp++) + if (page_is_ram(tmp)) { + ram++; + if (PageReserved(pfn_to_page(tmp))) + reservedpages++; + } + + num_physpages = ram; + codesize = (unsigned long) &_etext - (unsigned long) &_text; + datasize = (unsigned long) &_edata - (unsigned long) &_etext; + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin; + + kclist_add(&kcore_mem, __va(0), max_low_pfn << PAGE_SHIFT); + kclist_add(&kcore_vmalloc, (void *) VMALLOC_START, + VMALLOC_END - VMALLOC_START); + + printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, " + "%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n", + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), + ram << (PAGE_SHIFT-10), codesize >> 10, + reservedpages << (PAGE_SHIFT-10), datasize >> 10, + initsize >> 10, + (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); +} +#endif /* !CONFIG_NEED_MULTIPLE_NODES */ + +static void free_init_pages(const char *what, unsigned long begin, unsigned long end) +{ + unsigned long pfn; + + for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) { + struct page *page = pfn_to_page(pfn); + void *addr = phys_to_virt(PFN_PHYS(pfn)); + + ClearPageReserved(page); + init_page_count(page); + memset(addr, POISON_FREE_INITMEM, PAGE_SIZE); + __free_page(page); + totalram_pages++; + } + printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10); +} + +#ifdef CONFIG_BLK_DEV_INITRD +void free_initrd_mem(unsigned long start, unsigned long end) +{ + free_init_pages("initrd memory", + virt_to_phys((void *) start), + virt_to_phys((void *) end)); +} +#endif + +void __init_refok free_initmem(void) +{ + free_init_pages("unused kernel memory", + __pa(&__init_begin), + __pa(&__init_end)); +} + +unsigned long pgd_current; + +#define __page_aligned(order) __attribute__((__aligned__(PAGE_SIZE<<order))) + +/* + * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER + * are constants. So we use the variants from asm-offset.h until that gcc + * will officially be retired. + */ +pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned(PTE_ORDER); +pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned(PTE_ORDER); diff --git a/arch/score/mm/pgtable.c b/arch/score/mm/pgtable.c new file mode 100644 index 000000000000..6408bb73d3cc --- /dev/null +++ b/arch/score/mm/pgtable.c @@ -0,0 +1,52 @@ +/* + * arch/score/mm/pgtable-32.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Lennox Wu <lennox.wu@sunplusct.com> + * Chen Liqin <liqin.chen@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/bootmem.h> +#include <linux/init.h> +#include <linux/pfn.h> +#include <linux/mm.h> + +void pgd_init(unsigned long page) +{ + unsigned long *p = (unsigned long *) page; + int i; + + for (i = 0; i < USER_PTRS_PER_PGD; i += 8) { + p[i + 0] = (unsigned long) invalid_pte_table; + p[i + 1] = (unsigned long) invalid_pte_table; + p[i + 2] = (unsigned long) invalid_pte_table; + p[i + 3] = (unsigned long) invalid_pte_table; + p[i + 4] = (unsigned long) invalid_pte_table; + p[i + 5] = (unsigned long) invalid_pte_table; + p[i + 6] = (unsigned long) invalid_pte_table; + p[i + 7] = (unsigned long) invalid_pte_table; + } +} + +void __init pagetable_init(void) +{ + /* Initialize the entire pgd. */ + pgd_init((unsigned long)swapper_pg_dir); +} diff --git a/arch/score/mm/tlb-miss.S b/arch/score/mm/tlb-miss.S new file mode 100644 index 000000000000..f27651914e8d --- /dev/null +++ b/arch/score/mm/tlb-miss.S @@ -0,0 +1,199 @@ +/* + * arch/score/mm/tlbex.S + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Lennox Wu <lennox.wu@sunplusct.com> + * Chen Liqin <liqin.chen@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <asm/asmmacro.h> +#include <asm/pgtable-bits.h> +#include <asm/scoreregs.h> + +/* +* After this macro runs, the pte faulted on is +* in register PTE, a ptr into the table in which +* the pte belongs is in PTR. +*/ + .macro load_pte, pte, ptr + la \ptr, pgd_current + lw \ptr, [\ptr, 0] + mfcr \pte, cr6 + srli \pte, \pte, 22 + slli \pte, \pte, 2 + add \ptr, \ptr, \pte + lw \ptr, [\ptr, 0] + mfcr \pte, cr6 + srli \pte, \pte, 10 + andi \pte, 0xffc + add \ptr, \ptr, \pte + lw \pte, [\ptr, 0] + .endm + + .macro pte_reload, ptr + lw \ptr, [\ptr, 0] + mtcr \ptr, cr12 + nop + nop + nop + nop + nop + .endm + + .macro do_fault, write + SAVE_ALL + mfcr r6, cr6 + mv r4, r0 + ldi r5, \write + la r8, do_page_fault + brl r8 + j ret_from_exception + .endm + + .macro pte_writable, pte, ptr, label + andi \pte, 0x280 + cmpi.c \pte, 0x280 + bne \label + lw \pte, [\ptr, 0] /*reload PTE*/ + .endm + +/* + * Make PTE writable, update software status bits as well, + * then store at PTR. + */ + .macro pte_makewrite, pte, ptr + ori \pte, 0x426 + sw \pte, [\ptr, 0] + .endm + + .text +ENTRY(score7_FTLB_refill_Handler) + la r31, pgd_current /* get pgd pointer */ + lw r31, [r31, 0] /* get the address of PGD */ + mfcr r30, cr6 + srli r30, r30, 22 /* PGDIR_SHIFT = 22*/ + slli r30, r30, 2 + add r31, r31, r30 + lw r31, [r31, 0] /* get the address of the start address of PTE table */ + + mfcr r30, cr9 + andi r30, 0xfff /* equivalent to get PET index and right shift 2 bits */ + add r31, r31, r30 + lw r30, [r31, 0] /* load pte entry */ + mtcr r30, cr12 + nop + nop + nop + nop + nop + mtrtlb + nop + nop + nop + nop + nop + rte /* 6 cycles to make sure tlb entry works */ + +ENTRY(score7_KSEG_refill_Handler) + la r31, pgd_current /* get pgd pointer */ + lw r31, [r31, 0] /* get the address of PGD */ + mfcr r30, cr6 + srli r30, r30, 22 /* PGDIR_SHIFT = 22 */ + slli r30, r30, 2 + add r31, r31, r30 + lw r31, [r31, 0] /* get the address of the start address of PTE table */ + + mfcr r30, cr6 /* get Bad VPN */ + srli r30, r30, 10 + andi r30, 0xffc /* PTE VPN mask (bit 11~2) */ + + add r31, r31, r30 + lw r30, [r31, 0] /* load pte entry */ + mtcr r30, cr12 + nop + nop + nop + nop + nop + mtrtlb + nop + nop + nop + nop + nop + rte /* 6 cycles to make sure tlb entry works */ + +nopage_tlbl: + do_fault 0 /* Read */ + +ENTRY(handle_tlb_refill) + load_pte r30, r31 + pte_writable r30, r31, handle_tlb_refill_nopage + pte_makewrite r30, r31 /* Access|Modify|Dirty|Valid */ + pte_reload r31 + mtrtlb + nop + nop + nop + nop + nop + rte +handle_tlb_refill_nopage: + do_fault 0 /* Read */ + +ENTRY(handle_tlb_invaild) + load_pte r30, r31 + stlb /* find faulting entry */ + pte_writable r30, r31, handle_tlb_invaild_nopage + pte_makewrite r30, r31 /* Access|Modify|Dirty|Valid */ + pte_reload r31 + mtptlb + nop + nop + nop + nop + nop + rte +handle_tlb_invaild_nopage: + do_fault 0 /* Read */ + +ENTRY(handle_mod) + load_pte r30, r31 + stlb /* find faulting entry */ + andi r30, _PAGE_WRITE /* Writable? */ + cmpz.c r30 + beq nowrite_mod + lw r30, [r31, 0] /* reload into r30 */ + + /* Present and writable bits set, set accessed and dirty bits. */ + pte_makewrite r30, r31 + + /* Now reload the entry into the tlb. */ + pte_reload r31 + mtptlb + nop + nop + nop + nop + nop + rte + +nowrite_mod: + do_fault 1 /* Write */ diff --git a/arch/score/mm/tlb-score.c b/arch/score/mm/tlb-score.c new file mode 100644 index 000000000000..4fa5aa5afecc --- /dev/null +++ b/arch/score/mm/tlb-score.c @@ -0,0 +1,251 @@ +/* + * arch/score/mm/tlb-score.c + * + * Score Processor version. + * + * Copyright (C) 2009 Sunplus Core Technology Co., Ltd. + * Lennox Wu <lennox.wu@sunplusct.com> + * Chen Liqin <liqin.chen@sunplusct.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/highmem.h> +#include <linux/module.h> + +#include <asm/irq.h> +#include <asm/mmu_context.h> +#include <asm/tlb.h> + +#define TLBSIZE 32 + +unsigned long asid_cache = ASID_FIRST_VERSION; +EXPORT_SYMBOL(asid_cache); + +void local_flush_tlb_all(void) +{ + unsigned long flags; + unsigned long old_ASID; + int entry; + + local_irq_save(flags); + old_ASID = pevn_get() & ASID_MASK; + pectx_set(0); /* invalid */ + entry = tlblock_get(); /* skip locked entries*/ + + for (; entry < TLBSIZE; entry++) { + tlbpt_set(entry); + pevn_set(KSEG1); + barrier(); + tlb_write_indexed(); + } + pevn_set(old_ASID); + local_irq_restore(flags); +} + +/* + * If mm is currently active_mm, we can't really drop it. Instead, + * we will get a new one for it. + */ +static inline void +drop_mmu_context(struct mm_struct *mm) +{ + unsigned long flags; + + local_irq_save(flags); + get_new_mmu_context(mm); + pevn_set(mm->context & ASID_MASK); + local_irq_restore(flags); +} + +void local_flush_tlb_mm(struct mm_struct *mm) +{ + if (mm->context != 0) + drop_mmu_context(mm); +} + +void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + unsigned long vma_mm_context = mm->context; + if (mm->context != 0) { + unsigned long flags; + int size; + + local_irq_save(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + if (size <= TLBSIZE) { + int oldpid = pevn_get() & ASID_MASK; + int newpid = vma_mm_context & ASID_MASK; + + start &= PAGE_MASK; + end += (PAGE_SIZE - 1); + end &= PAGE_MASK; + while (start < end) { + int idx; + + pevn_set(start | newpid); + start += PAGE_SIZE; + barrier(); + tlb_probe(); + idx = tlbpt_get(); + pectx_set(0); + pevn_set(KSEG1); + if (idx < 0) + continue; + tlb_write_indexed(); + } + pevn_set(oldpid); + } else { + /* Bigger than TLBSIZE, get new ASID directly */ + get_new_mmu_context(mm); + if (mm == current->active_mm) + pevn_set(vma_mm_context & ASID_MASK); + } + local_irq_restore(flags); + } +} + +void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + unsigned long flags; + int size; + + local_irq_save(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + if (size <= TLBSIZE) { + int pid = pevn_get(); + + start &= PAGE_MASK; + end += PAGE_SIZE - 1; + end &= PAGE_MASK; + + while (start < end) { + long idx; + + pevn_set(start); + start += PAGE_SIZE; + tlb_probe(); + idx = tlbpt_get(); + if (idx < 0) + continue; + pectx_set(0); + pevn_set(KSEG1); + barrier(); + tlb_write_indexed(); + } + pevn_set(pid); + } else { + local_flush_tlb_all(); + } + + local_irq_restore(flags); +} + +void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + if (!vma || vma->vm_mm->context != 0) { + unsigned long flags; + int oldpid, newpid, idx; + unsigned long vma_ASID = vma->vm_mm->context; + + newpid = vma_ASID & ASID_MASK; + page &= PAGE_MASK; + local_irq_save(flags); + oldpid = pevn_get() & ASID_MASK; + pevn_set(page | newpid); + barrier(); + tlb_probe(); + idx = tlbpt_get(); + pectx_set(0); + pevn_set(KSEG1); + if (idx < 0) /* p_bit(31) - 1: miss, 0: hit*/ + goto finish; + barrier(); + tlb_write_indexed(); +finish: + pevn_set(oldpid); + local_irq_restore(flags); + } +} + +/* + * This one is only used for pages with the global bit set so we don't care + * much about the ASID. + */ +void local_flush_tlb_one(unsigned long page) +{ + unsigned long flags; + int oldpid, idx; + + local_irq_save(flags); + oldpid = pevn_get(); + page &= (PAGE_MASK << 1); + pevn_set(page); + barrier(); + tlb_probe(); + idx = tlbpt_get(); + pectx_set(0); + if (idx >= 0) { + /* Make sure all entries differ. */ + pevn_set(KSEG1); + barrier(); + tlb_write_indexed(); + } + pevn_set(oldpid); + local_irq_restore(flags); +} + +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) +{ + unsigned long flags; + int idx, pid; + + /* + * Handle debugger faulting in for debugee. + */ + if (current->active_mm != vma->vm_mm) + return; + + pid = pevn_get() & ASID_MASK; + + local_irq_save(flags); + address &= PAGE_MASK; + pevn_set(address | pid); + barrier(); + tlb_probe(); + idx = tlbpt_get(); + pectx_set(pte_val(pte)); + pevn_set(address | pid); + if (idx < 0) + tlb_write_random(); + else + tlb_write_indexed(); + + pevn_set(pid); + local_irq_restore(flags); +} + +void __cpuinit tlb_init(void) +{ + tlblock_set(0); + local_flush_tlb_all(); + memcpy((void *)(EXCEPTION_VECTOR_BASE_ADDR + 0x100), + &score7_FTLB_refill_Handler, 0xFC); + flush_icache_range(EXCEPTION_VECTOR_BASE_ADDR + 0x100, + EXCEPTION_VECTOR_BASE_ADDR + 0x1FC); +} diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index e2bdd7b94fd9..4df3570fe511 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -10,12 +10,17 @@ config SUPERH select EMBEDDED select HAVE_CLK select HAVE_IDE + select HAVE_LMB select HAVE_OPROFILE select HAVE_GENERIC_DMA_COHERENT select HAVE_IOREMAP_PROT if MMU select HAVE_ARCH_TRACEHOOK select HAVE_DMA_API_DEBUG select HAVE_PERF_COUNTERS + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_BZIP2 + select HAVE_KERNEL_LZMA + select HAVE_SYSCALL_TRACEPOINTS select RTC_LIB select GENERIC_ATOMIC64 help @@ -31,6 +36,9 @@ config SUPERH32 select HAVE_FUNCTION_TRACER select HAVE_FTRACE_MCOUNT_RECORD select HAVE_DYNAMIC_FTRACE + select HAVE_FUNCTION_TRACE_MCOUNT_TEST + select HAVE_FTRACE_SYSCALLS + select HAVE_FUNCTION_GRAPH_TRACER select HAVE_ARCH_KGDB select ARCH_HIBERNATION_POSSIBLE if MMU @@ -212,6 +220,8 @@ config CPU_SHX3 config ARCH_SHMOBILE bool select ARCH_SUSPEND_POSSIBLE + select PM + select PM_RUNTIME if SUPERH32 @@ -389,6 +399,13 @@ config CPU_SUBTYPE_SH7724 help Select SH7724 if you have an SH-MobileR2R CPU. +config CPU_SUBTYPE_SH7757 + bool "Support SH7757 processor" + select CPU_SH4A + select CPU_SHX2 + help + Select SH7757 if you have a SH4A SH7757 CPU. + config CPU_SUBTYPE_SH7763 bool "Support SH7763 processor" select CPU_SH4A @@ -751,12 +768,31 @@ config UBC_WAKEUP If unsure, say N. -config CMDLINE_BOOL - bool "Default bootloader kernel arguments" +choice + prompt "Kernel command line" + optional + default CMDLINE_OVERWRITE + help + Setting this option allows the kernel command line arguments + to be set. + +config CMDLINE_OVERWRITE + bool "Overwrite bootloader kernel arguments" + help + Given string will overwrite any arguments passed in by + a bootloader. + +config CMDLINE_EXTEND + bool "Extend bootloader kernel arguments" + help + Given string will be concatenated with arguments passed in + by a bootloader. + +endchoice config CMDLINE - string "Initial kernel command string" - depends on CMDLINE_BOOL + string "Kernel command line arguments string" + depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND default "console=ttySC1,115200" endmenu diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index 39224b57c6ef..55907af1dc25 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -38,11 +38,13 @@ config EARLY_SCIF_CONSOLE_PORT default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \ CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \ CPU_SUBTYPE_SH7343 - default "0xffea0000" if CPU_SUBTYPE_SH7785 + default "0xfe4c0000" if CPU_SUBTYPE_SH7757 + default "0xffeb0000" if CPU_SUBTYPE_SH7785 default "0xffeb0000" if CPU_SUBTYPE_SH7786 default "0xfffe8000" if CPU_SUBTYPE_SH7203 default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263 default "0xffe80000" if CPU_SH4 + default "0xa4000150" if CPU_SH3 default "0x00000000" config EARLY_PRINTK @@ -61,12 +63,14 @@ config EARLY_PRINTK select both the EARLY_SCIF_CONSOLE and SH_STANDARD_BIOS, using the kernel command line option to toggle back and forth. -config DEBUG_STACKOVERFLOW +config STACK_DEBUG bool "Check for stack overflows" depends on DEBUG_KERNEL && SUPERH32 help This option will cause messages to be printed if free stack space - drops below a certain limit. + drops below a certain limit. Saying Y here will add overhead to + every function call and will therefore incur a major + performance hit. Most users should say N. config DEBUG_STACK_USAGE bool "Stack utilization instrumentation" @@ -107,6 +111,14 @@ config DUMP_CODE Those looking for more verbose debugging output should say Y. +config DWARF_UNWINDER + bool "Enable the DWARF unwinder for stacktraces" + select FRAME_POINTER + default n + help + Enabling this option will make stacktraces more accurate, at + the cost of an increase in overall kernel size. + config SH_NO_BSS_INIT bool "Avoid zeroing BSS (to speed-up startup on suitable platforms)" depends on DEBUG_KERNEL @@ -123,4 +135,9 @@ config SH64_SR_WATCH bool "Debug: set SR.WATCH to enable hardware watchpoints and trace" depends on SUPERH64 +config MCOUNT + def_bool y + depends on SUPERH32 + depends on STACK_DEBUG || FUNCTION_TRACER + endmenu diff --git a/arch/sh/Makefile b/arch/sh/Makefile index 75d049b03f7e..fc51a918b31a 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -136,6 +136,8 @@ machdir-$(CONFIG_SH_7751_SYSTEMH) += mach-systemh machdir-$(CONFIG_SH_EDOSK7705) += mach-edosk7705 machdir-$(CONFIG_SH_HIGHLANDER) += mach-highlander machdir-$(CONFIG_SH_MIGOR) += mach-migor +machdir-$(CONFIG_SH_KFR2R09) += mach-kfr2r09 +machdir-$(CONFIG_SH_ECOVEC) += mach-ecovec24 machdir-$(CONFIG_SH_SDK7780) += mach-sdk7780 machdir-$(CONFIG_SH_X3PROTO) += mach-x3proto machdir-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp @@ -186,17 +188,27 @@ KBUILD_CFLAGS += -pipe $(cflags-y) KBUILD_CPPFLAGS += $(cflags-y) KBUILD_AFLAGS += $(cflags-y) +ifeq ($(CONFIG_MCOUNT),y) + KBUILD_CFLAGS += -pg +endif + +ifeq ($(CONFIG_DWARF_UNWINDER),y) + KBUILD_CFLAGS += -fasynchronous-unwind-tables +endif + libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y) libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y) -PHONY += maketools FORCE +BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.srec \ + zImage vmlinux.srec romImage +PHONY += maketools $(BOOT_TARGETS) FORCE maketools: include/linux/version.h FORCE $(Q)$(MAKE) $(build)=arch/sh/tools include/asm-sh/machtypes.h all: $(KBUILD_IMAGE) -zImage uImage uImage.srec vmlinux.srec: vmlinux +$(BOOT_TARGETS): vmlinux $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ compressed: zImage @@ -208,10 +220,14 @@ archclean: $(Q)$(MAKE) $(clean)=arch/sh/kernel/vsyscall define archhelp - @echo '* zImage - Compressed kernel image' + @echo ' zImage - Compressed kernel image' + @echo ' romImage - Compressed ROM image, if supported' @echo ' vmlinux.srec - Create an ELF S-record' - @echo ' uImage - Create a bootable image for U-Boot' - @echo ' uImage.srec - Create an S-record for U-Boot' + @echo '* uImage - Alias to bootable U-Boot image' + @echo ' uImage.srec - Create an S-record for U-Boot' + @echo '* uImage.gz - Kernel-only image for U-Boot (gzip)' + @echo ' uImage.bz2 - Kernel-only image for U-Boot (bzip2)' + @echo ' uImage.lzma - Kernel-only image for U-Boot (lzma)' endef CLEAN_FILES += include/asm-sh/machtypes.h diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 2b1af0eefa6a..aedd9deb5de2 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -160,7 +160,6 @@ config SH_SH7785LCR bool "SH7785LCR" depends on CPU_SUBTYPE_SH7785 select SYS_SUPPORTS_PCI - select IO_TRAPPED if MMU config SH_SH7785LCR_29BIT_PHYSMAPS bool "SH7785LCR 29bit physmaps" @@ -171,6 +170,13 @@ config SH_SH7785LCR_29BIT_PHYSMAPS DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, you can access all on-board device in 29bit address mode. +config SH_SH7785LCR_PT + bool "SH7785LCR prototype board on 32-bit MMU mode" + depends on SH_SH7785LCR && 32BIT + default n + help + If you use prototype board, this option is enabled. + config SH_URQUELL bool "Urquell" depends on CPU_SUBTYPE_SH7786 @@ -193,6 +199,20 @@ config SH_AP325RXA Renesas "AP-325RXA" support. Compatible with ALGO SYSTEM CO.,LTD. "AP-320A" +config SH_KFR2R09 + bool "KFR2R09" + depends on CPU_SUBTYPE_SH7724 + select ARCH_REQUIRE_GPIOLIB + help + "Kit For R2R for 2009" support. + +config SH_ECOVEC + bool "EcoVec" + depends on CPU_SUBTYPE_SH7724 + select ARCH_REQUIRE_GPIOLIB + help + Renesas "R0P7724LC0011/21RL (EcoVec)" support. + config SH_SH7763RDP bool "SH7763RDP" depends on CPU_SUBTYPE_SH7763 diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c index b9c88cc519e2..327d47c25a57 100644 --- a/arch/sh/boards/board-ap325rxa.c +++ b/arch/sh/boards/board-ap325rxa.c @@ -188,7 +188,7 @@ static struct sh_mobile_lcdc_info lcdc_info = { .name = "LB070WV1", .xres = 800, .yres = 480, - .left_margin = 40, + .left_margin = 32, .right_margin = 160, .hsync_len = 8, .upper_margin = 63, @@ -211,7 +211,7 @@ static struct resource lcdc_resources[] = { [0] = { .name = "LCDC", .start = 0xfe940000, /* P4-only space */ - .end = 0xfe941fff, + .end = 0xfe942fff, .flags = IORESOURCE_MEM, }, [1] = { @@ -227,6 +227,9 @@ static struct platform_device lcdc_device = { .dev = { .platform_data = &lcdc_info, }, + .archdata = { + .hwblk_id = HWBLK_LCDC, + }, }; static void camera_power(int val) @@ -377,6 +380,9 @@ static struct platform_device ceu_device = { .dev = { .platform_data = &sh_mobile_ceu_info, }, + .archdata = { + .hwblk_id = HWBLK_CEU, + }, }; struct spi_gpio_platform_data sdcard_cn3_platform_data = { diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c index 42410a15d255..e5a8a2fde39c 100644 --- a/arch/sh/boards/board-sh7785lcr.c +++ b/arch/sh/boards/board-sh7785lcr.c @@ -223,6 +223,19 @@ static struct platform_device sm501_device = { .resource = sm501_resources, }; +static struct resource i2c_proto_resources[] = { + [0] = { + .start = PCA9564_PROTO_32BIT_ADDR, + .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = 12, + .end = 12, + .flags = IORESOURCE_IRQ, + }, +}; + static struct resource i2c_resources[] = { [0] = { .start = PCA9564_ADDR, @@ -271,6 +284,11 @@ static int __init sh7785lcr_devices_setup(void) i2c_register_board_info(0, sh7785lcr_i2c_devices, ARRAY_SIZE(sh7785lcr_i2c_devices)); + if (mach_is_sh7785lcr_pt()) { + i2c_device.resource = i2c_proto_resources; + i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources); + } + return platform_add_devices(sh7785lcr_devices, ARRAY_SIZE(sh7785lcr_devices)); } diff --git a/arch/sh/boards/mach-ecovec24/Makefile b/arch/sh/boards/mach-ecovec24/Makefile new file mode 100644 index 000000000000..51f852151655 --- /dev/null +++ b/arch/sh/boards/mach-ecovec24/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the R0P7724LC0011/21RL (EcoVec) +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# + +obj-y := setup.o
\ No newline at end of file diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c new file mode 100644 index 000000000000..96bc1698310f --- /dev/null +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -0,0 +1,670 @@ +/* + * Copyright (C) 2009 Renesas Solutions Corp. + * + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/usb/r8a66597.h> +#include <linux/i2c.h> +#include <linux/input.h> +#include <video/sh_mobile_lcdc.h> +#include <media/sh_mobile_ceu.h> +#include <asm/heartbeat.h> +#include <asm/sh_eth.h> +#include <asm/sh_keysc.h> +#include <asm/clock.h> +#include <cpu/sh7724.h> + +/* + * Address Interface BusWidth + *----------------------------------------- + * 0x0000_0000 uboot 16bit + * 0x0004_0000 Linux romImage 16bit + * 0x0014_0000 MTD for Linux 16bit + * 0x0400_0000 Internal I/O 16/32bit + * 0x0800_0000 DRAM 32bit + * 0x1800_0000 MFI 16bit + */ + +/* Heartbeat */ +static unsigned char led_pos[] = { 0, 1, 2, 3 }; +static struct heartbeat_data heartbeat_data = { + .regsize = 8, + .nr_bits = 4, + .bit_pos = led_pos, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = 0xA405012C, /* PTG */ + .end = 0xA405012E - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +/* MTD */ +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "boot loader", + .offset = 0, + .size = (5 * 1024 * 1024), + .mask_flags = MTD_CAP_ROM, + }, { + .name = "free-area", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x03ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .resource = nor_flash_resources, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .dev = { + .platform_data = &nor_flash_data, + }, +}; + +/* SH Eth */ +#define SH_ETH_ADDR (0xA4600000) +#define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0) +#define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8) +static struct resource sh_eth_resources[] = { + [0] = { + .start = SH_ETH_ADDR, + .end = SH_ETH_ADDR + 0x1FC, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 91, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +struct sh_eth_plat_data sh_eth_plat = { + .phy = 0x1f, /* SMSC LAN8700 */ + .edmac_endian = EDMAC_LITTLE_ENDIAN, +}; + +static struct platform_device sh_eth_device = { + .name = "sh-eth", + .id = 0, + .dev = { + .platform_data = &sh_eth_plat, + }, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .resource = sh_eth_resources, +}; + +/* USB0 host */ +void usb0_port_power(int port, int power) +{ + gpio_set_value(GPIO_PTB4, power); +} + +static struct r8a66597_platdata usb0_host_data = { + .on_chip = 1, + .port_power = usb0_port_power, +}; + +static struct resource usb0_host_resources[] = { + [0] = { + .start = 0xa4d80000, + .end = 0xa4d80124 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 65, + .end = 65, + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device usb0_host_device = { + .name = "r8a66597_hcd", + .id = 0, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &usb0_host_data, + }, + .num_resources = ARRAY_SIZE(usb0_host_resources), + .resource = usb0_host_resources, +}; + +/* + * USB1 + * + * CN5 can use both host/function, + * and we can determine it by checking PTB[3] + * + * This time only USB1 host is supported. + */ +void usb1_port_power(int port, int power) +{ + if (!gpio_get_value(GPIO_PTB3)) { + printk(KERN_ERR "USB1 function is not supported\n"); + return; + } + + gpio_set_value(GPIO_PTB5, power); +} + +static struct r8a66597_platdata usb1_host_data = { + .on_chip = 1, + .port_power = usb1_port_power, +}; + +static struct resource usb1_host_resources[] = { + [0] = { + .start = 0xa4d90000, + .end = 0xa4d90124 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 66, + .end = 66, + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device usb1_host_device = { + .name = "r8a66597_hcd", + .id = 1, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &usb1_host_data, + }, + .num_resources = ARRAY_SIZE(usb1_host_resources), + .resource = usb1_host_resources, +}; + +/* LCDC */ +static struct sh_mobile_lcdc_info lcdc_info = { + .ch[0] = { + .interface_type = RGB18, + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .lcd_cfg = { + .sync = 0, /* hsync and vsync are active low */ + }, + .lcd_size_cfg = { /* 7.0 inch */ + .width = 152, + .height = 91, + }, + .board_cfg = { + }, + } +}; + +static struct resource lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, + .end = 0xfe942fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 106, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(lcdc_resources), + .resource = lcdc_resources, + .dev = { + .platform_data = &lcdc_info, + }, + .archdata = { + .hwblk_id = HWBLK_LCDC, + }, +}; + +/* CEU0 */ +static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource ceu0_resources[] = { + [0] = { + .name = "CEU0", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 52, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu0_device = { + .name = "sh_mobile_ceu", + .id = 0, /* "ceu0" clock */ + .num_resources = ARRAY_SIZE(ceu0_resources), + .resource = ceu0_resources, + .dev = { + .platform_data = &sh_mobile_ceu0_info, + }, + .archdata = { + .hwblk_id = HWBLK_CEU0, + }, +}; + +/* CEU1 */ +static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource ceu1_resources[] = { + [0] = { + .name = "CEU1", + .start = 0xfe914000, + .end = 0xfe91409f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 63, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu1_device = { + .name = "sh_mobile_ceu", + .id = 1, /* "ceu1" clock */ + .num_resources = ARRAY_SIZE(ceu1_resources), + .resource = ceu1_resources, + .dev = { + .platform_data = &sh_mobile_ceu1_info, + }, + .archdata = { + .hwblk_id = HWBLK_CEU1, + }, +}; + +/* I2C device */ +static struct i2c_board_info i2c1_devices[] = { + { + I2C_BOARD_INFO("r2025sd", 0x32), + }, +}; + +/* KEYSC */ +static struct sh_keysc_info keysc_info = { + .mode = SH_KEYSC_MODE_1, + .scan_timing = 3, + .delay = 50, + .kycr2_delay = 100, + .keycodes = { KEY_1, 0, 0, 0, 0, + KEY_2, 0, 0, 0, 0, + KEY_3, 0, 0, 0, 0, + KEY_4, 0, 0, 0, 0, + KEY_5, 0, 0, 0, 0, + KEY_6, 0, 0, 0, 0, }, +}; + +static struct resource keysc_resources[] = { + [0] = { + .name = "KEYSC", + .start = 0x044b0000, + .end = 0x044b000f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 79, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device keysc_device = { + .name = "sh_keysc", + .id = 0, /* keysc0 clock */ + .num_resources = ARRAY_SIZE(keysc_resources), + .resource = keysc_resources, + .dev = { + .platform_data = &keysc_info, + }, + .archdata = { + .hwblk_id = HWBLK_KEYSC, + }, +}; + +static struct platform_device *ecovec_devices[] __initdata = { + &heartbeat_device, + &nor_flash_device, + &sh_eth_device, + &usb0_host_device, + &usb1_host_device, /* USB1 host support */ + &lcdc_device, + &ceu0_device, + &ceu1_device, + &keysc_device, +}; + +#define EEPROM_ADDR 0x50 +static u8 mac_read(struct i2c_adapter *a, u8 command) +{ + struct i2c_msg msg[2]; + u8 buf; + int ret; + + msg[0].addr = EEPROM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &command; + + msg[1].addr = EEPROM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf; + + ret = i2c_transfer(a, msg, 2); + if (ret < 0) { + printk(KERN_ERR "error %d\n", ret); + buf = 0xff; + } + + return buf; +} + +#define MAC_LEN 6 +static void __init sh_eth_init(void) +{ + struct i2c_adapter *a = i2c_get_adapter(1); + struct clk *eth_clk; + u8 mac[MAC_LEN]; + int i; + + if (!a) { + pr_err("can not get I2C 1\n"); + return; + } + + eth_clk = clk_get(NULL, "eth0"); + if (!eth_clk) { + pr_err("can not get eth0 clk\n"); + return; + } + + /* read MAC address frome EEPROM */ + for (i = 0; i < MAC_LEN; i++) { + mac[i] = mac_read(a, 0x10 + i); + msleep(10); + } + + /* clock enable */ + clk_enable(eth_clk); + + /* reset sh-eth */ + ctrl_outl(0x1, SH_ETH_ADDR + 0x0); + + /* set MAC addr */ + ctrl_outl((mac[0] << 24) | + (mac[1] << 16) | + (mac[2] << 8) | + (mac[3] << 0), SH_ETH_MAHR); + ctrl_outl((mac[4] << 8) | + (mac[5] << 0), SH_ETH_MALR); + + clk_put(eth_clk); +} + +#define PORT_HIZA 0xA4050158 +#define IODRIVEA 0xA405018A +static int __init arch_setup(void) +{ + /* enable SCIFA0 */ + gpio_request(GPIO_FN_SCIF0_TXD, NULL); + gpio_request(GPIO_FN_SCIF0_RXD, NULL); + + /* enable debug LED */ + gpio_request(GPIO_PTG0, NULL); + gpio_request(GPIO_PTG1, NULL); + gpio_request(GPIO_PTG2, NULL); + gpio_request(GPIO_PTG3, NULL); + gpio_direction_output(GPIO_PTG0, 0); + gpio_direction_output(GPIO_PTG1, 0); + gpio_direction_output(GPIO_PTG2, 0); + gpio_direction_output(GPIO_PTG3, 0); + ctrl_outw((ctrl_inw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA); + + /* enable SH-Eth */ + gpio_request(GPIO_PTA1, NULL); + gpio_direction_output(GPIO_PTA1, 1); + mdelay(20); + + gpio_request(GPIO_FN_RMII_RXD0, NULL); + gpio_request(GPIO_FN_RMII_RXD1, NULL); + gpio_request(GPIO_FN_RMII_TXD0, NULL); + gpio_request(GPIO_FN_RMII_TXD1, NULL); + gpio_request(GPIO_FN_RMII_REF_CLK, NULL); + gpio_request(GPIO_FN_RMII_TX_EN, NULL); + gpio_request(GPIO_FN_RMII_RX_ER, NULL); + gpio_request(GPIO_FN_RMII_CRS_DV, NULL); + gpio_request(GPIO_FN_MDIO, NULL); + gpio_request(GPIO_FN_MDC, NULL); + gpio_request(GPIO_FN_LNKSTA, NULL); + + /* enable USB */ + ctrl_outw(0x0000, 0xA4D80000); + ctrl_outw(0x0000, 0xA4D90000); + gpio_request(GPIO_PTB3, NULL); + gpio_request(GPIO_PTB4, NULL); + gpio_request(GPIO_PTB5, NULL); + gpio_direction_input(GPIO_PTB3); + gpio_direction_output(GPIO_PTB4, 0); + gpio_direction_output(GPIO_PTB5, 0); + ctrl_outw(0x0600, 0xa40501d4); + ctrl_outw(0x0600, 0xa4050192); + + /* enable LCDC */ + gpio_request(GPIO_FN_LCDD23, NULL); + gpio_request(GPIO_FN_LCDD22, NULL); + gpio_request(GPIO_FN_LCDD21, NULL); + gpio_request(GPIO_FN_LCDD20, NULL); + gpio_request(GPIO_FN_LCDD19, NULL); + gpio_request(GPIO_FN_LCDD18, NULL); + gpio_request(GPIO_FN_LCDD17, NULL); + gpio_request(GPIO_FN_LCDD16, NULL); + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDDISP, NULL); + gpio_request(GPIO_FN_LCDHSYN, NULL); + gpio_request(GPIO_FN_LCDDCK, NULL); + gpio_request(GPIO_FN_LCDVSYN, NULL); + gpio_request(GPIO_FN_LCDDON, NULL); + gpio_request(GPIO_FN_LCDLCLK, NULL); + ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA); + + gpio_request(GPIO_PTE6, NULL); + gpio_request(GPIO_PTU1, NULL); + gpio_request(GPIO_PTR1, NULL); + gpio_request(GPIO_PTA2, NULL); + gpio_direction_input(GPIO_PTE6); + gpio_direction_output(GPIO_PTU1, 0); + gpio_direction_output(GPIO_PTR1, 0); + gpio_direction_output(GPIO_PTA2, 0); + + /* I/O buffer drive ability is low */ + ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0040 , IODRIVEA); + + if (gpio_get_value(GPIO_PTE6)) { + /* DVI */ + lcdc_info.clock_source = LCDC_CLK_EXTERNAL; + lcdc_info.ch[0].clock_divider = 1, + lcdc_info.ch[0].lcd_cfg.name = "DVI"; + lcdc_info.ch[0].lcd_cfg.xres = 1280; + lcdc_info.ch[0].lcd_cfg.yres = 720; + lcdc_info.ch[0].lcd_cfg.left_margin = 220; + lcdc_info.ch[0].lcd_cfg.right_margin = 110; + lcdc_info.ch[0].lcd_cfg.hsync_len = 40; + lcdc_info.ch[0].lcd_cfg.upper_margin = 20; + lcdc_info.ch[0].lcd_cfg.lower_margin = 5; + lcdc_info.ch[0].lcd_cfg.vsync_len = 5; + + gpio_set_value(GPIO_PTA2, 1); + gpio_set_value(GPIO_PTU1, 1); + } else { + /* Panel */ + + lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; + lcdc_info.ch[0].clock_divider = 2, + lcdc_info.ch[0].lcd_cfg.name = "Panel"; + lcdc_info.ch[0].lcd_cfg.xres = 800; + lcdc_info.ch[0].lcd_cfg.yres = 480; + lcdc_info.ch[0].lcd_cfg.left_margin = 220; + lcdc_info.ch[0].lcd_cfg.right_margin = 110; + lcdc_info.ch[0].lcd_cfg.hsync_len = 70; + lcdc_info.ch[0].lcd_cfg.upper_margin = 20; + lcdc_info.ch[0].lcd_cfg.lower_margin = 5; + lcdc_info.ch[0].lcd_cfg.vsync_len = 5; + + gpio_set_value(GPIO_PTR1, 1); + + /* FIXME + * + * LCDDON control is needed for Panel, + * but current sh_mobile_lcdc driver doesn't control it. + * It is temporary correspondence + */ + gpio_request(GPIO_PTF4, NULL); + gpio_direction_output(GPIO_PTF4, 1); + } + + /* enable CEU0 */ + gpio_request(GPIO_FN_VIO0_D15, NULL); + gpio_request(GPIO_FN_VIO0_D14, NULL); + gpio_request(GPIO_FN_VIO0_D13, NULL); + gpio_request(GPIO_FN_VIO0_D12, NULL); + gpio_request(GPIO_FN_VIO0_D11, NULL); + gpio_request(GPIO_FN_VIO0_D10, NULL); + gpio_request(GPIO_FN_VIO0_D9, NULL); + gpio_request(GPIO_FN_VIO0_D8, NULL); + gpio_request(GPIO_FN_VIO0_D7, NULL); + gpio_request(GPIO_FN_VIO0_D6, NULL); + gpio_request(GPIO_FN_VIO0_D5, NULL); + gpio_request(GPIO_FN_VIO0_D4, NULL); + gpio_request(GPIO_FN_VIO0_D3, NULL); + gpio_request(GPIO_FN_VIO0_D2, NULL); + gpio_request(GPIO_FN_VIO0_D1, NULL); + gpio_request(GPIO_FN_VIO0_D0, NULL); + gpio_request(GPIO_FN_VIO0_VD, NULL); + gpio_request(GPIO_FN_VIO0_CLK, NULL); + gpio_request(GPIO_FN_VIO0_FLD, NULL); + gpio_request(GPIO_FN_VIO0_HD, NULL); + platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); + + /* enable CEU1 */ + gpio_request(GPIO_FN_VIO1_D7, NULL); + gpio_request(GPIO_FN_VIO1_D6, NULL); + gpio_request(GPIO_FN_VIO1_D5, NULL); + gpio_request(GPIO_FN_VIO1_D4, NULL); + gpio_request(GPIO_FN_VIO1_D3, NULL); + gpio_request(GPIO_FN_VIO1_D2, NULL); + gpio_request(GPIO_FN_VIO1_D1, NULL); + gpio_request(GPIO_FN_VIO1_D0, NULL); + gpio_request(GPIO_FN_VIO1_FLD, NULL); + gpio_request(GPIO_FN_VIO1_HD, NULL); + gpio_request(GPIO_FN_VIO1_VD, NULL); + gpio_request(GPIO_FN_VIO1_CLK, NULL); + platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); + + /* enable KEYSC */ + gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); + gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYIN0, NULL); + + /* enable user debug switch */ + gpio_request(GPIO_PTR0, NULL); + gpio_request(GPIO_PTR4, NULL); + gpio_request(GPIO_PTR5, NULL); + gpio_request(GPIO_PTR6, NULL); + gpio_direction_input(GPIO_PTR0); + gpio_direction_input(GPIO_PTR4); + gpio_direction_input(GPIO_PTR5); + gpio_direction_input(GPIO_PTR6); + + /* enable I2C device */ + i2c_register_board_info(1, i2c1_devices, + ARRAY_SIZE(i2c1_devices)); + + return platform_add_devices(ecovec_devices, + ARRAY_SIZE(ecovec_devices)); +} +arch_initcall(arch_setup); + +static int __init devices_setup(void) +{ + sh_eth_init(); + return 0; +} +device_initcall(devices_setup); + + +static struct sh_machine_vector mv_ecovec __initmv = { + .mv_name = "R0P7724 (EcoVec)", +}; diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c index 1639f8915000..566e69d8d729 100644 --- a/arch/sh/boards/mach-highlander/setup.c +++ b/arch/sh/boards/mach-highlander/setup.c @@ -22,6 +22,7 @@ #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/usb/r8a66597.h> +#include <linux/usb/m66592.h> #include <net/ax88796.h> #include <asm/machvec.h> #include <mach/highlander.h> @@ -60,6 +61,11 @@ static struct platform_device r8a66597_usb_host_device = { .resource = r8a66597_usb_host_resources, }; +static struct m66592_platdata usbf_platdata = { + .xtal = M66592_PLATDATA_XTAL_24MHZ, + .vif = 1, +}; + static struct resource m66592_usb_peripheral_resources[] = { [0] = { .name = "m66592_udc", @@ -81,6 +87,7 @@ static struct platform_device m66592_usb_peripheral_device = { .dev = { .dma_mask = NULL, /* don't use dma */ .coherent_dma_mask = 0xffffffff, + .platform_data = &usbf_platdata, }, .num_resources = ARRAY_SIZE(m66592_usb_peripheral_resources), .resource = m66592_usb_peripheral_resources, diff --git a/arch/sh/boards/mach-kfr2r09/Makefile b/arch/sh/boards/mach-kfr2r09/Makefile new file mode 100644 index 000000000000..5d5867826e3b --- /dev/null +++ b/arch/sh/boards/mach-kfr2r09/Makefile @@ -0,0 +1,2 @@ +obj-y := setup.o +obj-$(CONFIG_FB_SH_MOBILE_LCDC) += lcd_wqvga.o diff --git a/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c new file mode 100644 index 000000000000..8ccb1cc8b589 --- /dev/null +++ b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c @@ -0,0 +1,332 @@ +/* + * KFR2R09 LCD panel support + * + * Copyright (C) 2009 Magnus Damm + * + * Register settings based on the out-of-tree t33fb.c driver + * Copyright (C) 2008 Lineo Solutions, Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/fb.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/gpio.h> +#include <video/sh_mobile_lcdc.h> +#include <mach/kfr2r09.h> +#include <cpu/sh7724.h> + +/* The on-board LCD module is a Hitachi TX07D34VM0AAA. This module is made + * up of a 240x400 LCD hooked up to a R61517 driver IC. The driver IC is + * communicating with the main port of the LCDC using an 18-bit SYS interface. + * + * The device code for this LCD module is 0x01221517. + */ + +static const unsigned char data_frame_if[] = { + 0x02, /* WEMODE: 1=cont, 0=one-shot */ + 0x00, 0x00, + 0x00, /* EPF, DFM */ + 0x02, /* RIM[1] : 1 (18bpp) */ +}; + +static const unsigned char data_panel[] = { + 0x0b, + 0x63, /* 400 lines */ + 0x04, 0x00, 0x00, 0x04, 0x11, 0x00, 0x00, +}; + +static const unsigned char data_timing[] = { + 0x00, 0x00, 0x13, 0x08, 0x08, +}; + +static const unsigned char data_timing_src[] = { + 0x11, 0x01, 0x00, 0x01, +}; + +static const unsigned char data_gamma[] = { + 0x01, 0x02, 0x08, 0x23, 0x03, 0x0c, 0x00, 0x06, 0x00, 0x00, + 0x01, 0x00, 0x0c, 0x23, 0x03, 0x08, 0x02, 0x06, 0x00, 0x00, +}; + +static const unsigned char data_power[] = { + 0x07, 0xc5, 0xdc, 0x02, 0x33, 0x0a, +}; + +static unsigned long read_reg(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + return so->read_data(sohandle); +} + +static void write_reg(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so, + int i, unsigned long v) +{ + if (i) + so->write_data(sohandle, v); /* PTH4/LCDRS High [param, 17:0] */ + else + so->write_index(sohandle, v); /* PTH4/LCDRS Low [cmd, 7:0] */ +} + +static void write_data(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so, + unsigned char const *data, int no_data) +{ + int i; + + for (i = 0; i < no_data; i++) + write_reg(sohandle, so, 1, data[i]); +} + +static unsigned long read_device_code(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + unsigned long device_code; + + /* access protect OFF */ + write_reg(sohandle, so, 0, 0xb0); + write_reg(sohandle, so, 1, 0x00); + + /* deep standby OFF */ + write_reg(sohandle, so, 0, 0xb1); + write_reg(sohandle, so, 1, 0x00); + + /* device code command */ + write_reg(sohandle, so, 0, 0xbf); + mdelay(50); + + /* dummy read */ + read_reg(sohandle, so); + + /* read device code */ + device_code = ((read_reg(sohandle, so) & 0xff) << 24); + device_code |= ((read_reg(sohandle, so) & 0xff) << 16); + device_code |= ((read_reg(sohandle, so) & 0xff) << 8); + device_code |= (read_reg(sohandle, so) & 0xff); + + return device_code; +} + +static void write_memory_start(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + write_reg(sohandle, so, 0, 0x2c); +} + +static void clear_memory(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + int i; + + /* write start */ + write_memory_start(sohandle, so); + + /* paint it black */ + for (i = 0; i < (240 * 400); i++) + write_reg(sohandle, so, 1, 0x00); +} + +static void display_on(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + /* access protect off */ + write_reg(sohandle, so, 0, 0xb0); + write_reg(sohandle, so, 1, 0x00); + + /* exit deep standby mode */ + write_reg(sohandle, so, 0, 0xb1); + write_reg(sohandle, so, 1, 0x00); + + /* frame memory I/F */ + write_reg(sohandle, so, 0, 0xb3); + write_data(sohandle, so, data_frame_if, ARRAY_SIZE(data_frame_if)); + + /* display mode and frame memory write mode */ + write_reg(sohandle, so, 0, 0xb4); + write_reg(sohandle, so, 1, 0x00); /* DBI, internal clock */ + + /* panel */ + write_reg(sohandle, so, 0, 0xc0); + write_data(sohandle, so, data_panel, ARRAY_SIZE(data_panel)); + + /* timing (normal) */ + write_reg(sohandle, so, 0, 0xc1); + write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing)); + + /* timing (partial) */ + write_reg(sohandle, so, 0, 0xc2); + write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing)); + + /* timing (idle) */ + write_reg(sohandle, so, 0, 0xc3); + write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing)); + + /* timing (source/VCOM/gate driving) */ + write_reg(sohandle, so, 0, 0xc4); + write_data(sohandle, so, data_timing_src, ARRAY_SIZE(data_timing_src)); + + /* gamma (red) */ + write_reg(sohandle, so, 0, 0xc8); + write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma)); + + /* gamma (green) */ + write_reg(sohandle, so, 0, 0xc9); + write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma)); + + /* gamma (blue) */ + write_reg(sohandle, so, 0, 0xca); + write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma)); + + /* power (common) */ + write_reg(sohandle, so, 0, 0xd0); + write_data(sohandle, so, data_power, ARRAY_SIZE(data_power)); + + /* VCOM */ + write_reg(sohandle, so, 0, 0xd1); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x0f); + write_reg(sohandle, so, 1, 0x02); + + /* power (normal) */ + write_reg(sohandle, so, 0, 0xd2); + write_reg(sohandle, so, 1, 0x63); + write_reg(sohandle, so, 1, 0x24); + + /* power (partial) */ + write_reg(sohandle, so, 0, 0xd3); + write_reg(sohandle, so, 1, 0x63); + write_reg(sohandle, so, 1, 0x24); + + /* power (idle) */ + write_reg(sohandle, so, 0, 0xd4); + write_reg(sohandle, so, 1, 0x63); + write_reg(sohandle, so, 1, 0x24); + + write_reg(sohandle, so, 0, 0xd8); + write_reg(sohandle, so, 1, 0x77); + write_reg(sohandle, so, 1, 0x77); + + /* TE signal */ + write_reg(sohandle, so, 0, 0x35); + write_reg(sohandle, so, 1, 0x00); + + /* TE signal line */ + write_reg(sohandle, so, 0, 0x44); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x00); + + /* column address */ + write_reg(sohandle, so, 0, 0x2a); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0xef); + + /* page address */ + write_reg(sohandle, so, 0, 0x2b); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x01); + write_reg(sohandle, so, 1, 0x8f); + + /* exit sleep mode */ + write_reg(sohandle, so, 0, 0x11); + + mdelay(120); + + /* clear vram */ + clear_memory(sohandle, so); + + /* display ON */ + write_reg(sohandle, so, 0, 0x29); + mdelay(1); + + write_memory_start(sohandle, so); +} + +int kfr2r09_lcd_setup(void *board_data, void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + /* power on */ + gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */ + gpio_set_value(GPIO_PTE4, 0); /* LCD_RST/ -> L */ + gpio_set_value(GPIO_PTF4, 1); /* PROTECT/ -> H */ + udelay(1100); + gpio_set_value(GPIO_PTE4, 1); /* LCD_RST/ -> H */ + udelay(10); + gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */ + mdelay(20); + + if (read_device_code(sohandle, so) != 0x01221517) + return -ENODEV; + + pr_info("KFR2R09 WQVGA LCD Module detected.\n"); + + display_on(sohandle, so); + return 0; +} + +#define CTRL_CKSW 0x10 +#define CTRL_C10 0x20 +#define CTRL_CPSW 0x80 +#define MAIN_MLED4 0x40 +#define MAIN_MSW 0x80 + +static int kfr2r09_lcd_backlight(int on) +{ + struct i2c_adapter *a; + struct i2c_msg msg; + unsigned char buf[2]; + int ret; + + a = i2c_get_adapter(0); + if (!a) + return -ENODEV; + + buf[0] = 0x00; + if (on) + buf[1] = CTRL_CPSW | CTRL_C10 | CTRL_CKSW; + else + buf[1] = 0; + + msg.addr = 0x75; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + buf[0] = 0x01; + if (on) + buf[1] = MAIN_MSW | MAIN_MLED4 | 0x0c; + else + buf[1] = 0; + + msg.addr = 0x75; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + return 0; +} + +void kfr2r09_lcd_on(void *board_data) +{ + kfr2r09_lcd_backlight(1); +} + +void kfr2r09_lcd_off(void *board_data) +{ + kfr2r09_lcd_backlight(0); +} diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c new file mode 100644 index 000000000000..c08d33fe2104 --- /dev/null +++ b/arch/sh/boards/mach-kfr2r09/setup.c @@ -0,0 +1,386 @@ +/* + * KFR2R09 board support code + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/onenand.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/usb/r8a66597.h> +#include <video/sh_mobile_lcdc.h> +#include <asm/clock.h> +#include <asm/machvec.h> +#include <asm/io.h> +#include <asm/sh_keysc.h> +#include <cpu/sh7724.h> +#include <mach/kfr2r09.h> + +static struct mtd_partition kfr2r09_nor_flash_partitions[] = +{ + { + .name = "boot", + .offset = 0, + .size = (4 * 1024 * 1024), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, + { + .name = "other", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data kfr2r09_nor_flash_data = { + .width = 2, + .parts = kfr2r09_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(kfr2r09_nor_flash_partitions), +}; + +static struct resource kfr2r09_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x03ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device kfr2r09_nor_flash_device = { + .name = "physmap-flash", + .resource = kfr2r09_nor_flash_resources, + .num_resources = ARRAY_SIZE(kfr2r09_nor_flash_resources), + .dev = { + .platform_data = &kfr2r09_nor_flash_data, + }, +}; + +static struct resource kfr2r09_nand_flash_resources[] = { + [0] = { + .name = "NAND Flash", + .start = 0x10000000, + .end = 0x1001ffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device kfr2r09_nand_flash_device = { + .name = "onenand-flash", + .resource = kfr2r09_nand_flash_resources, + .num_resources = ARRAY_SIZE(kfr2r09_nand_flash_resources), +}; + +static struct sh_keysc_info kfr2r09_sh_keysc_info = { + .mode = SH_KEYSC_MODE_1, /* KEYOUT0->4, KEYIN0->4 */ + .scan_timing = 3, + .delay = 10, + .keycodes = { + KEY_PHONE, KEY_CLEAR, KEY_MAIL, KEY_WWW, KEY_ENTER, + KEY_1, KEY_2, KEY_3, 0, KEY_UP, + KEY_4, KEY_5, KEY_6, 0, KEY_LEFT, + KEY_7, KEY_8, KEY_9, KEY_PROG1, KEY_RIGHT, + KEY_S, KEY_0, KEY_P, KEY_PROG2, KEY_DOWN, + 0, 0, 0, 0, 0 + }, +}; + +static struct resource kfr2r09_sh_keysc_resources[] = { + [0] = { + .name = "KEYSC", + .start = 0x044b0000, + .end = 0x044b000f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 79, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kfr2r09_sh_keysc_device = { + .name = "sh_keysc", + .id = 0, /* "keysc0" clock */ + .num_resources = ARRAY_SIZE(kfr2r09_sh_keysc_resources), + .resource = kfr2r09_sh_keysc_resources, + .dev = { + .platform_data = &kfr2r09_sh_keysc_info, + }, + .archdata = { + .hwblk_id = HWBLK_KEYSC, + }, +}; + +static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = { + .clock_source = LCDC_CLK_BUS, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .interface_type = SYS18, + .clock_divider = 6, + .flags = LCDC_FLAGS_DWPOL, + .lcd_cfg = { + .name = "TX07D34VM0AAA", + .xres = 240, + .yres = 400, + .left_margin = 0, + .right_margin = 16, + .hsync_len = 8, + .upper_margin = 0, + .lower_margin = 1, + .vsync_len = 1, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + }, + .lcd_size_cfg = { + .width = 35, + .height = 58, + }, + .board_cfg = { + .setup_sys = kfr2r09_lcd_setup, + .display_on = kfr2r09_lcd_on, + .display_off = kfr2r09_lcd_off, + }, + .sys_bus_cfg = { + .ldmt2r = 0x07010904, + .ldmt3r = 0x14012914, + /* set 1s delay to encourage fsync() */ + .deferred_io_msec = 1000, + }, + } +}; + +static struct resource kfr2r09_sh_lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, /* P4-only space */ + .end = 0xfe942fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 106, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kfr2r09_sh_lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(kfr2r09_sh_lcdc_resources), + .resource = kfr2r09_sh_lcdc_resources, + .dev = { + .platform_data = &kfr2r09_sh_lcdc_info, + }, + .archdata = { + .hwblk_id = HWBLK_LCDC, + }, +}; + +static struct r8a66597_platdata kfr2r09_usb0_gadget_data = { + .on_chip = 1, +}; + +static struct resource kfr2r09_usb0_gadget_resources[] = { + [0] = { + .start = 0x04d80000, + .end = 0x04d80123, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 65, + .end = 65, + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device kfr2r09_usb0_gadget_device = { + .name = "r8a66597_udc", + .id = 0, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &kfr2r09_usb0_gadget_data, + }, + .num_resources = ARRAY_SIZE(kfr2r09_usb0_gadget_resources), + .resource = kfr2r09_usb0_gadget_resources, +}; + +static struct platform_device *kfr2r09_devices[] __initdata = { + &kfr2r09_nor_flash_device, + &kfr2r09_nand_flash_device, + &kfr2r09_sh_keysc_device, + &kfr2r09_sh_lcdc_device, +}; + +#define BSC_CS0BCR 0xfec10004 +#define BSC_CS0WCR 0xfec10024 +#define BSC_CS4BCR 0xfec10010 +#define BSC_CS4WCR 0xfec10030 +#define PORT_MSELCRB 0xa4050182 + +#ifdef CONFIG_I2C +static int kfr2r09_usb0_gadget_i2c_setup(void) +{ + struct i2c_adapter *a; + struct i2c_msg msg; + unsigned char buf[2]; + int ret; + + a = i2c_get_adapter(0); + if (!a) + return -ENODEV; + + /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */ + buf[0] = 0x13; + msg.addr = 0x09; + msg.buf = buf; + msg.len = 1; + msg.flags = 0; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + buf[0] = 0; + msg.addr = 0x09; + msg.buf = buf; + msg.len = 1; + msg.flags = I2C_M_RD; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + buf[1] = buf[0] | (1 << 1); + buf[0] = 0x13; + msg.addr = 0x09; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + return 0; +} +#else +static int kfr2r09_usb0_gadget_i2c_setup(void) +{ + return -ENODEV; +} +#endif + +static int kfr2r09_usb0_gadget_setup(void) +{ + int plugged_in; + + gpio_request(GPIO_PTN4, NULL); /* USB_DET */ + gpio_direction_input(GPIO_PTN4); + plugged_in = gpio_get_value(GPIO_PTN4); + if (!plugged_in) + return -ENODEV; /* no cable plugged in */ + + if (kfr2r09_usb0_gadget_i2c_setup() != 0) + return -ENODEV; /* unable to configure using i2c */ + + ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); + gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */ + gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */ + gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */ + msleep(20); /* wait 20ms to let the clock settle */ + clk_enable(clk_get(NULL, "usb0")); + ctrl_outw(0x0600, 0xa40501d4); + + return 0; +} + +static int __init kfr2r09_devices_setup(void) +{ + /* enable SCIF1 serial port for YC401 console support */ + gpio_request(GPIO_FN_SCIF1_RXD, NULL); + gpio_request(GPIO_FN_SCIF1_TXD, NULL); + + /* setup NOR flash at CS0 */ + ctrl_outl(0x36db0400, BSC_CS0BCR); + ctrl_outl(0x00000500, BSC_CS0WCR); + + /* setup NAND flash at CS4 */ + ctrl_outl(0x36db0400, BSC_CS4BCR); + ctrl_outl(0x00000500, BSC_CS4WCR); + + /* setup KEYSC pins */ + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); + gpio_request(GPIO_FN_KEYIN0, NULL); + gpio_request(GPIO_FN_KEYIN1, NULL); + gpio_request(GPIO_FN_KEYIN2, NULL); + gpio_request(GPIO_FN_KEYIN3, NULL); + gpio_request(GPIO_FN_KEYIN4, NULL); + gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); + + /* setup LCDC pins for SYS panel */ + gpio_request(GPIO_FN_LCDD17, NULL); + gpio_request(GPIO_FN_LCDD16, NULL); + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDRS, NULL); /* LCD_RS */ + gpio_request(GPIO_FN_LCDCS, NULL); /* LCD_CS/ */ + gpio_request(GPIO_FN_LCDRD, NULL); /* LCD_RD/ */ + gpio_request(GPIO_FN_LCDWR, NULL); /* LCD_WR/ */ + gpio_request(GPIO_FN_LCDVSYN, NULL); /* LCD_VSYNC */ + gpio_request(GPIO_PTE4, NULL); /* LCD_RST/ */ + gpio_direction_output(GPIO_PTE4, 1); + gpio_request(GPIO_PTF4, NULL); /* PROTECT/ */ + gpio_direction_output(GPIO_PTF4, 1); + gpio_request(GPIO_PTU0, NULL); /* LEDSTDBY/ */ + gpio_direction_output(GPIO_PTU0, 1); + + /* setup USB function */ + if (kfr2r09_usb0_gadget_setup() == 0) + platform_device_register(&kfr2r09_usb0_gadget_device); + + return platform_add_devices(kfr2r09_devices, + ARRAY_SIZE(kfr2r09_devices)); +} +device_initcall(kfr2r09_devices_setup); + +/* Return the board specific boot mode pin configuration */ +static int kfr2r09_mode_pins(void) +{ + /* MD0=1, MD1=1, MD2=0: Clock Mode 3 + * MD3=0: 16-bit Area0 Bus Width + * MD5=1: Little Endian + * MD8=1: Test Mode Disabled + */ + return MODE_PIN0 | MODE_PIN1 | MODE_PIN5 | MODE_PIN8; +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_kfr2r09 __initmv = { + .mv_name = "kfr2r09", + .mv_mode_pins = kfr2r09_mode_pins, +}; diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c index f9b2e4df35b9..6ed1fd32369e 100644 --- a/arch/sh/boards/mach-migor/setup.c +++ b/arch/sh/boards/mach-migor/setup.c @@ -98,6 +98,9 @@ static struct platform_device sh_keysc_device = { .dev = { .platform_data = &sh_keysc_info, }, + .archdata = { + .hwblk_id = HWBLK_KEYSC, + }, }; static struct mtd_partition migor_nor_flash_partitions[] = @@ -276,7 +279,7 @@ static struct resource migor_lcdc_resources[] = { [0] = { .name = "LCDC", .start = 0xfe940000, /* P4-only space */ - .end = 0xfe941fff, + .end = 0xfe942fff, .flags = IORESOURCE_MEM, }, [1] = { @@ -292,6 +295,9 @@ static struct platform_device migor_lcdc_device = { .dev = { .platform_data = &sh_mobile_lcdc_info, }, + .archdata = { + .hwblk_id = HWBLK_LCDC, + }, }; static struct clk *camera_clk; @@ -379,6 +385,9 @@ static struct platform_device migor_ceu_device = { .dev = { .platform_data = &sh_mobile_ceu_info, }, + .archdata = { + .hwblk_id = HWBLK_CEU, + }, }; struct spi_gpio_platform_data sdcard_cn9_platform_data = { diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c index af84904ed86f..36374078e521 100644 --- a/arch/sh/boards/mach-se/7722/setup.c +++ b/arch/sh/boards/mach-se/7722/setup.c @@ -22,6 +22,7 @@ #include <asm/io.h> #include <asm/heartbeat.h> #include <asm/sh_keysc.h> +#include <cpu/sh7722.h> /* Heartbeat */ static struct heartbeat_data heartbeat_data = { @@ -137,6 +138,9 @@ static struct platform_device sh_keysc_device = { .dev = { .platform_data = &sh_keysc_info, }, + .archdata = { + .hwblk_id = HWBLK_KEYSC, + }, }; static struct platform_device *se7722_devices[] __initdata = { diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index 15456a0773bf..00973e0f8c63 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c @@ -39,7 +39,15 @@ * SW41 : abxx xxxx -> a = 0 : Analog monitor * 1 : Digital monitor * b = 0 : VGA - * 1 : SVGA + * 1 : 720p + */ + +/* + * about 720p + * + * When you use 1280 x 720 lcdc output, + * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz, + * and change SW41 to use 720p */ /* Heartbeat */ @@ -158,7 +166,7 @@ static struct resource lcdc_resources[] = { [0] = { .name = "LCDC", .start = 0xfe940000, - .end = 0xfe941fff, + .end = 0xfe942fff, .flags = IORESOURCE_MEM, }, [1] = { @@ -174,6 +182,9 @@ static struct platform_device lcdc_device = { .dev = { .platform_data = &lcdc_info, }, + .archdata = { + .hwblk_id = HWBLK_LCDC, + }, }; /* CEU0 */ @@ -205,6 +216,9 @@ static struct platform_device ceu0_device = { .dev = { .platform_data = &sh_mobile_ceu0_info, }, + .archdata = { + .hwblk_id = HWBLK_CEU0, + }, }; /* CEU1 */ @@ -236,6 +250,9 @@ static struct platform_device ceu1_device = { .dev = { .platform_data = &sh_mobile_ceu1_info, }, + .archdata = { + .hwblk_id = HWBLK_CEU1, + }, }; /* KEYSC in SoC (Needs SW33-2 set to ON) */ @@ -274,6 +291,9 @@ static struct platform_device keysc_device = { .dev = { .platform_data = &keysc_info, }, + .archdata = { + .hwblk_id = HWBLK_KEYSC, + }, }; /* SH Eth */ @@ -302,15 +322,19 @@ static struct platform_device sh_eth_device = { }, .num_resources = ARRAY_SIZE(sh_eth_resources), .resource = sh_eth_resources, + .archdata = { + .hwblk_id = HWBLK_ETHER, + }, }; static struct r8a66597_platdata sh7724_usb0_host_data = { + .on_chip = 1, }; static struct resource sh7724_usb0_host_resources[] = { [0] = { .start = 0xa4d80000, - .end = 0xa4d800ff, + .end = 0xa4d80124 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -330,6 +354,38 @@ static struct platform_device sh7724_usb0_host_device = { }, .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources), .resource = sh7724_usb0_host_resources, + .archdata = { + .hwblk_id = HWBLK_USB0, + }, +}; + +static struct r8a66597_platdata sh7724_usb1_gadget_data = { + .on_chip = 1, +}; + +static struct resource sh7724_usb1_gadget_resources[] = { + [0] = { + .start = 0xa4d90000, + .end = 0xa4d90123, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 66, + .end = 66, + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device sh7724_usb1_gadget_device = { + .name = "r8a66597_udc", + .id = 1, /* USB1 */ + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &sh7724_usb1_gadget_data, + }, + .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources), + .resource = sh7724_usb1_gadget_resources, }; static struct platform_device *ms7724se_devices[] __initdata = { @@ -342,6 +398,7 @@ static struct platform_device *ms7724se_devices[] __initdata = { &keysc_device, &sh_eth_device, &sh7724_usb0_host_device, + &sh7724_usb1_gadget_device, }; #define EEPROM_OP 0xBA206000 @@ -421,9 +478,38 @@ static int __init devices_setup(void) /* turn on USB clocks, use external clock */ ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); +#ifdef CONFIG_PM + /* Let LED9 show STATUS2 */ + gpio_request(GPIO_FN_STATUS2, NULL); + + /* Lit LED10 show STATUS0 */ + gpio_request(GPIO_FN_STATUS0, NULL); + + /* Lit LED11 show PDSTATUS */ + gpio_request(GPIO_FN_PDSTATUS, NULL); +#else + /* Lit LED9 */ + gpio_request(GPIO_PTJ6, NULL); + gpio_direction_output(GPIO_PTJ6, 1); + gpio_export(GPIO_PTJ6, 0); + + /* Lit LED10 */ + gpio_request(GPIO_PTJ5, NULL); + gpio_direction_output(GPIO_PTJ5, 1); + gpio_export(GPIO_PTJ5, 0); + + /* Lit LED11 */ + gpio_request(GPIO_PTJ7, NULL); + gpio_direction_output(GPIO_PTJ7, 1); + gpio_export(GPIO_PTJ7, 0); +#endif + /* enable USB0 port */ ctrl_outw(0x0600, 0xa40501d4); + /* enable USB1 port */ + ctrl_outw(0x0600, 0xa4050192); + /* enable IRQ 0,1,2 */ gpio_request(GPIO_FN_INTC_IRQ0, NULL); gpio_request(GPIO_FN_INTC_IRQ1, NULL); @@ -546,15 +632,15 @@ static int __init devices_setup(void) sh_eth_init(); if (sw & SW41_B) { - /* SVGA */ - lcdc_info.ch[0].lcd_cfg.xres = 800; - lcdc_info.ch[0].lcd_cfg.yres = 600; - lcdc_info.ch[0].lcd_cfg.left_margin = 142; - lcdc_info.ch[0].lcd_cfg.right_margin = 52; - lcdc_info.ch[0].lcd_cfg.hsync_len = 96; - lcdc_info.ch[0].lcd_cfg.upper_margin = 24; - lcdc_info.ch[0].lcd_cfg.lower_margin = 2; - lcdc_info.ch[0].lcd_cfg.vsync_len = 2; + /* 720p */ + lcdc_info.ch[0].lcd_cfg.xres = 1280; + lcdc_info.ch[0].lcd_cfg.yres = 720; + lcdc_info.ch[0].lcd_cfg.left_margin = 220; + lcdc_info.ch[0].lcd_cfg.right_margin = 110; + lcdc_info.ch[0].lcd_cfg.hsync_len = 40; + lcdc_info.ch[0].lcd_cfg.upper_margin = 20; + lcdc_info.ch[0].lcd_cfg.lower_margin = 5; + lcdc_info.ch[0].lcd_cfg.vsync_len = 5; } else { /* VGA */ lcdc_info.ch[0].lcd_cfg.xres = 640; diff --git a/arch/sh/boards/mach-x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c index 8913ae39a802..efe4cb9f8a77 100644 --- a/arch/sh/boards/mach-x3proto/setup.c +++ b/arch/sh/boards/mach-x3proto/setup.c @@ -17,6 +17,7 @@ #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/usb/r8a66597.h> +#include <linux/usb/m66592.h> #include <asm/ilsel.h> static struct resource heartbeat_resources[] = { @@ -89,6 +90,11 @@ static struct platform_device r8a66597_usb_host_device = { .resource = r8a66597_usb_host_resources, }; +static struct m66592_platdata usbf_platdata = { + .xtal = M66592_PLATDATA_XTAL_24MHZ, + .vif = 1, +}; + static struct resource m66592_usb_peripheral_resources[] = { [0] = { .name = "m66592_udc", @@ -109,6 +115,7 @@ static struct platform_device m66592_usb_peripheral_device = { .dev = { .dma_mask = NULL, /* don't use dma */ .coherent_dma_mask = 0xffffffff, + .platform_data = &usbf_platdata, }, .num_resources = ARRAY_SIZE(m66592_usb_peripheral_resources), .resource = m66592_usb_peripheral_resources, diff --git a/arch/sh/boot/.gitignore b/arch/sh/boot/.gitignore index aad5edddf93b..541087d2029c 100644 --- a/arch/sh/boot/.gitignore +++ b/arch/sh/boot/.gitignore @@ -1,4 +1,3 @@ zImage -vmlinux.srec -uImage -uImage.srec +vmlinux* +uImage* diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile index 78efb04c28f3..a1316872be6f 100644 --- a/arch/sh/boot/Makefile +++ b/arch/sh/boot/Makefile @@ -20,8 +20,13 @@ CONFIG_BOOT_LINK_OFFSET ?= 0x00800000 CONFIG_ZERO_PAGE_OFFSET ?= 0x00001000 CONFIG_ENTRY_OFFSET ?= 0x00001000 -targets := zImage vmlinux.srec uImage uImage.srec -subdir- := compressed +suffix-$(CONFIG_KERNEL_GZIP) := gz +suffix-$(CONFIG_KERNEL_BZIP2) := bz2 +suffix-$(CONFIG_KERNEL_LZMA) := lzma + +targets := zImage vmlinux.srec romImage uImage uImage.srec uImage.gz uImage.bz2 uImage.lzma +extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma +subdir- := compressed romimage $(obj)/zImage: $(obj)/compressed/vmlinux FORCE $(call if_changed,objcopy) @@ -30,6 +35,13 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE $(obj)/compressed/vmlinux: FORCE $(Q)$(MAKE) $(build)=$(obj)/compressed $@ +$(obj)/romImage: $(obj)/romimage/vmlinux FORCE + $(call if_changed,objcopy) + @echo ' Kernel: $@ is ready' + +$(obj)/romimage/vmlinux: $(obj)/zImage FORCE + $(Q)$(MAKE) $(build)=$(obj)/romimage $@ + KERNEL_MEMORY := 0x00000000 ifeq ($(CONFIG_PMB_FIXED),y) KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \ @@ -40,9 +52,6 @@ KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \ $$[$(CONFIG_MEMORY_START)]') endif -export CONFIG_PAGE_OFFSET CONFIG_MEMORY_START CONFIG_BOOT_LINK_OFFSET \ - CONFIG_ZERO_PAGE_OFFSET CONFIG_ENTRY_OFFSET KERNEL_MEMORY - KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \ $$[$(CONFIG_PAGE_OFFSET) + \ $(KERNEL_MEMORY) + \ @@ -55,19 +64,30 @@ KERNEL_ENTRY := $(shell /bin/bash -c 'printf "0x%08x" \ quiet_cmd_uimage = UIMAGE $@ cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \ - -C gzip -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \ + -C $(2) -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \ -n 'Linux-$(KERNELRELEASE)' -d $< $@ -$(obj)/uImage: $(obj)/vmlinux.bin.gz FORCE - $(call if_changed,uimage) - @echo ' Image $@ is ready' - $(obj)/vmlinux.bin: vmlinux FORCE $(call if_changed,objcopy) $(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE $(call if_changed,gzip) +$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE + $(call if_changed,bzip2) + +$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE + $(call if_changed,lzma) + +$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2 + $(call if_changed,uimage,bzip2) + +$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz + $(call if_changed,uimage,gzip) + +$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma + $(call if_changed,uimage,lzma) + OBJCOPYFLAGS_vmlinux.srec := -I binary -O srec $(obj)/vmlinux.srec: $(obj)/compressed/vmlinux $(call if_changed,objcopy) @@ -76,5 +96,9 @@ OBJCOPYFLAGS_uImage.srec := -I binary -O srec $(obj)/uImage.srec: $(obj)/uImage $(call if_changed,objcopy) -clean-files += uImage uImage.srec vmlinux.srec \ - vmlinux.bin vmlinux.bin.gz +$(obj)/uImage: $(obj)/uImage.$(suffix-y) + @ln -sf $(notdir $<) $@ + @echo ' Image $@ is ready' + +export CONFIG_PAGE_OFFSET CONFIG_MEMORY_START CONFIG_BOOT_LINK_OFFSET \ + CONFIG_ZERO_PAGE_OFFSET CONFIG_ENTRY_OFFSET KERNEL_MEMORY suffix-y diff --git a/arch/sh/boot/compressed/.gitignore b/arch/sh/boot/compressed/.gitignore new file mode 100644 index 000000000000..2374a83d87b2 --- /dev/null +++ b/arch/sh/boot/compressed/.gitignore @@ -0,0 +1 @@ +vmlinux.bin.* diff --git a/arch/sh/boot/compressed/Makefile b/arch/sh/boot/compressed/Makefile index 9531bf1b7c2f..6182eca5180a 100644 --- a/arch/sh/boot/compressed/Makefile +++ b/arch/sh/boot/compressed/Makefile @@ -5,9 +5,10 @@ # targets := vmlinux vmlinux.bin vmlinux.bin.gz \ - head_$(BITS).o misc_$(BITS).o piggy.o + vmlinux.bin.bz2 vmlinux.bin.lzma \ + head_$(BITS).o misc.o piggy.o -OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc_$(BITS).o $(obj)/cache.o +OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o ifdef CONFIG_SH_STANDARD_BIOS OBJECTS += $(obj)/../../kernel/sh_bios.o @@ -23,7 +24,7 @@ IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \ LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) -ifeq ($(CONFIG_FUNCTION_TRACER),y) +ifeq ($(CONFIG_MCOUNT),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif @@ -38,10 +39,18 @@ $(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(LIBGCC) FORCE $(obj)/vmlinux.bin: vmlinux FORCE $(call if_changed,objcopy) -$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE +vmlinux.bin.all-y := $(obj)/vmlinux.bin + +$(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) FORCE $(call if_changed,gzip) +$(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE + $(call if_changed,bzip2) +$(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE + $(call if_changed,lzma) OBJCOPYFLAGS += -R .empty_zero_page -$(obj)/piggy.o: $(obj)/piggy.S $(obj)/vmlinux.bin.gz FORCE - $(call if_changed,as_o_S) +LDFLAGS_piggy.o := -r --format binary --oformat $(ld-bfd) -T + +$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE + $(call if_changed,ld) diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S index 06ac31f3be88..02a30935f0b9 100644 --- a/arch/sh/boot/compressed/head_32.S +++ b/arch/sh/boot/compressed/head_32.S @@ -22,7 +22,7 @@ startup: bt clear_bss sub r0, r2 mov.l bss_start_addr, r0 - mov #0xe0, r1 + mov #0xffffffe0, r1 and r1, r0 ! align cache line mov.l text_start_addr, r3 mov r0, r1 diff --git a/arch/sh/boot/compressed/misc.c b/arch/sh/boot/compressed/misc.c new file mode 100644 index 000000000000..fd56a71ca9d9 --- /dev/null +++ b/arch/sh/boot/compressed/misc.c @@ -0,0 +1,149 @@ +/* + * arch/sh/boot/compressed/misc.c + * + * This is a collection of several routines from gzip-1.0.3 + * adapted for Linux. + * + * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 + * + * Adapted for SH by Stuart Menefy, Aug 1999 + * + * Modified to use standard LinuxSH BIOS by Greg Banks 7Jul2000 + */ + +#include <asm/uaccess.h> +#include <asm/addrspace.h> +#include <asm/page.h> +#include <asm/sh_bios.h> + +/* + * gzip declarations + */ + +#define STATIC static + +#undef memset +#undef memcpy +#define memzero(s, n) memset ((s), 0, (n)) + +/* cache.c */ +#define CACHE_ENABLE 0 +#define CACHE_DISABLE 1 +int cache_control(unsigned int command); + +extern char input_data[]; +extern int input_len; +static unsigned char *output; + +static void error(char *m); + +int puts(const char *); + +extern int _text; /* Defined in vmlinux.lds.S */ +extern int _end; +static unsigned long free_mem_ptr; +static unsigned long free_mem_end_ptr; + +#ifdef CONFIG_HAVE_KERNEL_BZIP2 +#define HEAP_SIZE 0x400000 +#else +#define HEAP_SIZE 0x10000 +#endif + +#ifdef CONFIG_KERNEL_GZIP +#include "../../../../lib/decompress_inflate.c" +#endif + +#ifdef CONFIG_KERNEL_BZIP2 +#include "../../../../lib/decompress_bunzip2.c" +#endif + +#ifdef CONFIG_KERNEL_LZMA +#include "../../../../lib/decompress_unlzma.c" +#endif + +#ifdef CONFIG_SH_STANDARD_BIOS +size_t strlen(const char *s) +{ + int i = 0; + + while (*s++) + i++; + return i; +} + +int puts(const char *s) +{ + int len = strlen(s); + sh_bios_console_write(s, len); + return len; +} +#else +int puts(const char *s) +{ + /* This should be updated to use the sh-sci routines */ + return 0; +} +#endif + +void* memset(void* s, int c, size_t n) +{ + int i; + char *ss = (char*)s; + + for (i=0;i<n;i++) ss[i] = c; + return s; +} + +void* memcpy(void* __dest, __const void* __src, + size_t __n) +{ + int i; + char *d = (char *)__dest, *s = (char *)__src; + + for (i=0;i<__n;i++) d[i] = s[i]; + return __dest; +} + +static void error(char *x) +{ + puts("\n\n"); + puts(x); + puts("\n\n -- System halted"); + + while(1); /* Halt */ +} + +#ifdef CONFIG_SUPERH64 +#define stackalign 8 +#else +#define stackalign 4 +#endif + +#define STACK_SIZE (4096) +long __attribute__ ((aligned(stackalign))) user_stack[STACK_SIZE]; +long *stack_start = &user_stack[STACK_SIZE]; + +void decompress_kernel(void) +{ + unsigned long output_addr; + +#ifdef CONFIG_SUPERH64 + output_addr = (CONFIG_MEMORY_START + 0x2000); +#else + output_addr = PHYSADDR((unsigned long)&_text+PAGE_SIZE); +#ifdef CONFIG_29BIT + output_addr |= P2SEG; +#endif +#endif + + output = (unsigned char *)output_addr; + free_mem_ptr = (unsigned long)&_end; + free_mem_end_ptr = free_mem_ptr + HEAP_SIZE; + + puts("Uncompressing Linux... "); + cache_control(CACHE_ENABLE); + decompress(input_data, input_len, NULL, NULL, output, NULL, error); + cache_control(CACHE_DISABLE); + puts("Ok, booting the kernel.\n"); +} diff --git a/arch/sh/boot/compressed/misc_32.c b/arch/sh/boot/compressed/misc_32.c deleted file mode 100644 index efdba6b29572..000000000000 --- a/arch/sh/boot/compressed/misc_32.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * arch/sh/boot/compressed/misc.c - * - * This is a collection of several routines from gzip-1.0.3 - * adapted for Linux. - * - * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 - * - * Adapted for SH by Stuart Menefy, Aug 1999 - * - * Modified to use standard LinuxSH BIOS by Greg Banks 7Jul2000 - */ - -#include <asm/uaccess.h> -#include <asm/addrspace.h> -#include <asm/page.h> -#ifdef CONFIG_SH_STANDARD_BIOS -#include <asm/sh_bios.h> -#endif - -/* - * gzip declarations - */ - -#define OF(args) args -#define STATIC static - -#undef memset -#undef memcpy -#define memzero(s, n) memset ((s), 0, (n)) - -typedef unsigned char uch; -typedef unsigned short ush; -typedef unsigned long ulg; - -#define WSIZE 0x8000 /* Window size must be at least 32k, */ - /* and a power of two */ - -static uch *inbuf; /* input buffer */ -static uch window[WSIZE]; /* Sliding window buffer */ - -static unsigned insize = 0; /* valid bytes in inbuf */ -static unsigned inptr = 0; /* index of next byte to be processed in inbuf */ -static unsigned outcnt = 0; /* bytes in output buffer */ - -/* gzip flag byte */ -#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */ -#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ -#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ -#define COMMENT 0x10 /* bit 4 set: file comment present */ -#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ -#define RESERVED 0xC0 /* bit 6,7: reserved */ - -#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf()) - -/* Diagnostic functions */ -#ifdef DEBUG -# define Assert(cond,msg) {if(!(cond)) error(msg);} -# define Trace(x) fprintf x -# define Tracev(x) {if (verbose) fprintf x ;} -# define Tracevv(x) {if (verbose>1) fprintf x ;} -# define Tracec(c,x) {if (verbose && (c)) fprintf x ;} -# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;} -#else -# define Assert(cond,msg) -# define Trace(x) -# define Tracev(x) -# define Tracevv(x) -# define Tracec(c,x) -# define Tracecv(c,x) -#endif - -static int fill_inbuf(void); -static void flush_window(void); -static void error(char *m); - -extern char input_data[]; -extern int input_len; - -static long bytes_out = 0; -static uch *output_data; -static unsigned long output_ptr = 0; - -static void error(char *m); - -int puts(const char *); - -extern int _text; /* Defined in vmlinux.lds.S */ -extern int _end; -static unsigned long free_mem_ptr; -static unsigned long free_mem_end_ptr; - -#define HEAP_SIZE 0x10000 - -#include "../../../../lib/inflate.c" - -#ifdef CONFIG_SH_STANDARD_BIOS -size_t strlen(const char *s) -{ - int i = 0; - - while (*s++) - i++; - return i; -} - -int puts(const char *s) -{ - int len = strlen(s); - sh_bios_console_write(s, len); - return len; -} -#else -int puts(const char *s) -{ - /* This should be updated to use the sh-sci routines */ - return 0; -} -#endif - -void* memset(void* s, int c, size_t n) -{ - int i; - char *ss = (char*)s; - - for (i=0;i<n;i++) ss[i] = c; - return s; -} - -void* memcpy(void* __dest, __const void* __src, - size_t __n) -{ - int i; - char *d = (char *)__dest, *s = (char *)__src; - - for (i=0;i<__n;i++) d[i] = s[i]; - return __dest; -} - -/* =========================================================================== - * Fill the input buffer. This is called only when the buffer is empty - * and at least one byte is really needed. - */ -static int fill_inbuf(void) -{ - if (insize != 0) { - error("ran out of input data"); - } - - inbuf = input_data; - insize = input_len; - inptr = 1; - return inbuf[0]; -} - -/* =========================================================================== - * Write the output window window[0..outcnt-1] and update crc and bytes_out. - * (Used for the decompressed data only.) - */ -static void flush_window(void) -{ - ulg c = crc; /* temporary variable */ - unsigned n; - uch *in, *out, ch; - - in = window; - out = &output_data[output_ptr]; - for (n = 0; n < outcnt; n++) { - ch = *out++ = *in++; - c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8); - } - crc = c; - bytes_out += (ulg)outcnt; - output_ptr += (ulg)outcnt; - outcnt = 0; -} - -static void error(char *x) -{ - puts("\n\n"); - puts(x); - puts("\n\n -- System halted"); - - while(1); /* Halt */ -} - -#define STACK_SIZE (4096) -long user_stack [STACK_SIZE]; -long* stack_start = &user_stack[STACK_SIZE]; - -void decompress_kernel(void) -{ - output_data = NULL; - output_ptr = PHYSADDR((unsigned long)&_text+PAGE_SIZE); -#ifdef CONFIG_29BIT - output_ptr |= P2SEG; -#endif - free_mem_ptr = (unsigned long)&_end; - free_mem_end_ptr = free_mem_ptr + HEAP_SIZE; - - makecrc(); - puts("Uncompressing Linux... "); - gunzip(); - puts("Ok, booting the kernel.\n"); -} diff --git a/arch/sh/boot/compressed/misc_64.c b/arch/sh/boot/compressed/misc_64.c deleted file mode 100644 index 2941657e18aa..000000000000 --- a/arch/sh/boot/compressed/misc_64.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * arch/sh/boot/compressed/misc_64.c - * - * This is a collection of several routines from gzip-1.0.3 - * adapted for Linux. - * - * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 - * - * Adapted for SHmedia from sh by Stuart Menefy, May 2002 - */ - -#include <asm/uaccess.h> - -/* cache.c */ -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 -int cache_control(unsigned int command); - -/* - * gzip declarations - */ - -#define OF(args) args -#define STATIC static - -#undef memset -#undef memcpy -#define memzero(s, n) memset ((s), 0, (n)) - -typedef unsigned char uch; -typedef unsigned short ush; -typedef unsigned long ulg; - -#define WSIZE 0x8000 /* Window size must be at least 32k, */ - /* and a power of two */ - -static uch *inbuf; /* input buffer */ -static uch window[WSIZE]; /* Sliding window buffer */ - -static unsigned insize = 0; /* valid bytes in inbuf */ -static unsigned inptr = 0; /* index of next byte to be processed in inbuf */ -static unsigned outcnt = 0; /* bytes in output buffer */ - -/* gzip flag byte */ -#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */ -#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ -#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ -#define COMMENT 0x10 /* bit 4 set: file comment present */ -#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ -#define RESERVED 0xC0 /* bit 6,7: reserved */ - -#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf()) - -/* Diagnostic functions */ -#ifdef DEBUG -# define Assert(cond,msg) {if(!(cond)) error(msg);} -# define Trace(x) fprintf x -# define Tracev(x) {if (verbose) fprintf x ;} -# define Tracevv(x) {if (verbose>1) fprintf x ;} -# define Tracec(c,x) {if (verbose && (c)) fprintf x ;} -# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;} -#else -# define Assert(cond,msg) -# define Trace(x) -# define Tracev(x) -# define Tracevv(x) -# define Tracec(c,x) -# define Tracecv(c,x) -#endif - -static int fill_inbuf(void); -static void flush_window(void); -static void error(char *m); - -extern char input_data[]; -extern int input_len; - -static long bytes_out = 0; -static uch *output_data; -static unsigned long output_ptr = 0; - -static void error(char *m); - -static void puts(const char *); - -extern int _text; /* Defined in vmlinux.lds.S */ -extern int _end; -static unsigned long free_mem_ptr; -static unsigned long free_mem_end_ptr; - -#define HEAP_SIZE 0x10000 - -#include "../../../../lib/inflate.c" - -void puts(const char *s) -{ -} - -void *memset(void *s, int c, size_t n) -{ - int i; - char *ss = (char *) s; - - for (i = 0; i < n; i++) - ss[i] = c; - return s; -} - -void *memcpy(void *__dest, __const void *__src, size_t __n) -{ - int i; - char *d = (char *) __dest, *s = (char *) __src; - - for (i = 0; i < __n; i++) - d[i] = s[i]; - return __dest; -} - -/* =========================================================================== - * Fill the input buffer. This is called only when the buffer is empty - * and at least one byte is really needed. - */ -static int fill_inbuf(void) -{ - if (insize != 0) { - error("ran out of input data\n"); - } - - inbuf = input_data; - insize = input_len; - inptr = 1; - return inbuf[0]; -} - -/* =========================================================================== - * Write the output window window[0..outcnt-1] and update crc and bytes_out. - * (Used for the decompressed data only.) - */ -static void flush_window(void) -{ - ulg c = crc; /* temporary variable */ - unsigned n; - uch *in, *out, ch; - - in = window; - out = &output_data[output_ptr]; - for (n = 0; n < outcnt; n++) { - ch = *out++ = *in++; - c = crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8); - } - crc = c; - bytes_out += (ulg) outcnt; - output_ptr += (ulg) outcnt; - outcnt = 0; - puts("."); -} - -static void error(char *x) -{ - puts("\n\n"); - puts(x); - puts("\n\n -- System halted"); - - while (1) ; /* Halt */ -} - -#define STACK_SIZE (4096) -long __attribute__ ((aligned(8))) user_stack[STACK_SIZE]; -long *stack_start = &user_stack[STACK_SIZE]; - -void decompress_kernel(void) -{ - output_data = (uch *) (CONFIG_MEMORY_START + 0x2000); - free_mem_ptr = (unsigned long) &_end; - free_mem_end_ptr = free_mem_ptr + HEAP_SIZE; - - makecrc(); - puts("Uncompressing Linux... "); - cache_control(CACHE_ENABLE); - gunzip(); - puts("\n"); - -#if 0 - /* When booting from ROM may want to do something like this if the - * boot loader doesn't. - */ - - /* Set up the parameters and command line */ - { - volatile unsigned int *parambase = - (int *) (CONFIG_MEMORY_START + 0x1000); - - parambase[0] = 0x1; /* MOUNT_ROOT_RDONLY */ - parambase[1] = 0x0; /* RAMDISK_FLAGS */ - parambase[2] = 0x0200; /* ORIG_ROOT_DEV */ - parambase[3] = 0x0; /* LOADER_TYPE */ - parambase[4] = 0x0; /* INITRD_START */ - parambase[5] = 0x0; /* INITRD_SIZE */ - parambase[6] = 0; - - strcpy((char *) ((int) parambase + 0x100), - "console=ttySC0,38400"); - } -#endif - - puts("Ok, booting the kernel.\n"); - - cache_control(CACHE_DISABLE); -} diff --git a/arch/sh/boot/compressed/piggy.S b/arch/sh/boot/compressed/piggy.S deleted file mode 100644 index 566071926b13..000000000000 --- a/arch/sh/boot/compressed/piggy.S +++ /dev/null @@ -1,8 +0,0 @@ - .global input_len, input_data - .data -input_len: - .long input_data_end - input_data -input_data: - .incbin "arch/sh/boot/compressed/vmlinux.bin.gz" -input_data_end: - .end diff --git a/arch/sh/boot/compressed/vmlinux.scr b/arch/sh/boot/compressed/vmlinux.scr new file mode 100644 index 000000000000..f02382ae5c48 --- /dev/null +++ b/arch/sh/boot/compressed/vmlinux.scr @@ -0,0 +1,10 @@ +SECTIONS +{ + .rodata.compressed : { + input_len = .; + LONG(input_data_end - input_data) input_data = .; + *(.data) + output_len = . - 4; + input_data_end = .; + } +} diff --git a/arch/sh/boot/romimage/Makefile b/arch/sh/boot/romimage/Makefile new file mode 100644 index 000000000000..5806eee84f6f --- /dev/null +++ b/arch/sh/boot/romimage/Makefile @@ -0,0 +1,19 @@ +# +# linux/arch/sh/boot/romimage/Makefile +# +# create an image suitable for burning to flash from zImage +# + +targets := vmlinux head.o + +OBJECTS = $(obj)/head.o +LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext 0 -e romstart + +$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o FORCE + $(call if_changed,ld) + @: + +LDFLAGS_piggy.o := -r --format binary --oformat $(ld-bfd) -T + +$(obj)/piggy.o: $(obj)/vmlinux.scr arch/sh/boot/zImage FORCE + $(call if_changed,ld) diff --git a/arch/sh/boot/romimage/head.S b/arch/sh/boot/romimage/head.S new file mode 100644 index 000000000000..219bc626dd71 --- /dev/null +++ b/arch/sh/boot/romimage/head.S @@ -0,0 +1,10 @@ +/* + * linux/arch/sh/boot/romimage/head.S + * + * Board specific setup code, executed before zImage loader + */ + +.text + .global romstart +romstart: +#include <mach/romimage.h> diff --git a/arch/sh/boot/romimage/vmlinux.scr b/arch/sh/boot/romimage/vmlinux.scr new file mode 100644 index 000000000000..287c08f8b4bb --- /dev/null +++ b/arch/sh/boot/romimage/vmlinux.scr @@ -0,0 +1,6 @@ +SECTIONS +{ + .text : { + *(.data) + } +} diff --git a/arch/sh/configs/ecovec24-romimage_defconfig b/arch/sh/configs/ecovec24-romimage_defconfig new file mode 100644 index 000000000000..9a22c64775be --- /dev/null +++ b/arch/sh/configs/ecovec24-romimage_defconfig @@ -0,0 +1,1032 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31-rc7 +# Tue Sep 8 13:56:18 2009 +# +CONFIG_SUPERH=y +CONFIG_SUPERH32=y +# CONFIG_SUPERH64 is not set +CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_IRQ_PER_CPU=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_SYS_SUPPORTS_CMT=y +CONFIG_SYS_SUPPORTS_TMU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_NO_VIRT_TO_BUS=y +CONFIG_ARCH_HAS_DEFAULT_IDLE=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_INITRAMFS_COMPRESSION_NONE=y +# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y + +# +# Performance Counters +# +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System type +# +CONFIG_CPU_SH4=y +CONFIG_CPU_SH4A=y +CONFIG_CPU_SHX2=y +CONFIG_ARCH_SHMOBILE=y +# CONFIG_CPU_SUBTYPE_SH7619 is not set +# CONFIG_CPU_SUBTYPE_SH7201 is not set +# CONFIG_CPU_SUBTYPE_SH7203 is not set +# CONFIG_CPU_SUBTYPE_SH7206 is not set +# CONFIG_CPU_SUBTYPE_SH7263 is not set +# CONFIG_CPU_SUBTYPE_MXG is not set +# CONFIG_CPU_SUBTYPE_SH7705 is not set +# CONFIG_CPU_SUBTYPE_SH7706 is not set +# CONFIG_CPU_SUBTYPE_SH7707 is not set +# CONFIG_CPU_SUBTYPE_SH7708 is not set +# CONFIG_CPU_SUBTYPE_SH7709 is not set +# CONFIG_CPU_SUBTYPE_SH7710 is not set +# CONFIG_CPU_SUBTYPE_SH7712 is not set +# CONFIG_CPU_SUBTYPE_SH7720 is not set +# CONFIG_CPU_SUBTYPE_SH7721 is not set +# CONFIG_CPU_SUBTYPE_SH7750 is not set +# CONFIG_CPU_SUBTYPE_SH7091 is not set +# CONFIG_CPU_SUBTYPE_SH7750R is not set +# CONFIG_CPU_SUBTYPE_SH7750S is not set +# CONFIG_CPU_SUBTYPE_SH7751 is not set +# CONFIG_CPU_SUBTYPE_SH7751R is not set +# CONFIG_CPU_SUBTYPE_SH7760 is not set +# CONFIG_CPU_SUBTYPE_SH4_202 is not set +# CONFIG_CPU_SUBTYPE_SH7723 is not set +CONFIG_CPU_SUBTYPE_SH7724=y +# CONFIG_CPU_SUBTYPE_SH7757 is not set +# CONFIG_CPU_SUBTYPE_SH7763 is not set +# CONFIG_CPU_SUBTYPE_SH7770 is not set +# CONFIG_CPU_SUBTYPE_SH7780 is not set +# CONFIG_CPU_SUBTYPE_SH7785 is not set +# CONFIG_CPU_SUBTYPE_SH7786 is not set +# CONFIG_CPU_SUBTYPE_SHX3 is not set +# CONFIG_CPU_SUBTYPE_SH7343 is not set +# CONFIG_CPU_SUBTYPE_SH7722 is not set +# CONFIG_CPU_SUBTYPE_SH7366 is not set + +# +# Memory management options +# +CONFIG_QUICKLIST=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MEMORY_START=0x08000000 +CONFIG_MEMORY_SIZE=0x08000000 +CONFIG_29BIT=y +# CONFIG_X2TLB is not set +CONFIG_VSYSCALL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_MAX_ACTIVE_REGIONS=1 +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_STATIC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_NR_QUICK=2 +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 + +# +# Cache configuration +# +CONFIG_CACHE_WRITEBACK=y +# CONFIG_CACHE_WRITETHROUGH is not set +# CONFIG_CACHE_OFF is not set + +# +# Processor features +# +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SH_FPU=y +# CONFIG_SH_STORE_QUEUES is not set +CONFIG_CPU_HAS_INTEVT=y +CONFIG_CPU_HAS_SR_RB=y +CONFIG_CPU_HAS_FPU=y + +# +# Board support +# +# CONFIG_SH_7724_SOLUTION_ENGINE is not set +# CONFIG_SH_KFR2R09 is not set +CONFIG_SH_ECOVEC=y + +# +# Timer and clock configuration +# +# CONFIG_SH_TIMER_TMU is not set +CONFIG_SH_TIMER_CMT=y +CONFIG_SH_PCLK_FREQ=33333333 +CONFIG_SH_CLK_CPG=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# DMA support +# +# CONFIG_SH_DMA is not set + +# +# Companion Chips +# + +# +# Additional SuperH Device Drivers +# +# CONFIG_HEARTBEAT is not set +# CONFIG_PUSH_SWITCH is not set + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +CONFIG_KEXEC=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_SECCOMP is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_GUSA=y +# CONFIG_SPARSE_IRQ is not set + +# +# Boot options +# +CONFIG_ZERO_PAGE_OFFSET=0x00001000 +CONFIG_BOOT_LINK_OFFSET=0x00800000 +CONFIG_ENTRY_OFFSET=0x00001000 +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttySC0,115200" + +# +# Bus options +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options (EXPERIMENTAL) +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_HIBERNATION is not set +CONFIG_PM_RUNTIME=y +# CONFIG_CPU_IDLE is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_GPIO is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_STNIC is not set +CONFIG_SH_ETH=y +# CONFIG_SMC91X is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=6 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_SH_MOBILE=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +CONFIG_USB_R8A66597_HCD=y +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLBFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FTRACE_SYSCALLS=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_SH_STANDARD_BIOS is not set +# CONFIG_EARLY_SCIF_CONSOLE is not set +# CONFIG_DWARF_UNWINDER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/sh/configs/ecovec24_defconfig b/arch/sh/configs/ecovec24_defconfig new file mode 100644 index 000000000000..2050a76683c3 --- /dev/null +++ b/arch/sh/configs/ecovec24_defconfig @@ -0,0 +1,1558 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31-rc7 +# Wed Aug 26 09:09:07 2009 +# +CONFIG_SUPERH=y +CONFIG_SUPERH32=y +# CONFIG_SUPERH64 is not set +CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_IRQ_PER_CPU=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_SYS_SUPPORTS_CMT=y +CONFIG_SYS_SUPPORTS_TMU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_NO_VIRT_TO_BUS=y +CONFIG_ARCH_HAS_DEFAULT_IDLE=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y + +# +# Performance Counters +# +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# System type +# +CONFIG_CPU_SH4=y +CONFIG_CPU_SH4A=y +CONFIG_CPU_SHX2=y +CONFIG_ARCH_SHMOBILE=y +# CONFIG_CPU_SUBTYPE_SH7619 is not set +# CONFIG_CPU_SUBTYPE_SH7201 is not set +# CONFIG_CPU_SUBTYPE_SH7203 is not set +# CONFIG_CPU_SUBTYPE_SH7206 is not set +# CONFIG_CPU_SUBTYPE_SH7263 is not set +# CONFIG_CPU_SUBTYPE_MXG is not set +# CONFIG_CPU_SUBTYPE_SH7705 is not set +# CONFIG_CPU_SUBTYPE_SH7706 is not set +# CONFIG_CPU_SUBTYPE_SH7707 is not set +# CONFIG_CPU_SUBTYPE_SH7708 is not set +# CONFIG_CPU_SUBTYPE_SH7709 is not set +# CONFIG_CPU_SUBTYPE_SH7710 is not set +# CONFIG_CPU_SUBTYPE_SH7712 is not set +# CONFIG_CPU_SUBTYPE_SH7720 is not set +# CONFIG_CPU_SUBTYPE_SH7721 is not set +# CONFIG_CPU_SUBTYPE_SH7750 is not set +# CONFIG_CPU_SUBTYPE_SH7091 is not set +# CONFIG_CPU_SUBTYPE_SH7750R is not set +# CONFIG_CPU_SUBTYPE_SH7750S is not set +# CONFIG_CPU_SUBTYPE_SH7751 is not set +# CONFIG_CPU_SUBTYPE_SH7751R is not set +# CONFIG_CPU_SUBTYPE_SH7760 is not set +# CONFIG_CPU_SUBTYPE_SH4_202 is not set +# CONFIG_CPU_SUBTYPE_SH7723 is not set +CONFIG_CPU_SUBTYPE_SH7724=y +# CONFIG_CPU_SUBTYPE_SH7757 is not set +# CONFIG_CPU_SUBTYPE_SH7763 is not set +# CONFIG_CPU_SUBTYPE_SH7770 is not set +# CONFIG_CPU_SUBTYPE_SH7780 is not set +# CONFIG_CPU_SUBTYPE_SH7785 is not set +# CONFIG_CPU_SUBTYPE_SH7786 is not set +# CONFIG_CPU_SUBTYPE_SHX3 is not set +# CONFIG_CPU_SUBTYPE_SH7343 is not set +# CONFIG_CPU_SUBTYPE_SH7722 is not set +# CONFIG_CPU_SUBTYPE_SH7366 is not set + +# +# Memory management options +# +CONFIG_QUICKLIST=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MEMORY_START=0x08000000 +CONFIG_MEMORY_SIZE=0x08000000 +CONFIG_29BIT=y +# CONFIG_X2TLB is not set +CONFIG_VSYSCALL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_MAX_ACTIVE_REGIONS=1 +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_STATIC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_NR_QUICK=2 +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 + +# +# Cache configuration +# +CONFIG_CACHE_WRITEBACK=y +# CONFIG_CACHE_WRITETHROUGH is not set +# CONFIG_CACHE_OFF is not set + +# +# Processor features +# +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SH_FPU=y +# CONFIG_SH_STORE_QUEUES is not set +CONFIG_CPU_HAS_INTEVT=y +CONFIG_CPU_HAS_SR_RB=y +CONFIG_CPU_HAS_FPU=y + +# +# Board support +# +# CONFIG_SH_7724_SOLUTION_ENGINE is not set +# CONFIG_SH_KFR2R09 is not set +CONFIG_SH_ECOVEC=y + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_TMU=y +# CONFIG_SH_TIMER_CMT is not set +CONFIG_SH_PCLK_FREQ=33333333 +CONFIG_SH_CLK_CPG=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# DMA support +# +# CONFIG_SH_DMA is not set + +# +# Companion Chips +# + +# +# Additional SuperH Device Drivers +# +CONFIG_HEARTBEAT=y +# CONFIG_PUSH_SWITCH is not set + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_SECCOMP=y +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_GUSA=y +# CONFIG_SPARSE_IRQ is not set + +# +# Boot options +# +CONFIG_ZERO_PAGE_OFFSET=0x00001000 +CONFIG_BOOT_LINK_OFFSET=0x00800000 +CONFIG_ENTRY_OFFSET=0x00001000 +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=tty0, console=ttySC0,115200 root=/dev/nfs ip=dhcp mem=120M memchunk.vpu=4m" + +# +# Bus options +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options (EXPERIMENTAL) +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_HIBERNATION is not set +CONFIG_PM_RUNTIME=y +# CONFIG_CPU_IDLE is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_MULTIPLE_TABLES is not set +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_OLD_REGULATORY is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +CONFIG_SMSC_PHY=y +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_GPIO is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_STNIC is not set +CONFIG_SH_ETH=y +# CONFIG_SMC91X is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_SH_KEYSC=y +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=6 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_SH_MOBILE=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_SH_SCI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_REGULATOR is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_CONTIG=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +CONFIG_SOC_CAMERA=y +# CONFIG_SOC_CAMERA_MT9M001 is not set +# CONFIG_SOC_CAMERA_MT9M111 is not set +# CONFIG_SOC_CAMERA_MT9T031 is not set +# CONFIG_SOC_CAMERA_MT9V022 is not set +# CONFIG_SOC_CAMERA_TW9910 is not set +# CONFIG_SOC_CAMERA_PLATFORM is not set +# CONFIG_SOC_CAMERA_OV772X is not set +CONFIG_VIDEO_SH_MOBILE_CEU=y +# CONFIG_V4L_USB_DRIVERS is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_USB_DSBR is not set +# CONFIG_USB_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_SH_MOBILE_LCDC=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_SUPERH_MONO is not set +# CONFIG_LOGO_SUPERH_VGA16 is not set +CONFIG_LOGO_SUPERH_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +CONFIG_USB_R8A66597_HCD=y +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_SPI=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +CONFIG_RTC_DRV_PCF8563=y +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SH is not set +# CONFIG_RTC_DRV_GENERIC is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_PDRV is not set +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_SERCOS3 is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLBFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FTRACE_SYSCALLS=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_SH_STANDARD_BIOS is not set +# CONFIG_EARLY_SCIF_CONSOLE is not set +# CONFIG_DWARF_UNWINDER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_CRC7=y +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/sh/configs/kfr2r09-romimage_defconfig b/arch/sh/configs/kfr2r09-romimage_defconfig new file mode 100644 index 000000000000..c0f9263e1387 --- /dev/null +++ b/arch/sh/configs/kfr2r09-romimage_defconfig @@ -0,0 +1,774 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31-rc6 +# Thu Aug 20 15:09:16 2009 +# +CONFIG_SUPERH=y +CONFIG_SUPERH32=y +# CONFIG_SUPERH64 is not set +CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_IRQ_PER_CPU=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_SYS_SUPPORTS_CMT=y +CONFIG_SYS_SUPPORTS_TMU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_NO_VIRT_TO_BUS=y +CONFIG_ARCH_HAS_DEFAULT_IDLE=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y + +# +# Performance Counters +# +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +# CONFIG_BLOCK is not set +# CONFIG_FREEZER is not set + +# +# System type +# +CONFIG_CPU_SH4=y +CONFIG_CPU_SH4A=y +CONFIG_CPU_SHX2=y +CONFIG_ARCH_SHMOBILE=y +# CONFIG_CPU_SUBTYPE_SH7619 is not set +# CONFIG_CPU_SUBTYPE_SH7201 is not set +# CONFIG_CPU_SUBTYPE_SH7203 is not set +# CONFIG_CPU_SUBTYPE_SH7206 is not set +# CONFIG_CPU_SUBTYPE_SH7263 is not set +# CONFIG_CPU_SUBTYPE_MXG is not set +# CONFIG_CPU_SUBTYPE_SH7705 is not set +# CONFIG_CPU_SUBTYPE_SH7706 is not set +# CONFIG_CPU_SUBTYPE_SH7707 is not set +# CONFIG_CPU_SUBTYPE_SH7708 is not set +# CONFIG_CPU_SUBTYPE_SH7709 is not set +# CONFIG_CPU_SUBTYPE_SH7710 is not set +# CONFIG_CPU_SUBTYPE_SH7712 is not set +# CONFIG_CPU_SUBTYPE_SH7720 is not set +# CONFIG_CPU_SUBTYPE_SH7721 is not set +# CONFIG_CPU_SUBTYPE_SH7750 is not set +# CONFIG_CPU_SUBTYPE_SH7091 is not set +# CONFIG_CPU_SUBTYPE_SH7750R is not set +# CONFIG_CPU_SUBTYPE_SH7750S is not set +# CONFIG_CPU_SUBTYPE_SH7751 is not set +# CONFIG_CPU_SUBTYPE_SH7751R is not set +# CONFIG_CPU_SUBTYPE_SH7760 is not set +# CONFIG_CPU_SUBTYPE_SH4_202 is not set +# CONFIG_CPU_SUBTYPE_SH7723 is not set +CONFIG_CPU_SUBTYPE_SH7724=y +# CONFIG_CPU_SUBTYPE_SH7763 is not set +# CONFIG_CPU_SUBTYPE_SH7770 is not set +# CONFIG_CPU_SUBTYPE_SH7780 is not set +# CONFIG_CPU_SUBTYPE_SH7785 is not set +# CONFIG_CPU_SUBTYPE_SH7786 is not set +# CONFIG_CPU_SUBTYPE_SHX3 is not set +# CONFIG_CPU_SUBTYPE_SH7343 is not set +# CONFIG_CPU_SUBTYPE_SH7722 is not set +# CONFIG_CPU_SUBTYPE_SH7366 is not set + +# +# Memory management options +# +CONFIG_QUICKLIST=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MEMORY_START=0x08000000 +CONFIG_MEMORY_SIZE=0x08000000 +CONFIG_29BIT=y +# CONFIG_X2TLB is not set +CONFIG_VSYSCALL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_MAX_ACTIVE_REGIONS=1 +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_STATIC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_NR_QUICK=2 +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 + +# +# Cache configuration +# +CONFIG_CACHE_WRITEBACK=y +# CONFIG_CACHE_WRITETHROUGH is not set +# CONFIG_CACHE_OFF is not set + +# +# Processor features +# +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SH_FPU=y +# CONFIG_SH_STORE_QUEUES is not set +CONFIG_CPU_HAS_INTEVT=y +CONFIG_CPU_HAS_SR_RB=y +CONFIG_CPU_HAS_FPU=y + +# +# Board support +# +# CONFIG_SH_7724_SOLUTION_ENGINE is not set +CONFIG_SH_KFR2R09=y +# CONFIG_SH_ECOVEC is not set + +# +# Timer and clock configuration +# +# CONFIG_SH_TIMER_TMU is not set +CONFIG_SH_TIMER_CMT=y +CONFIG_SH_PCLK_FREQ=33333333 +CONFIG_SH_CLK_CPG=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# DMA support +# +# CONFIG_SH_DMA is not set + +# +# Companion Chips +# + +# +# Additional SuperH Device Drivers +# +# CONFIG_HEARTBEAT is not set +# CONFIG_PUSH_SWITCH is not set + +# +# Kernel features +# +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_KEXEC=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_SECCOMP is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_GUSA=y +# CONFIG_SPARSE_IRQ is not set + +# +# Boot options +# +CONFIG_ZERO_PAGE_OFFSET=0x00001000 +CONFIG_BOOT_LINK_OFFSET=0x00800000 +CONFIG_ENTRY_OFFSET=0x00001000 +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttySC1,115200 quiet" + +# +# Bus options +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options (EXPERIMENTAL) +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_CPU_IDLE is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y + +# +# SCSI device support +# +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=6 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_SH_MOBILE=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +CONFIG_USB_GADGET_R8A66597=y +CONFIG_USB_R8A66597=y +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_CDC_COMPOSITE=y + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLBFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FTRACE_SYSCALLS=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_SH_STANDARD_BIOS is not set +# CONFIG_EARLY_SCIF_CONSOLE is not set +# CONFIG_DWARF_UNWINDER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/sh/configs/kfr2r09_defconfig b/arch/sh/configs/kfr2r09_defconfig new file mode 100644 index 000000000000..cef61319d2f4 --- /dev/null +++ b/arch/sh/configs/kfr2r09_defconfig @@ -0,0 +1,1059 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31-rc6 +# Thu Aug 20 21:58:52 2009 +# +CONFIG_SUPERH=y +CONFIG_SUPERH32=y +# CONFIG_SUPERH64 is not set +CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_IRQ_PER_CPU=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_SYS_SUPPORTS_CMT=y +CONFIG_SYS_SUPPORTS_TMU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_NO_VIRT_TO_BUS=y +CONFIG_ARCH_HAS_DEFAULT_IDLE=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y + +# +# Performance Counters +# +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_FREEZER is not set + +# +# System type +# +CONFIG_CPU_SH4=y +CONFIG_CPU_SH4A=y +CONFIG_CPU_SHX2=y +CONFIG_ARCH_SHMOBILE=y +# CONFIG_CPU_SUBTYPE_SH7619 is not set +# CONFIG_CPU_SUBTYPE_SH7201 is not set +# CONFIG_CPU_SUBTYPE_SH7203 is not set +# CONFIG_CPU_SUBTYPE_SH7206 is not set +# CONFIG_CPU_SUBTYPE_SH7263 is not set +# CONFIG_CPU_SUBTYPE_MXG is not set +# CONFIG_CPU_SUBTYPE_SH7705 is not set +# CONFIG_CPU_SUBTYPE_SH7706 is not set +# CONFIG_CPU_SUBTYPE_SH7707 is not set +# CONFIG_CPU_SUBTYPE_SH7708 is not set +# CONFIG_CPU_SUBTYPE_SH7709 is not set +# CONFIG_CPU_SUBTYPE_SH7710 is not set +# CONFIG_CPU_SUBTYPE_SH7712 is not set +# CONFIG_CPU_SUBTYPE_SH7720 is not set +# CONFIG_CPU_SUBTYPE_SH7721 is not set +# CONFIG_CPU_SUBTYPE_SH7750 is not set +# CONFIG_CPU_SUBTYPE_SH7091 is not set +# CONFIG_CPU_SUBTYPE_SH7750R is not set +# CONFIG_CPU_SUBTYPE_SH7750S is not set +# CONFIG_CPU_SUBTYPE_SH7751 is not set +# CONFIG_CPU_SUBTYPE_SH7751R is not set +# CONFIG_CPU_SUBTYPE_SH7760 is not set +# CONFIG_CPU_SUBTYPE_SH4_202 is not set +# CONFIG_CPU_SUBTYPE_SH7723 is not set +CONFIG_CPU_SUBTYPE_SH7724=y +# CONFIG_CPU_SUBTYPE_SH7763 is not set +# CONFIG_CPU_SUBTYPE_SH7770 is not set +# CONFIG_CPU_SUBTYPE_SH7780 is not set +# CONFIG_CPU_SUBTYPE_SH7785 is not set +# CONFIG_CPU_SUBTYPE_SH7786 is not set +# CONFIG_CPU_SUBTYPE_SHX3 is not set +# CONFIG_CPU_SUBTYPE_SH7343 is not set +# CONFIG_CPU_SUBTYPE_SH7722 is not set +# CONFIG_CPU_SUBTYPE_SH7366 is not set + +# +# Memory management options +# +CONFIG_QUICKLIST=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MEMORY_START=0x08000000 +CONFIG_MEMORY_SIZE=0x08000000 +CONFIG_29BIT=y +# CONFIG_X2TLB is not set +CONFIG_VSYSCALL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_MAX_ACTIVE_REGIONS=1 +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_STATIC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_NR_QUICK=2 +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 + +# +# Cache configuration +# +CONFIG_CACHE_WRITEBACK=y +# CONFIG_CACHE_WRITETHROUGH is not set +# CONFIG_CACHE_OFF is not set + +# +# Processor features +# +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SH_FPU=y +# CONFIG_SH_STORE_QUEUES is not set +CONFIG_CPU_HAS_INTEVT=y +CONFIG_CPU_HAS_SR_RB=y +CONFIG_CPU_HAS_FPU=y + +# +# Board support +# +# CONFIG_SH_7724_SOLUTION_ENGINE is not set +CONFIG_SH_KFR2R09=y +# CONFIG_SH_ECOVEC is not set + +# +# Timer and clock configuration +# +# CONFIG_SH_TIMER_TMU is not set +CONFIG_SH_TIMER_CMT=y +CONFIG_SH_PCLK_FREQ=33333333 +CONFIG_SH_CLK_CPG=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# DMA support +# +# CONFIG_SH_DMA is not set + +# +# Companion Chips +# + +# +# Additional SuperH Device Drivers +# +# CONFIG_HEARTBEAT is not set +# CONFIG_PUSH_SWITCH is not set + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +CONFIG_HZ_1000=y +CONFIG_HZ=1000 +# CONFIG_SCHED_HRTICK is not set +CONFIG_KEXEC=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_SECCOMP is not set +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_GUSA=y +# CONFIG_SPARSE_IRQ is not set + +# +# Boot options +# +CONFIG_ZERO_PAGE_OFFSET=0x00001000 +CONFIG_BOOT_LINK_OFFSET=0x00800000 +CONFIG_ENTRY_OFFSET=0x00001000 +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=tty0 console=ttySC1,115200" + +# +# Bus options +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options (EXPERIMENTAL) +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_HIBERNATION is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_SH_KEYSC=y +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=6 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_SH_MOBILE=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_SH_MOBILE_LCDC=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +CONFIG_FONT_MINI_4x6=y +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_SUPERH_MONO is not set +CONFIG_LOGO_SUPERH_VGA16=y +# CONFIG_LOGO_SUPERH_CLUT224 is not set +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +CONFIG_USB_GADGET_R8A66597=y +CONFIG_USB_R8A66597=y +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_CDC_COMPOSITE=y + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SH=y +# CONFIG_RTC_DRV_GENERIC is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_PDRV is not set +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_SERCOS3 is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLBFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FTRACE_SYSCALLS=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_SH_STANDARD_BIOS is not set +# CONFIG_EARLY_SCIF_CONSOLE is not set +# CONFIG_DWARF_UNWINDER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/sh/configs/snapgear_defconfig b/arch/sh/configs/snapgear_defconfig index ca3c88a88021..2be2d75adbb7 100644 --- a/arch/sh/configs/snapgear_defconfig +++ b/arch/sh/configs/snapgear_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30 -# Thu Jun 18 13:11:58 2009 +# Linux kernel version: 2.6.31-rc6 +# Thu Aug 20 15:03:04 2009 # CONFIG_SUPERH=y CONFIG_SUPERH32=y @@ -14,6 +14,7 @@ CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_IRQ_PER_CPU=y # CONFIG_GENERIC_GPIO is not set CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y @@ -28,7 +29,9 @@ CONFIG_HAVE_LATENCYTOP_SUPPORT=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_ARCH_NO_VIRT_TO_BUS=y CONFIG_ARCH_HAS_DEFAULT_IDLE=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -38,6 +41,12 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set # CONFIG_SWAP is not set # CONFIG_SYSVIPC is not set # CONFIG_POSIX_MQUEUE is not set @@ -86,10 +95,12 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y # # Performance Counters # +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y # CONFIG_STRIP_ASM_SYMS is not set @@ -106,6 +117,10 @@ CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_CLK=y CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# # CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y @@ -113,7 +128,7 @@ CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 # CONFIG_MODULES is not set CONFIG_BLOCK=y -# CONFIG_LBD is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -534,7 +549,11 @@ CONFIG_HAVE_IDE=y # # -# Enable only one of the two stacks, unless you know what you are doing +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set @@ -686,6 +705,11 @@ CONFIG_LEGACY_PTY_COUNT=256 CONFIG_DEVPORT=y # CONFIG_I2C is not set # CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set @@ -732,7 +756,44 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +CONFIG_RTC_DRV_DS1302=y +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SH is not set +# CONFIG_RTC_DRV_GENERIC is not set # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set @@ -754,6 +815,7 @@ CONFIG_EXT2_FS=y # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set CONFIG_FILE_LOCKING=y @@ -856,8 +918,11 @@ CONFIG_FRAME_WARN=1024 # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FTRACE_SYSCALLS=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_DMA_API_DEBUG is not set @@ -865,6 +930,7 @@ CONFIG_TRACING_SUPPORT=y CONFIG_HAVE_ARCH_KGDB=y # CONFIG_SH_STANDARD_BIOS is not set # CONFIG_EARLY_SCIF_CONSOLE is not set +# CONFIG_DWARF_UNWINDER is not set # # Security options @@ -893,5 +959,6 @@ CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y CONFIG_NLATTR=y CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig index 63e9dd30b41c..b91fa8dbf047 100644 --- a/arch/sh/drivers/dma/Kconfig +++ b/arch/sh/drivers/dma/Kconfig @@ -27,12 +27,12 @@ config NR_ONCHIP_DMA_CHANNELS default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \ CPU_SUBTYPE_SH7760 default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || \ - CPU_SUBTYPE_SH7785 + CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7724 default "6" help This allows you to specify the number of channels that the on-chip - DMAC supports. This will be 4 for SH7091/SH7750/SH7751 and 8 for the - SH7750R/SH7751R. + DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the + SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6. config NR_DMA_CHANNELS_BOOL depends on SH_DMA diff --git a/arch/sh/drivers/heartbeat.c b/arch/sh/drivers/heartbeat.c index 938817e34e2b..a9339a6174fc 100644 --- a/arch/sh/drivers/heartbeat.c +++ b/arch/sh/drivers/heartbeat.c @@ -40,14 +40,19 @@ static inline void heartbeat_toggle_bit(struct heartbeat_data *hd, if (inverted) new = ~new; + new &= hd->mask; + switch (hd->regsize) { case 32: + new |= ioread32(hd->base) & ~hd->mask; iowrite32(new, hd->base); break; case 16: + new |= ioread16(hd->base) & ~hd->mask; iowrite16(new, hd->base); break; default: + new |= ioread8(hd->base) & ~hd->mask; iowrite8(new, hd->base); break; } @@ -72,6 +77,7 @@ static int heartbeat_drv_probe(struct platform_device *pdev) { struct resource *res; struct heartbeat_data *hd; + int i; if (unlikely(pdev->num_resources != 1)) { dev_err(&pdev->dev, "invalid number of resources\n"); @@ -107,6 +113,10 @@ static int heartbeat_drv_probe(struct platform_device *pdev) hd->nr_bits = ARRAY_SIZE(default_bit_pos); } + hd->mask = 0; + for (i = 0; i < hd->nr_bits; i++) + hd->mask |= (1 << hd->bit_pos[i]); + if (!hd->regsize) hd->regsize = 8; /* default access size */ diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index 9a1c423ad167..c481df639022 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -295,6 +295,8 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, vma->vm_page_prot); } +#ifndef CONFIG_GENERIC_IOMAP + static void __iomem *ioport_map_pci(struct pci_dev *dev, unsigned long port, unsigned int nr) { @@ -346,6 +348,8 @@ void pci_iounmap(struct pci_dev *dev, void __iomem *addr) } EXPORT_SYMBOL(pci_iounmap); +#endif /* CONFIG_GENERIC_IOMAP */ + #ifdef CONFIG_HOTPLUG EXPORT_SYMBOL(pcibios_resource_to_bus); EXPORT_SYMBOL(pcibios_bus_to_resource); diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild index 43910cdf78a5..e121c30f797d 100644 --- a/arch/sh/include/asm/Kbuild +++ b/arch/sh/include/asm/Kbuild @@ -1,6 +1,6 @@ include include/asm-generic/Kbuild.asm -header-y += cpu-features.h +header-y += cachectl.h cpu-features.h unifdef-y += unistd_32.h unifdef-y += unistd_64.h diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h index c01718040166..d02c01b3e6b9 100644 --- a/arch/sh/include/asm/bug.h +++ b/arch/sh/include/asm/bug.h @@ -2,6 +2,7 @@ #define __ASM_SH_BUG_H #define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */ +#define BUGFLAG_UNWINDER (1 << 1) #ifdef CONFIG_GENERIC_BUG #define HAVE_ARCH_BUG @@ -72,6 +73,36 @@ do { \ unlikely(__ret_warn_on); \ }) +#define UNWINDER_BUG() \ +do { \ + __asm__ __volatile__ ( \ + "1:\t.short %O0\n" \ + _EMIT_BUG_ENTRY \ + : \ + : "n" (TRAPA_BUG_OPCODE), \ + "i" (__FILE__), \ + "i" (__LINE__), \ + "i" (BUGFLAG_UNWINDER), \ + "i" (sizeof(struct bug_entry))); \ +} while (0) + +#define UNWINDER_BUG_ON(x) ({ \ + int __ret_unwinder_on = !!(x); \ + if (__builtin_constant_p(__ret_unwinder_on)) { \ + if (__ret_unwinder_on) \ + UNWINDER_BUG(); \ + } else { \ + if (unlikely(__ret_unwinder_on)) \ + UNWINDER_BUG(); \ + } \ + unlikely(__ret_unwinder_on); \ +}) + +#else + +#define UNWINDER_BUG BUG +#define UNWINDER_BUG_ON BUG_ON + #endif /* CONFIG_GENERIC_BUG */ #include <asm-generic/bug.h> diff --git a/arch/sh/include/asm/bugs.h b/arch/sh/include/asm/bugs.h index 4924ff6f5439..46260fcbdf4b 100644 --- a/arch/sh/include/asm/bugs.h +++ b/arch/sh/include/asm/bugs.h @@ -21,25 +21,25 @@ static void __init check_bugs(void) current_cpu_data.loops_per_jiffy = loops_per_jiffy; - switch (current_cpu_data.type) { - case CPU_SH7619: + switch (current_cpu_data.family) { + case CPU_FAMILY_SH2: *p++ = '2'; break; - case CPU_SH7201 ... CPU_MXG: + case CPU_FAMILY_SH2A: *p++ = '2'; *p++ = 'a'; break; - case CPU_SH7705 ... CPU_SH7729: + case CPU_FAMILY_SH3: *p++ = '3'; break; - case CPU_SH7750 ... CPU_SH4_501: + case CPU_FAMILY_SH4: *p++ = '4'; break; - case CPU_SH7763 ... CPU_SHX3: + case CPU_FAMILY_SH4A: *p++ = '4'; *p++ = 'a'; break; - case CPU_SH7343 ... CPU_SH7366: + case CPU_FAMILY_SH4AL_DSP: *p++ = '4'; *p++ = 'a'; *p++ = 'l'; @@ -48,15 +48,15 @@ static void __init check_bugs(void) *p++ = 's'; *p++ = 'p'; break; - case CPU_SH5_101 ... CPU_SH5_103: + case CPU_FAMILY_SH5: *p++ = '6'; *p++ = '4'; break; - case CPU_SH_NONE: + case CPU_FAMILY_UNKNOWN: /* - * Specifically use CPU_SH_NONE rather than default:, - * so we're able to have the compiler whine about - * unhandled enumerations. + * Specifically use CPU_FAMILY_UNKNOWN rather than + * default:, so we're able to have the compiler whine + * about unhandled enumerations. */ break; } diff --git a/arch/sh/include/asm/cachectl.h b/arch/sh/include/asm/cachectl.h new file mode 100644 index 000000000000..6ffb4b7a212e --- /dev/null +++ b/arch/sh/include/asm/cachectl.h @@ -0,0 +1,19 @@ +#ifndef _SH_CACHECTL_H +#define _SH_CACHECTL_H + +/* Definitions for the cacheflush system call. */ + +#define CACHEFLUSH_D_INVAL 0x1 /* invalidate (without write back) */ +#define CACHEFLUSH_D_WB 0x2 /* write back (without invalidate) */ +#define CACHEFLUSH_D_PURGE 0x3 /* writeback and invalidate */ + +#define CACHEFLUSH_I 0x4 + +/* + * Options for cacheflush system call + */ +#define ICACHE CACHEFLUSH_I /* flush instruction cache */ +#define DCACHE CACHEFLUSH_D_PURGE /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +#endif /* _SH_CACHECTL_H */ diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h index 4c5462daa74c..c29918f3c819 100644 --- a/arch/sh/include/asm/cacheflush.h +++ b/arch/sh/include/asm/cacheflush.h @@ -3,45 +3,65 @@ #ifdef __KERNEL__ -#ifdef CONFIG_CACHE_OFF +#include <linux/mm.h> + /* - * Nothing to do when the cache is disabled, initial flush and explicit - * disabling is handled at CPU init time. + * Cache flushing: + * + * - flush_cache_all() flushes entire cache + * - flush_cache_mm(mm) flushes the specified mm context's cache lines + * - flush_cache_dup mm(mm) handles cache flushing when forking + * - flush_cache_page(mm, vmaddr, pfn) flushes a single page + * - flush_cache_range(vma, start, end) flushes a range of pages * - * See arch/sh/kernel/cpu/init.c:cache_init(). + * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache + * - flush_icache_range(start, end) flushes(invalidates) a range for icache + * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache + * - flush_cache_sigtramp(vaddr) flushes the signal trampoline */ -#define p3_cache_init() do { } while (0) -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) -#define flush_dcache_page(page) do { } while (0) -#define flush_icache_range(start, end) do { } while (0) -#define flush_icache_page(vma,pg) do { } while (0) -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_cache_sigtramp(vaddr) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) -#define __flush_wback_region(start, size) do { (void)(start); } while (0) -#define __flush_purge_region(start, size) do { (void)(start); } while (0) -#define __flush_invalidate_region(start, size) do { (void)(start); } while (0) -#else -#include <cpu/cacheflush.h> +extern void (*local_flush_cache_all)(void *args); +extern void (*local_flush_cache_mm)(void *args); +extern void (*local_flush_cache_dup_mm)(void *args); +extern void (*local_flush_cache_page)(void *args); +extern void (*local_flush_cache_range)(void *args); +extern void (*local_flush_dcache_page)(void *args); +extern void (*local_flush_icache_range)(void *args); +extern void (*local_flush_icache_page)(void *args); +extern void (*local_flush_cache_sigtramp)(void *args); -/* - * Consistent DMA requires that the __flush_xxx() primitives must be set - * for any of the enabled non-coherent caches (most of the UP CPUs), - * regardless of PIPT or VIPT cache configurations. - */ +static inline void cache_noop(void *args) { } + +extern void (*__flush_wback_region)(void *start, int size); +extern void (*__flush_purge_region)(void *start, int size); +extern void (*__flush_invalidate_region)(void *start, int size); + +extern void flush_cache_all(void); +extern void flush_cache_mm(struct mm_struct *mm); +extern void flush_cache_dup_mm(struct mm_struct *mm); +extern void flush_cache_page(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn); +extern void flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end); +extern void flush_dcache_page(struct page *page); +extern void flush_icache_range(unsigned long start, unsigned long end); +extern void flush_icache_page(struct vm_area_struct *vma, + struct page *page); +extern void flush_cache_sigtramp(unsigned long address); + +struct flusher_data { + struct vm_area_struct *vma; + unsigned long addr1, addr2; +}; -/* Flush (write-back only) a region (smaller than a page) */ -extern void __flush_wback_region(void *start, int size); -/* Flush (write-back & invalidate) a region (smaller than a page) */ -extern void __flush_purge_region(void *start, int size); -/* Flush (invalidate only) a region (smaller than a page) */ -extern void __flush_invalidate_region(void *start, int size); -#endif +#define ARCH_HAS_FLUSH_ANON_PAGE +extern void __flush_anon_page(struct page *page, unsigned long); + +static inline void flush_anon_page(struct vm_area_struct *vma, + struct page *page, unsigned long vmaddr) +{ + if (boot_cpu_data.dcache.n_aliases && PageAnon(page)) + __flush_anon_page(page, vmaddr); +} #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE static inline void flush_kernel_dcache_page(struct page *page) @@ -49,7 +69,6 @@ static inline void flush_kernel_dcache_page(struct page *page) flush_dcache_page(page); } -#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_CACHE_OFF) extern void copy_to_user_page(struct vm_area_struct *vma, struct page *page, unsigned long vaddr, void *dst, const void *src, unsigned long len); @@ -57,23 +76,20 @@ extern void copy_to_user_page(struct vm_area_struct *vma, extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page, unsigned long vaddr, void *dst, const void *src, unsigned long len); -#else -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - do { \ - flush_cache_page(vma, vaddr, page_to_pfn(page));\ - memcpy(dst, src, len); \ - flush_icache_user_range(vma, page, vaddr, len); \ - } while (0) - -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - do { \ - flush_cache_page(vma, vaddr, page_to_pfn(page));\ - memcpy(dst, src, len); \ - } while (0) -#endif #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) + +void kmap_coherent_init(void); +void *kmap_coherent(struct page *page, unsigned long addr); +void kunmap_coherent(void *kvaddr); + +#define PG_dcache_dirty PG_arch_1 + +void cpu_cache_init(void); + #endif /* __KERNEL__ */ #endif /* __ASM_SH_CACHEFLUSH_H */ diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h index 8688a88303ee..b16debfe8c1e 100644 --- a/arch/sh/include/asm/device.h +++ b/arch/sh/include/asm/device.h @@ -3,7 +3,9 @@ * * This file is released under the GPLv2 */ -#include <asm-generic/device.h> + +struct dev_archdata { +}; struct platform_device; /* allocate contiguous memory chunk and fill in struct resource */ @@ -12,3 +14,15 @@ int platform_resource_setup_memory(struct platform_device *pdev, void plat_early_device_setup(void); +#define PDEV_ARCHDATA_FLAG_INIT 0 +#define PDEV_ARCHDATA_FLAG_IDLE 1 +#define PDEV_ARCHDATA_FLAG_SUSP 2 + +struct pdev_archdata { + int hwblk_id; +#ifdef CONFIG_PM_RUNTIME + unsigned long flags; + struct list_head entry; + struct mutex mutex; +#endif +}; diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h index 0c8f8e14622a..68a5f4cb0343 100644 --- a/arch/sh/include/asm/dma-sh.h +++ b/arch/sh/include/asm/dma-sh.h @@ -16,6 +16,7 @@ /* DMAOR contorl: The DMAOR access size is different by CPU.*/ #if defined(CONFIG_CPU_SUBTYPE_SH7723) || \ + defined(CONFIG_CPU_SUBTYPE_SH7724) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) #define dmaor_read_reg(n) \ diff --git a/arch/sh/include/asm/dwarf.h b/arch/sh/include/asm/dwarf.h new file mode 100644 index 000000000000..ced6795891a6 --- /dev/null +++ b/arch/sh/include/asm/dwarf.h @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2009 Matt Fleming <matt@console-pimps.org> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#ifndef __ASM_SH_DWARF_H +#define __ASM_SH_DWARF_H + +#ifdef CONFIG_DWARF_UNWINDER + +/* + * DWARF expression operations + */ +#define DW_OP_addr 0x03 +#define DW_OP_deref 0x06 +#define DW_OP_const1u 0x08 +#define DW_OP_const1s 0x09 +#define DW_OP_const2u 0x0a +#define DW_OP_const2s 0x0b +#define DW_OP_const4u 0x0c +#define DW_OP_const4s 0x0d +#define DW_OP_const8u 0x0e +#define DW_OP_const8s 0x0f +#define DW_OP_constu 0x10 +#define DW_OP_consts 0x11 +#define DW_OP_dup 0x12 +#define DW_OP_drop 0x13 +#define DW_OP_over 0x14 +#define DW_OP_pick 0x15 +#define DW_OP_swap 0x16 +#define DW_OP_rot 0x17 +#define DW_OP_xderef 0x18 +#define DW_OP_abs 0x19 +#define DW_OP_and 0x1a +#define DW_OP_div 0x1b +#define DW_OP_minus 0x1c +#define DW_OP_mod 0x1d +#define DW_OP_mul 0x1e +#define DW_OP_neg 0x1f +#define DW_OP_not 0x20 +#define DW_OP_or 0x21 +#define DW_OP_plus 0x22 +#define DW_OP_plus_uconst 0x23 +#define DW_OP_shl 0x24 +#define DW_OP_shr 0x25 +#define DW_OP_shra 0x26 +#define DW_OP_xor 0x27 +#define DW_OP_skip 0x2f +#define DW_OP_bra 0x28 +#define DW_OP_eq 0x29 +#define DW_OP_ge 0x2a +#define DW_OP_gt 0x2b +#define DW_OP_le 0x2c +#define DW_OP_lt 0x2d +#define DW_OP_ne 0x2e +#define DW_OP_lit0 0x30 +#define DW_OP_lit1 0x31 +#define DW_OP_lit2 0x32 +#define DW_OP_lit3 0x33 +#define DW_OP_lit4 0x34 +#define DW_OP_lit5 0x35 +#define DW_OP_lit6 0x36 +#define DW_OP_lit7 0x37 +#define DW_OP_lit8 0x38 +#define DW_OP_lit9 0x39 +#define DW_OP_lit10 0x3a +#define DW_OP_lit11 0x3b +#define DW_OP_lit12 0x3c +#define DW_OP_lit13 0x3d +#define DW_OP_lit14 0x3e +#define DW_OP_lit15 0x3f +#define DW_OP_lit16 0x40 +#define DW_OP_lit17 0x41 +#define DW_OP_lit18 0x42 +#define DW_OP_lit19 0x43 +#define DW_OP_lit20 0x44 +#define DW_OP_lit21 0x45 +#define DW_OP_lit22 0x46 +#define DW_OP_lit23 0x47 +#define DW_OP_lit24 0x48 +#define DW_OP_lit25 0x49 +#define DW_OP_lit26 0x4a +#define DW_OP_lit27 0x4b +#define DW_OP_lit28 0x4c +#define DW_OP_lit29 0x4d +#define DW_OP_lit30 0x4e +#define DW_OP_lit31 0x4f +#define DW_OP_reg0 0x50 +#define DW_OP_reg1 0x51 +#define DW_OP_reg2 0x52 +#define DW_OP_reg3 0x53 +#define DW_OP_reg4 0x54 +#define DW_OP_reg5 0x55 +#define DW_OP_reg6 0x56 +#define DW_OP_reg7 0x57 +#define DW_OP_reg8 0x58 +#define DW_OP_reg9 0x59 +#define DW_OP_reg10 0x5a +#define DW_OP_reg11 0x5b +#define DW_OP_reg12 0x5c +#define DW_OP_reg13 0x5d +#define DW_OP_reg14 0x5e +#define DW_OP_reg15 0x5f +#define DW_OP_reg16 0x60 +#define DW_OP_reg17 0x61 +#define DW_OP_reg18 0x62 +#define DW_OP_reg19 0x63 +#define DW_OP_reg20 0x64 +#define DW_OP_reg21 0x65 +#define DW_OP_reg22 0x66 +#define DW_OP_reg23 0x67 +#define DW_OP_reg24 0x68 +#define DW_OP_reg25 0x69 +#define DW_OP_reg26 0x6a +#define DW_OP_reg27 0x6b +#define DW_OP_reg28 0x6c +#define DW_OP_reg29 0x6d +#define DW_OP_reg30 0x6e +#define DW_OP_reg31 0x6f +#define DW_OP_breg0 0x70 +#define DW_OP_breg1 0x71 +#define DW_OP_breg2 0x72 +#define DW_OP_breg3 0x73 +#define DW_OP_breg4 0x74 +#define DW_OP_breg5 0x75 +#define DW_OP_breg6 0x76 +#define DW_OP_breg7 0x77 +#define DW_OP_breg8 0x78 +#define DW_OP_breg9 0x79 +#define DW_OP_breg10 0x7a +#define DW_OP_breg11 0x7b +#define DW_OP_breg12 0x7c +#define DW_OP_breg13 0x7d +#define DW_OP_breg14 0x7e +#define DW_OP_breg15 0x7f +#define DW_OP_breg16 0x80 +#define DW_OP_breg17 0x81 +#define DW_OP_breg18 0x82 +#define DW_OP_breg19 0x83 +#define DW_OP_breg20 0x84 +#define DW_OP_breg21 0x85 +#define DW_OP_breg22 0x86 +#define DW_OP_breg23 0x87 +#define DW_OP_breg24 0x88 +#define DW_OP_breg25 0x89 +#define DW_OP_breg26 0x8a +#define DW_OP_breg27 0x8b +#define DW_OP_breg28 0x8c +#define DW_OP_breg29 0x8d +#define DW_OP_breg30 0x8e +#define DW_OP_breg31 0x8f +#define DW_OP_regx 0x90 +#define DW_OP_fbreg 0x91 +#define DW_OP_bregx 0x92 +#define DW_OP_piece 0x93 +#define DW_OP_deref_size 0x94 +#define DW_OP_xderef_size 0x95 +#define DW_OP_nop 0x96 +#define DW_OP_push_object_address 0x97 +#define DW_OP_call2 0x98 +#define DW_OP_call4 0x99 +#define DW_OP_call_ref 0x9a +#define DW_OP_form_tls_address 0x9b +#define DW_OP_call_frame_cfa 0x9c +#define DW_OP_bit_piece 0x9d +#define DW_OP_lo_user 0xe0 +#define DW_OP_hi_user 0xff + +/* + * Addresses used in FDE entries in the .eh_frame section may be encoded + * using one of the following encodings. + */ +#define DW_EH_PE_absptr 0x00 +#define DW_EH_PE_omit 0xff +#define DW_EH_PE_uleb128 0x01 +#define DW_EH_PE_udata2 0x02 +#define DW_EH_PE_udata4 0x03 +#define DW_EH_PE_udata8 0x04 +#define DW_EH_PE_sleb128 0x09 +#define DW_EH_PE_sdata2 0x0a +#define DW_EH_PE_sdata4 0x0b +#define DW_EH_PE_sdata8 0x0c +#define DW_EH_PE_signed 0x09 + +#define DW_EH_PE_pcrel 0x10 + +/* + * The architecture-specific register number that contains the return + * address in the .debug_frame table. + */ +#define DWARF_ARCH_RA_REG 17 + +#ifndef __ASSEMBLY__ +/* + * Read either the frame pointer (r14) or the stack pointer (r15). + * NOTE: this MUST be inlined. + */ +static __always_inline unsigned long dwarf_read_arch_reg(unsigned int reg) +{ + unsigned long value = 0; + + switch (reg) { + case 14: + __asm__ __volatile__("mov r14, %0\n" : "=r" (value)); + break; + case 15: + __asm__ __volatile__("mov r15, %0\n" : "=r" (value)); + break; + default: + BUG(); + } + + return value; +} + +/** + * dwarf_cie - Common Information Entry + */ +struct dwarf_cie { + unsigned long length; + unsigned long cie_id; + unsigned char version; + const char *augmentation; + unsigned int code_alignment_factor; + int data_alignment_factor; + + /* Which column in the rule table represents return addr of func. */ + unsigned int return_address_reg; + + unsigned char *initial_instructions; + unsigned char *instructions_end; + + unsigned char encoding; + + unsigned long cie_pointer; + + struct list_head link; + + unsigned long flags; +#define DWARF_CIE_Z_AUGMENTATION (1 << 0) +}; + +/** + * dwarf_fde - Frame Description Entry + */ +struct dwarf_fde { + unsigned long length; + unsigned long cie_pointer; + struct dwarf_cie *cie; + unsigned long initial_location; + unsigned long address_range; + unsigned char *instructions; + unsigned char *end; + struct list_head link; +}; + +/** + * dwarf_frame - DWARF information for a frame in the call stack + */ +struct dwarf_frame { + struct dwarf_frame *prev, *next; + + unsigned long pc; + + struct list_head reg_list; + + unsigned long cfa; + + /* Valid when DW_FRAME_CFA_REG_OFFSET is set in flags */ + unsigned int cfa_register; + unsigned int cfa_offset; + + /* Valid when DW_FRAME_CFA_REG_EXP is set in flags */ + unsigned char *cfa_expr; + unsigned int cfa_expr_len; + + unsigned long flags; +#define DWARF_FRAME_CFA_REG_OFFSET (1 << 0) +#define DWARF_FRAME_CFA_REG_EXP (1 << 1) + + unsigned long return_addr; +}; + +/** + * dwarf_reg - DWARF register + * @flags: Describes how to calculate the value of this register + */ +struct dwarf_reg { + struct list_head link; + + unsigned int number; + + unsigned long addr; + unsigned long flags; +#define DWARF_REG_OFFSET (1 << 0) +#define DWARF_VAL_OFFSET (1 << 1) +#define DWARF_UNDEFINED (1 << 2) +}; + +/* + * Call Frame instruction opcodes. + */ +#define DW_CFA_advance_loc 0x40 +#define DW_CFA_offset 0x80 +#define DW_CFA_restore 0xc0 +#define DW_CFA_nop 0x00 +#define DW_CFA_set_loc 0x01 +#define DW_CFA_advance_loc1 0x02 +#define DW_CFA_advance_loc2 0x03 +#define DW_CFA_advance_loc4 0x04 +#define DW_CFA_offset_extended 0x05 +#define DW_CFA_restore_extended 0x06 +#define DW_CFA_undefined 0x07 +#define DW_CFA_same_value 0x08 +#define DW_CFA_register 0x09 +#define DW_CFA_remember_state 0x0a +#define DW_CFA_restore_state 0x0b +#define DW_CFA_def_cfa 0x0c +#define DW_CFA_def_cfa_register 0x0d +#define DW_CFA_def_cfa_offset 0x0e +#define DW_CFA_def_cfa_expression 0x0f +#define DW_CFA_expression 0x10 +#define DW_CFA_offset_extended_sf 0x11 +#define DW_CFA_def_cfa_sf 0x12 +#define DW_CFA_def_cfa_offset_sf 0x13 +#define DW_CFA_val_offset 0x14 +#define DW_CFA_val_offset_sf 0x15 +#define DW_CFA_val_expression 0x16 +#define DW_CFA_lo_user 0x1c +#define DW_CFA_hi_user 0x3f + +/* GNU extension opcodes */ +#define DW_CFA_GNU_args_size 0x2e +#define DW_CFA_GNU_negative_offset_extended 0x2f + +/* + * Some call frame instructions encode their operands in the opcode. We + * need some helper functions to extract both the opcode and operands + * from an instruction. + */ +static inline unsigned int DW_CFA_opcode(unsigned long insn) +{ + return (insn & 0xc0); +} + +static inline unsigned int DW_CFA_operand(unsigned long insn) +{ + return (insn & 0x3f); +} + +#define DW_EH_FRAME_CIE 0 /* .eh_frame CIE IDs are 0 */ +#define DW_CIE_ID 0xffffffff +#define DW64_CIE_ID 0xffffffffffffffffULL + +/* + * DWARF FDE/CIE length field values. + */ +#define DW_EXT_LO 0xfffffff0 +#define DW_EXT_HI 0xffffffff +#define DW_EXT_DWARF64 DW_EXT_HI + +extern struct dwarf_frame *dwarf_unwind_stack(unsigned long, + struct dwarf_frame *); +#endif /* !__ASSEMBLY__ */ + +#define CFI_STARTPROC .cfi_startproc +#define CFI_ENDPROC .cfi_endproc +#define CFI_DEF_CFA .cfi_def_cfa +#define CFI_REGISTER .cfi_register +#define CFI_REL_OFFSET .cfi_rel_offset +#define CFI_UNDEFINED .cfi_undefined + +#else + +/* + * Use the asm comment character to ignore the rest of the line. + */ +#define CFI_IGNORE ! + +#define CFI_STARTPROC CFI_IGNORE +#define CFI_ENDPROC CFI_IGNORE +#define CFI_DEF_CFA CFI_IGNORE +#define CFI_REGISTER CFI_IGNORE +#define CFI_REL_OFFSET CFI_IGNORE +#define CFI_UNDEFINED CFI_IGNORE + +#ifndef __ASSEMBLY__ +static inline void dwarf_unwinder_init(void) +{ +} +#endif + +#endif /* CONFIG_DWARF_UNWINDER */ + +#endif /* __ASM_SH_DWARF_H */ diff --git a/arch/sh/include/asm/entry-macros.S b/arch/sh/include/asm/entry-macros.S index 3a4752a65722..cc43a55e1fcf 100644 --- a/arch/sh/include/asm/entry-macros.S +++ b/arch/sh/include/asm/entry-macros.S @@ -7,7 +7,7 @@ .endm .macro sti - mov #0xf0, r11 + mov #0xfffffff0, r11 extu.b r11, r11 not r11, r11 stc sr, r10 @@ -31,8 +31,92 @@ #endif .endm +#ifdef CONFIG_TRACE_IRQFLAGS + + .macro TRACE_IRQS_ON + mov.l r0, @-r15 + mov.l r1, @-r15 + mov.l r2, @-r15 + mov.l r3, @-r15 + mov.l r4, @-r15 + mov.l r5, @-r15 + mov.l r6, @-r15 + mov.l r7, @-r15 + + mov.l 7834f, r0 + jsr @r0 + nop + + mov.l @r15+, r7 + mov.l @r15+, r6 + mov.l @r15+, r5 + mov.l @r15+, r4 + mov.l @r15+, r3 + mov.l @r15+, r2 + mov.l @r15+, r1 + mov.l @r15+, r0 + mov.l 7834f, r0 + + bra 7835f + nop + .balign 4 +7834: .long trace_hardirqs_on +7835: + .endm + .macro TRACE_IRQS_OFF + + mov.l r0, @-r15 + mov.l r1, @-r15 + mov.l r2, @-r15 + mov.l r3, @-r15 + mov.l r4, @-r15 + mov.l r5, @-r15 + mov.l r6, @-r15 + mov.l r7, @-r15 + + mov.l 7834f, r0 + jsr @r0 + nop + + mov.l @r15+, r7 + mov.l @r15+, r6 + mov.l @r15+, r5 + mov.l @r15+, r4 + mov.l @r15+, r3 + mov.l @r15+, r2 + mov.l @r15+, r1 + mov.l @r15+, r0 + mov.l 7834f, r0 + + bra 7835f + nop + .balign 4 +7834: .long trace_hardirqs_off +7835: + .endm + +#else + .macro TRACE_IRQS_ON + .endm + + .macro TRACE_IRQS_OFF + .endm +#endif + #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4) # define PREF(x) pref @x #else # define PREF(x) nop #endif + + /* + * Macro for use within assembly. Because the DWARF unwinder + * needs to use the frame register to unwind the stack, we + * need to setup r14 with the value of the stack pointer as + * the return address is usually on the stack somewhere. + */ + .macro setup_frame_reg +#ifdef CONFIG_DWARF_UNWINDER + mov r15, r14 +#endif + .endm diff --git a/arch/sh/include/asm/ftrace.h b/arch/sh/include/asm/ftrace.h index 8fea7d8c8258..12f3a31f20af 100644 --- a/arch/sh/include/asm/ftrace.h +++ b/arch/sh/include/asm/ftrace.h @@ -4,6 +4,7 @@ #ifdef CONFIG_FUNCTION_TRACER #define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ +#define FTRACE_SYSCALL_MAX NR_syscalls #ifndef __ASSEMBLY__ extern void mcount(void); @@ -11,10 +12,13 @@ extern void mcount(void); #define MCOUNT_ADDR ((long)(mcount)) #ifdef CONFIG_DYNAMIC_FTRACE -#define CALLER_ADDR ((long)(ftrace_caller)) +#define CALL_ADDR ((long)(ftrace_call)) #define STUB_ADDR ((long)(ftrace_stub)) +#define GRAPH_ADDR ((long)(ftrace_graph_call)) +#define CALLER_ADDR ((long)(ftrace_caller)) -#define MCOUNT_INSN_OFFSET ((STUB_ADDR - CALLER_ADDR) >> 1) +#define MCOUNT_INSN_OFFSET ((STUB_ADDR - CALL_ADDR) - 4) +#define GRAPH_INSN_OFFSET ((CALLER_ADDR - GRAPH_ADDR) - 4) struct dyn_arch_ftrace { /* No extra data needed on sh */ diff --git a/arch/sh/include/asm/hardirq.h b/arch/sh/include/asm/hardirq.h index 715ee237fc77..a5be4afa790b 100644 --- a/arch/sh/include/asm/hardirq.h +++ b/arch/sh/include/asm/hardirq.h @@ -1,16 +1,9 @@ #ifndef __ASM_SH_HARDIRQ_H #define __ASM_SH_HARDIRQ_H -#include <linux/threads.h> -#include <linux/irq.h> - -/* entry.S is sensitive to the offsets of these fields */ -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ - extern void ack_bad_irq(unsigned int irq); +#define ack_bad_irq ack_bad_irq + +#include <asm-generic/hardirq.h> #endif /* __ASM_SH_HARDIRQ_H */ diff --git a/arch/sh/include/asm/heartbeat.h b/arch/sh/include/asm/heartbeat.h index 724a43ed245e..caaafe5a3ef1 100644 --- a/arch/sh/include/asm/heartbeat.h +++ b/arch/sh/include/asm/heartbeat.h @@ -11,6 +11,7 @@ struct heartbeat_data { unsigned int nr_bits; struct timer_list timer; unsigned int regsize; + unsigned int mask; unsigned long flags; }; diff --git a/arch/sh/include/asm/hwblk.h b/arch/sh/include/asm/hwblk.h new file mode 100644 index 000000000000..5d3ccae4202b --- /dev/null +++ b/arch/sh/include/asm/hwblk.h @@ -0,0 +1,72 @@ +#ifndef __ASM_SH_HWBLK_H +#define __ASM_SH_HWBLK_H + +#include <asm/clock.h> +#include <asm/io.h> + +#define HWBLK_CNT_USAGE 0 +#define HWBLK_CNT_IDLE 1 +#define HWBLK_CNT_DEVICES 2 +#define HWBLK_CNT_NR 3 + +#define HWBLK_AREA_FLAG_PARENT (1 << 0) /* valid parent */ + +#define HWBLK_AREA(_flags, _parent) \ +{ \ + .flags = _flags, \ + .parent = _parent, \ +} + +struct hwblk_area { + int cnt[HWBLK_CNT_NR]; + unsigned char parent; + unsigned char flags; +}; + +#define HWBLK(_mstp, _bit, _area) \ +{ \ + .mstp = (void __iomem *)_mstp, \ + .bit = _bit, \ + .area = _area, \ +} + +struct hwblk { + void __iomem *mstp; + unsigned char bit; + unsigned char area; + int cnt[HWBLK_CNT_NR]; +}; + +struct hwblk_info { + struct hwblk_area *areas; + int nr_areas; + struct hwblk *hwblks; + int nr_hwblks; +}; + +/* Should be defined by processor-specific code */ +int arch_hwblk_init(void); +int arch_hwblk_sleep_mode(void); + +int hwblk_register(struct hwblk_info *info); +int hwblk_init(void); + +void hwblk_enable(struct hwblk_info *info, int hwblk); +void hwblk_disable(struct hwblk_info *info, int hwblk); + +void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int cnt); +void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int cnt); + +/* allow clocks to enable and disable hardware blocks */ +#define SH_HWBLK_CLK(_name, _id, _parent, _hwblk, _flags) \ +{ \ + .name = _name, \ + .id = _id, \ + .parent = _parent, \ + .arch_flags = _hwblk, \ + .flags = _flags, \ +} + +int sh_hwblk_clk_register(struct clk *clks, int nr); + +#endif /* __ASM_SH_HWBLK_H */ diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index 25348141674b..5be45ea4dfec 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -92,8 +92,12 @@ static inline void ctrl_delay(void) { -#ifdef P2SEG +#ifdef CONFIG_CPU_SH4 + __raw_readw(CCN_PVR); +#elif defined(P2SEG) __raw_readw(P2SEG); +#else +#error "Need a dummy address for delay" #endif } @@ -146,6 +150,7 @@ __BUILD_MEMORY_STRING(q, u64) #define readl_relaxed(a) readl(a) #define readq_relaxed(a) readq(a) +#ifndef CONFIG_GENERIC_IOMAP /* Simple MMIO */ #define ioread8(a) __raw_readb(a) #define ioread16(a) __raw_readw(a) @@ -166,6 +171,15 @@ __BUILD_MEMORY_STRING(q, u64) #define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c)) #define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c)) #define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c)) +#endif + +#define mmio_insb(p,d,c) __raw_readsb(p,d,c) +#define mmio_insw(p,d,c) __raw_readsw(p,d,c) +#define mmio_insl(p,d,c) __raw_readsl(p,d,c) + +#define mmio_outsb(p,s,c) __raw_writesb(p,s,c) +#define mmio_outsw(p,s,c) __raw_writesw(p,s,c) +#define mmio_outsl(p,s,c) __raw_writesl(p,s,c) /* synco on SH-4A, otherwise a nop */ #define mmiowb() wmb() diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h index 0b9f896f203c..985219f9759e 100644 --- a/arch/sh/include/asm/kdebug.h +++ b/arch/sh/include/asm/kdebug.h @@ -4,6 +4,7 @@ /* Grossly misnamed. */ enum die_val { DIE_TRAP, + DIE_NMI, DIE_OOPS, }; diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h index 72704ed725e5..4235e228d921 100644 --- a/arch/sh/include/asm/kgdb.h +++ b/arch/sh/include/asm/kgdb.h @@ -30,9 +30,6 @@ static inline void arch_kgdb_breakpoint(void) __asm__ __volatile__ ("trapa #0x3c\n"); } -/* State info */ -extern char in_nmi; /* Debounce flag to prevent NMI reentry*/ - #define BUFMAX 2048 #define CACHE_FLUSH_IS_SAFE 1 diff --git a/arch/sh/include/asm/lmb.h b/arch/sh/include/asm/lmb.h new file mode 100644 index 000000000000..9b437f657ffa --- /dev/null +++ b/arch/sh/include/asm/lmb.h @@ -0,0 +1,6 @@ +#ifndef __ASM_SH_LMB_H +#define __ASM_SH_LMB_H + +#define LMB_REAL_LIMIT 0 + +#endif /* __ASM_SH_LMB_H */ diff --git a/arch/sh/include/asm/mmu_context.h b/arch/sh/include/asm/mmu_context.h index 67d8946db193..41080b173a7a 100644 --- a/arch/sh/include/asm/mmu_context.h +++ b/arch/sh/include/asm/mmu_context.h @@ -69,7 +69,7 @@ static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu) * We exhaust ASID of this version. * Flush all TLB and start new cycle. */ - flush_tlb_all(); + local_flush_tlb_all(); #ifdef CONFIG_SUPERH64 /* diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h index 49592c780a6e..81bffc0d6860 100644 --- a/arch/sh/include/asm/page.h +++ b/arch/sh/include/asm/page.h @@ -50,26 +50,24 @@ extern unsigned long shm_align_mask; extern unsigned long max_low_pfn, min_low_pfn; extern unsigned long memory_start, memory_end; -extern void clear_page(void *to); +static inline unsigned long +pages_do_alias(unsigned long addr1, unsigned long addr2) +{ + return (addr1 ^ addr2) & shm_align_mask; +} + + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) extern void copy_page(void *to, void *from); -#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \ - (defined(CONFIG_CPU_SH5) || defined(CONFIG_CPU_SH4) || \ - defined(CONFIG_SH7705_CACHE_32KB)) struct page; struct vm_area_struct; -extern void clear_user_page(void *to, unsigned long address, struct page *page); -extern void copy_user_page(void *to, void *from, unsigned long address, - struct page *page); -#if defined(CONFIG_CPU_SH4) + extern void copy_user_highpage(struct page *to, struct page *from, unsigned long vaddr, struct vm_area_struct *vma); #define __HAVE_ARCH_COPY_USER_HIGHPAGE -#endif -#else -#define clear_user_page(page, vaddr, pg) clear_page(page) -#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) -#endif +extern void clear_user_highpage(struct page *page, unsigned long vaddr); +#define clear_user_highpage clear_user_highpage /* * These are used to make use of C type-checking.. diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h index 2a011b18090b..4f3efa7d5a64 100644 --- a/arch/sh/include/asm/pgtable.h +++ b/arch/sh/include/asm/pgtable.h @@ -36,6 +36,12 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; #define NEFF_SIGN (1LL << (NEFF - 1)) #define NEFF_MASK (-1LL << NEFF) +static inline unsigned long long neff_sign_extend(unsigned long val) +{ + unsigned long long extended = val; + return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended; +} + #ifdef CONFIG_29BIT #define NPHYS 29 #else @@ -133,27 +139,25 @@ typedef pte_t *pte_addr_t; */ #define pgtable_cache_init() do { } while (0) -#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \ - defined(CONFIG_SH7705_CACHE_32KB)) -struct mm_struct; -#define __HAVE_ARCH_PTEP_GET_AND_CLEAR -pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); -#endif - struct vm_area_struct; -extern void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte); + +extern void __update_cache(struct vm_area_struct *vma, + unsigned long address, pte_t pte); +extern void __update_tlb(struct vm_area_struct *vma, + unsigned long address, pte_t pte); + +static inline void +update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) +{ + __update_cache(vma, address, pte); + __update_tlb(vma, address, pte); +} + extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern void paging_init(void); extern void page_table_range_init(unsigned long start, unsigned long end, pgd_t *pgd); -#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_CPU_SH4) && defined(CONFIG_MMU) -extern void kmap_coherent_init(void); -#else -#define kmap_coherent_init() do { } while (0) -#endif - /* arch/sh/mm/mmap.c */ #define HAVE_ARCH_UNMAPPED_AREA #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h index 72ea209195bd..c0d359ce337b 100644 --- a/arch/sh/include/asm/pgtable_32.h +++ b/arch/sh/include/asm/pgtable_32.h @@ -20,7 +20,7 @@ * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE. * * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages. - * Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused. + * Bit 10 is used for _PAGE_ACCESSED, and bit 11 is used for _PAGE_SPECIAL. * * - On 29 bit platforms, bits 31 to 29 are used for the space attributes * and timing control which (together with bit 0) are moved into the @@ -52,6 +52,7 @@ #define _PAGE_PROTNONE 0x200 /* software: if not present */ #define _PAGE_ACCESSED 0x400 /* software: page referenced */ #define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */ +#define _PAGE_SPECIAL 0x800 /* software: special page */ #define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1) #define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER) @@ -86,6 +87,14 @@ #define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */ #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */ +#ifndef CONFIG_X2TLB +/* copy the ptea attributes */ +static inline unsigned long copy_ptea_attributes(unsigned long x) +{ + return ((x >> 28) & 0xe) | (x & 0x1); +} +#endif + /* Mask which drops unused bits from the PTEL value */ #if defined(CONFIG_CPU_SH3) #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \ @@ -148,8 +157,12 @@ # define _PAGE_SZHUGE (_PAGE_FLAGS_HARD) #endif +/* + * Mask of bits that are to be preserved accross pgprot changes. + */ #define _PAGE_CHG_MASK \ - (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY) + (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | \ + _PAGE_DIRTY | _PAGE_SPECIAL) #ifndef __ASSEMBLY__ @@ -328,7 +341,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte) #define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY) #define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED) #define pte_file(pte) ((pte).pte_low & _PAGE_FILE) -#define pte_special(pte) (0) +#define pte_special(pte) ((pte).pte_low & _PAGE_SPECIAL) #ifdef CONFIG_X2TLB #define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE) @@ -358,8 +371,9 @@ PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY); PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY); PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED); PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED); +PTE_BIT_FUNC(low, mkspecial, |= _PAGE_SPECIAL); -static inline pte_t pte_mkspecial(pte_t pte) { return pte; } +#define __HAVE_ARCH_PTE_SPECIAL /* * Macro and implementation to make a page protection as uncachable. @@ -394,13 +408,19 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) /* to find an entry in a page-table-directory. */ #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) -#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) +#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) +#define __pgd_offset(address) pgd_index(address) /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(address) pgd_offset(&init_mm, address) +#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) +#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) + /* Find an entry in the third-level page table.. */ #define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define __pte_offset(address) pte_index(address) + #define pte_offset_kernel(dir, address) \ ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address)) #define pte_offset_map(dir, address) pte_offset_kernel(dir, address) diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h index c78990cda557..17cdbecc3adc 100644 --- a/arch/sh/include/asm/pgtable_64.h +++ b/arch/sh/include/asm/pgtable_64.h @@ -60,6 +60,9 @@ static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep) /* To find an entry in a kernel PGD. */ #define pgd_offset_k(address) pgd_offset(&init_mm, address) +#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) +#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) + /* * PMD level access routines. Same notes as above. */ @@ -80,6 +83,8 @@ static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep) #define pte_index(address) \ ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define __pte_offset(address) pte_index(address) + #define pte_offset_kernel(dir, addr) \ ((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr))) diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index ff7daaf9a620..017e0c1807b2 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -32,7 +32,7 @@ enum cpu_type { /* SH-4A types */ CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, - CPU_SH7723, CPU_SH7724, CPU_SHX3, + CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3, /* SH4AL-DSP types */ CPU_SH7343, CPU_SH7722, CPU_SH7366, @@ -44,6 +44,17 @@ enum cpu_type { CPU_SH_NONE }; +enum cpu_family { + CPU_FAMILY_SH2, + CPU_FAMILY_SH2A, + CPU_FAMILY_SH3, + CPU_FAMILY_SH4, + CPU_FAMILY_SH4A, + CPU_FAMILY_SH4AL_DSP, + CPU_FAMILY_SH5, + CPU_FAMILY_UNKNOWN, +}; + /* * TLB information structure * @@ -61,7 +72,7 @@ struct tlb_info { }; struct sh_cpuinfo { - unsigned int type; + unsigned int type, family; int cut_major, cut_minor; unsigned long loops_per_jiffy; unsigned long asid_cache; diff --git a/arch/sh/include/asm/romimage-macros.h b/arch/sh/include/asm/romimage-macros.h new file mode 100644 index 000000000000..ae17a150bb58 --- /dev/null +++ b/arch/sh/include/asm/romimage-macros.h @@ -0,0 +1,73 @@ +#ifndef __ROMIMAGE_MACRO_H +#define __ROMIMAGE_MACRO_H + +/* The LIST command is used to include comments in the script */ +.macro LIST comment +.endm + +/* The ED command is used to write a 32-bit word */ +.macro ED, addr, data + mov.l 1f, r1 + mov.l 2f, r0 + mov.l r0, @r1 + bra 3f + nop + .align 2 +1 : .long \addr +2 : .long \data +3 : +.endm + +/* The EW command is used to write a 16-bit word */ +.macro EW, addr, data + mov.l 1f, r1 + mov.l 2f, r0 + mov.w r0, @r1 + bra 3f + nop + .align 2 +1 : .long \addr +2 : .long \data +3 : +.endm + +/* The EB command is used to write an 8-bit word */ +.macro EB, addr, data + mov.l 1f, r1 + mov.l 2f, r0 + mov.b r0, @r1 + bra 3f + nop + .align 2 +1 : .long \addr +2 : .long \data +3 : +.endm + +/* The WAIT command is used to delay the execution */ +.macro WAIT, time + mov.l 2f, r3 +1 : + nop + tst r3, r3 + bf/s 1b + dt r3 + bra 3f + nop + .align 2 +2 : .long \time * 100 +3 : +.endm + +/* The DD command is used to read a 32-bit word */ +.macro DD, addr, addr2, nr + mov.l 1f, r1 + mov.l @r1, r0 + bra 2f + nop + .align 2 +1 : .long \addr +2 : +.endm + +#endif /* __ROMIMAGE_MACRO_H */ diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h index 01a4076a3719..a78701da775b 100644 --- a/arch/sh/include/asm/sections.h +++ b/arch/sh/include/asm/sections.h @@ -7,6 +7,7 @@ extern void __nosave_begin, __nosave_end; extern long __machvec_start, __machvec_end; extern char __uncached_start, __uncached_end; extern char _ebss[]; +extern char __start_eh_frame[], __stop_eh_frame[]; #endif /* __ASM_SH_SECTIONS_H */ diff --git a/arch/sh/include/asm/sh_keysc.h b/arch/sh/include/asm/sh_keysc.h index b5a4dd5a9729..4a65b1e40eab 100644 --- a/arch/sh/include/asm/sh_keysc.h +++ b/arch/sh/include/asm/sh_keysc.h @@ -7,6 +7,7 @@ struct sh_keysc_info { enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode; int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */ int delay; + int kycr2_delay; int keycodes[SH_KEYSC_MAXKEYS]; }; diff --git a/arch/sh/include/asm/stacktrace.h b/arch/sh/include/asm/stacktrace.h new file mode 100644 index 000000000000..797018213718 --- /dev/null +++ b/arch/sh/include/asm/stacktrace.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009 Matt Fleming + * + * Based on: + * The x86 implementation - arch/x86/include/asm/stacktrace.h + */ +#ifndef _ASM_SH_STACKTRACE_H +#define _ASM_SH_STACKTRACE_H + +/* Generic stack tracer with callbacks */ + +struct stacktrace_ops { + void (*warning)(void *data, char *msg); + /* msg must contain %s for the symbol */ + void (*warning_symbol)(void *data, char *msg, unsigned long symbol); + void (*address)(void *data, unsigned long address, int reliable); + /* On negative return stop dumping */ + int (*stack)(void *data, char *name); +}; + +void dump_trace(struct task_struct *tsk, struct pt_regs *regs, + unsigned long *stack, + const struct stacktrace_ops *ops, void *data); + +#endif /* _ASM_SH_STACKTRACE_H */ diff --git a/arch/sh/include/asm/suspend.h b/arch/sh/include/asm/suspend.h index b1b995370e79..5c8ea28ff7a4 100644 --- a/arch/sh/include/asm/suspend.h +++ b/arch/sh/include/asm/suspend.h @@ -10,6 +10,15 @@ struct swsusp_arch_regs { struct pt_regs user_regs; unsigned long bank1_regs[8]; }; + +void sh_mobile_call_standby(unsigned long mode); + +#ifdef CONFIG_CPU_IDLE +void sh_mobile_setup_cpuidle(void); +#else +static inline void sh_mobile_setup_cpuidle(void) {} +#endif + #endif /* flags passed to assembly suspend code */ diff --git a/arch/sh/include/asm/syscall_32.h b/arch/sh/include/asm/syscall_32.h index 6f83f2cc45c1..7d80df4f09cb 100644 --- a/arch/sh/include/asm/syscall_32.h +++ b/arch/sh/include/asm/syscall_32.h @@ -65,6 +65,7 @@ static inline void syscall_get_arguments(struct task_struct *task, case 3: args[2] = regs->regs[6]; case 2: args[1] = regs->regs[5]; case 1: args[0] = regs->regs[4]; + case 0: break; default: BUG(); diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h index ab79e1f4fbe0..b5c5acdc8c0e 100644 --- a/arch/sh/include/asm/system.h +++ b/arch/sh/include/asm/system.h @@ -14,18 +14,6 @@ #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */ -#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5) -#define __icbi() \ -{ \ - unsigned long __addr; \ - __addr = 0xa8000000; \ - __asm__ __volatile__( \ - "icbi %0\n\t" \ - : /* no output */ \ - : "m" (__m(__addr))); \ -} -#endif - /* * A brief note on ctrl_barrier(), the control register write barrier. * @@ -44,7 +32,7 @@ #define mb() __asm__ __volatile__ ("synco": : :"memory") #define rmb() mb() #define wmb() __asm__ __volatile__ ("synco": : :"memory") -#define ctrl_barrier() __icbi() +#define ctrl_barrier() __icbi(0xa8000000) #define read_barrier_depends() do { } while(0) #else #define mb() __asm__ __volatile__ ("": : :"memory") @@ -181,6 +169,11 @@ BUILD_TRAP_HANDLER(breakpoint); BUILD_TRAP_HANDLER(singlestep); BUILD_TRAP_HANDLER(fpu_error); BUILD_TRAP_HANDLER(fpu_state_restore); +BUILD_TRAP_HANDLER(nmi); + +#ifdef CONFIG_BUG +extern void handle_BUG(struct pt_regs *); +#endif #define arch_align_stack(x) (x) diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h index 6c68a51f1cc5..607d413f6168 100644 --- a/arch/sh/include/asm/system_32.h +++ b/arch/sh/include/asm/system_32.h @@ -14,12 +14,12 @@ do { \ (u32 *)&tsk->thread.dsp_status; \ __asm__ __volatile__ ( \ ".balign 4\n\t" \ + "movs.l @r2+, a0\n\t" \ "movs.l @r2+, a1\n\t" \ "movs.l @r2+, a0g\n\t" \ "movs.l @r2+, a1g\n\t" \ "movs.l @r2+, m0\n\t" \ "movs.l @r2+, m1\n\t" \ - "movs.l @r2+, a0\n\t" \ "movs.l @r2+, x0\n\t" \ "movs.l @r2+, x1\n\t" \ "movs.l @r2+, y0\n\t" \ @@ -39,20 +39,20 @@ do { \ \ __asm__ __volatile__ ( \ ".balign 4\n\t" \ - "stc.l mod, @-r2\n\t" \ + "stc.l mod, @-r2\n\t" \ "stc.l re, @-r2\n\t" \ "stc.l rs, @-r2\n\t" \ - "sts.l dsr, @-r2\n\t" \ - "sts.l y1, @-r2\n\t" \ - "sts.l y0, @-r2\n\t" \ - "sts.l x1, @-r2\n\t" \ - "sts.l x0, @-r2\n\t" \ - "sts.l a0, @-r2\n\t" \ - ".word 0xf653 ! movs.l a1, @-r2\n\t" \ - ".word 0xf6f3 ! movs.l a0g, @-r2\n\t" \ - ".word 0xf6d3 ! movs.l a1g, @-r2\n\t" \ - ".word 0xf6c3 ! movs.l m0, @-r2\n\t" \ - ".word 0xf6e3 ! movs.l m1, @-r2\n\t" \ + "sts.l dsr, @-r2\n\t" \ + "movs.l y1, @-r2\n\t" \ + "movs.l y0, @-r2\n\t" \ + "movs.l x1, @-r2\n\t" \ + "movs.l x0, @-r2\n\t" \ + "movs.l m1, @-r2\n\t" \ + "movs.l m0, @-r2\n\t" \ + "movs.l a1g, @-r2\n\t" \ + "movs.l a0g, @-r2\n\t" \ + "movs.l a1, @-r2\n\t" \ + "movs.l a0, @-r2\n\t" \ : : "r" (__ts2)); \ } while (0) @@ -63,6 +63,16 @@ do { \ #define __restore_dsp(tsk) do { } while (0) #endif +#if defined(CONFIG_CPU_SH4A) +#define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr)) +#else +#define __icbi(addr) mb() +#endif + +#define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr)) +#define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr)) +#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr)) + struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *next); @@ -198,8 +208,13 @@ do { \ }) #endif +static inline reg_size_t register_align(void *val) +{ + return (unsigned long)(signed long)val; +} + int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, - struct mem_access *ma); + struct mem_access *ma, int); asmlinkage void do_address_error(struct pt_regs *regs, unsigned long writeaccess, diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h index 943acf5ea07c..8e4a03e7966c 100644 --- a/arch/sh/include/asm/system_64.h +++ b/arch/sh/include/asm/system_64.h @@ -37,4 +37,14 @@ do { \ #define jump_to_uncached() do { } while (0) #define back_to_cached() do { } while (0) +#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr)) +#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr)) +#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr)) +#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr)) + +static inline reg_size_t register_align(void *val) +{ + return (unsigned long long)(signed long long)(signed long)val; +} + #endif /* __ASM_SH_SYSTEM_64_H */ diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h index d570ac2e5cb9..bdeb9d46d17d 100644 --- a/arch/sh/include/asm/thread_info.h +++ b/arch/sh/include/asm/thread_info.h @@ -97,7 +97,7 @@ static inline struct thread_info *current_thread_info(void) extern struct thread_info *alloc_thread_info(struct task_struct *tsk); extern void free_thread_info(struct thread_info *ti); - + #endif /* THREAD_SHIFT < PAGE_SHIFT */ #endif /* __ASSEMBLY__ */ @@ -116,6 +116,7 @@ extern void free_thread_info(struct thread_info *ti); #define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ #define TIF_SECCOMP 6 /* secure computing */ #define TIF_NOTIFY_RESUME 7 /* callback before returning to user */ +#define TIF_SYSCALL_TRACEPOINT 8 /* for ftrace syscall instrumentation */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 @@ -129,25 +130,27 @@ extern void free_thread_info(struct thread_info *ti); #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SECCOMP (1 << TIF_SECCOMP) #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) +#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) #define _TIF_USEDFPU (1 << TIF_USEDFPU) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) #define _TIF_FREEZE (1 << TIF_FREEZE) /* - * _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within a byte, or we + * _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or we * blow the tst immediate size constraints and need to fix up * arch/sh/kernel/entry-common.S. */ /* work to do in syscall trace */ #define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ - _TIF_SYSCALL_AUDIT | _TIF_SECCOMP) + _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \ + _TIF_SYSCALL_TRACEPOINT) /* work to do on any return to u-space */ #define _TIF_ALLWORK_MASK (_TIF_SYSCALL_TRACE | _TIF_SIGPENDING | \ _TIF_NEED_RESCHED | _TIF_SYSCALL_AUDIT | \ _TIF_SINGLESTEP | _TIF_RESTORE_SIGMASK | \ - _TIF_NOTIFY_RESUME) + _TIF_NOTIFY_RESUME | _TIF_SYSCALL_TRACEPOINT) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK (_TIF_ALLWORK_MASK & ~(_TIF_SYSCALL_TRACE | \ diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h index c7f3c94837dd..f8421f7ad63a 100644 --- a/arch/sh/include/asm/types.h +++ b/arch/sh/include/asm/types.h @@ -11,8 +11,10 @@ #ifdef CONFIG_SUPERH32 typedef u16 insn_size_t; +typedef u32 reg_size_t; #else typedef u32 insn_size_t; +typedef u64 reg_size_t; #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h index 61d6ad93d786..925dd40d9d55 100644 --- a/arch/sh/include/asm/unistd_32.h +++ b/arch/sh/include/asm/unistd_32.h @@ -132,7 +132,7 @@ #define __NR_clone 120 #define __NR_setdomainname 121 #define __NR_uname 122 -#define __NR_modify_ldt 123 +#define __NR_cacheflush 123 #define __NR_adjtimex 124 #define __NR_mprotect 125 #define __NR_sigprocmask 126 diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h index a751699afda3..2b84bc916bc5 100644 --- a/arch/sh/include/asm/unistd_64.h +++ b/arch/sh/include/asm/unistd_64.h @@ -137,7 +137,7 @@ #define __NR_clone 120 #define __NR_setdomainname 121 #define __NR_uname 122 -#define __NR_modify_ldt 123 +#define __NR_cacheflush 123 #define __NR_adjtimex 124 #define __NR_mprotect 125 #define __NR_sigprocmask 126 diff --git a/arch/sh/include/asm/unwinder.h b/arch/sh/include/asm/unwinder.h new file mode 100644 index 000000000000..1e65c07b3e18 --- /dev/null +++ b/arch/sh/include/asm/unwinder.h @@ -0,0 +1,31 @@ +#ifndef _LINUX_UNWINDER_H +#define _LINUX_UNWINDER_H + +#include <asm/stacktrace.h> + +struct unwinder { + const char *name; + struct list_head list; + int rating; + void (*dump)(struct task_struct *, struct pt_regs *, + unsigned long *, const struct stacktrace_ops *, void *); +}; + +extern int unwinder_init(void); +extern int unwinder_register(struct unwinder *); + +extern void unwind_stack(struct task_struct *, struct pt_regs *, + unsigned long *, const struct stacktrace_ops *, + void *); + +extern void stack_reader_dump(struct task_struct *, struct pt_regs *, + unsigned long *, const struct stacktrace_ops *, + void *); + +/* + * Used by fault handling code to signal to the unwinder code that it + * should switch to a different unwinder. + */ +extern int unwinder_faulted; + +#endif /* _LINUX_UNWINDER_H */ diff --git a/arch/sh/include/asm/vmlinux.lds.h b/arch/sh/include/asm/vmlinux.lds.h new file mode 100644 index 000000000000..244ec4ad9a79 --- /dev/null +++ b/arch/sh/include/asm/vmlinux.lds.h @@ -0,0 +1,17 @@ +#ifndef __ASM_SH_VMLINUX_LDS_H +#define __ASM_SH_VMLINUX_LDS_H + +#include <asm-generic/vmlinux.lds.h> + +#ifdef CONFIG_DWARF_UNWINDER +#define DWARF_EH_FRAME \ + .eh_frame : AT(ADDR(.eh_frame) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_eh_frame) = .; \ + *(.eh_frame) \ + VMLINUX_SYMBOL(__stop_eh_frame) = .; \ + } +#else +#define DWARF_EH_FRAME +#endif + +#endif /* __ASM_SH_VMLINUX_LDS_H */ diff --git a/arch/sh/include/asm/watchdog.h b/arch/sh/include/asm/watchdog.h index f024fed00a72..2fe7cee9e43a 100644 --- a/arch/sh/include/asm/watchdog.h +++ b/arch/sh/include/asm/watchdog.h @@ -13,10 +13,18 @@ #ifdef __KERNEL__ #include <linux/types.h> +#include <linux/io.h> + +#define WTCNT_HIGH 0x5a +#define WTCSR_HIGH 0xa5 + +#define WTCSR_CKS2 0x04 +#define WTCSR_CKS1 0x02 +#define WTCSR_CKS0 0x01 + #include <cpu/watchdog.h> -#include <asm/io.h> -/* +/* * See cpu-sh2/watchdog.h for explanation of this stupidity.. */ #ifndef WTCNT_R @@ -27,13 +35,6 @@ # define WTCSR_R WTCSR #endif -#define WTCNT_HIGH 0x5a -#define WTCSR_HIGH 0xa5 - -#define WTCSR_CKS2 0x04 -#define WTCSR_CKS1 0x02 -#define WTCSR_CKS0 0x01 - /* * CKS0-2 supports a number of clock division ratios. At the time the watchdog * is enabled, it defaults to a 41 usec overflow period .. we overload this to diff --git a/arch/sh/include/cpu-common/cpu/cacheflush.h b/arch/sh/include/cpu-common/cpu/cacheflush.h deleted file mode 100644 index c3db00b73605..000000000000 --- a/arch/sh/include/cpu-common/cpu/cacheflush.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * include/asm-sh/cpu-sh2/cacheflush.h - * - * Copyright (C) 2003 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_CPU_SH2_CACHEFLUSH_H -#define __ASM_CPU_SH2_CACHEFLUSH_H - -/* - * Cache flushing: - * - * - flush_cache_all() flushes entire cache - * - flush_cache_mm(mm) flushes the specified mm context's cache lines - * - flush_cache_dup mm(mm) handles cache flushing when forking - * - flush_cache_page(mm, vmaddr, pfn) flushes a single page - * - flush_cache_range(vma, start, end) flushes a range of pages - * - * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache - * - flush_icache_range(start, end) flushes(invalidates) a range for icache - * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache - * - * Caches are indexed (effectively) by physical address on SH-2, so - * we don't need them. - */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) -#define flush_dcache_page(page) do { } while (0) -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start, end) do { } while (0) -#define flush_icache_page(vma,pg) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) -#define flush_cache_sigtramp(vaddr) do { } while (0) - -#define p3_cache_init() do { } while (0) - -#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h deleted file mode 100644 index 3d3b9205d2ac..000000000000 --- a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef __ASM_CPU_SH2A_CACHEFLUSH_H -#define __ASM_CPU_SH2A_CACHEFLUSH_H - -/* - * Cache flushing: - * - * - flush_cache_all() flushes entire cache - * - flush_cache_mm(mm) flushes the specified mm context's cache lines - * - flush_cache_dup mm(mm) handles cache flushing when forking - * - flush_cache_page(mm, vmaddr, pfn) flushes a single page - * - flush_cache_range(vma, start, end) flushes a range of pages - * - * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache - * - flush_icache_range(start, end) flushes(invalidates) a range for icache - * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache - * - * Caches are indexed (effectively) by physical address on SH-2, so - * we don't need them. - */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) -#define flush_dcache_page(page) do { } while (0) -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -void flush_icache_range(unsigned long start, unsigned long end); -#define flush_icache_page(vma,pg) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) -#define flush_cache_sigtramp(vaddr) do { } while (0) - -#define p3_cache_init() do { } while (0) -#endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-sh3/cpu/cacheflush.h b/arch/sh/include/cpu-sh3/cpu/cacheflush.h deleted file mode 100644 index 1ac27aae6700..000000000000 --- a/arch/sh/include/cpu-sh3/cpu/cacheflush.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * include/asm-sh/cpu-sh3/cacheflush.h - * - * Copyright (C) 1999 Niibe Yutaka - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_CPU_SH3_CACHEFLUSH_H -#define __ASM_CPU_SH3_CACHEFLUSH_H - -#if defined(CONFIG_SH7705_CACHE_32KB) -/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the - * SH4. Unlike the SH4 this is a unified cache so we need to do some work - * in mmap when 'exec'ing a new binary - */ - /* 32KB cache, 4kb PAGE sizes need to check bit 12 */ -#define CACHE_ALIAS 0x00001000 - -#define PG_mapped PG_arch_1 - -void flush_cache_all(void); -void flush_cache_mm(struct mm_struct *mm); -#define flush_cache_dup_mm(mm) flush_cache_mm(mm) -void flush_cache_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end); -void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn); -void flush_dcache_page(struct page *pg); -void flush_icache_range(unsigned long start, unsigned long end); -void flush_icache_page(struct vm_area_struct *vma, struct page *page); - -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) - -/* SH3 has unified cache so no special action needed here */ -#define flush_cache_sigtramp(vaddr) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) - -#define p3_cache_init() do { } while (0) - -#else -#include <cpu-common/cpu/cacheflush.h> -#endif - -#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/cacheflush.h b/arch/sh/include/cpu-sh4/cpu/cacheflush.h deleted file mode 100644 index 065306d376eb..000000000000 --- a/arch/sh/include/cpu-sh4/cpu/cacheflush.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * include/asm-sh/cpu-sh4/cacheflush.h - * - * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2003 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_CPU_SH4_CACHEFLUSH_H -#define __ASM_CPU_SH4_CACHEFLUSH_H - -/* - * Caches are broken on SH-4 (unless we use write-through - * caching; in which case they're only semi-broken), - * so we need them. - */ -void flush_cache_all(void); -void flush_dcache_all(void); -void flush_cache_mm(struct mm_struct *mm); -#define flush_cache_dup_mm(mm) flush_cache_mm(mm) -void flush_cache_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end); -void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, - unsigned long pfn); -void flush_dcache_page(struct page *pg); - -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) - -void flush_icache_range(unsigned long start, unsigned long end); -void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, - unsigned long addr, int len); - -#define flush_icache_page(vma,pg) do { } while (0) - -/* Initialization of P3 area for copy_user_page */ -void p3_cache_init(void); - -#define PG_mapped PG_arch_1 - -#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h index 0ed5178fed69..f0886bc880e0 100644 --- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h +++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h @@ -16,7 +16,8 @@ #define DMAE0_IRQ 38 #define SH_DMAC_BASE0 0xFF608020 #define SH_DMARS_BASE 0xFF609000 -#elif defined(CONFIG_CPU_SUBTYPE_SH7723) +#elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \ + defined(CONFIG_CPU_SUBTYPE_SH7724) #define DMTE0_IRQ 48 /* DMAC0A*/ #define DMTE4_IRQ 40 /* DMAC0B */ #define DMTE6_IRQ 42 diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h index ccf1d999db6d..e1e90960ee9a 100644 --- a/arch/sh/include/cpu-sh4/cpu/freq.h +++ b/arch/sh/include/cpu-sh4/cpu/freq.h @@ -22,6 +22,10 @@ #define MSTPCR0 0xa4150030 #define MSTPCR1 0xa4150034 #define MSTPCR2 0xa4150038 +#elif defined(CONFIG_CPU_SUBTYPE_SH7757) +#define FRQCR 0xffc80000 +#define OSCCR 0xffc80018 +#define PLLCR 0xffc80024 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) #define FRQCR 0xffc80000 diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h index 738ea43c5038..48560407cbe1 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7722.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h @@ -221,4 +221,18 @@ enum { GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYOUT5_IN5, }; +enum { + HWBLK_UNKNOWN = 0, + HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_URAM, HWBLK_XYMEM, + HWBLK_INTC, HWBLK_DMAC, HWBLK_SHYWAY, HWBLK_HUDI, + HWBLK_UBC, HWBLK_TMU, HWBLK_CMT, HWBLK_RWDT, HWBLK_FLCTL, + HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SIO, + HWBLK_SIOF0, HWBLK_SIOF1, HWBLK_IIC, HWBLK_RTC, + HWBLK_TPU, HWBLK_IRDA, HWBLK_SDHI, HWBLK_SIM, HWBLK_KEYSC, + HWBLK_TSIF, HWBLK_USBF, HWBLK_2DG, HWBLK_SIU, HWBLK_VOU, + HWBLK_JPU, HWBLK_BEU, HWBLK_CEU, HWBLK_VEU, HWBLK_VPU, + HWBLK_LCDC, + HWBLK_NR, +}; + #endif /* __ASM_SH7722_H__ */ diff --git a/arch/sh/include/cpu-sh4/cpu/sh7723.h b/arch/sh/include/cpu-sh4/cpu/sh7723.h index 14c8ca936781..9b36fae72324 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7723.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7723.h @@ -265,4 +265,21 @@ enum { GPIO_FN_IDEA1, GPIO_FN_IDEA0, }; +enum { + HWBLK_UNKNOWN = 0, + HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_L2C, HWBLK_ILMEM, HWBLK_FPU, + HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY, + HWBLK_HUDI, HWBLK_DBG, HWBLK_UBC, HWBLK_SUBC, + HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1, + HWBLK_FLCTL, + HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, + HWBLK_SCIF3, HWBLK_SCIF4, HWBLK_SCIF5, + HWBLK_MSIOF0, HWBLK_MSIOF1, HWBLK_MERAM, HWBLK_IIC, HWBLK_RTC, + HWBLK_ATAPI, HWBLK_ADC, HWBLK_TPU, HWBLK_IRDA, HWBLK_TSIF, HWBLK_ICB, + HWBLK_SDHI0, HWBLK_SDHI1, HWBLK_KEYSC, HWBLK_USB, + HWBLK_2DG, HWBLK_SIU, HWBLK_VEU2H1, HWBLK_VOU, HWBLK_BEU, HWBLK_CEU, + HWBLK_VEU2H0, HWBLK_VPU, HWBLK_LCDC, + HWBLK_NR, +}; + #endif /* __ASM_SH7723_H__ */ diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h index 66fd1184359e..0cd1f71a1116 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7724.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h @@ -266,4 +266,21 @@ enum { GPIO_FN_INTC_IRQ1, GPIO_FN_INTC_IRQ0, }; +enum { + HWBLK_UNKNOWN = 0, + HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_RSMEM, HWBLK_ILMEM, HWBLK_L2C, + HWBLK_FPU, HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY, + HWBLK_HUDI, HWBLK_DBG, HWBLK_UBC, + HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1, + HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SCIF3, + HWBLK_SCIF4, HWBLK_SCIF5, HWBLK_MSIOF0, HWBLK_MSIOF1, + HWBLK_KEYSC, HWBLK_RTC, HWBLK_IIC0, HWBLK_IIC1, + HWBLK_MMC, HWBLK_ETHER, HWBLK_ATAPI, HWBLK_TPU, HWBLK_IRDA, + HWBLK_TSIF, HWBLK_USB1, HWBLK_USB0, HWBLK_2DG, + HWBLK_SDHI0, HWBLK_SDHI1, HWBLK_VEU1, HWBLK_CEU1, HWBLK_BEU1, + HWBLK_2DDMAC, HWBLK_SPU, HWBLK_JPU, HWBLK_VOU, + HWBLK_BEU0, HWBLK_CEU0, HWBLK_VEU0, HWBLK_VPU, HWBLK_LCDC, + HWBLK_NR, +}; + #endif /* __ASM_SH7724_H__ */ diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h new file mode 100644 index 000000000000..f4d267efad71 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h @@ -0,0 +1,243 @@ +#ifndef __ASM_SH7757_H__ +#define __ASM_SH7757_H__ + +enum { + /* PTA */ + GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, + GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0, + + /* PTB */ + GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4, + GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0, + + /* PTC */ + GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4, + GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0, + + /* PTD */ + GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4, + GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0, + + /* PTE */ + GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, + GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0, + + /* PTF */ + GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, + GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, + + /* PTG */ + GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4, + GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0, + + /* PTH */ + GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, + GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0, + + /* PTI */ + GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4, + GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0, + + /* PTJ */ + GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4, + GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0, + + /* PTK */ + GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4, + GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0, + + /* PTL */ + GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, + GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0, + + /* PTM */ + GPIO_PTM6, GPIO_PTM5, GPIO_PTM4, + GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0, + + /* PTN */ + GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4, + GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0, + + /* PTO */ + GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4, + GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0, + + /* PTP */ + GPIO_PTP6, GPIO_PTP5, GPIO_PTP4, + GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0, + + /* PTQ */ + GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4, + GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0, + + /* PTR */ + GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4, + GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0, + + /* PTS */ + GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4, + GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0, + + /* PTT */ + GPIO_PTT5, GPIO_PTT4, + GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0, + + /* PTU */ + GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4, + GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0, + + /* PTV */ + GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4, + GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0, + + /* PTW */ + GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4, + GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0, + + /* PTX */ + GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4, + GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0, + + /* PTY */ + GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4, + GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0, + + /* PTZ */ + GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4, + GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0, + + + /* PTA (mobule: LBSC, CPG, LPC) */ + GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY, + GPIO_FN_MD10, GPIO_FN_MD9, GPIO_FN_MD8, + GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4, + GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0, + + /* PTB (mobule: LBSC, EtherC, SIM, LPC) */ + GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, + GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, + GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO, + GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO, + GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST, + GPIO_FN_WPSZ1, GPIO_FN_WPSZ0, GPIO_FN_FWID, GPIO_FN_FLSHSZ, + GPIO_FN_LPC_SPIEN, GPIO_FN_BASEL, + + /* PTC (mobule: SD) */ + GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD, + GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0, + + /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ + GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4, + GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0, + GPIO_FN_MD6, GPIO_FN_MD5, GPIO_FN_MD3, GPIO_FN_MD2, + GPIO_FN_MD1, GPIO_FN_MD0, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0, + + /* PTE (mobule: EtherC) */ + GPIO_FN_ET0_CRS_DV, GPIO_FN_ET0_TXD1, + GPIO_FN_ET0_TXD0, GPIO_FN_ET0_TX_EN, + GPIO_FN_ET0_REF_CLK, GPIO_FN_ET0_RXD1, + GPIO_FN_ET0_RXD0, GPIO_FN_ET0_RX_ER, + + /* PTF (mobule: EtherC) */ + GPIO_FN_ET1_CRS_DV, GPIO_FN_ET1_TXD1, + GPIO_FN_ET1_TXD0, GPIO_FN_ET1_TX_EN, + GPIO_FN_ET1_REF_CLK, GPIO_FN_ET1_RXD1, + GPIO_FN_ET1_RXD0, GPIO_FN_ET1_RX_ER, + + /* PTG (mobule: SYSTEM, PWMX, LPC) */ + GPIO_FN_STATUS0, GPIO_FN_STATUS1, + GPIO_FN_PWX0, GPIO_FN_PWX1, GPIO_FN_PWX2, GPIO_FN_PWX3, + GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD, GPIO_FN_LDRQ, + + /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ + GPIO_FN_TCLK, GPIO_FN_RXD4, GPIO_FN_TXD4, + GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO, + GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB, + GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1, + GPIO_FN_SP0_SS1, + + /* PTI (mobule: INTC) */ + GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12, + GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8, + + /* PTJ (mobule: SCIF234, SERMUX) */ + GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_RXD2, GPIO_FN_TXD2, + GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD, + GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS, + + /* PTK (mobule: SERMUX) */ + GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD, + GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS, + GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR, + GPIO_FN_COM2_DCD, GPIO_FN_COM2_RI, + + /* PTL (mobule: SERMUX) */ + GPIO_FN_RAC_TXD, GPIO_FN_RAC_RXD, + GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS, + GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, + GPIO_FN_RAC_DCD, GPIO_FN_RAC_RI, + + /* PTM (mobule: IIC, LPC) */ + GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7, + GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_FMS1, + + /* PTN (mobule: SCIF234, EVC) */ + GPIO_FN_SCK2, GPIO_FN_RTS4, GPIO_FN_RTS3, GPIO_FN_RTS2, + GPIO_FN_CTS4, GPIO_FN_CTS3, GPIO_FN_CTS2, + GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4, + GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0, + + /* PTO (mobule: SGPIO) */ + GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, + GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO, + GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, + GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO, + + /* PTP (mobule: JMC, SCIF234) */ + GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI, + GPIO_FN_JMCRST, GPIO_FN_SCK4, GPIO_FN_SCK3, + + /* PTQ (mobule: LPC) */ + GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0, + GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK, + + /* PTR (mobule: GRA, IIC) */ + GPIO_FN_DDC3, GPIO_FN_DDC2, + GPIO_FN_SDA8, GPIO_FN_SCL8, GPIO_FN_SDA2, GPIO_FN_SCL2, + GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0, + + /* PTS (mobule: GRA, IIC) */ + GPIO_FN_DDC1, GPIO_FN_DDC0, + GPIO_FN_SDA9, GPIO_FN_SCL9, GPIO_FN_SDA5, GPIO_FN_SCL5, + GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3, + + /* PTT (mobule: SYSTEM, PWMX) */ + GPIO_FN_AUDSYNC, GPIO_FN_AUDCK, + GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, + GPIO_FN_AUDATA1, GPIO_FN_AUDATA0, + GPIO_FN_PWX7, GPIO_FN_PWX6, GPIO_FN_PWX5, GPIO_FN_PWX4, + + /* PTU (mobule: LBSC, DMAC) */ + GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CS0, + GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_A25, GPIO_FN_A24, + GPIO_FN_DREQ0, GPIO_FN_DACK0, + + /* PTV (mobule: LBSC, DMAC) */ + GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, + GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16, + GPIO_FN_TEND0, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_TEND1, + + /* PTW (mobule: LBSC) */ + GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12, + GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8, + + /* PTX (mobule: LBSC) */ + GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4, + GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0, + + /* PTY (mobule: LBSC) */ + GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, + GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, +}; + +#endif /* __ASM_SH7757_H__ */ diff --git a/arch/sh/include/cpu-sh5/cpu/cacheflush.h b/arch/sh/include/cpu-sh5/cpu/cacheflush.h deleted file mode 100644 index 5a11f0b7e66a..000000000000 --- a/arch/sh/include/cpu-sh5/cpu/cacheflush.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_SH_CPU_SH5_CACHEFLUSH_H -#define __ASM_SH_CPU_SH5_CACHEFLUSH_H - -#ifndef __ASSEMBLY__ - -struct vm_area_struct; -struct page; -struct mm_struct; - -extern void flush_cache_all(void); -extern void flush_cache_mm(struct mm_struct *mm); -extern void flush_cache_sigtramp(unsigned long vaddr); -extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end); -extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn); -extern void flush_dcache_page(struct page *pg); -extern void flush_icache_range(unsigned long start, unsigned long end); -extern void flush_icache_user_range(struct vm_area_struct *vma, - struct page *page, unsigned long addr, - int len); - -#define flush_cache_dup_mm(mm) flush_cache_mm(mm) - -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) - -#define flush_icache_page(vma, page) do { } while (0) -void p3_cache_init(void); - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_SH_CPU_SH5_CACHEFLUSH_H */ - diff --git a/arch/sh/include/mach-common/mach/migor.h b/arch/sh/include/mach-common/mach/migor.h deleted file mode 100644 index e451f0229e00..000000000000 --- a/arch/sh/include/mach-common/mach/migor.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __ASM_SH_MIGOR_H -#define __ASM_SH_MIGOR_H - -/* - * linux/include/asm-sh/migor.h - * - * Copyright (C) 2008 Renesas Solutions - * - * Portions Copyright (C) 2007 Nobuhiro Iwamatsu - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ -#include <asm/addrspace.h> - -/* GPIO */ -#define PORT_PACR 0xa4050100 -#define PORT_PDCR 0xa4050106 -#define PORT_PECR 0xa4050108 -#define PORT_PHCR 0xa405010e -#define PORT_PJCR 0xa4050110 -#define PORT_PKCR 0xa4050112 -#define PORT_PLCR 0xa4050114 -#define PORT_PMCR 0xa4050116 -#define PORT_PRCR 0xa405011c -#define PORT_PTCR 0xa4050140 -#define PORT_PUCR 0xa4050142 -#define PORT_PVCR 0xa4050144 -#define PORT_PWCR 0xa4050146 -#define PORT_PXCR 0xa4050148 -#define PORT_PYCR 0xa405014a -#define PORT_PZCR 0xa405014c -#define PORT_PADR 0xa4050120 -#define PORT_PHDR 0xa405012e -#define PORT_PTDR 0xa4050160 -#define PORT_PWDR 0xa4050166 - -#define PORT_HIZCRA 0xa4050158 -#define PORT_HIZCRC 0xa405015c - -#define PORT_MSELCRB 0xa4050182 - -#define PORT_PSELA 0xa405014e -#define PORT_PSELB 0xa4050150 -#define PORT_PSELC 0xa4050152 -#define PORT_PSELD 0xa4050154 -#define PORT_PSELE 0xa4050156 - -#define PORT_HIZCRA 0xa4050158 -#define PORT_HIZCRB 0xa405015a -#define PORT_HIZCRC 0xa405015c - -#define BSC_CS4BCR 0xfec10010 -#define BSC_CS6ABCR 0xfec1001c -#define BSC_CS4WCR 0xfec10030 - -#include <video/sh_mobile_lcdc.h> - -int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle, - struct sh_mobile_lcdc_sys_bus_ops *sys_ops); - -#endif /* __ASM_SH_MIGOR_H */ diff --git a/arch/sh/include/mach-common/mach/romimage.h b/arch/sh/include/mach-common/mach/romimage.h new file mode 100644 index 000000000000..267e24112d82 --- /dev/null +++ b/arch/sh/include/mach-common/mach/romimage.h @@ -0,0 +1 @@ +/* do nothing here by default */ diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h index 90011d435f30..1292ae5c21b3 100644 --- a/arch/sh/include/mach-common/mach/sh7785lcr.h +++ b/arch/sh/include/mach-common/mach/sh7785lcr.h @@ -35,6 +35,8 @@ #define PCA9564_ADDR 0x06000000 /* I2C */ #define PCA9564_SIZE 0x00000100 +#define PCA9564_PROTO_32BIT_ADDR 0x14000000 + #define SM107_MEM_ADDR 0x10000000 #define SM107_MEM_SIZE 0x00e00000 #define SM107_REG_ADDR 0x13e00000 diff --git a/arch/sh/include/mach-ecovec24/mach/partner-jet-setup.txt b/arch/sh/include/mach-ecovec24/mach/partner-jet-setup.txt new file mode 100644 index 000000000000..8b8e4fa1fee9 --- /dev/null +++ b/arch/sh/include/mach-ecovec24/mach/partner-jet-setup.txt @@ -0,0 +1,82 @@ +LIST "partner-jet-setup.txt" +LIST "(C) Copyright 2009 Renesas Solutions Corp" +LIST "Kuninori Morimoto <morimoto.kuninori@renesas.com>" +LIST "--------------------------------" +LIST "zImage (RAM boot)" +LIST "This script can be used to boot the kernel from RAM via JTAG:" +LIST "> < partner-jet-setup.txt" +LIST "> RD zImage, 0xa8800000" +LIST "> G=0xa8800000" +LIST "--------------------------------" +LIST "romImage (Flash boot)" +LIST "Use the following command to burn the zImage to flash via JTAG:" +LIST "> RD romImage, 0" +LIST "--------------------------------" + +LIST "disable watchdog" +EW 0xa4520004, 0xa507 + +LIST "MMU" +ED 0xff000010, 0x00000004 + +LIST "setup clocks" +ED 0xa4150024, 0x00004000 +ED 0xa4150000, 0x8E003508 +ED 0xa4150004, 0x00000000 + +WAIT 1 + +LIST "BSC" +ED 0xff800020, 0xa5a50000 +ED 0xfec10000, 0x00000013 +ED 0xfec10004, 0x11110400 +ED 0xfec10024, 0x00000440 + +WAIT 1 + +LIST "setup sdram" +ED 0xfd000108, 0x00000181 +ED 0xfd000020, 0x015B0002 +ED 0xfd000030, 0x03061502 +ED 0xfd000034, 0x02020102 +ED 0xfd000038, 0x01090305 +ED 0xfd00003c, 0x00000002 +ED 0xfd000008, 0x00000005 +ED 0xfd000018, 0x00000001 + +WAIT 1 + +ED 0xfd000014, 0x00000002 +ED 0xfd000060, 0x00020000 +ED 0xfd000060, 0x00030000 +ED 0xfd000060, 0x00010040 +ED 0xfd000060, 0x00000532 +ED 0xfd000014, 0x00000002 +ED 0xfd000014, 0x00000004 +ED 0xfd000014, 0x00000004 +ED 0xfd000060, 0x00000432 +ED 0xfd000060, 0x000103C0 +ED 0xfd000060, 0x00010040 + +WAIT 1 + +ED 0xfd000010, 0x00000001 +ED 0xfd000044, 0x00000613 +ED 0xfd000048, 0x238C003A +ED 0xfd000014, 0x00000002 + +LIST "Dummy read" +DD 0x0c400000, 0x0c400000 + +ED 0xfd000014, 0x00000002 +ED 0xfd000014, 0x00000004 +ED 0xfd000108, 0x00000080 +ED 0xfd000040, 0x00010000 + +WAIT 1 + +LIST "setup cache" +ED 0xff00001c, 0x0000090b + +LIST "disable USB" +EW 0xA4D80000, 0x0000 diff --git a/arch/sh/include/mach-ecovec24/mach/romimage.h b/arch/sh/include/mach-ecovec24/mach/romimage.h new file mode 100644 index 000000000000..1c8787ecb1c1 --- /dev/null +++ b/arch/sh/include/mach-ecovec24/mach/romimage.h @@ -0,0 +1,20 @@ +/* EcoVec board specific boot code: + * converts the "partner-jet-script.txt" script into assembly + * the assembly code is the first code to be executed in the romImage + */ + +#include <asm/romimage-macros.h> +#include "partner-jet-setup.txt" + + /* execute icbi after enabling cache */ + mov.l 1f, r0 + icbi @r0 + + /* jump to cached area */ + mova 2f, r0 + jmp @r0 + nop + + .align 2 +1 : .long 0xa8000000 +2 : diff --git a/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h b/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h new file mode 100644 index 000000000000..174374e19547 --- /dev/null +++ b/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h @@ -0,0 +1,21 @@ +#ifndef __ASM_SH_KFR2R09_H +#define __ASM_SH_KFR2R09_H + +#include <video/sh_mobile_lcdc.h> + +#ifdef CONFIG_FB_SH_MOBILE_LCDC +void kfr2r09_lcd_on(void *board_data); +void kfr2r09_lcd_off(void *board_data); +int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops); +#else +static inline void kfr2r09_lcd_on(void *board_data) {} +static inline void kfr2r09_lcd_off(void *board_data) {} +static inline int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops) +{ + return -ENODEV; +} +#endif + +#endif /* __ASM_SH_KFR2R09_H */ diff --git a/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt b/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt new file mode 100644 index 000000000000..3a65503714ee --- /dev/null +++ b/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt @@ -0,0 +1,143 @@ +LIST "partner-jet-setup.txt - 20090729 Magnus Damm" +LIST "set up enough of the kfr2r09 hardware to boot the kernel" + +LIST "zImage (RAM boot)" +LIST "This script can be used to boot the kernel from RAM via JTAG:" +LIST "> < partner-jet-setup.txt" +LIST "> RD zImage, 0xa8800000" +LIST "> G=0xa8800000" + +LIST "romImage (Flash boot)" +LIST "Use the following command to burn the zImage to flash via JTAG:" +LIST "> RD romImage, 0" + +LIST "--------------------------------" + +LIST "disable watchdog" +EW 0xa4520004, 0xa507 + +LIST "invalidate instruction cache" +ED 0xff00001c, 0x00000800 + +LIST "invalidate TLBs" +ED 0xff000010, 0x00000004 + +LIST "select mode for cs5 + cs6" +ED 0xff800020, 0xa5a50001 +ED 0xfec10000, 0x0000001b + +LIST "setup clocks" +LIST "The PLL and FLL values are updated here for the optimal" +LIST "RF frequency and improved reception sensitivity." +ED 0xa4150004, 0x00000050 +ED 0xa4150000, 0x91053508 +WAIT 1 +ED 0xa4150050, 0x00000340 +ED 0xa4150024, 0x00005000 + +LIST "setup pins" +EB 0xa4050120, 0x00 +EB 0xa4050122, 0x00 +EB 0xa4050124, 0x00 +EB 0xa4050126, 0x00 +EB 0xa4050128, 0xA0 +EB 0xa405012A, 0x10 +EB 0xa405012C, 0x00 +EB 0xa405012E, 0x00 +EB 0xa4050130, 0x00 +EB 0xa4050132, 0x00 +EB 0xa4050134, 0x01 +EB 0xa4050136, 0x40 +EB 0xa4050138, 0x00 +EB 0xa405013A, 0x00 +EB 0xa405013C, 0x00 +EB 0xa405013E, 0x20 +EB 0xa4050160, 0x00 +EB 0xa4050162, 0x40 +EB 0xa4050164, 0x03 +EB 0xa4050166, 0x00 +EB 0xa4050168, 0x00 +EB 0xa405016A, 0x00 +EB 0xa405016C, 0x00 + +EW 0xa405014E, 0x5660 +EW 0xa4050150, 0x0145 +EW 0xa4050152, 0x1550 +EW 0xa4050154, 0x0200 +EW 0xa4050156, 0x0040 + +EW 0xa4050158, 0x0000 +EW 0xa405015a, 0x0000 +EW 0xa405015c, 0x0000 +EW 0xa405015e, 0x0000 + +EW 0xa4050180, 0x0000 +EW 0xa4050182, 0x8002 +EW 0xa4050184, 0x0000 + +EW 0xa405018a, 0x9991 +EW 0xa405018c, 0x8011 +EW 0xa405018e, 0x9550 + +EW 0xa4050100, 0x0000 +EW 0xa4050102, 0x5540 +EW 0xa4050104, 0x0000 +EW 0xa4050106, 0x0000 +EW 0xa4050108, 0x4550 +EW 0xa405010a, 0x0130 +EW 0xa405010c, 0x0555 +EW 0xa405010e, 0x0000 +EW 0xa4050110, 0x0000 +EW 0xa4050112, 0xAAA8 +EW 0xa4050114, 0x8305 +EW 0xa4050116, 0x10F0 +EW 0xa4050118, 0x0F50 +EW 0xa405011a, 0x0000 +EW 0xa405011c, 0x0000 +EW 0xa405011e, 0x0555 +EW 0xa4050140, 0x0000 +EW 0xa4050142, 0x5141 +EW 0xa4050144, 0x5005 +EW 0xa4050146, 0xAAA9 +EW 0xa4050148, 0xFAA9 +EW 0xa405014a, 0x3000 +EW 0xa405014c, 0x0000 + +LIST "setup sdram" +ED 0xFD000108, 0x40000301 +ED 0xFD000020, 0x011B0002 +ED 0xFD000030, 0x03060E02 +ED 0xFD000034, 0x01020102 +ED 0xFD000038, 0x01090406 +ED 0xFD000008, 0x00000004 +ED 0xFD000040, 0x00000001 +ED 0xFD000040, 0x00000000 +ED 0xFD000018, 0x00000001 + +WAIT 1 + +ED 0xFD000014, 0x00000002 +ED 0xFD000060, 0x00000032 +ED 0xFD000060, 0x00020000 +ED 0xFD000014, 0x00000004 +ED 0xFD000014, 0x00000004 +ED 0xFD000010, 0x00000001 +ED 0xFD000044, 0x000004AF +ED 0xFD000048, 0x20CF0037 + +LIST "read 16 bytes from sdram" +DD 0xa8000000, 0xa8000000, 1 +DD 0xa8000004, 0xa8000004, 1 +DD 0xa8000008, 0xa8000008, 1 +DD 0xa800000c, 0xa800000c, 1 + +ED 0xFD000014, 0x00000002 +ED 0xFD000014, 0x00000004 +ED 0xFD000108, 0x40000300 +ED 0xFD000040, 0x00010000 + +LIST "write to internal ram" +ED 0xfd8007fc, 0 + +LIST "setup cache" +ED 0xff00001c, 0x0000090b diff --git a/arch/sh/include/mach-kfr2r09/mach/romimage.h b/arch/sh/include/mach-kfr2r09/mach/romimage.h new file mode 100644 index 000000000000..a110823f2bde --- /dev/null +++ b/arch/sh/include/mach-kfr2r09/mach/romimage.h @@ -0,0 +1,20 @@ +/* kfr2r09 board specific boot code: + * converts the "partner-jet-script.txt" script into assembly + * the assembly code is the first code to be executed in the romImage + */ + +#include <asm/romimage-macros.h> +#include "partner-jet-setup.txt" + + /* execute icbi after enabling cache */ + mov.l 1f, r0 + icbi @r0 + + /* jump to cached area */ + mova 2f, r0 + jmp @r0 + nop + + .align 2 +1: .long 0xa8000000 +2: diff --git a/arch/sh/include/mach-migor/mach/migor.h b/arch/sh/include/mach-migor/mach/migor.h new file mode 100644 index 000000000000..cee6cb88e020 --- /dev/null +++ b/arch/sh/include/mach-migor/mach/migor.h @@ -0,0 +1,14 @@ +#ifndef __ASM_SH_MIGOR_H +#define __ASM_SH_MIGOR_H + +#define PORT_MSELCRB 0xa4050182 +#define BSC_CS4BCR 0xfec10010 +#define BSC_CS6ABCR 0xfec1001c +#define BSC_CS4WCR 0xfec10030 + +#include <video/sh_mobile_lcdc.h> + +int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops); + +#endif /* __ASM_SH_MIGOR_H */ diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile index 349d833deab5..a2d0a40f3848 100644 --- a/arch/sh/kernel/Makefile +++ b/arch/sh/kernel/Makefile @@ -1,5 +1,41 @@ -ifeq ($(CONFIG_SUPERH32),y) -include ${srctree}/arch/sh/kernel/Makefile_32 -else -include ${srctree}/arch/sh/kernel/Makefile_64 +# +# Makefile for the Linux/SuperH kernel. +# + +extra-y := head_$(BITS).o init_task.o vmlinux.lds + +ifdef CONFIG_FUNCTION_TRACER +# Do not profile debug and lowlevel utilities +CFLAGS_REMOVE_ftrace.o = -pg endif + +obj-y := debugtraps.o dumpstack.o idle.o io.o io_generic.o irq.o \ + machvec.o nmi_debug.o process_$(BITS).o ptrace_$(BITS).o \ + setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o \ + syscalls_$(BITS).o time.o topology.o traps.o \ + traps_$(BITS).o unwinder.o + +obj-y += cpu/ +obj-$(CONFIG_VSYSCALL) += vsyscall/ +obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o +obj-$(CONFIG_KGDB) += kgdb.o +obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o +obj-$(CONFIG_MODULES) += sh_ksyms_$(BITS).o module.o +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o +obj-$(CONFIG_CRASH_DUMP) += crash_dump.o +obj-$(CONFIG_STACKTRACE) += stacktrace.o +obj-$(CONFIG_IO_TRAPPED) += io_trapped.o +obj-$(CONFIG_KPROBES) += kprobes.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o +obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o +obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o +obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o +obj-$(CONFIG_DUMP_CODE) += disassemble.o +obj-$(CONFIG_HIBERNATION) += swsusp.o +obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o + +obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/sh/kernel/Makefile_32 b/arch/sh/kernel/Makefile_32 deleted file mode 100644 index 9411e3e31e68..000000000000 --- a/arch/sh/kernel/Makefile_32 +++ /dev/null @@ -1,37 +0,0 @@ -# -# Makefile for the Linux/SuperH kernel. -# - -extra-y := head_32.o init_task.o vmlinux.lds - -ifdef CONFIG_FUNCTION_TRACER -# Do not profile debug and lowlevel utilities -CFLAGS_REMOVE_ftrace.o = -pg -endif - -obj-y := debugtraps.o idle.o io.o io_generic.o irq.o \ - machvec.o process_32.o ptrace_32.o setup.o signal_32.o \ - sys_sh.o sys_sh32.o syscalls_32.o time.o topology.o \ - traps.o traps_32.o - -obj-y += cpu/ -obj-$(CONFIG_VSYSCALL) += vsyscall/ -obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o -obj-$(CONFIG_KGDB) += kgdb.o -obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o -obj-$(CONFIG_MODULES) += sh_ksyms_32.o module.o -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o -obj-$(CONFIG_CRASH_DUMP) += crash_dump.o -obj-$(CONFIG_STACKTRACE) += stacktrace.o -obj-$(CONFIG_IO_TRAPPED) += io_trapped.o -obj-$(CONFIG_KPROBES) += kprobes.o -obj-$(CONFIG_GENERIC_GPIO) += gpio.o -obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o -obj-$(CONFIG_DUMP_CODE) += disassemble.o -obj-$(CONFIG_HIBERNATION) += swsusp.o - -obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/sh/kernel/Makefile_64 b/arch/sh/kernel/Makefile_64 deleted file mode 100644 index 67b9f6c6326b..000000000000 --- a/arch/sh/kernel/Makefile_64 +++ /dev/null @@ -1,19 +0,0 @@ -extra-y := head_64.o init_task.o vmlinux.lds - -obj-y := debugtraps.o idle.o io.o io_generic.o irq.o machvec.o process_64.o \ - ptrace_64.o setup.o signal_64.o sys_sh.o sys_sh64.o \ - syscalls_64.o time.o topology.o traps.o traps_64.o - -obj-y += cpu/ -obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o -obj-$(CONFIG_MODULES) += sh_ksyms_64.o module.o -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -obj-$(CONFIG_CRASH_DUMP) += crash_dump.o -obj-$(CONFIG_STACKTRACE) += stacktrace.o -obj-$(CONFIG_IO_TRAPPED) += io_trapped.o -obj-$(CONFIG_GENERIC_GPIO) += gpio.o - -obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/sh/kernel/asm-offsets.c b/arch/sh/kernel/asm-offsets.c index 99aceb28ee24..d218e808294e 100644 --- a/arch/sh/kernel/asm-offsets.c +++ b/arch/sh/kernel/asm-offsets.c @@ -26,6 +26,7 @@ int main(void) DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); DEFINE(TI_PRE_COUNT, offsetof(struct thread_info, preempt_count)); DEFINE(TI_RESTART_BLOCK,offsetof(struct thread_info, restart_block)); + DEFINE(TI_SIZE, sizeof(struct thread_info)); #ifdef CONFIG_HIBERNATION DEFINE(PBE_ADDRESS, offsetof(struct pbe, address)); diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile index eecad7cbd61e..3d6b9312dc47 100644 --- a/arch/sh/kernel/cpu/Makefile +++ b/arch/sh/kernel/cpu/Makefile @@ -19,4 +19,4 @@ obj-$(CONFIG_UBC_WAKEUP) += ubc.o obj-$(CONFIG_SH_ADC) += adc.o obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o -obj-y += irq/ init.o clock.o +obj-y += irq/ init.o clock.o hwblk.o diff --git a/arch/sh/kernel/cpu/hwblk.c b/arch/sh/kernel/cpu/hwblk.c new file mode 100644 index 000000000000..c0ad7d46e784 --- /dev/null +++ b/arch/sh/kernel/cpu/hwblk.c @@ -0,0 +1,155 @@ +#include <linux/clk.h> +#include <linux/compiler.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/spinlock.h> +#include <asm/suspend.h> +#include <asm/hwblk.h> +#include <asm/clock.h> + +static DEFINE_SPINLOCK(hwblk_lock); + +static void hwblk_area_mod_cnt(struct hwblk_info *info, + int area, int counter, int value, int goal) +{ + struct hwblk_area *hap = info->areas + area; + + hap->cnt[counter] += value; + + if (hap->cnt[counter] != goal) + return; + + if (hap->flags & HWBLK_AREA_FLAG_PARENT) + hwblk_area_mod_cnt(info, hap->parent, counter, value, goal); +} + + +static int __hwblk_mod_cnt(struct hwblk_info *info, int hwblk, + int counter, int value, int goal) +{ + struct hwblk *hp = info->hwblks + hwblk; + + hp->cnt[counter] += value; + if (hp->cnt[counter] == goal) + hwblk_area_mod_cnt(info, hp->area, counter, value, goal); + + return hp->cnt[counter]; +} + +static void hwblk_mod_cnt(struct hwblk_info *info, int hwblk, + int counter, int value, int goal) +{ + unsigned long flags; + + spin_lock_irqsave(&hwblk_lock, flags); + __hwblk_mod_cnt(info, hwblk, counter, value, goal); + spin_unlock_irqrestore(&hwblk_lock, flags); +} + +void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int counter) +{ + hwblk_mod_cnt(info, hwblk, counter, 1, 1); +} + +void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int counter) +{ + hwblk_mod_cnt(info, hwblk, counter, -1, 0); +} + +void hwblk_enable(struct hwblk_info *info, int hwblk) +{ + struct hwblk *hp = info->hwblks + hwblk; + unsigned long tmp; + unsigned long flags; + int ret; + + spin_lock_irqsave(&hwblk_lock, flags); + + ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, 1, 1); + if (ret == 1) { + tmp = __raw_readl(hp->mstp); + tmp &= ~(1 << hp->bit); + __raw_writel(tmp, hp->mstp); + } + + spin_unlock_irqrestore(&hwblk_lock, flags); +} + +void hwblk_disable(struct hwblk_info *info, int hwblk) +{ + struct hwblk *hp = info->hwblks + hwblk; + unsigned long tmp; + unsigned long flags; + int ret; + + spin_lock_irqsave(&hwblk_lock, flags); + + ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, -1, 0); + if (ret == 0) { + tmp = __raw_readl(hp->mstp); + tmp |= 1 << hp->bit; + __raw_writel(tmp, hp->mstp); + } + + spin_unlock_irqrestore(&hwblk_lock, flags); +} + +struct hwblk_info *hwblk_info; + +int __init hwblk_register(struct hwblk_info *info) +{ + hwblk_info = info; + return 0; +} + +int __init __weak arch_hwblk_init(void) +{ + return 0; +} + +int __weak arch_hwblk_sleep_mode(void) +{ + return SUSP_SH_SLEEP; +} + +int __init hwblk_init(void) +{ + return arch_hwblk_init(); +} + +/* allow clocks to enable and disable hardware blocks */ +static int sh_hwblk_clk_enable(struct clk *clk) +{ + if (!hwblk_info) + return -ENOENT; + + hwblk_enable(hwblk_info, clk->arch_flags); + return 0; +} + +static void sh_hwblk_clk_disable(struct clk *clk) +{ + if (hwblk_info) + hwblk_disable(hwblk_info, clk->arch_flags); +} + +static struct clk_ops sh_hwblk_clk_ops = { + .enable = sh_hwblk_clk_enable, + .disable = sh_hwblk_clk_disable, + .recalc = followparent_recalc, +}; + +int __init sh_hwblk_clk_register(struct clk *clks, int nr) +{ + struct clk *clkp; + int ret = 0; + int k; + + for (k = 0; !ret && (k < nr); k++) { + clkp = clks + k; + clkp->ops = &sh_hwblk_clk_ops; + ret |= clk_register(clkp); + } + + return ret; +} diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index ad85421099cd..e932ebef4738 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -3,7 +3,7 @@ * * CPU init code * - * Copyright (C) 2002 - 2007 Paul Mundt + * Copyright (C) 2002 - 2009 Paul Mundt * Copyright (C) 2003 Richard Curnow * * This file is subject to the terms and conditions of the GNU General Public @@ -62,6 +62,37 @@ static void __init speculative_execution_init(void) #define speculative_execution_init() do { } while (0) #endif +#ifdef CONFIG_CPU_SH4A +#define EXPMASK 0xff2f0004 +#define EXPMASK_RTEDS (1 << 0) +#define EXPMASK_BRDSSLP (1 << 1) +#define EXPMASK_MMCAW (1 << 4) + +static void __init expmask_init(void) +{ + unsigned long expmask = __raw_readl(EXPMASK); + + /* + * Future proofing. + * + * Disable support for slottable sleep instruction + * and non-nop instructions in the rte delay slot. + */ + expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP); + + /* + * Enable associative writes to the memory-mapped cache array + * until the cache flush ops have been rewritten. + */ + expmask |= EXPMASK_MMCAW; + + __raw_writel(expmask, EXPMASK); + ctrl_barrier(); +} +#else +#define expmask_init() do { } while (0) +#endif + /* 2nd-level cache init */ void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void) { @@ -268,11 +299,9 @@ asmlinkage void __init sh_cpu_init(void) cache_init(); if (raw_smp_processor_id() == 0) { -#ifdef CONFIG_MMU shm_align_mask = max_t(unsigned long, current_cpu_data.dcache.way_size - 1, PAGE_SIZE - 1); -#endif /* Boot CPU sets the cache shape */ detect_cache_shape(); @@ -321,4 +350,5 @@ asmlinkage void __init sh_cpu_init(void) #endif speculative_execution_init(); + expmask_init(); } diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index 808d99a48efb..c1508a90fc6a 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c @@ -35,6 +35,7 @@ static void disable_ipr_irq(unsigned int irq) unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set the priority in IPR to 0 */ __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr); + (void)__raw_readw(addr); /* Read back to flush write posting */ } static void enable_ipr_irq(unsigned int irq) diff --git a/arch/sh/kernel/cpu/sh2/entry.S b/arch/sh/kernel/cpu/sh2/entry.S index becc54c45692..c8a4331d9b8d 100644 --- a/arch/sh/kernel/cpu/sh2/entry.S +++ b/arch/sh/kernel/cpu/sh2/entry.S @@ -227,8 +227,9 @@ ENTRY(sh_bios_handler) mov.l @r15+, r14 add #8,r15 lds.l @r15+, pr + mov.l @r15+,r15 rte - mov.l @r15+,r15 + nop .align 2 1: .long gdb_vbr_vector #endif /* CONFIG_SH_STANDARD_BIOS */ diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c index 5916d9096b99..1db6d8883888 100644 --- a/arch/sh/kernel/cpu/sh2/probe.c +++ b/arch/sh/kernel/cpu/sh2/probe.c @@ -29,6 +29,7 @@ int __init detect_cpu_and_cache_system(void) */ boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; boot_cpu_data.icache = boot_cpu_data.dcache; + boot_cpu_data.family = CPU_FAMILY_SH2; return 0; } diff --git a/arch/sh/kernel/cpu/sh2a/entry.S b/arch/sh/kernel/cpu/sh2a/entry.S index ab3903eeda5c..222742ddc0d6 100644 --- a/arch/sh/kernel/cpu/sh2a/entry.S +++ b/arch/sh/kernel/cpu/sh2a/entry.S @@ -176,8 +176,9 @@ ENTRY(sh_bios_handler) movml.l @r15+,r14 add #8,r15 lds.l @r15+, pr + mov.l @r15+,r15 rte - mov.l @r15+,r15 + nop .align 2 1: .long gdb_vbr_vector #endif /* CONFIG_SH_STANDARD_BIOS */ diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index e098e2f6aa08..6825d6507164 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -15,6 +15,8 @@ int __init detect_cpu_and_cache_system(void) { + boot_cpu_data.family = CPU_FAMILY_SH2A; + /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ boot_cpu_data.flags |= CPU_HAS_OP32; diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c index fa30b6017730..e8749505bd2a 100644 --- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c +++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c @@ -22,13 +22,6 @@ static int stc_multipliers[] = { 1, 2, 4, 8, 3, 6, 1, 1 }; static int ifc_divisors[] = { 1, 2, 4, 1, 3, 1, 1, 1 }; static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 }; -static void set_bus_parent(struct clk *clk) -{ - struct clk *bus_clk = clk_get(NULL, "bus_clk"); - clk->parent = bus_clk; - clk_put(bus_clk); -} - static void master_clk_init(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); @@ -50,9 +43,6 @@ static unsigned long module_clk_recalc(struct clk *clk) } static struct clk_ops sh7709_module_clk_ops = { -#ifdef CLOCK_MODE_0_1_2_7 - .init = set_bus_parent, -#endif .recalc = module_clk_recalc, }; @@ -78,7 +68,6 @@ static unsigned long cpu_clk_recalc(struct clk *clk) } static struct clk_ops sh7709_cpu_clk_ops = { - .init = set_bus_parent, .recalc = cpu_clk_recalc, }; diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S index 3cb531f233f2..0151933e5253 100644 --- a/arch/sh/kernel/cpu/sh3/entry.S +++ b/arch/sh/kernel/cpu/sh3/entry.S @@ -53,10 +53,6 @@ * syscall # * */ -#if defined(CONFIG_KGDB) -NMI_VEC = 0x1c0 ! Must catch early for debounce -#endif - /* Offsets to the stack */ OFF_R0 = 0 /* Return value. New ABI also arg4 */ OFF_R1 = 4 /* New ABI: arg5 */ @@ -71,7 +67,6 @@ OFF_PC = (16*4) OFF_SR = (16*4+8) OFF_TRA = (16*4+6*4) - #define k0 r0 #define k1 r1 #define k2 r2 @@ -113,34 +108,34 @@ OFF_TRA = (16*4+6*4) #if defined(CONFIG_MMU) .align 2 ENTRY(tlb_miss_load) - bra call_dpf + bra call_handle_tlbmiss mov #0, r5 .align 2 ENTRY(tlb_miss_store) - bra call_dpf + bra call_handle_tlbmiss mov #1, r5 .align 2 ENTRY(initial_page_write) - bra call_dpf - mov #1, r5 + bra call_handle_tlbmiss + mov #2, r5 .align 2 ENTRY(tlb_protection_violation_load) - bra call_dpf + bra call_do_page_fault mov #0, r5 .align 2 ENTRY(tlb_protection_violation_store) - bra call_dpf + bra call_do_page_fault mov #1, r5 -call_dpf: +call_handle_tlbmiss: + setup_frame_reg mov.l 1f, r0 mov r5, r8 mov.l @r0, r6 - mov r6, r9 mov.l 2f, r0 sts pr, r10 jsr @r0 @@ -151,16 +146,25 @@ call_dpf: lds r10, pr rts nop -0: mov.l 3f, r0 - mov r9, r6 +0: mov r8, r5 +call_do_page_fault: + mov.l 1f, r0 + mov.l @r0, r6 + + sti + + mov.l 3f, r0 + mov.l 4f, r1 + mov r15, r4 jmp @r0 - mov r15, r4 + lds r1, pr .align 2 1: .long MMU_TEA -2: .long __do_page_fault +2: .long handle_tlbmiss 3: .long do_page_fault +4: .long ret_from_exception .align 2 ENTRY(address_error_load) @@ -256,7 +260,7 @@ restore_all: ! ! Calculate new SR value mov k3, k2 ! original SR value - mov #0xf0, k1 + mov #0xfffffff0, k1 extu.b k1, k1 not k1, k1 and k1, k2 ! Mask original SR value @@ -272,21 +276,12 @@ restore_all: 6: or k0, k2 ! Set the IMASK-bits ldc k2, ssr ! -#if defined(CONFIG_KGDB) - ! Clear in_nmi - mov.l 6f, k0 - mov #0, k1 - mov.b k1, @k0 -#endif mov k4, r15 rte nop .align 2 5: .long 0x00001000 ! DSP -#ifdef CONFIG_KGDB -6: .long in_nmi -#endif 7: .long 0x30000000 ! common exception handler @@ -478,23 +473,6 @@ ENTRY(save_low_regs) ! .balign 512,0,512 ENTRY(handle_interrupt) -#if defined(CONFIG_KGDB) - mov.l 2f, k2 - ! Debounce (filter nested NMI) - mov.l @k2, k0 - mov.l 9f, k1 - cmp/eq k1, k0 - bf 11f - mov.l 10f, k1 - tas.b @k1 - bt 11f - rte - nop - .align 2 -9: .long NMI_VEC -10: .long in_nmi -11: -#endif /* defined(CONFIG_KGDB) */ sts pr, k3 ! save original pr value in k3 mova exception_data, k0 @@ -507,13 +485,49 @@ ENTRY(handle_interrupt) bsr save_regs ! needs original pr value in k3 mov #-1, k2 ! default vector kept in k2 + setup_frame_reg + + stc sr, r0 ! get status register + shlr2 r0 + and #0x3c, r0 + cmp/eq #0x3c, r0 + bf 9f + TRACE_IRQS_OFF +9: + ! Setup return address and jump to do_IRQ mov.l 4f, r9 ! fetch return address lds r9, pr ! put return address in pr mov.l 2f, r4 mov.l 3f, r9 mov.l @r4, r4 ! pass INTEVT vector as arg0 + + shlr2 r4 + shlr r4 + mov r4, r0 ! save vector->jmp table offset for later + + shlr2 r4 ! vector to IRQ# conversion + add #-0x10, r4 + + cmp/pz r4 ! is it a valid IRQ? + bt 10f + + /* + * We got here as a result of taking the INTEVT path for something + * that isn't a valid hard IRQ, therefore we bypass the do_IRQ() + * path and special case the event dispatch instead. This is the + * expected path for the NMI (and any other brilliantly implemented + * exception), which effectively wants regular exception dispatch + * but is unfortunately reported through INTEVT rather than + * EXPEVT. Grr. + */ + mov.l 6f, r9 + mov.l @(r0, r9), r9 jmp @r9 + mov r15, r8 ! trap handlers take saved regs in r8 + +10: + jmp @r9 ! Off to do_IRQ() we go. mov r15, r5 ! pass saved registers as arg1 ENTRY(exception_none) diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S index e5a0de39a2db..46610c35c232 100644 --- a/arch/sh/kernel/cpu/sh3/ex.S +++ b/arch/sh/kernel/cpu/sh3/ex.S @@ -48,9 +48,7 @@ ENTRY(exception_handling_table) .long system_call ! Unconditional Trap /* 160 */ .long exception_error ! reserved_instruction (filled by trap_init) /* 180 */ .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/ -ENTRY(nmi_slot) - .long kgdb_handle_exception /* 1C0 */ ! Allow trap to debugger -ENTRY(user_break_point_trap) + .long nmi_trap_handler /* 1C0 */ ! Allow trap to debugger .long break_point_trap /* 1E0 */ /* diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c index 10f2a760c5ee..f9c7df64eb01 100644 --- a/arch/sh/kernel/cpu/sh3/probe.c +++ b/arch/sh/kernel/cpu/sh3/probe.c @@ -107,5 +107,7 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void) boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; boot_cpu_data.icache = boot_cpu_data.dcache; + boot_cpu_data.family = CPU_FAMILY_SH3; + return 0; } diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index 6c78d0a9c857..d36f0c45f55f 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -57,8 +57,12 @@ int __init detect_cpu_and_cache_system(void) * Setup some generic flags we can probe on SH-4A parts */ if (((pvr >> 16) & 0xff) == 0x10) { - if ((cvr & 0x10000000) == 0) + boot_cpu_data.family = CPU_FAMILY_SH4A; + + if ((cvr & 0x10000000) == 0) { boot_cpu_data.flags |= CPU_HAS_DSP; + boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP; + } boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER; boot_cpu_data.cut_major = pvr & 0x7f; @@ -68,6 +72,7 @@ int __init detect_cpu_and_cache_system(void) } else { /* And some SH-4 defaults.. */ boot_cpu_data.flags |= CPU_HAS_PTEA; + boot_cpu_data.family = CPU_FAMILY_SH4; } /* FPU detection works for everyone */ @@ -139,8 +144,15 @@ int __init detect_cpu_and_cache_system(void) } break; case 0x300b: - boot_cpu_data.type = CPU_SH7724; - boot_cpu_data.flags |= CPU_HAS_L2_CACHE; + switch (prr) { + case 0x20: + boot_cpu_data.type = CPU_SH7724; + boot_cpu_data.flags |= CPU_HAS_L2_CACHE; + break; + case 0x50: + boot_cpu_data.type = CPU_SH7757; + break; + } break; case 0x4000: /* 1st cut */ case 0x4001: /* 2nd cut */ @@ -173,9 +185,6 @@ int __init detect_cpu_and_cache_system(void) boot_cpu_data.dcache.ways = 2; break; - default: - boot_cpu_data.type = CPU_SH_NONE; - break; } /* diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index ebdd391d5f42..490d5dc9e372 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -3,6 +3,7 @@ # # CPU subtype setup +obj-$(CONFIG_CPU_SUBTYPE_SH7757) += setup-sh7757.o obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o @@ -19,15 +20,16 @@ obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o smp-$(CONFIG_CPU_SHX3) := smp-shx3.o # Primary on-chip clocks (common) +clock-$(CONFIG_CPU_SUBTYPE_SH7757) := clock-sh7757.o clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o -clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o -clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o -clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o +clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o hwblk-sh7722.o +clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o +clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o hwblk-sh7724.o clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o @@ -35,6 +37,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o +pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index 40f859354f79..ea38b554dc05 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c @@ -22,6 +22,8 @@ #include <linux/kernel.h> #include <linux/io.h> #include <asm/clock.h> +#include <asm/hwblk.h> +#include <cpu/sh7722.h> /* SH7722 registers */ #define FRQCR 0xa4150000 @@ -30,9 +32,6 @@ #define SCLKBCR 0xa415000c #define IRDACLKCR 0xa4150018 #define PLLCR 0xa4150024 -#define MSTPCR0 0xa4150030 -#define MSTPCR1 0xa4150034 -#define MSTPCR2 0xa4150038 #define DLLFRQ 0xa4150050 /* Fixed 32 KHz root clock for RTC and Power Management purposes */ @@ -140,35 +139,37 @@ struct clk div6_clks[] = { SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), }; -#define MSTP(_str, _parent, _reg, _bit, _flags) \ - SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) +#define R_CLK &r_clk +#define P_CLK &div4_clks[DIV4_P] +#define B_CLK &div4_clks[DIV4_B] +#define U_CLK &div4_clks[DIV4_U] static struct clk mstp_clks[] = { - MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), - MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), - MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), - MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), - MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), - MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), - MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), - MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), - MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), - - MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), - MSTP("rtc0", &r_clk, MSTPCR1, 8, 0), - - MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), - MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), - MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), - MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), - MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), - MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), - MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), - MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), - MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), - MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), - MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), - MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), + SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0), + SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), + SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), + SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), + SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), + SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), + SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), + + SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0), + SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), + + SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0), + SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), + SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0), + SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), + SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0), + SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), + SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0), + SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0), + SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0), + SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0), + SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), + SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0), }; int __init arch_clk_init(void) @@ -191,7 +192,7 @@ int __init arch_clk_init(void) ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); + ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c index e67c2678b8ae..20a31c2255a8 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c @@ -22,6 +22,8 @@ #include <linux/kernel.h> #include <linux/io.h> #include <asm/clock.h> +#include <asm/hwblk.h> +#include <cpu/sh7723.h> /* SH7723 registers */ #define FRQCR 0xa4150000 @@ -30,9 +32,6 @@ #define SCLKBCR 0xa415000c #define IRDACLKCR 0xa4150018 #define PLLCR 0xa4150024 -#define MSTPCR0 0xa4150030 -#define MSTPCR1 0xa4150034 -#define MSTPCR2 0xa4150038 #define DLLFRQ 0xa4150050 /* Fixed 32 KHz root clock for RTC and Power Management purposes */ @@ -140,60 +139,64 @@ struct clk div6_clks[] = { SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), }; -#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \ - SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT) +#define R_CLK (&r_clk) +#define P_CLK (&div4_clks[DIV4_P]) +#define B_CLK (&div4_clks[DIV4_B]) +#define U_CLK (&div4_clks[DIV4_U]) +#define I_CLK (&div4_clks[DIV4_I]) +#define SH_CLK (&div4_clks[DIV4_SH]) static struct clk mstp_clks[] = { /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ - MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0), - MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0), - MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0), - MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 28, 1, 1, 0), - MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0), - MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0), - MSTP("intc0", &div4_clks[DIV4_I], MSTPCR0, 22, 1, 1, 0), - MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1), - MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0), - MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0), - MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0), - MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0), - MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0), - MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0), - MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1), - MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 11, 0, 1, 0), - MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0), - MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0), - MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0), - MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0), - MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0), - MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0), - MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0), - MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0), - MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0), - MSTP("meram0", &div4_clks[DIV4_SH], MSTPCR0, 0, 1, 1, 0), - - MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0), - MSTP("rtc0", &r_clk, MSTPCR1, 8, 0, 0, 0), - - MSTP("atapi0", &div4_clks[DIV4_SH], MSTPCR2, 28, 0, 1, 0), - MSTP("adc0", &div4_clks[DIV4_P], MSTPCR2, 27, 0, 1, 0), - MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0), - MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0), - MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0), - MSTP("icb0", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1), - MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0), - MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0), - MSTP("keysc0", &r_clk, MSTPCR2, 14, 0, 0, 0), - MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 11, 0, 1, 0), - MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 10, 0, 1, 1), - MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0, 1, 0), - MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1), - MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1), - MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1), - MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1), - MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1), - MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1), - MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1), + SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("intc0", -1, I_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0), + SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), + SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), + SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), + SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), + SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), + SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), + SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), + SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), + SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), + SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), + SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), + SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), + SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), + SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), + SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), + SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), + SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0), + + SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0), + SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), + + SH_HWBLK_CLK("atapi0", -1, SH_CLK, HWBLK_ATAPI, 0), + SH_HWBLK_CLK("adc0", -1, P_CLK, HWBLK_ADC, 0), + SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0), + SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0), + SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0), + SH_HWBLK_CLK("icb0", -1, B_CLK, HWBLK_ICB, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0), + SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0), + SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), + SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0), + SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), + SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0), + SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0), + SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), + SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0), + SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0), + SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0), + SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), + SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), }; int __init arch_clk_init(void) @@ -216,7 +219,7 @@ int __init arch_clk_init(void) ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); + ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c index 5d5c9b952883..dfe9192be63e 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c @@ -22,6 +22,8 @@ #include <linux/kernel.h> #include <linux/io.h> #include <asm/clock.h> +#include <asm/hwblk.h> +#include <cpu/sh7724.h> /* SH7724 registers */ #define FRQCRA 0xa4150000 @@ -31,9 +33,6 @@ #define FCLKBCR 0xa415000c #define IRDACLKCR 0xa4150018 #define PLLCR 0xa4150024 -#define MSTPCR0 0xa4150030 -#define MSTPCR1 0xa4150034 -#define MSTPCR2 0xa4150038 #define SPUCLKCR 0xa415003c #define FLLFRQ 0xa4150050 #define LSTATS 0xa4150060 @@ -128,7 +127,7 @@ struct clk *main_clks[] = { &div3_clk, }; -static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; static struct clk_div_mult_table div4_table = { .divisors = divisors, @@ -156,64 +155,67 @@ struct clk div6_clks[] = { SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0), }; -#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \ - SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT) +#define R_CLK (&r_clk) +#define P_CLK (&div4_clks[DIV4_P]) +#define B_CLK (&div4_clks[DIV4_B]) +#define I_CLK (&div4_clks[DIV4_I]) +#define SH_CLK (&div4_clks[DIV4_SH]) static struct clk mstp_clks[] = { - MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0), - MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0), - MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0), - MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0), - MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0), - MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0), - MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0), - MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0), - MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1), - MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0), - MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0), - MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0), - MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0), - MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0), - MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0), - MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1), - MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0), - MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0), - MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0), - MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0), - MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0), - MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0), - MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0), - MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0), - MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0), - - MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0), - MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0), - MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0), - MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0), - - MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0), - MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0), - MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0), - MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0), - MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0), - MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0), - MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1), - MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1), - MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1), - MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0), - MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0), - MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1), - MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1), - MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1), - MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1), - MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0), - MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1), - MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1), - MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1), - MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1), - MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1), - MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1), - MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1), + SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("rs0", -1, B_CLK, HWBLK_RSMEM, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("intc0", -1, P_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0), + SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), + SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), + SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), + SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), + SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), + SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), + SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), + SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), + SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), + SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), + SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), + SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), + SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), + SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), + SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), + SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), + + SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), + SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), + SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC0, 0), + SH_HWBLK_CLK("i2c1", -1, P_CLK, HWBLK_IIC1, 0), + + SH_HWBLK_CLK("mmc0", -1, B_CLK, HWBLK_MMC, 0), + SH_HWBLK_CLK("eth0", -1, B_CLK, HWBLK_ETHER, 0), + SH_HWBLK_CLK("atapi0", -1, B_CLK, HWBLK_ATAPI, 0), + SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0), + SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0), + SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0), + SH_HWBLK_CLK("usb1", -1, B_CLK, HWBLK_USB1, 0), + SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB0, 0), + SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), + SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0), + SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0), + SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0), + SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0), + SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0), + SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0), + SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0), + SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0), + SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), + SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0), + SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0), + SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0), + SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), + SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), }; int __init arch_clk_init(void) @@ -236,7 +238,7 @@ int __init arch_clk_init(void) ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); + ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c new file mode 100644 index 000000000000..ddc235ca9664 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c @@ -0,0 +1,130 @@ +/* + * arch/sh/kernel/cpu/sh4/clock-sh7757.c + * + * SH7757 support for the clock framework + * + * Copyright (C) 2009 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <asm/clock.h> +#include <asm/freq.h> + +static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, + 16, 1, 1, 32, 1, 1, 1, 1 }; +static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, + 16, 1, 1, 32, 1, 1, 1, 1 }; +static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, + 16, 1, 1, 32, 1, 1, 1, 1 }; +static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, + 16, 1, 1, 32, 1, 1, 1, 1 }; + +static void master_clk_init(struct clk *clk) +{ + clk->rate = CONFIG_SH_PCLK_FREQ * 16; +} + +static struct clk_ops sh7757_master_clk_ops = { + .init = master_clk_init, +}; + +static void module_clk_recalc(struct clk *clk) +{ + int idx = ctrl_inl(FRQCR) & 0x0000000f; + clk->rate = clk->parent->rate / p1fc_divisors[idx]; +} + +static struct clk_ops sh7757_module_clk_ops = { + .recalc = module_clk_recalc, +}; + +static void bus_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f; + clk->rate = clk->parent->rate / bfc_divisors[idx]; +} + +static struct clk_ops sh7757_bus_clk_ops = { + .recalc = bus_clk_recalc, +}; + +static void cpu_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f; + clk->rate = clk->parent->rate / ifc_divisors[idx]; +} + +static struct clk_ops sh7757_cpu_clk_ops = { + .recalc = cpu_clk_recalc, +}; + +static struct clk_ops *sh7757_clk_ops[] = { + &sh7757_master_clk_ops, + &sh7757_module_clk_ops, + &sh7757_bus_clk_ops, + &sh7757_cpu_clk_ops, +}; + +void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +{ + if (idx < ARRAY_SIZE(sh7757_clk_ops)) + *ops = sh7757_clk_ops[idx]; +} + +static void shyway_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f; + clk->rate = clk->parent->rate / sfc_divisors[idx]; +} + +static struct clk_ops sh7757_shyway_clk_ops = { + .recalc = shyway_clk_recalc, +}; + +static struct clk sh7757_shyway_clk = { + .name = "shyway_clk", + .flags = CLK_ENABLE_ON_INIT, + .ops = &sh7757_shyway_clk_ops, +}; + +/* + * Additional sh7757-specific on-chip clocks that aren't already part of the + * clock framework + */ +static struct clk *sh7757_onchip_clocks[] = { + &sh7757_shyway_clk, +}; + +static int __init sh7757_clk_init(void) +{ + struct clk *clk = clk_get(NULL, "master_clk"); + int i; + + for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) { + struct clk *clkp = sh7757_onchip_clocks[i]; + + clkp->parent = clk; + clk_register(clkp); + clk_enable(clkp); + } + + /* + * Now that we have the rest of the clocks registered, we need to + * force the parent clock to propagate so that these clocks will + * automatically figure out their rate. We cheat by handing the + * parent clock its current rate and forcing child propagation. + */ + clk_set_rate(clk, clk_get_rate(clk)); + + clk_put(clk); + + return 0; +} + +arch_initcall(sh7757_clk_init); + diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c new file mode 100644 index 000000000000..a288b5d92341 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c @@ -0,0 +1,106 @@ +/* + * arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c + * + * SH7722 hardware block support + * + * Copyright (C) 2009 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <asm/suspend.h> +#include <asm/hwblk.h> +#include <cpu/sh7722.h> + +/* SH7722 registers */ +#define MSTPCR0 0xa4150030 +#define MSTPCR1 0xa4150034 +#define MSTPCR2 0xa4150038 + +/* SH7722 Power Domains */ +enum { CORE_AREA, SUB_AREA, CORE_AREA_BM }; +static struct hwblk_area sh7722_hwblk_area[] = { + [CORE_AREA] = HWBLK_AREA(0, 0), + [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA), + [SUB_AREA] = HWBLK_AREA(0, 0), +}; + +/* Table mapping HWBLK to Module Stop Bit and Power Domain */ +static struct hwblk sh7722_hwblk[HWBLK_NR] = { + [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA), + [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA), + [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA), + [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA), + [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA), + [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA), + [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM), + [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA), + [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA), + [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA), + [HWBLK_TMU] = HWBLK(MSTPCR0, 15, CORE_AREA), + [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA), + [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA), + [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA), + [HWBLK_SCIF0] = HWBLK(MSTPCR0, 7, CORE_AREA), + [HWBLK_SCIF1] = HWBLK(MSTPCR0, 6, CORE_AREA), + [HWBLK_SCIF2] = HWBLK(MSTPCR0, 5, CORE_AREA), + [HWBLK_SIO] = HWBLK(MSTPCR0, 3, CORE_AREA), + [HWBLK_SIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA), + [HWBLK_SIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA), + + [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA), + [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA), + + [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA), + [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA), + [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA), + [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA), + [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA), + [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA), + [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA), + [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM), + [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA), + [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM), + [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM), + [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM), + [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM), + [HWBLK_VEU] = HWBLK(MSTPCR2, 2, CORE_AREA_BM), + [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM), + [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM), +}; + +static struct hwblk_info sh7722_hwblk_info = { + .areas = sh7722_hwblk_area, + .nr_areas = ARRAY_SIZE(sh7722_hwblk_area), + .hwblks = sh7722_hwblk, + .nr_hwblks = ARRAY_SIZE(sh7722_hwblk), +}; + +int arch_hwblk_sleep_mode(void) +{ + if (!sh7722_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE]) + return SUSP_SH_STANDBY | SUSP_SH_SF; + + if (!sh7722_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE]) + return SUSP_SH_SLEEP | SUSP_SH_SF; + + return SUSP_SH_SLEEP; +} + +int __init arch_hwblk_init(void) +{ + return hwblk_register(&sh7722_hwblk_info); +} diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c new file mode 100644 index 000000000000..a7f4684d2032 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c @@ -0,0 +1,117 @@ +/* + * arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c + * + * SH7723 hardware block support + * + * Copyright (C) 2009 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <asm/suspend.h> +#include <asm/hwblk.h> +#include <cpu/sh7723.h> + +/* SH7723 registers */ +#define MSTPCR0 0xa4150030 +#define MSTPCR1 0xa4150034 +#define MSTPCR2 0xa4150038 + +/* SH7723 Power Domains */ +enum { CORE_AREA, SUB_AREA, CORE_AREA_BM }; +static struct hwblk_area sh7723_hwblk_area[] = { + [CORE_AREA] = HWBLK_AREA(0, 0), + [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA), + [SUB_AREA] = HWBLK_AREA(0, 0), +}; + +/* Table mapping HWBLK to Module Stop Bit and Power Domain */ +static struct hwblk sh7723_hwblk[HWBLK_NR] = { + [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA), + [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA), + [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA), + [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA), + [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA), + [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA), + [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA), + [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM), + [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA), + [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA), + [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA), + [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA), + [HWBLK_SUBC] = HWBLK(MSTPCR0, 16, CORE_AREA), + [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA), + [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA), + [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA), + [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM), + [HWBLK_TMU1] = HWBLK(MSTPCR0, 11, CORE_AREA), + [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA), + [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA), + [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA), + [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA), + [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA), + [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA), + [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA), + [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA), + [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA), + [HWBLK_MERAM] = HWBLK(MSTPCR0, 0, CORE_AREA), + + [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA), + [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA), + + [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM), + [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA), + [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA), + [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA), + [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA), + [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM), + [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA), + [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA), + [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA), + [HWBLK_USB] = HWBLK(MSTPCR2, 11, CORE_AREA), + [HWBLK_2DG] = HWBLK(MSTPCR2, 10, CORE_AREA_BM), + [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA), + [HWBLK_VEU2H1] = HWBLK(MSTPCR2, 6, CORE_AREA_BM), + [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM), + [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM), + [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM), + [HWBLK_VEU2H0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM), + [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM), + [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM), +}; + +static struct hwblk_info sh7723_hwblk_info = { + .areas = sh7723_hwblk_area, + .nr_areas = ARRAY_SIZE(sh7723_hwblk_area), + .hwblks = sh7723_hwblk, + .nr_hwblks = ARRAY_SIZE(sh7723_hwblk), +}; + +int arch_hwblk_sleep_mode(void) +{ + if (!sh7723_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE]) + return SUSP_SH_STANDBY | SUSP_SH_SF; + + if (!sh7723_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE]) + return SUSP_SH_SLEEP | SUSP_SH_SF; + + return SUSP_SH_SLEEP; +} + +int __init arch_hwblk_init(void) +{ + return hwblk_register(&sh7723_hwblk_info); +} diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c new file mode 100644 index 000000000000..1613ad6013c3 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c @@ -0,0 +1,121 @@ +/* + * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c + * + * SH7724 hardware block support + * + * Copyright (C) 2009 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <asm/suspend.h> +#include <asm/hwblk.h> +#include <cpu/sh7724.h> + +/* SH7724 registers */ +#define MSTPCR0 0xa4150030 +#define MSTPCR1 0xa4150034 +#define MSTPCR2 0xa4150038 + +/* SH7724 Power Domains */ +enum { CORE_AREA, SUB_AREA, CORE_AREA_BM }; +static struct hwblk_area sh7724_hwblk_area[] = { + [CORE_AREA] = HWBLK_AREA(0, 0), + [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA), + [SUB_AREA] = HWBLK_AREA(0, 0), +}; + +/* Table mapping HWBLK to Module Stop Bit and Power Domain */ +static struct hwblk sh7724_hwblk[HWBLK_NR] = { + [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA), + [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA), + [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA), + [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA), + [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA), + [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA), + [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA), + [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA), + [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM), + [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA), + [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA), + [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA), + [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA), + [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA), + [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA), + [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA), + [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM), + [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA), + [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA), + [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA), + [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA), + [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA), + [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA), + [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA), + [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA), + [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA), + + [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA), + [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA), + [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA), + [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA), + + [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA), + [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM), + [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM), + [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA), + [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA), + [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA), + [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA), + [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA), + [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM), + [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA), + [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA), + [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM), + [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM), + [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM), + [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM), + [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM), + [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM), + [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM), + [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM), + [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM), + [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM), + [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM), + [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM), +}; + +static struct hwblk_info sh7724_hwblk_info = { + .areas = sh7724_hwblk_area, + .nr_areas = ARRAY_SIZE(sh7724_hwblk_area), + .hwblks = sh7724_hwblk, + .nr_hwblks = ARRAY_SIZE(sh7724_hwblk), +}; + +int arch_hwblk_sleep_mode(void) +{ + if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE]) + return SUSP_SH_STANDBY | SUSP_SH_SF; + + if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE]) + return SUSP_SH_SLEEP | SUSP_SH_SF; + + return SUSP_SH_SLEEP; +} + +int __init arch_hwblk_init(void) +{ + return hwblk_register(&sh7724_hwblk_info); +} diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c new file mode 100644 index 000000000000..ed23b155c097 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c @@ -0,0 +1,2019 @@ +/* + * SH7757 (A0 step) Pinmux + * + * Copyright (C) 2009 Renesas Solutions Corp. + * + * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * Based on SH7757 Pinmux + * Copyright (C) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <cpu/sh7757.h> + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, + PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA, + PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, + PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA, + PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, + PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA, + PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, + PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA, + PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, + PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA, + PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, + PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA, + PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA, + PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA, + PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, + PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, + PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA, + PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA, + PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, + PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA, + PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, + PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, + PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, + PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, + PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, + PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA, + PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA, + PTP6_DATA, PTP5_DATA, PTP4_DATA, + PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA, + PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, + PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, + PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, + PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, + PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, + PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, + PTT5_DATA, PTT4_DATA, + PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, + PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, + PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, + PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, + PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA, + PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, + PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA, + PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, + PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA, + PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, + PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA, + PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, + PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA, + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN, + PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN, + PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN, + PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN, + PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN, + PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN, + PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, + PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN, + PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN, + PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN, + PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN, + PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN, + PTG7_IN, PTG6_IN, PTG5_IN, PTG4_IN, + PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN, + PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN, + PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN, + PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN, + PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN, + PTJ7_IN, PTJ6_IN, PTJ5_IN, PTJ4_IN, + PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN, + PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN, + PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN, + PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, + PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, + PTM6_IN, PTM5_IN, PTM4_IN, + PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, + PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, + PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, + PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN, + PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN, + PTP6_IN, PTP5_IN, PTP4_IN, + PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN, + PTQ6_IN, PTQ5_IN, PTQ4_IN, + PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN, + PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN, + PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN, + PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN, + PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN, + PTT5_IN, PTT4_IN, + PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN, + PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN, + PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, + PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN, + PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, + PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN, + PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN, + PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN, + PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN, + PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN, + PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN, + PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN, + PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, + PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, + PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, + PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, + PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU, + PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU, + PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, + PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, + PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, + PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, + PINMUX_INPUT_PULLUP_END, + + PINMUX_OUTPUT_BEGIN, + PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, + PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, + PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, + PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT, + PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT, + PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT, + PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT, + PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT, + PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT, + PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT, + PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT, + PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT, + PTG7_OUT, PTG6_OUT, PTG5_OUT, PTG4_OUT, + PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT, + PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT, + PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, + PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT, + PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT, + PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ4_OUT, + PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT, + PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT, + PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT, + PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, + PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, + PTM6_OUT, PTM5_OUT, PTM4_OUT, + PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, + PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, + PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, + PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT, + PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT, + PTP6_OUT, PTP5_OUT, PTP4_OUT, + PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT, + PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, + PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT, + PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT, + PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT, + PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT, + PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT, + PTT5_OUT, PTT4_OUT, + PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT, + PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT, + PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT, + PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT, + PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT, + PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT, + PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT, + PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT, + PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT, + PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT, + PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT, + PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT, + PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT, + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN, + PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN, + PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN, + PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN, + PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN, + PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN, + PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN, + PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN, + PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN, + PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN, + PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN, + PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN, + PTG7_FN, PTG6_FN, PTG5_FN, PTG4_FN, + PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN, + PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN, + PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN, + PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN, + PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN, + PTJ7_FN, PTJ6_FN, PTJ5_FN, PTJ4_FN, + PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN, + PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN, + PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN, + PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, + PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN, + PTM6_FN, PTM5_FN, PTM4_FN, + PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN, + PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN, + PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN, + PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN, + PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN, + PTP6_FN, PTP5_FN, PTP4_FN, + PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN, + PTQ6_FN, PTQ5_FN, PTQ4_FN, + PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN, + PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN, + PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN, + PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN, + PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN, + PTT5_FN, PTT4_FN, + PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN, + PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN, + PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN, + PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN, + PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN, + PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN, + PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN, + PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN, + PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN, + PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN, + PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN, + PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, + PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, + + PS0_15_FN1, PS0_15_FN3, + PS0_14_FN1, PS0_14_FN3, + PS0_13_FN1, PS0_13_FN3, + PS0_12_FN1, PS0_12_FN3, + PS0_7_FN1, PS0_7_FN2, + PS0_6_FN1, PS0_6_FN2, + PS0_5_FN1, PS0_5_FN2, + PS0_4_FN1, PS0_4_FN2, + PS0_3_FN1, PS0_3_FN2, + PS0_2_FN1, PS0_2_FN2, + PS0_1_FN1, PS0_1_FN2, + + PS1_7_FN1, PS1_7_FN3, + PS1_6_FN1, PS1_6_FN3, + + PS2_13_FN1, PS2_13_FN3, + PS2_12_FN1, PS2_12_FN3, + PS2_1_FN1, PS2_1_FN2, + PS2_0_FN1, PS2_0_FN2, + + PS4_15_FN1, PS4_15_FN2, + PS4_14_FN1, PS4_14_FN2, + PS4_13_FN1, PS4_13_FN2, + PS4_12_FN1, PS4_12_FN2, + PS4_11_FN1, PS4_11_FN2, + PS4_10_FN1, PS4_10_FN2, + PS4_9_FN1, PS4_9_FN2, + PS4_3_FN1, PS4_3_FN2, + PS4_2_FN1, PS4_2_FN2, + PS4_1_FN1, PS4_1_FN2, + PS4_0_FN1, PS4_0_FN2, + + PS5_9_FN1, PS5_9_FN2, + PS5_8_FN1, PS5_8_FN2, + PS5_7_FN1, PS5_7_FN2, + PS5_6_FN1, PS5_6_FN2, + PS5_5_FN1, PS5_5_FN2, + PS5_4_FN1, PS5_4_FN2, + + /* AN15 to 8 : EVENT15 to 8 */ + PS6_7_FN_AN, PS6_7_FN_EV, + PS6_6_FN_AN, PS6_6_FN_EV, + PS6_5_FN_AN, PS6_5_FN_EV, + PS6_4_FN_AN, PS6_4_FN_EV, + PS6_3_FN_AN, PS6_3_FN_EV, + PS6_2_FN_AN, PS6_2_FN_EV, + PS6_1_FN_AN, PS6_1_FN_EV, + PS6_0_FN_AN, PS6_0_FN_EV, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + /* PTA (mobule: LBSC, CPG, LPC) */ + BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK, + MD10_MARK, MD9_MARK, MD8_MARK, + LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK, + LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK, + + /* PTB (mobule: LBSC, EtherC, SIM, LPC) */ + D15_MARK, D14_MARK, D13_MARK, D12_MARK, + D11_MARK, D10_MARK, D9_MARK, D8_MARK, + ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK, + SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK, + WPSZ1_MARK, WPSZ0_MARK, FWID_MARK, FLSHSZ_MARK, + LPC_SPIEN_MARK, BASEL_MARK, + + /* PTC (mobule: SD) */ + SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK, + SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK, + + /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ + IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK, + IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK, + MD6_MARK, MD5_MARK, MD3_MARK, MD2_MARK, + MD1_MARK, MD0_MARK, ADTRG1_MARK, ADTRG0_MARK, + + /* PTE (mobule: EtherC) */ + ET0_CRS_DV_MARK, ET0_TXD1_MARK, + ET0_TXD0_MARK, ET0_TX_EN_MARK, + ET0_REF_CLK_MARK, ET0_RXD1_MARK, + ET0_RXD0_MARK, ET0_RX_ER_MARK, + + /* PTF (mobule: EtherC) */ + ET1_CRS_DV_MARK, ET1_TXD1_MARK, + ET1_TXD0_MARK, ET1_TX_EN_MARK, + ET1_REF_CLK_MARK, ET1_RXD1_MARK, + ET1_RXD0_MARK, ET1_RX_ER_MARK, + + /* PTG (mobule: SYSTEM, PWMX, LPC) */ + STATUS0_MARK, STATUS1_MARK, + PWX0_MARK, PWX1_MARK, PWX2_MARK, PWX3_MARK, + SERIRQ_MARK, CLKRUN_MARK, LPCPD_MARK, LDRQ_MARK, + + /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ + TCLK_MARK, RXD4_MARK, TXD4_MARK, + SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK, + SP1_SS0_MARK, SP1_SS1_MARK, SP0_SS1_MARK, + + /* PTI (mobule: INTC) */ + IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK, + IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK, + + /* PTJ (mobule: SCIF234, SERMUX) */ + RXD3_MARK, TXD3_MARK, RXD2_MARK, TXD2_MARK, + COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK, + + /* PTK (mobule: SERMUX) */ + COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK, + COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, COM2_RI_MARK, + + /* PTL (mobule: SERMUX) */ + RAC_TXD_MARK, RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, + RAC_DTR_MARK, RAC_DSR_MARK, RAC_DCD_MARK, RAC_RI_MARK, + + /* PTM (mobule: IIC, LPC) */ + SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK, + WP_MARK, FMS0_MARK, FMS1_MARK, + + /* PTN (mobule: SCIF234, EVC) */ + SCK2_MARK, RTS4_MARK, RTS3_MARK, RTS2_MARK, + CTS4_MARK, CTS3_MARK, CTS2_MARK, + EVENT7_MARK, EVENT6_MARK, EVENT5_MARK, EVENT4_MARK, + EVENT3_MARK, EVENT2_MARK, EVENT1_MARK, EVENT0_MARK, + + /* PTO (mobule: SGPIO) */ + SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, + SGPIO0_DI_MARK, SGPIO0_DO_MARK, + SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, + SGPIO1_DI_MARK, SGPIO1_DO_MARK, + + /* PTP (mobule: JMC, SCIF234) */ + JMCTCK_MARK, JMCTMS_MARK, JMCTDO_MARK, JMCTDI_MARK, + JMCRST_MARK, SCK4_MARK, SCK3_MARK, + + /* PTQ (mobule: LPC) */ + LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK, + LFRAME_MARK, LRESET_MARK, LCLK_MARK, + + /* PTR (mobule: GRA, IIC) */ + DDC3_MARK, DDC2_MARK, + SDA8_MARK, SCL8_MARK, SDA2_MARK, SCL2_MARK, + SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK, + + /* PTS (mobule: GRA, IIC) */ + DDC1_MARK, DDC0_MARK, + SDA9_MARK, SCL9_MARK, SDA5_MARK, SCL5_MARK, + SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK, + + /* PTT (mobule: SYSTEM, PWMX) */ + AUDSYNC_MARK, AUDCK_MARK, + AUDATA3_MARK, AUDATA2_MARK, + AUDATA1_MARK, AUDATA0_MARK, + PWX7_MARK, PWX6_MARK, PWX5_MARK, PWX4_MARK, + + /* PTU (mobule: LBSC, DMAC) */ + CS6_MARK, CS5_MARK, CS4_MARK, CS0_MARK, + RD_MARK, WE0_MARK, A25_MARK, A24_MARK, + DREQ0_MARK, DACK0_MARK, + + /* PTV (mobule: LBSC, DMAC) */ + A23_MARK, A22_MARK, A21_MARK, A20_MARK, + A19_MARK, A18_MARK, A17_MARK, A16_MARK, + TEND0_MARK, DREQ1_MARK, DACK1_MARK, TEND1_MARK, + + /* PTW (mobule: LBSC) */ + A15_MARK, A14_MARK, A13_MARK, A12_MARK, + A11_MARK, A10_MARK, A9_MARK, A8_MARK, + + /* PTX (mobule: LBSC) */ + A7_MARK, A6_MARK, A5_MARK, A4_MARK, + A3_MARK, A2_MARK, A1_MARK, A0_MARK, + + /* PTY (mobule: LBSC) */ + D7_MARK, D6_MARK, D5_MARK, D4_MARK, + D3_MARK, D2_MARK, D1_MARK, D0_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + /* PTA GPIO */ + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), + PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), + PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT), + PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT), + PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT), + PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT), + PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT), + + /* PTB GPIO */ + PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), + PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), + PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), + PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), + PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), + PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), + PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), + PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), + + /* PTC GPIO */ + PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT), + PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT), + PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT), + PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), + PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), + PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), + PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT), + PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), + + /* PTD GPIO */ + PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT), + PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT), + PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT), + PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT), + PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT), + PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT), + PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT), + PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), + + /* PTE GPIO */ + PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT), + PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), + PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), + PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT), + PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT), + PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT), + + /* PTF GPIO */ + PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT), + PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT), + PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT), + PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT), + PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT), + PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT), + PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT), + PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT), + + /* PTG GPIO */ + PINMUX_DATA(PTG7_DATA, PTG7_IN, PTG7_OUT), + PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT), + PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT), + PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT), + PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT), + PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT), + PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT), + PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT), + + /* PTH GPIO */ + PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT), + PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT), + PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT), + PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT), + PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT), + PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT), + PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT), + PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT), + + /* PTI GPIO */ + PINMUX_DATA(PTI7_DATA, PTI7_IN, PTI7_OUT), + PINMUX_DATA(PTI6_DATA, PTI6_IN, PTI6_OUT), + PINMUX_DATA(PTI5_DATA, PTI5_IN, PTI5_OUT), + PINMUX_DATA(PTI4_DATA, PTI4_IN, PTI4_OUT), + PINMUX_DATA(PTI3_DATA, PTI3_IN, PTI3_OUT), + PINMUX_DATA(PTI2_DATA, PTI2_IN, PTI2_OUT), + PINMUX_DATA(PTI1_DATA, PTI1_IN, PTI1_OUT), + PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT), + + /* PTJ GPIO */ + PINMUX_DATA(PTJ7_DATA, PTJ7_IN, PTJ7_OUT), + PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT), + PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT), + PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT), + PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT), + PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT), + PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT), + PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT), + + /* PTK GPIO */ + PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT), + PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT), + PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT), + PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT), + PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT), + PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT), + PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT), + PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), + + /* PTL GPIO */ + PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT), + PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), + PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), + PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), + PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT), + PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT), + PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT), + PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT), + + /* PTM GPIO */ + PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT), + PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT), + PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT), + PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT), + PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT), + PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT), + PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), + + /* PTN GPIO */ + PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT), + PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT), + PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT), + PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT), + PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT), + PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT), + PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT), + PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT), + + /* PTO GPIO */ + PINMUX_DATA(PTO7_DATA, PTO7_IN, PTO7_OUT), + PINMUX_DATA(PTO6_DATA, PTO6_IN, PTO6_OUT), + PINMUX_DATA(PTO5_DATA, PTO5_IN, PTO5_OUT), + PINMUX_DATA(PTO4_DATA, PTO4_IN, PTO4_OUT), + PINMUX_DATA(PTO3_DATA, PTO3_IN, PTO3_OUT), + PINMUX_DATA(PTO2_DATA, PTO2_IN, PTO2_OUT), + PINMUX_DATA(PTO1_DATA, PTO1_IN, PTO1_OUT), + PINMUX_DATA(PTO0_DATA, PTO0_IN, PTO0_OUT), + + /* PTQ GPIO */ + PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT), + PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT), + PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT), + PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT), + PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT), + PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT), + PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT), + + /* PTR GPIO */ + PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT), + PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT), + PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT), + PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT), + PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT), + PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT), + PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT), + PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT), + + /* PTS GPIO */ + PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT), + PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT), + PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT), + PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT), + PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT), + PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT), + PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT), + PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), + + /* PTT GPIO */ + PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT), + PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), + PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), + PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT), + PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT), + PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT), + + /* PTU GPIO */ + PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT), + PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT), + PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT), + PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT), + PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT), + PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT), + PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT), + PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT), + + /* PTV GPIO */ + PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT), + PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT), + PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT), + PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT), + PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT), + PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT), + PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT), + PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT), + + /* PTW GPIO */ + PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT), + PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT), + PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT), + PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT), + PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT), + PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT), + PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT), + PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT), + + /* PTX GPIO */ + PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT), + PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT), + PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT), + PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT), + PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT), + PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT), + PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT), + PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT), + + /* PTY GPIO */ + PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT), + PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT), + PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT), + PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT), + PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT), + PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT), + PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT), + PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT), + + /* PTZ GPIO */ + PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT), + PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT), + PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT), + PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT), + PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT), + PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT), + PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT), + PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT), + + /* PTA FN */ + PINMUX_DATA(BS_MARK, PS0_15_FN1, PTA7_FN), + PINMUX_DATA(LGPIO7_MARK, PS0_15_FN3, PTA7_FN), + PINMUX_DATA(RDWR_MARK, PS0_14_FN1, PTA6_FN), + PINMUX_DATA(LGPIO6_MARK, PS0_14_FN3, PTA6_FN), + PINMUX_DATA(WE1_MARK, PS0_13_FN1, PTA5_FN), + PINMUX_DATA(LGPIO5_MARK, PS0_13_FN3, PTA5_FN), + PINMUX_DATA(RDY_MARK, PS0_12_FN1, PTA4_FN), + PINMUX_DATA(LGPIO4_MARK, PS0_12_FN3, PTA4_FN), + PINMUX_DATA(LGPIO3_MARK, PTA3_FN), + PINMUX_DATA(LGPIO2_MARK, PTA2_FN), + PINMUX_DATA(LGPIO1_MARK, PTA1_FN), + PINMUX_DATA(LGPIO0_MARK, PTA0_FN), + + /* PTB FN */ + PINMUX_DATA(D15_MARK, PS0_7_FN1, PTB7_FN), + PINMUX_DATA(ET0_MDC_MARK, PS0_7_FN2, PTB7_FN), + PINMUX_DATA(D14_MARK, PS0_6_FN1, PTB6_FN), + PINMUX_DATA(ET0_MDIO_MARK, PS0_6_FN2, PTB6_FN), + PINMUX_DATA(D13_MARK, PS0_5_FN1, PTB5_FN), + PINMUX_DATA(ET1_MDC_MARK, PS0_5_FN2, PTB5_FN), + PINMUX_DATA(D12_MARK, PS0_4_FN1, PTB4_FN), + PINMUX_DATA(ET1_MDIO_MARK, PS0_4_FN2, PTB4_FN), + PINMUX_DATA(D11_MARK, PS0_3_FN1, PTB3_FN), + PINMUX_DATA(SIM_D_MARK, PS0_3_FN2, PTB3_FN), + PINMUX_DATA(D10_MARK, PS0_2_FN1, PTB2_FN), + PINMUX_DATA(SIM_CLK_MARK, PS0_2_FN2, PTB2_FN), + PINMUX_DATA(D9_MARK, PS0_1_FN1, PTB1_FN), + PINMUX_DATA(SIM_RST_MARK, PS0_1_FN2, PTB1_FN), + PINMUX_DATA(D8_MARK, PTB0_FN), + + /* PTC FN */ + PINMUX_DATA(SD_WP_MARK, PTC7_FN), + PINMUX_DATA(SD_CD_MARK, PTC6_FN), + PINMUX_DATA(SD_CLK_MARK, PTC5_FN), + PINMUX_DATA(SD_CMD_MARK, PTC4_FN), + PINMUX_DATA(SD_D3_MARK, PTC3_FN), + PINMUX_DATA(SD_D2_MARK, PTC2_FN), + PINMUX_DATA(SD_D1_MARK, PTC1_FN), + PINMUX_DATA(SD_D0_MARK, PTC0_FN), + + /* PTD FN */ + PINMUX_DATA(IRQ7_MARK, PS1_7_FN1, PTD7_FN), + PINMUX_DATA(ADTRG1_MARK, PS1_7_FN3, PTD7_FN), + PINMUX_DATA(IRQ6_MARK, PS1_6_FN1, PTD6_FN), + PINMUX_DATA(ADTRG0_MARK, PS1_6_FN3, PTD6_FN), + PINMUX_DATA(IRQ5_MARK, PTD5_FN), + PINMUX_DATA(IRQ4_MARK, PTD4_FN), + PINMUX_DATA(IRQ3_MARK, PTD3_FN), + PINMUX_DATA(IRQ2_MARK, PTD2_FN), + PINMUX_DATA(IRQ1_MARK, PTD1_FN), + PINMUX_DATA(IRQ0_MARK, PTD0_FN), + + /* PTE FN */ + PINMUX_DATA(ET0_CRS_DV_MARK, PTE7_FN), + PINMUX_DATA(ET0_TXD1_MARK, PTE6_FN), + PINMUX_DATA(ET0_TXD0_MARK, PTE5_FN), + PINMUX_DATA(ET0_TX_EN_MARK, PTE4_FN), + PINMUX_DATA(ET0_REF_CLK_MARK, PTE3_FN), + PINMUX_DATA(ET0_RXD1_MARK, PTE2_FN), + PINMUX_DATA(ET0_RXD0_MARK, PTE1_FN), + PINMUX_DATA(ET0_RX_ER_MARK, PTE0_FN), + + /* PTF FN */ + PINMUX_DATA(ET1_CRS_DV_MARK, PTF7_FN), + PINMUX_DATA(ET1_TXD1_MARK, PTF6_FN), + PINMUX_DATA(ET1_TXD0_MARK, PTF5_FN), + PINMUX_DATA(ET1_TX_EN_MARK, PTF4_FN), + PINMUX_DATA(ET1_REF_CLK_MARK, PTF3_FN), + PINMUX_DATA(ET1_RXD1_MARK, PTF2_FN), + PINMUX_DATA(ET1_RXD0_MARK, PTF1_FN), + PINMUX_DATA(ET1_RX_ER_MARK, PTF0_FN), + + /* PTG FN */ + PINMUX_DATA(PWX0_MARK, PTG7_FN), + PINMUX_DATA(PWX1_MARK, PTG6_FN), + PINMUX_DATA(STATUS0_MARK, PS2_13_FN1, PTG5_FN), + PINMUX_DATA(PWX2_MARK, PS2_13_FN3, PTG5_FN), + PINMUX_DATA(STATUS1_MARK, PS2_12_FN1, PTG4_FN), + PINMUX_DATA(PWX3_MARK, PS2_12_FN3, PTG4_FN), + PINMUX_DATA(SERIRQ_MARK, PTG3_FN), + PINMUX_DATA(CLKRUN_MARK, PTG2_FN), + PINMUX_DATA(LPCPD_MARK, PTG1_FN), + PINMUX_DATA(LDRQ_MARK, PTG0_FN), + + /* PTH FN */ + PINMUX_DATA(SP1_MOSI_MARK, PTH7_FN), + PINMUX_DATA(SP1_MISO_MARK, PTH6_FN), + PINMUX_DATA(SP1_SCK_MARK, PTH5_FN), + PINMUX_DATA(SP1_SCK_FB_MARK, PTH4_FN), + PINMUX_DATA(SP1_SS0_MARK, PTH3_FN), + PINMUX_DATA(TCLK_MARK, PTH2_FN), + PINMUX_DATA(RXD4_MARK, PS2_1_FN1, PTH1_FN), + PINMUX_DATA(SP1_SS1_MARK, PS2_1_FN2, PTH1_FN), + PINMUX_DATA(TXD4_MARK, PS2_0_FN1, PTH0_FN), + PINMUX_DATA(SP0_SS1_MARK, PS2_0_FN2, PTH0_FN), + + /* PTI FN */ + PINMUX_DATA(IRQ15_MARK, PTI7_FN), + PINMUX_DATA(IRQ14_MARK, PTI6_FN), + PINMUX_DATA(IRQ13_MARK, PTI5_FN), + PINMUX_DATA(IRQ12_MARK, PTI4_FN), + PINMUX_DATA(IRQ11_MARK, PTI3_FN), + PINMUX_DATA(IRQ10_MARK, PTI2_FN), + PINMUX_DATA(IRQ9_MARK, PTI1_FN), + PINMUX_DATA(IRQ8_MARK, PTI0_FN), + + /* PTJ FN */ + PINMUX_DATA(RXD3_MARK, PTJ7_FN), + PINMUX_DATA(TXD3_MARK, PTJ6_FN), + PINMUX_DATA(RXD2_MARK, PTJ5_FN), + PINMUX_DATA(TXD2_MARK, PTJ4_FN), + PINMUX_DATA(COM1_TXD_MARK, PTJ3_FN), + PINMUX_DATA(COM1_RXD_MARK, PTJ2_FN), + PINMUX_DATA(COM1_RTS_MARK, PTJ1_FN), + PINMUX_DATA(COM1_CTS_MARK, PTJ0_FN), + + /* PTK FN */ + PINMUX_DATA(COM2_TXD_MARK, PTK7_FN), + PINMUX_DATA(COM2_RXD_MARK, PTK6_FN), + PINMUX_DATA(COM2_RTS_MARK, PTK5_FN), + PINMUX_DATA(COM2_CTS_MARK, PTK4_FN), + PINMUX_DATA(COM2_DTR_MARK, PTK3_FN), + PINMUX_DATA(COM2_DSR_MARK, PTK2_FN), + PINMUX_DATA(COM2_DCD_MARK, PTK1_FN), + PINMUX_DATA(COM2_RI_MARK, PTK0_FN), + + /* PTL FN */ + PINMUX_DATA(RAC_TXD_MARK, PTL7_FN), + PINMUX_DATA(RAC_RXD_MARK, PTL6_FN), + PINMUX_DATA(RAC_RTS_MARK, PTL5_FN), + PINMUX_DATA(RAC_CTS_MARK, PTL4_FN), + PINMUX_DATA(RAC_DTR_MARK, PTL3_FN), + PINMUX_DATA(RAC_DSR_MARK, PTL2_FN), + PINMUX_DATA(RAC_DCD_MARK, PTL1_FN), + PINMUX_DATA(RAC_RI_MARK, PTL0_FN), + + /* PTM FN */ + PINMUX_DATA(WP_MARK, PTM6_FN), + PINMUX_DATA(FMS0_MARK, PTM5_FN), + PINMUX_DATA(FMS1_MARK, PTM4_FN), + PINMUX_DATA(SDA6_MARK, PTM3_FN), + PINMUX_DATA(SCL6_MARK, PTM2_FN), + PINMUX_DATA(SDA7_MARK, PTM1_FN), + PINMUX_DATA(SCL7_MARK, PTM0_FN), + + /* PTN FN */ + PINMUX_DATA(SCK2_MARK, PS4_15_FN1, PTN7_FN), + PINMUX_DATA(EVENT7_MARK, PS4_15_FN2, PTN7_FN), + PINMUX_DATA(RTS4_MARK, PS4_14_FN1, PTN6_FN), + PINMUX_DATA(EVENT6_MARK, PS4_14_FN2, PTN6_FN), + PINMUX_DATA(RTS3_MARK, PS4_13_FN1, PTN5_FN), + PINMUX_DATA(EVENT5_MARK, PS4_13_FN2, PTN5_FN), + PINMUX_DATA(RTS2_MARK, PS4_12_FN1, PTN4_FN), + PINMUX_DATA(EVENT4_MARK, PS4_12_FN2, PTN4_FN), + PINMUX_DATA(CTS4_MARK, PS4_11_FN1, PTN3_FN), + PINMUX_DATA(EVENT3_MARK, PS4_11_FN2, PTN3_FN), + PINMUX_DATA(CTS3_MARK, PS4_10_FN1, PTN2_FN), + PINMUX_DATA(EVENT2_MARK, PS4_10_FN2, PTN2_FN), + PINMUX_DATA(CTS2_MARK, PS4_9_FN1, PTN1_FN), + PINMUX_DATA(EVENT1_MARK, PS4_9_FN2, PTN1_FN), + PINMUX_DATA(EVENT0_MARK, PTN0_FN), + + /* PTO FN */ + PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN), + PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN), + PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN), + PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN), + PINMUX_DATA(SGPIO1_CLK_MARK, PTO3_FN), + PINMUX_DATA(SGPIO1_LOAD_MARK, PTO2_FN), + PINMUX_DATA(SGPIO1_DI_MARK, PTO1_FN), + PINMUX_DATA(SGPIO1_DO_MARK, PTO0_FN), + + /* PTP FN */ + PINMUX_DATA(JMCTCK_MARK, PTP6_FN), + PINMUX_DATA(JMCTMS_MARK, PTP5_FN), + PINMUX_DATA(JMCTDO_MARK, PTP4_FN), + PINMUX_DATA(JMCTDI_MARK, PTP3_FN), + PINMUX_DATA(JMCRST_MARK, PTP2_FN), + PINMUX_DATA(SCK4_MARK, PTP1_FN), + PINMUX_DATA(SCK3_MARK, PTP0_FN), + + /* PTQ FN */ + PINMUX_DATA(LAD3_MARK, PTQ6_FN), + PINMUX_DATA(LAD2_MARK, PTQ5_FN), + PINMUX_DATA(LAD1_MARK, PTQ4_FN), + PINMUX_DATA(LAD0_MARK, PTQ3_FN), + PINMUX_DATA(LFRAME_MARK, PTQ2_FN), + PINMUX_DATA(SCK4_MARK, PTQ1_FN), + PINMUX_DATA(SCK3_MARK, PTQ0_FN), + + /* PTR FN */ + PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */ + PINMUX_DATA(SCL8_MARK, PTR6_FN), /* DDC2? */ + PINMUX_DATA(SDA2_MARK, PTR5_FN), + PINMUX_DATA(SCL2_MARK, PTR4_FN), + PINMUX_DATA(SDA1_MARK, PTR3_FN), + PINMUX_DATA(SCL1_MARK, PTR2_FN), + PINMUX_DATA(SDA0_MARK, PTR1_FN), + PINMUX_DATA(SCL0_MARK, PTR0_FN), + + /* PTS FN */ + PINMUX_DATA(SDA9_MARK, PTS7_FN), /* DDC1? */ + PINMUX_DATA(SCL9_MARK, PTS6_FN), /* DDC0? */ + PINMUX_DATA(SDA5_MARK, PTS5_FN), + PINMUX_DATA(SCL5_MARK, PTS4_FN), + PINMUX_DATA(SDA4_MARK, PTS3_FN), + PINMUX_DATA(SCL4_MARK, PTS2_FN), + PINMUX_DATA(SDA3_MARK, PTS1_FN), + PINMUX_DATA(SCL3_MARK, PTS0_FN), + + /* PTT FN */ + PINMUX_DATA(AUDSYNC_MARK, PTS5_FN), + PINMUX_DATA(AUDCK_MARK, PTS4_FN), + PINMUX_DATA(AUDATA3_MARK, PS4_3_FN1, PTS3_FN), + PINMUX_DATA(PWX7_MARK, PS4_3_FN2, PTS3_FN), + PINMUX_DATA(AUDATA2_MARK, PS4_2_FN1, PTS2_FN), + PINMUX_DATA(PWX6_MARK, PS4_2_FN2, PTS2_FN), + PINMUX_DATA(AUDATA1_MARK, PS4_1_FN1, PTS1_FN), + PINMUX_DATA(PWX5_MARK, PS4_1_FN2, PTS1_FN), + PINMUX_DATA(AUDATA0_MARK, PS4_0_FN1, PTS0_FN), + PINMUX_DATA(PWX4_MARK, PS4_0_FN2, PTS0_FN), + + /* PTU FN */ + PINMUX_DATA(CS6_MARK, PTU7_FN), + PINMUX_DATA(CS5_MARK, PTU6_FN), + PINMUX_DATA(CS4_MARK, PTU5_FN), + PINMUX_DATA(CS0_MARK, PTU4_FN), + PINMUX_DATA(RD_MARK, PTU3_FN), + PINMUX_DATA(WE0_MARK, PTU2_FN), + PINMUX_DATA(A25_MARK, PS5_9_FN1, PTU1_FN), + PINMUX_DATA(DREQ0_MARK, PS5_9_FN2, PTU1_FN), + PINMUX_DATA(A24_MARK, PS5_8_FN1, PTU0_FN), + PINMUX_DATA(DACK0_MARK, PS5_8_FN2, PTU0_FN), + + /* PTV FN */ + PINMUX_DATA(A23_MARK, PS5_7_FN1, PTV7_FN), + PINMUX_DATA(TEND0_MARK, PS5_7_FN2, PTV7_FN), + PINMUX_DATA(A22_MARK, PS5_6_FN1, PTV6_FN), + PINMUX_DATA(DREQ1_MARK, PS5_6_FN2, PTV6_FN), + PINMUX_DATA(A21_MARK, PS5_5_FN1, PTV5_FN), + PINMUX_DATA(DACK1_MARK, PS5_5_FN2, PTV5_FN), + PINMUX_DATA(A20_MARK, PS5_4_FN1, PTV4_FN), + PINMUX_DATA(TEND1_MARK, PS5_4_FN2, PTV4_FN), + PINMUX_DATA(A19_MARK, PTV3_FN), + PINMUX_DATA(A18_MARK, PTV2_FN), + PINMUX_DATA(A17_MARK, PTV1_FN), + PINMUX_DATA(A16_MARK, PTV0_FN), + + /* PTW FN */ + PINMUX_DATA(A15_MARK, PTW7_FN), + PINMUX_DATA(A14_MARK, PTW6_FN), + PINMUX_DATA(A13_MARK, PTW5_FN), + PINMUX_DATA(A12_MARK, PTW4_FN), + PINMUX_DATA(A11_MARK, PTW3_FN), + PINMUX_DATA(A10_MARK, PTW2_FN), + PINMUX_DATA(A9_MARK, PTW1_FN), + PINMUX_DATA(A8_MARK, PTW0_FN), + + /* PTX FN */ + PINMUX_DATA(A7_MARK, PTX7_FN), + PINMUX_DATA(A6_MARK, PTX6_FN), + PINMUX_DATA(A5_MARK, PTX5_FN), + PINMUX_DATA(A4_MARK, PTX4_FN), + PINMUX_DATA(A3_MARK, PTX3_FN), + PINMUX_DATA(A2_MARK, PTX2_FN), + PINMUX_DATA(A1_MARK, PTX1_FN), + PINMUX_DATA(A0_MARK, PTX0_FN), + + /* PTY FN */ + PINMUX_DATA(D7_MARK, PTY7_FN), + PINMUX_DATA(D6_MARK, PTY6_FN), + PINMUX_DATA(D5_MARK, PTY5_FN), + PINMUX_DATA(D4_MARK, PTY4_FN), + PINMUX_DATA(D3_MARK, PTY3_FN), + PINMUX_DATA(D2_MARK, PTY2_FN), + PINMUX_DATA(D1_MARK, PTY1_FN), + PINMUX_DATA(D0_MARK, PTY0_FN), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + /* PTA */ + PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), + PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), + PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), + PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), + PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), + PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), + PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), + PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), + + /* PTB */ + PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), + PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), + PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), + PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), + PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), + PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), + PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), + PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), + + /* PTC */ + PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), + PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), + PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), + PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), + PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), + PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), + PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), + PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), + + /* PTD */ + PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), + PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), + PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), + PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), + PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), + PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), + PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), + PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), + + /* PTE */ + PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), + PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), + PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), + PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), + PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), + PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), + PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), + PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), + + /* PTF */ + PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), + PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), + PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), + PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), + PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), + PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), + PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), + PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), + + /* PTG */ + PINMUX_GPIO(GPIO_PTG7, PTG7_DATA), + PINMUX_GPIO(GPIO_PTG6, PTG6_DATA), + PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), + PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), + PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), + PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), + PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), + PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), + + /* PTH */ + PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), + PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), + PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), + PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), + PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), + PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), + PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), + PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), + + /* PTI */ + PINMUX_GPIO(GPIO_PTI7, PTI7_DATA), + PINMUX_GPIO(GPIO_PTI6, PTI6_DATA), + PINMUX_GPIO(GPIO_PTI5, PTI5_DATA), + PINMUX_GPIO(GPIO_PTI4, PTI4_DATA), + PINMUX_GPIO(GPIO_PTI3, PTI3_DATA), + PINMUX_GPIO(GPIO_PTI2, PTI2_DATA), + PINMUX_GPIO(GPIO_PTI1, PTI1_DATA), + PINMUX_GPIO(GPIO_PTI0, PTI0_DATA), + + /* PTJ */ + PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), + PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), + PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), + PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), + PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), + PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), + PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), + PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), + + /* PTK */ + PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), + PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), + PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), + PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), + PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), + PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), + PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), + PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), + + /* PTL */ + PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), + PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), + PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), + PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), + PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), + PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), + PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), + PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), + + /* PTM */ + PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), + PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), + PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), + PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), + PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), + PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), + PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), + + /* PTN */ + PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), + PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), + PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), + PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), + PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), + PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), + PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), + PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), + + /* PTO */ + PINMUX_GPIO(GPIO_PTO7, PTO7_DATA), + PINMUX_GPIO(GPIO_PTO6, PTO6_DATA), + PINMUX_GPIO(GPIO_PTO5, PTO5_DATA), + PINMUX_GPIO(GPIO_PTO4, PTO4_DATA), + PINMUX_GPIO(GPIO_PTO3, PTO3_DATA), + PINMUX_GPIO(GPIO_PTO2, PTO2_DATA), + PINMUX_GPIO(GPIO_PTO1, PTO1_DATA), + PINMUX_GPIO(GPIO_PTO0, PTO0_DATA), + + /* PTP */ + PINMUX_GPIO(GPIO_PTP6, PTP6_DATA), + PINMUX_GPIO(GPIO_PTP5, PTP5_DATA), + PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), + PINMUX_GPIO(GPIO_PTP3, PTP3_DATA), + PINMUX_GPIO(GPIO_PTP2, PTP2_DATA), + PINMUX_GPIO(GPIO_PTP1, PTP1_DATA), + PINMUX_GPIO(GPIO_PTP0, PTP0_DATA), + + /* PTQ */ + PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), + PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), + PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), + PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), + PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), + PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), + PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), + + /* PTR */ + PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), + PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), + PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), + PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), + PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), + PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), + PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), + PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), + + /* PTS */ + PINMUX_GPIO(GPIO_PTS7, PTS7_DATA), + PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), + PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), + PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), + PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), + PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), + PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), + PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), + + /* PTT */ + PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), + PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), + PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), + PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), + PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), + PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), + + /* PTU */ + PINMUX_GPIO(GPIO_PTU7, PTU7_DATA), + PINMUX_GPIO(GPIO_PTU6, PTU6_DATA), + PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), + PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), + PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), + PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), + PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), + PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), + + /* PTV */ + PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), + PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), + PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), + PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), + PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), + PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), + PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), + PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), + + /* PTW */ + PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), + PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), + PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), + PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), + PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), + PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), + PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), + PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), + + /* PTX */ + PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), + PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), + PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), + PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), + PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), + PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), + PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), + PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), + + /* PTY */ + PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), + PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), + PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), + PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), + PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), + PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), + PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), + PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), + + /* PTZ */ + PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), + PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), + PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), + PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), + PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), + PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), + PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), + PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), + + /* PTA (mobule: LBSC, CPG, LPC) */ + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), + PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), + PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), + PINMUX_GPIO(GPIO_FN_MD10, MD10_MARK), + PINMUX_GPIO(GPIO_FN_MD9, MD9_MARK), + PINMUX_GPIO(GPIO_FN_MD8, MD8_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), + + /* PTB (mobule: LBSC, EtherC, SIM, LPC) */ + PINMUX_GPIO(GPIO_FN_D15, D15_MARK), + PINMUX_GPIO(GPIO_FN_D14, D14_MARK), + PINMUX_GPIO(GPIO_FN_D13, D13_MARK), + PINMUX_GPIO(GPIO_FN_D12, D12_MARK), + PINMUX_GPIO(GPIO_FN_D11, D11_MARK), + PINMUX_GPIO(GPIO_FN_D10, D10_MARK), + PINMUX_GPIO(GPIO_FN_D9, D9_MARK), + PINMUX_GPIO(GPIO_FN_D8, D8_MARK), + PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), + PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), + PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), + PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), + PINMUX_GPIO(GPIO_FN_WPSZ1, WPSZ1_MARK), + PINMUX_GPIO(GPIO_FN_WPSZ0, WPSZ0_MARK), + PINMUX_GPIO(GPIO_FN_FWID, FWID_MARK), + PINMUX_GPIO(GPIO_FN_FLSHSZ, FLSHSZ_MARK), + PINMUX_GPIO(GPIO_FN_LPC_SPIEN, LPC_SPIEN_MARK), + PINMUX_GPIO(GPIO_FN_BASEL, BASEL_MARK), + + /* PTC (mobule: SD) */ + PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), + PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), + PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), + PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), + PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), + PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), + PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), + + /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ + PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), + PINMUX_GPIO(GPIO_FN_MD6, MD6_MARK), + PINMUX_GPIO(GPIO_FN_MD5, MD5_MARK), + PINMUX_GPIO(GPIO_FN_MD3, MD3_MARK), + PINMUX_GPIO(GPIO_FN_MD2, MD2_MARK), + PINMUX_GPIO(GPIO_FN_MD1, MD1_MARK), + PINMUX_GPIO(GPIO_FN_MD0, MD0_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), + + /* PTE (mobule: EtherC) */ + PINMUX_GPIO(GPIO_FN_ET0_CRS_DV, ET0_CRS_DV_MARK), + PINMUX_GPIO(GPIO_FN_ET0_TXD1, ET0_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_ET0_TXD0, ET0_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_ET0_TX_EN, ET0_TX_EN_MARK), + PINMUX_GPIO(GPIO_FN_ET0_REF_CLK, ET0_REF_CLK_MARK), + PINMUX_GPIO(GPIO_FN_ET0_RXD1, ET0_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_ET0_RXD0, ET0_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_ET0_RX_ER, ET0_RX_ER_MARK), + + /* PTF (mobule: EtherC) */ + PINMUX_GPIO(GPIO_FN_ET1_CRS_DV, ET1_CRS_DV_MARK), + PINMUX_GPIO(GPIO_FN_ET1_TXD1, ET1_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_ET1_TXD0, ET1_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_ET1_TX_EN, ET1_TX_EN_MARK), + PINMUX_GPIO(GPIO_FN_ET1_REF_CLK, ET1_REF_CLK_MARK), + PINMUX_GPIO(GPIO_FN_ET1_RXD1, ET1_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_ET1_RXD0, ET1_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_ET1_RX_ER, ET1_RX_ER_MARK), + + /* PTG (mobule: SYSTEM, PWMX, LPC) */ + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + PINMUX_GPIO(GPIO_FN_PWX0, PWX0_MARK), + PINMUX_GPIO(GPIO_FN_PWX1, PWX1_MARK), + PINMUX_GPIO(GPIO_FN_PWX2, PWX2_MARK), + PINMUX_GPIO(GPIO_FN_PWX3, PWX3_MARK), + PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), + PINMUX_GPIO(GPIO_FN_CLKRUN, CLKRUN_MARK), + PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), + PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), + + /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ + PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), + PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), + PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), + PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), + PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), + PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), + PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), + PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), + + /* PTI (mobule: INTC) */ + PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), + PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), + PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), + PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), + PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), + PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), + PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), + PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), + + /* PTJ (mobule: SCIF234, SERMUX) */ + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), + PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), + + /* PTK (mobule: SERMUX) */ + PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), + PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), + PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), + PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK), + PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), + PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), + PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), + PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), + + /* PTL (mobule: SERMUX) */ + PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), + PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), + PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), + PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), + PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), + PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), + PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), + PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), + + /* PTM (mobule: IIC, LPC) */ + PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), + PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), + PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), + PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), + PINMUX_GPIO(GPIO_FN_WP, WP_MARK), + PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), + PINMUX_GPIO(GPIO_FN_FMS1, FMS1_MARK), + + /* PTN (mobule: SCIF234, EVC) */ + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), + PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), + PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), + PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), + PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), + PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), + PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), + PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), + PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), + PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), + PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), + PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), + PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), + PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), + + /* PTO (mobule: SGPIO) */ + PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), + + /* PTP (mobule: JMC, SCIF234) */ + PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), + PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), + PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), + PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), + PINMUX_GPIO(GPIO_FN_JMCRST, JMCRST_MARK), + PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + + /* PTQ (mobule: LPC) */ + PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), + PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK), + PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK), + PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK), + PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK), + PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK), + PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK), + + /* PTR (mobule: GRA, IIC) */ + PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK), + PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK), + PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK), + PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK), + PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), + PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), + PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), + PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), + PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + + /* PTS (mobule: GRA, IIC) */ + PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK), + PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK), + PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK), + PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK), + PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK), + PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK), + PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK), + PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK), + PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), + PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), + + /* PTT (mobule: SYSTEM, PWMX) */ + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + PINMUX_GPIO(GPIO_FN_PWX7, PWX7_MARK), + PINMUX_GPIO(GPIO_FN_PWX6, PWX6_MARK), + PINMUX_GPIO(GPIO_FN_PWX5, PWX5_MARK), + PINMUX_GPIO(GPIO_FN_PWX4, PWX4_MARK), + + /* PTU (mobule: LBSC, DMAC) */ + PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), + PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), + PINMUX_GPIO(GPIO_FN_RD, RD_MARK), + PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + + /* PTV (mobule: LBSC, DMAC) */ + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_A20, A20_MARK), + PINMUX_GPIO(GPIO_FN_A19, A19_MARK), + PINMUX_GPIO(GPIO_FN_A18, A18_MARK), + PINMUX_GPIO(GPIO_FN_A17, A17_MARK), + PINMUX_GPIO(GPIO_FN_A16, A16_MARK), + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + + /* PTW (mobule: LBSC) */ + PINMUX_GPIO(GPIO_FN_A16, A16_MARK), + PINMUX_GPIO(GPIO_FN_A15, A15_MARK), + PINMUX_GPIO(GPIO_FN_A14, A14_MARK), + PINMUX_GPIO(GPIO_FN_A13, A13_MARK), + PINMUX_GPIO(GPIO_FN_A12, A12_MARK), + PINMUX_GPIO(GPIO_FN_A11, A11_MARK), + PINMUX_GPIO(GPIO_FN_A10, A10_MARK), + PINMUX_GPIO(GPIO_FN_A9, A9_MARK), + PINMUX_GPIO(GPIO_FN_A8, A8_MARK), + + /* PTX (mobule: LBSC) */ + PINMUX_GPIO(GPIO_FN_A7, A7_MARK), + PINMUX_GPIO(GPIO_FN_A6, A6_MARK), + PINMUX_GPIO(GPIO_FN_A5, A5_MARK), + PINMUX_GPIO(GPIO_FN_A4, A4_MARK), + PINMUX_GPIO(GPIO_FN_A3, A3_MARK), + PINMUX_GPIO(GPIO_FN_A2, A2_MARK), + PINMUX_GPIO(GPIO_FN_A1, A1_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + + /* PTY (mobule: LBSC) */ + PINMUX_GPIO(GPIO_FN_D7, D7_MARK), + PINMUX_GPIO(GPIO_FN_D6, D6_MARK), + PINMUX_GPIO(GPIO_FN_D5, D5_MARK), + PINMUX_GPIO(GPIO_FN_D4, D4_MARK), + PINMUX_GPIO(GPIO_FN_D3, D3_MARK), + PINMUX_GPIO(GPIO_FN_D2, D2_MARK), + PINMUX_GPIO(GPIO_FN_D1, D1_MARK), + PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + }; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { + PTA7_FN, PTA7_OUT, PTA7_IN, 0, + PTA6_FN, PTA6_OUT, PTA6_IN, 0, + PTA5_FN, PTA5_OUT, PTA5_IN, 0, + PTA4_FN, PTA4_OUT, PTA4_IN, 0, + PTA3_FN, PTA3_OUT, PTA3_IN, 0, + PTA2_FN, PTA2_OUT, PTA2_IN, 0, + PTA1_FN, PTA1_OUT, PTA1_IN, 0, + PTA0_FN, PTA0_OUT, PTA0_IN, 0 } + }, + { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) { + PTB7_FN, PTB7_OUT, PTB7_IN, 0, + PTB6_FN, PTB6_OUT, PTB6_IN, 0, + PTB5_FN, PTB5_OUT, PTB5_IN, 0, + PTB4_FN, PTB4_OUT, PTB4_IN, 0, + PTB3_FN, PTB3_OUT, PTB3_IN, 0, + PTB2_FN, PTB2_OUT, PTB2_IN, 0, + PTB1_FN, PTB1_OUT, PTB1_IN, 0, + PTB0_FN, PTB0_OUT, PTB0_IN, 0 } + }, + { PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) { + PTC7_FN, PTC7_OUT, PTC7_IN, 0, + PTC6_FN, PTC6_OUT, PTC6_IN, 0, + PTC5_FN, PTC5_OUT, PTC5_IN, 0, + PTC4_FN, PTC4_OUT, PTC4_IN, 0, + PTC3_FN, PTC3_OUT, PTC3_IN, 0, + PTC2_FN, PTC2_OUT, PTC2_IN, 0, + PTC1_FN, PTC1_OUT, PTC1_IN, 0, + PTC0_FN, PTC0_OUT, PTC0_IN, 0 } + }, + { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) { + PTD7_FN, PTD7_OUT, PTD7_IN, 0, + PTD6_FN, PTD6_OUT, PTD6_IN, 0, + PTD5_FN, PTD5_OUT, PTD5_IN, 0, + PTD4_FN, PTD4_OUT, PTD4_IN, 0, + PTD3_FN, PTD3_OUT, PTD3_IN, 0, + PTD2_FN, PTD2_OUT, PTD2_IN, 0, + PTD1_FN, PTD1_OUT, PTD1_IN, 0, + PTD0_FN, PTD0_OUT, PTD0_IN, 0 } + }, + { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) { + PTE7_FN, PTE7_OUT, PTE7_IN, 0, + PTE6_FN, PTE6_OUT, PTE6_IN, 0, + PTE5_FN, PTE5_OUT, PTE5_IN, 0, + PTE4_FN, PTE4_OUT, PTE4_IN, 0, + PTE3_FN, PTE3_OUT, PTE3_IN, 0, + PTE2_FN, PTE2_OUT, PTE2_IN, 0, + PTE1_FN, PTE1_OUT, PTE1_IN, 0, + PTE0_FN, PTE0_OUT, PTE0_IN, 0 } + }, + { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) { + PTF7_FN, PTF7_OUT, PTF7_IN, 0, + PTF6_FN, PTF6_OUT, PTF6_IN, 0, + PTF5_FN, PTF5_OUT, PTF5_IN, 0, + PTF4_FN, PTF4_OUT, PTF4_IN, 0, + PTF3_FN, PTF3_OUT, PTF3_IN, 0, + PTF2_FN, PTF2_OUT, PTF2_IN, 0, + PTF1_FN, PTF1_OUT, PTF1_IN, 0, + PTF0_FN, PTF0_OUT, PTF0_IN, 0 } + }, + { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) { + PTG7_FN, PTG7_OUT, PTG7_IN, 0, + PTG6_FN, PTG6_OUT, PTG6_IN, 0, + PTG5_FN, PTG5_OUT, PTG5_IN, 0, + PTG4_FN, PTG4_OUT, PTG4_IN, 0, + PTG3_FN, PTG3_OUT, PTG3_IN, 0, + PTG2_FN, PTG2_OUT, PTG2_IN, 0, + PTG1_FN, PTG1_OUT, PTG1_IN, 0, + PTG0_FN, PTG0_OUT, PTG0_IN, 0 } + }, + { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) { + PTH7_FN, PTH7_OUT, PTH7_IN, 0, + PTH6_FN, PTH6_OUT, PTH6_IN, 0, + PTH5_FN, PTH5_OUT, PTH5_IN, 0, + PTH4_FN, PTH4_OUT, PTH4_IN, 0, + PTH3_FN, PTH3_OUT, PTH3_IN, 0, + PTH2_FN, PTH2_OUT, PTH2_IN, 0, + PTH1_FN, PTH1_OUT, PTH1_IN, 0, + PTH0_FN, PTH0_OUT, PTH0_IN, 0 } + }, + { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) { + PTI7_FN, PTI7_OUT, PTI7_IN, 0, + PTI6_FN, PTI6_OUT, PTI6_IN, 0, + PTI5_FN, PTI5_OUT, PTI5_IN, 0, + PTI4_FN, PTI4_OUT, PTI4_IN, 0, + PTI3_FN, PTI3_OUT, PTI3_IN, 0, + PTI2_FN, PTI2_OUT, PTI2_IN, 0, + PTI1_FN, PTI1_OUT, PTI1_IN, 0, + PTI0_FN, PTI0_OUT, PTI0_IN, 0 } + }, + { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) { + PTJ7_FN, PTJ7_OUT, PTJ7_IN, 0, + PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0, + PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0, + PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0, + PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0, + PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0, + PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0, + PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 } + }, + { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) { + PTK7_FN, PTK7_OUT, PTK7_IN, 0, + PTK6_FN, PTK6_OUT, PTK6_IN, 0, + PTK5_FN, PTK5_OUT, PTK5_IN, 0, + PTK4_FN, PTK4_OUT, PTK4_IN, 0, + PTK3_FN, PTK3_OUT, PTK3_IN, 0, + PTK2_FN, PTK2_OUT, PTK2_IN, 0, + PTK1_FN, PTK1_OUT, PTK1_IN, 0, + PTK0_FN, PTK0_OUT, PTK0_IN, 0 } + }, + { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) { + PTL7_FN, PTL7_OUT, PTL7_IN, 0, + PTL6_FN, PTL6_OUT, PTL6_IN, 0, + PTL5_FN, PTL5_OUT, PTL5_IN, 0, + PTL4_FN, PTL4_OUT, PTL4_IN, 0, + PTL3_FN, PTL3_OUT, PTL3_IN, 0, + PTL2_FN, PTL2_OUT, PTL2_IN, 0, + PTL1_FN, PTL1_OUT, PTL1_IN, 0, + PTL0_FN, PTL0_OUT, PTL0_IN, 0 } + }, + { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) { + 0, 0, 0, 0, /* reserved: always set 1 */ + PTM6_FN, PTM6_OUT, PTM6_IN, 0, + PTM5_FN, PTM5_OUT, PTM5_IN, 0, + PTM4_FN, PTM4_OUT, PTM4_IN, 0, + PTM3_FN, PTM3_OUT, PTM3_IN, 0, + PTM2_FN, PTM2_OUT, PTM2_IN, 0, + PTM1_FN, PTM1_OUT, PTM1_IN, 0, + PTM0_FN, PTM0_OUT, PTM0_IN, 0 } + }, + { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) { + PTN7_FN, PTN7_OUT, PTN7_IN, 0, + PTN6_FN, PTN6_OUT, PTN6_IN, 0, + PTN5_FN, PTN5_OUT, PTN5_IN, 0, + PTN4_FN, PTN4_OUT, PTN4_IN, 0, + PTN3_FN, PTN3_OUT, PTN3_IN, 0, + PTN2_FN, PTN2_OUT, PTN2_IN, 0, + PTN1_FN, PTN1_OUT, PTN1_IN, 0, + PTN0_FN, PTN0_OUT, PTN0_IN, 0 } + }, + { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) { + PTO7_FN, PTO7_OUT, PTO7_IN, 0, + PTO6_FN, PTO6_OUT, PTO6_IN, 0, + PTO5_FN, PTO5_OUT, PTO5_IN, 0, + PTO4_FN, PTO4_OUT, PTO4_IN, 0, + PTO3_FN, PTO3_OUT, PTO3_IN, 0, + PTO2_FN, PTO2_OUT, PTO2_IN, 0, + PTO1_FN, PTO1_OUT, PTO1_IN, 0, + PTO0_FN, PTO0_OUT, PTO0_IN, 0 } + }, + { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) { + 0, 0, 0, 0, /* reserved: always set 1 */ + PTP6_FN, PTP6_OUT, PTP6_IN, 0, + PTP5_FN, PTP5_OUT, PTP5_IN, 0, + PTP4_FN, PTP4_OUT, PTP4_IN, 0, + PTP3_FN, PTP3_OUT, PTP3_IN, 0, + PTP2_FN, PTP2_OUT, PTP2_IN, 0, + PTP1_FN, PTP1_OUT, PTP1_IN, 0, + PTP0_FN, PTP0_OUT, PTP0_IN, 0 } + }, + { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) { + 0, 0, 0, 0, /* reserved: always set 1 */ + PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0, + PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0, + PTQ4_FN, PTQ4_OUT, PTQ4_IN, 0, + PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0, + PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0, + PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0, + PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 } + }, + { PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2) { + PTR7_FN, PTR7_OUT, PTR7_IN, 0, + PTR6_FN, PTR6_OUT, PTR6_IN, 0, + PTR5_FN, PTR5_OUT, PTR5_IN, 0, + PTR4_FN, PTR4_OUT, PTR4_IN, 0, + PTR3_FN, PTR3_OUT, PTR3_IN, 0, + PTR2_FN, PTR2_OUT, PTR2_IN, 0, + PTR1_FN, PTR1_OUT, PTR1_IN, 0, + PTR0_FN, PTR0_OUT, PTR0_IN, 0 } + }, + { PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2) { + PTS7_FN, PTS7_OUT, PTS7_IN, 0, + PTS6_FN, PTS6_OUT, PTS6_IN, 0, + PTS5_FN, PTS5_OUT, PTS5_IN, 0, + PTS4_FN, PTS4_OUT, PTS4_IN, 0, + PTS3_FN, PTS3_OUT, PTS3_IN, 0, + PTS2_FN, PTS2_OUT, PTS2_IN, 0, + PTS1_FN, PTS1_OUT, PTS1_IN, 0, + PTS0_FN, PTS0_OUT, PTS0_IN, 0 } + }, + { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) { + 0, 0, 0, 0, /* reserved: always set 1 */ + 0, 0, 0, 0, /* reserved: always set 1 */ + PTT5_FN, PTT5_OUT, PTT5_IN, 0, + PTT4_FN, PTT4_OUT, PTT4_IN, 0, + PTT3_FN, PTT3_OUT, PTT3_IN, 0, + PTT2_FN, PTT2_OUT, PTT2_IN, 0, + PTT1_FN, PTT1_OUT, PTT1_IN, 0, + PTT0_FN, PTT0_OUT, PTT0_IN, 0 } + }, + { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) { + PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU, + PTU6_FN, PTU6_OUT, PTU6_IN, PTU6_IN_PU, + PTU5_FN, PTU5_OUT, PTU5_IN, PTU5_IN_PU, + PTU4_FN, PTU4_OUT, PTU4_IN, PTU4_IN_PU, + PTU3_FN, PTU3_OUT, PTU3_IN, PTU3_IN_PU, + PTU2_FN, PTU2_OUT, PTU2_IN, PTU2_IN_PU, + PTU1_FN, PTU1_OUT, PTU1_IN, PTU1_IN_PU, + PTU0_FN, PTU0_OUT, PTU0_IN, PTU0_IN_PU } + }, + { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) { + PTV7_FN, PTV7_OUT, PTV7_IN, PTV7_IN_PU, + PTV6_FN, PTV6_OUT, PTV6_IN, PTV6_IN_PU, + PTV5_FN, PTV5_OUT, PTV5_IN, PTV5_IN_PU, + PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU, + PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU, + PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU, + PTV1_FN, PTV1_OUT, PTV1_IN, PTV1_IN_PU, + PTV0_FN, PTV0_OUT, PTV0_IN, PTV0_IN_PU } + }, + { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) { + PTW7_FN, PTW7_OUT, PTW7_IN, PTW7_IN_PU, + PTW6_FN, PTW6_OUT, PTW6_IN, PTW6_IN_PU, + PTW5_FN, PTW5_OUT, PTW5_IN, PTW5_IN_PU, + PTW4_FN, PTW4_OUT, PTW4_IN, PTW4_IN_PU, + PTW3_FN, PTW3_OUT, PTW3_IN, PTW3_IN_PU, + PTW2_FN, PTW2_OUT, PTW2_IN, PTW2_IN_PU, + PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU, + PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU } + }, + { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) { + PTX7_FN, PTX7_OUT, PTX7_IN, PTX7_IN_PU, + PTX6_FN, PTX6_OUT, PTX6_IN, PTX6_IN_PU, + PTX5_FN, PTX5_OUT, PTX5_IN, PTX5_IN_PU, + PTX4_FN, PTX4_OUT, PTX4_IN, PTX4_IN_PU, + PTX3_FN, PTX3_OUT, PTX3_IN, PTX3_IN_PU, + PTX2_FN, PTX2_OUT, PTX2_IN, PTX2_IN_PU, + PTX1_FN, PTX1_OUT, PTX1_IN, PTX1_IN_PU, + PTX0_FN, PTX0_OUT, PTX0_IN, PTX0_IN_PU } + }, + { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) { + PTY7_FN, PTY7_OUT, PTY7_IN, PTY7_IN_PU, + PTY6_FN, PTY6_OUT, PTY6_IN, PTY6_IN_PU, + PTY5_FN, PTY5_OUT, PTY5_IN, PTY5_IN_PU, + PTY4_FN, PTY4_OUT, PTY4_IN, PTY4_IN_PU, + PTY3_FN, PTY3_OUT, PTY3_IN, PTY3_IN_PU, + PTY2_FN, PTY2_OUT, PTY2_IN, PTY2_IN_PU, + PTY1_FN, PTY1_OUT, PTY1_IN, PTY1_IN_PU, + PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU } + }, + { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) { + 0, PTZ7_OUT, PTZ7_IN, 0, + 0, PTZ6_OUT, PTZ6_IN, 0, + 0, PTZ5_OUT, PTZ5_IN, 0, + 0, PTZ4_OUT, PTZ4_IN, 0, + 0, PTZ3_OUT, PTZ3_IN, 0, + 0, PTZ2_OUT, PTZ2_IN, 0, + 0, PTZ1_OUT, PTZ1_IN, 0, + 0, PTZ0_OUT, PTZ0_IN, 0 } + }, + + { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) { + PS0_15_FN3, PS0_15_FN1, + PS0_14_FN3, PS0_14_FN1, + PS0_13_FN3, PS0_13_FN1, + PS0_12_FN3, PS0_12_FN1, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PS0_7_FN2, PS0_7_FN1, + PS0_6_FN2, PS0_6_FN1, + PS0_5_FN2, PS0_5_FN1, + PS0_4_FN2, PS0_4_FN1, + PS0_3_FN2, PS0_3_FN1, + PS0_2_FN2, PS0_2_FN1, + PS0_1_FN2, PS0_1_FN1, + 0, 0, } + }, + { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PS1_7_FN1, PS1_7_FN3, + PS1_6_FN1, PS1_6_FN3, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, } + }, + { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) { + 0, 0, + 0, 0, + PS2_13_FN3, PS2_13_FN1, + PS2_12_FN3, PS2_12_FN1, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PS2_1_FN1, PS2_1_FN2, + PS2_0_FN1, PS2_0_FN2, } + }, + { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) { + PS4_15_FN2, PS4_15_FN1, + PS4_14_FN2, PS4_14_FN1, + PS4_13_FN2, PS4_13_FN1, + PS4_12_FN2, PS4_12_FN1, + PS4_11_FN2, PS4_11_FN1, + PS4_10_FN2, PS4_10_FN1, + PS4_9_FN2, PS4_9_FN1, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PS4_3_FN2, PS4_3_FN1, + PS4_2_FN2, PS4_2_FN1, + PS4_1_FN2, PS4_1_FN1, + PS4_0_FN2, PS4_0_FN1, } + }, + { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PS5_9_FN1, PS5_9_FN2, + PS5_8_FN1, PS5_8_FN2, + PS5_7_FN1, PS5_7_FN2, + PS5_6_FN1, PS5_6_FN2, + PS5_5_FN1, PS5_5_FN2, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, } + }, + { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PS6_7_FN_AN, PS6_7_FN_EV, + PS6_6_FN_AN, PS6_6_FN_EV, + PS6_5_FN_AN, PS6_5_FN_EV, + PS6_4_FN_AN, PS6_4_FN_EV, + PS6_3_FN_AN, PS6_3_FN_EV, + PS6_2_FN_AN, PS6_2_FN_EV, + PS6_1_FN_AN, PS6_1_FN_EV, + PS6_0_FN_AN, PS6_0_FN_EV, } + }, + {} +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PADR", 0xffec0034, 8) { + PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, + PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } + }, + { PINMUX_DATA_REG("PBDR", 0xffec0036, 8) { + PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, + PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } + }, + { PINMUX_DATA_REG("PCDR", 0xffec0038, 8) { + PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, + PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA } + }, + { PINMUX_DATA_REG("PDDR", 0xffec003a, 8) { + PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, + PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } + }, + { PINMUX_DATA_REG("PEDR", 0xffec003c, 8) { + PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, + PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA } + }, + { PINMUX_DATA_REG("PFDR", 0xffec003e, 8) { + PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, + PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } + }, + { PINMUX_DATA_REG("PGDR", 0xffec0040, 8) { + PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA, + PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } + }, + { PINMUX_DATA_REG("PHDR", 0xffec0042, 8) { + PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, + PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } + }, + { PINMUX_DATA_REG("PIDR", 0xffec0044, 8) { + PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA, + PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA } + }, + { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) { + PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, + PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } + }, + { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) { + PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, + PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } + }, + { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) { + PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } + }, + { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) { + 0, PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } + }, + { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) { + PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } + }, + { PINMUX_DATA_REG("PODR", 0xffec0050, 8) { + PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA, + PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA } + }, + { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) { + 0, PTP6_DATA, PTP5_DATA, PTP4_DATA, + PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA } + }, + { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) { + 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, + PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } + }, + { PINMUX_DATA_REG("PRDR", 0xffec0056, 8) { + PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, + PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } + }, + { PINMUX_DATA_REG("PSDR", 0xffec0058, 8) { + PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, + PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } + }, + { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) { + 0, 0, PTT5_DATA, PTT4_DATA, + PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } + }, + { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) { + PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, + PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } + }, + { PINMUX_DATA_REG("PVDR", 0xffec005e, 8) { + PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, + PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } + }, + { PINMUX_DATA_REG("PWDR", 0xffec0060, 8) { + PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, + PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } + }, + { PINMUX_DATA_REG("PXDR", 0xffec0062, 8) { + PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, + PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } + }, + { PINMUX_DATA_REG("PYDR", 0xffec0064, 8) { + PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, + PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } + }, + { PINMUX_DATA_REG("PZDR", 0xffec0066, 8) { + PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, + PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } + }, + { }, +}; + +static struct pinmux_info sh7757_pinmux_info = { + .name = "sh7757_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PTA7, + .last_gpio = GPIO_FN_D0, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +static int __init plat_pinmux_setup(void) +{ + return register_pinmux(&sh7757_pinmux_info); +} + +arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 1a956b1beccc..4a9010bf4fd3 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c @@ -40,7 +40,7 @@ static struct platform_device iic_device = { }; static struct r8a66597_platdata r8a66597_data = { - /* This set zero to all members */ + .on_chip = 1, }; static struct resource usb_host_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index cda76ebf87c3..35097753456c 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -13,9 +13,11 @@ #include <linux/serial_sci.h> #include <linux/mm.h> #include <linux/uio_driver.h> +#include <linux/usb/m66592.h> #include <linux/sh_timer.h> #include <asm/clock.h> #include <asm/mmzone.h> +#include <cpu/sh7722.h> static struct resource rtc_resources[] = { [0] = { @@ -45,11 +47,18 @@ static struct platform_device rtc_device = { .id = -1, .num_resources = ARRAY_SIZE(rtc_resources), .resource = rtc_resources, + .archdata = { + .hwblk_id = HWBLK_RTC, + }, +}; + +static struct m66592_platdata usbf_platdata = { + .on_chip = 1, }; static struct resource usbf_resources[] = { [0] = { - .name = "m66592_udc", + .name = "USBF", .start = 0x04480000, .end = 0x044800FF, .flags = IORESOURCE_MEM, @@ -67,9 +76,13 @@ static struct platform_device usbf_device = { .dev = { .dma_mask = NULL, .coherent_dma_mask = 0xffffffff, + .platform_data = &usbf_platdata, }, .num_resources = ARRAY_SIZE(usbf_resources), .resource = usbf_resources, + .archdata = { + .hwblk_id = HWBLK_USBF, + }, }; static struct resource iic_resources[] = { @@ -91,6 +104,9 @@ static struct platform_device iic_device = { .id = 0, /* "i2c0" clock */ .num_resources = ARRAY_SIZE(iic_resources), .resource = iic_resources, + .archdata = { + .hwblk_id = HWBLK_IIC, + }, }; static struct uio_info vpu_platform_data = { @@ -119,6 +135,9 @@ static struct platform_device vpu_device = { }, .resource = vpu_resources, .num_resources = ARRAY_SIZE(vpu_resources), + .archdata = { + .hwblk_id = HWBLK_VPU, + }, }; static struct uio_info veu_platform_data = { @@ -147,6 +166,9 @@ static struct platform_device veu_device = { }, .resource = veu_resources, .num_resources = ARRAY_SIZE(veu_resources), + .archdata = { + .hwblk_id = HWBLK_VEU, + }, }; static struct uio_info jpu_platform_data = { @@ -175,6 +197,9 @@ static struct platform_device jpu_device = { }, .resource = jpu_resources, .num_resources = ARRAY_SIZE(jpu_resources), + .archdata = { + .hwblk_id = HWBLK_JPU, + }, }; static struct sh_timer_config cmt_platform_data = { @@ -207,6 +232,9 @@ static struct platform_device cmt_device = { }, .resource = cmt_resources, .num_resources = ARRAY_SIZE(cmt_resources), + .archdata = { + .hwblk_id = HWBLK_CMT, + }, }; static struct sh_timer_config tmu0_platform_data = { @@ -238,6 +266,9 @@ static struct platform_device tmu0_device = { }, .resource = tmu0_resources, .num_resources = ARRAY_SIZE(tmu0_resources), + .archdata = { + .hwblk_id = HWBLK_TMU, + }, }; static struct sh_timer_config tmu1_platform_data = { @@ -269,6 +300,9 @@ static struct platform_device tmu1_device = { }, .resource = tmu1_resources, .num_resources = ARRAY_SIZE(tmu1_resources), + .archdata = { + .hwblk_id = HWBLK_TMU, + }, }; static struct sh_timer_config tmu2_platform_data = { @@ -299,6 +333,9 @@ static struct platform_device tmu2_device = { }, .resource = tmu2_resources, .num_resources = ARRAY_SIZE(tmu2_resources), + .archdata = { + .hwblk_id = HWBLK_TMU, + }, }; static struct plat_sci_port sci_platform_data[] = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index b45dace9539f..4caa5a7ca86e 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -18,6 +18,7 @@ #include <linux/io.h> #include <asm/clock.h> #include <asm/mmzone.h> +#include <cpu/sh7723.h> static struct uio_info vpu_platform_data = { .name = "VPU5", @@ -45,6 +46,9 @@ static struct platform_device vpu_device = { }, .resource = vpu_resources, .num_resources = ARRAY_SIZE(vpu_resources), + .archdata = { + .hwblk_id = HWBLK_VPU, + }, }; static struct uio_info veu0_platform_data = { @@ -73,6 +77,9 @@ static struct platform_device veu0_device = { }, .resource = veu0_resources, .num_resources = ARRAY_SIZE(veu0_resources), + .archdata = { + .hwblk_id = HWBLK_VEU2H0, + }, }; static struct uio_info veu1_platform_data = { @@ -101,6 +108,9 @@ static struct platform_device veu1_device = { }, .resource = veu1_resources, .num_resources = ARRAY_SIZE(veu1_resources), + .archdata = { + .hwblk_id = HWBLK_VEU2H1, + }, }; static struct sh_timer_config cmt_platform_data = { @@ -133,6 +143,9 @@ static struct platform_device cmt_device = { }, .resource = cmt_resources, .num_resources = ARRAY_SIZE(cmt_resources), + .archdata = { + .hwblk_id = HWBLK_CMT, + }, }; static struct sh_timer_config tmu0_platform_data = { @@ -164,6 +177,9 @@ static struct platform_device tmu0_device = { }, .resource = tmu0_resources, .num_resources = ARRAY_SIZE(tmu0_resources), + .archdata = { + .hwblk_id = HWBLK_TMU0, + }, }; static struct sh_timer_config tmu1_platform_data = { @@ -195,6 +211,9 @@ static struct platform_device tmu1_device = { }, .resource = tmu1_resources, .num_resources = ARRAY_SIZE(tmu1_resources), + .archdata = { + .hwblk_id = HWBLK_TMU0, + }, }; static struct sh_timer_config tmu2_platform_data = { @@ -225,6 +244,9 @@ static struct platform_device tmu2_device = { }, .resource = tmu2_resources, .num_resources = ARRAY_SIZE(tmu2_resources), + .archdata = { + .hwblk_id = HWBLK_TMU0, + }, }; static struct sh_timer_config tmu3_platform_data = { @@ -255,6 +277,9 @@ static struct platform_device tmu3_device = { }, .resource = tmu3_resources, .num_resources = ARRAY_SIZE(tmu3_resources), + .archdata = { + .hwblk_id = HWBLK_TMU1, + }, }; static struct sh_timer_config tmu4_platform_data = { @@ -285,6 +310,9 @@ static struct platform_device tmu4_device = { }, .resource = tmu4_resources, .num_resources = ARRAY_SIZE(tmu4_resources), + .archdata = { + .hwblk_id = HWBLK_TMU1, + }, }; static struct sh_timer_config tmu5_platform_data = { @@ -315,6 +343,9 @@ static struct platform_device tmu5_device = { }, .resource = tmu5_resources, .num_resources = ARRAY_SIZE(tmu5_resources), + .archdata = { + .hwblk_id = HWBLK_TMU1, + }, }; static struct plat_sci_port sci_platform_data[] = { @@ -395,10 +426,13 @@ static struct platform_device rtc_device = { .id = -1, .num_resources = ARRAY_SIZE(rtc_resources), .resource = rtc_resources, + .archdata = { + .hwblk_id = HWBLK_RTC, + }, }; static struct r8a66597_platdata r8a66597_data = { - /* This set zero to all members */ + .on_chip = 1, }; static struct resource sh7723_usb_host_resources[] = { @@ -424,6 +458,9 @@ static struct platform_device sh7723_usb_host_device = { }, .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), .resource = sh7723_usb_host_resources, + .archdata = { + .hwblk_id = HWBLK_USB, + }, }; static struct resource iic_resources[] = { @@ -445,6 +482,9 @@ static struct platform_device iic_device = { .id = 0, /* "i2c0" clock */ .num_resources = ARRAY_SIZE(iic_resources), .resource = iic_resources, + .archdata = { + .hwblk_id = HWBLK_IIC, + }, }; static struct platform_device *sh7723_devices[] __initdata = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index a04edaab9a29..f3851fd757ec 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <asm/clock.h> #include <asm/mmzone.h> +#include <cpu/sh7724.h> /* Serial */ static struct plat_sci_port sci_platform_data[] = { @@ -103,6 +104,9 @@ static struct platform_device rtc_device = { .id = -1, .num_resources = ARRAY_SIZE(rtc_resources), .resource = rtc_resources, + .archdata = { + .hwblk_id = HWBLK_RTC, + }, }; /* I2C0 */ @@ -125,6 +129,9 @@ static struct platform_device iic0_device = { .id = 0, /* "i2c0" clock */ .num_resources = ARRAY_SIZE(iic0_resources), .resource = iic0_resources, + .archdata = { + .hwblk_id = HWBLK_IIC0, + }, }; /* I2C1 */ @@ -147,6 +154,9 @@ static struct platform_device iic1_device = { .id = 1, /* "i2c1" clock */ .num_resources = ARRAY_SIZE(iic1_resources), .resource = iic1_resources, + .archdata = { + .hwblk_id = HWBLK_IIC1, + }, }; /* VPU */ @@ -176,6 +186,9 @@ static struct platform_device vpu_device = { }, .resource = vpu_resources, .num_resources = ARRAY_SIZE(vpu_resources), + .archdata = { + .hwblk_id = HWBLK_VPU, + }, }; /* VEU0 */ @@ -205,6 +218,9 @@ static struct platform_device veu0_device = { }, .resource = veu0_resources, .num_resources = ARRAY_SIZE(veu0_resources), + .archdata = { + .hwblk_id = HWBLK_VEU0, + }, }; /* VEU1 */ @@ -234,6 +250,9 @@ static struct platform_device veu1_device = { }, .resource = veu1_resources, .num_resources = ARRAY_SIZE(veu1_resources), + .archdata = { + .hwblk_id = HWBLK_VEU1, + }, }; static struct sh_timer_config cmt_platform_data = { @@ -266,6 +285,9 @@ static struct platform_device cmt_device = { }, .resource = cmt_resources, .num_resources = ARRAY_SIZE(cmt_resources), + .archdata = { + .hwblk_id = HWBLK_CMT, + }, }; static struct sh_timer_config tmu0_platform_data = { @@ -297,6 +319,9 @@ static struct platform_device tmu0_device = { }, .resource = tmu0_resources, .num_resources = ARRAY_SIZE(tmu0_resources), + .archdata = { + .hwblk_id = HWBLK_TMU0, + }, }; static struct sh_timer_config tmu1_platform_data = { @@ -328,6 +353,9 @@ static struct platform_device tmu1_device = { }, .resource = tmu1_resources, .num_resources = ARRAY_SIZE(tmu1_resources), + .archdata = { + .hwblk_id = HWBLK_TMU0, + }, }; static struct sh_timer_config tmu2_platform_data = { @@ -358,6 +386,9 @@ static struct platform_device tmu2_device = { }, .resource = tmu2_resources, .num_resources = ARRAY_SIZE(tmu2_resources), + .archdata = { + .hwblk_id = HWBLK_TMU0, + }, }; @@ -389,6 +420,9 @@ static struct platform_device tmu3_device = { }, .resource = tmu3_resources, .num_resources = ARRAY_SIZE(tmu3_resources), + .archdata = { + .hwblk_id = HWBLK_TMU1, + }, }; static struct sh_timer_config tmu4_platform_data = { @@ -419,6 +453,9 @@ static struct platform_device tmu4_device = { }, .resource = tmu4_resources, .num_resources = ARRAY_SIZE(tmu4_resources), + .archdata = { + .hwblk_id = HWBLK_TMU1, + }, }; static struct sh_timer_config tmu5_platform_data = { @@ -449,6 +486,9 @@ static struct platform_device tmu5_device = { }, .resource = tmu5_resources, .num_resources = ARRAY_SIZE(tmu5_resources), + .archdata = { + .hwblk_id = HWBLK_TMU1, + }, }; /* JPU */ @@ -478,6 +518,9 @@ static struct platform_device jpu_device = { }, .resource = jpu_resources, .num_resources = ARRAY_SIZE(jpu_resources), + .archdata = { + .hwblk_id = HWBLK_JPU, + }, }; static struct platform_device *sh7724_devices[] __initdata = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c new file mode 100644 index 000000000000..c470e15f2e03 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c @@ -0,0 +1,513 @@ +/* + * SH7757 Setup + * + * Copyright (C) 2009 Renesas Solutions Corp. + * + * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial.h> +#include <linux/serial_sci.h> +#include <linux/io.h> +#include <linux/mm.h> +#include <linux/sh_timer.h> + +static struct sh_timer_config tmu0_platform_data = { + .name = "TMU0", + .channel_offset = 0x04, + .timer_bit = 0, + .clk = "peripheral_clk", + .clockevent_rating = 200, +}; + +static struct resource tmu0_resources[] = { + [0] = { + .name = "TMU0", + .start = 0xfe430008, + .end = 0xfe430013, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 28, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu0_device = { + .name = "sh_tmu", + .id = 0, + .dev = { + .platform_data = &tmu0_platform_data, + }, + .resource = tmu0_resources, + .num_resources = ARRAY_SIZE(tmu0_resources), +}; + +static struct sh_timer_config tmu1_platform_data = { + .name = "TMU1", + .channel_offset = 0x10, + .timer_bit = 1, + .clk = "peripheral_clk", + .clocksource_rating = 200, +}; + +static struct resource tmu1_resources[] = { + [0] = { + .name = "TMU1", + .start = 0xfe430014, + .end = 0xfe43001f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 29, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu1_device = { + .name = "sh_tmu", + .id = 1, + .dev = { + .platform_data = &tmu1_platform_data, + }, + .resource = tmu1_resources, + .num_resources = ARRAY_SIZE(tmu1_resources), +}; + +static struct plat_sci_port sci_platform_data[] = { + { + .mapbase = 0xfe4b0000, /* SCIF2 */ + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 40, 40, 40, 40 }, + }, { + .mapbase = 0xfe4c0000, /* SCIF3 */ + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 76, 76, 76, 76 }, + }, { + .mapbase = 0xfe4d0000, /* SCIF4 */ + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 104, 104, 104, 104 }, + }, { + .flags = 0, + } +}; + +static struct platform_device sci_device = { + .name = "sh-sci", + .id = -1, + .dev = { + .platform_data = sci_platform_data, + }, +}; + +static struct platform_device *sh7757_devices[] __initdata = { + &tmu0_device, + &tmu1_device, + &sci_device, +}; + +static int __init sh7757_devices_setup(void) +{ + return platform_add_devices(sh7757_devices, + ARRAY_SIZE(sh7757_devices)); +} +arch_initcall(sh7757_devices_setup); + +enum { + UNUSED = 0, + + /* interrupt sources */ + + IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, + IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, + IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, + IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, + + IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, + IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, + IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, + IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, + + SDHI, + DVC, + IRQ8, IRQ9, IRQ10, + WDT0, + TMU0, TMU1, TMU2, TMU2_TICPI, + HUDI, + + ARC4, + DMAC0, + IRQ11, + SCIF2, + DMAC1_6, + USB0, + IRQ12, + JMC, + SPI1, + IRQ13, IRQ14, + USB1, + TMR01, TMR23, TMR45, + WDT1, + FRT, + LPC, + SCIF0, SCIF1, SCIF3, + PECI0I, PECI1I, PECI2I, + IRQ15, + ETHERC, + SPI0, + ADC1, + DMAC1_8, + SIM, + TMU3, TMU4, TMU5, + ADC0, + SCIF4, + IIC0_0, IIC0_1, IIC0_2, IIC0_3, + IIC1_0, IIC1_1, IIC1_2, IIC1_3, + IIC2_0, IIC2_1, IIC2_2, IIC2_3, + IIC3_0, IIC3_1, IIC3_2, IIC3_3, + IIC4_0, IIC4_1, IIC4_2, IIC4_3, + IIC5_0, IIC5_1, IIC5_2, IIC5_3, + IIC6_0, IIC6_1, IIC6_2, IIC6_3, + IIC7_0, IIC7_1, IIC7_2, IIC7_3, + IIC8_0, IIC8_1, IIC8_2, IIC8_3, + IIC9_0, IIC9_1, IIC9_2, IIC9_3, + PCIINTA, + PCIE, + SGPIO, + + /* interrupt groups */ + + TMU012, TMU345, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0), + INTC_VECT(SDHI, 0x4c0), + INTC_VECT(DVC, 0x4e0), + INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), + INTC_VECT(IRQ10, 0x540), + INTC_VECT(WDT0, 0x560), + INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), + INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), + INTC_VECT(HUDI, 0x600), + INTC_VECT(ARC4, 0x620), + INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), + INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), + INTC_VECT(DMAC0, 0x6c0), + INTC_VECT(IRQ11, 0x6e0), + INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), + INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), + INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), + INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0), + INTC_VECT(USB0, 0x840), + INTC_VECT(IRQ12, 0x880), + INTC_VECT(JMC, 0x8a0), + INTC_VECT(SPI1, 0x8c0), + INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900), + INTC_VECT(USB1, 0x920), + INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), + INTC_VECT(TMR45, 0xa40), + INTC_VECT(WDT1, 0xa60), + INTC_VECT(FRT, 0xa80), + INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), + INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), + INTC_VECT(LPC, 0xb20), + INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), + INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), + INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), + INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20), + INTC_VECT(PECI2I, 0xc40), + INTC_VECT(IRQ15, 0xc60), + INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), + INTC_VECT(SPI0, 0xcc0), + INTC_VECT(ADC1, 0xce0), + INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20), + INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60), + INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), + INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), + INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), + INTC_VECT(TMU5, 0xe40), + INTC_VECT(ADC0, 0xe60), + INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20), + INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60), + INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420), + INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460), + INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0), + INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520), + INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560), + INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600), + INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640), + INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700), + INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800), + INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840), + INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), + INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), + INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), + INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980), + INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), + INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), + INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), + INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), + INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), + INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), + INTC_VECT(PCIINTA, 0x1ce0), + INTC_VECT(PCIE, 0x1e00), + INTC_VECT(SGPIO, 0x1f80), + INTC_VECT(SGPIO, 0x1fa0), +}; + +static struct intc_group groups[] __initdata = { + INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), + INTC_GROUP(TMU345, TMU3, TMU4, TMU5), +}; + +static struct intc_mask_reg mask_registers[] __initdata = { + { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, + + { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ + { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, + IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, + IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, + IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, + IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, + IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, + IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, + IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, + + { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45, + TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0, + HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012 + } }, + + { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ + { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, + IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, + ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I, + ARC4, 0, SPI1, JMC, 0, 0, 0, DVC + } }, + + { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ + { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0, + 0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, + IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, + IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2 + } }, + + { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */ + { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0, + IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, + PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3, + IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 + } }, +}; + +#define INTPRI 0xffd00010 +#define INT2PRI0 0xffd40000 +#define INT2PRI1 0xffd40004 +#define INT2PRI2 0xffd40008 +#define INT2PRI3 0xffd4000c +#define INT2PRI4 0xffd40010 +#define INT2PRI5 0xffd40014 +#define INT2PRI6 0xffd40018 +#define INT2PRI7 0xffd4001c +#define INT2PRI8 0xffd400a0 +#define INT2PRI9 0xffd400a4 +#define INT2PRI10 0xffd400a8 +#define INT2PRI11 0xffd400ac +#define INT2PRI12 0xffd400b0 +#define INT2PRI13 0xffd400b4 +#define INT2PRI14 0xffd400b8 +#define INT2PRI15 0xffd400bc +#define INT2PRI16 0xffd10000 +#define INT2PRI17 0xffd10004 +#define INT2PRI18 0xffd10008 +#define INT2PRI19 0xffd1000c +#define INT2PRI20 0xffd10010 +#define INT2PRI21 0xffd10014 +#define INT2PRI22 0xffd10018 +#define INT2PRI23 0xffd1001c +#define INT2PRI24 0xffd100a0 +#define INT2PRI25 0xffd100a4 +#define INT2PRI26 0xffd100a8 +#define INT2PRI27 0xffd100ac +#define INT2PRI28 0xffd100b0 +#define INT2PRI29 0xffd100b4 +#define INT2PRI30 0xffd100b8 +#define INT2PRI31 0xffd100bc + +static struct intc_prio_reg prio_registers[] __initdata = { + { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, + IRQ4, IRQ5, IRQ6, IRQ7 } }, + + { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, + { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, + { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } }, + { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } }, + { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, + { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } }, + { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } }, + { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, + { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, + { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, + { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } }, + { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } }, + { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, + { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, + + { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, + { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } }, + { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, + { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, + { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, + { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, + { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } }, + { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } }, + { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } }, + { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, + { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } }, + { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } }, + { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } }, + { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, + { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } }, + { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, + mask_registers, prio_registers, NULL); + +/* Support for external interrupt pins in IRQ mode */ +static struct intc_vect vectors_irq0123[] __initdata = { + INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), + INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), +}; + +static struct intc_vect vectors_irq4567[] __initdata = { + INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), + INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), +}; + +static struct intc_sense_reg sense_registers[] __initdata = { + { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, + IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static struct intc_mask_reg ack_registers[] __initdata = { + { 0xffd00024, 0, 32, /* INTREQ */ + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123", + vectors_irq0123, NULL, mask_registers, + prio_registers, sense_registers, ack_registers); + +static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567", + vectors_irq4567, NULL, mask_registers, + prio_registers, sense_registers, ack_registers); + +/* External interrupt pins in IRL mode */ +static struct intc_vect vectors_irl0123[] __initdata = { + INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), + INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), + INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), + INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), + INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), + INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), + INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), + INTC_VECT(IRL0_HHHL, 0x3c0), +}; + +static struct intc_vect vectors_irl4567[] __initdata = { + INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20), + INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60), + INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0), + INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0), + INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20), + INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60), + INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0), + INTC_VECT(IRL4_HHHL, 0xcc0), +}; + +static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123, + NULL, mask_registers, NULL, NULL); + +static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567, + NULL, mask_registers, NULL, NULL); + +#define INTC_ICR0 0xffd00000 +#define INTC_INTMSK0 0xffd00044 +#define INTC_INTMSK1 0xffd00048 +#define INTC_INTMSK2 0xffd40080 +#define INTC_INTMSKCLR1 0xffd00068 +#define INTC_INTMSKCLR2 0xffd40084 + +void __init plat_irq_setup(void) +{ + /* disable IRQ3-0 + IRQ7-4 */ + ctrl_outl(0xff000000, INTC_INTMSK0); + + /* disable IRL3-0 + IRL7-4 */ + ctrl_outl(0xc0000000, INTC_INTMSK1); + ctrl_outl(0xfffefffe, INTC_INTMSK2); + + /* select IRL mode for IRL3-0 + IRL7-4 */ + ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); + + /* disable holding function, ie enable "SH-4 Mode" */ + ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); + + register_intc_controller(&intc_desc); +} + +void __init plat_irq_setup_pins(int mode) +{ + switch (mode) { + case IRQ_MODE_IRQ7654: + /* select IRQ mode for IRL7-4 */ + ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); + register_intc_controller(&intc_desc_irq4567); + break; + case IRQ_MODE_IRQ3210: + /* select IRQ mode for IRL3-0 */ + ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); + register_intc_controller(&intc_desc_irq0123); + break; + case IRQ_MODE_IRL7654: + /* enable IRL7-4 but don't provide any masking */ + ctrl_outl(0x40000000, INTC_INTMSKCLR1); + ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); + break; + case IRQ_MODE_IRL3210: + /* enable IRL0-3 but don't provide any masking */ + ctrl_outl(0x80000000, INTC_INTMSKCLR1); + ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); + break; + case IRQ_MODE_IRL7654_MASK: + /* enable IRL7-4 and mask using cpu intc controller */ + ctrl_outl(0x40000000, INTC_INTMSKCLR1); + register_intc_controller(&intc_desc_irl4567); + break; + case IRQ_MODE_IRL3210_MASK: + /* enable IRL0-3 and mask using cpu intc controller */ + ctrl_outl(0x80000000, INTC_INTMSKCLR1); + register_intc_controller(&intc_desc_irl0123); + break; + default: + BUG(); + } +} + +void __init plat_mem_setup(void) +{ +} diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 07f078961c71..e848443deeb9 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c @@ -268,11 +268,7 @@ enum { UNUSED = 0, /* interrupt sources */ - IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, - IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, - IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, - IRL_HHLL, IRL_HHLH, IRL_HHHL, - IRQ0, IRQ1, IRQ2, IRQ3, + IRL, IRQ0, IRQ1, IRQ2, IRQ3, HUDII, TMU0, TMU1, TMU2, TMU3, TMU4, TMU5, PCII0, PCII1, PCII2, PCII3, PCII4, @@ -287,10 +283,7 @@ enum { DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE, IIC, VIN0, VIN1, VCORE0, ATAPI, - DTU0_TEND, DTU0_AE, DTU0_TMISS, - DTU1_TEND, DTU1_AE, DTU1_TMISS, - DTU2_TEND, DTU2_AE, DTU2_TMISS, - DTU3_TEND, DTU3_AE, DTU3_TMISS, + DTU0, DTU1, DTU2, DTU3, FE0, FE1, GPIO0, GPIO1, GPIO2, GPIO3, PAM, IRM, @@ -298,8 +291,8 @@ enum { INTICI4, INTICI5, INTICI6, INTICI7, /* interrupt groups */ - IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3, - DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3, + PCII56789, SCIF0, SCIF1, SCIF2, SCIF3, + DMAC0, DMAC1, }; static struct intc_vect vectors[] __initdata = { @@ -332,14 +325,14 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(IIC, 0xae0), INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20), INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60), - INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20), - INTC_VECT(DTU0_TMISS, 0xc40), - INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80), - INTC_VECT(DTU1_TMISS, 0xca0), - INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0), - INTC_VECT(DTU2_TMISS, 0xd00), - INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40), - INTC_VECT(DTU3_TMISS, 0xd60), + INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20), + INTC_VECT(DTU0, 0xc40), + INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80), + INTC_VECT(DTU1, 0xca0), + INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0), + INTC_VECT(DTU2, 0xd00), + INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40), + INTC_VECT(DTU3, 0xd60), INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20), INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60), INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0), @@ -351,10 +344,6 @@ static struct intc_vect vectors[] __initdata = { }; static struct intc_group groups[] __initdata = { - INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, - IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, - IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, - IRL_HHLL, IRL_HHLH, IRL_HHHL), INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9), INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), @@ -364,10 +353,6 @@ static struct intc_group groups[] __initdata = { DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), - INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS), - INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS), - INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS), - INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS), }; static struct intc_mask_reg mask_registers[] __initdata = { @@ -434,14 +419,14 @@ static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups, /* External interrupt pins in IRL mode */ static struct intc_vect vectors_irl[] __initdata = { - INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), - INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), - INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), - INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), - INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), - INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), - INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), - INTC_VECT(IRL_HHHL, 0x3c0), + INTC_VECT(IRL, 0x200), INTC_VECT(IRL, 0x220), + INTC_VECT(IRL, 0x240), INTC_VECT(IRL, 0x260), + INTC_VECT(IRL, 0x280), INTC_VECT(IRL, 0x2a0), + INTC_VECT(IRL, 0x2c0), INTC_VECT(IRL, 0x2e0), + INTC_VECT(IRL, 0x300), INTC_VECT(IRL, 0x320), + INTC_VECT(IRL, 0x340), INTC_VECT(IRL, 0x360), + INTC_VECT(IRL, 0x380), INTC_VECT(IRL, 0x3a0), + INTC_VECT(IRL, 0x3c0), }; static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups, diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c index 2b6b0d50c576..185ec3976a25 100644 --- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c @@ -57,6 +57,8 @@ void __init plat_prepare_cpus(unsigned int max_cpus) { int i; + local_timer_setup(0); + BUILD_BUG_ON(SMP_MSG_NR >= 8); for (i = 0; i < SMP_MSG_NR; i++) diff --git a/arch/sh/kernel/cpu/sh5/probe.c b/arch/sh/kernel/cpu/sh5/probe.c index 92ad844b5c12..521d05b3f7ba 100644 --- a/arch/sh/kernel/cpu/sh5/probe.c +++ b/arch/sh/kernel/cpu/sh5/probe.c @@ -34,6 +34,8 @@ int __init detect_cpu_and_cache_system(void) /* CPU.VCR aliased at CIR address on SH5-101 */ boot_cpu_data.type = CPU_SH5_101; + boot_cpu_data.family = CPU_FAMILY_SH5; + /* * First, setup some sane values for the I-cache. */ diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile index 08bfa7c7db29..a39f88ea1a85 100644 --- a/arch/sh/kernel/cpu/shmobile/Makefile +++ b/arch/sh/kernel/cpu/shmobile/Makefile @@ -4,3 +4,5 @@ # Power Management & Sleep mode obj-$(CONFIG_PM) += pm.o sleep.o +obj-$(CONFIG_CPU_IDLE) += cpuidle.o +obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c new file mode 100644 index 000000000000..1c504bd972c3 --- /dev/null +++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c @@ -0,0 +1,113 @@ +/* + * arch/sh/kernel/cpu/shmobile/cpuidle.c + * + * Cpuidle support code for SuperH Mobile + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/suspend.h> +#include <linux/cpuidle.h> +#include <asm/suspend.h> +#include <asm/uaccess.h> +#include <asm/hwblk.h> + +static unsigned long cpuidle_mode[] = { + SUSP_SH_SLEEP, /* regular sleep mode */ + SUSP_SH_SLEEP | SUSP_SH_SF, /* sleep mode + self refresh */ + SUSP_SH_STANDBY | SUSP_SH_SF, /* software standby mode + self refresh */ +}; + +static int cpuidle_sleep_enter(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + unsigned long allowed_mode = arch_hwblk_sleep_mode(); + ktime_t before, after; + int requested_state = state - &dev->states[0]; + int allowed_state; + int k; + + /* convert allowed mode to allowed state */ + for (k = ARRAY_SIZE(cpuidle_mode) - 1; k > 0; k--) + if (cpuidle_mode[k] == allowed_mode) + break; + + allowed_state = k; + + /* take the following into account for sleep mode selection: + * - allowed_state: best mode allowed by hardware (clock deps) + * - requested_state: best mode allowed by software (latencies) + */ + k = min_t(int, allowed_state, requested_state); + + dev->last_state = &dev->states[k]; + before = ktime_get(); + sh_mobile_call_standby(cpuidle_mode[k]); + after = ktime_get(); + return ktime_to_ns(ktime_sub(after, before)) >> 10; +} + +static struct cpuidle_device cpuidle_dev; +static struct cpuidle_driver cpuidle_driver = { + .name = "sh_idle", + .owner = THIS_MODULE, +}; + +void sh_mobile_setup_cpuidle(void) +{ + struct cpuidle_device *dev = &cpuidle_dev; + struct cpuidle_state *state; + int i; + + cpuidle_register_driver(&cpuidle_driver); + + for (i = 0; i < CPUIDLE_STATE_MAX; i++) { + dev->states[i].name[0] = '\0'; + dev->states[i].desc[0] = '\0'; + } + + i = CPUIDLE_DRIVER_STATE_START; + + state = &dev->states[i++]; + snprintf(state->name, CPUIDLE_NAME_LEN, "C0"); + strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN); + state->exit_latency = 1; + state->target_residency = 1 * 2; + state->power_usage = 3; + state->flags = 0; + state->flags |= CPUIDLE_FLAG_SHALLOW; + state->flags |= CPUIDLE_FLAG_TIME_VALID; + state->enter = cpuidle_sleep_enter; + + dev->safe_state = state; + + state = &dev->states[i++]; + snprintf(state->name, CPUIDLE_NAME_LEN, "C1"); + strncpy(state->desc, "SuperH Sleep Mode [SF]", CPUIDLE_DESC_LEN); + state->exit_latency = 100; + state->target_residency = 1 * 2; + state->power_usage = 1; + state->flags = 0; + state->flags |= CPUIDLE_FLAG_TIME_VALID; + state->enter = cpuidle_sleep_enter; + + state = &dev->states[i++]; + snprintf(state->name, CPUIDLE_NAME_LEN, "C2"); + strncpy(state->desc, "SuperH Mobile Standby Mode [SF]", CPUIDLE_DESC_LEN); + state->exit_latency = 2300; + state->target_residency = 1 * 2; + state->power_usage = 1; + state->flags = 0; + state->flags |= CPUIDLE_FLAG_TIME_VALID; + state->enter = cpuidle_sleep_enter; + + dev->state_count = i; + + cpuidle_register_device(dev); +} diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c index 8c067adf6830..ee3c2aaf66fb 100644 --- a/arch/sh/kernel/cpu/shmobile/pm.c +++ b/arch/sh/kernel/cpu/shmobile/pm.c @@ -1,5 +1,5 @@ /* - * arch/sh/kernel/cpu/sh4a/pm-sh_mobile.c + * arch/sh/kernel/cpu/shmobile/pm.c * * Power management support code for SuperH Mobile * @@ -32,40 +32,20 @@ * * R-standby mode is unsupported, but will be added in the future * U-standby mode is low priority since it needs bootloader hacks - * - * All modes should be tied in with cpuidle. But before that can - * happen we need to keep track of enabled hardware blocks so we - * can avoid entering sleep modes that stop clocks to hardware - * blocks that are in use even though the cpu core is idle. */ +#define ILRAM_BASE 0xe5200000 + extern const unsigned char sh_mobile_standby[]; extern const unsigned int sh_mobile_standby_size; -static void sh_mobile_call_standby(unsigned long mode) +void sh_mobile_call_standby(unsigned long mode) { - extern void *vbr_base; - void *onchip_mem = (void *)0xe5200000; /* ILRAM */ - void (*standby_onchip_mem)(unsigned long) = onchip_mem; - - /* Note: Wake up from sleep may generate exceptions! - * Setup VBR to point to on-chip ram if self-refresh is - * going to be used. - */ - if (mode & SUSP_SH_SF) - asm volatile("ldc %0, vbr" : : "r" (onchip_mem) : "memory"); - - /* Copy the assembly snippet to the otherwise ununsed ILRAM */ - memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size); - wmb(); - ctrl_barrier(); + void *onchip_mem = (void *)ILRAM_BASE; + void (*standby_onchip_mem)(unsigned long, unsigned long) = onchip_mem; /* Let assembly snippet in on-chip memory handle the rest */ - standby_onchip_mem(mode); - - /* Put VBR back in System RAM again */ - if (mode & SUSP_SH_SF) - asm volatile("ldc %0, vbr" : : "r" (&vbr_base) : "memory"); + standby_onchip_mem(mode, ILRAM_BASE); } static int sh_pm_enter(suspend_state_t state) @@ -85,7 +65,15 @@ static struct platform_suspend_ops sh_pm_ops = { static int __init sh_pm_init(void) { + void *onchip_mem = (void *)ILRAM_BASE; + + /* Copy the assembly snippet to the otherwise ununsed ILRAM */ + memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size); + wmb(); + ctrl_barrier(); + suspend_set_ops(&sh_pm_ops); + sh_mobile_setup_cpuidle(); return 0; } diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c new file mode 100644 index 000000000000..7c615b17e209 --- /dev/null +++ b/arch/sh/kernel/cpu/shmobile/pm_runtime.c @@ -0,0 +1,303 @@ +/* + * arch/sh/kernel/cpu/shmobile/pm_runtime.c + * + * Runtime PM support code for SuperH Mobile + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/pm_runtime.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> +#include <asm/hwblk.h> + +static DEFINE_SPINLOCK(hwblk_lock); +static LIST_HEAD(hwblk_idle_list); +static struct work_struct hwblk_work; + +extern struct hwblk_info *hwblk_info; + +static void platform_pm_runtime_not_idle(struct platform_device *pdev) +{ + unsigned long flags; + + /* remove device from idle list */ + spin_lock_irqsave(&hwblk_lock, flags); + if (test_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags)) { + list_del(&pdev->archdata.entry); + __clear_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags); + } + spin_unlock_irqrestore(&hwblk_lock, flags); +} + +static int __platform_pm_runtime_resume(struct platform_device *pdev) +{ + struct device *d = &pdev->dev; + struct pdev_archdata *ad = &pdev->archdata; + int hwblk = ad->hwblk_id; + int ret = -ENOSYS; + + dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk); + + if (d->driver && d->driver->pm && d->driver->pm->runtime_resume) { + hwblk_enable(hwblk_info, hwblk); + ret = 0; + + if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) { + ret = d->driver->pm->runtime_resume(d); + if (!ret) + clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags); + else + hwblk_disable(hwblk_info, hwblk); + } + } + + dev_dbg(d, "__platform_pm_runtime_resume() [%d] - returns %d\n", + hwblk, ret); + + return ret; +} + +static int __platform_pm_runtime_suspend(struct platform_device *pdev) +{ + struct device *d = &pdev->dev; + struct pdev_archdata *ad = &pdev->archdata; + int hwblk = ad->hwblk_id; + int ret = -ENOSYS; + + dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk); + + if (d->driver && d->driver->pm && d->driver->pm->runtime_suspend) { + BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags)); + + hwblk_enable(hwblk_info, hwblk); + ret = d->driver->pm->runtime_suspend(d); + hwblk_disable(hwblk_info, hwblk); + + if (!ret) { + set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags); + platform_pm_runtime_not_idle(pdev); + hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE); + } + } + + dev_dbg(d, "__platform_pm_runtime_suspend() [%d] - returns %d\n", + hwblk, ret); + + return ret; +} + +static void platform_pm_runtime_work(struct work_struct *work) +{ + struct platform_device *pdev; + unsigned long flags; + int ret; + + /* go through the idle list and suspend one device at a time */ + do { + spin_lock_irqsave(&hwblk_lock, flags); + if (list_empty(&hwblk_idle_list)) + pdev = NULL; + else + pdev = list_first_entry(&hwblk_idle_list, + struct platform_device, + archdata.entry); + spin_unlock_irqrestore(&hwblk_lock, flags); + + if (pdev) { + mutex_lock(&pdev->archdata.mutex); + ret = __platform_pm_runtime_suspend(pdev); + + /* at this point the platform device may be: + * suspended: ret = 0, FLAG_SUSP set, clock stopped + * failed: ret < 0, FLAG_IDLE set, clock stopped + */ + mutex_unlock(&pdev->archdata.mutex); + } else { + ret = -ENODEV; + } + } while (!ret); +} + +/* this function gets called from cpuidle context when all devices in the + * main power domain are unused but some are counted as idle, ie the hwblk + * counter values are (HWBLK_CNT_USAGE == 0) && (HWBLK_CNT_IDLE != 0) + */ +void platform_pm_runtime_suspend_idle(void) +{ + queue_work(pm_wq, &hwblk_work); +} + +int platform_pm_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct pdev_archdata *ad = &pdev->archdata; + unsigned long flags; + int hwblk = ad->hwblk_id; + int ret = 0; + + dev_dbg(dev, "platform_pm_runtime_suspend() [%d]\n", hwblk); + + /* ignore off-chip platform devices */ + if (!hwblk) + goto out; + + /* interrupt context not allowed */ + might_sleep(); + + /* catch misconfigured drivers not starting with resume */ + if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags)) { + ret = -EINVAL; + goto out; + } + + /* serialize */ + mutex_lock(&ad->mutex); + + /* disable clock */ + hwblk_disable(hwblk_info, hwblk); + + /* put device on idle list */ + spin_lock_irqsave(&hwblk_lock, flags); + list_add_tail(&pdev->archdata.entry, &hwblk_idle_list); + __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags); + spin_unlock_irqrestore(&hwblk_lock, flags); + + /* increase idle count */ + hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_IDLE); + + /* at this point the platform device is: + * idle: ret = 0, FLAG_IDLE set, clock stopped + */ + mutex_unlock(&ad->mutex); + +out: + dev_dbg(dev, "platform_pm_runtime_suspend() [%d] returns %d\n", + hwblk, ret); + + return ret; +} + +int platform_pm_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct pdev_archdata *ad = &pdev->archdata; + int hwblk = ad->hwblk_id; + int ret = 0; + + dev_dbg(dev, "platform_pm_runtime_resume() [%d]\n", hwblk); + + /* ignore off-chip platform devices */ + if (!hwblk) + goto out; + + /* interrupt context not allowed */ + might_sleep(); + + /* serialize */ + mutex_lock(&ad->mutex); + + /* make sure device is removed from idle list */ + platform_pm_runtime_not_idle(pdev); + + /* decrease idle count */ + if (!test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags) && + !test_bit(PDEV_ARCHDATA_FLAG_SUSP, &pdev->archdata.flags)) + hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE); + + /* resume the device if needed */ + ret = __platform_pm_runtime_resume(pdev); + + /* the driver has been initialized now, so clear the init flag */ + clear_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags); + + /* at this point the platform device may be: + * resumed: ret = 0, flags = 0, clock started + * failed: ret < 0, FLAG_SUSP set, clock stopped + */ + mutex_unlock(&ad->mutex); +out: + dev_dbg(dev, "platform_pm_runtime_resume() [%d] returns %d\n", + hwblk, ret); + + return ret; +} + +int platform_pm_runtime_idle(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + int hwblk = pdev->archdata.hwblk_id; + int ret = 0; + + dev_dbg(dev, "platform_pm_runtime_idle() [%d]\n", hwblk); + + /* ignore off-chip platform devices */ + if (!hwblk) + goto out; + + /* interrupt context not allowed, use pm_runtime_put()! */ + might_sleep(); + + /* suspend synchronously to disable clocks immediately */ + ret = pm_runtime_suspend(dev); +out: + dev_dbg(dev, "platform_pm_runtime_idle() [%d] done!\n", hwblk); + return ret; +} + +static int platform_bus_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct device *dev = data; + struct platform_device *pdev = to_platform_device(dev); + int hwblk = pdev->archdata.hwblk_id; + + /* ignore off-chip platform devices */ + if (!hwblk) + return 0; + + switch (action) { + case BUS_NOTIFY_ADD_DEVICE: + INIT_LIST_HEAD(&pdev->archdata.entry); + mutex_init(&pdev->archdata.mutex); + /* platform devices without drivers should be disabled */ + hwblk_enable(hwblk_info, hwblk); + hwblk_disable(hwblk_info, hwblk); + /* make sure driver re-inits itself once */ + __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags); + break; + /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */ + case BUS_NOTIFY_BOUND_DRIVER: + /* keep track of number of devices in use per hwblk */ + hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_DEVICES); + break; + case BUS_NOTIFY_UNBOUND_DRIVER: + /* keep track of number of devices in use per hwblk */ + hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_DEVICES); + /* make sure driver re-inits itself once */ + __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags); + break; + case BUS_NOTIFY_DEL_DEVICE: + break; + } + return 0; +} + +static struct notifier_block platform_bus_notifier = { + .notifier_call = platform_bus_notify +}; + +static int __init sh_pm_runtime_init(void) +{ + INIT_WORK(&hwblk_work, platform_pm_runtime_work); + + bus_register_notifier(&platform_bus_type, &platform_bus_notifier); + return 0; +} +core_initcall(sh_pm_runtime_init); diff --git a/arch/sh/kernel/cpu/shmobile/sleep.S b/arch/sh/kernel/cpu/shmobile/sleep.S index baf2d7d46b05..a439e6c7824f 100644 --- a/arch/sh/kernel/cpu/shmobile/sleep.S +++ b/arch/sh/kernel/cpu/shmobile/sleep.S @@ -16,19 +16,52 @@ #include <asm/asm-offsets.h> #include <asm/suspend.h> +/* + * Kernel mode register usage, see entry.S: + * k0 scratch + * k1 scratch + * k4 scratch + */ +#define k0 r0 +#define k1 r1 +#define k4 r4 + /* manage self-refresh and enter standby mode. * this code will be copied to on-chip memory and executed from there. */ .balign 4096,0,4096 ENTRY(sh_mobile_standby) + + /* save original vbr */ + stc vbr, r1 + mova saved_vbr, r0 + mov.l r1, @r0 + + /* point vbr to our on-chip memory page */ + ldc r5, vbr + + /* save return address */ + mova saved_spc, r0 + sts pr, r5 + mov.l r5, @r0 + + /* save sr */ + mova saved_sr, r0 + stc sr, r5 + mov.l r5, @r0 + + /* save mode flags */ + mova saved_mode, r0 + mov.l r4, @r0 + + /* put mode flags in r0 */ mov r4, r0 tst #SUSP_SH_SF, r0 bt skip_set_sf #ifdef CONFIG_CPU_SUBTYPE_SH7724 /* DBSC: put memory in self-refresh mode */ - mov.l dben_reg, r4 mov.l dben_data0, r1 mov.l r1, @r4 @@ -60,14 +93,6 @@ ENTRY(sh_mobile_standby) #endif skip_set_sf: - tst #SUSP_SH_SLEEP, r0 - bt test_standby - - /* set mode to "sleep mode" */ - bra do_sleep - mov #0x00, r1 - -test_standby: tst #SUSP_SH_STANDBY, r0 bt test_rstandby @@ -85,77 +110,107 @@ test_rstandby: test_ustandby: tst #SUSP_SH_USTANDBY, r0 - bt done_sleep + bt force_sleep /* set mode to "u-standby mode" */ - mov #0x10, r1 + bra do_sleep + mov #0x10, r1 - /* fall-through */ +force_sleep: + + /* set mode to "sleep mode" */ + mov #0x00, r1 do_sleep: /* setup and enter selected standby mode */ mov.l 5f, r4 mov.l r1, @r4 +again: sleep + bra again + nop + +restore_jump_vbr: + /* setup spc with return address to c code */ + mov.l saved_spc, k0 + ldc k0, spc + + /* restore vbr */ + mov.l saved_vbr, k0 + ldc k0, vbr + + /* setup ssr with saved sr */ + mov.l saved_sr, k0 + ldc k0, ssr + + /* get mode flags */ + mov.l saved_mode, k0 done_sleep: /* reset standby mode to sleep mode */ - mov.l 5f, r4 - mov #0x00, r1 - mov.l r1, @r4 + mov.l 5f, k4 + mov #0x00, k1 + mov.l k1, @k4 - tst #SUSP_SH_SF, r0 + tst #SUSP_SH_SF, k0 bt skip_restore_sf #ifdef CONFIG_CPU_SUBTYPE_SH7724 /* DBSC: put memory in auto-refresh mode */ + mov.l dbrfpdn0_reg, k4 + mov.l dbrfpdn0_data0, k1 + mov.l k1, @k4 - mov.l dbrfpdn0_reg, r4 - mov.l dbrfpdn0_data0, r1 - mov.l r1, @r4 - - /* sleep 140 ns */ - nop + nop /* sleep 140 ns */ nop nop nop - mov.l dbcmdcnt_reg, r4 - mov.l dbcmdcnt_data0, r1 - mov.l r1, @r4 + mov.l dbcmdcnt_reg, k4 + mov.l dbcmdcnt_data0, k1 + mov.l k1, @k4 - mov.l dbcmdcnt_reg, r4 - mov.l dbcmdcnt_data1, r1 - mov.l r1, @r4 + mov.l dbcmdcnt_reg, k4 + mov.l dbcmdcnt_data1, k1 + mov.l k1, @k4 - mov.l dben_reg, r4 - mov.l dben_data1, r1 - mov.l r1, @r4 + mov.l dben_reg, k4 + mov.l dben_data1, k1 + mov.l k1, @k4 - mov.l dbrfpdn0_reg, r4 - mov.l dbrfpdn0_data2, r1 - mov.l r1, @r4 + mov.l dbrfpdn0_reg, k4 + mov.l dbrfpdn0_data2, k1 + mov.l k1, @k4 #else /* SBSC: set auto-refresh mode */ - mov.l 1f, r4 - mov.l @r4, r2 - mov.l 4f, r3 - and r3, r2 - mov.l r2, @r4 - mov.l 6f, r4 - mov.l 7f, r1 - mov.l 8f, r2 - mov.l @r4, r3 - mov #-1, r4 - add r4, r3 - or r2, r3 - mov.l r3, @r1 + mov.l 1f, k4 + mov.l @k4, k0 + mov.l 4f, k1 + and k1, k0 + mov.l k0, @k4 + mov.l 6f, k4 + mov.l 8f, k0 + mov.l @k4, k1 + mov #-1, k4 + add k4, k1 + or k1, k0 + mov.l 7f, k1 + mov.l k0, @k1 #endif skip_restore_sf: - rts + /* jump to vbr vector */ + mov.l saved_vbr, k0 + mov.l offset_vbr, k4 + add k4, k0 + jmp @k0 nop .balign 4 +saved_mode: .long 0 +saved_spc: .long 0 +saved_sr: .long 0 +saved_vbr: .long 0 +offset_vbr: .long 0x600 #ifdef CONFIG_CPU_SUBTYPE_SH7724 dben_reg: .long 0xfd000010 /* DBEN */ dben_data0: .long 0 @@ -178,12 +233,12 @@ dbcmdcnt_data1: .long 4 7: .long 0xfe400018 /* RTCNT */ 8: .long 0xa55a0000 + /* interrupt vector @ 0x600 */ .balign 0x400,0,0x400 .long 0xdeadbeef .balign 0x200,0,0x200 - /* sh7722 will end up here in sleep mode */ - rte + bra restore_jump_vbr nop sh_mobile_standby_end: diff --git a/arch/sh/kernel/cpufreq.c b/arch/sh/kernel/cpufreq.c index e0590ffebd73..dce4f3ff0932 100644 --- a/arch/sh/kernel/cpufreq.c +++ b/arch/sh/kernel/cpufreq.c @@ -82,7 +82,8 @@ static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy) cpuclk = clk_get(NULL, "cpu_clk"); if (IS_ERR(cpuclk)) { - printk(KERN_ERR "cpufreq: couldn't get CPU clk\n"); + printk(KERN_ERR "cpufreq: couldn't get CPU#%d clk\n", + policy->cpu); return PTR_ERR(cpuclk); } @@ -95,22 +96,21 @@ static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy) policy->min = policy->cpuinfo.min_freq; policy->max = policy->cpuinfo.max_freq; - /* * Catch the cases where the clock framework hasn't been wired up * properly to support scaling. */ if (unlikely(policy->min == policy->max)) { printk(KERN_ERR "cpufreq: clock framework rate rounding " - "not supported on this CPU.\n"); + "not supported on CPU#%d.\n", policy->cpu); clk_put(cpuclk); return -EINVAL; } - printk(KERN_INFO "cpufreq: Frequencies - Minimum %u.%03u MHz, " + printk(KERN_INFO "cpufreq: CPU#%d Frequencies - Minimum %u.%03u MHz, " "Maximum %u.%03u MHz.\n", - policy->min / 1000, policy->min % 1000, + policy->cpu, policy->min / 1000, policy->min % 1000, policy->max / 1000, policy->max % 1000); return 0; diff --git a/arch/sh/kernel/dumpstack.c b/arch/sh/kernel/dumpstack.c new file mode 100644 index 000000000000..6f5ad1513409 --- /dev/null +++ b/arch/sh/kernel/dumpstack.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 1991, 1992 Linus Torvalds + * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs + * Copyright (C) 2009 Matt Fleming + */ +#include <linux/kallsyms.h> +#include <linux/ftrace.h> +#include <linux/debug_locks.h> +#include <asm/unwinder.h> +#include <asm/stacktrace.h> + +void printk_address(unsigned long address, int reliable) +{ + printk(" [<%p>] %s%pS\n", (void *) address, + reliable ? "" : "? ", (void *) address); +} + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER +static void +print_ftrace_graph_addr(unsigned long addr, void *data, + const struct stacktrace_ops *ops, + struct thread_info *tinfo, int *graph) +{ + struct task_struct *task = tinfo->task; + unsigned long ret_addr; + int index = task->curr_ret_stack; + + if (addr != (unsigned long)return_to_handler) + return; + + if (!task->ret_stack || index < *graph) + return; + + index -= *graph; + ret_addr = task->ret_stack[index].ret; + + ops->address(data, ret_addr, 1); + + (*graph)++; +} +#else +static inline void +print_ftrace_graph_addr(unsigned long addr, void *data, + const struct stacktrace_ops *ops, + struct thread_info *tinfo, int *graph) +{ } +#endif + +void +stack_reader_dump(struct task_struct *task, struct pt_regs *regs, + unsigned long *sp, const struct stacktrace_ops *ops, + void *data) +{ + struct thread_info *context; + int graph = 0; + + context = (struct thread_info *) + ((unsigned long)sp & (~(THREAD_SIZE - 1))); + + while (!kstack_end(sp)) { + unsigned long addr = *sp++; + + if (__kernel_text_address(addr)) { + ops->address(data, addr, 1); + + print_ftrace_graph_addr(addr, data, ops, + context, &graph); + } + } +} + +static void +print_trace_warning_symbol(void *data, char *msg, unsigned long symbol) +{ + printk(data); + print_symbol(msg, symbol); + printk("\n"); +} + +static void print_trace_warning(void *data, char *msg) +{ + printk("%s%s\n", (char *)data, msg); +} + +static int print_trace_stack(void *data, char *name) +{ + printk("%s <%s> ", (char *)data, name); + return 0; +} + +/* + * Print one address/symbol entries per line. + */ +static void print_trace_address(void *data, unsigned long addr, int reliable) +{ + printk(data); + printk_address(addr, reliable); +} + +static const struct stacktrace_ops print_trace_ops = { + .warning = print_trace_warning, + .warning_symbol = print_trace_warning_symbol, + .stack = print_trace_stack, + .address = print_trace_address, +}; + +void show_trace(struct task_struct *tsk, unsigned long *sp, + struct pt_regs *regs) +{ + if (regs && user_mode(regs)) + return; + + printk("\nCall trace:\n"); + + unwind_stack(tsk, regs, sp, &print_trace_ops, ""); + + printk("\n"); + + if (!tsk) + tsk = current; + + debug_show_held_locks(tsk); +} diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c new file mode 100644 index 000000000000..bc4d8d75332b --- /dev/null +++ b/arch/sh/kernel/dwarf.c @@ -0,0 +1,972 @@ +/* + * Copyright (C) 2009 Matt Fleming <matt@console-pimps.org> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * This is an implementation of a DWARF unwinder. Its main purpose is + * for generating stacktrace information. Based on the DWARF 3 + * specification from http://www.dwarfstd.org. + * + * TODO: + * - DWARF64 doesn't work. + * - Registers with DWARF_VAL_OFFSET rules aren't handled properly. + */ + +/* #define DEBUG */ +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/list.h> +#include <linux/mempool.h> +#include <linux/mm.h> +#include <asm/dwarf.h> +#include <asm/unwinder.h> +#include <asm/sections.h> +#include <asm/unaligned.h> +#include <asm/dwarf.h> +#include <asm/stacktrace.h> + +/* Reserve enough memory for two stack frames */ +#define DWARF_FRAME_MIN_REQ 2 +/* ... with 4 registers per frame. */ +#define DWARF_REG_MIN_REQ (DWARF_FRAME_MIN_REQ * 4) + +static struct kmem_cache *dwarf_frame_cachep; +static mempool_t *dwarf_frame_pool; + +static struct kmem_cache *dwarf_reg_cachep; +static mempool_t *dwarf_reg_pool; + +static LIST_HEAD(dwarf_cie_list); +static DEFINE_SPINLOCK(dwarf_cie_lock); + +static LIST_HEAD(dwarf_fde_list); +static DEFINE_SPINLOCK(dwarf_fde_lock); + +static struct dwarf_cie *cached_cie; + +/** + * dwarf_frame_alloc_reg - allocate memory for a DWARF register + * @frame: the DWARF frame whose list of registers we insert on + * @reg_num: the register number + * + * Allocate space for, and initialise, a dwarf reg from + * dwarf_reg_pool and insert it onto the (unsorted) linked-list of + * dwarf registers for @frame. + * + * Return the initialised DWARF reg. + */ +static struct dwarf_reg *dwarf_frame_alloc_reg(struct dwarf_frame *frame, + unsigned int reg_num) +{ + struct dwarf_reg *reg; + + reg = mempool_alloc(dwarf_reg_pool, GFP_ATOMIC); + if (!reg) { + printk(KERN_WARNING "Unable to allocate a DWARF register\n"); + /* + * Let's just bomb hard here, we have no way to + * gracefully recover. + */ + UNWINDER_BUG(); + } + + reg->number = reg_num; + reg->addr = 0; + reg->flags = 0; + + list_add(®->link, &frame->reg_list); + + return reg; +} + +static void dwarf_frame_free_regs(struct dwarf_frame *frame) +{ + struct dwarf_reg *reg, *n; + + list_for_each_entry_safe(reg, n, &frame->reg_list, link) { + list_del(®->link); + mempool_free(reg, dwarf_reg_pool); + } +} + +/** + * dwarf_frame_reg - return a DWARF register + * @frame: the DWARF frame to search in for @reg_num + * @reg_num: the register number to search for + * + * Lookup and return the dwarf reg @reg_num for this frame. Return + * NULL if @reg_num is an register invalid number. + */ +static struct dwarf_reg *dwarf_frame_reg(struct dwarf_frame *frame, + unsigned int reg_num) +{ + struct dwarf_reg *reg; + + list_for_each_entry(reg, &frame->reg_list, link) { + if (reg->number == reg_num) + return reg; + } + + return NULL; +} + +/** + * dwarf_read_addr - read dwarf data + * @src: source address of data + * @dst: destination address to store the data to + * + * Read 'n' bytes from @src, where 'n' is the size of an address on + * the native machine. We return the number of bytes read, which + * should always be 'n'. We also have to be careful when reading + * from @src and writing to @dst, because they can be arbitrarily + * aligned. Return 'n' - the number of bytes read. + */ +static inline int dwarf_read_addr(unsigned long *src, unsigned long *dst) +{ + u32 val = get_unaligned(src); + put_unaligned(val, dst); + return sizeof(unsigned long *); +} + +/** + * dwarf_read_uleb128 - read unsigned LEB128 data + * @addr: the address where the ULEB128 data is stored + * @ret: address to store the result + * + * Decode an unsigned LEB128 encoded datum. The algorithm is taken + * from Appendix C of the DWARF 3 spec. For information on the + * encodings refer to section "7.6 - Variable Length Data". Return + * the number of bytes read. + */ +static inline unsigned long dwarf_read_uleb128(char *addr, unsigned int *ret) +{ + unsigned int result; + unsigned char byte; + int shift, count; + + result = 0; + shift = 0; + count = 0; + + while (1) { + byte = __raw_readb(addr); + addr++; + count++; + + result |= (byte & 0x7f) << shift; + shift += 7; + + if (!(byte & 0x80)) + break; + } + + *ret = result; + + return count; +} + +/** + * dwarf_read_leb128 - read signed LEB128 data + * @addr: the address of the LEB128 encoded data + * @ret: address to store the result + * + * Decode signed LEB128 data. The algorithm is taken from Appendix + * C of the DWARF 3 spec. Return the number of bytes read. + */ +static inline unsigned long dwarf_read_leb128(char *addr, int *ret) +{ + unsigned char byte; + int result, shift; + int num_bits; + int count; + + result = 0; + shift = 0; + count = 0; + + while (1) { + byte = __raw_readb(addr); + addr++; + result |= (byte & 0x7f) << shift; + shift += 7; + count++; + + if (!(byte & 0x80)) + break; + } + + /* The number of bits in a signed integer. */ + num_bits = 8 * sizeof(result); + + if ((shift < num_bits) && (byte & 0x40)) + result |= (-1 << shift); + + *ret = result; + + return count; +} + +/** + * dwarf_read_encoded_value - return the decoded value at @addr + * @addr: the address of the encoded value + * @val: where to write the decoded value + * @encoding: the encoding with which we can decode @addr + * + * GCC emits encoded address in the .eh_frame FDE entries. Decode + * the value at @addr using @encoding. The decoded value is written + * to @val and the number of bytes read is returned. + */ +static int dwarf_read_encoded_value(char *addr, unsigned long *val, + char encoding) +{ + unsigned long decoded_addr = 0; + int count = 0; + + switch (encoding & 0x70) { + case DW_EH_PE_absptr: + break; + case DW_EH_PE_pcrel: + decoded_addr = (unsigned long)addr; + break; + default: + pr_debug("encoding=0x%x\n", (encoding & 0x70)); + UNWINDER_BUG(); + } + + if ((encoding & 0x07) == 0x00) + encoding |= DW_EH_PE_udata4; + + switch (encoding & 0x0f) { + case DW_EH_PE_sdata4: + case DW_EH_PE_udata4: + count += 4; + decoded_addr += get_unaligned((u32 *)addr); + __raw_writel(decoded_addr, val); + break; + default: + pr_debug("encoding=0x%x\n", encoding); + UNWINDER_BUG(); + } + + return count; +} + +/** + * dwarf_entry_len - return the length of an FDE or CIE + * @addr: the address of the entry + * @len: the length of the entry + * + * Read the initial_length field of the entry and store the size of + * the entry in @len. We return the number of bytes read. Return a + * count of 0 on error. + */ +static inline int dwarf_entry_len(char *addr, unsigned long *len) +{ + u32 initial_len; + int count; + + initial_len = get_unaligned((u32 *)addr); + count = 4; + + /* + * An initial length field value in the range DW_LEN_EXT_LO - + * DW_LEN_EXT_HI indicates an extension, and should not be + * interpreted as a length. The only extension that we currently + * understand is the use of DWARF64 addresses. + */ + if (initial_len >= DW_EXT_LO && initial_len <= DW_EXT_HI) { + /* + * The 64-bit length field immediately follows the + * compulsory 32-bit length field. + */ + if (initial_len == DW_EXT_DWARF64) { + *len = get_unaligned((u64 *)addr + 4); + count = 12; + } else { + printk(KERN_WARNING "Unknown DWARF extension\n"); + count = 0; + } + } else + *len = initial_len; + + return count; +} + +/** + * dwarf_lookup_cie - locate the cie + * @cie_ptr: pointer to help with lookup + */ +static struct dwarf_cie *dwarf_lookup_cie(unsigned long cie_ptr) +{ + struct dwarf_cie *cie; + unsigned long flags; + + spin_lock_irqsave(&dwarf_cie_lock, flags); + + /* + * We've cached the last CIE we looked up because chances are + * that the FDE wants this CIE. + */ + if (cached_cie && cached_cie->cie_pointer == cie_ptr) { + cie = cached_cie; + goto out; + } + + list_for_each_entry(cie, &dwarf_cie_list, link) { + if (cie->cie_pointer == cie_ptr) { + cached_cie = cie; + break; + } + } + + /* Couldn't find the entry in the list. */ + if (&cie->link == &dwarf_cie_list) + cie = NULL; +out: + spin_unlock_irqrestore(&dwarf_cie_lock, flags); + return cie; +} + +/** + * dwarf_lookup_fde - locate the FDE that covers pc + * @pc: the program counter + */ +struct dwarf_fde *dwarf_lookup_fde(unsigned long pc) +{ + struct dwarf_fde *fde; + unsigned long flags; + + spin_lock_irqsave(&dwarf_fde_lock, flags); + + list_for_each_entry(fde, &dwarf_fde_list, link) { + unsigned long start, end; + + start = fde->initial_location; + end = fde->initial_location + fde->address_range; + + if (pc >= start && pc < end) + break; + } + + /* Couldn't find the entry in the list. */ + if (&fde->link == &dwarf_fde_list) + fde = NULL; + + spin_unlock_irqrestore(&dwarf_fde_lock, flags); + + return fde; +} + +/** + * dwarf_cfa_execute_insns - execute instructions to calculate a CFA + * @insn_start: address of the first instruction + * @insn_end: address of the last instruction + * @cie: the CIE for this function + * @fde: the FDE for this function + * @frame: the instructions calculate the CFA for this frame + * @pc: the program counter of the address we're interested in + * + * Execute the Call Frame instruction sequence starting at + * @insn_start and ending at @insn_end. The instructions describe + * how to calculate the Canonical Frame Address of a stackframe. + * Store the results in @frame. + */ +static int dwarf_cfa_execute_insns(unsigned char *insn_start, + unsigned char *insn_end, + struct dwarf_cie *cie, + struct dwarf_fde *fde, + struct dwarf_frame *frame, + unsigned long pc) +{ + unsigned char insn; + unsigned char *current_insn; + unsigned int count, delta, reg, expr_len, offset; + struct dwarf_reg *regp; + + current_insn = insn_start; + + while (current_insn < insn_end && frame->pc <= pc) { + insn = __raw_readb(current_insn++); + + /* + * Firstly, handle the opcodes that embed their operands + * in the instructions. + */ + switch (DW_CFA_opcode(insn)) { + case DW_CFA_advance_loc: + delta = DW_CFA_operand(insn); + delta *= cie->code_alignment_factor; + frame->pc += delta; + continue; + /* NOTREACHED */ + case DW_CFA_offset: + reg = DW_CFA_operand(insn); + count = dwarf_read_uleb128(current_insn, &offset); + current_insn += count; + offset *= cie->data_alignment_factor; + regp = dwarf_frame_alloc_reg(frame, reg); + regp->addr = offset; + regp->flags |= DWARF_REG_OFFSET; + continue; + /* NOTREACHED */ + case DW_CFA_restore: + reg = DW_CFA_operand(insn); + continue; + /* NOTREACHED */ + } + + /* + * Secondly, handle the opcodes that don't embed their + * operands in the instruction. + */ + switch (insn) { + case DW_CFA_nop: + continue; + case DW_CFA_advance_loc1: + delta = *current_insn++; + frame->pc += delta * cie->code_alignment_factor; + break; + case DW_CFA_advance_loc2: + delta = get_unaligned((u16 *)current_insn); + current_insn += 2; + frame->pc += delta * cie->code_alignment_factor; + break; + case DW_CFA_advance_loc4: + delta = get_unaligned((u32 *)current_insn); + current_insn += 4; + frame->pc += delta * cie->code_alignment_factor; + break; + case DW_CFA_offset_extended: + count = dwarf_read_uleb128(current_insn, ®); + current_insn += count; + count = dwarf_read_uleb128(current_insn, &offset); + current_insn += count; + offset *= cie->data_alignment_factor; + break; + case DW_CFA_restore_extended: + count = dwarf_read_uleb128(current_insn, ®); + current_insn += count; + break; + case DW_CFA_undefined: + count = dwarf_read_uleb128(current_insn, ®); + current_insn += count; + regp = dwarf_frame_alloc_reg(frame, reg); + regp->flags |= DWARF_UNDEFINED; + break; + case DW_CFA_def_cfa: + count = dwarf_read_uleb128(current_insn, + &frame->cfa_register); + current_insn += count; + count = dwarf_read_uleb128(current_insn, + &frame->cfa_offset); + current_insn += count; + + frame->flags |= DWARF_FRAME_CFA_REG_OFFSET; + break; + case DW_CFA_def_cfa_register: + count = dwarf_read_uleb128(current_insn, + &frame->cfa_register); + current_insn += count; + frame->flags |= DWARF_FRAME_CFA_REG_OFFSET; + break; + case DW_CFA_def_cfa_offset: + count = dwarf_read_uleb128(current_insn, &offset); + current_insn += count; + frame->cfa_offset = offset; + break; + case DW_CFA_def_cfa_expression: + count = dwarf_read_uleb128(current_insn, &expr_len); + current_insn += count; + + frame->cfa_expr = current_insn; + frame->cfa_expr_len = expr_len; + current_insn += expr_len; + + frame->flags |= DWARF_FRAME_CFA_REG_EXP; + break; + case DW_CFA_offset_extended_sf: + count = dwarf_read_uleb128(current_insn, ®); + current_insn += count; + count = dwarf_read_leb128(current_insn, &offset); + current_insn += count; + offset *= cie->data_alignment_factor; + regp = dwarf_frame_alloc_reg(frame, reg); + regp->flags |= DWARF_REG_OFFSET; + regp->addr = offset; + break; + case DW_CFA_val_offset: + count = dwarf_read_uleb128(current_insn, ®); + current_insn += count; + count = dwarf_read_leb128(current_insn, &offset); + offset *= cie->data_alignment_factor; + regp = dwarf_frame_alloc_reg(frame, reg); + regp->flags |= DWARF_VAL_OFFSET; + regp->addr = offset; + break; + case DW_CFA_GNU_args_size: + count = dwarf_read_uleb128(current_insn, &offset); + current_insn += count; + break; + case DW_CFA_GNU_negative_offset_extended: + count = dwarf_read_uleb128(current_insn, ®); + current_insn += count; + count = dwarf_read_uleb128(current_insn, &offset); + offset *= cie->data_alignment_factor; + + regp = dwarf_frame_alloc_reg(frame, reg); + regp->flags |= DWARF_REG_OFFSET; + regp->addr = -offset; + break; + default: + pr_debug("unhandled DWARF instruction 0x%x\n", insn); + UNWINDER_BUG(); + break; + } + } + + return 0; +} + +/** + * dwarf_unwind_stack - recursively unwind the stack + * @pc: address of the function to unwind + * @prev: struct dwarf_frame of the previous stackframe on the callstack + * + * Return a struct dwarf_frame representing the most recent frame + * on the callstack. Each of the lower (older) stack frames are + * linked via the "prev" member. + */ +struct dwarf_frame * dwarf_unwind_stack(unsigned long pc, + struct dwarf_frame *prev) +{ + struct dwarf_frame *frame; + struct dwarf_cie *cie; + struct dwarf_fde *fde; + struct dwarf_reg *reg; + unsigned long addr; + + /* + * If this is the first invocation of this recursive function we + * need get the contents of a physical register to get the CFA + * in order to begin the virtual unwinding of the stack. + * + * NOTE: the return address is guaranteed to be setup by the + * time this function makes its first function call. + */ + if (!pc && !prev) + pc = (unsigned long)current_text_addr(); + + frame = mempool_alloc(dwarf_frame_pool, GFP_ATOMIC); + if (!frame) { + printk(KERN_ERR "Unable to allocate a dwarf frame\n"); + UNWINDER_BUG(); + } + + INIT_LIST_HEAD(&frame->reg_list); + frame->flags = 0; + frame->prev = prev; + frame->return_addr = 0; + + fde = dwarf_lookup_fde(pc); + if (!fde) { + /* + * This is our normal exit path - the one that stops the + * recursion. There's two reasons why we might exit + * here, + * + * a) pc has no asscociated DWARF frame info and so + * we don't know how to unwind this frame. This is + * usually the case when we're trying to unwind a + * frame that was called from some assembly code + * that has no DWARF info, e.g. syscalls. + * + * b) the DEBUG info for pc is bogus. There's + * really no way to distinguish this case from the + * case above, which sucks because we could print a + * warning here. + */ + goto bail; + } + + cie = dwarf_lookup_cie(fde->cie_pointer); + + frame->pc = fde->initial_location; + + /* CIE initial instructions */ + dwarf_cfa_execute_insns(cie->initial_instructions, + cie->instructions_end, cie, fde, + frame, pc); + + /* FDE instructions */ + dwarf_cfa_execute_insns(fde->instructions, fde->end, cie, + fde, frame, pc); + + /* Calculate the CFA */ + switch (frame->flags) { + case DWARF_FRAME_CFA_REG_OFFSET: + if (prev) { + reg = dwarf_frame_reg(prev, frame->cfa_register); + UNWINDER_BUG_ON(!reg); + UNWINDER_BUG_ON(reg->flags != DWARF_REG_OFFSET); + + addr = prev->cfa + reg->addr; + frame->cfa = __raw_readl(addr); + + } else { + /* + * Again, this is the first invocation of this + * recurisve function. We need to physically + * read the contents of a register in order to + * get the Canonical Frame Address for this + * function. + */ + frame->cfa = dwarf_read_arch_reg(frame->cfa_register); + } + + frame->cfa += frame->cfa_offset; + break; + default: + UNWINDER_BUG(); + } + + reg = dwarf_frame_reg(frame, DWARF_ARCH_RA_REG); + + /* + * If we haven't seen the return address register or the return + * address column is undefined then we must assume that this is + * the end of the callstack. + */ + if (!reg || reg->flags == DWARF_UNDEFINED) + goto bail; + + UNWINDER_BUG_ON(reg->flags != DWARF_REG_OFFSET); + + addr = frame->cfa + reg->addr; + frame->return_addr = __raw_readl(addr); + + return frame; + +bail: + dwarf_frame_free_regs(frame); + mempool_free(frame, dwarf_frame_pool); + return NULL; +} + +static int dwarf_parse_cie(void *entry, void *p, unsigned long len, + unsigned char *end) +{ + struct dwarf_cie *cie; + unsigned long flags; + int count; + + cie = kzalloc(sizeof(*cie), GFP_KERNEL); + if (!cie) + return -ENOMEM; + + cie->length = len; + + /* + * Record the offset into the .eh_frame section + * for this CIE. It allows this CIE to be + * quickly and easily looked up from the + * corresponding FDE. + */ + cie->cie_pointer = (unsigned long)entry; + + cie->version = *(char *)p++; + UNWINDER_BUG_ON(cie->version != 1); + + cie->augmentation = p; + p += strlen(cie->augmentation) + 1; + + count = dwarf_read_uleb128(p, &cie->code_alignment_factor); + p += count; + + count = dwarf_read_leb128(p, &cie->data_alignment_factor); + p += count; + + /* + * Which column in the rule table contains the + * return address? + */ + if (cie->version == 1) { + cie->return_address_reg = __raw_readb(p); + p++; + } else { + count = dwarf_read_uleb128(p, &cie->return_address_reg); + p += count; + } + + if (cie->augmentation[0] == 'z') { + unsigned int length, count; + cie->flags |= DWARF_CIE_Z_AUGMENTATION; + + count = dwarf_read_uleb128(p, &length); + p += count; + + UNWINDER_BUG_ON((unsigned char *)p > end); + + cie->initial_instructions = p + length; + cie->augmentation++; + } + + while (*cie->augmentation) { + /* + * "L" indicates a byte showing how the + * LSDA pointer is encoded. Skip it. + */ + if (*cie->augmentation == 'L') { + p++; + cie->augmentation++; + } else if (*cie->augmentation == 'R') { + /* + * "R" indicates a byte showing + * how FDE addresses are + * encoded. + */ + cie->encoding = *(char *)p++; + cie->augmentation++; + } else if (*cie->augmentation == 'P') { + /* + * "R" indicates a personality + * routine in the CIE + * augmentation. + */ + UNWINDER_BUG(); + } else if (*cie->augmentation == 'S') { + UNWINDER_BUG(); + } else { + /* + * Unknown augmentation. Assume + * 'z' augmentation. + */ + p = cie->initial_instructions; + UNWINDER_BUG_ON(!p); + break; + } + } + + cie->initial_instructions = p; + cie->instructions_end = end; + + /* Add to list */ + spin_lock_irqsave(&dwarf_cie_lock, flags); + list_add_tail(&cie->link, &dwarf_cie_list); + spin_unlock_irqrestore(&dwarf_cie_lock, flags); + + return 0; +} + +static int dwarf_parse_fde(void *entry, u32 entry_type, + void *start, unsigned long len, + unsigned char *end) +{ + struct dwarf_fde *fde; + struct dwarf_cie *cie; + unsigned long flags; + int count; + void *p = start; + + fde = kzalloc(sizeof(*fde), GFP_KERNEL); + if (!fde) + return -ENOMEM; + + fde->length = len; + + /* + * In a .eh_frame section the CIE pointer is the + * delta between the address within the FDE + */ + fde->cie_pointer = (unsigned long)(p - entry_type - 4); + + cie = dwarf_lookup_cie(fde->cie_pointer); + fde->cie = cie; + + if (cie->encoding) + count = dwarf_read_encoded_value(p, &fde->initial_location, + cie->encoding); + else + count = dwarf_read_addr(p, &fde->initial_location); + + p += count; + + if (cie->encoding) + count = dwarf_read_encoded_value(p, &fde->address_range, + cie->encoding & 0x0f); + else + count = dwarf_read_addr(p, &fde->address_range); + + p += count; + + if (fde->cie->flags & DWARF_CIE_Z_AUGMENTATION) { + unsigned int length; + count = dwarf_read_uleb128(p, &length); + p += count + length; + } + + /* Call frame instructions. */ + fde->instructions = p; + fde->end = end; + + /* Add to list. */ + spin_lock_irqsave(&dwarf_fde_lock, flags); + list_add_tail(&fde->link, &dwarf_fde_list); + spin_unlock_irqrestore(&dwarf_fde_lock, flags); + + return 0; +} + +static void dwarf_unwinder_dump(struct task_struct *task, + struct pt_regs *regs, + unsigned long *sp, + const struct stacktrace_ops *ops, + void *data) +{ + struct dwarf_frame *frame, *_frame; + unsigned long return_addr; + + _frame = NULL; + return_addr = 0; + + while (1) { + frame = dwarf_unwind_stack(return_addr, _frame); + + if (_frame) { + dwarf_frame_free_regs(_frame); + mempool_free(_frame, dwarf_frame_pool); + } + + _frame = frame; + + if (!frame || !frame->return_addr) + break; + + return_addr = frame->return_addr; + ops->address(data, return_addr, 1); + } +} + +static struct unwinder dwarf_unwinder = { + .name = "dwarf-unwinder", + .dump = dwarf_unwinder_dump, + .rating = 150, +}; + +static void dwarf_unwinder_cleanup(void) +{ + struct dwarf_cie *cie; + struct dwarf_fde *fde; + + /* + * Deallocate all the memory allocated for the DWARF unwinder. + * Traverse all the FDE/CIE lists and remove and free all the + * memory associated with those data structures. + */ + list_for_each_entry(cie, &dwarf_cie_list, link) + kfree(cie); + + list_for_each_entry(fde, &dwarf_fde_list, link) + kfree(fde); + + kmem_cache_destroy(dwarf_reg_cachep); + kmem_cache_destroy(dwarf_frame_cachep); +} + +/** + * dwarf_unwinder_init - initialise the dwarf unwinder + * + * Build the data structures describing the .dwarf_frame section to + * make it easier to lookup CIE and FDE entries. Because the + * .eh_frame section is packed as tightly as possible it is not + * easy to lookup the FDE for a given PC, so we build a list of FDE + * and CIE entries that make it easier. + */ +static int __init dwarf_unwinder_init(void) +{ + u32 entry_type; + void *p, *entry; + int count, err = 0; + unsigned long len; + unsigned int c_entries, f_entries; + unsigned char *end; + INIT_LIST_HEAD(&dwarf_cie_list); + INIT_LIST_HEAD(&dwarf_fde_list); + + c_entries = 0; + f_entries = 0; + entry = &__start_eh_frame; + + dwarf_frame_cachep = kmem_cache_create("dwarf_frames", + sizeof(struct dwarf_frame), 0, + SLAB_PANIC | SLAB_HWCACHE_ALIGN | SLAB_NOTRACK, NULL); + + dwarf_reg_cachep = kmem_cache_create("dwarf_regs", + sizeof(struct dwarf_reg), 0, + SLAB_PANIC | SLAB_HWCACHE_ALIGN | SLAB_NOTRACK, NULL); + + dwarf_frame_pool = mempool_create(DWARF_FRAME_MIN_REQ, + mempool_alloc_slab, + mempool_free_slab, + dwarf_frame_cachep); + + dwarf_reg_pool = mempool_create(DWARF_REG_MIN_REQ, + mempool_alloc_slab, + mempool_free_slab, + dwarf_reg_cachep); + + while ((char *)entry < __stop_eh_frame) { + p = entry; + + count = dwarf_entry_len(p, &len); + if (count == 0) { + /* + * We read a bogus length field value. There is + * nothing we can do here apart from disabling + * the DWARF unwinder. We can't even skip this + * entry and move to the next one because 'len' + * tells us where our next entry is. + */ + goto out; + } else + p += count; + + /* initial length does not include itself */ + end = p + len; + + entry_type = get_unaligned((u32 *)p); + p += 4; + + if (entry_type == DW_EH_FRAME_CIE) { + err = dwarf_parse_cie(entry, p, len, end); + if (err < 0) + goto out; + else + c_entries++; + } else { + err = dwarf_parse_fde(entry, entry_type, p, len, end); + if (err < 0) + goto out; + else + f_entries++; + } + + entry = (char *)entry + len + 4; + } + + printk(KERN_INFO "DWARF unwinder initialised: read %u CIEs, %u FDEs\n", + c_entries, f_entries); + + err = unwinder_register(&dwarf_unwinder); + if (err) + goto out; + + return 0; + +out: + printk(KERN_ERR "Failed to initialise DWARF unwinder: %d\n", err); + dwarf_unwinder_cleanup(); + return -EINVAL; +} +early_initcall(dwarf_unwinder_init); diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c index a952dcf9999d..81a46145ffa5 100644 --- a/arch/sh/kernel/early_printk.c +++ b/arch/sh/kernel/early_printk.c @@ -134,7 +134,7 @@ static void scif_sercon_init(char *s) sci_out(&scif_port, SCFCR, 0x0030); /* TTRG=b'11 */ sci_out(&scif_port, SCSCR, 0x0030); /* TE, RE */ } -#elif defined(CONFIG_CPU_SH4) +#elif defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SH3) #define DEFAULT_BAUD 115200 /* * Simple SCIF init, primarily aimed at SH7750 and other similar SH-4 @@ -220,8 +220,7 @@ static int __init setup_early_printk(char *buf) early_console = &scif_console; #if !defined(CONFIG_SH_STANDARD_BIOS) -#if defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SH3) scif_sercon_init(buf + 6); #endif #endif diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S index d62359cfbbe2..68d9223b145e 100644 --- a/arch/sh/kernel/entry-common.S +++ b/arch/sh/kernel/entry-common.S @@ -43,9 +43,10 @@ * syscall # * */ +#include <asm/dwarf.h> #if defined(CONFIG_PREEMPT) -# define preempt_stop() cli +# define preempt_stop() cli ; TRACE_IRQS_OFF #else # define preempt_stop() # define resume_kernel __restore_all @@ -55,11 +56,7 @@ .align 2 ENTRY(exception_error) ! -#ifdef CONFIG_TRACE_IRQFLAGS - mov.l 2f, r0 - jsr @r0 - nop -#endif + TRACE_IRQS_ON sti mov.l 1f, r0 jmp @r0 @@ -67,18 +64,15 @@ ENTRY(exception_error) .align 2 1: .long do_exception_error -#ifdef CONFIG_TRACE_IRQFLAGS -2: .long trace_hardirqs_on -#endif .align 2 ret_from_exception: + CFI_STARTPROC simple + CFI_DEF_CFA r14, 0 + CFI_REL_OFFSET 17, 64 + CFI_REL_OFFSET 15, 0 + CFI_REL_OFFSET 14, 56 preempt_stop() -#ifdef CONFIG_TRACE_IRQFLAGS - mov.l 4f, r0 - jsr @r0 - nop -#endif ENTRY(ret_from_irq) ! mov #OFF_SR, r0 @@ -93,6 +87,7 @@ ENTRY(ret_from_irq) nop ENTRY(resume_kernel) cli + TRACE_IRQS_OFF mov.l @(TI_PRE_COUNT,r8), r0 ! current_thread_info->preempt_count tst r0, r0 bf noresched @@ -103,8 +98,9 @@ need_resched: mov #OFF_SR, r0 mov.l @(r0,r15), r0 ! get status register - and #0xf0, r0 ! interrupts off (exception path)? - cmp/eq #0xf0, r0 + shlr r0 + and #(0xf0>>1), r0 ! interrupts off (exception path)? + cmp/eq #(0xf0>>1), r0 bt noresched mov.l 3f, r0 jsr @r0 ! call preempt_schedule_irq @@ -125,13 +121,9 @@ noresched: ENTRY(resume_userspace) ! r8: current_thread_info cli -#ifdef CONFIG_TRACE_IRQFLAGS - mov.l 5f, r0 - jsr @r0 - nop -#endif + TRACE_IRQS_OfF mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags - tst #_TIF_WORK_MASK, r0 + tst #(_TIF_WORK_MASK & 0xff), r0 bt/s __restore_all tst #_TIF_NEED_RESCHED, r0 @@ -156,14 +148,10 @@ work_resched: jsr @r1 ! schedule nop cli -#ifdef CONFIG_TRACE_IRQFLAGS - mov.l 5f, r0 - jsr @r0 - nop -#endif + TRACE_IRQS_OFF ! mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags - tst #_TIF_WORK_MASK, r0 + tst #(_TIF_WORK_MASK & 0xff), r0 bt __restore_all bra work_pending tst #_TIF_NEED_RESCHED, r0 @@ -172,23 +160,15 @@ work_resched: 1: .long schedule 2: .long do_notify_resume 3: .long resume_userspace -#ifdef CONFIG_TRACE_IRQFLAGS -4: .long trace_hardirqs_on -5: .long trace_hardirqs_off -#endif .align 2 syscall_exit_work: ! r0: current_thread_info->flags ! r8: current_thread_info - tst #_TIF_WORK_SYSCALL_MASK, r0 + tst #(_TIF_WORK_SYSCALL_MASK & 0xff), r0 bt/s work_pending tst #_TIF_NEED_RESCHED, r0 -#ifdef CONFIG_TRACE_IRQFLAGS - mov.l 5f, r0 - jsr @r0 - nop -#endif + TRACE_IRQS_ON sti mov r15, r4 mov.l 8f, r0 ! do_syscall_trace_leave @@ -226,12 +206,25 @@ syscall_trace_entry: mov.l r0, @(OFF_R0,r15) ! Return value __restore_all: - mov.l 1f, r0 + mov #OFF_SR, r0 + mov.l @(r0,r15), r0 ! get status register + + shlr2 r0 + and #0x3c, r0 + cmp/eq #0x3c, r0 + bt 1f + TRACE_IRQS_ON + bra 2f + nop +1: + TRACE_IRQS_OFF +2: + mov.l 3f, r0 jmp @r0 nop .align 2 -1: .long restore_all +3: .long restore_all .align 2 syscall_badsys: ! Bad syscall number @@ -259,6 +252,7 @@ debug_trap: nop bra __restore_all nop + CFI_ENDPROC .align 2 1: .long debug_trap_table @@ -304,6 +298,7 @@ ret_from_fork: * system calls and debug traps through their respective jump tables. */ ENTRY(system_call) + setup_frame_reg #if !defined(CONFIG_CPU_SH2) mov.l 1f, r9 mov.l @r9, r8 ! Read from TRA (Trap Address) Register @@ -321,18 +316,18 @@ ENTRY(system_call) bt/s debug_trap ! it's a debug trap.. nop -#ifdef CONFIG_TRACE_IRQFLAGS - mov.l 5f, r10 - jsr @r10 - nop -#endif + TRACE_IRQS_ON sti ! get_current_thread_info r8, r10 mov.l @(TI_FLAGS,r8), r8 - mov #_TIF_WORK_SYSCALL_MASK, r10 + mov #(_TIF_WORK_SYSCALL_MASK & 0xff), r10 + mov #(_TIF_WORK_SYSCALL_MASK >> 8), r9 tst r10, r8 + shll8 r9 + bf syscall_trace_entry + tst r9, r8 bf syscall_trace_entry ! mov.l 2f, r8 ! Number of syscalls @@ -351,15 +346,15 @@ syscall_call: ! syscall_exit: cli -#ifdef CONFIG_TRACE_IRQFLAGS - mov.l 6f, r0 - jsr @r0 - nop -#endif + TRACE_IRQS_OFF ! get_current_thread_info r8, r0 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags - tst #_TIF_ALLWORK_MASK, r0 + tst #(_TIF_ALLWORK_MASK & 0xff), r0 + mov #(_TIF_ALLWORK_MASK >> 8), r1 + bf syscall_exit_work + shlr8 r0 + tst r0, r1 bf syscall_exit_work bra __restore_all nop @@ -369,9 +364,5 @@ syscall_exit: #endif 2: .long NR_syscalls 3: .long sys_call_table -#ifdef CONFIG_TRACE_IRQFLAGS -5: .long trace_hardirqs_on -6: .long trace_hardirqs_off -#endif 7: .long do_syscall_trace_enter 8: .long do_syscall_trace_leave diff --git a/arch/sh/kernel/ftrace.c b/arch/sh/kernel/ftrace.c index 066f37dc32a9..a3dcc6d5d253 100644 --- a/arch/sh/kernel/ftrace.c +++ b/arch/sh/kernel/ftrace.c @@ -16,9 +16,13 @@ #include <linux/string.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/kernel.h> #include <asm/ftrace.h> #include <asm/cacheflush.h> +#include <asm/unistd.h> +#include <trace/syscall.h> +#ifdef CONFIG_DYNAMIC_FTRACE static unsigned char ftrace_replaced_code[MCOUNT_INSN_SIZE]; static unsigned char ftrace_nop[4]; @@ -131,3 +135,187 @@ int __init ftrace_dyn_arch_init(void *data) return 0; } +#endif /* CONFIG_DYNAMIC_FTRACE */ + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER +#ifdef CONFIG_DYNAMIC_FTRACE +extern void ftrace_graph_call(void); + +static int ftrace_mod(unsigned long ip, unsigned long old_addr, + unsigned long new_addr) +{ + unsigned char code[MCOUNT_INSN_SIZE]; + + if (probe_kernel_read(code, (void *)ip, MCOUNT_INSN_SIZE)) + return -EFAULT; + + if (old_addr != __raw_readl((unsigned long *)code)) + return -EINVAL; + + __raw_writel(new_addr, ip); + return 0; +} + +int ftrace_enable_ftrace_graph_caller(void) +{ + unsigned long ip, old_addr, new_addr; + + ip = (unsigned long)(&ftrace_graph_call) + GRAPH_INSN_OFFSET; + old_addr = (unsigned long)(&skip_trace); + new_addr = (unsigned long)(&ftrace_graph_caller); + + return ftrace_mod(ip, old_addr, new_addr); +} + +int ftrace_disable_ftrace_graph_caller(void) +{ + unsigned long ip, old_addr, new_addr; + + ip = (unsigned long)(&ftrace_graph_call) + GRAPH_INSN_OFFSET; + old_addr = (unsigned long)(&ftrace_graph_caller); + new_addr = (unsigned long)(&skip_trace); + + return ftrace_mod(ip, old_addr, new_addr); +} +#endif /* CONFIG_DYNAMIC_FTRACE */ + +/* + * Hook the return address and push it in the stack of return addrs + * in the current thread info. + * + * This is the main routine for the function graph tracer. The function + * graph tracer essentially works like this: + * + * parent is the stack address containing self_addr's return address. + * We pull the real return address out of parent and store it in + * current's ret_stack. Then, we replace the return address on the stack + * with the address of return_to_handler. self_addr is the function that + * called mcount. + * + * When self_addr returns, it will jump to return_to_handler which calls + * ftrace_return_to_handler. ftrace_return_to_handler will pull the real + * return address off of current's ret_stack and jump to it. + */ +void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) +{ + unsigned long old; + int faulted, err; + struct ftrace_graph_ent trace; + unsigned long return_hooker = (unsigned long)&return_to_handler; + + if (unlikely(atomic_read(¤t->tracing_graph_pause))) + return; + + /* + * Protect against fault, even if it shouldn't + * happen. This tool is too much intrusive to + * ignore such a protection. + */ + __asm__ __volatile__( + "1: \n\t" + "mov.l @%2, %0 \n\t" + "2: \n\t" + "mov.l %3, @%2 \n\t" + "mov #0, %1 \n\t" + "3: \n\t" + ".section .fixup, \"ax\" \n\t" + "4: \n\t" + "mov.l 5f, %0 \n\t" + "jmp @%0 \n\t" + " mov #1, %1 \n\t" + ".balign 4 \n\t" + "5: .long 3b \n\t" + ".previous \n\t" + ".section __ex_table,\"a\" \n\t" + ".long 1b, 4b \n\t" + ".long 2b, 4b \n\t" + ".previous \n\t" + : "=&r" (old), "=r" (faulted) + : "r" (parent), "r" (return_hooker) + ); + + if (unlikely(faulted)) { + ftrace_graph_stop(); + WARN_ON(1); + return; + } + + err = ftrace_push_return_trace(old, self_addr, &trace.depth, 0); + if (err == -EBUSY) { + __raw_writel(old, parent); + return; + } + + trace.func = self_addr; + + /* Only trace if the calling function expects to */ + if (!ftrace_graph_entry(&trace)) { + current->curr_ret_stack--; + __raw_writel(old, parent); + } +} +#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ + +#ifdef CONFIG_FTRACE_SYSCALLS + +extern unsigned long __start_syscalls_metadata[]; +extern unsigned long __stop_syscalls_metadata[]; +extern unsigned long *sys_call_table; + +static struct syscall_metadata **syscalls_metadata; + +static struct syscall_metadata *find_syscall_meta(unsigned long *syscall) +{ + struct syscall_metadata *start; + struct syscall_metadata *stop; + char str[KSYM_SYMBOL_LEN]; + + + start = (struct syscall_metadata *)__start_syscalls_metadata; + stop = (struct syscall_metadata *)__stop_syscalls_metadata; + kallsyms_lookup((unsigned long) syscall, NULL, NULL, NULL, str); + + for ( ; start < stop; start++) { + if (start->name && !strcmp(start->name, str)) + return start; + } + + return NULL; +} + +struct syscall_metadata *syscall_nr_to_meta(int nr) +{ + if (!syscalls_metadata || nr >= FTRACE_SYSCALL_MAX || nr < 0) + return NULL; + + return syscalls_metadata[nr]; +} + +void arch_init_ftrace_syscalls(void) +{ + int i; + struct syscall_metadata *meta; + unsigned long **psys_syscall_table = &sys_call_table; + static atomic_t refs; + + if (atomic_inc_return(&refs) != 1) + goto end; + + syscalls_metadata = kzalloc(sizeof(*syscalls_metadata) * + FTRACE_SYSCALL_MAX, GFP_KERNEL); + if (!syscalls_metadata) { + WARN_ON(1); + return; + } + + for (i = 0; i < FTRACE_SYSCALL_MAX; i++) { + meta = find_syscall_meta(psys_syscall_table[i]); + syscalls_metadata[i] = meta; + } + return; + + /* Paranoid: avoid overflow */ +end: + atomic_dec(&refs); +} +#endif /* CONFIG_FTRACE_SYSCALLS */ diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c index 4f85fffaa557..4770c241c679 100644 --- a/arch/sh/kernel/io.c +++ b/arch/sh/kernel/io.c @@ -1,12 +1,9 @@ /* - * linux/arch/sh/kernel/io.c + * arch/sh/kernel/io.c - Machine independent I/O functions. * - * Copyright (C) 2000 Stuart Menefy + * Copyright (C) 2000 - 2009 Stuart Menefy * Copyright (C) 2005 Paul Mundt * - * Provide real functions which expand to whatever the header file defined. - * Also definitions of machine independent IO functions. - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -18,33 +15,87 @@ /* * Copy data from IO memory space to "real" memory space. - * This needs to be optimized. */ void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned long count) { - unsigned char *p = to; - while (count) { - count--; - *p = readb(from); - p++; - from++; - } + /* + * Would it be worthwhile doing byte and long transfers first + * to try and get aligned? + */ +#ifdef CONFIG_CPU_SH4 + if ((count >= 0x20) && + (((u32)to & 0x1f) == 0) && (((u32)from & 0x3) == 0)) { + int tmp2, tmp3, tmp4, tmp5, tmp6; + + __asm__ __volatile__( + "1: \n\t" + "mov.l @%7+, r0 \n\t" + "mov.l @%7+, %2 \n\t" + "movca.l r0, @%0 \n\t" + "mov.l @%7+, %3 \n\t" + "mov.l @%7+, %4 \n\t" + "mov.l @%7+, %5 \n\t" + "mov.l @%7+, %6 \n\t" + "mov.l @%7+, r7 \n\t" + "mov.l @%7+, r0 \n\t" + "mov.l %2, @(0x04,%0) \n\t" + "mov #0x20, %2 \n\t" + "mov.l %3, @(0x08,%0) \n\t" + "sub %2, %1 \n\t" + "mov.l %4, @(0x0c,%0) \n\t" + "cmp/hi %1, %2 ! T if 32 > count \n\t" + "mov.l %5, @(0x10,%0) \n\t" + "mov.l %6, @(0x14,%0) \n\t" + "mov.l r7, @(0x18,%0) \n\t" + "mov.l r0, @(0x1c,%0) \n\t" + "bf.s 1b \n\t" + " add #0x20, %0 \n\t" + : "=&r" (to), "=&r" (count), + "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4), + "=&r" (tmp5), "=&r" (tmp6), "=&r" (from) + : "7"(from), "0" (to), "1" (count) + : "r0", "r7", "t", "memory"); + } +#endif + + if ((((u32)to | (u32)from) & 0x3) == 0) { + for (; count > 3; count -= 4) { + *(u32 *)to = *(volatile u32 *)from; + to += 4; + from += 4; + } + } + + for (; count > 0; count--) { + *(u8 *)to = *(volatile u8 *)from; + to++; + from++; + } + + mb(); } EXPORT_SYMBOL(memcpy_fromio); /* * Copy data from "real" memory space to IO memory space. - * This needs to be optimized. */ void memcpy_toio(volatile void __iomem *to, const void *from, unsigned long count) { - const unsigned char *p = from; - while (count) { - count--; - writeb(*p, to); - p++; - to++; - } + if ((((u32)to | (u32)from) & 0x3) == 0) { + for ( ; count > 3; count -= 4) { + *(volatile u32 *)to = *(u32 *)from; + to += 4; + from += 4; + } + } + + for (; count > 0; count--) { + *(volatile u8 *)to = *(u8 *)from; + to++; + from++; + } + + mb(); } EXPORT_SYMBOL(memcpy_toio); @@ -62,6 +113,8 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count) } EXPORT_SYMBOL(memset_io); +#ifndef CONFIG_GENERIC_IOMAP + void __iomem *ioport_map(unsigned long port, unsigned int nr) { void __iomem *ret; @@ -79,3 +132,5 @@ void ioport_unmap(void __iomem *addr) sh_mv.mv_ioport_unmap(addr); } EXPORT_SYMBOL(ioport_unmap); + +#endif /* CONFIG_GENERIC_IOMAP */ diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c index 5a7f554d9ca1..4ff507239286 100644 --- a/arch/sh/kernel/io_generic.c +++ b/arch/sh/kernel/io_generic.c @@ -73,35 +73,19 @@ u32 generic_inl_p(unsigned long port) void generic_insb(unsigned long port, void *dst, unsigned long count) { - volatile u8 *port_addr; - u8 *buf = dst; - - port_addr = (volatile u8 __force *)__ioport_map(port, 1); - while (count--) - *buf++ = *port_addr; + __raw_readsb(__ioport_map(port, 1), dst, count); + dummy_read(); } void generic_insw(unsigned long port, void *dst, unsigned long count) { - volatile u16 *port_addr; - u16 *buf = dst; - - port_addr = (volatile u16 __force *)__ioport_map(port, 2); - while (count--) - *buf++ = *port_addr; - + __raw_readsw(__ioport_map(port, 2), dst, count); dummy_read(); } void generic_insl(unsigned long port, void *dst, unsigned long count) { - volatile u32 *port_addr; - u32 *buf = dst; - - port_addr = (volatile u32 __force *)__ioport_map(port, 4); - while (count--) - *buf++ = *port_addr; - + __raw_readsl(__ioport_map(port, 4), dst, count); dummy_read(); } @@ -145,37 +129,19 @@ void generic_outl_p(u32 b, unsigned long port) */ void generic_outsb(unsigned long port, const void *src, unsigned long count) { - volatile u8 *port_addr; - const u8 *buf = src; - - port_addr = (volatile u8 __force *)__ioport_map(port, 1); - - while (count--) - *port_addr = *buf++; + __raw_writesb(__ioport_map(port, 1), src, count); + dummy_read(); } void generic_outsw(unsigned long port, const void *src, unsigned long count) { - volatile u16 *port_addr; - const u16 *buf = src; - - port_addr = (volatile u16 __force *)__ioport_map(port, 2); - - while (count--) - *port_addr = *buf++; - + __raw_writesw(__ioport_map(port, 2), src, count); dummy_read(); } void generic_outsl(unsigned long port, const void *src, unsigned long count) { - volatile u32 *port_addr; - const u32 *buf = src; - - port_addr = (volatile u32 __force *)__ioport_map(port, 4); - while (count--) - *port_addr = *buf++; - + __raw_writesl(__ioport_map(port, 4), src, count); dummy_read(); } diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c index 77dfecb64373..69be603aa2d7 100644 --- a/arch/sh/kernel/io_trapped.c +++ b/arch/sh/kernel/io_trapped.c @@ -112,14 +112,15 @@ void __iomem *match_trapped_io_handler(struct list_head *list, struct trapped_io *tiop; struct resource *res; int k, len; + unsigned long flags; - spin_lock_irq(&trapped_lock); + spin_lock_irqsave(&trapped_lock, flags); list_for_each_entry(tiop, list, list) { voffs = 0; for (k = 0; k < tiop->num_resources; k++) { res = tiop->resource + k; if (res->start == offset) { - spin_unlock_irq(&trapped_lock); + spin_unlock_irqrestore(&trapped_lock, flags); return tiop->virt_base + voffs; } @@ -127,7 +128,7 @@ void __iomem *match_trapped_io_handler(struct list_head *list, voffs += roundup(len, PAGE_SIZE); } } - spin_unlock_irq(&trapped_lock); + spin_unlock_irqrestore(&trapped_lock, flags); return NULL; } EXPORT_SYMBOL_GPL(match_trapped_io_handler); @@ -283,7 +284,8 @@ int handle_trapped_io(struct pt_regs *regs, unsigned long address) return 0; } - tmp = handle_unaligned_access(instruction, regs, &trapped_io_access); + tmp = handle_unaligned_access(instruction, regs, + &trapped_io_access, 1); set_fs(oldfs); return tmp == 0; } diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c index 3d09062f4682..60f8af4497c7 100644 --- a/arch/sh/kernel/irq.c +++ b/arch/sh/kernel/irq.c @@ -114,24 +114,7 @@ asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs) #endif irq_enter(); - -#ifdef CONFIG_DEBUG_STACKOVERFLOW - /* Debugging check for stack overflow: is there less than 1KB free? */ - { - long sp; - - __asm__ __volatile__ ("and r15, %0" : - "=r" (sp) : "0" (THREAD_SIZE - 1)); - - if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { - printk("do_IRQ: stack overflow: %ld\n", - sp - sizeof(struct thread_info)); - dump_stack(); - } - } -#endif - - irq = irq_demux(intc_evt2irq(irq)); + irq = irq_demux(irq); #ifdef CONFIG_IRQSTACKS curctx = (union irq_ctx *)current_thread_info(); diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c index 305aad742aec..3e532d0d4a5c 100644 --- a/arch/sh/kernel/kgdb.c +++ b/arch/sh/kernel/kgdb.c @@ -15,8 +15,6 @@ #include <linux/io.h> #include <asm/cacheflush.h> -char in_nmi = 0; /* Set during NMI to prevent re-entry */ - /* Macros for single step instruction identification */ #define OPCODE_BT(op) (((op) & 0xff00) == 0x8900) #define OPCODE_BF(op) (((op) & 0xff00) == 0x8b00) @@ -195,8 +193,6 @@ void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) regs->gbr = gdb_regs[GDB_GBR]; regs->mach = gdb_regs[GDB_MACH]; regs->macl = gdb_regs[GDB_MACL]; - - __asm__ __volatile__ ("ldc %0, vbr" : : "r" (gdb_regs[GDB_VBR])); } void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) diff --git a/arch/sh/kernel/localtimer.c b/arch/sh/kernel/localtimer.c index 96e8eaea1e62..0b04e7d4a9b9 100644 --- a/arch/sh/kernel/localtimer.c +++ b/arch/sh/kernel/localtimer.c @@ -22,6 +22,7 @@ #include <linux/jiffies.h> #include <linux/percpu.h> #include <linux/clockchips.h> +#include <linux/hardirq.h> #include <linux/irq.h> static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); @@ -33,7 +34,9 @@ void local_timer_interrupt(void) { struct clock_event_device *clk = &__get_cpu_var(local_clockevent); + irq_enter(); clk->event_handler(clk); + irq_exit(); } static void dummy_timer_set_mode(enum clock_event_mode mode, @@ -46,8 +49,10 @@ void __cpuinit local_timer_setup(unsigned int cpu) struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); clk->name = "dummy_timer"; - clk->features = CLOCK_EVT_FEAT_DUMMY; - clk->rating = 200; + clk->features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_DUMMY; + clk->rating = 400; clk->mult = 1; clk->set_mode = dummy_timer_set_mode; clk->broadcast = smp_timer_broadcast; diff --git a/arch/sh/kernel/nmi_debug.c b/arch/sh/kernel/nmi_debug.c new file mode 100644 index 000000000000..ff0abbd1e652 --- /dev/null +++ b/arch/sh/kernel/nmi_debug.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/delay.h> +#include <linux/kdebug.h> +#include <linux/notifier.h> +#include <linux/sched.h> +#include <linux/hardirq.h> + +enum nmi_action { + NMI_SHOW_STATE = 1 << 0, + NMI_SHOW_REGS = 1 << 1, + NMI_DIE = 1 << 2, + NMI_DEBOUNCE = 1 << 3, +}; + +static unsigned long nmi_actions; + +static int nmi_debug_notify(struct notifier_block *self, + unsigned long val, void *data) +{ + struct die_args *args = data; + + if (likely(val != DIE_NMI)) + return NOTIFY_DONE; + + if (nmi_actions & NMI_SHOW_STATE) + show_state(); + if (nmi_actions & NMI_SHOW_REGS) + show_regs(args->regs); + if (nmi_actions & NMI_DEBOUNCE) + mdelay(10); + if (nmi_actions & NMI_DIE) + return NOTIFY_BAD; + + return NOTIFY_OK; +} + +static struct notifier_block nmi_debug_nb = { + .notifier_call = nmi_debug_notify, +}; + +static int __init nmi_debug_setup(char *str) +{ + char *p, *sep; + + register_die_notifier(&nmi_debug_nb); + + if (*str != '=') + return 0; + + for (p = str + 1; *p; p = sep + 1) { + sep = strchr(p, ','); + if (sep) + *sep = 0; + if (strcmp(p, "state") == 0) + nmi_actions |= NMI_SHOW_STATE; + else if (strcmp(p, "regs") == 0) + nmi_actions |= NMI_SHOW_REGS; + else if (strcmp(p, "debounce") == 0) + nmi_actions |= NMI_DEBOUNCE; + else if (strcmp(p, "die") == 0) + nmi_actions |= NMI_DIE; + else + printk(KERN_WARNING "NMI: Unrecognized action `%s'\n", + p); + if (!sep) + break; + } + + return 0; +} +__setup("nmi_debug", nmi_debug_setup); diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c index 92d7740faab1..0673c4746be3 100644 --- a/arch/sh/kernel/process_32.c +++ b/arch/sh/kernel/process_32.c @@ -23,6 +23,7 @@ #include <linux/tick.h> #include <linux/reboot.h> #include <linux/fs.h> +#include <linux/ftrace.h> #include <linux/preempt.h> #include <asm/uaccess.h> #include <asm/mmu_context.h> @@ -31,15 +32,35 @@ #include <asm/ubc.h> #include <asm/fpu.h> #include <asm/syscalls.h> +#include <asm/watchdog.h> int ubc_usercnt = 0; +#ifdef CONFIG_32BIT +static void watchdog_trigger_immediate(void) +{ + sh_wdt_write_cnt(0xFF); + sh_wdt_write_csr(0xC2); +} + +void machine_restart(char * __unused) +{ + local_irq_disable(); + + /* Use watchdog timer to trigger reset */ + watchdog_trigger_immediate(); + + while (1) + cpu_sleep(); +} +#else void machine_restart(char * __unused) { /* SR.BL=1 and invoke address error to let CPU reset (manual reset) */ asm volatile("ldc %0, sr\n\t" "mov.l @%1, %0" : : "r" (0x10000000), "r" (0x80000001)); } +#endif void machine_halt(void) { @@ -264,8 +285,8 @@ static void ubc_set_tracing(int asid, unsigned long pc) * switch_to(x,y) should switch tasks from x to y. * */ -struct task_struct *__switch_to(struct task_struct *prev, - struct task_struct *next) +__notrace_funcgraph struct task_struct * +__switch_to(struct task_struct *prev, struct task_struct *next) { #if defined(CONFIG_SH_FPU) unlazy_fpu(prev, task_pt_regs(prev)); diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c index 24de74214940..1192398ef582 100644 --- a/arch/sh/kernel/process_64.c +++ b/arch/sh/kernel/process_64.c @@ -425,7 +425,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, struct task_struct *p, struct pt_regs *regs) { struct pt_regs *childregs; - unsigned long long se; /* Sign extension */ #ifdef CONFIG_SH_FPU if(last_task_used_math == current) { @@ -441,11 +440,19 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, *childregs = *regs; + /* + * Sign extend the edited stack. + * Note that thread.pc and thread.pc will stay + * 32-bit wide and context switch must take care + * of NEFF sign extension. + */ if (user_mode(regs)) { - childregs->regs[15] = usp; + childregs->regs[15] = neff_sign_extend(usp); p->thread.uregs = childregs; } else { - childregs->regs[15] = (unsigned long)task_stack_page(p) + THREAD_SIZE; + childregs->regs[15] = + neff_sign_extend((unsigned long)task_stack_page(p) + + THREAD_SIZE); } childregs->regs[9] = 0; /* Set return value for child */ @@ -454,17 +461,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, p->thread.sp = (unsigned long) childregs; p->thread.pc = (unsigned long) ret_from_fork; - /* - * Sign extend the edited stack. - * Note that thread.pc and thread.pc will stay - * 32-bit wide and context switch must take care - * of NEFF sign extension. - */ - - se = childregs->regs[15]; - se = (se & NEFF_SIGN) ? (se | NEFF_MASK) : se; - childregs->regs[15] = se; - return 0; } diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c index 3392e835a374..9be35f348093 100644 --- a/arch/sh/kernel/ptrace_32.c +++ b/arch/sh/kernel/ptrace_32.c @@ -34,6 +34,9 @@ #include <asm/syscalls.h> #include <asm/fpu.h> +#define CREATE_TRACE_POINTS +#include <trace/events/syscalls.h> + /* * This routine will get a word off of the process kernel stack. */ @@ -459,6 +462,9 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs) */ ret = -1L; + if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) + trace_sys_enter(regs, regs->regs[0]); + if (unlikely(current->audit_context)) audit_syscall_entry(audit_arch(), regs->regs[3], regs->regs[4], regs->regs[5], @@ -475,6 +481,9 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs) audit_syscall_exit(AUDITSC_RESULT(regs->regs[0]), regs->regs[0]); + if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) + trace_sys_exit(regs, regs->regs[0]); + step = test_thread_flag(TIF_SINGLESTEP); if (step || test_thread_flag(TIF_SYSCALL_TRACE)) tracehook_report_syscall_exit(regs, step); diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c index 695097438f02..952da83903da 100644 --- a/arch/sh/kernel/ptrace_64.c +++ b/arch/sh/kernel/ptrace_64.c @@ -40,6 +40,9 @@ #include <asm/syscalls.h> #include <asm/fpu.h> +#define CREATE_TRACE_POINTS +#include <trace/events/syscalls.h> + /* This mask defines the bits of the SR which the user is not allowed to change, which are everything except S, Q, M, PR, SZ, FR. */ #define SR_MASK (0xffff8cfd) @@ -438,6 +441,9 @@ asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs) */ ret = -1LL; + if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) + trace_sys_enter(regs, regs->regs[9]); + if (unlikely(current->audit_context)) audit_syscall_entry(audit_arch(), regs->regs[1], regs->regs[2], regs->regs[3], @@ -452,6 +458,9 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs) audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]), regs->regs[9]); + if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) + trace_sys_exit(regs, regs->regs[9]); + if (test_thread_flag(TIF_SYSCALL_TRACE)) tracehook_report_syscall_exit(regs, 0); } diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index dd38338553ef..f9d44f8e0df6 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -30,6 +30,7 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/platform_device.h> +#include <linux/lmb.h> #include <asm/uaccess.h> #include <asm/io.h> #include <asm/page.h> @@ -48,6 +49,7 @@ struct sh_cpuinfo cpu_data[NR_CPUS] __read_mostly = { [0] = { .type = CPU_SH_NONE, + .family = CPU_FAMILY_UNKNOWN, .loops_per_jiffy = 10000000, }, }; @@ -233,39 +235,45 @@ void __init __add_active_range(unsigned int nid, unsigned long start_pfn, void __init setup_bootmem_allocator(unsigned long free_pfn) { unsigned long bootmap_size; + unsigned long bootmap_pages, bootmem_paddr; + u64 total_pages = (lmb_end_of_DRAM() - __MEMORY_START) >> PAGE_SHIFT; + int i; + + bootmap_pages = bootmem_bootmap_pages(total_pages); + + bootmem_paddr = lmb_alloc(bootmap_pages << PAGE_SHIFT, PAGE_SIZE); /* * Find a proper area for the bootmem bitmap. After this * bootstrap step all allocations (until the page allocator * is intact) must be done via bootmem_alloc(). */ - bootmap_size = init_bootmem_node(NODE_DATA(0), free_pfn, + bootmap_size = init_bootmem_node(NODE_DATA(0), + bootmem_paddr >> PAGE_SHIFT, min_low_pfn, max_low_pfn); - __add_active_range(0, min_low_pfn, max_low_pfn); - register_bootmem_low_pages(); - - node_set_online(0); + /* Add active regions with valid PFNs. */ + for (i = 0; i < lmb.memory.cnt; i++) { + unsigned long start_pfn, end_pfn; + start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT; + end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i); + __add_active_range(0, start_pfn, end_pfn); + } /* - * Reserve the kernel text and - * Reserve the bootmem bitmap. We do this in two steps (first step - * was init_bootmem()), because this catches the (definitely buggy) - * case of us accidentally initializing the bootmem allocator with - * an invalid RAM area. + * Add all physical memory to the bootmem map and mark each + * area as present. */ - reserve_bootmem(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET, - (PFN_PHYS(free_pfn) + bootmap_size + PAGE_SIZE - 1) - - (__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET), - BOOTMEM_DEFAULT); + register_bootmem_low_pages(); - /* - * Reserve physical pages below CONFIG_ZERO_PAGE_OFFSET. - */ - if (CONFIG_ZERO_PAGE_OFFSET != 0) - reserve_bootmem(__MEMORY_START, CONFIG_ZERO_PAGE_OFFSET, + /* Reserve the sections we're already using. */ + for (i = 0; i < lmb.reserved.cnt; i++) + reserve_bootmem(lmb.reserved.region[i].base, + lmb_size_bytes(&lmb.reserved, i), BOOTMEM_DEFAULT); + node_set_online(0); + sparse_memory_present_with_active_regions(0); #ifdef CONFIG_BLK_DEV_INITRD @@ -296,12 +304,37 @@ void __init setup_bootmem_allocator(unsigned long free_pfn) static void __init setup_memory(void) { unsigned long start_pfn; + u64 base = min_low_pfn << PAGE_SHIFT; + u64 size = (max_low_pfn << PAGE_SHIFT) - base; /* * Partially used pages are not usable - thus * we are rounding upwards: */ start_pfn = PFN_UP(__pa(_end)); + + lmb_add(base, size); + + /* + * Reserve the kernel text and + * Reserve the bootmem bitmap. We do this in two steps (first step + * was init_bootmem()), because this catches the (definitely buggy) + * case of us accidentally initializing the bootmem allocator with + * an invalid RAM area. + */ + lmb_reserve(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET, + (PFN_PHYS(start_pfn) + PAGE_SIZE - 1) - + (__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET)); + + /* + * Reserve physical pages below CONFIG_ZERO_PAGE_OFFSET. + */ + if (CONFIG_ZERO_PAGE_OFFSET != 0) + lmb_reserve(__MEMORY_START, CONFIG_ZERO_PAGE_OFFSET); + + lmb_analyze(); + lmb_dump_all(); + setup_bootmem_allocator(start_pfn); } #else @@ -372,10 +405,14 @@ void __init setup_arch(char **cmdline_p) if (!memory_end) memory_end = memory_start + __MEMORY_SIZE; -#ifdef CONFIG_CMDLINE_BOOL +#ifdef CONFIG_CMDLINE_OVERWRITE strlcpy(command_line, CONFIG_CMDLINE, sizeof(command_line)); #else strlcpy(command_line, COMMAND_LINE, sizeof(command_line)); +#ifdef CONFIG_CMDLINE_EXTEND + strlcat(command_line, " ", sizeof(command_line)); + strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line)); +#endif #endif /* Save unparsed command line copy for /proc/cmdline */ @@ -402,6 +439,7 @@ void __init setup_arch(char **cmdline_p) nodes_clear(node_online_map); /* Setup bootmem with available RAM */ + lmb_init(); setup_memory(); sparse_init(); @@ -448,7 +486,7 @@ static const char *cpu_name[] = { [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785", - [CPU_SH7786] = "SH7786", + [CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757", [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3", [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c index fcc5de31f83b..8dbe26b17c44 100644 --- a/arch/sh/kernel/sh_ksyms_32.c +++ b/arch/sh/kernel/sh_ksyms_32.c @@ -101,20 +101,14 @@ EXPORT_SYMBOL(flush_cache_range); EXPORT_SYMBOL(flush_dcache_page); #endif -#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \ - (defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)) -EXPORT_SYMBOL(clear_user_page); -#endif - -#ifdef CONFIG_FUNCTION_TRACER -EXPORT_SYMBOL(mcount); +#ifdef CONFIG_MCOUNT +DECLARE_EXPORT(mcount); #endif EXPORT_SYMBOL(csum_partial); EXPORT_SYMBOL(csum_partial_copy_generic); #ifdef CONFIG_IPV6 EXPORT_SYMBOL(csum_ipv6_magic); #endif -EXPORT_SYMBOL(clear_page); EXPORT_SYMBOL(copy_page); EXPORT_SYMBOL(__clear_user); EXPORT_SYMBOL(_ebss); diff --git a/arch/sh/kernel/sh_ksyms_64.c b/arch/sh/kernel/sh_ksyms_64.c index f5bd156ea504..d008e17eb257 100644 --- a/arch/sh/kernel/sh_ksyms_64.c +++ b/arch/sh/kernel/sh_ksyms_64.c @@ -30,14 +30,6 @@ extern int dump_fpu(struct pt_regs *, elf_fpregset_t *); EXPORT_SYMBOL(dump_fpu); EXPORT_SYMBOL(kernel_thread); -#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) -EXPORT_SYMBOL(clear_user_page); -#endif - -#ifndef CONFIG_CACHE_OFF -EXPORT_SYMBOL(flush_dcache_page); -#endif - #ifdef CONFIG_VT EXPORT_SYMBOL(screen_info); #endif @@ -52,7 +44,6 @@ EXPORT_SYMBOL(__get_user_asm_l); EXPORT_SYMBOL(__get_user_asm_q); EXPORT_SYMBOL(__strnlen_user); EXPORT_SYMBOL(__strncpy_from_user); -EXPORT_SYMBOL(clear_page); EXPORT_SYMBOL(__clear_user); EXPORT_SYMBOL(copy_page); EXPORT_SYMBOL(__copy_user); diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c index 04a21883f327..6729703547a1 100644 --- a/arch/sh/kernel/signal_32.c +++ b/arch/sh/kernel/signal_32.c @@ -41,6 +41,16 @@ struct fdpic_func_descriptor { }; /* + * The following define adds a 64 byte gap between the signal + * stack frame and previous contents of the stack. This allows + * frame unwinding in a function epilogue but only if a frame + * pointer is used in the function. This is necessary because + * current gcc compilers (<4.3) do not generate unwind info on + * SH for function epilogues. + */ +#define UNWINDGUARD 64 + +/* * Atomically swap in the new signal mask, and wait for a signal. */ asmlinkage int @@ -327,7 +337,7 @@ get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size) sp = current->sas_ss_sp + current->sas_ss_size; } - return (void __user *)((sp - frame_size) & -8ul); + return (void __user *)((sp - (frame_size+UNWINDGUARD)) & -8ul); } /* These symbols are defined with the addresses in the vsyscall page. diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c index 9e5c9b1d7e98..74793c80a57a 100644 --- a/arch/sh/kernel/signal_64.c +++ b/arch/sh/kernel/signal_64.c @@ -561,13 +561,11 @@ static int setup_frame(int sig, struct k_sigaction *ka, /* Set up to return from userspace. If provided, use a stub already in userspace. */ if (ka->sa.sa_flags & SA_RESTORER) { - DEREF_REG_PR = (unsigned long) ka->sa.sa_restorer | 0x1; - /* * On SH5 all edited pointers are subject to NEFF */ - DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? - (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; + DEREF_REG_PR = neff_sign_extend((unsigned long) + ka->sa.sa_restorer | 0x1); } else { /* * Different approach on SH5. @@ -580,9 +578,8 @@ static int setup_frame(int sig, struct k_sigaction *ka, * . being code, linker turns ShMedia bit on, always * dereference index -1. */ - DEREF_REG_PR = (unsigned long) frame->retcode | 0x01; - DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? - (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; + DEREF_REG_PR = neff_sign_extend((unsigned long) + frame->retcode | 0x01); if (__copy_to_user(frame->retcode, (void *)((unsigned long)sa_default_restorer & (~1)), 16) != 0) @@ -596,9 +593,7 @@ static int setup_frame(int sig, struct k_sigaction *ka, * Set up registers for signal handler. * All edited pointers are subject to NEFF. */ - regs->regs[REG_SP] = (unsigned long) frame; - regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ? - (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP]; + regs->regs[REG_SP] = neff_sign_extend((unsigned long)frame); regs->regs[REG_ARG1] = signal; /* Arg for signal handler */ /* FIXME: @@ -613,8 +608,7 @@ static int setup_frame(int sig, struct k_sigaction *ka, regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->sc; regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->sc; - regs->pc = (unsigned long) ka->sa.sa_handler; - regs->pc = (regs->pc & NEFF_SIGN) ? (regs->pc | NEFF_MASK) : regs->pc; + regs->pc = neff_sign_extend((unsigned long)ka->sa.sa_handler); set_fs(USER_DS); @@ -676,13 +670,11 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, /* Set up to return from userspace. If provided, use a stub already in userspace. */ if (ka->sa.sa_flags & SA_RESTORER) { - DEREF_REG_PR = (unsigned long) ka->sa.sa_restorer | 0x1; - /* * On SH5 all edited pointers are subject to NEFF */ - DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? - (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; + DEREF_REG_PR = neff_sign_extend((unsigned long) + ka->sa.sa_restorer | 0x1); } else { /* * Different approach on SH5. @@ -695,15 +687,14 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, * . being code, linker turns ShMedia bit on, always * dereference index -1. */ - - DEREF_REG_PR = (unsigned long) frame->retcode | 0x01; - DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? - (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; + DEREF_REG_PR = neff_sign_extend((unsigned long) + frame->retcode | 0x01); if (__copy_to_user(frame->retcode, (void *)((unsigned long)sa_default_rt_restorer & (~1)), 16) != 0) goto give_sigsegv; + /* Cohere the trampoline with the I-cache. */ flush_icache_range(DEREF_REG_PR-1, DEREF_REG_PR-1+15); } @@ -711,14 +702,11 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, * Set up registers for signal handler. * All edited pointers are subject to NEFF. */ - regs->regs[REG_SP] = (unsigned long) frame; - regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ? - (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP]; + regs->regs[REG_SP] = neff_sign_extend((unsigned long)frame); regs->regs[REG_ARG1] = signal; /* Arg for signal handler */ regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->info; regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->uc.uc_mcontext; - regs->pc = (unsigned long) ka->sa.sa_handler; - regs->pc = (regs->pc & NEFF_SIGN) ? (regs->pc | NEFF_MASK) : regs->pc; + regs->pc = neff_sign_extend((unsigned long)ka->sa.sa_handler); set_fs(USER_DS); diff --git a/arch/sh/kernel/stacktrace.c b/arch/sh/kernel/stacktrace.c index 1a2a5eb76e41..c2e45c48409c 100644 --- a/arch/sh/kernel/stacktrace.c +++ b/arch/sh/kernel/stacktrace.c @@ -13,47 +13,93 @@ #include <linux/stacktrace.h> #include <linux/thread_info.h> #include <linux/module.h> +#include <asm/unwinder.h> #include <asm/ptrace.h> +#include <asm/stacktrace.h> + +static void save_stack_warning(void *data, char *msg) +{ +} + +static void +save_stack_warning_symbol(void *data, char *msg, unsigned long symbol) +{ +} + +static int save_stack_stack(void *data, char *name) +{ + return 0; +} /* * Save stack-backtrace addresses into a stack_trace buffer. */ +static void save_stack_address(void *data, unsigned long addr, int reliable) +{ + struct stack_trace *trace = data; + + if (!reliable) + return; + + if (trace->skip > 0) { + trace->skip--; + return; + } + + if (trace->nr_entries < trace->max_entries) + trace->entries[trace->nr_entries++] = addr; +} + +static const struct stacktrace_ops save_stack_ops = { + .warning = save_stack_warning, + .warning_symbol = save_stack_warning_symbol, + .stack = save_stack_stack, + .address = save_stack_address, +}; + void save_stack_trace(struct stack_trace *trace) { unsigned long *sp = (unsigned long *)current_stack_pointer; - while (!kstack_end(sp)) { - unsigned long addr = *sp++; - - if (__kernel_text_address(addr)) { - if (trace->skip > 0) - trace->skip--; - else - trace->entries[trace->nr_entries++] = addr; - if (trace->nr_entries >= trace->max_entries) - break; - } - } + unwind_stack(current, NULL, sp, &save_stack_ops, trace); + if (trace->nr_entries < trace->max_entries) + trace->entries[trace->nr_entries++] = ULONG_MAX; } EXPORT_SYMBOL_GPL(save_stack_trace); +static void +save_stack_address_nosched(void *data, unsigned long addr, int reliable) +{ + struct stack_trace *trace = (struct stack_trace *)data; + + if (!reliable) + return; + + if (in_sched_functions(addr)) + return; + + if (trace->skip > 0) { + trace->skip--; + return; + } + + if (trace->nr_entries < trace->max_entries) + trace->entries[trace->nr_entries++] = addr; +} + +static const struct stacktrace_ops save_stack_ops_nosched = { + .warning = save_stack_warning, + .warning_symbol = save_stack_warning_symbol, + .stack = save_stack_stack, + .address = save_stack_address_nosched, +}; + void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) { unsigned long *sp = (unsigned long *)tsk->thread.sp; - while (!kstack_end(sp)) { - unsigned long addr = *sp++; - - if (__kernel_text_address(addr)) { - if (in_sched_functions(addr)) - break; - if (trace->skip > 0) - trace->skip--; - else - trace->entries[trace->nr_entries++] = addr; - if (trace->nr_entries >= trace->max_entries) - break; - } - } + unwind_stack(current, NULL, sp, &save_stack_ops_nosched, trace); + if (trace->nr_entries < trace->max_entries) + trace->entries[trace->nr_entries++] = ULONG_MAX; } EXPORT_SYMBOL_GPL(save_stack_trace_tsk); diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c index 90d00e47264d..8aa5d1ceaf14 100644 --- a/arch/sh/kernel/sys_sh.c +++ b/arch/sh/kernel/sys_sh.c @@ -25,6 +25,8 @@ #include <asm/syscalls.h> #include <asm/uaccess.h> #include <asm/unistd.h> +#include <asm/cacheflush.h> +#include <asm/cachectl.h> static inline long do_mmap2(unsigned long addr, unsigned long len, unsigned long prot, @@ -179,6 +181,47 @@ asmlinkage int sys_ipc(uint call, int first, int second, return -EINVAL; } +/* sys_cacheflush -- flush (part of) the processor cache. */ +asmlinkage int sys_cacheflush(unsigned long addr, unsigned long len, int op) +{ + struct vm_area_struct *vma; + + if ((op <= 0) || (op > (CACHEFLUSH_D_PURGE|CACHEFLUSH_I))) + return -EINVAL; + + /* + * Verify that the specified address region actually belongs + * to this process. + */ + if (addr + len < addr) + return -EFAULT; + + down_read(¤t->mm->mmap_sem); + vma = find_vma (current->mm, addr); + if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end) { + up_read(¤t->mm->mmap_sem); + return -EFAULT; + } + + switch (op & CACHEFLUSH_D_PURGE) { + case CACHEFLUSH_D_INVAL: + __flush_invalidate_region((void *)addr, len); + break; + case CACHEFLUSH_D_WB: + __flush_wback_region((void *)addr, len); + break; + case CACHEFLUSH_D_PURGE: + __flush_purge_region((void *)addr, len); + break; + } + + if (op & CACHEFLUSH_I) + flush_cache_all(); + + up_read(¤t->mm->mmap_sem); + return 0; +} + asmlinkage int sys_uname(struct old_utsname __user *name) { int err; diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S index f9e21fa2f592..16ba225ede89 100644 --- a/arch/sh/kernel/syscalls_32.S +++ b/arch/sh/kernel/syscalls_32.S @@ -139,7 +139,7 @@ ENTRY(sys_call_table) .long sys_clone /* 120 */ .long sys_setdomainname .long sys_newuname - .long sys_ni_syscall /* sys_modify_ldt */ + .long sys_cacheflush /* x86: sys_modify_ldt */ .long sys_adjtimex .long sys_mprotect /* 125 */ .long sys_sigprocmask diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S index bf420b616ae0..af6fb7410c21 100644 --- a/arch/sh/kernel/syscalls_64.S +++ b/arch/sh/kernel/syscalls_64.S @@ -143,7 +143,7 @@ sys_call_table: .long sys_clone /* 120 */ .long sys_setdomainname .long sys_newuname - .long sys_ni_syscall /* sys_modify_ldt */ + .long sys_cacheflush /* x86: sys_modify_ldt */ .long sys_adjtimex .long sys_mprotect /* 125 */ .long sys_sigprocmask diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c index 9b352a1e3fb4..953fa1613312 100644 --- a/arch/sh/kernel/time.c +++ b/arch/sh/kernel/time.c @@ -21,6 +21,7 @@ #include <linux/smp.h> #include <linux/rtc.h> #include <asm/clock.h> +#include <asm/hwblk.h> #include <asm/rtc.h> /* Dummy RTC ops */ @@ -39,11 +40,9 @@ void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time; int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time; #ifdef CONFIG_GENERIC_CMOS_UPDATE -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { - struct timespec tv; - rtc_sh_get_time(&tv); - return tv.tv_sec; + rtc_sh_get_time(ts); } int update_persistent_clock(struct timespec now) @@ -91,21 +90,8 @@ module_init(rtc_generic_init); void (*board_time_init)(void); -void __init time_init(void) +static void __init sh_late_time_init(void) { - if (board_time_init) - board_time_init(); - - clk_init(); - - rtc_sh_get_time(&xtime); - set_normalized_timespec(&wall_to_monotonic, - -xtime.tv_sec, -xtime.tv_nsec); - -#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST - local_timer_setup(smp_processor_id()); -#endif - /* * Make sure all compiled-in early timers register themselves. * @@ -118,3 +104,18 @@ void __init time_init(void) early_platform_driver_register_all("earlytimer"); early_platform_driver_probe("earlytimer", 2, 0); } + +void __init time_init(void) +{ + if (board_time_init) + board_time_init(); + + hwblk_init(); + clk_init(); + + rtc_sh_get_time(&xtime); + set_normalized_timespec(&wall_to_monotonic, + -xtime.tv_sec, -xtime.tv_nsec); + + late_time_init = sh_late_time_init; +} diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c index b3e0067db358..a8396f36bd14 100644 --- a/arch/sh/kernel/traps.c +++ b/arch/sh/kernel/traps.c @@ -5,18 +5,33 @@ #include <linux/signal.h> #include <linux/sched.h> #include <linux/uaccess.h> +#include <linux/hardirq.h> +#include <asm/unwinder.h> #include <asm/system.h> #ifdef CONFIG_BUG -static void handle_BUG(struct pt_regs *regs) +void handle_BUG(struct pt_regs *regs) { + const struct bug_entry *bug; + unsigned long bugaddr = regs->pc; enum bug_trap_type tt; - tt = report_bug(regs->pc, regs); + + if (!is_valid_bugaddr(bugaddr)) + goto invalid; + + bug = find_bug(bugaddr); + + /* Switch unwinders when unwind_stack() is called */ + if (bug->flags & BUGFLAG_UNWINDER) + unwinder_faulted = 1; + + tt = report_bug(bugaddr, regs); if (tt == BUG_TRAP_TYPE_WARN) { - regs->pc += instruction_size(regs->pc); + regs->pc += instruction_size(bugaddr); return; } +invalid: die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff); } @@ -28,8 +43,10 @@ int is_valid_bugaddr(unsigned long addr) return 0; if (probe_kernel_address((insn_size_t *)addr, opcode)) return 0; + if (opcode == TRAPA_BUG_OPCODE) + return 1; - return opcode == TRAPA_BUG_OPCODE; + return 0; } #endif @@ -75,3 +92,23 @@ BUILD_TRAP_HANDLER(bug) force_sig(SIGTRAP, current); } + +BUILD_TRAP_HANDLER(nmi) +{ + TRAP_HANDLER_DECL; + + nmi_enter(); + + switch (notify_die(DIE_NMI, "NMI", regs, 0, vec & 0xff, SIGINT)) { + case NOTIFY_OK: + case NOTIFY_STOP: + break; + case NOTIFY_BAD: + die("Fatal Non-Maskable Interrupt", regs, SIGINT); + default: + printk(KERN_ALERT "Got NMI, but nobody cared. Ignoring...\n"); + break; + } + + nmi_exit(); +} diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c index 2b772776fcda..6aba9af79eaf 100644 --- a/arch/sh/kernel/traps_32.c +++ b/arch/sh/kernel/traps_32.c @@ -24,6 +24,7 @@ #include <linux/kdebug.h> #include <linux/kexec.h> #include <linux/limits.h> +#include <linux/proc_fs.h> #include <asm/system.h> #include <asm/uaccess.h> #include <asm/fpu.h> @@ -44,6 +45,85 @@ #define TRAP_ILLEGAL_SLOT_INST 13 #endif +static unsigned long se_user; +static unsigned long se_sys; +static unsigned long se_half; +static unsigned long se_word; +static unsigned long se_dword; +static unsigned long se_multi; +/* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not + valid! */ +static int se_usermode = 3; +/* 0: no warning 1: print a warning message */ +static int se_kernmode_warn = 1; + +#ifdef CONFIG_PROC_FS +static const char *se_usermode_action[] = { + "ignored", + "warn", + "fixup", + "fixup+warn", + "signal", + "signal+warn" +}; + +static int +proc_alignment_read(char *page, char **start, off_t off, int count, int *eof, + void *data) +{ + char *p = page; + int len; + + p += sprintf(p, "User:\t\t%lu\n", se_user); + p += sprintf(p, "System:\t\t%lu\n", se_sys); + p += sprintf(p, "Half:\t\t%lu\n", se_half); + p += sprintf(p, "Word:\t\t%lu\n", se_word); + p += sprintf(p, "DWord:\t\t%lu\n", se_dword); + p += sprintf(p, "Multi:\t\t%lu\n", se_multi); + p += sprintf(p, "User faults:\t%i (%s)\n", se_usermode, + se_usermode_action[se_usermode]); + p += sprintf(p, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn, + se_kernmode_warn ? "+warn" : ""); + + len = (p - page) - off; + if (len < 0) + len = 0; + + *eof = (len <= count) ? 1 : 0; + *start = page + off; + + return len; +} + +static int proc_alignment_write(struct file *file, const char __user *buffer, + unsigned long count, void *data) +{ + char mode; + + if (count > 0) { + if (get_user(mode, buffer)) + return -EFAULT; + if (mode >= '0' && mode <= '5') + se_usermode = mode - '0'; + } + return count; +} + +static int proc_alignment_kern_write(struct file *file, const char __user *buffer, + unsigned long count, void *data) +{ + char mode; + + if (count > 0) { + if (get_user(mode, buffer)) + return -EFAULT; + if (mode >= '0' && mode <= '1') + se_kernmode_warn = mode - '0'; + } + return count; +} +#endif + static void dump_mem(const char *str, unsigned long bottom, unsigned long top) { unsigned long p; @@ -136,6 +216,7 @@ static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err) regs->pc = fixup->fixup; return; } + die(str, regs, err); } } @@ -193,6 +274,13 @@ static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, count = 1<<(instruction&3); + switch (count) { + case 1: se_half += 1; break; + case 2: se_word += 1; break; + case 4: se_dword += 1; break; + case 8: se_multi += 1; break; /* ??? */ + } + ret = -EFAULT; switch (instruction>>12) { case 0: /* mov.[bwl] to/from memory via r0+rn */ @@ -358,15 +446,8 @@ static inline int handle_delayslot(struct pt_regs *regs, #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) -/* - * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit - * opcodes.. - */ - -static int handle_unaligned_notify_count = 10; - int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, - struct mem_access *ma) + struct mem_access *ma, int expected) { u_int rm; int ret, index; @@ -374,15 +455,13 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, index = (instruction>>8)&15; /* 0x0F00 */ rm = regs->regs[index]; - /* shout about the first ten userspace fixups */ - if (user_mode(regs) && handle_unaligned_notify_count>0) { - handle_unaligned_notify_count--; - - printk(KERN_NOTICE "Fixing up unaligned userspace access " + /* shout about fixups */ + if (!expected && printk_ratelimit()) + printk(KERN_NOTICE "Fixing up unaligned %s access " "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", + user_mode(regs) ? "userspace" : "kernel", current->comm, task_pid_nr(current), (void *)regs->pc, instruction); - } ret = -EFAULT; switch (instruction&0xF000) { @@ -538,6 +617,36 @@ asmlinkage void do_address_error(struct pt_regs *regs, local_irq_enable(); + se_user += 1; + +#ifndef CONFIG_CPU_SH2A + set_fs(USER_DS); + if (copy_from_user(&instruction, (u16 *)(regs->pc & ~1), 2)) { + set_fs(oldfs); + goto uspace_segv; + } + set_fs(oldfs); + + /* shout about userspace fixups */ + if (se_usermode & 1) + printk(KERN_NOTICE "Unaligned userspace access " + "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", + current->comm, current->pid, (void *)regs->pc, + instruction); +#endif + + if (se_usermode & 2) + goto fixup; + + if (se_usermode & 4) + goto uspace_segv; + else { + /* ignore */ + regs->pc += instruction_size(instruction); + return; + } + +fixup: /* bad PC is not something we can fix */ if (regs->pc & 1) { si_code = BUS_ADRALN; @@ -545,17 +654,8 @@ asmlinkage void do_address_error(struct pt_regs *regs, } set_fs(USER_DS); - if (copy_from_user(&instruction, (void __user *)(regs->pc), - sizeof(instruction))) { - /* Argh. Fault on the instruction itself. - This should never happen non-SMP - */ - set_fs(oldfs); - goto uspace_segv; - } - tmp = handle_unaligned_access(instruction, regs, - &user_mem_access); + &user_mem_access, 0); set_fs(oldfs); if (tmp==0) @@ -571,6 +671,14 @@ uspace_segv: info.si_addr = (void __user *)address; force_sig_info(SIGBUS, &info, current); } else { + se_sys += 1; + + if (se_kernmode_warn) + printk(KERN_NOTICE "Unaligned kernel access " + "on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", + current->comm, current->pid, (void *)regs->pc, + instruction); + if (regs->pc & 1) die("unaligned program counter", regs, error_code); @@ -584,7 +692,8 @@ uspace_segv: die("insn faulting in do_address_error", regs, 0); } - handle_unaligned_access(instruction, regs, &user_mem_access); + handle_unaligned_access(instruction, regs, + &user_mem_access, 0); set_fs(oldfs); } } @@ -858,30 +967,6 @@ void __init trap_init(void) per_cpu_trap_init(); } -void show_trace(struct task_struct *tsk, unsigned long *sp, - struct pt_regs *regs) -{ - unsigned long addr; - - if (regs && user_mode(regs)) - return; - - printk("\nCall trace:\n"); - - while (!kstack_end(sp)) { - addr = *sp++; - if (kernel_text_address(addr)) - print_ip_sym(addr); - } - - printk("\n"); - - if (!tsk) - tsk = current; - - debug_show_held_locks(tsk); -} - void show_stack(struct task_struct *tsk, unsigned long *sp) { unsigned long stack; @@ -904,3 +989,38 @@ void dump_stack(void) show_stack(NULL, NULL); } EXPORT_SYMBOL(dump_stack); + +#ifdef CONFIG_PROC_FS +/* + * This needs to be done after sysctl_init, otherwise sys/ will be + * overwritten. Actually, this shouldn't be in sys/ at all since + * it isn't a sysctl, and it doesn't contain sysctl information. + * We now locate it in /proc/cpu/alignment instead. + */ +static int __init alignment_init(void) +{ + struct proc_dir_entry *dir, *res; + + dir = proc_mkdir("cpu", NULL); + if (!dir) + return -ENOMEM; + + res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, dir); + if (!res) + return -ENOMEM; + + res->read_proc = proc_alignment_read; + res->write_proc = proc_alignment_write; + + res = create_proc_entry("kernel_alignment", S_IWUSR | S_IRUGO, dir); + if (!res) + return -ENOMEM; + + res->read_proc = proc_alignment_read; + res->write_proc = proc_alignment_kern_write; + + return 0; +} + +fs_initcall(alignment_init); +#endif diff --git a/arch/sh/kernel/unwinder.c b/arch/sh/kernel/unwinder.c new file mode 100644 index 000000000000..468889d958f4 --- /dev/null +++ b/arch/sh/kernel/unwinder.c @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2009 Matt Fleming + * + * Based, in part, on kernel/time/clocksource.c. + * + * This file provides arbitration code for stack unwinders. + * + * Multiple stack unwinders can be available on a system, usually with + * the most accurate unwinder being the currently active one. + */ +#include <linux/errno.h> +#include <linux/list.h> +#include <linux/spinlock.h> +#include <linux/module.h> +#include <asm/unwinder.h> +#include <asm/atomic.h> + +/* + * This is the most basic stack unwinder an architecture can + * provide. For architectures without reliable frame pointers, e.g. + * RISC CPUs, it can be implemented by looking through the stack for + * addresses that lie within the kernel text section. + * + * Other CPUs, e.g. x86, can use their frame pointer register to + * construct more accurate stack traces. + */ +static struct list_head unwinder_list; +static struct unwinder stack_reader = { + .name = "stack-reader", + .dump = stack_reader_dump, + .rating = 50, + .list = { + .next = &unwinder_list, + .prev = &unwinder_list, + }, +}; + +/* + * "curr_unwinder" points to the stack unwinder currently in use. This + * is the unwinder with the highest rating. + * + * "unwinder_list" is a linked-list of all available unwinders, sorted + * by rating. + * + * All modifications of "curr_unwinder" and "unwinder_list" must be + * performed whilst holding "unwinder_lock". + */ +static struct unwinder *curr_unwinder = &stack_reader; + +static struct list_head unwinder_list = { + .next = &stack_reader.list, + .prev = &stack_reader.list, +}; + +static DEFINE_SPINLOCK(unwinder_lock); + +/** + * select_unwinder - Select the best registered stack unwinder. + * + * Private function. Must hold unwinder_lock when called. + * + * Select the stack unwinder with the best rating. This is useful for + * setting up curr_unwinder. + */ +static struct unwinder *select_unwinder(void) +{ + struct unwinder *best; + + if (list_empty(&unwinder_list)) + return NULL; + + best = list_entry(unwinder_list.next, struct unwinder, list); + if (best == curr_unwinder) + return NULL; + + return best; +} + +/* + * Enqueue the stack unwinder sorted by rating. + */ +static int unwinder_enqueue(struct unwinder *ops) +{ + struct list_head *tmp, *entry = &unwinder_list; + + list_for_each(tmp, &unwinder_list) { + struct unwinder *o; + + o = list_entry(tmp, struct unwinder, list); + if (o == ops) + return -EBUSY; + /* Keep track of the place, where to insert */ + if (o->rating >= ops->rating) + entry = tmp; + } + list_add(&ops->list, entry); + + return 0; +} + +/** + * unwinder_register - Used to install new stack unwinder + * @u: unwinder to be registered + * + * Install the new stack unwinder on the unwinder list, which is sorted + * by rating. + * + * Returns -EBUSY if registration fails, zero otherwise. + */ +int unwinder_register(struct unwinder *u) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&unwinder_lock, flags); + ret = unwinder_enqueue(u); + if (!ret) + curr_unwinder = select_unwinder(); + spin_unlock_irqrestore(&unwinder_lock, flags); + + return ret; +} + +int unwinder_faulted = 0; + +/* + * Unwind the call stack and pass information to the stacktrace_ops + * functions. Also handle the case where we need to switch to a new + * stack dumper because the current one faulted unexpectedly. + */ +void unwind_stack(struct task_struct *task, struct pt_regs *regs, + unsigned long *sp, const struct stacktrace_ops *ops, + void *data) +{ + unsigned long flags; + + /* + * The problem with unwinders with high ratings is that they are + * inherently more complicated than the simple ones with lower + * ratings. We are therefore more likely to fault in the + * complicated ones, e.g. hitting BUG()s. If we fault in the + * code for the current stack unwinder we try to downgrade to + * one with a lower rating. + * + * Hopefully this will give us a semi-reliable stacktrace so we + * can diagnose why curr_unwinder->dump() faulted. + */ + if (unwinder_faulted) { + spin_lock_irqsave(&unwinder_lock, flags); + + /* Make sure no one beat us to changing the unwinder */ + if (unwinder_faulted && !list_is_singular(&unwinder_list)) { + list_del(&curr_unwinder->list); + curr_unwinder = select_unwinder(); + + unwinder_faulted = 0; + } + + spin_unlock_irqrestore(&unwinder_lock, flags); + } + + curr_unwinder->dump(task, regs, sp, ops, data); +} +EXPORT_SYMBOL_GPL(unwind_stack); diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S index 0ce254bca92f..a1e4ec24f1f5 100644 --- a/arch/sh/kernel/vmlinux.lds.S +++ b/arch/sh/kernel/vmlinux.lds.S @@ -12,7 +12,7 @@ OUTPUT_ARCH(sh) #include <asm/thread_info.h> #include <asm/cache.h> -#include <asm-generic/vmlinux.lds.h> +#include <asm/vmlinux.lds.h> ENTRY(_start) SECTIONS @@ -50,12 +50,7 @@ SECTIONS _etext = .; /* End of text section */ } = 0x0009 - . = ALIGN(16); /* Exception table */ - __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { - __start___ex_table = .; - *(__ex_table) - __stop___ex_table = .; - } + EXCEPTION_TABLE(16) NOTES RO_DATA(PAGE_SIZE) @@ -71,69 +66,16 @@ SECTIONS __uncached_end = .; } - . = ALIGN(THREAD_SIZE); - .data : AT(ADDR(.data) - LOAD_OFFSET) { /* Data */ - *(.data.init_task) - - . = ALIGN(L1_CACHE_BYTES); - *(.data.cacheline_aligned) - - . = ALIGN(L1_CACHE_BYTES); - *(.data.read_mostly) - - . = ALIGN(PAGE_SIZE); - *(.data.page_aligned) - - __nosave_begin = .; - *(.data.nosave) - . = ALIGN(PAGE_SIZE); - __nosave_end = .; - - DATA_DATA - CONSTRUCTORS - } + RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) _edata = .; /* End of data section */ - . = ALIGN(PAGE_SIZE); /* Init code and data */ - .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) { - __init_begin = .; - _sinittext = .; - INIT_TEXT - _einittext = .; - } - - .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) { INIT_DATA } - - . = ALIGN(16); - .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) { - __setup_start = .; - *(.init.setup) - __setup_end = .; - } - - .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) { - __initcall_start = .; - INITCALLS - __initcall_end = .; - } - - .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) { - __con_initcall_start = .; - *(.con_initcall.init) - __con_initcall_end = .; - } - - SECURITY_INIT + DWARF_EH_FRAME -#ifdef CONFIG_BLK_DEV_INITRD - . = ALIGN(PAGE_SIZE); - .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { - __initramfs_start = .; - *(.init.ramfs) - __initramfs_end = .; - } -#endif + . = ALIGN(PAGE_SIZE); /* Init code and data */ + __init_begin = .; + INIT_TEXT_SECTION(PAGE_SIZE) + INIT_DATA_SECTION(16) . = ALIGN(4); .machvec.init : AT(ADDR(.machvec.init) - LOAD_OFFSET) { @@ -152,25 +94,13 @@ SECTIONS .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { EXIT_DATA } . = ALIGN(PAGE_SIZE); - .bss : AT(ADDR(.bss) - LOAD_OFFSET) { - __init_end = .; - __bss_start = .; /* BSS */ - *(.bss.page_aligned) - *(.bss) - *(COMMON) - . = ALIGN(4); - _ebss = .; /* uClinux MTD sucks */ - _end = . ; - } + __init_end = .; + BSS_SECTION(0, PAGE_SIZE, 4) + _ebss = .; /* uClinux MTD sucks */ + _end = . ; STABS_DEBUG DWARF_DEBUG - /* - * When something in the kernel is NOT compiled as a module, the - * module cleanup code and data are put into these segments. Both - * can then be thrown away, as cleanup code is never called unless - * it's a module. - */ DISCARDS } diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index aaea580b65bb..a969b47c5463 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -23,8 +23,8 @@ obj-y += io.o memcpy-y := memcpy.o memcpy-$(CONFIG_CPU_SH4) := memcpy-sh4.o -lib-$(CONFIG_MMU) += copy_page.o clear_page.o -lib-$(CONFIG_FUNCTION_TRACER) += mcount.o +lib-$(CONFIG_MMU) += copy_page.o __clear_user.o +lib-$(CONFIG_MCOUNT) += mcount.o lib-y += $(memcpy-y) $(udivsi3-y) EXTRA_CFLAGS += -Werror diff --git a/arch/sh/lib/clear_page.S b/arch/sh/lib/__clear_user.S index 8342bfbde64c..db1dca7aad14 100644 --- a/arch/sh/lib/clear_page.S +++ b/arch/sh/lib/__clear_user.S @@ -8,56 +8,10 @@ #include <linux/linkage.h> #include <asm/page.h> -/* - * clear_page - * @to: P1 address - * - * void clear_page(void *to) - */ - -/* - * r0 --- scratch - * r4 --- to - * r5 --- to + PAGE_SIZE - */ -ENTRY(clear_page) - mov r4,r5 - mov.l .Llimit,r0 - add r0,r5 - mov #0,r0 - ! -1: -#if defined(CONFIG_CPU_SH4) - movca.l r0,@r4 - mov r4,r1 -#else - mov.l r0,@r4 -#endif - add #32,r4 - mov.l r0,@-r4 - mov.l r0,@-r4 - mov.l r0,@-r4 - mov.l r0,@-r4 - mov.l r0,@-r4 - mov.l r0,@-r4 - mov.l r0,@-r4 -#if defined(CONFIG_CPU_SH4) - ocbwb @r1 -#endif - cmp/eq r5,r4 - bf/s 1b - add #28,r4 - ! - rts - nop - - .balign 4 -.Llimit: .long (PAGE_SIZE-28) - ENTRY(__clear_user) ! mov #0, r0 - mov #0xe0, r1 ! 0xffffffe0 + mov #0xffffffe0, r1 ! ! r4..(r4+31)&~32 -------- not aligned [ Area 0 ] ! (r4+31)&~32..(r4+r5)&~32 -------- aligned [ Area 1 ] diff --git a/arch/sh/lib/copy_page.S b/arch/sh/lib/copy_page.S index 43de7e8e4e17..9d7b8bc51866 100644 --- a/arch/sh/lib/copy_page.S +++ b/arch/sh/lib/copy_page.S @@ -30,7 +30,9 @@ ENTRY(copy_page) mov r4,r10 mov r5,r11 mov r5,r8 - mov.l .Lpsz,r0 + mov #(PAGE_SIZE >> 10), r0 + shll8 r0 + shll2 r0 add r0,r8 ! 1: mov.l @r11+,r0 @@ -43,7 +45,6 @@ ENTRY(copy_page) mov.l @r11+,r7 #if defined(CONFIG_CPU_SH4) movca.l r0,@r10 - mov r10,r0 #else mov.l r0,@r10 #endif @@ -55,9 +56,6 @@ ENTRY(copy_page) mov.l r3,@-r10 mov.l r2,@-r10 mov.l r1,@-r10 -#if defined(CONFIG_CPU_SH4) - ocbwb @r0 -#endif cmp/eq r11,r8 bf/s 1b add #28,r10 @@ -68,9 +66,6 @@ ENTRY(copy_page) rts nop - .balign 4 -.Lpsz: .long PAGE_SIZE - /* * __kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n); * Return the number of bytes NOT copied diff --git a/arch/sh/lib/delay.c b/arch/sh/lib/delay.c index f3ddd2133e6f..faa8f86c0db4 100644 --- a/arch/sh/lib/delay.c +++ b/arch/sh/lib/delay.c @@ -21,13 +21,14 @@ void __delay(unsigned long loops) inline void __const_udelay(unsigned long xloops) { + xloops *= 4; __asm__("dmulu.l %0, %2\n\t" "sts mach, %0" : "=r" (xloops) : "0" (xloops), - "r" (HZ * cpu_data[raw_smp_processor_id()].loops_per_jiffy) + "r" (cpu_data[raw_smp_processor_id()].loops_per_jiffy * (HZ/4)) : "macl", "mach"); - __delay(xloops); + __delay(++xloops); } void __udelay(unsigned long usecs) diff --git a/arch/sh/lib/mcount.S b/arch/sh/lib/mcount.S index 110fbfe1831f..84a57761f17e 100644 --- a/arch/sh/lib/mcount.S +++ b/arch/sh/lib/mcount.S @@ -1,14 +1,16 @@ /* * arch/sh/lib/mcount.S * - * Copyright (C) 2008 Paul Mundt - * Copyright (C) 2008 Matt Fleming + * Copyright (C) 2008, 2009 Paul Mundt + * Copyright (C) 2008, 2009 Matt Fleming * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #include <asm/ftrace.h> +#include <asm/thread_info.h> +#include <asm/asm-offsets.h> #define MCOUNT_ENTER() \ mov.l r4, @-r15; \ @@ -28,6 +30,55 @@ rts; \ mov.l @r15+, r4 +#ifdef CONFIG_STACK_DEBUG +/* + * Perform diagnostic checks on the state of the kernel stack. + * + * Check for stack overflow. If there is less than 1KB free + * then it has overflowed. + * + * Make sure the stack pointer contains a valid address. Valid + * addresses for kernel stacks are anywhere after the bss + * (after _ebss) and anywhere in init_thread_union (init_stack). + */ +#define STACK_CHECK() \ + mov #(THREAD_SIZE >> 10), r0; \ + shll8 r0; \ + shll2 r0; \ + \ + /* r1 = sp & (THREAD_SIZE - 1) */ \ + mov #-1, r1; \ + add r0, r1; \ + and r15, r1; \ + \ + mov #TI_SIZE, r3; \ + mov #(STACK_WARN >> 8), r2; \ + shll8 r2; \ + add r3, r2; \ + \ + /* Is the stack overflowing? */ \ + cmp/hi r2, r1; \ + bf stack_panic; \ + \ + /* If sp > _ebss then we're OK. */ \ + mov.l .L_ebss, r1; \ + cmp/hi r1, r15; \ + bt 1f; \ + \ + /* If sp < init_stack, we're not OK. */ \ + mov.l .L_init_thread_union, r1; \ + cmp/hs r1, r15; \ + bf stack_panic; \ + \ + /* If sp > init_stack && sp < _ebss, not OK. */ \ + add r0, r1; \ + cmp/hs r1, r15; \ + bt stack_panic; \ +1: +#else +#define STACK_CHECK() +#endif /* CONFIG_STACK_DEBUG */ + .align 2 .globl _mcount .type _mcount,@function @@ -35,6 +86,19 @@ .type mcount,@function _mcount: mcount: + STACK_CHECK() + +#ifndef CONFIG_FUNCTION_TRACER + rts + nop +#else +#ifndef CONFIG_DYNAMIC_FTRACE + mov.l .Lfunction_trace_stop, r0 + mov.l @r0, r0 + tst r0, r0 + bf ftrace_stub +#endif + MCOUNT_ENTER() #ifdef CONFIG_DYNAMIC_FTRACE @@ -52,16 +116,69 @@ mcount_call: jsr @r6 nop +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + mov.l .Lftrace_graph_return, r6 + mov.l .Lftrace_stub, r7 + cmp/eq r6, r7 + bt 1f + + mov.l .Lftrace_graph_caller, r0 + jmp @r0 + nop + +1: + mov.l .Lftrace_graph_entry, r6 + mov.l .Lftrace_graph_entry_stub, r7 + cmp/eq r6, r7 + bt skip_trace + + mov.l .Lftrace_graph_caller, r0 + jmp @r0 + nop + + .align 2 +.Lftrace_graph_return: + .long ftrace_graph_return +.Lftrace_graph_entry: + .long ftrace_graph_entry +.Lftrace_graph_entry_stub: + .long ftrace_graph_entry_stub +.Lftrace_graph_caller: + .long ftrace_graph_caller +#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ + + .globl skip_trace skip_trace: MCOUNT_LEAVE() .align 2 .Lftrace_trace_function: - .long ftrace_trace_function + .long ftrace_trace_function #ifdef CONFIG_DYNAMIC_FTRACE +#ifdef CONFIG_FUNCTION_GRAPH_TRACER +/* + * NOTE: Do not move either ftrace_graph_call or ftrace_caller + * as this will affect the calculation of GRAPH_INSN_OFFSET. + */ + .globl ftrace_graph_call +ftrace_graph_call: + mov.l .Lskip_trace, r0 + jmp @r0 + nop + + .align 2 +.Lskip_trace: + .long skip_trace +#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ + .globl ftrace_caller ftrace_caller: + mov.l .Lfunction_trace_stop, r0 + mov.l @r0, r0 + tst r0, r0 + bf ftrace_stub + MCOUNT_ENTER() .globl ftrace_call @@ -70,9 +187,18 @@ ftrace_call: jsr @r6 nop +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + bra ftrace_graph_call + nop +#else MCOUNT_LEAVE() +#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ #endif /* CONFIG_DYNAMIC_FTRACE */ + .align 2 +.Lfunction_trace_stop: + .long function_trace_stop + /* * NOTE: From here on the locations of the .Lftrace_stub label and * ftrace_stub itself are fixed. Adding additional data here will skew @@ -80,7 +206,6 @@ ftrace_call: * Place new labels either after the ftrace_stub body, or before * ftrace_caller. You have been warned. */ - .align 2 .Lftrace_stub: .long ftrace_stub @@ -88,3 +213,98 @@ ftrace_call: ftrace_stub: rts nop + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + .globl ftrace_graph_caller +ftrace_graph_caller: + mov.l 2f, r0 + mov.l @r0, r0 + tst r0, r0 + bt 1f + + mov.l 3f, r1 + jmp @r1 + nop +1: + /* + * MCOUNT_ENTER() pushed 5 registers onto the stack, so + * the stack address containing our return address is + * r15 + 20. + */ + mov #20, r0 + add r15, r0 + mov r0, r4 + + mov.l .Lprepare_ftrace_return, r0 + jsr @r0 + nop + + MCOUNT_LEAVE() + + .align 2 +2: .long function_trace_stop +3: .long skip_trace +.Lprepare_ftrace_return: + .long prepare_ftrace_return + + .globl return_to_handler +return_to_handler: + /* + * Save the return values. + */ + mov.l r0, @-r15 + mov.l r1, @-r15 + + mov #0, r4 + + mov.l .Lftrace_return_to_handler, r0 + jsr @r0 + nop + + /* + * The return value from ftrace_return_handler has the real + * address that we should return to. + */ + lds r0, pr + mov.l @r15+, r1 + rts + mov.l @r15+, r0 + + + .align 2 +.Lftrace_return_to_handler: + .long ftrace_return_to_handler +#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ +#endif /* CONFIG_FUNCTION_TRACER */ + +#ifdef CONFIG_STACK_DEBUG + .globl stack_panic +stack_panic: + mov.l .Ldump_stack, r0 + jsr @r0 + nop + + mov.l .Lpanic, r0 + jsr @r0 + mov.l .Lpanic_s, r4 + + rts + nop + + .align 2 +.L_ebss: + .long _ebss +.L_init_thread_union: + .long init_thread_union +.Lpanic: + .long panic +.Lpanic_s: + .long .Lpanic_str +.Ldump_stack: + .long dump_stack + + .section .rodata + .align 2 +.Lpanic_str: + .string "Stack error" +#endif /* CONFIG_STACK_DEBUG */ diff --git a/arch/sh/lib64/Makefile b/arch/sh/lib64/Makefile index 334bb2da36ea..1fee75aa1f98 100644 --- a/arch/sh/lib64/Makefile +++ b/arch/sh/lib64/Makefile @@ -11,7 +11,7 @@ # Panic should really be compiled as PIC lib-y := udelay.o dbg.o panic.o memcpy.o memset.o \ - copy_user_memcpy.o copy_page.o clear_page.o strcpy.o strlen.o + copy_user_memcpy.o copy_page.o strcpy.o strlen.o # Extracted from libgcc lib-y += udivsi3.o udivdi3.o sdivsi3.o diff --git a/arch/sh/lib64/clear_page.S b/arch/sh/lib64/clear_page.S deleted file mode 100644 index 007ab48ecc1c..000000000000 --- a/arch/sh/lib64/clear_page.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - Copyright 2003 Richard Curnow, SuperH (UK) Ltd. - - This file is subject to the terms and conditions of the GNU General Public - License. See the file "COPYING" in the main directory of this archive - for more details. - - Tight version of memset for the case of just clearing a page. It turns out - that having the alloco's spaced out slightly due to the increment/branch - pair causes them to contend less for access to the cache. Similarly, - keeping the stores apart from the allocos causes less contention. => Do two - separate loops. Do multiple stores per loop to amortise the - increment/branch cost a little. - - Parameters: - r2 : source effective address (start of page) - - Always clears 4096 bytes. - - Note : alloco guarded by synco to avoid TAKum03020 erratum - -*/ - - .section .text..SHmedia32,"ax" - .little - - .balign 8 - .global clear_page -clear_page: - pta/l 1f, tr1 - pta/l 2f, tr2 - ptabs/l r18, tr0 - - movi 4096, r7 - add r2, r7, r7 - add r2, r63, r6 -1: - alloco r6, 0 - synco ! TAKum03020 - addi r6, 32, r6 - bgt/l r7, r6, tr1 - - add r2, r63, r6 -2: - st.q r6, 0, r63 - st.q r6, 8, r63 - st.q r6, 16, r63 - st.q r6, 24, r63 - addi r6, 32, r6 - bgt/l r7, r6, tr2 - - blink tr0, r63 - - diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig index 2795618e4f07..64dc1ad59801 100644 --- a/arch/sh/mm/Kconfig +++ b/arch/sh/mm/Kconfig @@ -82,7 +82,7 @@ config 32BIT config PMB_ENABLE bool "Support 32-bit physical addressing through PMB" - depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) select 32BIT default y help @@ -97,7 +97,7 @@ choice config PMB bool "PMB" - depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) select 32BIT help If you say Y here, physical addressing will be extended to @@ -106,7 +106,8 @@ config PMB config PMB_FIXED bool "fixed PMB" - depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || \ + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || \ + CPU_SUBTYPE_SH7780 || \ CPU_SUBTYPE_SH7785) select 32BIT help diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile index 9f4bc3d90b1e..3759bf853293 100644 --- a/arch/sh/mm/Makefile +++ b/arch/sh/mm/Makefile @@ -1,5 +1,65 @@ -ifeq ($(CONFIG_SUPERH32),y) -include ${srctree}/arch/sh/mm/Makefile_32 -else -include ${srctree}/arch/sh/mm/Makefile_64 +# +# Makefile for the Linux SuperH-specific parts of the memory manager. +# + +obj-y := cache.o init.o consistent.o mmap.o + +cacheops-$(CONFIG_CPU_SH2) := cache-sh2.o +cacheops-$(CONFIG_CPU_SH2A) := cache-sh2a.o +cacheops-$(CONFIG_CPU_SH3) := cache-sh3.o +cacheops-$(CONFIG_CPU_SH4) := cache-sh4.o flush-sh4.o +cacheops-$(CONFIG_CPU_SH5) := cache-sh5.o flush-sh4.o +cacheops-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o + +obj-y += $(cacheops-y) + +mmu-y := nommu.o extable_32.o +mmu-$(CONFIG_MMU) := extable_$(BITS).o fault_$(BITS).o \ + ioremap_$(BITS).o kmap.o tlbflush_$(BITS).o + +obj-y += $(mmu-y) +obj-$(CONFIG_DEBUG_FS) += asids-debugfs.o + +ifdef CONFIG_DEBUG_FS +obj-$(CONFIG_CPU_SH4) += cache-debugfs.o endif + +ifdef CONFIG_MMU +tlb-$(CONFIG_CPU_SH3) := tlb-sh3.o +tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o +tlb-$(CONFIG_CPU_SH5) := tlb-sh5.o +tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o +obj-y += $(tlb-y) +endif + +obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o +obj-$(CONFIG_PMB) += pmb.o +obj-$(CONFIG_PMB_FIXED) += pmb-fixed.o +obj-$(CONFIG_NUMA) += numa.o + +# Special flags for fault_64.o. This puts restrictions on the number of +# caller-save registers that the compiler can target when building this file. +# This is required because the code is called from a context in entry.S where +# very few registers have been saved in the exception handler (for speed +# reasons). +# The caller save registers that have been saved and which can be used are +# r2,r3,r4,r5 : argument passing +# r15, r18 : SP and LINK +# tr0-4 : allow all caller-save TR's. The compiler seems to be able to make +# use of them, so it's probably beneficial to performance to save them +# and have them available for it. +# +# The resources not listed below are callee save, i.e. the compiler is free to +# use any of them and will spill them to the stack itself. + +CFLAGS_fault_64.o += -ffixed-r7 \ + -ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12 \ + -ffixed-r13 -ffixed-r14 -ffixed-r16 -ffixed-r17 -ffixed-r19 \ + -ffixed-r20 -ffixed-r21 -ffixed-r22 -ffixed-r23 \ + -ffixed-r24 -ffixed-r25 -ffixed-r26 -ffixed-r27 \ + -ffixed-r36 -ffixed-r37 -ffixed-r38 -ffixed-r39 -ffixed-r40 \ + -ffixed-r41 -ffixed-r42 -ffixed-r43 \ + -ffixed-r60 -ffixed-r61 -ffixed-r62 \ + -fomit-frame-pointer + +EXTRA_CFLAGS += -Werror diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32 deleted file mode 100644 index 986a1e055834..000000000000 --- a/arch/sh/mm/Makefile_32 +++ /dev/null @@ -1,43 +0,0 @@ -# -# Makefile for the Linux SuperH-specific parts of the memory manager. -# - -obj-y := init.o extable_32.o consistent.o mmap.o - -ifndef CONFIG_CACHE_OFF -cache-$(CONFIG_CPU_SH2) := cache-sh2.o -cache-$(CONFIG_CPU_SH2A) := cache-sh2a.o -cache-$(CONFIG_CPU_SH3) := cache-sh3.o -cache-$(CONFIG_CPU_SH4) := cache-sh4.o -cache-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o -endif - -obj-y += $(cache-y) - -mmu-y := tlb-nommu.o pg-nommu.o -mmu-$(CONFIG_MMU) := fault_32.o tlbflush_32.o ioremap_32.o - -obj-y += $(mmu-y) -obj-$(CONFIG_DEBUG_FS) += asids-debugfs.o - -ifdef CONFIG_DEBUG_FS -obj-$(CONFIG_CPU_SH4) += cache-debugfs.o -endif - -ifdef CONFIG_MMU -tlb-$(CONFIG_CPU_SH3) := tlb-sh3.o -tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o -tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o -obj-y += $(tlb-y) -ifndef CONFIG_CACHE_OFF -obj-$(CONFIG_CPU_SH4) += pg-sh4.o -obj-$(CONFIG_SH7705_CACHE_32KB) += pg-sh7705.o -endif -endif - -obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o -obj-$(CONFIG_PMB) += pmb.o -obj-$(CONFIG_PMB_FIXED) += pmb-fixed.o -obj-$(CONFIG_NUMA) += numa.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/sh/mm/Makefile_64 b/arch/sh/mm/Makefile_64 deleted file mode 100644 index 2863ffb7006d..000000000000 --- a/arch/sh/mm/Makefile_64 +++ /dev/null @@ -1,46 +0,0 @@ -# -# Makefile for the Linux SuperH-specific parts of the memory manager. -# - -obj-y := init.o consistent.o mmap.o - -mmu-y := tlb-nommu.o pg-nommu.o extable_32.o -mmu-$(CONFIG_MMU) := fault_64.o ioremap_64.o tlbflush_64.o tlb-sh5.o \ - extable_64.o - -ifndef CONFIG_CACHE_OFF -obj-y += cache-sh5.o -endif - -obj-y += $(mmu-y) -obj-$(CONFIG_DEBUG_FS) += asids-debugfs.o - -obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o -obj-$(CONFIG_NUMA) += numa.o - -EXTRA_CFLAGS += -Werror - -# Special flags for fault_64.o. This puts restrictions on the number of -# caller-save registers that the compiler can target when building this file. -# This is required because the code is called from a context in entry.S where -# very few registers have been saved in the exception handler (for speed -# reasons). -# The caller save registers that have been saved and which can be used are -# r2,r3,r4,r5 : argument passing -# r15, r18 : SP and LINK -# tr0-4 : allow all caller-save TR's. The compiler seems to be able to make -# use of them, so it's probably beneficial to performance to save them -# and have them available for it. -# -# The resources not listed below are callee save, i.e. the compiler is free to -# use any of them and will spill them to the stack itself. - -CFLAGS_fault_64.o += -ffixed-r7 \ - -ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12 \ - -ffixed-r13 -ffixed-r14 -ffixed-r16 -ffixed-r17 -ffixed-r19 \ - -ffixed-r20 -ffixed-r21 -ffixed-r22 -ffixed-r23 \ - -ffixed-r24 -ffixed-r25 -ffixed-r26 -ffixed-r27 \ - -ffixed-r36 -ffixed-r37 -ffixed-r38 -ffixed-r39 -ffixed-r40 \ - -ffixed-r41 -ffixed-r42 -ffixed-r43 \ - -ffixed-r60 -ffixed-r61 -ffixed-r62 \ - -fomit-frame-pointer diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c index c4e80d2b764b..699a71f46327 100644 --- a/arch/sh/mm/cache-sh2.c +++ b/arch/sh/mm/cache-sh2.c @@ -16,7 +16,7 @@ #include <asm/cacheflush.h> #include <asm/io.h> -void __flush_wback_region(void *start, int size) +static void sh2__flush_wback_region(void *start, int size) { unsigned long v; unsigned long begin, end; @@ -37,7 +37,7 @@ void __flush_wback_region(void *start, int size) } } -void __flush_purge_region(void *start, int size) +static void sh2__flush_purge_region(void *start, int size) { unsigned long v; unsigned long begin, end; @@ -51,7 +51,7 @@ void __flush_purge_region(void *start, int size) CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); } -void __flush_invalidate_region(void *start, int size) +static void sh2__flush_invalidate_region(void *start, int size) { #ifdef CONFIG_CACHE_WRITEBACK /* @@ -82,3 +82,10 @@ void __flush_invalidate_region(void *start, int size) CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); #endif } + +void __init sh2_cache_init(void) +{ + __flush_wback_region = sh2__flush_wback_region; + __flush_purge_region = sh2__flush_purge_region; + __flush_invalidate_region = sh2__flush_invalidate_region; +} diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c index 24d86a794065..975899d83564 100644 --- a/arch/sh/mm/cache-sh2a.c +++ b/arch/sh/mm/cache-sh2a.c @@ -15,7 +15,7 @@ #include <asm/cacheflush.h> #include <asm/io.h> -void __flush_wback_region(void *start, int size) +static void sh2a__flush_wback_region(void *start, int size) { unsigned long v; unsigned long begin, end; @@ -44,7 +44,7 @@ void __flush_wback_region(void *start, int size) local_irq_restore(flags); } -void __flush_purge_region(void *start, int size) +static void sh2a__flush_purge_region(void *start, int size) { unsigned long v; unsigned long begin, end; @@ -65,7 +65,7 @@ void __flush_purge_region(void *start, int size) local_irq_restore(flags); } -void __flush_invalidate_region(void *start, int size) +static void sh2a__flush_invalidate_region(void *start, int size) { unsigned long v; unsigned long begin, end; @@ -97,13 +97,15 @@ void __flush_invalidate_region(void *start, int size) } /* WBack O-Cache and flush I-Cache */ -void flush_icache_range(unsigned long start, unsigned long end) +static void sh2a_flush_icache_range(void *args) { + struct flusher_data *data = args; + unsigned long start, end; unsigned long v; unsigned long flags; - start = start & ~(L1_CACHE_BYTES-1); - end = (end + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1); + start = data->addr1 & ~(L1_CACHE_BYTES-1); + end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1); local_irq_save(flags); jump_to_uncached(); @@ -127,3 +129,12 @@ void flush_icache_range(unsigned long start, unsigned long end) back_to_cached(); local_irq_restore(flags); } + +void __init sh2a_cache_init(void) +{ + local_flush_icache_range = sh2a_flush_icache_range; + + __flush_wback_region = sh2a__flush_wback_region; + __flush_purge_region = sh2a__flush_purge_region; + __flush_invalidate_region = sh2a__flush_invalidate_region; +} diff --git a/arch/sh/mm/cache-sh3.c b/arch/sh/mm/cache-sh3.c index 6d1dbec08ad4..faef80c98134 100644 --- a/arch/sh/mm/cache-sh3.c +++ b/arch/sh/mm/cache-sh3.c @@ -32,7 +32,7 @@ * SIZE: Size of the region. */ -void __flush_wback_region(void *start, int size) +static void sh3__flush_wback_region(void *start, int size) { unsigned long v, j; unsigned long begin, end; @@ -71,7 +71,7 @@ void __flush_wback_region(void *start, int size) * START: Virtual Address (U0, P1, or P3) * SIZE: Size of the region. */ -void __flush_purge_region(void *start, int size) +static void sh3__flush_purge_region(void *start, int size) { unsigned long v; unsigned long begin, end; @@ -90,11 +90,16 @@ void __flush_purge_region(void *start, int size) } } -/* - * No write back please - * - * Except I don't think there's any way to avoid the writeback. So we - * just alias it to __flush_purge_region(). dwmw2. - */ -void __flush_invalidate_region(void *start, int size) - __attribute__((alias("__flush_purge_region"))); +void __init sh3_cache_init(void) +{ + __flush_wback_region = sh3__flush_wback_region; + __flush_purge_region = sh3__flush_purge_region; + + /* + * No write back please + * + * Except I don't think there's any way to avoid the writeback. + * So we just alias it to sh3__flush_purge_region(). dwmw2. + */ + __flush_invalidate_region = sh3__flush_purge_region; +} diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index 5cfe08dbb59e..b2453bbef4cd 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c @@ -14,6 +14,7 @@ #include <linux/mm.h> #include <linux/io.h> #include <linux/mutex.h> +#include <linux/fs.h> #include <asm/mmu_context.h> #include <asm/cacheflush.h> @@ -25,13 +26,6 @@ #define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */ #define MAX_ICACHE_PAGES 32 -static void __flush_dcache_segment_1way(unsigned long start, - unsigned long extent); -static void __flush_dcache_segment_2way(unsigned long start, - unsigned long extent); -static void __flush_dcache_segment_4way(unsigned long start, - unsigned long extent); - static void __flush_cache_4096(unsigned long addr, unsigned long phys, unsigned long exec_offset); @@ -43,182 +37,56 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys, static void (*__flush_dcache_segment_fn)(unsigned long, unsigned long) = (void (*)(unsigned long, unsigned long))0xdeadbeef; -static void compute_alias(struct cache_info *c) +/* + * Write back the range of D-cache, and purge the I-cache. + * + * Called from kernel/module.c:sys_init_module and routine for a.out format, + * signal handler code and kprobes code + */ +static void sh4_flush_icache_range(void *args) { - c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1); - c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0; -} + struct flusher_data *data = args; + unsigned long start, end; + unsigned long flags, v; + int i; -static void __init emit_cache_params(void) -{ - printk("PVR=%08x CVR=%08x PRR=%08x\n", - ctrl_inl(CCN_PVR), - ctrl_inl(CCN_CVR), - ctrl_inl(CCN_PRR)); - printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n", - boot_cpu_data.icache.ways, - boot_cpu_data.icache.sets, - boot_cpu_data.icache.way_incr); - printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", - boot_cpu_data.icache.entry_mask, - boot_cpu_data.icache.alias_mask, - boot_cpu_data.icache.n_aliases); - printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n", - boot_cpu_data.dcache.ways, - boot_cpu_data.dcache.sets, - boot_cpu_data.dcache.way_incr); - printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", - boot_cpu_data.dcache.entry_mask, - boot_cpu_data.dcache.alias_mask, - boot_cpu_data.dcache.n_aliases); + start = data->addr1; + end = data->addr2; - /* - * Emit Secondary Cache parameters if the CPU has a probed L2. - */ - if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) { - printk("S-cache : n_ways=%d n_sets=%d way_incr=%d\n", - boot_cpu_data.scache.ways, - boot_cpu_data.scache.sets, - boot_cpu_data.scache.way_incr); - printk("S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", - boot_cpu_data.scache.entry_mask, - boot_cpu_data.scache.alias_mask, - boot_cpu_data.scache.n_aliases); + /* If there are too many pages then just blow away the caches */ + if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { + local_flush_cache_all(NULL); + return; } - if (!__flush_dcache_segment_fn) - panic("unknown number of cache ways\n"); -} + /* + * Selectively flush d-cache then invalidate the i-cache. + * This is inefficient, so only use this for small ranges. + */ + start &= ~(L1_CACHE_BYTES-1); + end += L1_CACHE_BYTES-1; + end &= ~(L1_CACHE_BYTES-1); -/* - * SH-4 has virtually indexed and physically tagged cache. - */ -void __init p3_cache_init(void) -{ - compute_alias(&boot_cpu_data.icache); - compute_alias(&boot_cpu_data.dcache); - compute_alias(&boot_cpu_data.scache); - - switch (boot_cpu_data.dcache.ways) { - case 1: - __flush_dcache_segment_fn = __flush_dcache_segment_1way; - break; - case 2: - __flush_dcache_segment_fn = __flush_dcache_segment_2way; - break; - case 4: - __flush_dcache_segment_fn = __flush_dcache_segment_4way; - break; - default: - __flush_dcache_segment_fn = NULL; - break; - } + local_irq_save(flags); + jump_to_uncached(); - emit_cache_params(); -} + for (v = start; v < end; v += L1_CACHE_BYTES) { + unsigned long icacheaddr; -/* - * Write back the dirty D-caches, but not invalidate them. - * - * START: Virtual Address (U0, P1, or P3) - * SIZE: Size of the region. - */ -void __flush_wback_region(void *start, int size) -{ - unsigned long v; - unsigned long begin, end; - - begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); - end = ((unsigned long)start + size + L1_CACHE_BYTES-1) - & ~(L1_CACHE_BYTES-1); - for (v = begin; v < end; v+=L1_CACHE_BYTES) { - asm volatile("ocbwb %0" - : /* no output */ - : "m" (__m(v))); - } -} + __ocbwb(v); -/* - * Write back the dirty D-caches and invalidate them. - * - * START: Virtual Address (U0, P1, or P3) - * SIZE: Size of the region. - */ -void __flush_purge_region(void *start, int size) -{ - unsigned long v; - unsigned long begin, end; - - begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); - end = ((unsigned long)start + size + L1_CACHE_BYTES-1) - & ~(L1_CACHE_BYTES-1); - for (v = begin; v < end; v+=L1_CACHE_BYTES) { - asm volatile("ocbp %0" - : /* no output */ - : "m" (__m(v))); - } -} + icacheaddr = CACHE_IC_ADDRESS_ARRAY | (v & + cpu_data->icache.entry_mask); -/* - * No write back please - */ -void __flush_invalidate_region(void *start, int size) -{ - unsigned long v; - unsigned long begin, end; - - begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); - end = ((unsigned long)start + size + L1_CACHE_BYTES-1) - & ~(L1_CACHE_BYTES-1); - for (v = begin; v < end; v+=L1_CACHE_BYTES) { - asm volatile("ocbi %0" - : /* no output */ - : "m" (__m(v))); + /* Clear i-cache line valid-bit */ + for (i = 0; i < cpu_data->icache.ways; i++) { + __raw_writel(0, icacheaddr); + icacheaddr += cpu_data->icache.way_incr; + } } -} - -/* - * Write back the range of D-cache, and purge the I-cache. - * - * Called from kernel/module.c:sys_init_module and routine for a.out format, - * signal handler code and kprobes code - */ -void flush_icache_range(unsigned long start, unsigned long end) -{ - int icacheaddr; - unsigned long flags, v; - int i; - /* If there are too many pages then just blow the caches */ - if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { - flush_cache_all(); - } else { - /* selectively flush d-cache then invalidate the i-cache */ - /* this is inefficient, so only use for small ranges */ - start &= ~(L1_CACHE_BYTES-1); - end += L1_CACHE_BYTES-1; - end &= ~(L1_CACHE_BYTES-1); - - local_irq_save(flags); - jump_to_uncached(); - - for (v = start; v < end; v+=L1_CACHE_BYTES) { - asm volatile("ocbwb %0" - : /* no output */ - : "m" (__m(v))); - - icacheaddr = CACHE_IC_ADDRESS_ARRAY | ( - v & cpu_data->icache.entry_mask); - - for (i = 0; i < cpu_data->icache.ways; - i++, icacheaddr += cpu_data->icache.way_incr) - /* Clear i-cache line valid-bit */ - ctrl_outl(0, icacheaddr); - } - - back_to_cached(); - local_irq_restore(flags); - } + back_to_cached(); + local_irq_restore(flags); } static inline void flush_cache_4096(unsigned long start, @@ -244,9 +112,17 @@ static inline void flush_cache_4096(unsigned long start, * Write back & invalidate the D-cache of the page. * (To avoid "alias" issues) */ -void flush_dcache_page(struct page *page) +static void sh4_flush_dcache_page(void *arg) { - if (test_bit(PG_mapped, &page->flags)) { + struct page *page = arg; +#ifndef CONFIG_SMP + struct address_space *mapping = page_mapping(page); + + if (mapping && !mapping_mapped(mapping)) + set_bit(PG_dcache_dirty, &page->flags); + else +#endif + { unsigned long phys = PHYSADDR(page_address(page)); unsigned long addr = CACHE_OC_ADDRESS_ARRAY; int i, n; @@ -282,13 +158,13 @@ static void __uses_jump_to_uncached flush_icache_all(void) local_irq_restore(flags); } -void flush_dcache_all(void) +static inline void flush_dcache_all(void) { (*__flush_dcache_segment_fn)(0UL, boot_cpu_data.dcache.way_size); wmb(); } -void flush_cache_all(void) +static void sh4_flush_cache_all(void *unused) { flush_dcache_all(); flush_icache_all(); @@ -380,8 +256,13 @@ loop_exit: * * Caller takes mm->mmap_sem. */ -void flush_cache_mm(struct mm_struct *mm) +static void sh4_flush_cache_mm(void *arg) { + struct mm_struct *mm = arg; + + if (cpu_context(smp_processor_id(), mm) == NO_CONTEXT) + return; + /* * If cache is only 4k-per-way, there are never any 'aliases'. Since * the cache is physically tagged, the data can just be left in there. @@ -417,12 +298,21 @@ void flush_cache_mm(struct mm_struct *mm) * ADDR: Virtual Address (U0 address) * PFN: Physical page number */ -void flush_cache_page(struct vm_area_struct *vma, unsigned long address, - unsigned long pfn) +static void sh4_flush_cache_page(void *args) { - unsigned long phys = pfn << PAGE_SHIFT; + struct flusher_data *data = args; + struct vm_area_struct *vma; + unsigned long address, pfn, phys; unsigned int alias_mask; + vma = data->vma; + address = data->addr1; + pfn = data->addr2; + phys = pfn << PAGE_SHIFT; + + if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT) + return; + alias_mask = boot_cpu_data.dcache.alias_mask; /* We only need to flush D-cache when we have alias */ @@ -462,9 +352,19 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address, * Flushing the cache lines for U0 only isn't enough. * We need to flush for P1 too, which may contain aliases. */ -void flush_cache_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) +static void sh4_flush_cache_range(void *args) { + struct flusher_data *data = args; + struct vm_area_struct *vma; + unsigned long start, end; + + vma = data->vma; + start = data->addr1; + end = data->addr2; + + if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT) + return; + /* * If cache is only 4k-per-way, there are never any 'aliases'. Since * the cache is physically tagged, the data can just be left in there. @@ -492,20 +392,6 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, } } -/* - * flush_icache_user_range - * @vma: VMA of the process - * @page: page - * @addr: U0 address - * @len: length of the range (< page size) - */ -void flush_icache_user_range(struct vm_area_struct *vma, - struct page *page, unsigned long addr, int len) -{ - flush_cache_page(vma, addr, page_to_pfn(page)); - mb(); -} - /** * __flush_cache_4096 * @@ -581,7 +467,49 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys, * Break the 1, 2 and 4 way variants of this out into separate functions to * avoid nearly all the overhead of having the conditional stuff in the function * bodies (+ the 1 and 2 way cases avoid saving any registers too). + * + * We want to eliminate unnecessary bus transactions, so this code uses + * a non-obvious technique. + * + * Loop over a cache way sized block of, one cache line at a time. For each + * line, use movca.a to cause the current cache line contents to be written + * back, but without reading anything from main memory. However this has the + * side effect that the cache is now caching that memory location. So follow + * this with a cache invalidate to mark the cache line invalid. And do all + * this with interrupts disabled, to avoid the cache line being accidently + * evicted while it is holding garbage. + * + * This also breaks in a number of circumstances: + * - if there are modifications to the region of memory just above + * empty_zero_page (for example because a breakpoint has been placed + * there), then these can be lost. + * + * This is because the the memory address which the cache temporarily + * caches in the above description is empty_zero_page. So the + * movca.l hits the cache (it is assumed that it misses, or at least + * isn't dirty), modifies the line and then invalidates it, losing the + * required change. + * + * - If caches are disabled or configured in write-through mode, then + * the movca.l writes garbage directly into memory. */ +static void __flush_dcache_segment_writethrough(unsigned long start, + unsigned long extent_per_way) +{ + unsigned long addr; + int i; + + addr = CACHE_OC_ADDRESS_ARRAY | (start & cpu_data->dcache.entry_mask); + + while (extent_per_way) { + for (i = 0; i < cpu_data->dcache.ways; i++) + __raw_writel(0, addr + cpu_data->dcache.way_incr * i); + + addr += cpu_data->dcache.linesz; + extent_per_way -= cpu_data->dcache.linesz; + } +} + static void __flush_dcache_segment_1way(unsigned long start, unsigned long extent_per_way) { @@ -773,3 +701,47 @@ static void __flush_dcache_segment_4way(unsigned long start, a3 += linesz; } while (a0 < a0e); } + +extern void __weak sh4__flush_region_init(void); + +/* + * SH-4 has virtually indexed and physically tagged cache. + */ +void __init sh4_cache_init(void) +{ + unsigned int wt_enabled = !!(__raw_readl(CCR) & CCR_CACHE_WT); + + printk("PVR=%08x CVR=%08x PRR=%08x\n", + ctrl_inl(CCN_PVR), + ctrl_inl(CCN_CVR), + ctrl_inl(CCN_PRR)); + + if (wt_enabled) + __flush_dcache_segment_fn = __flush_dcache_segment_writethrough; + else { + switch (boot_cpu_data.dcache.ways) { + case 1: + __flush_dcache_segment_fn = __flush_dcache_segment_1way; + break; + case 2: + __flush_dcache_segment_fn = __flush_dcache_segment_2way; + break; + case 4: + __flush_dcache_segment_fn = __flush_dcache_segment_4way; + break; + default: + panic("unknown number of cache ways\n"); + break; + } + } + + local_flush_icache_range = sh4_flush_icache_range; + local_flush_dcache_page = sh4_flush_dcache_page; + local_flush_cache_all = sh4_flush_cache_all; + local_flush_cache_mm = sh4_flush_cache_mm; + local_flush_cache_dup_mm = sh4_flush_cache_mm; + local_flush_cache_page = sh4_flush_cache_page; + local_flush_cache_range = sh4_flush_cache_range; + + sh4__flush_region_init(); +} diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c index 86762092508c..467ff8e260f7 100644 --- a/arch/sh/mm/cache-sh5.c +++ b/arch/sh/mm/cache-sh5.c @@ -20,23 +20,11 @@ #include <asm/uaccess.h> #include <asm/mmu_context.h> +extern void __weak sh4__flush_region_init(void); + /* Wired TLB entry for the D-cache */ static unsigned long long dtlb_cache_slot; -void __init p3_cache_init(void) -{ - /* Reserve a slot for dcache colouring in the DTLB */ - dtlb_cache_slot = sh64_get_wired_dtlb_entry(); -} - -#ifdef CONFIG_DCACHE_DISABLED -#define sh64_dcache_purge_all() do { } while (0) -#define sh64_dcache_purge_coloured_phy_page(paddr, eaddr) do { } while (0) -#define sh64_dcache_purge_user_range(mm, start, end) do { } while (0) -#define sh64_dcache_purge_phy_page(paddr) do { } while (0) -#define sh64_dcache_purge_virt_page(mm, eaddr) do { } while (0) -#endif - /* * The following group of functions deal with mapping and unmapping a * temporary page into a DTLB slot that has been set aside for exclusive @@ -56,7 +44,6 @@ static inline void sh64_teardown_dtlb_cache_slot(void) local_irq_enable(); } -#ifndef CONFIG_ICACHE_DISABLED static inline void sh64_icache_inv_all(void) { unsigned long long addr, flag, data; @@ -214,52 +201,6 @@ static void sh64_icache_inv_user_page_range(struct mm_struct *mm, } } -/* - * Invalidate a small range of user context I-cache, not necessarily page - * (or even cache-line) aligned. - * - * Since this is used inside ptrace, the ASID in the mm context typically - * won't match current_asid. We'll have to switch ASID to do this. For - * safety, and given that the range will be small, do all this under cli. - * - * Note, there is a hazard that the ASID in mm->context is no longer - * actually associated with mm, i.e. if the mm->context has started a new - * cycle since mm was last active. However, this is just a performance - * issue: all that happens is that we invalidate lines belonging to - * another mm, so the owning process has to refill them when that mm goes - * live again. mm itself can't have any cache entries because there will - * have been a flush_cache_all when the new mm->context cycle started. - */ -static void sh64_icache_inv_user_small_range(struct mm_struct *mm, - unsigned long start, int len) -{ - unsigned long long eaddr = start; - unsigned long long eaddr_end = start + len; - unsigned long current_asid, mm_asid; - unsigned long flags; - unsigned long long epage_start; - - /* - * Align to start of cache line. Otherwise, suppose len==8 and - * start was at 32N+28 : the last 4 bytes wouldn't get invalidated. - */ - eaddr = L1_CACHE_ALIGN(start); - eaddr_end = start + len; - - mm_asid = cpu_asid(smp_processor_id(), mm); - local_irq_save(flags); - current_asid = switch_and_save_asid(mm_asid); - - epage_start = eaddr & PAGE_MASK; - - while (eaddr < eaddr_end) { - __asm__ __volatile__("icbi %0, 0" : : "r" (eaddr)); - eaddr += L1_CACHE_BYTES; - } - switch_and_save_asid(current_asid); - local_irq_restore(flags); -} - static void sh64_icache_inv_current_user_range(unsigned long start, unsigned long end) { /* The icbi instruction never raises ITLBMISS. i.e. if there's not a @@ -287,9 +228,7 @@ static void sh64_icache_inv_current_user_range(unsigned long start, unsigned lon addr += L1_CACHE_BYTES; } } -#endif /* !CONFIG_ICACHE_DISABLED */ -#ifndef CONFIG_DCACHE_DISABLED /* Buffer used as the target of alloco instructions to purge data from cache sets by natural eviction. -- RPC */ #define DUMMY_ALLOCO_AREA_SIZE ((L1_CACHE_BYTES << 10) + (1024 * 4)) @@ -541,59 +480,10 @@ static void sh64_dcache_purge_user_range(struct mm_struct *mm, } /* - * Purge the range of addresses from the D-cache. - * - * The addresses lie in the superpage mapping. There's no harm if we - * overpurge at either end - just a small performance loss. - */ -void __flush_purge_region(void *start, int size) -{ - unsigned long long ullend, addr, aligned_start; - - aligned_start = (unsigned long long)(signed long long)(signed long) start; - addr = L1_CACHE_ALIGN(aligned_start); - ullend = (unsigned long long) (signed long long) (signed long) start + size; - - while (addr <= ullend) { - __asm__ __volatile__ ("ocbp %0, 0" : : "r" (addr)); - addr += L1_CACHE_BYTES; - } -} - -void __flush_wback_region(void *start, int size) -{ - unsigned long long ullend, addr, aligned_start; - - aligned_start = (unsigned long long)(signed long long)(signed long) start; - addr = L1_CACHE_ALIGN(aligned_start); - ullend = (unsigned long long) (signed long long) (signed long) start + size; - - while (addr < ullend) { - __asm__ __volatile__ ("ocbwb %0, 0" : : "r" (addr)); - addr += L1_CACHE_BYTES; - } -} - -void __flush_invalidate_region(void *start, int size) -{ - unsigned long long ullend, addr, aligned_start; - - aligned_start = (unsigned long long)(signed long long)(signed long) start; - addr = L1_CACHE_ALIGN(aligned_start); - ullend = (unsigned long long) (signed long long) (signed long) start + size; - - while (addr < ullend) { - __asm__ __volatile__ ("ocbi %0, 0" : : "r" (addr)); - addr += L1_CACHE_BYTES; - } -} -#endif /* !CONFIG_DCACHE_DISABLED */ - -/* * Invalidate the entire contents of both caches, after writing back to * memory any dirty data from the D-cache. */ -void flush_cache_all(void) +static void sh5_flush_cache_all(void *unused) { sh64_dcache_purge_all(); sh64_icache_inv_all(); @@ -620,7 +510,7 @@ void flush_cache_all(void) * I-cache. This is similar to the lack of action needed in * flush_tlb_mm - see fault.c. */ -void flush_cache_mm(struct mm_struct *mm) +static void sh5_flush_cache_mm(void *unused) { sh64_dcache_purge_all(); } @@ -632,13 +522,18 @@ void flush_cache_mm(struct mm_struct *mm) * * Note, 'end' is 1 byte beyond the end of the range to flush. */ -void flush_cache_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) +static void sh5_flush_cache_range(void *args) { - struct mm_struct *mm = vma->vm_mm; + struct flusher_data *data = args; + struct vm_area_struct *vma; + unsigned long start, end; + + vma = data->vma; + start = data->addr1; + end = data->addr2; - sh64_dcache_purge_user_range(mm, start, end); - sh64_icache_inv_user_page_range(mm, start, end); + sh64_dcache_purge_user_range(vma->vm_mm, start, end); + sh64_icache_inv_user_page_range(vma->vm_mm, start, end); } /* @@ -650,16 +545,23 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, * * Note, this is called with pte lock held. */ -void flush_cache_page(struct vm_area_struct *vma, unsigned long eaddr, - unsigned long pfn) +static void sh5_flush_cache_page(void *args) { + struct flusher_data *data = args; + struct vm_area_struct *vma; + unsigned long eaddr, pfn; + + vma = data->vma; + eaddr = data->addr1; + pfn = data->addr2; + sh64_dcache_purge_phy_page(pfn << PAGE_SHIFT); if (vma->vm_flags & VM_EXEC) sh64_icache_inv_user_page(vma, eaddr); } -void flush_dcache_page(struct page *page) +static void sh5_flush_dcache_page(void *page) { sh64_dcache_purge_phy_page(page_to_phys(page)); wmb(); @@ -673,162 +575,47 @@ void flush_dcache_page(struct page *page) * mapping, therefore it's guaranteed that there no cache entries for * the range in cache sets of the wrong colour. */ -void flush_icache_range(unsigned long start, unsigned long end) +static void sh5_flush_icache_range(void *args) { + struct flusher_data *data = args; + unsigned long start, end; + + start = data->addr1; + end = data->addr2; + __flush_purge_region((void *)start, end); wmb(); sh64_icache_inv_kernel_range(start, end); } /* - * Flush the range of user (defined by vma->vm_mm) address space starting - * at 'addr' for 'len' bytes from the cache. The range does not straddle - * a page boundary, the unique physical page containing the range is - * 'page'. This seems to be used mainly for invalidating an address - * range following a poke into the program text through the ptrace() call - * from another process (e.g. for BRK instruction insertion). - */ -void flush_icache_user_range(struct vm_area_struct *vma, - struct page *page, unsigned long addr, int len) -{ - - sh64_dcache_purge_coloured_phy_page(page_to_phys(page), addr); - mb(); - - if (vma->vm_flags & VM_EXEC) - sh64_icache_inv_user_small_range(vma->vm_mm, addr, len); -} - -/* * For the address range [start,end), write back the data from the * D-cache and invalidate the corresponding region of the I-cache for the * current process. Used to flush signal trampolines on the stack to * make them executable. */ -void flush_cache_sigtramp(unsigned long vaddr) +static void sh5_flush_cache_sigtramp(void *vaddr) { - unsigned long end = vaddr + L1_CACHE_BYTES; + unsigned long end = (unsigned long)vaddr + L1_CACHE_BYTES; - __flush_wback_region((void *)vaddr, L1_CACHE_BYTES); + __flush_wback_region(vaddr, L1_CACHE_BYTES); wmb(); - sh64_icache_inv_current_user_range(vaddr, end); + sh64_icache_inv_current_user_range((unsigned long)vaddr, end); } -#ifdef CONFIG_MMU -/* - * These *MUST* lie in an area of virtual address space that's otherwise - * unused. - */ -#define UNIQUE_EADDR_START 0xe0000000UL -#define UNIQUE_EADDR_END 0xe8000000UL - -/* - * Given a physical address paddr, and a user virtual address user_eaddr - * which will eventually be mapped to it, create a one-off kernel-private - * eaddr mapped to the same paddr. This is used for creating special - * destination pages for copy_user_page and clear_user_page. - */ -static unsigned long sh64_make_unique_eaddr(unsigned long user_eaddr, - unsigned long paddr) -{ - static unsigned long current_pointer = UNIQUE_EADDR_START; - unsigned long coloured_pointer; - - if (current_pointer == UNIQUE_EADDR_END) { - sh64_dcache_purge_all(); - current_pointer = UNIQUE_EADDR_START; - } - - coloured_pointer = (current_pointer & ~CACHE_OC_SYN_MASK) | - (user_eaddr & CACHE_OC_SYN_MASK); - sh64_setup_dtlb_cache_slot(coloured_pointer, get_asid(), paddr); - - current_pointer += (PAGE_SIZE << CACHE_OC_N_SYNBITS); - - return coloured_pointer; -} - -static void sh64_copy_user_page_coloured(void *to, void *from, - unsigned long address) +void __init sh5_cache_init(void) { - void *coloured_to; + local_flush_cache_all = sh5_flush_cache_all; + local_flush_cache_mm = sh5_flush_cache_mm; + local_flush_cache_dup_mm = sh5_flush_cache_mm; + local_flush_cache_page = sh5_flush_cache_page; + local_flush_cache_range = sh5_flush_cache_range; + local_flush_dcache_page = sh5_flush_dcache_page; + local_flush_icache_range = sh5_flush_icache_range; + local_flush_cache_sigtramp = sh5_flush_cache_sigtramp; - /* - * Discard any existing cache entries of the wrong colour. These are - * present quite often, if the kernel has recently used the page - * internally, then given it up, then it's been allocated to the user. - */ - sh64_dcache_purge_coloured_phy_page(__pa(to), (unsigned long)to); - - coloured_to = (void *)sh64_make_unique_eaddr(address, __pa(to)); - copy_page(from, coloured_to); - - sh64_teardown_dtlb_cache_slot(); -} - -static void sh64_clear_user_page_coloured(void *to, unsigned long address) -{ - void *coloured_to; - - /* - * Discard any existing kernel-originated lines of the wrong - * colour (as above) - */ - sh64_dcache_purge_coloured_phy_page(__pa(to), (unsigned long)to); - - coloured_to = (void *)sh64_make_unique_eaddr(address, __pa(to)); - clear_page(coloured_to); - - sh64_teardown_dtlb_cache_slot(); -} - -/* - * 'from' and 'to' are kernel virtual addresses (within the superpage - * mapping of the physical RAM). 'address' is the user virtual address - * where the copy 'to' will be mapped after. This allows a custom - * mapping to be used to ensure that the new copy is placed in the - * right cache sets for the user to see it without having to bounce it - * out via memory. Note however : the call to flush_page_to_ram in - * (generic)/mm/memory.c:(break_cow) undoes all this good work in that one - * very important case! - * - * TBD : can we guarantee that on every call, any cache entries for - * 'from' are in the same colour sets as 'address' also? i.e. is this - * always used just to deal with COW? (I suspect not). - * - * There are two possibilities here for when the page 'from' was last accessed: - * - by the kernel : this is OK, no purge required. - * - by the/a user (e.g. for break_COW) : need to purge. - * - * If the potential user mapping at 'address' is the same colour as - * 'from' there is no need to purge any cache lines from the 'from' - * page mapped into cache sets of colour 'address'. (The copy will be - * accessing the page through 'from'). - */ -void copy_user_page(void *to, void *from, unsigned long address, - struct page *page) -{ - if (((address ^ (unsigned long) from) & CACHE_OC_SYN_MASK) != 0) - sh64_dcache_purge_coloured_phy_page(__pa(from), address); - - if (((address ^ (unsigned long) to) & CACHE_OC_SYN_MASK) == 0) - copy_page(to, from); - else - sh64_copy_user_page_coloured(to, from, address); -} + /* Reserve a slot for dcache colouring in the DTLB */ + dtlb_cache_slot = sh64_get_wired_dtlb_entry(); -/* - * 'to' is a kernel virtual address (within the superpage mapping of the - * physical RAM). 'address' is the user virtual address where the 'to' - * page will be mapped after. This allows a custom mapping to be used to - * ensure that the new copy is placed in the right cache sets for the - * user to see it without having to bounce it out via memory. - */ -void clear_user_page(void *to, unsigned long address, struct page *page) -{ - if (((address ^ (unsigned long) to) & CACHE_OC_SYN_MASK) == 0) - clear_page(to); - else - sh64_clear_user_page_coloured(to, address); + sh4__flush_region_init(); } -#endif diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c index 22dacc778823..2cadee2037ac 100644 --- a/arch/sh/mm/cache-sh7705.c +++ b/arch/sh/mm/cache-sh7705.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/mman.h> #include <linux/mm.h> +#include <linux/fs.h> #include <linux/threads.h> #include <asm/addrspace.h> #include <asm/page.h> @@ -63,15 +64,21 @@ static inline void cache_wback_all(void) * * Called from kernel/module.c:sys_init_module and routine for a.out format. */ -void flush_icache_range(unsigned long start, unsigned long end) +static void sh7705_flush_icache_range(void *args) { + struct flusher_data *data = args; + unsigned long start, end; + + start = data->addr1; + end = data->addr2; + __flush_wback_region((void *)start, end - start); } /* * Writeback&Invalidate the D-cache of the page */ -static void __uses_jump_to_uncached __flush_dcache_page(unsigned long phys) +static void __flush_dcache_page(unsigned long phys) { unsigned long ways, waysize, addrstart; unsigned long flags; @@ -126,13 +133,18 @@ static void __uses_jump_to_uncached __flush_dcache_page(unsigned long phys) * Write back & invalidate the D-cache of the page. * (To avoid "alias" issues) */ -void flush_dcache_page(struct page *page) +static void sh7705_flush_dcache_page(void *arg) { - if (test_bit(PG_mapped, &page->flags)) + struct page *page = arg; + struct address_space *mapping = page_mapping(page); + + if (mapping && !mapping_mapped(mapping)) + set_bit(PG_dcache_dirty, &page->flags); + else __flush_dcache_page(PHYSADDR(page_address(page))); } -void __uses_jump_to_uncached flush_cache_all(void) +static void sh7705_flush_cache_all(void *args) { unsigned long flags; @@ -144,44 +156,16 @@ void __uses_jump_to_uncached flush_cache_all(void) local_irq_restore(flags); } -void flush_cache_mm(struct mm_struct *mm) -{ - /* Is there any good way? */ - /* XXX: possibly call flush_cache_range for each vm area */ - flush_cache_all(); -} - -/* - * Write back and invalidate D-caches. - * - * START, END: Virtual Address (U0 address) - * - * NOTE: We need to flush the _physical_ page entry. - * Flushing the cache lines for U0 only isn't enough. - * We need to flush for P1 too, which may contain aliases. - */ -void flush_cache_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - - /* - * We could call flush_cache_page for the pages of these range, - * but it's not efficient (scan the caches all the time...). - * - * We can't use A-bit magic, as there's the case we don't have - * valid entry on TLB. - */ - flush_cache_all(); -} - /* * Write back and invalidate I/D-caches for the page. * * ADDRESS: Virtual Address (U0 address) */ -void flush_cache_page(struct vm_area_struct *vma, unsigned long address, - unsigned long pfn) +static void sh7705_flush_cache_page(void *args) { + struct flusher_data *data = args; + unsigned long pfn = data->addr2; + __flush_dcache_page(pfn << PAGE_SHIFT); } @@ -193,7 +177,19 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address, * Not entirely sure why this is necessary on SH3 with 32K cache but * without it we get occasional "Memory fault" when loading a program. */ -void flush_icache_page(struct vm_area_struct *vma, struct page *page) +static void sh7705_flush_icache_page(void *page) { __flush_purge_region(page_address(page), PAGE_SIZE); } + +void __init sh7705_cache_init(void) +{ + local_flush_icache_range = sh7705_flush_icache_range; + local_flush_dcache_page = sh7705_flush_dcache_page; + local_flush_cache_all = sh7705_flush_cache_all; + local_flush_cache_mm = sh7705_flush_cache_all; + local_flush_cache_dup_mm = sh7705_flush_cache_all; + local_flush_cache_range = sh7705_flush_cache_all; + local_flush_cache_page = sh7705_flush_cache_page; + local_flush_icache_page = sh7705_flush_icache_page; +} diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c new file mode 100644 index 000000000000..35c37b7f717a --- /dev/null +++ b/arch/sh/mm/cache.c @@ -0,0 +1,316 @@ +/* + * arch/sh/mm/cache.c + * + * Copyright (C) 1999, 2000, 2002 Niibe Yutaka + * Copyright (C) 2002 - 2009 Paul Mundt + * + * Released under the terms of the GNU GPL v2.0. + */ +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/mutex.h> +#include <linux/fs.h> +#include <linux/smp.h> +#include <linux/highmem.h> +#include <linux/module.h> +#include <asm/mmu_context.h> +#include <asm/cacheflush.h> + +void (*local_flush_cache_all)(void *args) = cache_noop; +void (*local_flush_cache_mm)(void *args) = cache_noop; +void (*local_flush_cache_dup_mm)(void *args) = cache_noop; +void (*local_flush_cache_page)(void *args) = cache_noop; +void (*local_flush_cache_range)(void *args) = cache_noop; +void (*local_flush_dcache_page)(void *args) = cache_noop; +void (*local_flush_icache_range)(void *args) = cache_noop; +void (*local_flush_icache_page)(void *args) = cache_noop; +void (*local_flush_cache_sigtramp)(void *args) = cache_noop; + +void (*__flush_wback_region)(void *start, int size); +void (*__flush_purge_region)(void *start, int size); +void (*__flush_invalidate_region)(void *start, int size); + +static inline void noop__flush_region(void *start, int size) +{ +} + +static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info, + int wait) +{ + preempt_disable(); + smp_call_function(func, info, wait); + func(info); + preempt_enable(); +} + +void copy_to_user_page(struct vm_area_struct *vma, struct page *page, + unsigned long vaddr, void *dst, const void *src, + unsigned long len) +{ + if (boot_cpu_data.dcache.n_aliases && page_mapped(page) && + !test_bit(PG_dcache_dirty, &page->flags)) { + void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(vto, src, len); + kunmap_coherent(vto); + } else { + memcpy(dst, src, len); + if (boot_cpu_data.dcache.n_aliases) + set_bit(PG_dcache_dirty, &page->flags); + } + + if (vma->vm_flags & VM_EXEC) + flush_cache_page(vma, vaddr, page_to_pfn(page)); +} + +void copy_from_user_page(struct vm_area_struct *vma, struct page *page, + unsigned long vaddr, void *dst, const void *src, + unsigned long len) +{ + if (boot_cpu_data.dcache.n_aliases && page_mapped(page) && + !test_bit(PG_dcache_dirty, &page->flags)) { + void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(dst, vfrom, len); + kunmap_coherent(vfrom); + } else { + memcpy(dst, src, len); + if (boot_cpu_data.dcache.n_aliases) + set_bit(PG_dcache_dirty, &page->flags); + } +} + +void copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr, struct vm_area_struct *vma) +{ + void *vfrom, *vto; + + vto = kmap_atomic(to, KM_USER1); + + if (boot_cpu_data.dcache.n_aliases && page_mapped(from) && + !test_bit(PG_dcache_dirty, &from->flags)) { + vfrom = kmap_coherent(from, vaddr); + copy_page(vto, vfrom); + kunmap_coherent(vfrom); + } else { + vfrom = kmap_atomic(from, KM_USER0); + copy_page(vto, vfrom); + kunmap_atomic(vfrom, KM_USER0); + } + + if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) + __flush_purge_region(vto, PAGE_SIZE); + + kunmap_atomic(vto, KM_USER1); + /* Make sure this page is cleared on other CPU's too before using it */ + smp_wmb(); +} +EXPORT_SYMBOL(copy_user_highpage); + +void clear_user_highpage(struct page *page, unsigned long vaddr) +{ + void *kaddr = kmap_atomic(page, KM_USER0); + + clear_page(kaddr); + + if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK)) + __flush_purge_region(kaddr, PAGE_SIZE); + + kunmap_atomic(kaddr, KM_USER0); +} +EXPORT_SYMBOL(clear_user_highpage); + +void __update_cache(struct vm_area_struct *vma, + unsigned long address, pte_t pte) +{ + struct page *page; + unsigned long pfn = pte_pfn(pte); + + if (!boot_cpu_data.dcache.n_aliases) + return; + + page = pfn_to_page(pfn); + if (pfn_valid(pfn) && page_mapping(page)) { + int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); + if (dirty) { + unsigned long addr = (unsigned long)page_address(page); + + if (pages_do_alias(addr, address & PAGE_MASK)) + __flush_purge_region((void *)addr, PAGE_SIZE); + } + } +} + +void __flush_anon_page(struct page *page, unsigned long vmaddr) +{ + unsigned long addr = (unsigned long) page_address(page); + + if (pages_do_alias(addr, vmaddr)) { + if (boot_cpu_data.dcache.n_aliases && page_mapped(page) && + !test_bit(PG_dcache_dirty, &page->flags)) { + void *kaddr; + + kaddr = kmap_coherent(page, vmaddr); + /* XXX.. For now kunmap_coherent() does a purge */ + /* __flush_purge_region((void *)kaddr, PAGE_SIZE); */ + kunmap_coherent(kaddr); + } else + __flush_purge_region((void *)addr, PAGE_SIZE); + } +} + +void flush_cache_all(void) +{ + cacheop_on_each_cpu(local_flush_cache_all, NULL, 1); +} + +void flush_cache_mm(struct mm_struct *mm) +{ + cacheop_on_each_cpu(local_flush_cache_mm, mm, 1); +} + +void flush_cache_dup_mm(struct mm_struct *mm) +{ + cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1); +} + +void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn) +{ + struct flusher_data data; + + data.vma = vma; + data.addr1 = addr; + data.addr2 = pfn; + + cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1); +} + +void flush_cache_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + struct flusher_data data; + + data.vma = vma; + data.addr1 = start; + data.addr2 = end; + + cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1); +} + +void flush_dcache_page(struct page *page) +{ + cacheop_on_each_cpu(local_flush_dcache_page, page, 1); +} + +void flush_icache_range(unsigned long start, unsigned long end) +{ + struct flusher_data data; + + data.vma = NULL; + data.addr1 = start; + data.addr2 = end; + + cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1); +} + +void flush_icache_page(struct vm_area_struct *vma, struct page *page) +{ + /* Nothing uses the VMA, so just pass the struct page along */ + cacheop_on_each_cpu(local_flush_icache_page, page, 1); +} + +void flush_cache_sigtramp(unsigned long address) +{ + cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1); +} + +static void compute_alias(struct cache_info *c) +{ + c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1); + c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0; +} + +static void __init emit_cache_params(void) +{ + printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n", + boot_cpu_data.icache.ways, + boot_cpu_data.icache.sets, + boot_cpu_data.icache.way_incr); + printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", + boot_cpu_data.icache.entry_mask, + boot_cpu_data.icache.alias_mask, + boot_cpu_data.icache.n_aliases); + printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n", + boot_cpu_data.dcache.ways, + boot_cpu_data.dcache.sets, + boot_cpu_data.dcache.way_incr); + printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", + boot_cpu_data.dcache.entry_mask, + boot_cpu_data.dcache.alias_mask, + boot_cpu_data.dcache.n_aliases); + + /* + * Emit Secondary Cache parameters if the CPU has a probed L2. + */ + if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) { + printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n", + boot_cpu_data.scache.ways, + boot_cpu_data.scache.sets, + boot_cpu_data.scache.way_incr); + printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n", + boot_cpu_data.scache.entry_mask, + boot_cpu_data.scache.alias_mask, + boot_cpu_data.scache.n_aliases); + } +} + +void __init cpu_cache_init(void) +{ + compute_alias(&boot_cpu_data.icache); + compute_alias(&boot_cpu_data.dcache); + compute_alias(&boot_cpu_data.scache); + + __flush_wback_region = noop__flush_region; + __flush_purge_region = noop__flush_region; + __flush_invalidate_region = noop__flush_region; + + if (boot_cpu_data.family == CPU_FAMILY_SH2) { + extern void __weak sh2_cache_init(void); + + sh2_cache_init(); + } + + if (boot_cpu_data.family == CPU_FAMILY_SH2A) { + extern void __weak sh2a_cache_init(void); + + sh2a_cache_init(); + } + + if (boot_cpu_data.family == CPU_FAMILY_SH3) { + extern void __weak sh3_cache_init(void); + + sh3_cache_init(); + + if ((boot_cpu_data.type == CPU_SH7705) && + (boot_cpu_data.dcache.sets == 512)) { + extern void __weak sh7705_cache_init(void); + + sh7705_cache_init(); + } + } + + if ((boot_cpu_data.family == CPU_FAMILY_SH4) || + (boot_cpu_data.family == CPU_FAMILY_SH4A) || + (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) { + extern void __weak sh4_cache_init(void); + + sh4_cache_init(); + } + + if (boot_cpu_data.family == CPU_FAMILY_SH5) { + extern void __weak sh5_cache_init(void); + + sh5_cache_init(); + } + + emit_cache_params(); +} diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index 71925946f1e1..781b413ff82d 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -2,7 +2,7 @@ * Page fault handler for SH with an MMU. * * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2003 - 2008 Paul Mundt + * Copyright (C) 2003 - 2009 Paul Mundt * * Based on linux/arch/i386/mm/fault.c: * Copyright (C) 1995 Linus Torvalds @@ -25,18 +25,91 @@ static inline int notify_page_fault(struct pt_regs *regs, int trap) { int ret = 0; -#ifdef CONFIG_KPROBES - if (!user_mode(regs)) { + if (kprobes_built_in() && !user_mode(regs)) { preempt_disable(); if (kprobe_running() && kprobe_fault_handler(regs, trap)) ret = 1; preempt_enable(); } -#endif return ret; } +static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address) +{ + unsigned index = pgd_index(address); + pgd_t *pgd_k; + pud_t *pud, *pud_k; + pmd_t *pmd, *pmd_k; + + pgd += index; + pgd_k = init_mm.pgd + index; + + if (!pgd_present(*pgd_k)) + return NULL; + + pud = pud_offset(pgd, address); + pud_k = pud_offset(pgd_k, address); + if (!pud_present(*pud_k)) + return NULL; + + pmd = pmd_offset(pud, address); + pmd_k = pmd_offset(pud_k, address); + if (!pmd_present(*pmd_k)) + return NULL; + + if (!pmd_present(*pmd)) + set_pmd(pmd, *pmd_k); + else { + /* + * The page tables are fully synchronised so there must + * be another reason for the fault. Return NULL here to + * signal that we have not taken care of the fault. + */ + BUG_ON(pmd_page(*pmd) != pmd_page(*pmd_k)); + return NULL; + } + + return pmd_k; +} + +/* + * Handle a fault on the vmalloc or module mapping area + */ +static noinline int vmalloc_fault(unsigned long address) +{ + pgd_t *pgd_k; + pmd_t *pmd_k; + pte_t *pte_k; + + /* Make sure we are in vmalloc/module/P3 area: */ + if (!(address >= VMALLOC_START && address < P3_ADDR_MAX)) + return -1; + + /* + * Synchronize this task's top level page-table + * with the 'reference' page table. + * + * Do _not_ use "current" here. We might be inside + * an interrupt in the middle of a task switch.. + */ + pgd_k = get_TTB(); + pmd_k = vmalloc_sync_one(pgd_k, address); + if (!pmd_k) + return -1; + + pte_k = pte_offset_kernel(pmd_k, address); + if (!pte_present(*pte_k)) + return -1; + + return 0; +} + +static int fault_in_kernel_space(unsigned long address) +{ + return address >= TASK_SIZE; +} + /* * This routine handles page faults. It determines the address, * and the problem, and then passes it off to one of the appropriate @@ -46,6 +119,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long writeaccess, unsigned long address) { + unsigned long vec; struct task_struct *tsk; struct mm_struct *mm; struct vm_area_struct * vma; @@ -53,59 +127,30 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, int fault; siginfo_t info; - /* - * We don't bother with any notifier callbacks here, as they are - * all handled through the __do_page_fault() fast-path. - */ - tsk = current; + mm = tsk->mm; si_code = SEGV_MAPERR; + vec = lookup_exception_vector(); - if (unlikely(address >= TASK_SIZE)) { - /* - * Synchronize this task's top level page-table - * with the 'reference' page table. - * - * Do _not_ use "tsk" here. We might be inside - * an interrupt in the middle of a task switch.. - */ - int offset = pgd_index(address); - pgd_t *pgd, *pgd_k; - pud_t *pud, *pud_k; - pmd_t *pmd, *pmd_k; - - pgd = get_TTB() + offset; - pgd_k = swapper_pg_dir + offset; - - if (!pgd_present(*pgd)) { - if (!pgd_present(*pgd_k)) - goto bad_area_nosemaphore; - set_pgd(pgd, *pgd_k); + /* + * We fault-in kernel-space virtual memory on-demand. The + * 'reference' page table is init_mm.pgd. + * + * NOTE! We MUST NOT take any locks for this case. We may + * be in an interrupt or a critical region, and should + * only copy the information from the master page table, + * nothing more. + */ + if (unlikely(fault_in_kernel_space(address))) { + if (vmalloc_fault(address) >= 0) return; - } - - pud = pud_offset(pgd, address); - pud_k = pud_offset(pgd_k, address); - - if (!pud_present(*pud)) { - if (!pud_present(*pud_k)) - goto bad_area_nosemaphore; - set_pud(pud, *pud_k); + if (notify_page_fault(regs, vec)) return; - } - pmd = pmd_offset(pud, address); - pmd_k = pmd_offset(pud_k, address); - if (pmd_present(*pmd) || !pmd_present(*pmd_k)) - goto bad_area_nosemaphore; - set_pmd(pmd, *pmd_k); - - return; + goto bad_area_nosemaphore; } - mm = tsk->mm; - - if (unlikely(notify_page_fault(regs, lookup_exception_vector()))) + if (unlikely(notify_page_fault(regs, vec))) return; /* Only enable interrupts if they were on before the fault */ @@ -115,8 +160,8 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); /* - * If we're in an interrupt or have no user - * context, we must not take the fault.. + * If we're in an interrupt, have no user context or are running + * in an atomic region then we must not take the fault: */ if (in_atomic() || !mm) goto no_context; @@ -132,10 +177,11 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, goto bad_area; if (expand_stack(vma, address)) goto bad_area; -/* - * Ok, we have a good vm_area for this memory access, so - * we can handle it.. - */ + + /* + * Ok, we have a good vm_area for this memory access, so + * we can handle it.. + */ good_area: si_code = SEGV_ACCERR; if (writeaccess) { @@ -173,10 +219,10 @@ survive: up_read(&mm->mmap_sem); return; -/* - * Something tried to access memory that isn't in our memory map.. - * Fix it, but check if it's kernel or user first.. - */ + /* + * Something tried to access memory that isn't in our memory map.. + * Fix it, but check if it's kernel or user first.. + */ bad_area: up_read(&mm->mmap_sem); @@ -272,16 +318,15 @@ do_sigbus: /* * Called with interrupts disabled. */ -asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs, - unsigned long writeaccess, - unsigned long address) +asmlinkage int __kprobes +handle_tlbmiss(struct pt_regs *regs, unsigned long writeaccess, + unsigned long address) { pgd_t *pgd; pud_t *pud; pmd_t *pmd; pte_t *pte; pte_t entry; - int ret = 1; /* * We don't take page faults for P1, P2, and parts of P4, these @@ -292,40 +337,41 @@ asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs, pgd = pgd_offset_k(address); } else { if (unlikely(address >= TASK_SIZE || !current->mm)) - goto out; + return 1; pgd = pgd_offset(current->mm, address); } pud = pud_offset(pgd, address); if (pud_none_or_clear_bad(pud)) - goto out; + return 1; pmd = pmd_offset(pud, address); if (pmd_none_or_clear_bad(pmd)) - goto out; + return 1; pte = pte_offset_kernel(pmd, address); entry = *pte; if (unlikely(pte_none(entry) || pte_not_present(entry))) - goto out; + return 1; if (unlikely(writeaccess && !pte_write(entry))) - goto out; + return 1; if (writeaccess) entry = pte_mkdirty(entry); entry = pte_mkyoung(entry); + set_pte(pte, entry); + #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SMP) /* - * ITLB is not affected by "ldtlb" instruction. - * So, we need to flush the entry by ourselves. + * SH-4 does not set MMUCR.RC to the corresponding TLB entry in + * the case of an initial page write exception, so we need to + * flush it in order to avoid potential TLB entry duplication. */ - local_flush_tlb_one(get_asid(), address & PAGE_MASK); + if (writeaccess == 2) + local_flush_tlb_one(get_asid(), address & PAGE_MASK); #endif - set_pte(pte, entry); update_mmu_cache(NULL, address, entry); - ret = 0; -out: - return ret; + return 0; } diff --git a/arch/sh/mm/fault_64.c b/arch/sh/mm/fault_64.c index bd63b961b2a9..2b356cec2489 100644 --- a/arch/sh/mm/fault_64.c +++ b/arch/sh/mm/fault_64.c @@ -56,16 +56,7 @@ inline void __do_tlb_refill(unsigned long address, /* * Set PTEH register */ - pteh = address & MMU_VPN_MASK; - - /* Sign extend based on neff. */ -#if (NEFF == 32) - /* Faster sign extension */ - pteh = (unsigned long long)(signed long long)(signed long)pteh; -#else - /* General case */ - pteh = (pteh & NEFF_SIGN) ? (pteh | NEFF_MASK) : pteh; -#endif + pteh = neff_sign_extend(address & MMU_VPN_MASK); /* Set the ASID. */ pteh |= get_asid() << PTEH_ASID_SHIFT; diff --git a/arch/sh/mm/flush-sh4.c b/arch/sh/mm/flush-sh4.c new file mode 100644 index 000000000000..cef402678f42 --- /dev/null +++ b/arch/sh/mm/flush-sh4.c @@ -0,0 +1,108 @@ +#include <linux/mm.h> +#include <asm/mmu_context.h> +#include <asm/cacheflush.h> + +/* + * Write back the dirty D-caches, but not invalidate them. + * + * START: Virtual Address (U0, P1, or P3) + * SIZE: Size of the region. + */ +static void sh4__flush_wback_region(void *start, int size) +{ + reg_size_t aligned_start, v, cnt, end; + + aligned_start = register_align(start); + v = aligned_start & ~(L1_CACHE_BYTES-1); + end = (aligned_start + size + L1_CACHE_BYTES-1) + & ~(L1_CACHE_BYTES-1); + cnt = (end - v) / L1_CACHE_BYTES; + + while (cnt >= 8) { + __ocbwb(v); v += L1_CACHE_BYTES; + __ocbwb(v); v += L1_CACHE_BYTES; + __ocbwb(v); v += L1_CACHE_BYTES; + __ocbwb(v); v += L1_CACHE_BYTES; + __ocbwb(v); v += L1_CACHE_BYTES; + __ocbwb(v); v += L1_CACHE_BYTES; + __ocbwb(v); v += L1_CACHE_BYTES; + __ocbwb(v); v += L1_CACHE_BYTES; + cnt -= 8; + } + + while (cnt) { + __ocbwb(v); v += L1_CACHE_BYTES; + cnt--; + } +} + +/* + * Write back the dirty D-caches and invalidate them. + * + * START: Virtual Address (U0, P1, or P3) + * SIZE: Size of the region. + */ +static void sh4__flush_purge_region(void *start, int size) +{ + reg_size_t aligned_start, v, cnt, end; + + aligned_start = register_align(start); + v = aligned_start & ~(L1_CACHE_BYTES-1); + end = (aligned_start + size + L1_CACHE_BYTES-1) + & ~(L1_CACHE_BYTES-1); + cnt = (end - v) / L1_CACHE_BYTES; + + while (cnt >= 8) { + __ocbp(v); v += L1_CACHE_BYTES; + __ocbp(v); v += L1_CACHE_BYTES; + __ocbp(v); v += L1_CACHE_BYTES; + __ocbp(v); v += L1_CACHE_BYTES; + __ocbp(v); v += L1_CACHE_BYTES; + __ocbp(v); v += L1_CACHE_BYTES; + __ocbp(v); v += L1_CACHE_BYTES; + __ocbp(v); v += L1_CACHE_BYTES; + cnt -= 8; + } + while (cnt) { + __ocbp(v); v += L1_CACHE_BYTES; + cnt--; + } +} + +/* + * No write back please + */ +static void sh4__flush_invalidate_region(void *start, int size) +{ + reg_size_t aligned_start, v, cnt, end; + + aligned_start = register_align(start); + v = aligned_start & ~(L1_CACHE_BYTES-1); + end = (aligned_start + size + L1_CACHE_BYTES-1) + & ~(L1_CACHE_BYTES-1); + cnt = (end - v) / L1_CACHE_BYTES; + + while (cnt >= 8) { + __ocbi(v); v += L1_CACHE_BYTES; + __ocbi(v); v += L1_CACHE_BYTES; + __ocbi(v); v += L1_CACHE_BYTES; + __ocbi(v); v += L1_CACHE_BYTES; + __ocbi(v); v += L1_CACHE_BYTES; + __ocbi(v); v += L1_CACHE_BYTES; + __ocbi(v); v += L1_CACHE_BYTES; + __ocbi(v); v += L1_CACHE_BYTES; + cnt -= 8; + } + + while (cnt) { + __ocbi(v); v += L1_CACHE_BYTES; + cnt--; + } +} + +void __init sh4__flush_region_init(void) +{ + __flush_wback_region = sh4__flush_wback_region; + __flush_invalidate_region = sh4__flush_invalidate_region; + __flush_purge_region = sh4__flush_purge_region; +} diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index fe532aeaa16d..edc842ff61ed 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -106,27 +106,31 @@ void __init page_table_range_init(unsigned long start, unsigned long end, pgd_t *pgd; pud_t *pud; pmd_t *pmd; - int pgd_idx; + pte_t *pte; + int i, j, k; unsigned long vaddr; - vaddr = start & PMD_MASK; - end = (end + PMD_SIZE - 1) & PMD_MASK; - pgd_idx = pgd_index(vaddr); - pgd = pgd_base + pgd_idx; - - for ( ; (pgd_idx < PTRS_PER_PGD) && (vaddr != end); pgd++, pgd_idx++) { - BUG_ON(pgd_none(*pgd)); - pud = pud_offset(pgd, 0); - BUG_ON(pud_none(*pud)); - pmd = pmd_offset(pud, 0); - - if (!pmd_present(*pmd)) { - pte_t *pte_table; - pte_table = (pte_t *)alloc_bootmem_low_pages(PAGE_SIZE); - pmd_populate_kernel(&init_mm, pmd, pte_table); + vaddr = start; + i = __pgd_offset(vaddr); + j = __pud_offset(vaddr); + k = __pmd_offset(vaddr); + pgd = pgd_base + i; + + for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) { + pud = (pud_t *)pgd; + for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) { + pmd = (pmd_t *)pud; + for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) { + if (pmd_none(*pmd)) { + pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); + pmd_populate_kernel(&init_mm, pmd, pte); + BUG_ON(pte != pte_offset_kernel(pmd, 0)); + } + vaddr += PMD_SIZE; + } + k = 0; } - - vaddr += PMD_SIZE; + j = 0; } } #endif /* CONFIG_MMU */ @@ -137,7 +141,7 @@ void __init page_table_range_init(unsigned long start, unsigned long end, void __init paging_init(void) { unsigned long max_zone_pfns[MAX_NR_ZONES]; - unsigned long vaddr; + unsigned long vaddr, end; int nid; /* We don't need to map the kernel through the TLB, as @@ -155,7 +159,8 @@ void __init paging_init(void) * pte's will be filled in by __set_fixmap(). */ vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK; - page_table_range_init(vaddr, 0, swapper_pg_dir); + end = (FIXADDR_TOP + PMD_SIZE - 1) & PMD_MASK; + page_table_range_init(vaddr, end, swapper_pg_dir); kmap_coherent_init(); @@ -210,6 +215,9 @@ void __init mem_init(void) high_memory = node_high_memory; } + /* Set this up early, so we can take care of the zero page */ + cpu_cache_init(); + /* clear the zero-page */ memset(empty_zero_page, 0, PAGE_SIZE); __flush_wback_region(empty_zero_page, PAGE_SIZE); @@ -230,8 +238,6 @@ void __init mem_init(void) datasize >> 10, initsize >> 10); - p3_cache_init(); - /* Initialize the vDSO */ vsyscall_init(); } diff --git a/arch/sh/mm/ioremap_32.c b/arch/sh/mm/ioremap_32.c index da2f4186f2cd..c3250614e3ae 100644 --- a/arch/sh/mm/ioremap_32.c +++ b/arch/sh/mm/ioremap_32.c @@ -57,14 +57,6 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size, if (is_pci_memory_fixed_range(phys_addr, size)) return (void __iomem *)phys_addr; -#if !defined(CONFIG_PMB_FIXED) - /* - * Don't allow anybody to remap normal RAM that we're using.. - */ - if (phys_addr < virt_to_phys(high_memory)) - return NULL; -#endif - /* * Mappings have to be page-aligned */ diff --git a/arch/sh/mm/ioremap_64.c b/arch/sh/mm/ioremap_64.c index 828c8597219d..b16843d02b76 100644 --- a/arch/sh/mm/ioremap_64.c +++ b/arch/sh/mm/ioremap_64.c @@ -94,7 +94,6 @@ static struct resource *shmedia_find_resource(struct resource *root, static void __iomem *shmedia_alloc_io(unsigned long phys, unsigned long size, const char *name, unsigned long flags) { - static int printed_full; struct xresource *xres; struct resource *res; char *tack; @@ -108,11 +107,8 @@ static void __iomem *shmedia_alloc_io(unsigned long phys, unsigned long size, tack = xres->xname; res = &xres->xres; } else { - if (!printed_full) { - printk(KERN_NOTICE "%s: done with statics, " + printk_once(KERN_NOTICE "%s: done with statics, " "switching to kmalloc\n", __func__); - printed_full = 1; - } tlen = strlen(name); tack = kmalloc(sizeof(struct resource) + tlen + 1, GFP_KERNEL); if (!tack) diff --git a/arch/sh/mm/kmap.c b/arch/sh/mm/kmap.c new file mode 100644 index 000000000000..16e01b5fed04 --- /dev/null +++ b/arch/sh/mm/kmap.c @@ -0,0 +1,65 @@ +/* + * arch/sh/mm/kmap.c + * + * Copyright (C) 1999, 2000, 2002 Niibe Yutaka + * Copyright (C) 2002 - 2009 Paul Mundt + * + * Released under the terms of the GNU GPL v2.0. + */ +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/mutex.h> +#include <linux/fs.h> +#include <linux/highmem.h> +#include <linux/module.h> +#include <asm/mmu_context.h> +#include <asm/cacheflush.h> + +#define kmap_get_fixmap_pte(vaddr) \ + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) + +static pte_t *kmap_coherent_pte; + +void __init kmap_coherent_init(void) +{ + unsigned long vaddr; + + /* cache the first coherent kmap pte */ + vaddr = __fix_to_virt(FIX_CMAP_BEGIN); + kmap_coherent_pte = kmap_get_fixmap_pte(vaddr); +} + +void *kmap_coherent(struct page *page, unsigned long addr) +{ + enum fixed_addresses idx; + unsigned long vaddr; + + BUG_ON(test_bit(PG_dcache_dirty, &page->flags)); + + pagefault_disable(); + + idx = FIX_CMAP_END - + ((addr & current_cpu_data.dcache.alias_mask) >> PAGE_SHIFT); + vaddr = __fix_to_virt(idx); + + BUG_ON(!pte_none(*(kmap_coherent_pte - idx))); + set_pte(kmap_coherent_pte - idx, mk_pte(page, PAGE_KERNEL)); + + return (void *)vaddr; +} + +void kunmap_coherent(void *kvaddr) +{ + if (kvaddr >= (void *)FIXADDR_START) { + unsigned long vaddr = (unsigned long)kvaddr & PAGE_MASK; + enum fixed_addresses idx = __virt_to_fix(vaddr); + + /* XXX.. Kill this later, here for sanity at the moment.. */ + __flush_purge_region((void *)vaddr, PAGE_SIZE); + + pte_clear(&init_mm, vaddr, kmap_coherent_pte - idx); + local_flush_tlb_one(get_asid(), vaddr); + } + + pagefault_enable(); +} diff --git a/arch/sh/mm/mmap.c b/arch/sh/mm/mmap.c index 1b5fdfb4e0c2..d2984fa42d3d 100644 --- a/arch/sh/mm/mmap.c +++ b/arch/sh/mm/mmap.c @@ -14,10 +14,10 @@ #include <asm/page.h> #include <asm/processor.h> -#ifdef CONFIG_MMU unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */ EXPORT_SYMBOL(shm_align_mask); +#ifdef CONFIG_MMU /* * To avoid cache aliases, we map the shared page with same color. */ diff --git a/arch/sh/mm/tlb-nommu.c b/arch/sh/mm/nommu.c index 71c742b5aee3..ac16c05917ef 100644 --- a/arch/sh/mm/tlb-nommu.c +++ b/arch/sh/mm/nommu.c @@ -1,20 +1,41 @@ /* - * arch/sh/mm/tlb-nommu.c + * arch/sh/mm/nommu.c * - * TLB Operations for MMUless SH. + * Various helper routines and stubs for MMUless SH. * - * Copyright (C) 2002 Paul Mundt + * Copyright (C) 2002 - 2009 Paul Mundt * * Released under the terms of the GNU GPL v2.0. */ #include <linux/kernel.h> +#include <linux/init.h> +#include <linux/string.h> #include <linux/mm.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> +#include <asm/page.h> +#include <asm/uaccess.h> /* * Nothing too terribly exciting here .. */ +void copy_page(void *to, void *from) +{ + memcpy(to, from, PAGE_SIZE); +} + +__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n) +{ + memcpy(to, from, n); + return 0; +} + +__kernel_size_t __clear_user(void *to, __kernel_size_t n) +{ + memset(to, 0, n); + return 0; +} + void local_flush_tlb_all(void) { BUG(); @@ -46,8 +67,21 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) BUG(); } -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) +{ +} + +void __init kmap_coherent_init(void) +{ +} + +void *kmap_coherent(struct page *page, unsigned long addr) +{ + BUG(); + return NULL; +} + +void kunmap_coherent(void *kvaddr) { BUG(); } diff --git a/arch/sh/mm/numa.c b/arch/sh/mm/numa.c index 095d93bec7cd..9b784fdb947c 100644 --- a/arch/sh/mm/numa.c +++ b/arch/sh/mm/numa.c @@ -9,6 +9,7 @@ */ #include <linux/module.h> #include <linux/bootmem.h> +#include <linux/lmb.h> #include <linux/mm.h> #include <linux/numa.h> #include <linux/pfn.h> @@ -26,6 +27,15 @@ EXPORT_SYMBOL_GPL(node_data); void __init setup_memory(void) { unsigned long free_pfn = PFN_UP(__pa(_end)); + u64 base = min_low_pfn << PAGE_SHIFT; + u64 size = (max_low_pfn << PAGE_SHIFT) - min_low_pfn; + + lmb_add(base, size); + + /* Reserve the LMB regions used by the kernel, initrd, etc.. */ + lmb_reserve(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET, + (PFN_PHYS(free_pfn) + PAGE_SIZE - 1) - + (__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET)); /* * Node 0 sets up its pgdat at the first available pfn, @@ -45,24 +55,23 @@ void __init setup_memory(void) void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end) { - unsigned long bootmap_pages, bootmap_start, bootmap_size; - unsigned long start_pfn, free_pfn, end_pfn; + unsigned long bootmap_pages; + unsigned long start_pfn, end_pfn; + unsigned long bootmem_paddr; /* Don't allow bogus node assignment */ BUG_ON(nid > MAX_NUMNODES || nid == 0); - /* - * The free pfn starts at the beginning of the range, and is - * advanced as necessary for pgdat and node map allocations. - */ - free_pfn = start_pfn = start >> PAGE_SHIFT; + start_pfn = start >> PAGE_SHIFT; end_pfn = end >> PAGE_SHIFT; + lmb_add(start, end - start); + __add_active_range(nid, start_pfn, end_pfn); /* Node-local pgdat */ - NODE_DATA(nid) = pfn_to_kaddr(free_pfn); - free_pfn += PFN_UP(sizeof(struct pglist_data)); + NODE_DATA(nid) = __va(lmb_alloc_base(sizeof(struct pglist_data), + SMP_CACHE_BYTES, end_pfn)); memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); NODE_DATA(nid)->bdata = &bootmem_node_data[nid]; @@ -71,16 +80,17 @@ void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end) /* Node-local bootmap */ bootmap_pages = bootmem_bootmap_pages(end_pfn - start_pfn); - bootmap_start = (unsigned long)pfn_to_kaddr(free_pfn); - bootmap_size = init_bootmem_node(NODE_DATA(nid), free_pfn, start_pfn, - end_pfn); + bootmem_paddr = lmb_alloc_base(bootmap_pages << PAGE_SHIFT, + PAGE_SIZE, end_pfn); + init_bootmem_node(NODE_DATA(nid), bootmem_paddr >> PAGE_SHIFT, + start_pfn, end_pfn); free_bootmem_with_active_regions(nid, end_pfn); /* Reserve the pgdat and bootmap space with the bootmem allocator */ reserve_bootmem_node(NODE_DATA(nid), start_pfn << PAGE_SHIFT, sizeof(struct pglist_data), BOOTMEM_DEFAULT); - reserve_bootmem_node(NODE_DATA(nid), free_pfn << PAGE_SHIFT, + reserve_bootmem_node(NODE_DATA(nid), bootmem_paddr, bootmap_pages << PAGE_SHIFT, BOOTMEM_DEFAULT); /* It's up */ diff --git a/arch/sh/mm/pg-nommu.c b/arch/sh/mm/pg-nommu.c deleted file mode 100644 index 91ed4e695ff7..000000000000 --- a/arch/sh/mm/pg-nommu.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * arch/sh/mm/pg-nommu.c - * - * clear_page()/copy_page() implementation for MMUless SH. - * - * Copyright (C) 2003 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <asm/page.h> -#include <asm/uaccess.h> - -void copy_page(void *to, void *from) -{ - memcpy(to, from, PAGE_SIZE); -} - -void clear_page(void *to) -{ - memset(to, 0, PAGE_SIZE); -} - -__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n) -{ - memcpy(to, from, n); - return 0; -} - -__kernel_size_t __clear_user(void *to, __kernel_size_t n) -{ - memset(to, 0, n); - return 0; -} diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c deleted file mode 100644 index 2fe14da1f839..000000000000 --- a/arch/sh/mm/pg-sh4.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * arch/sh/mm/pg-sh4.c - * - * Copyright (C) 1999, 2000, 2002 Niibe Yutaka - * Copyright (C) 2002 - 2007 Paul Mundt - * - * Released under the terms of the GNU GPL v2.0. - */ -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/mutex.h> -#include <linux/fs.h> -#include <linux/highmem.h> -#include <linux/module.h> -#include <asm/mmu_context.h> -#include <asm/cacheflush.h> - -#define CACHE_ALIAS (current_cpu_data.dcache.alias_mask) - -#define kmap_get_fixmap_pte(vaddr) \ - pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) - -static pte_t *kmap_coherent_pte; - -void __init kmap_coherent_init(void) -{ - unsigned long vaddr; - - /* cache the first coherent kmap pte */ - vaddr = __fix_to_virt(FIX_CMAP_BEGIN); - kmap_coherent_pte = kmap_get_fixmap_pte(vaddr); -} - -static inline void *kmap_coherent(struct page *page, unsigned long addr) -{ - enum fixed_addresses idx; - unsigned long vaddr, flags; - pte_t pte; - - inc_preempt_count(); - - idx = (addr & current_cpu_data.dcache.alias_mask) >> PAGE_SHIFT; - vaddr = __fix_to_virt(FIX_CMAP_END - idx); - pte = mk_pte(page, PAGE_KERNEL); - - local_irq_save(flags); - flush_tlb_one(get_asid(), vaddr); - local_irq_restore(flags); - - update_mmu_cache(NULL, vaddr, pte); - - set_pte(kmap_coherent_pte - (FIX_CMAP_END - idx), pte); - - return (void *)vaddr; -} - -static inline void kunmap_coherent(struct page *page) -{ - dec_preempt_count(); - preempt_check_resched(); -} - -/* - * clear_user_page - * @to: P1 address - * @address: U0 address to be mapped - * @page: page (virt_to_page(to)) - */ -void clear_user_page(void *to, unsigned long address, struct page *page) -{ - __set_bit(PG_mapped, &page->flags); - - clear_page(to); - if ((((address & PAGE_MASK) ^ (unsigned long)to) & CACHE_ALIAS)) - __flush_wback_region(to, PAGE_SIZE); -} - -void copy_to_user_page(struct vm_area_struct *vma, struct page *page, - unsigned long vaddr, void *dst, const void *src, - unsigned long len) -{ - void *vto; - - __set_bit(PG_mapped, &page->flags); - - vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); - memcpy(vto, src, len); - kunmap_coherent(vto); - - if (vma->vm_flags & VM_EXEC) - flush_cache_page(vma, vaddr, page_to_pfn(page)); -} - -void copy_from_user_page(struct vm_area_struct *vma, struct page *page, - unsigned long vaddr, void *dst, const void *src, - unsigned long len) -{ - void *vfrom; - - __set_bit(PG_mapped, &page->flags); - - vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); - memcpy(dst, vfrom, len); - kunmap_coherent(vfrom); -} - -void copy_user_highpage(struct page *to, struct page *from, - unsigned long vaddr, struct vm_area_struct *vma) -{ - void *vfrom, *vto; - - __set_bit(PG_mapped, &to->flags); - - vto = kmap_atomic(to, KM_USER1); - vfrom = kmap_coherent(from, vaddr); - copy_page(vto, vfrom); - kunmap_coherent(vfrom); - - if (((vaddr ^ (unsigned long)vto) & CACHE_ALIAS)) - __flush_wback_region(vto, PAGE_SIZE); - - kunmap_atomic(vto, KM_USER1); - /* Make sure this page is cleared on other CPU's too before using it */ - smp_wmb(); -} -EXPORT_SYMBOL(copy_user_highpage); - -/* - * For SH-4, we have our own implementation for ptep_get_and_clear - */ -pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) -{ - pte_t pte = *ptep; - - pte_clear(mm, addr, ptep); - if (!pte_not_present(pte)) { - unsigned long pfn = pte_pfn(pte); - if (pfn_valid(pfn)) { - struct page *page = pfn_to_page(pfn); - struct address_space *mapping = page_mapping(page); - if (!mapping || !mapping_writably_mapped(mapping)) - __clear_bit(PG_mapped, &page->flags); - } - } - return pte; -} diff --git a/arch/sh/mm/pg-sh7705.c b/arch/sh/mm/pg-sh7705.c deleted file mode 100644 index eaf25147194c..000000000000 --- a/arch/sh/mm/pg-sh7705.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * arch/sh/mm/pg-sh7705.c - * - * Copyright (C) 1999, 2000 Niibe Yutaka - * Copyright (C) 2004 Alex Song - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include <linux/init.h> -#include <linux/mman.h> -#include <linux/mm.h> -#include <linux/threads.h> -#include <linux/fs.h> -#include <asm/addrspace.h> -#include <asm/page.h> -#include <asm/pgtable.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/io.h> -#include <asm/uaccess.h> -#include <asm/pgalloc.h> -#include <asm/mmu_context.h> -#include <asm/cacheflush.h> - -static inline void __flush_purge_virtual_region(void *p1, void *virt, int size) -{ - unsigned long v; - unsigned long begin, end; - unsigned long p1_begin; - - - begin = L1_CACHE_ALIGN((unsigned long)virt); - end = L1_CACHE_ALIGN((unsigned long)virt + size); - - p1_begin = (unsigned long)p1 & ~(L1_CACHE_BYTES - 1); - - /* do this the slow way as we may not have TLB entries - * for virt yet. */ - for (v = begin; v < end; v += L1_CACHE_BYTES) { - unsigned long p; - unsigned long ways, addr; - - p = __pa(p1_begin); - - ways = current_cpu_data.dcache.ways; - addr = CACHE_OC_ADDRESS_ARRAY; - - do { - unsigned long data; - - addr |= (v & current_cpu_data.dcache.entry_mask); - - data = ctrl_inl(addr); - if ((data & CACHE_PHYSADDR_MASK) == - (p & CACHE_PHYSADDR_MASK)) { - data &= ~(SH_CACHE_UPDATED|SH_CACHE_VALID); - ctrl_outl(data, addr); - } - - addr += current_cpu_data.dcache.way_incr; - } while (--ways); - - p1_begin += L1_CACHE_BYTES; - } -} - -/* - * clear_user_page - * @to: P1 address - * @address: U0 address to be mapped - */ -void clear_user_page(void *to, unsigned long address, struct page *pg) -{ - struct page *page = virt_to_page(to); - - __set_bit(PG_mapped, &page->flags); - if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) { - clear_page(to); - __flush_wback_region(to, PAGE_SIZE); - } else { - __flush_purge_virtual_region(to, - (void *)(address & 0xfffff000), - PAGE_SIZE); - clear_page(to); - __flush_wback_region(to, PAGE_SIZE); - } -} - -/* - * copy_user_page - * @to: P1 address - * @from: P1 address - * @address: U0 address to be mapped - */ -void copy_user_page(void *to, void *from, unsigned long address, struct page *pg) -{ - struct page *page = virt_to_page(to); - - - __set_bit(PG_mapped, &page->flags); - if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) { - copy_page(to, from); - __flush_wback_region(to, PAGE_SIZE); - } else { - __flush_purge_virtual_region(to, - (void *)(address & 0xfffff000), - PAGE_SIZE); - copy_page(to, from); - __flush_wback_region(to, PAGE_SIZE); - } -} - -/* - * For SH7705, we have our own implementation for ptep_get_and_clear - * Copied from pg-sh4.c - */ -pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) -{ - pte_t pte = *ptep; - - pte_clear(mm, addr, ptep); - if (!pte_not_present(pte)) { - unsigned long pfn = pte_pfn(pte); - if (pfn_valid(pfn)) { - struct page *page = pfn_to_page(pfn); - struct address_space *mapping = page_mapping(page); - if (!mapping || !mapping_writably_mapped(mapping)) - __clear_bit(PG_mapped, &page->flags); - } - } - - return pte; -} - diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c index 2aab3ea934d7..409b7c2b4b9d 100644 --- a/arch/sh/mm/tlb-pteaex.c +++ b/arch/sh/mm/tlb-pteaex.c @@ -16,34 +16,16 @@ #include <asm/mmu_context.h> #include <asm/cacheflush.h> -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) { - unsigned long flags; - unsigned long pteval; - unsigned long vpn; + unsigned long flags, pteval, vpn; - /* Ptrace may call this routine. */ + /* + * Handle debugger faulting in for debugee. + */ if (vma && current->active_mm != vma->vm_mm) return; -#ifndef CONFIG_CACHE_OFF - { - unsigned long pfn = pte_pfn(pte); - - if (pfn_valid(pfn)) { - struct page *page = pfn_to_page(pfn); - - if (!test_bit(PG_mapped, &page->flags)) { - unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; - __flush_wback_region((void *)P1SEGADDR(phys), - PAGE_SIZE); - __set_bit(PG_mapped, &page->flags); - } - } - } -#endif - local_irq_save(flags); /* Set PTEH register */ diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c index 17cb7c3adf22..ace8e6d2f59d 100644 --- a/arch/sh/mm/tlb-sh3.c +++ b/arch/sh/mm/tlb-sh3.c @@ -27,32 +27,16 @@ #include <asm/mmu_context.h> #include <asm/cacheflush.h> -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) { - unsigned long flags; - unsigned long pteval; - unsigned long vpn; + unsigned long flags, pteval, vpn; - /* Ptrace may call this routine. */ + /* + * Handle debugger faulting in for debugee. + */ if (vma && current->active_mm != vma->vm_mm) return; -#if defined(CONFIG_SH7705_CACHE_32KB) - { - struct page *page = pte_page(pte); - unsigned long pfn = pte_pfn(pte); - - if (pfn_valid(pfn) && !test_bit(PG_mapped, &page->flags)) { - unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; - - __flush_wback_region((void *)P1SEGADDR(phys), - PAGE_SIZE); - __set_bit(PG_mapped, &page->flags); - } - } -#endif - local_irq_save(flags); /* Set PTEH register */ @@ -93,4 +77,3 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) for (i = 0; i < ways; i++) ctrl_outl(data, addr + (i << 8)); } - diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c index f0c7b7397fa6..8cf550e2570f 100644 --- a/arch/sh/mm/tlb-sh4.c +++ b/arch/sh/mm/tlb-sh4.c @@ -15,34 +15,16 @@ #include <asm/mmu_context.h> #include <asm/cacheflush.h> -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) { - unsigned long flags; - unsigned long pteval; - unsigned long vpn; + unsigned long flags, pteval, vpn; - /* Ptrace may call this routine. */ + /* + * Handle debugger faulting in for debugee. + */ if (vma && current->active_mm != vma->vm_mm) return; -#ifndef CONFIG_CACHE_OFF - { - unsigned long pfn = pte_pfn(pte); - - if (pfn_valid(pfn)) { - struct page *page = pfn_to_page(pfn); - - if (!test_bit(PG_mapped, &page->flags)) { - unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; - __flush_wback_region((void *)P1SEGADDR(phys), - PAGE_SIZE); - __set_bit(PG_mapped, &page->flags); - } - } - } -#endif - local_irq_save(flags); /* Set PTEH register */ @@ -61,9 +43,12 @@ void update_mmu_cache(struct vm_area_struct * vma, */ ctrl_outl(pte.pte_high, MMU_PTEA); #else - if (cpu_data->flags & CPU_HAS_PTEA) - /* TODO: make this look less hacky */ - ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA); + if (cpu_data->flags & CPU_HAS_PTEA) { + /* The last 3 bits and the first one of pteval contains + * the PTEA timing control and space attribute bits + */ + ctrl_outl(copy_ptea_attributes(pteval), MMU_PTEA); + } #endif /* Set PTEL register */ diff --git a/arch/sh/mm/tlb-sh5.c b/arch/sh/mm/tlb-sh5.c index dae131243bcc..fdb64e41ec50 100644 --- a/arch/sh/mm/tlb-sh5.c +++ b/arch/sh/mm/tlb-sh5.c @@ -117,26 +117,15 @@ int sh64_put_wired_dtlb_entry(unsigned long long entry) * Load up a virtual<->physical translation for @eaddr<->@paddr in the * pre-allocated TLB slot @config_addr (see sh64_get_wired_dtlb_entry). */ -inline void sh64_setup_tlb_slot(unsigned long long config_addr, - unsigned long eaddr, - unsigned long asid, - unsigned long paddr) +void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr, + unsigned long asid, unsigned long paddr) { unsigned long long pteh, ptel; - /* Sign extension */ -#if (NEFF == 32) - pteh = (unsigned long long)(signed long long)(signed long) eaddr; -#else -#error "Can't sign extend more than 32 bits yet" -#endif + pteh = neff_sign_extend(eaddr); pteh &= PAGE_MASK; pteh |= (asid << PTEH_ASID_SHIFT) | PTEH_VALID; -#if (NEFF == 32) - ptel = (unsigned long long)(signed long long)(signed long) paddr; -#else -#error "Can't sign extend more than 32 bits yet" -#endif + ptel = neff_sign_extend(paddr); ptel &= PAGE_MASK; ptel |= (_PAGE_CACHABLE | _PAGE_READ | _PAGE_WRITE); @@ -152,5 +141,5 @@ inline void sh64_setup_tlb_slot(unsigned long long config_addr, * * Teardown any existing mapping in the TLB slot @config_addr. */ -inline void sh64_teardown_tlb_slot(unsigned long long config_addr) +void sh64_teardown_tlb_slot(unsigned long long config_addr) __attribute__ ((alias("__flush_tlb_slot"))); diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index 3ce40ea34824..2dcc48528f7a 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -329,22 +329,6 @@ do_sigbus: goto no_context; } -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - /* - * This appears to get called once for every pte entry that gets - * established => I don't think it's efficient to try refilling the - * TLBs with the pages - some may not get accessed even. Also, for - * executable pages, it is impossible to determine reliably here which - * TLB they should be mapped into (or both even). - * - * So, just do nothing here and handle faults on demand. In the - * TLBMISS handling case, the refill is now done anyway after the pte - * has been fixed up, so that deals with most useful cases. - */ -} - void local_flush_tlb_one(unsigned long asid, unsigned long page) { unsigned long long match, pteh=0, lpage; @@ -353,7 +337,7 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) /* * Sign-extend based on neff. */ - lpage = (page & NEFF_SIGN) ? (page | NEFF_MASK) : page; + lpage = neff_sign_extend(page); match = (asid << PTEH_ASID_SHIFT) | PTEH_VALID; match |= lpage; @@ -482,3 +466,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) /* FIXME: Optimize this later.. */ flush_tlb_all(); } + +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) +{ +} diff --git a/arch/sh/oprofile/backtrace.c b/arch/sh/oprofile/backtrace.c index 9499a2914f89..2bc74de23f08 100644 --- a/arch/sh/oprofile/backtrace.c +++ b/arch/sh/oprofile/backtrace.c @@ -17,9 +17,43 @@ #include <linux/sched.h> #include <linux/kallsyms.h> #include <linux/mm.h> +#include <asm/unwinder.h> #include <asm/ptrace.h> #include <asm/uaccess.h> #include <asm/sections.h> +#include <asm/stacktrace.h> + +static void backtrace_warning_symbol(void *data, char *msg, + unsigned long symbol) +{ + /* Ignore warnings */ +} + +static void backtrace_warning(void *data, char *msg) +{ + /* Ignore warnings */ +} + +static int backtrace_stack(void *data, char *name) +{ + /* Yes, we want all stacks */ + return 0; +} + +static void backtrace_address(void *data, unsigned long addr, int reliable) +{ + unsigned int *depth = data; + + if ((*depth)--) + oprofile_add_trace(addr); +} + +static struct stacktrace_ops backtrace_ops = { + .warning = backtrace_warning, + .warning_symbol = backtrace_warning_symbol, + .stack = backtrace_stack, + .address = backtrace_address, +}; /* Limit to stop backtracing too far. */ static int backtrace_limit = 20; @@ -47,50 +81,6 @@ user_backtrace(unsigned long *stackaddr, struct pt_regs *regs) return stackaddr; } -/* - * | | /\ Higher addresses - * | | - * --------------- stack base (address of current_thread_info) - * | thread info | - * . . - * | stack | - * --------------- saved regs->regs[15] value if valid - * . . - * --------------- struct pt_regs stored on stack (struct pt_regs *) - * | | - * . . - * | | - * --------------- ??? - * | | - * | | \/ Lower addresses - * - * Thus, &pt_regs <-> stack base restricts the valid(ish) fp values - */ -static int valid_kernel_stack(unsigned long *stackaddr, struct pt_regs *regs) -{ - unsigned long stack = (unsigned long)regs; - unsigned long stack_base = (stack & ~(THREAD_SIZE - 1)) + THREAD_SIZE; - - return ((unsigned long)stackaddr > stack) && ((unsigned long)stackaddr < stack_base); -} - -static unsigned long * -kernel_backtrace(unsigned long *stackaddr, struct pt_regs *regs) -{ - unsigned long addr; - - /* - * If not a valid kernel address, keep going till we find one - * or the SP stops being a valid address. - */ - do { - addr = *stackaddr++; - oprofile_add_trace(addr); - } while (valid_kernel_stack(stackaddr, regs)); - - return stackaddr; -} - void sh_backtrace(struct pt_regs * const regs, unsigned int depth) { unsigned long *stackaddr; @@ -103,9 +93,9 @@ void sh_backtrace(struct pt_regs * const regs, unsigned int depth) stackaddr = (unsigned long *)regs->regs[15]; if (!user_mode(regs)) { - while (depth-- && valid_kernel_stack(stackaddr, regs)) - stackaddr = kernel_backtrace(stackaddr, regs); - + if (depth) + unwind_stack(NULL, regs, stackaddr, + &backtrace_ops, &depth); return; } diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types index fec3a53b8650..6639b25d8d57 100644 --- a/arch/sh/tools/mach-types +++ b/arch/sh/tools/mach-types @@ -53,6 +53,9 @@ RSK7203 SH_RSK7203 AP325RXA SH_AP325RXA SH7763RDP SH_SH7763RDP SH7785LCR SH_SH7785LCR +SH7785LCR_PT SH_SH7785LCR_PT URQUELL SH_URQUELL ESPT SH_ESPT POLARIS SH_POLARIS +KFR2R09 SH_KFR2R09 +ECOVEC SH_ECOVEC diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S index 866390feb683..4e5992593967 100644 --- a/arch/sparc/kernel/vmlinux.lds.S +++ b/arch/sparc/kernel/vmlinux.lds.S @@ -51,70 +51,27 @@ SECTIONS _etext = .; RO_DATA(PAGE_SIZE) - .data : { - DATA_DATA - CONSTRUCTORS - } .data1 : { *(.data1) } - . = ALIGN(SMP_CACHE_BYTES); - .data.cacheline_aligned : { - *(.data.cacheline_aligned) - } - . = ALIGN(SMP_CACHE_BYTES); - .data.read_mostly : { - *(.data.read_mostly) - } + RW_DATA_SECTION(SMP_CACHE_BYTES, 0, THREAD_SIZE) + /* End of data section */ _edata = .; - /* init_task */ - . = ALIGN(THREAD_SIZE); - .data.init_task : { - *(.data.init_task) - } .fixup : { __start___fixup = .; *(.fixup) __stop___fixup = .; } - . = ALIGN(16); - __ex_table : { - __start___ex_table = .; - *(__ex_table) - __stop___ex_table = .; - } + EXCEPTION_TABLE(16) NOTES . = ALIGN(PAGE_SIZE); - .init.text : { - __init_begin = .; - _sinittext = .; - INIT_TEXT - _einittext = .; - } + __init_begin = ALIGN(PAGE_SIZE); + INIT_TEXT_SECTION(PAGE_SIZE) __init_text_end = .; - .init.data : { - INIT_DATA - } - . = ALIGN(16); - .init.setup : { - __setup_start = .; - *(.init.setup) - __setup_end = .; - } - .initcall.init : { - __initcall_start = .; - INITCALLS - __initcall_end = .; - } - .con_initcall.init : { - __con_initcall_start = .; - *(.con_initcall.init) - __con_initcall_end = .; - } - SECURITY_INIT + INIT_DATA_SECTION(16) . = ALIGN(4); .tsb_ldquad_phys_patch : { @@ -146,29 +103,11 @@ SECTIONS __sun4v_2insn_patch_end = .; } -#ifdef CONFIG_BLK_DEV_INITRD - . = ALIGN(PAGE_SIZE); - .init.ramfs : { - __initramfs_start = .; - *(.init.ramfs) - __initramfs_end = .; - } -#endif - PERCPU(PAGE_SIZE) . = ALIGN(PAGE_SIZE); __init_end = .; - __bss_start = .; - .sbss : { - *(.sbss) - *(.scommon) - } - .bss : { - *(.dynbss) - *(.bss) - *(COMMON) - } + BSS_SECTION(0, 0, 0) _end = . ; STABS_DEBUG diff --git a/arch/um/os-Linux/helper.c b/arch/um/os-Linux/helper.c index 30860b89ec58..b6b1096152aa 100644 --- a/arch/um/os-Linux/helper.c +++ b/arch/um/os-Linux/helper.c @@ -15,7 +15,6 @@ #include "os.h" #include "um_malloc.h" #include "user.h" -#include <linux/limits.h> struct helper_data { void (*pre_exec)(void*); diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e5deee2dfcfe..51c59015b280 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -325,6 +325,7 @@ config X86_EXTENDED_PLATFORM SGI 320/540 (Visual Workstation) Summit/EXA (IBM x440) Unisys ES7000 IA32 series + Moorestown MID devices If you have one of these systems, or if you want to build a generic distribution kernel, say Y here - otherwise say N. @@ -384,6 +385,18 @@ config X86_ELAN If unsure, choose "PC-compatible" instead. +config X86_MRST + bool "Moorestown MID platform" + depends on X86_32 + depends on X86_EXTENDED_PLATFORM + ---help--- + Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin + Internet Device(MID) platform. Moorestown consists of two chips: + Lincroft (CPU core, graphics, and memory controller) and Langwell IOH. + Unlike standard x86 PCs, Moorestown does not have many legacy devices + nor standard legacy replacement devices/features. e.g. Moorestown does + not contain i8259, i8254, HPET, legacy BIOS, most of the io ports. + config X86_RDC321X bool "RDC R-321x SoC" depends on X86_32 diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 586b7adb8e53..c6d21b18806c 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -70,9 +70,6 @@ static inline void default_inquire_remote_apic(int apicid) */ #ifdef CONFIG_PARAVIRT #include <asm/paravirt.h> -#else -#define setup_boot_clock setup_boot_APIC_clock -#define setup_secondary_clock setup_secondary_APIC_clock #endif #ifdef CONFIG_X86_64 @@ -252,6 +249,8 @@ static inline void lapic_shutdown(void) { } static inline void init_apic_mappings(void) { } static inline void disable_local_APIC(void) { } static inline void apic_disable(void) { } +# define setup_boot_APIC_clock x86_init_noop +# define setup_secondary_APIC_clock x86_init_noop #endif /* !CONFIG_X86_LOCAL_APIC */ #ifdef CONFIG_X86_64 @@ -300,7 +299,7 @@ struct apic { int (*cpu_present_to_apicid)(int mps_cpu); physid_mask_t (*apicid_to_cpu_present)(int phys_apicid); void (*setup_portio_remap)(void); - int (*check_phys_apicid_present)(int boot_cpu_physical_apicid); + int (*check_phys_apicid_present)(int phys_apicid); void (*enable_apic_mode)(void); int (*phys_pkg_id)(int cpuid_apic, int index_msb); @@ -434,7 +433,7 @@ extern struct apic apic_x2apic_uv_x; DECLARE_PER_CPU(int, x2apic_extra_bits); extern int default_cpu_present_to_apicid(int mps_cpu); -extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); +extern int default_check_phys_apicid_present(int phys_apicid); #endif static inline void default_wait_for_init_deassert(atomic_t *deassert) @@ -550,9 +549,9 @@ static inline int __default_cpu_present_to_apicid(int mps_cpu) } static inline int -__default_check_phys_apicid_present(int boot_cpu_physical_apicid) +__default_check_phys_apicid_present(int phys_apicid) { - return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); + return physid_isset(phys_apicid, phys_cpu_present_map); } #ifdef CONFIG_X86_32 @@ -562,13 +561,13 @@ static inline int default_cpu_present_to_apicid(int mps_cpu) } static inline int -default_check_phys_apicid_present(int boot_cpu_physical_apicid) +default_check_phys_apicid_present(int phys_apicid) { - return __default_check_phys_apicid_present(boot_cpu_physical_apicid); + return __default_check_phys_apicid_present(phys_apicid); } #else extern int default_cpu_present_to_apicid(int mps_cpu); -extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); +extern int default_check_phys_apicid_present(int phys_apicid); #endif static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index 6ca20218dd72..6be33d83c716 100644 --- a/arch/x86/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h @@ -110,4 +110,14 @@ struct boot_params { __u8 _pad9[276]; /* 0xeec */ } __attribute__((packed)); +enum { + X86_SUBARCH_PC = 0, + X86_SUBARCH_LGUEST, + X86_SUBARCH_XEN, + X86_SUBARCH_MRST, + X86_NR_SUBARCHS, +}; + + + #endif /* _ASM_X86_BOOTPARAM_H */ diff --git a/arch/x86/include/asm/do_timer.h b/arch/x86/include/asm/do_timer.h deleted file mode 100644 index 23ecda0b28a0..000000000000 --- a/arch/x86/include/asm/do_timer.h +++ /dev/null @@ -1,16 +0,0 @@ -/* defines for inline arch setup functions */ -#include <linux/clockchips.h> - -#include <asm/i8259.h> -#include <asm/i8253.h> - -/** - * do_timer_interrupt_hook - hook into timer tick - * - * Call the pit clock event handler. see asm/i8253.h - **/ - -static inline void do_timer_interrupt_hook(void) -{ - global_clock_event->event_handler(global_clock_event); -} diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index 7ecba4d85089..40b4e614fe71 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -126,8 +126,6 @@ extern void e820_reserve_resources(void); extern void e820_reserve_resources_late(void); extern void setup_memory_map(void); extern char *default_machine_specific_memory_setup(void); -extern char *machine_specific_memory_setup(void); -extern char *memory_setup(void); #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h index 369f5c5d09a1..b78c0941e422 100644 --- a/arch/x86/include/asm/hypervisor.h +++ b/arch/x86/include/asm/hypervisor.h @@ -20,7 +20,7 @@ #ifndef ASM_X86__HYPERVISOR_H #define ASM_X86__HYPERVISOR_H -extern unsigned long get_hypervisor_tsc_freq(void); extern void init_hypervisor(struct cpuinfo_x86 *c); +extern void init_hypervisor_platform(void); #endif diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h index 85232d32fcb8..7c7c16cde1f8 100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -143,6 +143,8 @@ extern int noioapicreroute; /* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */ extern int timer_through_8259; +extern void io_apic_disable_legacy(void); + /* * If we use the IO-APIC for IRQ routing, disable automatic * assignment of PCI IRQ's. @@ -176,6 +178,7 @@ extern int setup_ioapic_entry(int apic, int irq, int polarity, int vector, int pin); extern void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e); +extern void setup_ioapic_ids_from_mpc(void); struct mp_ioapic_gsi{ int gsi_base; @@ -187,12 +190,14 @@ int mp_find_ioapic_pin(int ioapic, int gsi); void __init mp_register_ioapic(int id, u32 address, u32 gsi_base); #else /* !CONFIG_X86_IO_APIC */ + #define io_apic_assign_pci_irqs 0 +#define setup_ioapic_ids_from_mpc x86_init_noop static const int timer_through_8259 = 0; static inline void ioapic_init_mappings(void) { } static inline void ioapic_insert_resources(void) { } - static inline void probe_nr_irqs_gsi(void) { } + #endif #endif /* _ASM_X86_IO_APIC_H */ diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index f38481bcd455..ddda6cbed6f4 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -37,7 +37,6 @@ extern void fixup_irqs(void); #endif extern void (*generic_interrupt_extension)(void); -extern void init_IRQ(void); extern void native_init_IRQ(void); extern bool handle_irq(unsigned irq, struct pt_regs *regs); @@ -47,4 +46,6 @@ extern unsigned int do_IRQ(struct pt_regs *regs); extern DECLARE_BITMAP(used_vectors, NR_VECTORS); extern int vector_used_by_percpu_irq(unsigned int vector); +extern void init_ISA_irqs(void); + #endif /* _ASM_X86_IRQ_H */ diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index e2a1bb6d71ea..79c94500c0bb 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -4,6 +4,7 @@ #include <linux/init.h> #include <asm/mpspec_def.h> +#include <asm/x86_init.h> extern int apic_version[MAX_APICS]; extern int pic_mode; @@ -41,9 +42,6 @@ extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; #endif /* CONFIG_X86_64 */ -extern void early_find_smp_config(void); -extern void early_get_smp_config(void); - #if defined(CONFIG_MCA) || defined(CONFIG_EISA) extern int mp_bus_id_to_type[MAX_MP_BUSSES]; #endif @@ -52,20 +50,55 @@ extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); extern unsigned int boot_cpu_physical_apicid; extern unsigned int max_physical_apicid; -extern int smp_found_config; extern int mpc_default_type; extern unsigned long mp_lapic_addr; -extern void get_smp_config(void); +#ifdef CONFIG_X86_LOCAL_APIC +extern int smp_found_config; +#else +# define smp_found_config 0 +#endif + +static inline void get_smp_config(void) +{ + x86_init.mpparse.get_smp_config(0); +} + +static inline void early_get_smp_config(void) +{ + x86_init.mpparse.get_smp_config(1); +} + +static inline void find_smp_config(void) +{ + x86_init.mpparse.find_smp_config(1); +} + +static inline void early_find_smp_config(void) +{ + x86_init.mpparse.find_smp_config(0); +} #ifdef CONFIG_X86_MPPARSE -extern void find_smp_config(void); extern void early_reserve_e820_mpc_new(void); extern int enable_update_mptable; +extern int default_mpc_apic_id(struct mpc_cpu *m); +extern void default_smp_read_mpc_oem(struct mpc_table *mpc); +# ifdef CONFIG_X86_IO_APIC +extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str); +# else +# define default_mpc_oem_bus_info NULL +# endif +extern void default_find_smp_config(unsigned int reserve); +extern void default_get_smp_config(unsigned int early); #else -static inline void find_smp_config(void) { } static inline void early_reserve_e820_mpc_new(void) { } #define enable_update_mptable 0 +#define default_mpc_apic_id NULL +#define default_smp_read_mpc_oem NULL +#define default_mpc_oem_bus_info NULL +#define default_find_smp_config x86_init_uint_noop +#define default_get_smp_config x86_init_uint_noop #endif void __cpuinit generic_processor_info(int apicid, int version); diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index 40d6586af25b..8aebcc41041d 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -24,22 +24,6 @@ static inline void load_sp0(struct tss_struct *tss, PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); } -#define ARCH_SETUP pv_init_ops.arch_setup(); -static inline unsigned long get_wallclock(void) -{ - return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock); -} - -static inline int set_wallclock(unsigned long nowtime) -{ - return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime); -} - -static inline void (*choose_time_init(void))(void) -{ - return pv_time_ops.time_init; -} - /* The paravirtualized CPUID instruction. */ static inline void __cpuid(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) @@ -245,7 +229,6 @@ static inline unsigned long long paravirt_sched_clock(void) { return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); } -#define calibrate_tsc() (pv_time_ops.get_tsc_khz()) static inline unsigned long long paravirt_read_pmc(int counter) { @@ -363,34 +346,6 @@ static inline void slow_down_io(void) #endif } -#ifdef CONFIG_X86_LOCAL_APIC -static inline void setup_boot_clock(void) -{ - PVOP_VCALL0(pv_apic_ops.setup_boot_clock); -} - -static inline void setup_secondary_clock(void) -{ - PVOP_VCALL0(pv_apic_ops.setup_secondary_clock); -} -#endif - -static inline void paravirt_post_allocator_init(void) -{ - if (pv_init_ops.post_allocator_init) - (*pv_init_ops.post_allocator_init)(); -} - -static inline void paravirt_pagetable_setup_start(pgd_t *base) -{ - (*pv_mmu_ops.pagetable_setup_start)(base); -} - -static inline void paravirt_pagetable_setup_done(pgd_t *base) -{ - (*pv_mmu_ops.pagetable_setup_done)(base); -} - #ifdef CONFIG_SMP static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip, unsigned long start_esp) @@ -948,6 +903,8 @@ static inline unsigned long __raw_local_irq_save(void) #undef PVOP_VCALL4 #undef PVOP_CALL4 +extern void default_banner(void); + #else /* __ASSEMBLY__ */ #define _PVSITE(ptype, clobbers, ops, word, algn) \ @@ -1088,5 +1045,7 @@ static inline unsigned long __raw_local_irq_save(void) #endif /* CONFIG_X86_32 */ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_PARAVIRT */ +#else /* CONFIG_PARAVIRT */ +# define default_banner x86_init_noop +#endif /* !CONFIG_PARAVIRT */ #endif /* _ASM_X86_PARAVIRT_H */ diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index 25402d0006e7..dd0f5b32489d 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -78,14 +78,6 @@ struct pv_init_ops { */ unsigned (*patch)(u8 type, u16 clobber, void *insnbuf, unsigned long addr, unsigned len); - - /* Basic arch-specific setup */ - void (*arch_setup)(void); - char *(*memory_setup)(void); - void (*post_allocator_init)(void); - - /* Print a banner to identify the environment */ - void (*banner)(void); }; @@ -96,12 +88,6 @@ struct pv_lazy_ops { }; struct pv_time_ops { - void (*time_init)(void); - - /* Set and set time of day */ - unsigned long (*get_wallclock)(void); - int (*set_wallclock)(unsigned long); - unsigned long long (*sched_clock)(void); unsigned long (*get_tsc_khz)(void); }; @@ -203,8 +189,6 @@ struct pv_cpu_ops { }; struct pv_irq_ops { - void (*init_IRQ)(void); - /* * Get/set interrupt state. save_fl and restore_fl are only * expected to use X86_EFLAGS_IF; all other bits @@ -229,9 +213,6 @@ struct pv_irq_ops { struct pv_apic_ops { #ifdef CONFIG_X86_LOCAL_APIC - void (*setup_boot_clock)(void); - void (*setup_secondary_clock)(void); - void (*startup_ipi_hook)(int phys_apicid, unsigned long start_eip, unsigned long start_esp); @@ -239,15 +220,6 @@ struct pv_apic_ops { }; struct pv_mmu_ops { - /* - * Called before/after init_mm pagetable setup. setup_start - * may reset %cr3, and may pre-install parts of the pagetable; - * pagetable setup is expected to preserve any existing - * mapping. - */ - void (*pagetable_setup_start)(pgd_t *pgd_base); - void (*pagetable_setup_done)(pgd_t *pgd_base); - unsigned long (*read_cr2)(void); void (*write_cr2)(unsigned long); diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index 4c5b51fdc788..af6fd360ab35 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -56,16 +56,6 @@ extern struct list_head pgd_list; #define pte_update(mm, addr, ptep) do { } while (0) #define pte_update_defer(mm, addr, ptep) do { } while (0) -static inline void __init paravirt_pagetable_setup_start(pgd_t *base) -{ - native_pagetable_setup_start(base); -} - -static inline void __init paravirt_pagetable_setup_done(pgd_t *base) -{ - native_pagetable_setup_done(base); -} - #define pgd_val(x) native_pgd_val(x) #define __pgd(x) native_make_pgd(x) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 54cb697f4900..7b467bf3c680 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -299,8 +299,8 @@ void set_pte_vaddr(unsigned long vaddr, pte_t pte); extern void native_pagetable_setup_start(pgd_t *base); extern void native_pagetable_setup_done(pgd_t *base); #else -static inline void native_pagetable_setup_start(pgd_t *base) {} -static inline void native_pagetable_setup_done(pgd_t *base) {} +#define native_pagetable_setup_start x86_init_pgd_noop +#define native_pagetable_setup_done x86_init_pgd_noop #endif struct seq_file; diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index 4093d1ed6db2..18e496c98ff0 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -5,43 +5,6 @@ #define COMMAND_LINE_SIZE 2048 -#ifndef __ASSEMBLY__ - -/* - * Any setup quirks to be performed? - */ -struct mpc_cpu; -struct mpc_bus; -struct mpc_oemtable; - -struct x86_quirks { - int (*arch_pre_time_init)(void); - int (*arch_time_init)(void); - int (*arch_pre_intr_init)(void); - int (*arch_intr_init)(void); - int (*arch_trap_init)(void); - char * (*arch_memory_setup)(void); - int (*mach_get_smp_config)(unsigned int early); - int (*mach_find_smp_config)(unsigned int reserve); - - int *mpc_record; - int (*mpc_apic_id)(struct mpc_cpu *m); - void (*mpc_oem_bus_info)(struct mpc_bus *m, char *name); - void (*mpc_oem_pci_bus)(struct mpc_bus *m); - void (*smp_read_mpc_oem)(struct mpc_oemtable *oemtable, - unsigned short oemsize); - int (*setup_ioapic_ids)(void); -}; - -extern void x86_quirk_intr_init(void); - -extern void x86_quirk_trap_init(void); - -extern void x86_quirk_pre_time_init(void); -extern void x86_quirk_time_init(void); - -#endif /* __ASSEMBLY__ */ - #ifdef __i386__ #include <linux/pfn.h> @@ -61,6 +24,7 @@ extern void x86_quirk_time_init(void); #ifndef __ASSEMBLY__ #include <asm/bootparam.h> +#include <asm/x86_init.h> /* Interrupt control for vSMPowered x86_64 systems */ #ifdef CONFIG_X86_64 @@ -79,11 +43,16 @@ static inline void visws_early_detect(void) { } static inline int is_visws_box(void) { return 0; } #endif -extern struct x86_quirks *x86_quirks; extern unsigned long saved_video_mode; -#ifndef CONFIG_PARAVIRT -#define paravirt_post_allocator_init() do {} while (0) +extern void reserve_standard_io_resources(void); +extern void i386_reserve_resources(void); +extern void setup_default_timer_irq(void); + +#ifdef CONFIG_X86_MRST +extern void x86_mrst_early_setup(void); +#else +static inline void x86_mrst_early_setup(void) { } #endif #ifndef _SETUP diff --git a/arch/x86/include/asm/time.h b/arch/x86/include/asm/time.h index 50c733aac421..7bdec4e9b739 100644 --- a/arch/x86/include/asm/time.h +++ b/arch/x86/include/asm/time.h @@ -4,60 +4,7 @@ extern void hpet_time_init(void); #include <asm/mc146818rtc.h> -#ifdef CONFIG_X86_32 -#include <linux/efi.h> - -static inline unsigned long native_get_wallclock(void) -{ - unsigned long retval; - - if (efi_enabled) - retval = efi_get_time(); - else - retval = mach_get_cmos_time(); - - return retval; -} - -static inline int native_set_wallclock(unsigned long nowtime) -{ - int retval; - - if (efi_enabled) - retval = efi_set_rtc_mmss(nowtime); - else - retval = mach_set_rtc_mmss(nowtime); - - return retval; -} - -#else -extern void native_time_init_hook(void); - -static inline unsigned long native_get_wallclock(void) -{ - return mach_get_cmos_time(); -} - -static inline int native_set_wallclock(unsigned long nowtime) -{ - return mach_set_rtc_mmss(nowtime); -} - -#endif extern void time_init(void); -#ifdef CONFIG_PARAVIRT -#include <asm/paravirt.h> -#else /* !CONFIG_PARAVIRT */ - -#define get_wallclock() native_get_wallclock() -#define set_wallclock(x) native_set_wallclock(x) -#define choose_time_init() hpet_time_init - -#endif /* CONFIG_PARAVIRT */ - -extern unsigned long __init calibrate_cpu(void); - #endif /* _ASM_X86_TIME_H */ diff --git a/arch/x86/include/asm/timer.h b/arch/x86/include/asm/timer.h index 20ca9c4d4686..5469630b27f5 100644 --- a/arch/x86/include/asm/timer.h +++ b/arch/x86/include/asm/timer.h @@ -8,20 +8,16 @@ #define TICK_SIZE (tick_nsec / 1000) unsigned long long native_sched_clock(void); -unsigned long native_calibrate_tsc(void); +extern int recalibrate_cpu_khz(void); -#ifdef CONFIG_X86_32 +#if defined(CONFIG_X86_32) && defined(CONFIG_X86_IO_APIC) extern int timer_ack; -extern irqreturn_t timer_interrupt(int irq, void *dev_id); -#endif /* CONFIG_X86_32 */ -extern int recalibrate_cpu_khz(void); +#else +# define timer_ack (0) +#endif extern int no_timer_check; -#ifndef CONFIG_PARAVIRT -#define calibrate_tsc() native_calibrate_tsc() -#endif - /* Accelerators for sched_clock() * convert from cycles(64bits) => nanoseconds (64bits) * basic equation: diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 38ae163cc91b..c0427295e8f5 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -48,7 +48,8 @@ static __always_inline cycles_t vget_cycles(void) extern void tsc_init(void); extern void mark_tsc_unstable(char *reason); extern int unsynchronized_tsc(void); -int check_tsc_unstable(void); +extern int check_tsc_unstable(void); +extern unsigned long native_calibrate_tsc(void); /* * Boot-time check whether the TSCs are synchronized across diff --git a/arch/x86/include/asm/vgtod.h b/arch/x86/include/asm/vgtod.h index dc27a69e5d2a..3d61e204826f 100644 --- a/arch/x86/include/asm/vgtod.h +++ b/arch/x86/include/asm/vgtod.h @@ -21,6 +21,7 @@ struct vsyscall_gtod_data { u32 shift; } clock; struct timespec wall_to_monotonic; + struct timespec wall_time_coarse; }; extern struct vsyscall_gtod_data __vsyscall_gtod_data __section_vsyscall_gtod_data; diff --git a/arch/x86/include/asm/vmware.h b/arch/x86/include/asm/vmware.h index c11b7e100d83..e49ed6d2fd4e 100644 --- a/arch/x86/include/asm/vmware.h +++ b/arch/x86/include/asm/vmware.h @@ -20,7 +20,7 @@ #ifndef ASM_X86__VMWARE_H #define ASM_X86__VMWARE_H -extern unsigned long vmware_get_tsc_khz(void); +extern void vmware_platform_setup(void); extern int vmware_platform(void); extern void vmware_set_feature_bits(struct cpuinfo_x86 *c); diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h new file mode 100644 index 000000000000..2c756fd4ab0e --- /dev/null +++ b/arch/x86/include/asm/x86_init.h @@ -0,0 +1,133 @@ +#ifndef _ASM_X86_PLATFORM_H +#define _ASM_X86_PLATFORM_H + +#include <asm/pgtable_types.h> +#include <asm/bootparam.h> + +struct mpc_bus; +struct mpc_cpu; +struct mpc_table; + +/** + * struct x86_init_mpparse - platform specific mpparse ops + * @mpc_record: platform specific mpc record accounting + * @setup_ioapic_ids: platform specific ioapic id override + * @mpc_apic_id: platform specific mpc apic id assignment + * @smp_read_mpc_oem: platform specific oem mpc table setup + * @mpc_oem_pci_bus: platform specific pci bus setup (default NULL) + * @mpc_oem_bus_info: platform specific mpc bus info + * @find_smp_config: find the smp configuration + * @get_smp_config: get the smp configuration + */ +struct x86_init_mpparse { + void (*mpc_record)(unsigned int mode); + void (*setup_ioapic_ids)(void); + int (*mpc_apic_id)(struct mpc_cpu *m); + void (*smp_read_mpc_oem)(struct mpc_table *mpc); + void (*mpc_oem_pci_bus)(struct mpc_bus *m); + void (*mpc_oem_bus_info)(struct mpc_bus *m, char *name); + void (*find_smp_config)(unsigned int reserve); + void (*get_smp_config)(unsigned int early); +}; + +/** + * struct x86_init_resources - platform specific resource related ops + * @probe_roms: probe BIOS roms + * @reserve_resources: reserve the standard resources for the + * platform + * @memory_setup: platform specific memory setup + * + */ +struct x86_init_resources { + void (*probe_roms)(void); + void (*reserve_resources)(void); + char *(*memory_setup)(void); +}; + +/** + * struct x86_init_irqs - platform specific interrupt setup + * @pre_vector_init: init code to run before interrupt vectors + * are set up. + * @intr_init: interrupt init code + * @trap_init: platform specific trap setup + */ +struct x86_init_irqs { + void (*pre_vector_init)(void); + void (*intr_init)(void); + void (*trap_init)(void); +}; + +/** + * struct x86_init_oem - oem platform specific customizing functions + * @arch_setup: platform specific architecure setup + * @banner: print a platform specific banner + */ +struct x86_init_oem { + void (*arch_setup)(void); + void (*banner)(void); +}; + +/** + * struct x86_init_paging - platform specific paging functions + * @pagetable_setup_start: platform specific pre paging_init() call + * @pagetable_setup_done: platform specific post paging_init() call + */ +struct x86_init_paging { + void (*pagetable_setup_start)(pgd_t *base); + void (*pagetable_setup_done)(pgd_t *base); +}; + +/** + * struct x86_init_timers - platform specific timer setup + * @setup_perpcu_clockev: set up the per cpu clock event device for the + * boot cpu + * @tsc_pre_init: platform function called before TSC init + * @timer_init: initialize the platform timer (default PIT/HPET) + */ +struct x86_init_timers { + void (*setup_percpu_clockev)(void); + void (*tsc_pre_init)(void); + void (*timer_init)(void); +}; + +/** + * struct x86_init_ops - functions for platform specific setup + * + */ +struct x86_init_ops { + struct x86_init_resources resources; + struct x86_init_mpparse mpparse; + struct x86_init_irqs irqs; + struct x86_init_oem oem; + struct x86_init_paging paging; + struct x86_init_timers timers; +}; + +/** + * struct x86_cpuinit_ops - platform specific cpu hotplug setups + * @setup_percpu_clockev: set up the per cpu clock event device + */ +struct x86_cpuinit_ops { + void (*setup_percpu_clockev)(void); +}; + +/** + * struct x86_platform_ops - platform specific runtime functions + * @calibrate_tsc: calibrate TSC + * @get_wallclock: get time from HW clock like RTC etc. + * @set_wallclock: set time back to HW clock + */ +struct x86_platform_ops { + unsigned long (*calibrate_tsc)(void); + unsigned long (*get_wallclock)(void); + int (*set_wallclock)(unsigned long nowtime); +}; + +extern struct x86_init_ops x86_init; +extern struct x86_cpuinit_ops x86_cpuinit; +extern struct x86_platform_ops x86_platform; + +extern void x86_init_noop(void); +extern void x86_init_uint_noop(unsigned int unused); + +#endif diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 832cb838cb48..4ba419b668a5 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -31,8 +31,8 @@ GCOV_PROFILE_paravirt.o := n obj-y := process_$(BITS).o signal.o entry_$(BITS).o obj-y += traps.o irq.o irq_$(BITS).o dumpstack_$(BITS).o -obj-y += time_$(BITS).o ioport.o ldt.o dumpstack.o -obj-y += setup.o i8259.o irqinit.o +obj-y += time.o ioport.o ldt.o dumpstack.o +obj-y += setup.o x86_init.o i8259.o irqinit.o obj-$(CONFIG_X86_VISWS) += visws_quirks.o obj-$(CONFIG_X86_32) += probe_roms_32.o obj-$(CONFIG_X86_32) += sys_i386_32.o i386_ksyms_32.o @@ -105,6 +105,7 @@ obj-$(CONFIG_SCx200) += scx200.o scx200-y += scx200_32.o obj-$(CONFIG_OLPC) += olpc.o +obj-$(CONFIG_X86_MRST) += mrst.o microcode-y := microcode_core.o microcode-$(CONFIG_MICROCODE_INTEL) += microcode_intel.o diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 159740decc41..a34601f52987 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -36,6 +36,7 @@ #include <linux/mm.h> #include <asm/perf_counter.h> +#include <asm/x86_init.h> #include <asm/pgalloc.h> #include <asm/atomic.h> #include <asm/mpspec.h> @@ -1709,7 +1710,7 @@ int __init APIC_init_uniprocessor(void) localise_nmi_watchdog(); #endif - setup_boot_clock(); + x86_init.timers.setup_percpu_clockev(); #ifdef CONFIG_X86_64 check_nmi_watchdog(); #endif diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c index 676cdac385c0..77a06413b6b2 100644 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -112,7 +112,7 @@ static physid_mask_t bigsmp_ioapic_phys_id_map(physid_mask_t phys_map) return physids_promote(0xFFL); } -static int bigsmp_check_phys_apicid_present(int boot_cpu_physical_apicid) +static int bigsmp_check_phys_apicid_present(int phys_apicid) { return 1; } diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 3c8f9e75d038..809e1cf86d6b 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -96,6 +96,11 @@ struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; /* # of MP IRQ source entries */ int mp_irq_entries; +/* Number of legacy interrupts */ +static int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY; +/* GSI interrupts */ +static int nr_irqs_gsi = NR_IRQS_LEGACY; + #if defined (CONFIG_MCA) || defined (CONFIG_EISA) int mp_bus_id_to_type[MAX_MP_BUSSES]; #endif @@ -173,6 +178,12 @@ static struct irq_cfg irq_cfgx[NR_IRQS] = { [15] = { .vector = IRQ15_VECTOR, }, }; +void __init io_apic_disable_legacy(void) +{ + nr_legacy_irqs = 0; + nr_irqs_gsi = 0; +} + int __init arch_early_irq_init(void) { struct irq_cfg *cfg; @@ -190,7 +201,7 @@ int __init arch_early_irq_init(void) desc->chip_data = &cfg[i]; zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); - if (i < NR_IRQS_LEGACY) + if (i < nr_legacy_irqs) cpumask_setall(cfg[i].domain); } @@ -867,7 +878,7 @@ static int __init find_isa_irq_apic(int irq, int type) */ static int EISA_ELCR(unsigned int irq) { - if (irq < NR_IRQS_LEGACY) { + if (irq < nr_legacy_irqs) { unsigned int port = 0x4d0 + (irq >> 3); return (inb(port) >> (irq & 7)) & 1; } @@ -1464,7 +1475,7 @@ static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq } ioapic_register_intr(irq, desc, trigger); - if (irq < NR_IRQS_LEGACY) + if (irq < nr_legacy_irqs) disable_8259A_irq(irq); ioapic_write_entry(apic_id, pin, entry); @@ -1831,7 +1842,7 @@ __apicdebuginit(void) print_PIC(void) unsigned int v; unsigned long flags; - if (apic_verbosity == APIC_QUIET) + if (apic_verbosity == APIC_QUIET || !nr_legacy_irqs) return; printk(KERN_DEBUG "\nprinting PIC contents\n"); @@ -1894,6 +1905,10 @@ void __init enable_IO_APIC(void) spin_unlock_irqrestore(&ioapic_lock, flags); nr_ioapic_registers[apic] = reg_01.bits.entries+1; } + + if (!nr_legacy_irqs) + return; + for(apic = 0; apic < nr_ioapics; apic++) { int pin; /* See if any of the pins is in ExtINT mode */ @@ -1948,6 +1963,9 @@ void disable_IO_APIC(void) */ clear_IO_APIC(); + if (!nr_legacy_irqs) + return; + /* * If the i8259 is routed through an IOAPIC * Put that IOAPIC in virtual wire mode @@ -1994,7 +2012,7 @@ void disable_IO_APIC(void) * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 */ -static void __init setup_ioapic_ids_from_mpc(void) +void __init setup_ioapic_ids_from_mpc(void) { union IO_APIC_reg_00 reg_00; physid_mask_t phys_id_present_map; @@ -2003,9 +2021,8 @@ static void __init setup_ioapic_ids_from_mpc(void) unsigned char old_id; unsigned long flags; - if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) + if (acpi_ioapic) return; - /* * Don't check I/O APIC IDs for xAPIC systems. They have * no meaning without the serial APIC bus. @@ -2179,7 +2196,7 @@ static unsigned int startup_ioapic_irq(unsigned int irq) struct irq_cfg *cfg; spin_lock_irqsave(&ioapic_lock, flags); - if (irq < NR_IRQS_LEGACY) { + if (irq < nr_legacy_irqs) { disable_8259A_irq(irq); if (i8259A_irq_pending(irq)) was_pending = 1; @@ -2657,7 +2674,7 @@ static inline void init_IO_APIC_traps(void) * so default to an old-fashioned 8259 * interrupt if we can.. */ - if (irq < NR_IRQS_LEGACY) + if (irq < nr_legacy_irqs) make_8259A_irq(irq); else /* Strange. Oh, well.. */ @@ -2993,7 +3010,7 @@ out: * the I/O APIC in all cases now. No actual device should request * it anyway. --macro */ -#define PIC_IRQS (1 << PIC_CASCADE_IR) +#define PIC_IRQS (1UL << PIC_CASCADE_IR) void __init setup_IO_APIC(void) { @@ -3001,21 +3018,19 @@ void __init setup_IO_APIC(void) /* * calling enable_IO_APIC() is moved to setup_local_APIC for BP */ - - io_apic_irqs = ~PIC_IRQS; + io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL; apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); /* * Set up IO-APIC IRQ routing. */ -#ifdef CONFIG_X86_32 - if (!acpi_ioapic) - setup_ioapic_ids_from_mpc(); -#endif + x86_init.mpparse.setup_ioapic_ids(); + sync_Arb_IDs(); setup_IO_APIC_irqs(); init_IO_APIC_traps(); - check_timer(); + if (nr_legacy_irqs) + check_timer(); } /* @@ -3116,7 +3131,6 @@ static int __init ioapic_init_sysfs(void) device_initcall(ioapic_init_sysfs); -static int nr_irqs_gsi = NR_IRQS_LEGACY; /* * Dynamic irq allocate and deallocation */ @@ -3856,7 +3870,7 @@ static int __io_apic_set_pci_routing(struct device *dev, int irq, /* * IRQs < 16 are already in the irq_2_pin[] map */ - if (irq >= NR_IRQS_LEGACY) { + if (irq >= nr_legacy_irqs) { cfg = desc->chip_data; if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { printk(KERN_INFO "can not add pin %d for irq %d\n", diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c index ca96e68f0d23..efa00e2b8505 100644 --- a/arch/x86/kernel/apic/numaq_32.c +++ b/arch/x86/kernel/apic/numaq_32.c @@ -66,7 +66,6 @@ struct mpc_trans { unsigned short trans_reserved; }; -/* x86_quirks member */ static int mpc_record; static struct mpc_trans *translation_table[MAX_MPC_ENTRY]; @@ -130,10 +129,9 @@ void __cpuinit numaq_tsc_disable(void) } } -static int __init numaq_pre_time_init(void) +static void __init numaq_tsc_init(void) { numaq_tsc_disable(); - return 0; } static inline int generate_logical_apicid(int quad, int phys_apicid) @@ -177,6 +175,19 @@ static void mpc_oem_pci_bus(struct mpc_bus *m) quad_local_to_mp_bus_id[quad][local] = m->busid; } +/* + * Called from mpparse code. + * mode = 0: prescan + * mode = 1: one mpc entry scanned + */ +static void numaq_mpc_record(unsigned int mode) +{ + if (!mode) + mpc_record = 0; + else + mpc_record++; +} + static void __init MP_translation_info(struct mpc_trans *m) { printk(KERN_INFO @@ -206,9 +217,9 @@ static int __init mpf_checksum(unsigned char *mp, int len) /* * Read/parse the MPC oem tables */ -static void __init - smp_read_mpc_oem(struct mpc_oemtable *oemtable, unsigned short oemsize) +static void __init smp_read_mpc_oem(struct mpc_table *mpc) { + struct mpc_oemtable *oemtable = (void *)(long)mpc->oemptr; int count = sizeof(*oemtable); /* the header size */ unsigned char *oemptr = ((unsigned char *)oemtable) + count; @@ -250,29 +261,6 @@ static void __init } } -static int __init numaq_setup_ioapic_ids(void) -{ - /* so can skip it */ - return 1; -} - -static struct x86_quirks numaq_x86_quirks __initdata = { - .arch_pre_time_init = numaq_pre_time_init, - .arch_time_init = NULL, - .arch_pre_intr_init = NULL, - .arch_memory_setup = NULL, - .arch_intr_init = NULL, - .arch_trap_init = NULL, - .mach_get_smp_config = NULL, - .mach_find_smp_config = NULL, - .mpc_record = &mpc_record, - .mpc_apic_id = mpc_apic_id, - .mpc_oem_bus_info = mpc_oem_bus_info, - .mpc_oem_pci_bus = mpc_oem_pci_bus, - .smp_read_mpc_oem = smp_read_mpc_oem, - .setup_ioapic_ids = numaq_setup_ioapic_ids, -}; - static __init void early_check_numaq(void) { /* @@ -286,8 +274,15 @@ static __init void early_check_numaq(void) if (smp_found_config) early_get_smp_config(); - if (found_numaq) - x86_quirks = &numaq_x86_quirks; + if (found_numaq) { + x86_init.mpparse.mpc_record = numaq_mpc_record; + x86_init.mpparse.setup_ioapic_ids = x86_init_noop; + x86_init.mpparse.mpc_apic_id = mpc_apic_id; + x86_init.mpparse.smp_read_mpc_oem = smp_read_mpc_oem; + x86_init.mpparse.mpc_oem_pci_bus = mpc_oem_pci_bus; + x86_init.mpparse.mpc_oem_bus_info = mpc_oem_bus_info; + x86_init.timers.tsc_pre_init = numaq_tsc_init; + } } int __init get_memcfg_numaq(void) @@ -418,7 +413,7 @@ static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid) /* Where the IO area was mapped on multiquad, always 0 otherwise */ void *xquad_portio; -static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid) +static inline int numaq_check_phys_apicid_present(int phys_apicid) { return 1; } diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c index eafdfbd1ea95..645ecc4ff0be 100644 --- a/arch/x86/kernel/apic/summit_32.c +++ b/arch/x86/kernel/apic/summit_32.c @@ -272,7 +272,7 @@ static physid_mask_t summit_apicid_to_cpu_present(int apicid) return physid_mask_of_physid(0); } -static int summit_check_phys_apicid_present(int boot_cpu_physical_apicid) +static int summit_check_phys_apicid_present(int physical_apicid) { return 1; } diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 2055fc2b2e6b..2fea97eccf77 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -34,7 +34,6 @@ #include <asm/mce.h> #include <asm/msr.h> #include <asm/pat.h> -#include <linux/smp.h> #ifdef CONFIG_X86_LOCAL_APIC #include <asm/uv/uv.h> diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c index 479cc8c418c1..7d5c3b0ea8da 100644 --- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c +++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c @@ -523,6 +523,21 @@ static const struct dmi_system_id sw_any_bug_dmi_table[] = { }, { } }; + +static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) +{ + /* http://www.intel.com/Assets/PDF/specupdate/314554.pdf + * AL30: A Machine Check Exception (MCE) Occurring during an + * Enhanced Intel SpeedStep Technology Ratio Change May Cause + * Both Processor Cores to Lock Up when HT is enabled*/ + if (c->x86_vendor == X86_VENDOR_INTEL) { + if ((c->x86 == 15) && + (c->x86_model == 6) && + (c->x86_mask == 8) && smt_capable()) + return -ENODEV; + } + return 0; +} #endif static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) @@ -537,6 +552,12 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) dprintk("acpi_cpufreq_cpu_init\n"); +#ifdef CONFIG_SMP + result = acpi_cpufreq_blacklist(c); + if (result) + return result; +#endif + data = kzalloc(sizeof(struct acpi_cpufreq_data), GFP_KERNEL); if (!data) return -ENOMEM; diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c index 2a50ef891000..6394aa5c7985 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c @@ -605,9 +605,10 @@ static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst, return 0; } -static void invalidate_entry(struct powernow_k8_data *data, unsigned int entry) +static void invalidate_entry(struct cpufreq_frequency_table *powernow_table, + unsigned int entry) { - data->powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID; + powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID; } static void print_basics(struct powernow_k8_data *data) @@ -854,6 +855,10 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) goto err_out; } + /* fill in data */ + data->numps = data->acpi_data.state_count; + powernow_k8_acpi_pst_values(data, 0); + if (cpu_family == CPU_HW_PSTATE) ret_val = fill_powernow_table_pstate(data, powernow_table); else @@ -866,11 +871,8 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) powernow_table[data->acpi_data.state_count].index = 0; data->powernow_table = powernow_table; - /* fill in data */ - data->numps = data->acpi_data.state_count; if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) print_basics(data); - powernow_k8_acpi_pst_values(data, 0); /* notify BIOS that we exist */ acpi_processor_notify_smm(THIS_MODULE); @@ -914,13 +916,13 @@ static int fill_powernow_table_pstate(struct powernow_k8_data *data, "bad value %d.\n", i, index); printk(KERN_ERR PFX "Please report to BIOS " "manufacturer\n"); - invalidate_entry(data, i); + invalidate_entry(powernow_table, i); continue; } rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi); if (!(hi & HW_PSTATE_VALID_MASK)) { dprintk("invalid pstate %d, ignoring\n", index); - invalidate_entry(data, i); + invalidate_entry(powernow_table, i); continue; } @@ -941,7 +943,6 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table) { int i; - int cntlofreq = 0; for (i = 0; i < data->acpi_data.state_count; i++) { u32 fid; @@ -970,7 +971,7 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data, /* verify frequency is OK */ if ((freq > (MAX_FREQ * 1000)) || (freq < (MIN_FREQ * 1000))) { dprintk("invalid freq %u kHz, ignoring\n", freq); - invalidate_entry(data, i); + invalidate_entry(powernow_table, i); continue; } @@ -978,38 +979,17 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data, * BIOSs are using "off" to indicate invalid */ if (vid == VID_OFF) { dprintk("invalid vid %u, ignoring\n", vid); - invalidate_entry(data, i); + invalidate_entry(powernow_table, i); continue; } - /* verify only 1 entry from the lo frequency table */ - if (fid < HI_FID_TABLE_BOTTOM) { - if (cntlofreq) { - /* if both entries are the same, - * ignore this one ... */ - if ((freq != powernow_table[cntlofreq].frequency) || - (index != powernow_table[cntlofreq].index)) { - printk(KERN_ERR PFX - "Too many lo freq table " - "entries\n"); - return 1; - } - - dprintk("double low frequency table entry, " - "ignoring it.\n"); - invalidate_entry(data, i); - continue; - } else - cntlofreq = i; - } - if (freq != (data->acpi_data.states[i].core_frequency * 1000)) { printk(KERN_INFO PFX "invalid freq entries " "%u kHz vs. %u kHz\n", freq, (unsigned int) (data->acpi_data.states[i].core_frequency * 1000)); - invalidate_entry(data, i); + invalidate_entry(powernow_table, i); continue; } } diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c index 93ba8eeb100a..08be922de33a 100644 --- a/arch/x86/kernel/cpu/hypervisor.c +++ b/arch/x86/kernel/cpu/hypervisor.c @@ -34,13 +34,6 @@ detect_hypervisor_vendor(struct cpuinfo_x86 *c) c->x86_hyper_vendor = X86_HYPER_VENDOR_NONE; } -unsigned long get_hypervisor_tsc_freq(void) -{ - if (boot_cpu_data.x86_hyper_vendor == X86_HYPER_VENDOR_VMWARE) - return vmware_get_tsc_khz(); - return 0; -} - static inline void __cpuinit hypervisor_set_feature_bits(struct cpuinfo_x86 *c) { @@ -55,3 +48,10 @@ void __cpuinit init_hypervisor(struct cpuinfo_x86 *c) detect_hypervisor_vendor(c); hypervisor_set_feature_bits(c); } + +void __init init_hypervisor_platform(void) +{ + init_hypervisor(&boot_cpu_data); + if (boot_cpu_data.x86_hyper_vendor == X86_HYPER_VENDOR_VMWARE) + vmware_platform_setup(); +} diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c index bc24f514ec93..0a46b4df5d80 100644 --- a/arch/x86/kernel/cpu/vmware.c +++ b/arch/x86/kernel/cpu/vmware.c @@ -24,6 +24,7 @@ #include <linux/dmi.h> #include <asm/div64.h> #include <asm/vmware.h> +#include <asm/x86_init.h> #define CPUID_VMWARE_INFO_LEAF 0x40000000 #define VMWARE_HYPERVISOR_MAGIC 0x564D5868 @@ -47,21 +48,29 @@ static inline int __vmware_platform(void) return eax != (uint32_t)-1 && ebx == VMWARE_HYPERVISOR_MAGIC; } -static unsigned long __vmware_get_tsc_khz(void) +static unsigned long vmware_get_tsc_khz(void) { uint64_t tsc_hz; uint32_t eax, ebx, ecx, edx; VMWARE_PORT(GETHZ, eax, ebx, ecx, edx); - if (ebx == UINT_MAX) - return 0; tsc_hz = eax | (((uint64_t)ebx) << 32); do_div(tsc_hz, 1000); BUG_ON(tsc_hz >> 32); return tsc_hz; } +void __init vmware_platform_setup(void) +{ + uint32_t eax, ebx, ecx, edx; + + VMWARE_PORT(GETHZ, eax, ebx, ecx, edx); + + if (ebx != UINT_MAX) + x86_platform.calibrate_tsc = vmware_get_tsc_khz; +} + /* * While checking the dmi string infomation, just checking the product * serial key should be enough, as this will always have a VMware @@ -87,12 +96,6 @@ int vmware_platform(void) return 0; } -unsigned long vmware_get_tsc_khz(void) -{ - BUG_ON(!vmware_platform()); - return __vmware_get_tsc_khz(); -} - /* * VMware hypervisor takes care of exporting a reliable TSC to the guest. * Still, due to timing difference when running on virtual cpus, the TSC can diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c index b07af8861244..6a52d4b36a30 100644 --- a/arch/x86/kernel/cpuid.c +++ b/arch/x86/kernel/cpuid.c @@ -182,7 +182,7 @@ static struct notifier_block __refdata cpuid_class_cpu_notifier = .notifier_call = cpuid_class_cpu_callback, }; -static char *cpuid_nodename(struct device *dev) +static char *cpuid_devnode(struct device *dev, mode_t *mode) { return kasprintf(GFP_KERNEL, "cpu/%u/cpuid", MINOR(dev->devt)); } @@ -203,7 +203,7 @@ static int __init cpuid_init(void) err = PTR_ERR(cpuid_class); goto out_chrdev; } - cpuid_class->nodename = cpuid_nodename; + cpuid_class->devnode = cpuid_devnode; for_each_online_cpu(i) { err = cpuid_device_create(i); if (err != 0) diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index 147005a1cc3c..a3210ce1eccd 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -1455,28 +1455,11 @@ char *__init default_machine_specific_memory_setup(void) return who; } -char *__init __attribute__((weak)) machine_specific_memory_setup(void) -{ - if (x86_quirks->arch_memory_setup) { - char *who = x86_quirks->arch_memory_setup(); - - if (who) - return who; - } - return default_machine_specific_memory_setup(); -} - -/* Overridden in paravirt.c if CONFIG_PARAVIRT */ -char * __init __attribute__((weak)) memory_setup(void) -{ - return machine_specific_memory_setup(); -} - void __init setup_memory_map(void) { char *who; - who = memory_setup(); + who = x86_init.resources.memory_setup(); memcpy(&e820_saved, &e820, sizeof(struct e820map)); printk(KERN_INFO "BIOS-provided physical RAM map:\n"); e820_print_map(who); diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c index fe26ba3e3451..ad5bd988fb79 100644 --- a/arch/x86/kernel/efi.c +++ b/arch/x86/kernel/efi.c @@ -42,6 +42,7 @@ #include <asm/time.h> #include <asm/cacheflush.h> #include <asm/tlbflush.h> +#include <asm/x86_init.h> #define EFI_DEBUG 1 #define PFX "EFI: " @@ -453,6 +454,9 @@ void __init efi_init(void) if (add_efi_memmap) do_add_efi_memmap(); + x86_platform.get_wallclock = efi_get_time; + x86_platform.set_wallclock = efi_set_rtc_mmss; + /* Setup for EFI runtime service */ reboot_type = BOOT_EFI; diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c index 3f8579f8d42c..4f8e2507e8f3 100644 --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -11,8 +11,21 @@ #include <asm/setup.h> #include <asm/sections.h> #include <asm/e820.h> -#include <asm/bios_ebda.h> +#include <asm/page.h> #include <asm/trampoline.h> +#include <asm/apic.h> +#include <asm/io_apic.h> +#include <asm/bios_ebda.h> + +static void __init i386_default_early_setup(void) +{ + /* Initilize 32bit specific setup functions */ + x86_init.resources.probe_roms = probe_roms; + x86_init.resources.reserve_resources = i386_reserve_resources; + x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc; + + reserve_ebda_region(); +} void __init i386_start_kernel(void) { @@ -29,7 +42,16 @@ void __init i386_start_kernel(void) reserve_early(ramdisk_image, ramdisk_end, "RAMDISK"); } #endif - reserve_ebda_region(); + + /* Call the subarch specific early setup function */ + switch (boot_params.hdr.hardware_subarch) { + case X86_SUBARCH_MRST: + x86_mrst_early_setup(); + break; + default: + i386_default_early_setup(); + break; + } /* * At this point everything still needed from the boot loader diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index 70eaa852c732..0b06cd778fd9 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -23,8 +23,8 @@ #include <asm/sections.h> #include <asm/kdebug.h> #include <asm/e820.h> -#include <asm/bios_ebda.h> #include <asm/trampoline.h> +#include <asm/bios_ebda.h> static void __init zap_identity_mappings(void) { diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S index 7ffec6b3b331..b766e8c7252d 100644 --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -157,6 +157,7 @@ subarch_entries: .long default_entry /* normal x86/PC */ .long lguest_entry /* lguest hypervisor */ .long xen_entry /* Xen hypervisor */ + .long default_entry /* Moorestown MID */ num_subarch_entries = (. - subarch_entries) / 4 .previous #endif /* CONFIG_PARAVIRT */ diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c index 5cf36c053ac4..23c167925a5c 100644 --- a/arch/x86/kernel/i8253.c +++ b/arch/x86/kernel/i8253.c @@ -19,12 +19,6 @@ DEFINE_SPINLOCK(i8253_lock); EXPORT_SYMBOL(i8253_lock); -#ifdef CONFIG_X86_32 -static void pit_disable_clocksource(void); -#else -static inline void pit_disable_clocksource(void) { } -#endif - /* * HPET replaces the PIT, when enabled. So we need to know, which of * the two timers is used @@ -57,12 +51,10 @@ static void init_pit_timer(enum clock_event_mode mode, outb_pit(0, PIT_CH0); outb_pit(0, PIT_CH0); } - pit_disable_clocksource(); break; case CLOCK_EVT_MODE_ONESHOT: /* One shot setup */ - pit_disable_clocksource(); outb_pit(0x38, PIT_MODE); break; @@ -200,17 +192,6 @@ static struct clocksource pit_cs = { .shift = 20, }; -static void pit_disable_clocksource(void) -{ - /* - * Use mult to check whether it is registered or not - */ - if (pit_cs.mult) { - clocksource_unregister(&pit_cs); - pit_cs.mult = 0; - } -} - static int __init init_pit_clocksource(void) { /* diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c index ccf8ab54f31a..300883112e3d 100644 --- a/arch/x86/kernel/irqinit.c +++ b/arch/x86/kernel/irqinit.c @@ -116,7 +116,7 @@ int vector_used_by_percpu_irq(unsigned int vector) return 0; } -static void __init init_ISA_irqs(void) +void __init init_ISA_irqs(void) { int i; @@ -140,8 +140,10 @@ static void __init init_ISA_irqs(void) } } -/* Overridden in paravirt.c */ -void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ"))); +void __init init_IRQ(void) +{ + x86_init.irqs.intr_init(); +} static void __init smp_intr_init(void) { @@ -213,32 +215,12 @@ static void __init apic_intr_init(void) #endif } -/** - * x86_quirk_pre_intr_init - initialisation prior to setting up interrupt vectors - * - * Description: - * Perform any necessary interrupt initialisation prior to setting up - * the "ordinary" interrupt call gates. For legacy reasons, the ISA - * interrupts should be initialised here if the machine emulates a PC - * in any way. - **/ -static void __init x86_quirk_pre_intr_init(void) -{ -#ifdef CONFIG_X86_32 - if (x86_quirks->arch_pre_intr_init) { - if (x86_quirks->arch_pre_intr_init()) - return; - } -#endif - init_ISA_irqs(); -} - void __init native_init_IRQ(void) { int i; /* Execute any quirks before the call gates are initialised: */ - x86_quirk_pre_intr_init(); + x86_init.irqs.pre_vector_init(); apic_intr_init(); @@ -258,12 +240,6 @@ void __init native_init_IRQ(void) #ifdef CONFIG_X86_32 /* - * Call quirks after call gates are initialised (usually add in - * the architecture specific gates): - */ - x86_quirk_intr_init(); - - /* * External FPU? Set up irq13 if so, for * original braindamaged IBM FERR coupling. */ diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index e5efcdcca31b..feaeb0d3aa4f 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -22,6 +22,8 @@ #include <asm/msr.h> #include <asm/apic.h> #include <linux/percpu.h> + +#include <asm/x86_init.h> #include <asm/reboot.h> #define KVM_SCALE 22 @@ -182,12 +184,13 @@ void __init kvmclock_init(void) if (kvmclock && kvm_para_has_feature(KVM_FEATURE_CLOCKSOURCE)) { if (kvm_register_clock("boot clock")) return; - pv_time_ops.get_wallclock = kvm_get_wallclock; - pv_time_ops.set_wallclock = kvm_set_wallclock; pv_time_ops.sched_clock = kvm_clock_read; - pv_time_ops.get_tsc_khz = kvm_get_tsc_khz; + x86_platform.calibrate_tsc = kvm_get_tsc_khz; + x86_platform.get_wallclock = kvm_get_wallclock; + x86_platform.set_wallclock = kvm_set_wallclock; #ifdef CONFIG_X86_LOCAL_APIC - pv_apic_ops.setup_secondary_clock = kvm_setup_secondary_clock; + x86_cpuinit.setup_percpu_clockev = + kvm_setup_secondary_clock; #endif #ifdef CONFIG_SMP smp_ops.smp_prepare_boot_cpu = kvm_smp_prepare_boot_cpu; diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index 9371448290ac..0db7969b0dde 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -236,7 +236,7 @@ static const struct file_operations microcode_fops = { static struct miscdevice microcode_dev = { .minor = MICROCODE_MINOR, .name = "microcode", - .devnode = "cpu/microcode", + .nodename = "cpu/microcode", .fops = µcode_fops, }; diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index fcd513bf2846..5be95ef4ffec 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -45,6 +45,11 @@ static int __init mpf_checksum(unsigned char *mp, int len) return sum & 0xFF; } +int __init default_mpc_apic_id(struct mpc_cpu *m) +{ + return m->apicid; +} + static void __init MP_processor_info(struct mpc_cpu *m) { int apicid; @@ -55,10 +60,7 @@ static void __init MP_processor_info(struct mpc_cpu *m) return; } - if (x86_quirks->mpc_apic_id) - apicid = x86_quirks->mpc_apic_id(m); - else - apicid = m->apicid; + apicid = x86_init.mpparse.mpc_apic_id(m); if (m->cpuflag & CPU_BOOTPROCESSOR) { bootup_cpu = " (Bootup-CPU)"; @@ -70,16 +72,18 @@ static void __init MP_processor_info(struct mpc_cpu *m) } #ifdef CONFIG_X86_IO_APIC -static void __init MP_bus_info(struct mpc_bus *m) +void __init default_mpc_oem_bus_info(struct mpc_bus *m, char *str) { - char str[7]; memcpy(str, m->bustype, 6); str[6] = 0; + apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); +} - if (x86_quirks->mpc_oem_bus_info) - x86_quirks->mpc_oem_bus_info(m, str); - else - apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); +static void __init MP_bus_info(struct mpc_bus *m) +{ + char str[7]; + + x86_init.mpparse.mpc_oem_bus_info(m, str); #if MAX_MP_BUSSES < 256 if (m->busid >= MAX_MP_BUSSES) { @@ -96,8 +100,8 @@ static void __init MP_bus_info(struct mpc_bus *m) mp_bus_id_to_type[m->busid] = MP_BUS_ISA; #endif } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { - if (x86_quirks->mpc_oem_pci_bus) - x86_quirks->mpc_oem_pci_bus(m); + if (x86_init.mpparse.mpc_oem_pci_bus) + x86_init.mpparse.mpc_oem_pci_bus(m); clear_bit(m->busid, mp_bus_not_pci); #if defined(CONFIG_EISA) || defined(CONFIG_MCA) @@ -291,6 +295,8 @@ static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt) 1, mpc, mpc->length, 1); } +void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { } + static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) { char str[16]; @@ -312,16 +318,13 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) if (early) return 1; - if (mpc->oemptr && x86_quirks->smp_read_mpc_oem) { - struct mpc_oemtable *oem_table = (void *)(long)mpc->oemptr; - x86_quirks->smp_read_mpc_oem(oem_table, mpc->oemsize); - } + if (mpc->oemptr) + x86_init.mpparse.smp_read_mpc_oem(mpc); /* * Now process the configuration blocks. */ - if (x86_quirks->mpc_record) - *x86_quirks->mpc_record = 0; + x86_init.mpparse.mpc_record(0); while (count < mpc->length) { switch (*mpt) { @@ -353,8 +356,7 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) count = mpc->length; break; } - if (x86_quirks->mpc_record) - (*x86_quirks->mpc_record)++; + x86_init.mpparse.mpc_record(1); } #ifdef CONFIG_X86_BIGSMP @@ -608,7 +610,7 @@ static int __init check_physptr(struct mpf_intel *mpf, unsigned int early) /* * Scan the memory blocks for an SMP configuration block. */ -static void __init __get_smp_config(unsigned int early) +void __init default_get_smp_config(unsigned int early) { struct mpf_intel *mpf = mpf_found; @@ -625,11 +627,6 @@ static void __init __get_smp_config(unsigned int early) if (acpi_lapic && acpi_ioapic) return; - if (x86_quirks->mach_get_smp_config) { - if (x86_quirks->mach_get_smp_config(early)) - return; - } - printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->specification); #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) @@ -670,16 +667,6 @@ static void __init __get_smp_config(unsigned int early) */ } -void __init early_get_smp_config(void) -{ - __get_smp_config(1); -} - -void __init get_smp_config(void) -{ - __get_smp_config(0); -} - static void __init smp_reserve_bootmem(struct mpf_intel *mpf) { unsigned long size = get_mpc_size(mpf->physptr); @@ -745,14 +732,10 @@ static int __init smp_scan_config(unsigned long base, unsigned long length, return 0; } -static void __init __find_smp_config(unsigned int reserve) +void __init default_find_smp_config(unsigned int reserve) { unsigned int address; - if (x86_quirks->mach_find_smp_config) { - if (x86_quirks->mach_find_smp_config(reserve)) - return; - } /* * FIXME: Linux assumes you have 640K of base ram.. * this continues the error... @@ -787,16 +770,6 @@ static void __init __find_smp_config(unsigned int reserve) smp_scan_config(address, 0x400, reserve); } -void __init early_find_smp_config(void) -{ - __find_smp_config(0); -} - -void __init find_smp_config(void) -{ - __find_smp_config(1); -} - #ifdef CONFIG_X86_IO_APIC static u8 __initdata irq_used[MAX_IRQ_SOURCES]; diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c new file mode 100644 index 000000000000..3b7078abc871 --- /dev/null +++ b/arch/x86/kernel/mrst.c @@ -0,0 +1,24 @@ +/* + * mrst.c: Intel Moorestown platform specific setup code + * + * (C) Copyright 2008 Intel Corporation + * Author: Jacob Pan (jacob.jun.pan@intel.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ +#include <linux/init.h> + +#include <asm/setup.h> + +/* + * Moorestown specific x86_init function overrides and early setup + * calls. + */ +void __init x86_mrst_early_setup(void) +{ + x86_init.resources.probe_roms = x86_init_noop; + x86_init.resources.reserve_resources = x86_init_noop; +} diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 7dd950094178..6a3cefc7dda1 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -241,7 +241,7 @@ static struct notifier_block __refdata msr_class_cpu_notifier = { .notifier_call = msr_class_cpu_callback, }; -static char *msr_nodename(struct device *dev) +static char *msr_devnode(struct device *dev, mode_t *mode) { return kasprintf(GFP_KERNEL, "cpu/%u/msr", MINOR(dev->devt)); } @@ -262,7 +262,7 @@ static int __init msr_init(void) err = PTR_ERR(msr_class); goto out_chrdev; } - msr_class->nodename = msr_nodename; + msr_class->devnode = msr_devnode; for_each_online_cpu(i) { err = msr_device_create(i); if (err != 0) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index f5b0b4a01fb2..1b1739d16310 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -54,17 +54,12 @@ u64 _paravirt_ident_64(u64 x) return x; } -static void __init default_banner(void) +void __init default_banner(void) { printk(KERN_INFO "Booting paravirtualized kernel on %s\n", pv_info.name); } -char *memory_setup(void) -{ - return pv_init_ops.memory_setup(); -} - /* Simple instruction patching code. */ #define DEF_NATIVE(ops, name, code) \ extern const char start_##ops##_##name[], end_##ops##_##name[]; \ @@ -188,11 +183,6 @@ unsigned paravirt_patch_insns(void *insnbuf, unsigned len, return insn_len; } -void init_IRQ(void) -{ - pv_irq_ops.init_IRQ(); -} - static void native_flush_tlb(void) { __native_flush_tlb(); @@ -218,13 +208,6 @@ extern void native_irq_enable_sysexit(void); extern void native_usergs_sysret32(void); extern void native_usergs_sysret64(void); -static int __init print_banner(void) -{ - pv_init_ops.banner(); - return 0; -} -core_initcall(print_banner); - static struct resource reserve_ioports = { .start = 0, .end = IO_SPACE_LIMIT, @@ -320,21 +303,13 @@ struct pv_info pv_info = { struct pv_init_ops pv_init_ops = { .patch = native_patch, - .banner = default_banner, - .arch_setup = paravirt_nop, - .memory_setup = machine_specific_memory_setup, }; struct pv_time_ops pv_time_ops = { - .time_init = hpet_time_init, - .get_wallclock = native_get_wallclock, - .set_wallclock = native_set_wallclock, .sched_clock = native_sched_clock, - .get_tsc_khz = native_calibrate_tsc, }; struct pv_irq_ops pv_irq_ops = { - .init_IRQ = native_init_IRQ, .save_fl = __PV_IS_CALLEE_SAVE(native_save_fl), .restore_fl = __PV_IS_CALLEE_SAVE(native_restore_fl), .irq_disable = __PV_IS_CALLEE_SAVE(native_irq_disable), @@ -409,8 +384,6 @@ struct pv_cpu_ops pv_cpu_ops = { struct pv_apic_ops pv_apic_ops = { #ifdef CONFIG_X86_LOCAL_APIC - .setup_boot_clock = setup_boot_APIC_clock, - .setup_secondary_clock = setup_secondary_APIC_clock, .startup_ipi_hook = paravirt_nop, #endif }; @@ -424,13 +397,6 @@ struct pv_apic_ops pv_apic_ops = { #endif struct pv_mmu_ops pv_mmu_ops = { -#ifndef CONFIG_X86_64 - .pagetable_setup_start = native_pagetable_setup_start, - .pagetable_setup_done = native_pagetable_setup_done, -#else - .pagetable_setup_start = paravirt_nop, - .pagetable_setup_done = paravirt_nop, -#endif .read_cr2 = native_read_cr2, .write_cr2 = native_write_cr2, diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c index 5d465b207e72..1cfbbfc3ae26 100644 --- a/arch/x86/kernel/rtc.c +++ b/arch/x86/kernel/rtc.c @@ -8,6 +8,7 @@ #include <linux/pnp.h> #include <asm/vsyscall.h> +#include <asm/x86_init.h> #include <asm/time.h> #ifdef CONFIG_X86_32 @@ -165,33 +166,29 @@ void rtc_cmos_write(unsigned char val, unsigned char addr) } EXPORT_SYMBOL(rtc_cmos_write); -static int set_rtc_mmss(unsigned long nowtime) +int update_persistent_clock(struct timespec now) { unsigned long flags; int retval; spin_lock_irqsave(&rtc_lock, flags); - retval = set_wallclock(nowtime); + retval = x86_platform.set_wallclock(now.tv_sec); spin_unlock_irqrestore(&rtc_lock, flags); return retval; } /* not static: needed by APM */ -unsigned long read_persistent_clock(void) +void read_persistent_clock(struct timespec *ts) { unsigned long retval, flags; spin_lock_irqsave(&rtc_lock, flags); - retval = get_wallclock(); + retval = x86_platform.get_wallclock(); spin_unlock_irqrestore(&rtc_lock, flags); - return retval; -} - -int update_persistent_clock(struct timespec now) -{ - return set_rtc_mmss(now.tv_sec); + ts->tv_sec = retval; + ts->tv_nsec = 0; } unsigned long long native_read_tsc(void) diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 19f15c4076fb..a55f6609fe1f 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -109,10 +109,6 @@ #include <asm/numa_64.h> #endif -#ifndef ARCH_SETUP -#define ARCH_SETUP -#endif - /* * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries. * The direct mapping extends to max_pfn_mapped, so that we can directly access @@ -134,9 +130,9 @@ int default_cpu_present_to_apicid(int mps_cpu) return __default_cpu_present_to_apicid(mps_cpu); } -int default_check_phys_apicid_present(int boot_cpu_physical_apicid) +int default_check_phys_apicid_present(int phys_apicid) { - return __default_check_phys_apicid_present(boot_cpu_physical_apicid); + return __default_check_phys_apicid_present(phys_apicid); } #endif @@ -172,13 +168,6 @@ static struct resource bss_resource = { #ifdef CONFIG_X86_32 -static struct resource video_ram_resource = { - .name = "Video RAM area", - .start = 0xa0000, - .end = 0xbffff, - .flags = IORESOURCE_BUSY | IORESOURCE_MEM -}; - /* cpu data as detected by the assembly code in head.S */ struct cpuinfo_x86 new_cpu_data __cpuinitdata = {0, 0, 0, 0, -1, 1, 0, 0, -1}; /* common cpu data for all cpus */ @@ -606,7 +595,7 @@ static struct resource standard_io_resources[] = { .flags = IORESOURCE_BUSY | IORESOURCE_IO } }; -static void __init reserve_standard_io_resources(void) +void __init reserve_standard_io_resources(void) { int i; @@ -638,10 +627,6 @@ static int __init setup_elfcorehdr(char *arg) early_param("elfcorehdr", setup_elfcorehdr); #endif -static struct x86_quirks default_x86_quirks __initdata; - -struct x86_quirks *x86_quirks __initdata = &default_x86_quirks; - #ifdef CONFIG_X86_RESERVE_LOW_64K static int __init dmi_low_memory_corruption(const struct dmi_system_id *d) { @@ -773,7 +758,7 @@ void __init setup_arch(char **cmdline_p) } #endif - ARCH_SETUP + x86_init.oem.arch_setup(); setup_memory_map(); parse_setup_data(); @@ -844,11 +829,9 @@ void __init setup_arch(char **cmdline_p) * VMware detection requires dmi to be available, so this * needs to be done after dmi_scan_machine, for the BP. */ - init_hypervisor(&boot_cpu_data); + init_hypervisor_platform(); -#ifdef CONFIG_X86_32 - probe_roms(); -#endif + x86_init.resources.probe_roms(); /* after parse_early_param, so could debug it */ insert_resource(&iomem_resource, &code_resource); @@ -983,10 +966,9 @@ void __init setup_arch(char **cmdline_p) kvmclock_init(); #endif - paravirt_pagetable_setup_start(swapper_pg_dir); + x86_init.paging.pagetable_setup_start(swapper_pg_dir); paging_init(); - paravirt_pagetable_setup_done(swapper_pg_dir); - paravirt_post_allocator_init(); + x86_init.paging.pagetable_setup_done(swapper_pg_dir); tboot_probe(); @@ -1003,13 +985,11 @@ void __init setup_arch(char **cmdline_p) */ acpi_boot_init(); -#if defined(CONFIG_X86_MPPARSE) || defined(CONFIG_X86_VISWS) /* * get boot-time SMP configuration: */ if (smp_found_config) get_smp_config(); -#endif prefill_possible_map(); @@ -1028,10 +1008,7 @@ void __init setup_arch(char **cmdline_p) e820_reserve_resources(); e820_mark_nosave_regions(max_low_pfn); -#ifdef CONFIG_X86_32 - request_resource(&iomem_resource, &video_ram_resource); -#endif - reserve_standard_io_resources(); + x86_init.resources.reserve_resources(); e820_setup_gap(); @@ -1043,78 +1020,22 @@ void __init setup_arch(char **cmdline_p) conswitchp = &dummy_con; #endif #endif + x86_init.oem.banner(); } #ifdef CONFIG_X86_32 -/** - * x86_quirk_intr_init - post gate setup interrupt initialisation - * - * Description: - * Fill in any interrupts that may have been left out by the general - * init_IRQ() routine. interrupts having to do with the machine rather - * than the devices on the I/O bus (like APIC interrupts in intel MP - * systems) are started here. - **/ -void __init x86_quirk_intr_init(void) -{ - if (x86_quirks->arch_intr_init) { - if (x86_quirks->arch_intr_init()) - return; - } -} - -/** - * x86_quirk_trap_init - initialise system specific traps - * - * Description: - * Called as the final act of trap_init(). Used in VISWS to initialise - * the various board specific APIC traps. - **/ -void __init x86_quirk_trap_init(void) -{ - if (x86_quirks->arch_trap_init) { - if (x86_quirks->arch_trap_init()) - return; - } -} - -static struct irqaction irq0 = { - .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER, - .name = "timer" +static struct resource video_ram_resource = { + .name = "Video RAM area", + .start = 0xa0000, + .end = 0xbffff, + .flags = IORESOURCE_BUSY | IORESOURCE_MEM }; -/** - * x86_quirk_pre_time_init - do any specific initialisations before. - * - **/ -void __init x86_quirk_pre_time_init(void) +void __init i386_reserve_resources(void) { - if (x86_quirks->arch_pre_time_init) - x86_quirks->arch_pre_time_init(); + request_resource(&iomem_resource, &video_ram_resource); + reserve_standard_io_resources(); } -/** - * x86_quirk_time_init - do any specific initialisations for the system timer. - * - * Description: - * Must plug the system timer interrupt source at HZ into the IRQ listed - * in irq_vectors.h:TIMER_IRQ - **/ -void __init x86_quirk_time_init(void) -{ - if (x86_quirks->arch_time_init) { - /* - * A nonzero return code does not mean failure, it means - * that the architecture quirk does not want any - * generic (timer) setup to be performed after this: - */ - if (x86_quirks->arch_time_init()) - return; - } - - irq0.mask = cpumask_of_cpu(0); - setup_irq(0, &irq0); -} #endif /* CONFIG_X86_32 */ diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index a25eeec00080..09c5e077dff7 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -324,7 +324,7 @@ notrace static void __cpuinit start_secondary(void *unused) /* enable local interrupts */ local_irq_enable(); - setup_secondary_clock(); + x86_cpuinit.setup_percpu_clockev(); wmb(); cpu_idle(); @@ -1114,7 +1114,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) printk(KERN_INFO "CPU%d: ", 0); print_cpu_info(&cpu_data(0)); - setup_boot_clock(); + x86_init.timers.setup_percpu_clockev(); if (is_uv_system()) uv_system_init(); diff --git a/arch/x86/kernel/time.c b/arch/x86/kernel/time.c new file mode 100644 index 000000000000..e293ac56c723 --- /dev/null +++ b/arch/x86/kernel/time.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 1991,1992,1995 Linus Torvalds + * Copyright (c) 1994 Alan Modra + * Copyright (c) 1995 Markus Kuhn + * Copyright (c) 1996 Ingo Molnar + * Copyright (c) 1998 Andrea Arcangeli + * Copyright (c) 2002,2006 Vojtech Pavlik + * Copyright (c) 2003 Andi Kleen + * + */ + +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/time.h> +#include <linux/mca.h> + +#include <asm/vsyscall.h> +#include <asm/x86_init.h> +#include <asm/i8259.h> +#include <asm/i8253.h> +#include <asm/timer.h> +#include <asm/hpet.h> +#include <asm/time.h> + +#if defined(CONFIG_X86_32) && defined(CONFIG_X86_IO_APIC) +int timer_ack; +#endif + +#ifdef CONFIG_X86_64 +volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES; +#endif + +unsigned long profile_pc(struct pt_regs *regs) +{ + unsigned long pc = instruction_pointer(regs); + + if (!user_mode_vm(regs) && in_lock_functions(pc)) { +#ifdef CONFIG_FRAME_POINTER + return *(unsigned long *)(regs->bp + sizeof(long)); +#else + unsigned long *sp = (unsigned long *)regs->sp; + /* + * Return address is either directly at stack pointer + * or above a saved flags. Eflags has bits 22-31 zero, + * kernel addresses don't. + */ + if (sp[0] >> 22) + return sp[0]; + if (sp[1] >> 22) + return sp[1]; +#endif + } + return pc; +} +EXPORT_SYMBOL(profile_pc); + +/* + * Default timer interrupt handler for PIT/HPET + */ +static irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + /* Keep nmi watchdog up to date */ + inc_irq_stat(irq0_irqs); + + /* Optimized out for !IO_APIC and x86_64 */ + if (timer_ack) { + /* + * Subtle, when I/O APICs are used we have to ack timer IRQ + * manually to deassert NMI lines for the watchdog if run + * on an 82489DX-based system. + */ + spin_lock(&i8259A_lock); + outb(0x0c, PIC_MASTER_OCW3); + /* Ack the IRQ; AEOI will end it automatically. */ + inb(PIC_MASTER_POLL); + spin_unlock(&i8259A_lock); + } + + global_clock_event->event_handler(global_clock_event); + + /* MCA bus quirk: Acknowledge irq0 by setting bit 7 in port 0x61 */ + if (MCA_bus) + outb_p(inb_p(0x61)| 0x80, 0x61); + + return IRQ_HANDLED; +} + +static struct irqaction irq0 = { + .handler = timer_interrupt, + .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER, + .name = "timer" +}; + +void __init setup_default_timer_irq(void) +{ + irq0.mask = cpumask_of_cpu(0); + setup_irq(0, &irq0); +} + +/* Default timer init function */ +void __init hpet_time_init(void) +{ + if (!hpet_enable()) + setup_pit_timer(); + setup_default_timer_irq(); +} + +static __init void x86_late_time_init(void) +{ + x86_init.timers.timer_init(); + tsc_init(); +} + +/* + * Initialize TSC and delay the periodic timer init to + * late x86_late_time_init() so ioremap works. + */ +void __init time_init(void) +{ + late_time_init = x86_late_time_init; +} diff --git a/arch/x86/kernel/time_32.c b/arch/x86/kernel/time_32.c deleted file mode 100644 index 5c5d87f0b2e1..000000000000 --- a/arch/x86/kernel/time_32.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) 1991, 1992, 1995 Linus Torvalds - * - * This file contains the PC-specific time handling details: - * reading the RTC at bootup, etc.. - * 1994-07-02 Alan Modra - * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime - * 1995-03-26 Markus Kuhn - * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887 - * precision CMOS clock update - * 1996-05-03 Ingo Molnar - * fixed time warps in do_[slow|fast]_gettimeoffset() - * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 - * "A Kernel Model for Precision Timekeeping" by Dave Mills - * 1998-09-05 (Various) - * More robust do_fast_gettimeoffset() algorithm implemented - * (works with APM, Cyrix 6x86MX and Centaur C6), - * monotonic gettimeofday() with fast_get_timeoffset(), - * drift-proof precision TSC calibration on boot - * (C. Scott Ananian <cananian@alumni.princeton.edu>, Andrew D. - * Balsa <andrebalsa@altern.org>, Philip Gladstone <philip@raptor.com>; - * ported from 2.0.35 Jumbo-9 by Michael Krause <m.krause@tu-harburg.de>). - * 1998-12-16 Andrea Arcangeli - * Fixed Jumbo-9 code in 2.1.131: do_gettimeofday was missing 1 jiffy - * because was not accounting lost_ticks. - * 1998-12-24 Copyright (C) 1998 Andrea Arcangeli - * Fixed a xtime SMP race (we need the xtime_lock rw spinlock to - * serialize accesses to xtime/lost_ticks). - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/time.h> -#include <linux/mca.h> - -#include <asm/setup.h> -#include <asm/hpet.h> -#include <asm/time.h> -#include <asm/timer.h> - -#include <asm/do_timer.h> - -int timer_ack; - -unsigned long profile_pc(struct pt_regs *regs) -{ - unsigned long pc = instruction_pointer(regs); - -#ifdef CONFIG_SMP - if (!user_mode_vm(regs) && in_lock_functions(pc)) { -#ifdef CONFIG_FRAME_POINTER - return *(unsigned long *)(regs->bp + sizeof(long)); -#else - unsigned long *sp = (unsigned long *)®s->sp; - - /* Return address is either directly at stack pointer - or above a saved flags. Eflags has bits 22-31 zero, - kernel addresses don't. */ - if (sp[0] >> 22) - return sp[0]; - if (sp[1] >> 22) - return sp[1]; -#endif - } -#endif - return pc; -} -EXPORT_SYMBOL(profile_pc); - -/* - * This is the same as the above, except we _also_ save the current - * Time Stamp Counter value at the time of the timer interrupt, so that - * we later on can estimate the time of day more exactly. - */ -irqreturn_t timer_interrupt(int irq, void *dev_id) -{ - /* Keep nmi watchdog up to date */ - inc_irq_stat(irq0_irqs); - -#ifdef CONFIG_X86_IO_APIC - if (timer_ack) { - /* - * Subtle, when I/O APICs are used we have to ack timer IRQ - * manually to deassert NMI lines for the watchdog if run - * on an 82489DX-based system. - */ - spin_lock(&i8259A_lock); - outb(0x0c, PIC_MASTER_OCW3); - /* Ack the IRQ; AEOI will end it automatically. */ - inb(PIC_MASTER_POLL); - spin_unlock(&i8259A_lock); - } -#endif - - do_timer_interrupt_hook(); - -#ifdef CONFIG_MCA - if (MCA_bus) { - /* The PS/2 uses level-triggered interrupts. You can't - turn them off, nor would you want to (any attempt to - enable edge-triggered interrupts usually gets intercepted by a - special hardware circuit). Hence we have to acknowledge - the timer interrupt. Through some incredibly stupid - design idea, the reset for IRQ 0 is done by setting the - high bit of the PPI port B (0x61). Note that some PS/2s, - notably the 55SX, work fine if this is removed. */ - - u8 irq_v = inb_p(0x61); /* read the current state */ - outb_p(irq_v | 0x80, 0x61); /* reset the IRQ */ - } -#endif - - return IRQ_HANDLED; -} - -/* Duplicate of time_init() below, with hpet_enable part added */ -void __init hpet_time_init(void) -{ - if (!hpet_enable()) - setup_pit_timer(); - x86_quirk_time_init(); -} - -/* - * This is called directly from init code; we must delay timer setup in the - * HPET case as we can't make the decision to turn on HPET this early in the - * boot process. - * - * The chosen time_init function will usually be hpet_time_init, above, but - * in the case of virtual hardware, an alternative function may be substituted. - */ -void __init time_init(void) -{ - x86_quirk_pre_time_init(); - tsc_init(); - late_time_init = choose_time_init(); -} diff --git a/arch/x86/kernel/time_64.c b/arch/x86/kernel/time_64.c deleted file mode 100644 index 5ba343e61844..000000000000 --- a/arch/x86/kernel/time_64.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * "High Precision Event Timer" based timekeeping. - * - * Copyright (c) 1991,1992,1995 Linus Torvalds - * Copyright (c) 1994 Alan Modra - * Copyright (c) 1995 Markus Kuhn - * Copyright (c) 1996 Ingo Molnar - * Copyright (c) 1998 Andrea Arcangeli - * Copyright (c) 2002,2006 Vojtech Pavlik - * Copyright (c) 2003 Andi Kleen - * RTC support code taken from arch/i386/kernel/timers/time_hpet.c - */ - -#include <linux/clockchips.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/module.h> -#include <linux/time.h> -#include <linux/mca.h> -#include <linux/nmi.h> - -#include <asm/i8253.h> -#include <asm/hpet.h> -#include <asm/vgtod.h> -#include <asm/time.h> -#include <asm/timer.h> - -volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES; - -unsigned long profile_pc(struct pt_regs *regs) -{ - unsigned long pc = instruction_pointer(regs); - - /* Assume the lock function has either no stack frame or a copy - of flags from PUSHF - Eflags always has bits 22 and up cleared unlike kernel addresses. */ - if (!user_mode_vm(regs) && in_lock_functions(pc)) { -#ifdef CONFIG_FRAME_POINTER - return *(unsigned long *)(regs->bp + sizeof(long)); -#else - unsigned long *sp = (unsigned long *)regs->sp; - if (sp[0] >> 22) - return sp[0]; - if (sp[1] >> 22) - return sp[1]; -#endif - } - return pc; -} -EXPORT_SYMBOL(profile_pc); - -static irqreturn_t timer_interrupt(int irq, void *dev_id) -{ - inc_irq_stat(irq0_irqs); - - global_clock_event->event_handler(global_clock_event); - -#ifdef CONFIG_MCA - if (MCA_bus) { - u8 irq_v = inb_p(0x61); /* read the current state */ - outb_p(irq_v|0x80, 0x61); /* reset the IRQ */ - } -#endif - - return IRQ_HANDLED; -} - -/* calibrate_cpu is used on systems with fixed rate TSCs to determine - * processor frequency */ -#define TICK_COUNT 100000000 -unsigned long __init calibrate_cpu(void) -{ - int tsc_start, tsc_now; - int i, no_ctr_free; - unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0; - unsigned long flags; - - for (i = 0; i < 4; i++) - if (avail_to_resrv_perfctr_nmi_bit(i)) - break; - no_ctr_free = (i == 4); - if (no_ctr_free) { - WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... " - "cpu_khz value may be incorrect.\n"); - i = 3; - rdmsrl(MSR_K7_EVNTSEL3, evntsel3); - wrmsrl(MSR_K7_EVNTSEL3, 0); - rdmsrl(MSR_K7_PERFCTR3, pmc3); - } else { - reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i); - reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i); - } - local_irq_save(flags); - /* start measuring cycles, incrementing from 0 */ - wrmsrl(MSR_K7_PERFCTR0 + i, 0); - wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76); - rdtscl(tsc_start); - do { - rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now); - tsc_now = get_cycles(); - } while ((tsc_now - tsc_start) < TICK_COUNT); - - local_irq_restore(flags); - if (no_ctr_free) { - wrmsrl(MSR_K7_EVNTSEL3, 0); - wrmsrl(MSR_K7_PERFCTR3, pmc3); - wrmsrl(MSR_K7_EVNTSEL3, evntsel3); - } else { - release_perfctr_nmi(MSR_K7_PERFCTR0 + i); - release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); - } - - return pmc_now * tsc_khz / (tsc_now - tsc_start); -} - -static struct irqaction irq0 = { - .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_IRQPOLL | IRQF_NOBALANCING | IRQF_TIMER, - .name = "timer" -}; - -void __init hpet_time_init(void) -{ - if (!hpet_enable()) - setup_pit_timer(); - - setup_irq(0, &irq0); -} - -void __init time_init(void) -{ - tsc_init(); - - late_time_init = choose_time_init(); -} diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 83264922a878..9346e102338d 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -59,12 +59,12 @@ #include <asm/mach_traps.h> #ifdef CONFIG_X86_64 +#include <asm/x86_init.h> #include <asm/pgalloc.h> #include <asm/proto.h> #else #include <asm/processor-flags.h> #include <asm/setup.h> -#include <asm/traps.h> asmlinkage int system_call(void); @@ -972,7 +972,5 @@ void __init trap_init(void) */ cpu_init(); -#ifdef CONFIG_X86_32 - x86_quirk_trap_init(); -#endif + x86_init.irqs.trap_init(); } diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 71f4368b357e..17409e8d1097 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -17,6 +17,8 @@ #include <asm/time.h> #include <asm/delay.h> #include <asm/hypervisor.h> +#include <asm/nmi.h> +#include <asm/x86_init.h> unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ EXPORT_SYMBOL(cpu_khz); @@ -400,15 +402,9 @@ unsigned long native_calibrate_tsc(void) { u64 tsc1, tsc2, delta, ref1, ref2; unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; - unsigned long flags, latch, ms, fast_calibrate, hv_tsc_khz; + unsigned long flags, latch, ms, fast_calibrate; int hpet = is_hpet_enabled(), i, loopmin; - hv_tsc_khz = get_hypervisor_tsc_freq(); - if (hv_tsc_khz) { - printk(KERN_INFO "TSC: Frequency read from the hypervisor\n"); - return hv_tsc_khz; - } - local_irq_save(flags); fast_calibrate = quick_pit_calibrate(); local_irq_restore(flags); @@ -566,7 +562,7 @@ int recalibrate_cpu_khz(void) unsigned long cpu_khz_old = cpu_khz; if (cpu_has_tsc) { - tsc_khz = calibrate_tsc(); + tsc_khz = x86_platform.calibrate_tsc(); cpu_khz = tsc_khz; cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy, @@ -744,10 +740,16 @@ static cycle_t __vsyscall_fn vread_tsc(void) } #endif +static void resume_tsc(void) +{ + clocksource_tsc.cycle_last = 0; +} + static struct clocksource clocksource_tsc = { .name = "tsc", .rating = 300, .read = read_tsc, + .resume = resume_tsc, .mask = CLOCKSOURCE_MASK(64), .shift = 22, .flags = CLOCK_SOURCE_IS_CONTINUOUS | @@ -761,12 +763,14 @@ void mark_tsc_unstable(char *reason) { if (!tsc_unstable) { tsc_unstable = 1; - printk("Marking TSC unstable due to %s\n", reason); + printk(KERN_INFO "Marking TSC unstable due to %s\n", reason); /* Change only the rating, when not registered */ if (clocksource_tsc.mult) - clocksource_change_rating(&clocksource_tsc, 0); - else + clocksource_mark_unstable(&clocksource_tsc); + else { + clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE; clocksource_tsc.rating = 0; + } } } @@ -852,15 +856,71 @@ static void __init init_tsc_clocksource(void) clocksource_register(&clocksource_tsc); } +#ifdef CONFIG_X86_64 +/* + * calibrate_cpu is used on systems with fixed rate TSCs to determine + * processor frequency + */ +#define TICK_COUNT 100000000 +static unsigned long __init calibrate_cpu(void) +{ + int tsc_start, tsc_now; + int i, no_ctr_free; + unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0; + unsigned long flags; + + for (i = 0; i < 4; i++) + if (avail_to_resrv_perfctr_nmi_bit(i)) + break; + no_ctr_free = (i == 4); + if (no_ctr_free) { + WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... " + "cpu_khz value may be incorrect.\n"); + i = 3; + rdmsrl(MSR_K7_EVNTSEL3, evntsel3); + wrmsrl(MSR_K7_EVNTSEL3, 0); + rdmsrl(MSR_K7_PERFCTR3, pmc3); + } else { + reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i); + reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i); + } + local_irq_save(flags); + /* start measuring cycles, incrementing from 0 */ + wrmsrl(MSR_K7_PERFCTR0 + i, 0); + wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76); + rdtscl(tsc_start); + do { + rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now); + tsc_now = get_cycles(); + } while ((tsc_now - tsc_start) < TICK_COUNT); + + local_irq_restore(flags); + if (no_ctr_free) { + wrmsrl(MSR_K7_EVNTSEL3, 0); + wrmsrl(MSR_K7_PERFCTR3, pmc3); + wrmsrl(MSR_K7_EVNTSEL3, evntsel3); + } else { + release_perfctr_nmi(MSR_K7_PERFCTR0 + i); + release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); + } + + return pmc_now * tsc_khz / (tsc_now - tsc_start); +} +#else +static inline unsigned long calibrate_cpu(void) { return cpu_khz; } +#endif + void __init tsc_init(void) { u64 lpj; int cpu; + x86_init.timers.tsc_pre_init(); + if (!cpu_has_tsc) return; - tsc_khz = calibrate_tsc(); + tsc_khz = x86_platform.calibrate_tsc(); cpu_khz = tsc_khz; if (!tsc_khz) { @@ -868,11 +928,9 @@ void __init tsc_init(void) return; } -#ifdef CONFIG_X86_64 if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) && (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)) cpu_khz = calibrate_cpu(); -#endif printk("Detected %lu.%03lu MHz processor.\n", (unsigned long)cpu_khz / 1000, diff --git a/arch/x86/kernel/visws_quirks.c b/arch/x86/kernel/visws_quirks.c index 31ffc24eec4d..f068553a1b17 100644 --- a/arch/x86/kernel/visws_quirks.c +++ b/arch/x86/kernel/visws_quirks.c @@ -30,6 +30,7 @@ #include <asm/setup.h> #include <asm/apic.h> #include <asm/e820.h> +#include <asm/time.h> #include <asm/io.h> #include <linux/kernel_stat.h> @@ -53,7 +54,7 @@ int is_visws_box(void) return visws_board_type >= 0; } -static int __init visws_time_init(void) +static void __init visws_time_init(void) { printk(KERN_INFO "Starting Cobalt Timer system clock\n"); @@ -66,21 +67,13 @@ static int __init visws_time_init(void) /* Enable (unmask) the timer interrupt */ co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK); - /* - * Zero return means the generic timer setup code will set up - * the standard vector: - */ - return 0; + setup_default_timer_irq(); } -static int __init visws_pre_intr_init(void) +/* Replaces the default init_ISA_irqs in the generic setup */ +static void __init visws_pre_intr_init(void) { init_VISWS_APIC_irqs(); - - /* - * We dont want ISA irqs to be set up by the generic code: - */ - return 1; } /* Quirk for machine specific memory setup. */ @@ -156,12 +149,8 @@ static void visws_machine_power_off(void) outl(PIIX_SPECIAL_STOP, 0xCFC); } -static int __init visws_get_smp_config(unsigned int early) +static void __init visws_get_smp_config(unsigned int early) { - /* - * Prevent MP-table parsing by the generic code: - */ - return 1; } /* @@ -208,7 +197,7 @@ static void __init MP_processor_info(struct mpc_cpu *m) apic_version[m->apicid] = ver; } -static int __init visws_find_smp_config(unsigned int reserve) +static void __init visws_find_smp_config(unsigned int reserve) { struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS); unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS)); @@ -230,21 +219,9 @@ static int __init visws_find_smp_config(unsigned int reserve) MP_processor_info(mp++); mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; - - return 1; } -static int visws_trap_init(void); - -static struct x86_quirks visws_x86_quirks __initdata = { - .arch_time_init = visws_time_init, - .arch_pre_intr_init = visws_pre_intr_init, - .arch_memory_setup = visws_memory_setup, - .arch_intr_init = NULL, - .arch_trap_init = visws_trap_init, - .mach_get_smp_config = visws_get_smp_config, - .mach_find_smp_config = visws_find_smp_config, -}; +static void visws_trap_init(void); void __init visws_early_detect(void) { @@ -257,11 +234,14 @@ void __init visws_early_detect(void) return; /* - * Install special quirks for timer, interrupt and memory setup: - * Fall back to generic behavior for traps: - * Override generic MP-table parsing: + * Override the default platform setup functions */ - x86_quirks = &visws_x86_quirks; + x86_init.resources.memory_setup = visws_memory_setup; + x86_init.mpparse.get_smp_config = visws_get_smp_config; + x86_init.mpparse.find_smp_config = visws_find_smp_config; + x86_init.irqs.pre_vector_init = visws_pre_intr_init; + x86_init.irqs.trap_init = visws_trap_init; + x86_init.timers.timer_init = visws_time_init; /* * Install reboot quirks: @@ -400,12 +380,10 @@ static __init void cobalt_init(void) co_apic_read(CO_APIC_ID)); } -static int __init visws_trap_init(void) +static void __init visws_trap_init(void) { lithium_init(); cobalt_init(); - - return 1; } /* diff --git a/arch/x86/kernel/vmi_32.c b/arch/x86/kernel/vmi_32.c index 95a7289e4b0c..31e6f6cfe53e 100644 --- a/arch/x86/kernel/vmi_32.c +++ b/arch/x86/kernel/vmi_32.c @@ -817,15 +817,15 @@ static inline int __init activate_vmi(void) vmi_timer_ops.set_alarm = vmi_get_function(VMI_CALL_SetAlarm); vmi_timer_ops.cancel_alarm = vmi_get_function(VMI_CALL_CancelAlarm); - pv_time_ops.time_init = vmi_time_init; - pv_time_ops.get_wallclock = vmi_get_wallclock; - pv_time_ops.set_wallclock = vmi_set_wallclock; + x86_init.timers.timer_init = vmi_time_init; #ifdef CONFIG_X86_LOCAL_APIC - pv_apic_ops.setup_boot_clock = vmi_time_bsp_init; - pv_apic_ops.setup_secondary_clock = vmi_time_ap_init; + x86_init.timers.setup_percpu_clockev = vmi_time_bsp_init; + x86_cpuinit.setup_percpu_clockev = vmi_time_ap_init; #endif pv_time_ops.sched_clock = vmi_sched_clock; - pv_time_ops.get_tsc_khz = vmi_tsc_khz; + x86_platform.calibrate_tsc = vmi_tsc_khz; + x86_platform.get_wallclock = vmi_get_wallclock; + x86_platform.set_wallclock = vmi_set_wallclock; /* We have true wallclock functions; disable CMOS clock sync */ no_sync_cmos_clock = 1; diff --git a/arch/x86/kernel/vmiclock_32.c b/arch/x86/kernel/vmiclock_32.c index 2b3eb82efeeb..611b9e2360d3 100644 --- a/arch/x86/kernel/vmiclock_32.c +++ b/arch/x86/kernel/vmiclock_32.c @@ -68,7 +68,7 @@ unsigned long long vmi_sched_clock(void) return cycles_2_ns(vmi_timer_ops.get_cycle_counter(VMI_CYCLES_AVAILABLE)); } -/* paravirt_ops.get_tsc_khz = vmi_tsc_khz */ +/* x86_platform.calibrate_tsc = vmi_tsc_khz */ unsigned long vmi_tsc_khz(void) { unsigned long long khz; diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c index 25ee06a80aad..cf53a78e2dcf 100644 --- a/arch/x86/kernel/vsyscall_64.c +++ b/arch/x86/kernel/vsyscall_64.c @@ -87,6 +87,7 @@ void update_vsyscall(struct timespec *wall_time, struct clocksource *clock) vsyscall_gtod_data.wall_time_sec = wall_time->tv_sec; vsyscall_gtod_data.wall_time_nsec = wall_time->tv_nsec; vsyscall_gtod_data.wall_to_monotonic = wall_to_monotonic; + vsyscall_gtod_data.wall_time_coarse = __current_kernel_time(); write_sequnlock_irqrestore(&vsyscall_gtod_data.lock, flags); } diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c new file mode 100644 index 000000000000..4449a4a2c2ed --- /dev/null +++ b/arch/x86/kernel/x86_init.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de> + * + * For licencing details see kernel-base/COPYING + */ +#include <linux/init.h> + +#include <asm/bios_ebda.h> +#include <asm/paravirt.h> +#include <asm/mpspec.h> +#include <asm/setup.h> +#include <asm/apic.h> +#include <asm/e820.h> +#include <asm/time.h> +#include <asm/irq.h> +#include <asm/tsc.h> + +void __cpuinit x86_init_noop(void) { } +void __init x86_init_uint_noop(unsigned int unused) { } +void __init x86_init_pgd_noop(pgd_t *unused) { } + +/* + * The platform setup functions are preset with the default functions + * for standard PC hardware. + */ +struct x86_init_ops x86_init __initdata = { + + .resources = { + .probe_roms = x86_init_noop, + .reserve_resources = reserve_standard_io_resources, + .memory_setup = default_machine_specific_memory_setup, + }, + + .mpparse = { + .mpc_record = x86_init_uint_noop, + .setup_ioapic_ids = x86_init_noop, + .mpc_apic_id = default_mpc_apic_id, + .smp_read_mpc_oem = default_smp_read_mpc_oem, + .mpc_oem_bus_info = default_mpc_oem_bus_info, + .find_smp_config = default_find_smp_config, + .get_smp_config = default_get_smp_config, + }, + + .irqs = { + .pre_vector_init = init_ISA_irqs, + .intr_init = native_init_IRQ, + .trap_init = x86_init_noop, + }, + + .oem = { + .arch_setup = x86_init_noop, + .banner = default_banner, + }, + + .paging = { + .pagetable_setup_start = native_pagetable_setup_start, + .pagetable_setup_done = native_pagetable_setup_done, + }, + + .timers = { + .setup_percpu_clockev = setup_boot_APIC_clock, + .tsc_pre_init = x86_init_noop, + .timer_init = hpet_time_init, + }, +}; + +struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = { + .setup_percpu_clockev = setup_secondary_APIC_clock, +}; + +struct x86_platform_ops x86_platform = { + .calibrate_tsc = native_calibrate_tsc, + .get_wallclock = mach_get_cmos_time, + .set_wallclock = mach_set_rtc_mmss, +}; diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c index d677fa9ca650..4cb7d5d18b8e 100644 --- a/arch/x86/lguest/boot.c +++ b/arch/x86/lguest/boot.c @@ -1262,7 +1262,6 @@ __init void lguest_init(void) */ /* Interrupt-related operations */ - pv_irq_ops.init_IRQ = lguest_init_IRQ; pv_irq_ops.save_fl = PV_CALLEE_SAVE(save_fl); pv_irq_ops.restore_fl = __PV_IS_CALLEE_SAVE(lg_restore_fl); pv_irq_ops.irq_disable = PV_CALLEE_SAVE(irq_disable); @@ -1270,7 +1269,6 @@ __init void lguest_init(void) pv_irq_ops.safe_halt = lguest_safe_halt; /* Setup operations */ - pv_init_ops.memory_setup = lguest_memory_setup; pv_init_ops.patch = lguest_patch; /* Intercepts of various CPU instructions */ @@ -1320,10 +1318,11 @@ __init void lguest_init(void) set_lguest_basic_apic_ops(); #endif - /* Time operations */ - pv_time_ops.get_wallclock = lguest_get_wallclock; - pv_time_ops.time_init = lguest_time_init; - pv_time_ops.get_tsc_khz = lguest_tsc_khz; + x86_init.resources.memory_setup = lguest_memory_setup; + x86_init.irqs.intr_init = lguest_init_IRQ; + x86_init.timers.timer_init = lguest_time_init; + x86_platform.calibrate_tsc = lguest_tsc_khz; + x86_platform.get_wallclock = lguest_get_wallclock; /* * Now is a good time to look at the implementations of these functions diff --git a/arch/x86/mm/kmemcheck/shadow.c b/arch/x86/mm/kmemcheck/shadow.c index e773b6bd0079..3f66b82076a3 100644 --- a/arch/x86/mm/kmemcheck/shadow.c +++ b/arch/x86/mm/kmemcheck/shadow.c @@ -1,7 +1,6 @@ #include <linux/kmemcheck.h> #include <linux/module.h> #include <linux/mm.h> -#include <linux/module.h> #include <asm/page.h> #include <asm/pgtable.h> diff --git a/arch/x86/vdso/vclock_gettime.c b/arch/x86/vdso/vclock_gettime.c index 6a40b78b46aa..ee55754cc3c5 100644 --- a/arch/x86/vdso/vclock_gettime.c +++ b/arch/x86/vdso/vclock_gettime.c @@ -86,14 +86,47 @@ notrace static noinline int do_monotonic(struct timespec *ts) return 0; } +notrace static noinline int do_realtime_coarse(struct timespec *ts) +{ + unsigned long seq; + do { + seq = read_seqbegin(>od->lock); + ts->tv_sec = gtod->wall_time_coarse.tv_sec; + ts->tv_nsec = gtod->wall_time_coarse.tv_nsec; + } while (unlikely(read_seqretry(>od->lock, seq))); + return 0; +} + +notrace static noinline int do_monotonic_coarse(struct timespec *ts) +{ + unsigned long seq, ns, secs; + do { + seq = read_seqbegin(>od->lock); + secs = gtod->wall_time_coarse.tv_sec; + ns = gtod->wall_time_coarse.tv_nsec; + secs += gtod->wall_to_monotonic.tv_sec; + ns += gtod->wall_to_monotonic.tv_nsec; + } while (unlikely(read_seqretry(>od->lock, seq))); + vset_normalized_timespec(ts, secs, ns); + return 0; +} + notrace int __vdso_clock_gettime(clockid_t clock, struct timespec *ts) { - if (likely(gtod->sysctl_enabled && gtod->clock.vread)) + if (likely(gtod->sysctl_enabled)) switch (clock) { case CLOCK_REALTIME: - return do_realtime(ts); + if (likely(gtod->clock.vread)) + return do_realtime(ts); + break; case CLOCK_MONOTONIC: - return do_monotonic(ts); + if (likely(gtod->clock.vread)) + return do_monotonic(ts); + break; + case CLOCK_REALTIME_COARSE: + return do_realtime_coarse(ts); + case CLOCK_MONOTONIC_COARSE: + return do_monotonic_coarse(ts); } return vdso_fallback_gettime(clock, ts); } diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 0dd0c2c6cae0..544eb7496531 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -912,19 +912,9 @@ static const struct pv_info xen_info __initdata = { static const struct pv_init_ops xen_init_ops __initdata = { .patch = xen_patch, - - .banner = xen_banner, - .memory_setup = xen_memory_setup, - .arch_setup = xen_arch_setup, - .post_allocator_init = xen_post_allocator_init, }; static const struct pv_time_ops xen_time_ops __initdata = { - .time_init = xen_time_init, - - .set_wallclock = xen_set_wallclock, - .get_wallclock = xen_get_wallclock, - .get_tsc_khz = xen_tsc_khz, .sched_clock = xen_sched_clock, }; @@ -990,8 +980,6 @@ static const struct pv_cpu_ops xen_cpu_ops __initdata = { static const struct pv_apic_ops xen_apic_ops __initdata = { #ifdef CONFIG_X86_LOCAL_APIC - .setup_boot_clock = paravirt_nop, - .setup_secondary_clock = paravirt_nop, .startup_ipi_hook = paravirt_nop, #endif }; @@ -1070,7 +1058,18 @@ asmlinkage void __init xen_start_kernel(void) pv_time_ops = xen_time_ops; pv_cpu_ops = xen_cpu_ops; pv_apic_ops = xen_apic_ops; - pv_mmu_ops = xen_mmu_ops; + + x86_init.resources.memory_setup = xen_memory_setup; + x86_init.oem.arch_setup = xen_arch_setup; + x86_init.oem.banner = xen_banner; + + x86_init.timers.timer_init = xen_time_init; + x86_init.timers.setup_percpu_clockev = x86_init_noop; + x86_cpuinit.setup_percpu_clockev = x86_init_noop; + + x86_platform.calibrate_tsc = xen_tsc_khz; + x86_platform.get_wallclock = xen_get_wallclock; + x86_platform.set_wallclock = xen_set_wallclock; /* * Set up some pagetable state before starting to set any ptes. @@ -1095,6 +1094,7 @@ asmlinkage void __init xen_start_kernel(void) */ xen_setup_stackprotector(); + xen_init_mmu_ops(); xen_init_irq_ops(); xen_init_cpuid_mask(); diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c index cfd17799bd6d..9d30105a0c4a 100644 --- a/arch/x86/xen/irq.c +++ b/arch/x86/xen/irq.c @@ -1,5 +1,7 @@ #include <linux/hardirq.h> +#include <asm/x86_init.h> + #include <xen/interface/xen.h> #include <xen/interface/sched.h> #include <xen/interface/vcpu.h> @@ -112,8 +114,6 @@ static void xen_halt(void) } static const struct pv_irq_ops xen_irq_ops __initdata = { - .init_IRQ = xen_init_IRQ, - .save_fl = PV_CALLEE_SAVE(xen_save_fl), .restore_fl = PV_CALLEE_SAVE(xen_restore_fl), .irq_disable = PV_CALLEE_SAVE(xen_irq_disable), @@ -129,4 +129,5 @@ static const struct pv_irq_ops xen_irq_ops __initdata = { void __init xen_init_irq_ops() { pv_irq_ops = xen_irq_ops; + x86_init.irqs.intr_init = xen_init_IRQ; } diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c index 4ceb28581652..093dd59b5385 100644 --- a/arch/x86/xen/mmu.c +++ b/arch/x86/xen/mmu.c @@ -1229,9 +1229,12 @@ static __init void xen_pagetable_setup_start(pgd_t *base) { } +static void xen_post_allocator_init(void); + static __init void xen_pagetable_setup_done(pgd_t *base) { xen_setup_shared_info(); + xen_post_allocator_init(); } static void xen_write_cr2(unsigned long cr2) @@ -1841,7 +1844,7 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot) #endif } -__init void xen_post_allocator_init(void) +static __init void xen_post_allocator_init(void) { pv_mmu_ops.set_pte = xen_set_pte; pv_mmu_ops.set_pmd = xen_set_pmd; @@ -1875,10 +1878,7 @@ static void xen_leave_lazy_mmu(void) preempt_enable(); } -const struct pv_mmu_ops xen_mmu_ops __initdata = { - .pagetable_setup_start = xen_pagetable_setup_start, - .pagetable_setup_done = xen_pagetable_setup_done, - +static const struct pv_mmu_ops xen_mmu_ops __initdata = { .read_cr2 = xen_read_cr2, .write_cr2 = xen_write_cr2, @@ -1954,6 +1954,12 @@ const struct pv_mmu_ops xen_mmu_ops __initdata = { .set_fixmap = xen_set_fixmap, }; +void __init xen_init_mmu_ops(void) +{ + x86_init.paging.pagetable_setup_start = xen_pagetable_setup_start; + x86_init.paging.pagetable_setup_done = xen_pagetable_setup_done; + pv_mmu_ops = xen_mmu_ops; +} #ifdef CONFIG_XEN_DEBUG_FS diff --git a/arch/x86/xen/mmu.h b/arch/x86/xen/mmu.h index da7302624897..5fe6bc7f5ecf 100644 --- a/arch/x86/xen/mmu.h +++ b/arch/x86/xen/mmu.h @@ -59,5 +59,5 @@ void xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr, unsigned long xen_read_cr2_direct(void); -extern const struct pv_mmu_ops xen_mmu_ops; +extern void xen_init_mmu_ops(void); #endif /* _XEN_MMU_H */ diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h index 22494fd4c9b5..355fa6b99c9c 100644 --- a/arch/x86/xen/xen-ops.h +++ b/arch/x86/xen/xen-ops.h @@ -30,8 +30,6 @@ pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn); void xen_ident_map_ISA(void); void xen_reserve_top(void); -void xen_post_allocator_init(void); - char * __init xen_memory_setup(void); void __init xen_arch_setup(void); void __init xen_init_IRQ(void); diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c index 8848120d291b..19085ff0484a 100644 --- a/arch/xtensa/kernel/time.c +++ b/arch/xtensa/kernel/time.c @@ -59,9 +59,8 @@ static struct irqaction timer_irqaction = { void __init time_init(void) { - xtime.tv_nsec = 0; - xtime.tv_sec = read_persistent_clock(); - + /* FIXME: xtime&wall_to_monotonic are set in timekeeping_init. */ + read_persistent_clock(&xtime); set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); |