diff options
Diffstat (limited to 'arch')
926 files changed, 30632 insertions, 5849 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index e8d19c3cb91f..a7b57dd42c26 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -128,22 +128,6 @@ config UPROBES managed by the kernel and kept transparent to the probed application. ) -config HAVE_64BIT_ALIGNED_ACCESS - def_bool 64BIT && !HAVE_EFFICIENT_UNALIGNED_ACCESS - help - Some architectures require 64 bit accesses to be 64 bit - aligned, which also requires structs containing 64 bit values - to be 64 bit aligned too. This includes some 32 bit - architectures which can do 64 bit accesses, as well as 64 bit - architectures without unaligned access. - - This symbol should be selected by an architecture if 64 bit - accesses are required to be 64 bit aligned in this way even - though it is not a 64 bit architecture. - - See Documentation/unaligned-memory-access.txt for more - information on the topic of unaligned memory accesses. - config HAVE_EFFICIENT_UNALIGNED_ACCESS bool help @@ -585,6 +569,9 @@ config HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD config HAVE_ARCH_HUGE_VMAP bool +config ARCH_WANT_HUGE_PMD_SHARE + bool + config HAVE_ARCH_SOFT_DIRTY bool @@ -809,6 +796,9 @@ config ARCH_NO_COHERENT_DMA_MMAP config ARCH_NO_PREEMPT bool +config ARCH_SUPPORTS_RT + bool + config CPU_NO_EFFICIENT_FFS def_bool n diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h index ccf9d65166bb..af2c0063dc75 100644 --- a/arch/alpha/include/asm/io.h +++ b/arch/alpha/include/asm/io.h @@ -93,11 +93,6 @@ static inline void * phys_to_virt(unsigned long address) #define page_to_phys(page) page_to_pa(page) -static inline dma_addr_t __deprecated isa_page_to_bus(struct page *page) -{ - return page_to_phys(page); -} - /* Maximum PIO space address supported? */ #define IO_SPACE_LIMIT 0xffff diff --git a/arch/alpha/kernel/syscalls/syscall.tbl b/arch/alpha/kernel/syscalls/syscall.tbl index 1db9bbcfb84e..728fe028c02c 100644 --- a/arch/alpha/kernel/syscalls/syscall.tbl +++ b/arch/alpha/kernel/syscalls/syscall.tbl @@ -474,3 +474,4 @@ 542 common fsmount sys_fsmount 543 common fspick sys_fspick 544 common pidfd_open sys_pidfd_open +# 545 reserved for clone3 diff --git a/arch/arc/boot/dts/haps_hs.dts b/arch/arc/boot/dts/haps_hs.dts index 1ebfa046492b..44bc522fdec8 100644 --- a/arch/arc/boot/dts/haps_hs.dts +++ b/arch/arc/boot/dts/haps_hs.dts @@ -62,5 +62,35 @@ #interrupt-cells = <1>; interrupts = <20>; }; + + virtio0: virtio@f0100000 { + compatible = "virtio,mmio"; + reg = <0xf0100000 0x2000>; + interrupts = <31>; + }; + + virtio1: virtio@f0102000 { + compatible = "virtio,mmio"; + reg = <0xf0102000 0x2000>; + interrupts = <32>; + }; + + virtio2: virtio@f0104000 { + compatible = "virtio,mmio"; + reg = <0xf0104000 0x2000>; + interrupts = <33>; + }; + + virtio3: virtio@f0106000 { + compatible = "virtio,mmio"; + reg = <0xf0106000 0x2000>; + interrupts = <34>; + }; + + virtio4: virtio@f0108000 { + compatible = "virtio,mmio"; + reg = <0xf0108000 0x2000>; + interrupts = <35>; + }; }; }; diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts index 9a45cb093096..bfc7f5f5d6f2 100644 --- a/arch/arc/boot/dts/hsdk.dts +++ b/arch/arc/boot/dts/hsdk.dts @@ -8,6 +8,7 @@ */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/reset/snps,hsdk-reset.h> / { @@ -252,6 +253,19 @@ dma-coherent; }; + spi0: spi@20000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x20000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <16>; + num-cs = <2>; + reg-io-width = <4>; + clocks = <&input_clk>; + cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>, + <&creg_gpio 1 GPIO_ACTIVE_LOW>; + }; + creg_gpio: gpio@14b0 { compatible = "snps,creg-gpio-hsdk"; reg = <0x14b0 0x4>; diff --git a/arch/arc/configs/haps_hs_defconfig b/arch/arc/configs/haps_hs_defconfig index b117e6c16d41..436f2135bdc1 100644 --- a/arch/arc/configs/haps_hs_defconfig +++ b/arch/arc/configs/haps_hs_defconfig @@ -35,10 +35,12 @@ CONFIG_INET=y # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_BLK_DEV is not set +CONFIG_VIRTIO_BLK=y CONFIG_NETDEVICES=y +CONFIG_VIRTIO_NET=y # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_INTEL is not set @@ -68,6 +70,7 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y # CONFIG_HID is not set # CONFIG_USB_SUPPORT is not set +CONFIG_VIRTIO_MMIO=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y diff --git a/arch/arc/configs/hsdk_defconfig b/arch/arc/configs/hsdk_defconfig index c8fb5d60c53f..403125d9c9a3 100644 --- a/arch/arc/configs/hsdk_defconfig +++ b/arch/arc/configs/hsdk_defconfig @@ -46,6 +46,9 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y # CONFIG_HW_RANDOM is not set +CONFIG_SPI=y +CONFIG_SPI_DESIGNWARE=y +CONFIG_SPI_DW_MMIO=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_DWAPB=y @@ -66,6 +69,8 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_DW=y +CONFIG_DMADEVICES=y +CONFIG_DW_AXI_DMAC=y CONFIG_EXT3_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index 225e7df2d8ed..f5ae394ebe06 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -7,232 +7,251 @@ #include <asm/irqflags-arcv2.h> #include <asm/thread_info.h> /* For THREAD_SIZE */ +/* + * Interrupt/Exception stack layout (pt_regs) for ARCv2 + * (End of struct aligned to end of page [unless nested]) + * + * INTERRUPT EXCEPTION + * + * manual --------------------- manual + * | orig_r0 | + * | event/ECR | + * | bta | + * | user_r25 | + * | gp | + * | fp | + * | sp | + * | r12 | + * | r30 | + * | r58 | + * | r59 | + * hw autosave --------------------- + * optional | r0 | + * | r1 | + * ~ ~ + * | r9 | + * | r10 | + * | r11 | + * | blink | + * | lpe | + * | lps | + * | lpc | + * | ei base | + * | ldi base | + * | jli base | + * --------------------- + * hw autosave | pc / eret | + * mandatory | stat32 / erstatus | + * --------------------- + */ + /*------------------------------------------------------------------------*/ -.macro INTERRUPT_PROLOGUE called_from +.macro INTERRUPT_PROLOGUE - ; Before jumping to Interrupt Vector, hardware micro-ops did following: + ; (A) Before jumping to Interrupt Vector, hardware micro-ops did following: ; 1. SP auto-switched to kernel mode stack - ; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1, K:0) - ; 3. Auto saved: r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI, PC, STAT32 + ; 2. STATUS32.Z flag set if in U mode at time of interrupt (U:1,K:0) + ; 3. Auto save: (mandatory) Push PC and STAT32 on stack + ; hardware does even if CONFIG_ARC_IRQ_NO_AUTOSAVE + ; 4. Auto save: (optional) r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI ; - ; Now manually save: r12, sp, fp, gp, r25 + ; (B) Manually saved some regs: r12,r25,r30, sp,fp,gp, ACCL pair #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE -.ifnc \called_from, exception - st.as r9, [sp, -10] ; save r9 in it's final stack slot - sub sp, sp, 12 ; skip JLI, LDI, EI - - PUSH lp_count - PUSHAX lp_start - PUSHAX lp_end - PUSH blink - - PUSH r11 - PUSH r10 - - sub sp, sp, 4 ; skip r9 - - PUSH r8 - PUSH r7 - PUSH r6 - PUSH r5 - PUSH r4 - PUSH r3 - PUSH r2 - PUSH r1 - PUSH r0 -.endif -#endif + ; carve pt_regs on stack (case #3), PC/STAT32 already on stack + sub sp, sp, SZ_PT_REGS - 8 -#ifdef CONFIG_ARC_HAS_ACCL_REGS - PUSH r59 - PUSH r58 + __SAVE_REGFILE_HARD +#else + ; carve pt_regs on stack (case #4), which grew partially already + sub sp, sp, PT_r0 #endif - PUSH r30 - PUSH r12 + __SAVE_REGFILE_SOFT +.endm + +/*------------------------------------------------------------------------*/ +.macro EXCEPTION_PROLOGUE + + ; (A) Before jumping to Exception Vector, hardware micro-ops did following: + ; 1. SP auto-switched to kernel mode stack + ; 2. STATUS32.Z flag set if in U mode at time of exception (U:1,K:0) + ; + ; (B) Manually save the complete reg file below + + sub sp, sp, SZ_PT_REGS ; carve pt_regs + + ; _HARD saves r10 clobbered by _SOFT as scratch hence comes first + + __SAVE_REGFILE_HARD + __SAVE_REGFILE_SOFT + + st r0, [sp] ; orig_r0 + + lr r10, [eret] + lr r11, [erstatus] + ST2 r10, r11, PT_ret + + lr r10, [ecr] + lr r11, [erbta] + ST2 r10, r11, PT_event + + ; OUTPUT: r10 has ECR expected by EV_Trap +.endm + +/*------------------------------------------------------------------------ + * This macro saves the registers manually which would normally be autosaved + * by hardware on taken interrupts. It is used by + * - exception handlers (which don't have autosave) + * - interrupt autosave disabled due to CONFIG_ARC_IRQ_NO_AUTOSAVE + */ +.macro __SAVE_REGFILE_HARD + + ST2 r0, r1, PT_r0 + ST2 r2, r3, PT_r2 + ST2 r4, r5, PT_r4 + ST2 r6, r7, PT_r6 + ST2 r8, r9, PT_r8 + ST2 r10, r11, PT_r10 + + st blink, [sp, PT_blink] + + lr r10, [lp_end] + lr r11, [lp_start] + ST2 r10, r11, PT_lpe + + st lp_count, [sp, PT_lpc] + + ; skip JLI, LDI, EI for now +.endm + +/*------------------------------------------------------------------------ + * This macros saves a bunch of other registers which can't be autosaved for + * various reasons: + * - r12: the last caller saved scratch reg since hardware saves in pairs so r0-r11 + * - r30: free reg, used by gcc as scratch + * - ACCL/ACCH pair when they exist + */ +.macro __SAVE_REGFILE_SOFT + + ST2 gp, fp, PT_r26 ; gp (r26), fp (r27) + + st r12, [sp, PT_sp + 4] + st r30, [sp, PT_sp + 8] ; Saving pt_regs->sp correctly requires some extra work due to the way ; Auto stack switch works ; - U mode: retrieve it from AUX_USER_SP ; - K mode: add the offset from current SP where H/w starts auto push ; - ; Utilize the fact that Z bit is set if Intr taken in U mode - mov.nz r9, sp - add.nz r9, r9, SZ_PT_REGS - PT_sp - 4 - bnz 1f + ; 1. Utilize the fact that Z bit is set if Intr taken in U mode + ; 2. Upon entry SP is always saved (for any inspection, unwinding etc), + ; but on return, restored only if U mode - lr r9, [AUX_USER_SP] -1: - PUSH r9 ; SP + lr r10, [AUX_USER_SP] ; U mode SP + + ; ISA requires ADD.nz to have same dest and src reg operands + mov.nz r10, sp + add.nz r10, r10, SZ_PT_REGS ; K mode SP - PUSH fp - PUSH gp + st r10, [sp, PT_sp] ; SP (pt_regs->sp) #ifdef CONFIG_ARC_CURR_IN_REG - PUSH r25 ; user_r25 + st r25, [sp, PT_user_r25] GET_CURR_TASK_ON_CPU r25 -#else - sub sp, sp, 4 #endif -.ifnc \called_from, exception - sub sp, sp, 12 ; BTA/ECR/orig_r0 placeholder per pt_regs -.endif +#ifdef CONFIG_ARC_HAS_ACCL_REGS + ST2 r58, r59, PT_sp + 12 +#endif .endm /*------------------------------------------------------------------------*/ -.macro INTERRUPT_EPILOGUE called_from +.macro __RESTORE_REGFILE_SOFT -.ifnc \called_from, exception - add sp, sp, 12 ; skip BTA/ECR/orig_r0 placeholderss -.endif + LD2 gp, fp, PT_r26 ; gp (r26), fp (r27) -#ifdef CONFIG_ARC_CURR_IN_REG - POP r25 -#else - add sp, sp, 4 -#endif + ld r12, [sp, PT_sp + 4] + ld r30, [sp, PT_sp + 8] - POP gp - POP fp - - ; Don't touch AUX_USER_SP if returning to K mode (Z bit set) - ; (Z bit set on K mode is inverse of INTERRUPT_PROLOGUE) - add.z sp, sp, 4 + ; Restore SP (into AUX_USER_SP) only if returning to U mode + ; - for K mode, it will be implicitly restored as stack is unwound + ; - Z flag set on K is inverse of what hardware does on interrupt entry + ; but that doesn't really matter bz 1f - POPAX AUX_USER_SP + ld r10, [sp, PT_sp] ; SP (pt_regs->sp) + sr r10, [AUX_USER_SP] 1: - POP r12 - POP r30 -#ifdef CONFIG_ARC_HAS_ACCL_REGS - POP r58 - POP r59 +#ifdef CONFIG_ARC_CURR_IN_REG + ld r25, [sp, PT_user_r25] #endif -#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE -.ifnc \called_from, exception - POP r0 - POP r1 - POP r2 - POP r3 - POP r4 - POP r5 - POP r6 - POP r7 - POP r8 - POP r9 - POP r10 - POP r11 - - POP blink - POPAX lp_end - POPAX lp_start - - POP r9 - mov lp_count, r9 - - add sp, sp, 12 ; skip JLI, LDI, EI - ld.as r9, [sp, -10] ; reload r9 which got clobbered -.endif +#ifdef CONFIG_ARC_HAS_ACCL_REGS + LD2 r58, r59, PT_sp + 12 #endif +.endm +/*------------------------------------------------------------------------*/ +.macro __RESTORE_REGFILE_HARD + + ld blink, [sp, PT_blink] + + LD2 r10, r11, PT_lpe + sr r10, [lp_end] + sr r11, [lp_start] + + ld r10, [sp, PT_lpc] ; lp_count can't be target of LD + mov lp_count, r10 + + LD2 r0, r1, PT_r0 + LD2 r2, r3, PT_r2 + LD2 r4, r5, PT_r4 + LD2 r6, r7, PT_r6 + LD2 r8, r9, PT_r8 + LD2 r10, r11, PT_r10 .endm + /*------------------------------------------------------------------------*/ -.macro EXCEPTION_PROLOGUE +.macro INTERRUPT_EPILOGUE - ; Before jumping to Exception Vector, hardware micro-ops did following: - ; 1. SP auto-switched to kernel mode stack - ; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1,K:0) - ; - ; Now manually save the complete reg file - - PUSH r9 ; freeup a register: slot of erstatus - - PUSHAX eret - sub sp, sp, 12 ; skip JLI, LDI, EI - PUSH lp_count - PUSHAX lp_start - PUSHAX lp_end - PUSH blink - - PUSH r11 - PUSH r10 - - ld.as r9, [sp, 10] ; load stashed r9 (status32 stack slot) - lr r10, [erstatus] - st.as r10, [sp, 10] ; save status32 at it's right stack slot - - PUSH r9 - PUSH r8 - PUSH r7 - PUSH r6 - PUSH r5 - PUSH r4 - PUSH r3 - PUSH r2 - PUSH r1 - PUSH r0 - - ; -- for interrupts, regs above are auto-saved by h/w in that order -- - ; Now do what ISR prologue does (manually save r12, sp, fp, gp, r25) - ; - ; Set Z flag if this was from U mode (expected by INTERRUPT_PROLOGUE) - ; Although H/w exception micro-ops do set Z flag for U mode (just like - ; for interrupts), it could get clobbered in case we soft land here from - ; a TLB Miss exception handler (tlbex.S) + ; INPUT: r0 has STAT32 of calling context + ; INPUT: Z flag set if returning to K mode - and r10, r10, STATUS_U_MASK - xor.f 0, r10, STATUS_U_MASK + ; _SOFT clobbers r10 restored by _HARD hence the order - INTERRUPT_PROLOGUE exception + __RESTORE_REGFILE_SOFT - PUSHAX erbta - PUSHAX ecr ; r9 contains ECR, expected by EV_Trap +#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE + __RESTORE_REGFILE_HARD + add sp, sp, SZ_PT_REGS - 8 +#else + add sp, sp, PT_r0 +#endif - PUSH r0 ; orig_r0 .endm /*------------------------------------------------------------------------*/ .macro EXCEPTION_EPILOGUE - ; Assumes r0 has PT_status32 - btst r0, STATUS_U_BIT ; Z flag set if K, used in INTERRUPT_EPILOGUE - - add sp, sp, 8 ; orig_r0/ECR don't need restoring - POPAX erbta - - INTERRUPT_EPILOGUE exception + ; INPUT: r0 has STAT32 of calling context - POP r0 - POP r1 - POP r2 - POP r3 - POP r4 - POP r5 - POP r6 - POP r7 - POP r8 - POP r9 - POP r10 - POP r11 + btst r0, STATUS_U_BIT ; Z flag set if K, used in restoring SP - POP blink - POPAX lp_end - POPAX lp_start + ld r10, [sp, PT_event + 4] + sr r10, [erbta] - POP r9 - mov lp_count, r9 + LD2 r10, r11, PT_ret + sr r10, [eret] + sr r11, [erstatus] - add sp, sp, 12 ; skip JLI, LDI, EI - POPAX eret - POPAX erstatus + __RESTORE_REGFILE_SOFT + __RESTORE_REGFILE_HARD - ld.as r9, [sp, -12] ; reload r9 which got clobbered + add sp, sp, SZ_PT_REGS .endm .macro FAKE_RET_FROM_EXCPN diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h index 66ba1bf21d28..66a292335ee6 100644 --- a/arch/arc/include/asm/entry-compact.h +++ b/arch/arc/include/asm/entry-compact.h @@ -195,8 +195,8 @@ PUSHAX CTOP_AUX_EFLAGS #endif - lr r9, [ecr] - st r9, [sp, PT_event] /* EV_Trap expects r9 to have ECR */ + lr r10, [ecr] + st r10, [sp, PT_event] /* EV_Trap expects r10 to have ECR */ .endm /*-------------------------------------------------------------- diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h index 54f5ec5c1759..a0eeb9f8f0a9 100644 --- a/arch/arc/include/asm/linkage.h +++ b/arch/arc/include/asm/linkage.h @@ -10,6 +10,24 @@ #ifdef __ASSEMBLY__ +.macro ST2 e, o, off +#ifdef CONFIG_ARC_HAS_LL64 + std \e, [sp, \off] +#else + st \e, [sp, \off] + st \o, [sp, \off+4] +#endif +.endm + +.macro LD2 e, o, off +#ifdef CONFIG_ARC_HAS_LL64 + ldd \e, [sp, \off] +#else + ld \e, [sp, \off] + ld \o, [sp, \off+4] +#endif +.endm + #define ASM_NL ` /* use '`' to mark new line in macro */ /* annotation for data we want in DCCM - if enabled in .config */ diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index da446180f17b..1d87c18a2976 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -32,7 +32,7 @@ #ifndef _ASM_ARC_PGTABLE_H #define _ASM_ARC_PGTABLE_H -#include <linux/const.h> +#include <linux/bits.h> #define __ARCH_USE_5LEVEL_HACK #include <asm-generic/pgtable-nopmd.h> #include <asm/page.h> @@ -215,11 +215,11 @@ #define BITS_FOR_PTE (PGDIR_SHIFT - PAGE_SHIFT) #define BITS_FOR_PGD (32 - PGDIR_SHIFT) -#define PGDIR_SIZE _BITUL(PGDIR_SHIFT) /* vaddr span, not PDG sz */ +#define PGDIR_SIZE BIT(PGDIR_SHIFT) /* vaddr span, not PDG sz */ #define PGDIR_MASK (~(PGDIR_SIZE-1)) -#define PTRS_PER_PTE _BITUL(BITS_FOR_PTE) -#define PTRS_PER_PGD _BITUL(BITS_FOR_PGD) +#define PTRS_PER_PTE BIT(BITS_FOR_PTE) +#define PTRS_PER_PGD BIT(BITS_FOR_PGD) /* * Number of entries a user land program use. diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c index dba116535005..1f621e416521 100644 --- a/arch/arc/kernel/asm-offsets.c +++ b/arch/arc/kernel/asm-offsets.c @@ -55,7 +55,14 @@ int main(void) DEFINE(PT_r5, offsetof(struct pt_regs, r5)); DEFINE(PT_r6, offsetof(struct pt_regs, r6)); DEFINE(PT_r7, offsetof(struct pt_regs, r7)); + DEFINE(PT_r8, offsetof(struct pt_regs, r8)); + DEFINE(PT_r10, offsetof(struct pt_regs, r10)); + DEFINE(PT_r26, offsetof(struct pt_regs, r26)); DEFINE(PT_ret, offsetof(struct pt_regs, ret)); + DEFINE(PT_blink, offsetof(struct pt_regs, blink)); + DEFINE(PT_lpe, offsetof(struct pt_regs, lp_end)); + DEFINE(PT_lpc, offsetof(struct pt_regs, lp_count)); + DEFINE(PT_user_r25, offsetof(struct pt_regs, user_r25)); DEFINE(SZ_CALLEE_REGS, sizeof(struct callee_regs)); DEFINE(SZ_PT_REGS, sizeof(struct pt_regs)); diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S index 14254b866fdc..12d5f12d10d2 100644 --- a/arch/arc/kernel/entry-arcv2.S +++ b/arch/arc/kernel/entry-arcv2.S @@ -67,7 +67,7 @@ reserved: ENTRY(handle_interrupt) - INTERRUPT_PROLOGUE irq + INTERRUPT_PROLOGUE # irq control APIs local_irq_save/restore/disable/enable fiddle with # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio) @@ -79,7 +79,7 @@ ENTRY(handle_interrupt) # # Note this disable is only for consistent book-keeping as further interrupts # will be disabled anyways even w/o this. Hardware tracks active interrupts - # seperately in AUX_IRQ_ACTIVE.active and will not take new interrupts + # seperately in AUX_IRQ_ACT.active and will not take new interrupts # unless this one returns (or higher prio becomes pending in 2-prio scheme) IRQ_DISABLE @@ -200,17 +200,18 @@ restore_regs: ld r0, [sp, PT_status32] ; U/K mode at time of entry lr r10, [AUX_IRQ_ACT] - bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE + bmsk r11, r10, 15 ; extract AUX_IRQ_ACT.active breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception ;####### Return from Intr ####### +.Lisr_ret: + debug_marker_l1: ; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot btst r0, STATUS_DE_BIT ; Z flag set if bit clear bnz .Lintr_ret_to_delay_slot ; branch if STATUS_DE_BIT set -.Lisr_ret_fast_path: ; Handle special case #1: (Entry via Exception, Return via IRQ) ; ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig @@ -223,7 +224,7 @@ debug_marker_l1: bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U sr r11, [AUX_IRQ_ACT] - INTERRUPT_EPILOGUE irq + INTERRUPT_EPILOGUE rtie ;####### Return from Exception / pure kernel mode ####### @@ -244,8 +245,8 @@ debug_marker_syscall: ; ; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround ; -; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline -; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly +; Solution is to drop out of interrupt context into pure kernel mode +; and return from pure kernel mode which does right things for delay slot .Lintr_ret_to_delay_slot: debug_marker_ds: @@ -254,48 +255,9 @@ debug_marker_ds: add r2, r2, 1 st r2, [@intr_to_DE_cnt] - ld r2, [sp, PT_ret] - ld r3, [sp, PT_status32] - - ; STAT32 for Int return created from scratch - ; (No delay dlot, disable Further intr in trampoline) - - bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK - st r0, [sp, PT_status32] - - mov r1, .Lintr_ret_to_delay_slot_2 - st r1, [sp, PT_ret] - - ; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots - st r2, [sp, 0] - st r3, [sp, 4] - - b .Lisr_ret_fast_path - -.Lintr_ret_to_delay_slot_2: - ; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP - sub sp, sp, SZ_PT_REGS - st r9, [sp, -4] - - ld r9, [sp, 0] - sr r9, [eret] - - ld r9, [sp, 4] - sr r9, [erstatus] - - ; restore AUX_USER_SP if returning to U mode - bbit0 r9, STATUS_U_BIT, 1f - ld r9, [sp, PT_sp] - sr r9, [AUX_USER_SP] - -1: - ld r9, [sp, 8] - sr r9, [erbta] - - ld r9, [sp, -4] - add sp, sp, SZ_PT_REGS - - ; return from pure kernel mode to delay slot - rtie + ; drop out of interrupt context (clear AUX_IRQ_ACT.active) + bmskn r11, r10, 15 + sr r11, [AUX_IRQ_ACT] + b .Lexcept_ret END(ret_from_exception) diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S index 7fe59880c16b..5cb0cd7e4eab 100644 --- a/arch/arc/kernel/entry-compact.S +++ b/arch/arc/kernel/entry-compact.S @@ -256,7 +256,7 @@ ENTRY(EV_TLBProtV) EXCEPTION_PROLOGUE - mov r2, r9 ; ECR set into r9 already + mov r2, r10 ; ECR set into r10 already lr r0, [efa] ; Faulting Data address (not part of pt_regs saved above) ; Exception auto-disables further Intr/exceptions. diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S index a2bfacbcfce1..72be01270e24 100644 --- a/arch/arc/kernel/entry.S +++ b/arch/arc/kernel/entry.S @@ -232,8 +232,8 @@ ENTRY(EV_Trap) EXCEPTION_PROLOGUE ;============ TRAP 1 :breakpoints - ; Check ECR for trap with arg (PROLOGUE ensures r9 has ECR) - bmsk.f 0, r9, 7 + ; Check ECR for trap with arg (PROLOGUE ensures r10 has ECR) + bmsk.f 0, r10, 7 bnz trap_with_param ;============ TRAP (no param): syscall top level diff --git a/arch/arc/kernel/unwind.c b/arch/arc/kernel/unwind.c index 182ce67dfe10..c2663fce7f6c 100644 --- a/arch/arc/kernel/unwind.c +++ b/arch/arc/kernel/unwind.c @@ -181,11 +181,6 @@ static void *__init unw_hdr_alloc_early(unsigned long sz) return memblock_alloc_from(sz, sizeof(unsigned int), MAX_DMA_ADDRESS); } -static void *unw_hdr_alloc(unsigned long sz) -{ - return kmalloc(sz, GFP_KERNEL); -} - static void init_unwind_table(struct unwind_table *table, const char *name, const void *core_start, unsigned long core_size, const void *init_start, unsigned long init_size, @@ -366,6 +361,10 @@ ret_err: } #ifdef CONFIG_MODULES +static void *unw_hdr_alloc(unsigned long sz) +{ + return kmalloc(sz, GFP_KERNEL); +} static struct unwind_table *last_table; diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c index 81e84426fe21..3861543b66a0 100644 --- a/arch/arc/mm/fault.c +++ b/arch/arc/mm/fault.c @@ -63,24 +63,19 @@ void do_page_fault(unsigned long address, struct pt_regs *regs) struct vm_area_struct *vma = NULL; struct task_struct *tsk = current; struct mm_struct *mm = tsk->mm; - int si_code = SEGV_MAPERR; - int ret; - vm_fault_t fault; - int write = regs->ecr_cause & ECR_C_PROTV_STORE; /* ST/EX */ - unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; + int sig, si_code = SEGV_MAPERR; + unsigned int write = 0, exec = 0, mask; + vm_fault_t fault = VM_FAULT_SIGSEGV; /* handle_mm_fault() output */ + unsigned int flags; /* handle_mm_fault() input */ /* - * We fault-in kernel-space virtual memory on-demand. The - * 'reference' page table is init_mm.pgd. - * * NOTE! We MUST NOT take any locks for this case. We may * be in an interrupt or a critical region, and should * only copy the information from the master page table, * nothing more. */ if (address >= VMALLOC_START && !user_mode(regs)) { - ret = handle_kernel_vaddr_fault(address); - if (unlikely(ret)) + if (unlikely(handle_kernel_vaddr_fault(address))) goto no_context; else return; @@ -93,143 +88,117 @@ void do_page_fault(unsigned long address, struct pt_regs *regs) if (faulthandler_disabled() || !mm) goto no_context; + if (regs->ecr_cause & ECR_C_PROTV_STORE) /* ST/EX */ + write = 1; + else if ((regs->ecr_vec == ECR_V_PROTV) && + (regs->ecr_cause == ECR_C_PROTV_INST_FETCH)) + exec = 1; + + flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; if (user_mode(regs)) flags |= FAULT_FLAG_USER; + if (write) + flags |= FAULT_FLAG_WRITE; + retry: down_read(&mm->mmap_sem); + vma = find_vma(mm, address); if (!vma) goto bad_area; - if (vma->vm_start <= address) - goto good_area; - if (!(vma->vm_flags & VM_GROWSDOWN)) - goto bad_area; - if (expand_stack(vma, address)) - goto bad_area; + if (unlikely(address < vma->vm_start)) { + if (!(vma->vm_flags & VM_GROWSDOWN) || expand_stack(vma, address)) + goto bad_area; + } /* - * Ok, we have a good vm_area for this memory access, so - * we can handle it.. + * vm_area is good, now check permissions for this memory access */ -good_area: - si_code = SEGV_ACCERR; - - /* Handle protection violation, execute on heap or stack */ - - if ((regs->ecr_vec == ECR_V_PROTV) && - (regs->ecr_cause == ECR_C_PROTV_INST_FETCH)) + mask = VM_READ; + if (write) + mask = VM_WRITE; + if (exec) + mask = VM_EXEC; + + if (!(vma->vm_flags & mask)) { + si_code = SEGV_ACCERR; goto bad_area; - - if (write) { - if (!(vma->vm_flags & VM_WRITE)) - goto bad_area; - flags |= FAULT_FLAG_WRITE; - } else { - if (!(vma->vm_flags & (VM_READ | VM_EXEC))) - goto bad_area; } - /* - * If for any reason at all we couldn't handle the fault, - * make sure we exit gracefully rather than endlessly redo - * the fault. - */ fault = handle_mm_fault(vma, address, flags); - if (fatal_signal_pending(current)) { + /* + * Fault retry nuances + */ + if (unlikely(fault & VM_FAULT_RETRY)) { /* - * if fault retry, mmap_sem already relinquished by core mm - * so OK to return to user mode (with signal handled first) + * If fault needs to be retried, handle any pending signals + * first (by returning to user mode). + * mmap_sem already relinquished by core mm for RETRY case */ - if (fault & VM_FAULT_RETRY) { + if (fatal_signal_pending(current)) { if (!user_mode(regs)) goto no_context; return; } - } - - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address); - - if (likely(!(fault & VM_FAULT_ERROR))) { + /* + * retry state machine + */ if (flags & FAULT_FLAG_ALLOW_RETRY) { - /* To avoid updating stats twice for retry case */ - if (fault & VM_FAULT_MAJOR) { - tsk->maj_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, - regs, address); - } else { - tsk->min_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, - regs, address); - } - - if (fault & VM_FAULT_RETRY) { - flags &= ~FAULT_FLAG_ALLOW_RETRY; - flags |= FAULT_FLAG_TRIED; - goto retry; - } + flags &= ~FAULT_FLAG_ALLOW_RETRY; + flags |= FAULT_FLAG_TRIED; + goto retry; } - - /* Fault Handled Gracefully */ - up_read(&mm->mmap_sem); - return; } - if (fault & VM_FAULT_OOM) - goto out_of_memory; - else if (fault & VM_FAULT_SIGSEGV) - goto bad_area; - else if (fault & VM_FAULT_SIGBUS) - goto do_sigbus; - - /* no man's land */ - BUG(); +bad_area: + up_read(&mm->mmap_sem); /* - * Something tried to access memory that isn't in our memory map.. - * Fix it, but check if it's kernel or user first.. + * Major/minor page fault accounting + * (in case of retry we only land here once) */ -bad_area: - up_read(&mm->mmap_sem); + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address); - /* User mode accesses just cause a SIGSEGV */ - if (user_mode(regs)) { - tsk->thread.fault_address = address; - force_sig_fault(SIGSEGV, si_code, (void __user *)address); - return; - } + if (likely(!(fault & VM_FAULT_ERROR))) { + if (fault & VM_FAULT_MAJOR) { + tsk->maj_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, + regs, address); + } else { + tsk->min_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, + regs, address); + } -no_context: - /* Are we prepared to handle this kernel fault? - * - * (The kernel has valid exception-points in the source - * when it accesses user-memory. When it fails in one - * of those points, we find it in a table and do a jump - * to some fixup code that loads an appropriate error - * code) - */ - if (fixup_exception(regs)) + /* Normal return path: fault Handled Gracefully */ return; + } - die("Oops", regs, address); - -out_of_memory: - up_read(&mm->mmap_sem); + if (!user_mode(regs)) + goto no_context; - if (user_mode(regs)) { + if (fault & VM_FAULT_OOM) { pagefault_out_of_memory(); return; } - goto no_context; + if (fault & VM_FAULT_SIGBUS) { + sig = SIGBUS; + si_code = BUS_ADRERR; + } + else { + sig = SIGSEGV; + } -do_sigbus: - up_read(&mm->mmap_sem); + tsk->thread.fault_address = address; + force_sig_fault(sig, si_code, (void __user *)address); + return; - if (!user_mode(regs)) - goto no_context; +no_context: + if (fixup_exception(regs)) + return; - tsk->thread.fault_address = address; - force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)address); + die("Oops", regs, address); } diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 471a97bf492d..c55d95dd2f39 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -393,6 +393,17 @@ EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation ;-------- Common routine to call Linux Page Fault Handler ----------- do_slow_path_pf: +#ifdef CONFIG_ISA_ARCV2 + ; Set Z flag if exception in U mode. Hardware micro-ops do this on any + ; taken interrupt/exception, and thus is already the case at the entry + ; above, but ensuing code would have already clobbered. + ; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set + + lr r2, [erstatus] + and r2, r2, STATUS_U_MASK + bxor.f 0, r2, STATUS_U_BIT +#endif + ; Restore the 4-scratch regs saved by fast path miss handler TLBMISS_RESTORE_REGS diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h index 309a994f64f0..a4a61531c7fb 100644 --- a/arch/arc/plat-eznps/include/plat/ctop.h +++ b/arch/arc/plat-eznps/include/plat/ctop.h @@ -10,6 +10,7 @@ #error "Incorrect ctop.h include" #endif +#include <linux/bits.h> #include <linux/types.h> #include <soc/nps/common.h> @@ -51,19 +52,19 @@ #define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06 /* Do not use D$ for address in 2G-3G */ -#define HW_COMPLY_KRN_NOT_D_CACHED _BITUL(28) +#define HW_COMPLY_KRN_NOT_D_CACHED BIT(28) #define NPS_MSU_EN_CFG 0x80 #define NPS_CRG_BLKID 0x480 -#define NPS_CRG_SYNC_BIT _BITUL(0) +#define NPS_CRG_SYNC_BIT BIT(0) #define NPS_GIM_BLKID 0x5C0 /* GIM registers and fields*/ -#define NPS_GIM_UART_LINE _BITUL(7) -#define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE _BITUL(10) -#define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE _BITUL(11) -#define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE _BITUL(25) -#define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE _BITUL(26) +#define NPS_GIM_UART_LINE BIT(7) +#define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE BIT(10) +#define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE BIT(11) +#define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE BIT(25) +#define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE BIT(26) #ifndef __ASSEMBLY__ /* Functional registers definition */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2bf1ce39a96d..33b00579beff 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -377,15 +377,6 @@ config ARCH_FOOTBRIDGE Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. -config ARCH_NETX - bool "Hilscher NetX based" - select ARM_VIC - select CLKSRC_MMIO - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - help - This enables support for systems based on the Hilscher NetX Soc - config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU @@ -531,7 +522,7 @@ config ARCH_RPC select ARCH_ACORN select ARCH_MAY_HAVE_PC_FDC select ARCH_SPARSEMEM_ENABLE - select ARCH_USES_GETTIMEOFFSET + select ARM_HAS_SG_CHAIN select CPU_SA110 select FIQ select HAVE_IDE @@ -552,6 +543,7 @@ config ARCH_SA1100 select CLKSRC_MMIO select CLKSRC_PXA select TIMER_OF if OF + select COMMON_CLK select CPU_FREQ select CPU_SA1100 select GENERIC_CLOCKEVENTS @@ -770,8 +762,6 @@ source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/mach-mxs/Kconfig" -source "arch/arm/mach-netx/Kconfig" - source "arch/arm/mach-nomadik/Kconfig" source "arch/arm/mach-npcm/Kconfig" @@ -1297,7 +1287,7 @@ config SMP will run faster if you say N here. See also <file:Documentation/x86/i386/IO-APIC.rst>, - <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at + <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at <http://tldp.org/HOWTO/SMP-HOWTO.html>. If you don't know what to do here, say N. @@ -2036,7 +2026,7 @@ config CRASH_DUMP kdump/kexec. The crash dump kernel must be compiled to a memory address not used by the main kernel - For more details see Documentation/kdump/kdump.rst + For more details see Documentation/admin-guide/kdump/kdump.rst config AUTO_ZRELADDR bool "Auto calculation of the decompressed kernel image address" @@ -2142,7 +2132,7 @@ config VFP Say Y to include VFP support code in the kernel. This is needed if your hardware includes a VFP unit. - Please see <file:Documentation/arm/VFP/release-notes.txt> for + Please see <file:Documentation/arm/vfp/release-notes.rst> for release notes and additional status information. Say N if your target does not have VFP hardware. diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 9a8862fee738..c929bea9a9ff 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -638,13 +638,6 @@ choice Say Y here if you want kernel low-level debugging support for Mediatek mt8135 based platforms on UART3. - config DEBUG_NETX_UART - bool "Kernel low-level debugging messages via NetX UART" - depends on ARCH_NETX - help - Say Y here if you want kernel low-level debugging support - on Hilscher NetX based platforms. - config DEBUG_NOMADIK_UART bool "Kernel low-level debugging messages via NOMADIK UART" depends on ARCH_NOMADIK diff --git a/arch/arm/Makefile b/arch/arm/Makefile index f863c6935d0e..c3624ca6c0bc 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -191,7 +191,6 @@ machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs -machine-$(CONFIG_ARCH_NETX) += netx machine-$(CONFIG_ARCH_NOMADIK) += nomadik machine-$(CONFIG_ARCH_NPCM) += npcm machine-$(CONFIG_ARCH_NSPIRE) += nspire diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index dab2914fa293..9159fa2cea90 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -586,6 +586,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ imx7d-mba7.dtb \ + imx7d-meerkat96.dtb \ imx7d-nitrogen7.dtb \ imx7d-pico-hobbit.dtb \ imx7d-pico-pi.dtb \ @@ -602,6 +603,7 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \ dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ + ls1021a-tsn.dtb \ ls1021a-twr.dtb dtb-$(CONFIG_SOC_VF610) += \ vf500-colibri-eval-v3.dtb \ @@ -748,6 +750,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-pepper.dtb \ am335x-phycore-rdk.dtb \ am335x-pocketbeagle.dtb \ + am335x-regor-rdk.dtb \ am335x-sancloud-bbe.dtb \ am335x-shc.dtb \ am335x-sbc-t335.dtb \ @@ -975,6 +978,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ + stm32mp157a-avenger96.dtb \ stm32mp157a-dk1.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ @@ -1268,10 +1272,16 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ + aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-intel-s2600wf.dtb \ + aspeed-bmc-inspur-fp5280g2.dtb \ + aspeed-bmc-lenovo-hr630.dtb \ + aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-palmetto.dtb \ aspeed-bmc-opp-romulus.dtb \ + aspeed-bmc-opp-swift.dtb \ + aspeed-bmc-opp-vesnin.dtb \ aspeed-bmc-opp-witherspoon.dtb \ aspeed-bmc-opp-zaius.dtb \ aspeed-bmc-portwell-neptune.dtb \ diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index 49e46baf9542..386d5f89978e 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -30,6 +30,12 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ >; }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ + >; + }; }; &uart1 { @@ -65,7 +71,13 @@ }; &cpsw_emac1 { - phy-mode = "rgmii-txid"; + phy-mode = "rgmii-id"; dual_emac_res_vlan = <2>; phy-handle = <&phy1>; }; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts index 9e88bc2f6465..b0df7256db13 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -51,6 +51,12 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ >; }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ + >; + }; }; &uart1 { @@ -107,7 +113,13 @@ }; &cpsw_emac1 { - phy-mode = "rgmii-txid"; + phy-mode = "rgmii-id"; dual_emac_res_vlan = <2>; phy-handle = <&phy1>; }; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index 28aa00422951..d6aa46e8700e 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -60,6 +60,11 @@ >; }; + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ + >; + }; }; &uart1 { @@ -125,7 +130,7 @@ }; &cpsw_emac1 { - phy-mode = "rgmii-txid"; + phy-mode = "rgmii-id"; dual_emac_res_vlan = <2>; phy-handle = <&phy1>; }; @@ -136,3 +141,9 @@ status = "okay"; }; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi index d774bf76720c..9bfa032bcada 100644 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi @@ -36,15 +36,13 @@ pinctrl-names = "default"; pinctrl-0 = <&user_leds_pins>; - green { - label = "green:user"; + user-led0 { gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "gpio"; default-state = "on"; }; - yellow { - label = "yellow:user"; + user-led1 { gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; linux,default-trigger = "gpio"; default-state = "on"; @@ -135,22 +133,6 @@ &davinci_mdio { phy1: ethernet-phy@2 { reg = <2>; - - /* Register 260 (104h) – RGMII Clock and Control Pad Skew */ - rxc-skew-ps = <1400>; - rxdv-skew-ps = <0>; - txc-skew-ps = <1400>; - txen-skew-ps = <0>; - /* Register 261 (105h) – RGMII RX Data Pad Skew */ - rxd3-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd0-skew-ps = <0>; - /* Register 262 (106h) – RGMII TX Data Pad Skew */ - txd3-skew-ps = <0>; - txd2-skew-ps = <0>; - txd1-skew-ps = <0>; - txd0-skew-ps = <0>; }; }; diff --git a/arch/arm/boot/dts/am335x-phycore-rdk.dts b/arch/arm/boot/dts/am335x-phycore-rdk.dts index 672daf9d36be..43907d03e675 100644 --- a/arch/arm/boot/dts/am335x-phycore-rdk.dts +++ b/arch/arm/boot/dts/am335x-phycore-rdk.dts @@ -10,6 +10,10 @@ #include "am335x-pcm-953.dtsi" /* SoM */ +&gpmc { + status = "okay"; +}; + &i2c_eeprom { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index ee6b1cb27ce5..3d0672b53d77 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -27,17 +27,13 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - regulators { - compatible = "simple-bus"; - - vcc5v: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; + vcc5v: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; }; }; @@ -50,6 +46,33 @@ status = "okay"; }; +/* EMMC */ +&am33xx_pinmux { + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + vmmc-supply = <&vmmc_reg>; + bus-width = <8>; + ti,non-removable; + status = "disabled"; +}; + /* Ethernet */ &am33xx_pinmux { ethernet0_pins: pinmux_ethernet0 { @@ -164,7 +187,7 @@ }; &gpmc { - status = "okay"; + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins>; ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ diff --git a/arch/arm/boot/dts/am335x-regor-rdk.dts b/arch/arm/boot/dts/am335x-regor-rdk.dts new file mode 100644 index 000000000000..66a1360b83d5 --- /dev/null +++ b/arch/arm/boot/dts/am335x-regor-rdk.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + * + */ + +/dts-v1/; + +#include "am335x-phycore-som.dtsi" +#include "am335x-regor.dtsi" + +/* SoM */ +&gpmc { + status = "okay"; +}; + +&i2c_eeprom { + status = "okay"; +}; + +&serial_flash { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am335x-regor.dtsi b/arch/arm/boot/dts/am335x-regor.dtsi new file mode 100644 index 000000000000..5aff02a95766 --- /dev/null +++ b/arch/arm/boot/dts/am335x-regor.dtsi @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + * + */ + +/ { + model = "Phytec AM335x phyBOARD-REGOR"; + compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; + + vcc3v3: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* User IO */ + user_leds: user_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_pins>; + + run_stop-led { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + error-led { + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + }; +}; + +/* User Leds */ +&am33xx_pinmux { + user_leds_pins: pinmux_user_leds { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ + >; + }; +}; + +/* CAN Busses */ +&am33xx_pinmux { + dcan1_pins: pinmux_dcan1 { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet1_pins: pinmux_ethernet1 { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ + >; + }; +}; + +&cpsw_emac1 { + phy-handle = <&phy1>; + phy-mode = "mii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mac { + slaves = <2>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_pins ðernet1_pins>; + dual_emac = <1>; +}; + +/* GPIOs */ +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&user_gpios_pins>; + + user_gpios_pins: pinmux_user_gpios { + pinctrl-single,pins = < + /* DIGIN 1-4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */ + /* DIGOUT 1-4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */ + >; + }; +}; + +/* MMC */ +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1 { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* RTC */ +&i2c_rtc { + status = "okay"; +}; + +/* UARTs */ +&am33xx_pinmux { + uart0_pins: pinmux_uart0 { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart2_pins: pinmux_uart2 { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +/* RS485 - UART1 */ +&am33xx_pinmux { + uart1_rs485_pins: pinmux_uart1_rs485_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_rs485_pins>; + status = "okay"; + linux,rs485-enabled-at-boot-time; +}; + +/* USB */ +&cppi41dma { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am335x-wega-rdk.dts b/arch/arm/boot/dts/am335x-wega-rdk.dts index 2e04f6df8257..866b5f0cbfbc 100644 --- a/arch/arm/boot/dts/am335x-wega-rdk.dts +++ b/arch/arm/boot/dts/am335x-wega-rdk.dts @@ -10,6 +10,10 @@ #include "am335x-wega.dtsi" /* SoM */ +&gpmc { + status = "okay"; +}; + &i2c_eeprom { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi index 67bde56f89fd..61fc4cd2d164 100644 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ b/arch/arm/boot/dts/am335x-wega.dtsi @@ -12,16 +12,12 @@ compatible = "ti,da830-evm-audio"; }; - regulators { - compatible = "simple-bus"; - - vcc3v3: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; + vcc3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; }; }; diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index 610506723ea5..fe0207b88053 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -119,6 +119,9 @@ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x40000000 0x04000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; flash1@44000000 { @@ -126,6 +129,9 @@ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x44000000 0x04000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; /* SMSC LAN91C111 ethernet with PHY and EEPROM */ diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index cbbb8878daa3..2625ce66f8e7 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -120,12 +120,18 @@ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x30000000 0x4000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; fpga_flash@38000000 { compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x38000000 0x800000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; /* diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 2015619ca22c..c69cf7ddbe61 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -235,6 +235,9 @@ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x40000000 0x04000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; flash1@44000000 { @@ -242,6 +245,9 @@ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x44000000 0x04000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; bridge { diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index a81e9c282432..09f3f544f3a7 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -134,6 +134,9 @@ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x40000000 0x04000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; flash1@44000000 { @@ -141,6 +144,9 @@ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x44000000 0x04000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; /* SMSC 9118 ethernet with PHY and EEPROM */ diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 9fd1cb9f4992..85e2e9e27a9f 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -143,6 +143,20 @@ }; }; + auxdisplay { + compatible = "hit,hd44780"; + data-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>, + <&gpio1 26 GPIO_ACTIVE_HIGH>, + <&gpio1 27 GPIO_ACTIVE_HIGH>, + <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + rw-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + backlight-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + display-height-chars = <2>; + display-width-chars = <16>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&backup_button_pin diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts index 43aba4071a5c..d519d307aa2a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -372,3 +372,11 @@ &adc { status = "okay"; }; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts new file mode 100644 index 000000000000..4e09a9cf32b7 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + model = "Facebook YAMP 100 BMC"; + compatible = "facebook,yamp-bmc", "aspeed,ast2500"; + + aliases { + /* + * Override the default uart aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +/* + * Update reset type to "system" (full chip) to fix warm reboot hang issue + * when reset type is set to default ("soc", gated by reset mask registers). + */ +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +/* + * wdt2 is not used by Yamp. + */ +&wdt2 { + status = "disabled"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "facebook-bmc-flash-layout.dtsi" + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + use-ncsi; + no-hw-checksum; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts new file mode 100644 index 000000000000..628195b66d46 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts @@ -0,0 +1,846 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> + +/ { + model = "FP5280G2 BMC"; + compatible = "inspur,fp5280g2-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + coldfire_memory: codefire_memory@9ef00000 { + reg = <0x9ef00000 0x00100000>; + no-map; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + fsi: gpio-fsi { + compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(B, 3)>; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(F, 0)>; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(F, 1)>; + }; + + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca1 0 GPIO_ACTIVE_LOW>; + linux,code = <1>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca1 1 GPIO_ACTIVE_LOW>; + linux,code = <2>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca1 2 GPIO_ACTIVE_LOW>; + linux,code = <3>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca1 3 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + fan4-presence { + label = "fan4-presence"; + gpios = <&pca1 4 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fan5-presence { + label = "fan5-presence"; + gpios = <&pca1 5 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan6-presence { + label = "fan6-presence"; + gpios = <&pca1 6 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + fan7-presence { + label = "fan7-presence"; + gpios = <&pca1 7 GPIO_ACTIVE_LOW>; + linux,code = <8>; + }; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "power"; + /* TODO: dummy gpio */ + gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>; + }; + + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, + <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>; + }; + +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* Test Point */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart3 { + /* APSS */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; +}; + +&uart5 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + /* LCD */ + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + label = "fru"; + }; + +}; + +&i2c2 { + status = "okay"; + + tmp112@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + label = "inlet"; + }; + + tmp112@49 { + compatible = "ti,tmp112"; + reg = <0x49>; + label = "outlet"; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tmp112@4a { + compatible = "ti,tmp112"; + reg = <0x4a>; + label = "psu_inlet"; + }; + + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tmp112@4a { + compatible = "ti,tmp112"; + reg = <0x4a>; + label = "ocp_zone"; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + tmp112@4a { + compatible = "ti,tmp112"; + reg = <0x4a>; + label = "bmc_zone"; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + tmp112@7c { + compatible = "microchip,emc1413"; + reg = <0x7c>; + }; + }; + + }; +}; + +&i2c3 { + /* Riser Card */ + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; +}; + +&i2c5 { + /* vr */ + status = "okay"; +}; + +&i2c6 { + /* bp card */ + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + }; + + adm1278@13 { + compatible = "adi,adm1278"; + reg = <0x13>; + }; + + adm1278@50 { + compatible = "adi,adm1278"; + reg = <0x50>; + }; + + adm1278@53 { + compatible = "adi,adm1278"; + reg = <0x53>; + }; + + }; + + /*pcie riser*/ + + }; +}; + +&i2c8 { + status = "okay"; + + pca0: pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + }; + + pca1: pca9555@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + pca2: pca9555@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + pca3: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + pca4: pca9555@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + pca5: pca9555@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + +}; + +&i2c9 { + /* cpld */ + status = "okay"; +}; + +&i2c10 { + /* hdd bp */ + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + power-supply@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + power-supply@5a { + compatible = "pmbus"; + reg = <0x5a>; + }; +}; + +&i2c12 { + /* odcc */ + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&gpio { + pin_gpio_b7 { + gpio-hog; + gpios = <ASPEED_GPIO(B,7) GPIO_ACTIVE_LOW>; + output-high; + line-name = "BMC_INIT_OK"; + }; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&ibt { + status = "okay"; + +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default &pinctrl_adc4_default + &pinctrl_adc5_default &pinctrl_adc6_default &pinctrl_adc7_default + &pinctrl_adc8_default &pinctrl_adc9_default &pinctrl_adc10_default + &pinctrl_adc11_default &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>; + }; + + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>; + }; + +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts new file mode 100644 index 000000000000..d3695a32e8e0 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts @@ -0,0 +1,566 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Lenovo Hr630 platform + * + * Copyright (C) 2019-present Lenovo + */ + +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "HR630 BMC"; + compatible = "lenovo,hr630-bmc", "aspeed,ast2500"; + + aliases { + i2c14 = &i2c_rbp; + i2c15 = &i2c_fbp1; + i2c16 = &i2c_fbp2; + i2c17 = &i2c_fbp3; + i2c18 = &i2c_riser2; + i2c19 = &i2c_pcie4; + i2c20 = &i2c_riser1; + i2c21 = &i2c_ocp; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x00100000>; /* 1M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>; + }; + + fault { + gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, + <&adc 12>, <&adc 13>, <&adc 14>; + }; + +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default + &pinctrl_nrts2_default + &pinctrl_ndtr2_default + &pinctrl_ndsr2_default + &pinctrl_ncts2_default + &pinctrl_ndcd2_default + &pinctrl_nri2_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart5 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&adc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default>; +}; + +&i2c0 { + status = "okay"; + /* temp1 inlet */ + tmp75@4e { + compatible = "national,lm75"; + reg = <0x4e>; + }; +}; + +&i2c1 { + status = "okay"; + /* temp2 outlet */ + tmp75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + /* Slot 0, + * Slot 1, + * Slot 2, + * Slot 3 + */ + + i2c-switch@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; /* may use mux@70 next. */ + + i2c_rbp: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_fbp1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_fbp2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_fbp3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c7 { + status = "okay"; + + /* Slot 0, + * Slot 1, + * Slot 2, + * Slot 3 + */ + i2c-switch@76 { + compatible = "nxp,pca9546"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; /* may use mux@76 next. */ + + i2c_riser2: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_pcie4: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_riser1: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_ocp: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c8 { + status = "okay"; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@10 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@11 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@12 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@13 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; +}; + +&gpio { + + pin_gpio_b5 { + gpio-hog; + gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "IRQ_BMC_PCH_SMI_LPC_N"; + }; + + pin_gpio_f0 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "IRQ_BMC_PCH_NMI_R"; + }; + + pin_gpio_f3 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "I2C_BUS0_RST_OUT_N"; + }; + + pin_gpio_f4 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "FM_SKT0_FAULT_LED"; + }; + + pin_gpio_f5 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "FM_SKT1_FAULT_LED"; + }; + + pin_gpio_g4 { + gpio-hog; + gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "FAN_PWR_CTL_N"; + }; + + pin_gpio_g7 { + gpio-hog; + gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "RST_BMC_PCIE_I2CMUX_N"; + }; + + pin_gpio_h2 { + gpio-hog; + gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PSU1_FFS_N_R"; + }; + + pin_gpio_h3 { + gpio-hog; + gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PSU2_FFS_N_R"; + }; + + pin_gpio_i3 { + gpio-hog; + gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "BMC_INTRUDED_COVER"; + }; + + pin_gpio_j2 { + gpio-hog; + gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "BMC_BIOS_UPDATE_N"; + }; + + pin_gpio_j3 { + gpio-hog; + gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "RST_BMC_HDD_I2CMUX_N"; + }; + + pin_gpio_s2 { + gpio-hog; + gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "BMC_VGA_SW"; + }; + + pin_gpio_s4 { + gpio-hog; + gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>; + output; + line-name = "VBAT_EN_N"; + }; + + pin_gpio_s6 { + gpio-hog; + gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PU_BMC_GPIOS6"; + }; + + pin_gpio_y0 { + gpio-hog; + gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "BMC_NCSI_MUX_CTL_S0"; + }; + + pin_gpio_y1 { + gpio-hog; + gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "BMC_NCSI_MUX_CTL_S1"; + }; + + pin_gpio_z0 { + gpio-hog; + gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "I2C_RISER2_INT_N"; + }; + + pin_gpio_z2 { + gpio-hog; + gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "I2C_RISER2_RESET_N"; + }; + + pin_gpio_z3 { + gpio-hog; + gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "FM_BMC_PCH_SCI_LPC_N"; + }; + + pin_gpio_z7 { + gpio-hog; + gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "BMC_POST_CMPLT_N"; + }; + + pin_gpio_aa0 { + gpio-hog; + gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "HOST_BMC_USB_SEL"; + }; + + pin_gpio_aa5 { + gpio-hog; + gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "I2C_BUS1_RST_OUT_N"; + }; + +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts new file mode 100644 index 000000000000..73319917cb74 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts @@ -0,0 +1,207 @@ +//SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "aspeed-g4.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "Olympus BMC"; + compatible = "microsoft,olympus-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@40000000 { + reg = <0x40000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@5f000000 { + no-map; + reg = <0x5f000000 0x01000000>; /* 16M */ + }; + }; + + leds { + compatible = "gpio-leds"; + + bmc_heartbeat { + gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; + }; + + power_green { + gpios = <&gpio ASPEED_GPIO(U, 2) GPIO_ACTIVE_HIGH>; + }; + + power_amber { + gpios = <&gpio ASPEED_GPIO(U, 3) GPIO_ACTIVE_HIGH>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + }; + + fault { + gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; + }; + }; + + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts index 024e52a6cd0f..de95112e2a04 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts @@ -322,3 +322,5 @@ &adc { status = "okay"; }; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index b249da80fb83..b0cb34ccb135 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -347,3 +347,25 @@ line-name = "BMC_TPM_INT_N"; }; }; + +&fsi { + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + fsi_hub0: hub@3400 { + compatible = "ibm,fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + no-scan-on-init; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 418a1988b262..9628ecb879cf 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -42,6 +42,13 @@ compatible = "shared-dma-pool"; reusable; }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; }; leds { @@ -304,3 +311,10 @@ &adc { status = "okay"; }; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts new file mode 100644 index 000000000000..caac895c60b4 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts @@ -0,0 +1,966 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> + +/ { + model = "Swift BMC"; + compatible = "ibm,swift-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + air-water { + label = "air-water"; + gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(B, 5)>; + }; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(J, 2)>; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(R, 7)>; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(N, 0)>; + }; + + oppanel-presence { + label = "oppanel-presence"; + gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(A, 7)>; + }; + + opencapi-riser-presence { + label = "opencapi-riser-presence"; + gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(I, 0)>; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + scm0-presence { + label = "scm0-presence"; + gpios = <&pca9552 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + scm1-presence { + label = "scm1-presence"; + gpios = <&pca9552 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + cpu0vrm-presence { + label = "cpu0vrm-presence"; + gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + + cpu1vrm-presence { + label = "cpu1vrm-presence"; + gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 8 GPIO_ACTIVE_LOW>; + linux,code = <8>; + }; + + fanboost-presence { + label = "fanboost-presence"; + gpios = <&pca0 9 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + }; + + leds { + compatible = "gpio-leds"; + + fan0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 0 GPIO_ACTIVE_LOW>; + }; + + fan1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; + }; + + fan2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 2 GPIO_ACTIVE_LOW>; + }; + + fan3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 3 GPIO_ACTIVE_LOW>; + }; + + fanboost { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + }; + + front-fault { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca1 2 GPIO_ACTIVE_LOW>; + }; + + front-power { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca1 3 GPIO_ACTIVE_LOW>; + }; + + front-id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca1 0 GPIO_ACTIVE_LOW>; + }; + + rear-fault { + gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; + }; + + rear-id { + gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon-dps310 { + compatible = "iio-hwmon"; + io-channels = <&dps 0>; + }; + +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <100000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x7F80000>; + label = "obmc-ubi"; + }; + }; + }; + + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <100000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "alt-u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "alt-u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x7F80000>; + label = "alt-obmc-ubi"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* APSS */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart5 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; +}; + +&i2c2 { + status = "okay"; + + /* MUX -> + * Samtec 1 + * Samtec 2 + */ +}; + +&i2c3 { + status = "okay"; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@4 { + compatible = "pmbus-fan"; + reg = <4>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + si7021a20@20 { + compatible = "si,si7021a20"; + reg = <0x20>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca1: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; +}; + +&i2c8 { + status = "okay"; + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", + "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", + "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", + "P9_SCM0_PRES", "P9_SCM1_PRES", + "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", + "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", + "PRESENT_VRM_CP0_N", "PRESENT_VRM_CP1_N", + "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c9 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + pca2: pca9539@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + }; + + gpio@1 { + reg = <1>; + }; + + gpio@2 { + reg = <2>; + }; + + gpio@3 { + reg = <3>; + }; + + gpio@4 { + reg = <4>; + }; + + gpio@5 { + reg = <5>; + }; + + gpio@6 { + reg = <6>; + }; + + gpio@7 { + reg = <7>; + }; + + gpio@8 { + reg = <8>; + }; + + gpio@9 { + reg = <9>; + }; + + gpio@10 { + reg = <10>; + }; + + gpio@11 { + reg = <11>; + }; + + gpio@12 { + reg = <12>; + }; + + gpio@13 { + reg = <13>; + }; + + gpio@14 { + reg = <14>; + }; + + gpio@15 { + reg = <15>; + }; + }; +}; + +&i2c10 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + pca3: pca9539@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + }; + + gpio@1 { + reg = <1>; + }; + + gpio@2 { + reg = <2>; + }; + + gpio@3 { + reg = <3>; + }; + + gpio@4 { + reg = <4>; + }; + + gpio@5 { + reg = <5>; + }; + + gpio@6 { + reg = <6>; + }; + + gpio@7 { + reg = <7>; + }; + + gpio@8 { + reg = <8>; + }; + + gpio@9 { + reg = <9>; + }; + + gpio@10 { + reg = <10>; + }; + + gpio@11 { + reg = <11>; + }; + + gpio@12 { + reg = <12>; + }; + + gpio@13 { + reg = <13>; + }; + + gpio@14 { + reg = <14>; + }; + + gpio@15 { + reg = <15>; + }; + }; +}; + +&i2c11 { + /* MUX + * -> PCIe Slot 0 + * -> PCIe Slot 1 + * -> PCIe Slot 2 + * -> PCIe Slot 3 + */ + status = "okay"; +}; + +&i2c12 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c13 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + aspeed,alt-boot; +}; + +&ibt { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts new file mode 100644 index 000000000000..0b9e29c3212e --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 YADRO +/dts-v1/; + +#include "aspeed-g4.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "Vesnin BMC"; + compatible = "yadro,vesnin-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory { + reg = <0x40000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@5f000000 { + no-map; + reg = <0x5f000000 0x01000000>; /* 16MB */ + }; + flash_memory: region@5c000000 { + no-map; + reg = <0x5c000000 0x02000000>; /* 32M */ + }; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; + }; + power_red { + gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>; + }; + + id_blue { + gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>; + }; + + alarm_red { + gpios = <&gpio ASPEED_GPIO(N, 6) GPIO_ACTIVE_LOW>; + }; + + alarm_yel { + gpios = <&gpio ASPEED_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button_checkstop { + label = "checkstop"; + linux,code = <74>; + gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; + }; + + button_identify { + label = "identify"; + linux,code = <152>; + gpios = <&gpio ASPEED_GPIO(O, 7) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1debug_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&mac0 { + status = "okay"; + + use-ncsi; + no-hw-checksum; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + + +&uart5 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi>; +}; + +&ibt { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&i2c1 { + status = "okay"; + + tmp75@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + occ-hwmon@50 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x50>; + }; +}; + +&i2c5 { + status = "okay"; + + occ-hwmon@51 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x51>; + }; +}; + +&i2c6 { + status = "okay"; + + w83795g@2f { + compatible = "nuvoton,w83795g"; + reg = <0x2f>; + }; +}; + +&i2c7 { + status = "okay"; + + occ-hwmon@56 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x56>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + occ-hwmon@57 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x57>; + }; +}; + +&i2c12 { + status = "okay"; + + rtc@68 { + compatible = "maxim,ds3231"; + reg = <0x68>; + }; +}; + +&i2c13 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index f1356ca794d8..31ea34e14c79 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -33,6 +33,13 @@ compatible = "shared-dma-pool"; reusable; }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32MM */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; }; gpio-keys { @@ -640,3 +647,10 @@ &vhub { status = "okay"; }; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 2c5aa90a546d..30624378316d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -7,6 +7,14 @@ model = "Zaius BMC"; compatible = "ingrasys,zaius-bmc", "aspeed,ast2500"; + aliases { + i2c15 = &i2cpcie0; + i2c16 = &i2cpcie1; + i2c17 = &i2cpcie2; + i2c19 = &i2cpcie3; + i2c20 = &i2cpcie4; + }; + chosen { stdout-path = &uart5; bootargs = "console=ttyS4,115200 earlyprintk"; @@ -223,6 +231,27 @@ reg = <0x71>; #address-cells = <1>; #size-cells = <0>; + + i2cpcie0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2cpcie1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2cpcie2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + i2ctpm: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; /* MUX1 PCA9546A @71h @@ -253,6 +282,17 @@ reg = <0x71>; #address-cells = <1>; #size-cells = <0>; + + i2cpcie3: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2cpcie4: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; }; /* MUX1 PCA9546A @71h @@ -296,33 +336,98 @@ reg = <0x54>; }; }; + + }; + + vrm@64 { + compatible = "isil,isl68137"; + reg = <0x64>; + }; + + vrm@40 { + compatible = "isil,isl68137"; + reg = <0x40>; + }; + + vrm@60 { + compatible = "isil,isl68137"; + reg = <0x60>; + }; + + vrm@43 { + compatible = "infineon,ir38064"; + reg = <0x43>; + }; + + vrm@41 { + compatible = "isil,isl68137"; + reg = <0x41>; }; /* Master selector PCA9541A @70h (other master: CPU0) * LM5066I PMBUS @10h */ - /* 12V Quarter Brick DC/DC Converter Q54SJ12050 @61h */ - power-brick@61 { + /* + * Brick will be one of these types/addresses. Depending + * on the board SKU only one is actually present and will successfully + * instantiate while the others will fail the probe operation. + * These are the PVT (and presumably beyond) addresses: + * 12V Quarter Brick DC/DC Converter Q54SJ12050 @6Ah + * 12V Quarter Brick DC/DC Converter Q54SH12050 @30h + */ + power-brick@6a { + compatible = "delta,dps800"; + reg = <0x6a>; + }; + power-brick@30 { compatible = "delta,dps800"; - reg = <0x61>; + reg = <0x30>; }; /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */ /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */ /* CPU0 VR ISL68137 0.8V PMBUS @60h */ - /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */ + /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */ /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */ + /* Master selector PCA9541A @70h (other master: CPU0) + * LM5066I PMBUS @10h + */ }; &i2c8 { status = "okay"; - /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */ - /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */ - /* CPU1 VR ISL68137 0.8V PMBUS @61h */ + vrm@64 { + compatible = "isil,isl68137"; + reg = <0x64>; + }; + + vrm@40 { + compatible = "isil,isl68137"; + reg = <0x40>; + }; + + vrm@41 { + compatible = "isil,isl68137"; + reg = <0x41>; + }; + + vrm@42 { + compatible = "infineon,ir38064"; + reg = <0x42>; + }; + + vrm@60 { + compatible = "isil,isl68137"; + reg = <0x60>; + }; + + /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */ + /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */ + /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */ /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */ - /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */ + /* CPU1 VR ISL68137 0.8V PMBUS @60h */ }; @@ -435,3 +540,5 @@ &ibt { status = "okay"; }; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts index 0d7c6339da46..a68ff0675c28 100644 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts @@ -112,6 +112,11 @@ &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; }; +&p2a { + status = "okay"; + memory-region = <&vga_memory>; +}; + &ibt { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 5d7050d00874..dd4b0b15afcf 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -53,7 +53,7 @@ #size-cells = <1>; ranges; - fmc: flash-controller@1e620000 { + fmc: spi@1e620000 { reg = < 0x1e620000 0x94 0x20000000 0x10000000 >; #address-cells = <1>; @@ -69,7 +69,7 @@ }; }; - spi: flash-controller@1e630000 { + spi: spi@1e630000 { reg = < 0x1e630000 0x18 0x30000000 0x10000000 >; #address-cells = <1>; @@ -165,6 +165,10 @@ compatible = "aspeed,g4-pinctrl"; }; + p2a: p2a-control { + compatible = "aspeed,ast2400-p2a-ctrl"; + status = "disabled"; + }; }; rng: hwrng@1e6e2078 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 4345c3153ca7..5b1ca265c2ce 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -60,7 +60,7 @@ #size-cells = <1>; ranges; - fmc: flash-controller@1e620000 { + fmc: spi@1e620000 { reg = < 0x1e620000 0xc4 0x20000000 0x10000000 >; #address-cells = <1>; @@ -86,7 +86,7 @@ }; }; - spi1: flash-controller@1e630000 { + spi1: spi@1e630000 { reg = < 0x1e630000 0xc4 0x30000000 0x08000000 >; #address-cells = <1>; @@ -106,7 +106,7 @@ }; }; - spi2: flash-controller@1e631000 { + spi2: spi@1e631000 { reg = < 0x1e631000 0xc4 0x38000000 0x08000000 >; #address-cells = <1>; @@ -219,6 +219,11 @@ aspeed,external-nodes = <&gfx &lhc>; }; + + p2a: p2a-control { + compatible = "aspeed,ast2500-p2a-ctrl"; + status = "disabled"; + }; }; rng: hwrng@1e6e2078 { diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi index 85692c8ef2b1..4ed8500a5cb8 100644 --- a/arch/arm/boot/dts/at91-wb50n.dtsi +++ b/arch/arm/boot/dts/at91-wb50n.dtsi @@ -42,7 +42,7 @@ clock-frequency = <12000000>; }; -&slow_osc { +&clk32k { atmel,osc-bypass; }; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index 1fa84d2f06c7..7debdeabcf2f 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -14,14 +14,6 @@ chosen { bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; stdout-path = "serial0:115200n8"; - - clocksource { - timer = <&timer0>; - }; - - clockevent { - timer = <&timer1>; - }; }; memory { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 9483609a2105..691c95ea6175 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -1258,30 +1258,11 @@ }; }; - sckc@fffffd50 { + clk32k: sckc@fffffd50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffd50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - atmel,startup-time-usec = <1200000>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - atmel,startup-time-usec = <75>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; + clocks = <&slow_xtal>; + #clock-cells = <0>; }; rtc@fffffd20 { diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index e2d38ce43442..8643b7151565 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -868,30 +868,11 @@ status = "disabled"; }; - sckc@fffffd50 { + clk32k: sckc@fffffd50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffd50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - atmel,startup-time-usec = <1200000>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - atmel,startup-time-usec = <75>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; + clocks = <&slow_xtal>; + #clock-cells = <0>; }; rtc@fffffd20 { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 9b7ce6bb1ddc..ef47c005ef03 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -149,28 +149,11 @@ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; - sckc@fffffe50 { + clk32k: sckc@fffffe50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffe50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc>, <&slow_osc>; - }; + clocks = <&slow_xtal>; + #clock-cells = <0>; }; tcb0: timer@f8008000 { diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi index 80b6ba4ca50c..52f91a12a99a 100644 --- a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi @@ -42,7 +42,7 @@ clocks { }; /* Cygnus ARM PLL */ - armpll: armpll { + armpll: armpll@19000000 { #clock-cells = <0>; compatible = "brcm,cygnus-armpll"; clocks = <&osc>; @@ -67,7 +67,7 @@ clocks { clock-mult = <1>; }; - genpll: genpll { + genpll: genpll@301d000 { #clock-cells = <1>; compatible = "brcm,cygnus-genpll"; reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; @@ -94,7 +94,7 @@ clocks { clock-mult = <1>; }; - lcpll0: lcpll0 { + lcpll0: lcpll0@301d02c { #clock-cells = <1>; compatible = "brcm,cygnus-lcpll0"; reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>; @@ -103,7 +103,7 @@ clocks { "usb_phy", "smart_card", "ch5"; }; - mipipll: mipipll { + mipipll: mipipll@180a9800 { #clock-cells = <1>; compatible = "brcm,cygnus-mipipll"; reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>; @@ -113,7 +113,7 @@ clocks { "ch5_unused"; }; - asiu_clks: asiu_clks { + asiu_clks: asiu_clks@301d048 { #clock-cells = <1>; compatible = "brcm,cygnus-asiu-clk"; reg = <0x0301d048 0xc>, <0x180aa024 0x4>; @@ -122,7 +122,7 @@ clocks { clock-output-names = "keypad", "adc/touch", "pwm"; }; - audiopll: audiopll { + audiopll: audiopll@180aeb00 { #clock-cells = <1>; compatible = "brcm,cygnus-audiopll"; reg = <0x180aeb00 0x68>; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 5f7b46503a51..2dac3efc7640 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -45,7 +45,7 @@ ethernet0 = ð0; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0>; }; @@ -69,7 +69,7 @@ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; }; - core { + core@19000000 { compatible = "simple-bus"; ranges = <0x00000000 0x19000000 0x1000000>; #address-cells = <1>; @@ -91,7 +91,7 @@ <0x20100 0x100>; }; - L2: l2-cache { + L2: l2-cache@22000 { compatible = "arm,pl310-cache"; reg = <0x22000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 6925b30c2253..da6d70f09ef1 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -77,7 +77,7 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; - mpcore { + mpcore@19000000 { compatible = "simple-bus"; ranges = <0x00000000 0x19000000 0x00023000>; #address-cells = <1>; @@ -122,7 +122,7 @@ <0x20100 0x100>; }; - L2: l2-cache { + L2: l2-cache@22000 { compatible = "arm,pl310-cache"; reg = <0x22000 0x1000>; cache-unified; @@ -166,7 +166,7 @@ }; }; - axi { + axi@18000000 { compatible = "simple-bus"; ranges = <0x00000000 0x18000000 0x0011c40c>; #address-cells = <1>; @@ -415,9 +415,6 @@ "imp_sleep_timer_p5", "imp_sleep_timer_p7", "imp_sleep_timer_p8"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; /* ports are defined in board DTS */ diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index b99c2e579622..6197e7d80e3b 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -100,7 +100,7 @@ reg-io-width = <4>; }; - L2: l2-cache { + L2: l2-cache@3ff20000 { compatible = "brcm,bcm11351-a2-pl310-cache"; reg = <0x3ff20000 0x1000>; cache-unified; @@ -225,21 +225,21 @@ #size-cells = <1>; ranges; - root_ccu: root_ccu { + root_ccu: root_ccu@35001000 { compatible = "brcm,bcm11351-root-ccu"; reg = <0x35001000 0x0f00>; #clock-cells = <1>; clock-output-names = "frac_1m"; }; - hub_ccu: hub_ccu { + hub_ccu: hub_ccu@34000000 { compatible = "brcm,bcm11351-hub-ccu"; reg = <0x34000000 0x0f00>; #clock-cells = <1>; clock-output-names = "tmon_1m"; }; - aon_ccu: aon_ccu { + aon_ccu: aon_ccu@35002000 { compatible = "brcm,bcm11351-aon-ccu"; reg = <0x35002000 0x0f00>; #clock-cells = <1>; @@ -248,7 +248,7 @@ "pmu_bsc_var"; }; - master_ccu: master_ccu { + master_ccu: master_ccu@3f001000 { compatible = "brcm,bcm11351-master-ccu"; reg = <0x3f001000 0x0f00>; #clock-cells = <1>; @@ -261,7 +261,7 @@ "hsic2_12m"; }; - slave_ccu: slave_ccu { + slave_ccu: slave_ccu@3e011000 { compatible = "brcm,bcm11351-slave-ccu"; reg = <0x3e011000 0x0f00>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts index 8b045cfab64b..be468f4adc37 100644 --- a/arch/arm/boot/dts/bcm21664-garnet.dts +++ b/arch/arm/boot/dts/bcm21664-garnet.dts @@ -21,7 +21,7 @@ model = "BCM21664 Garnet board"; compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 758daa334148..3cf66faf3b56 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -90,7 +90,7 @@ reg-io-width = <4>; }; - L2: l2-cache { + L2: l2-cache@3ff20000 { compatible = "arm,pl310-cache"; reg = <0x3ff20000 0x1000>; cache-unified; @@ -295,21 +295,21 @@ clock-frequency = <156000000>; }; - root_ccu: root_ccu { + root_ccu: root_ccu@35001000 { compatible = BCM21664_DT_ROOT_CCU_COMPAT; reg = <0x35001000 0x0f00>; #clock-cells = <1>; clock-output-names = "frac_1m"; }; - aon_ccu: aon_ccu { + aon_ccu: aon_ccu@35002000 { compatible = BCM21664_DT_AON_CCU_COMPAT; reg = <0x35002000 0x0f00>; #clock-cells = <1>; clock-output-names = "hub_timer"; }; - master_ccu: master_ccu { + master_ccu: master_ccu@3f001000 { compatible = BCM21664_DT_MASTER_CCU_COMPAT; reg = <0x3f001000 0x0f00>; #clock-cells = <1>; @@ -323,7 +323,7 @@ "sdio4_sleep"; }; - slave_ccu: slave_ccu { + slave_ccu: slave_ccu@3e011000 { compatible = BCM21664_DT_SLAVE_CCU_COMPAT; reg = <0x3e011000 0x0f00>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/bcm23550-sparrow.dts b/arch/arm/boot/dts/bcm23550-sparrow.dts index 1c66b15f3013..ace77709f468 100644 --- a/arch/arm/boot/dts/bcm23550-sparrow.dts +++ b/arch/arm/boot/dts/bcm23550-sparrow.dts @@ -45,7 +45,7 @@ bootargs = "console=ttyS0,115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi index 701198f5f498..a36c9b1d23c8 100644 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ b/arch/arm/boot/dts/bcm23550.dtsi @@ -371,21 +371,21 @@ clock-frequency = <156000000>; }; - root_ccu: root_ccu { + root_ccu: root_ccu@35001000 { compatible = BCM21664_DT_ROOT_CCU_COMPAT; reg = <0x35001000 0x0f00>; #clock-cells = <1>; clock-output-names = "frac_1m"; }; - aon_ccu: aon_ccu { + aon_ccu: aon_ccu@35002000 { compatible = BCM21664_DT_AON_CCU_COMPAT; reg = <0x35002000 0x0f00>; #clock-cells = <1>; clock-output-names = "hub_timer"; }; - slave_ccu: slave_ccu { + slave_ccu: slave_ccu@3e011000 { compatible = BCM21664_DT_SLAVE_CCU_COMPAT; reg = <0x3e011000 0x0f00>; #clock-cells = <1>; @@ -398,7 +398,7 @@ "bsc4"; }; - master_ccu: master_ccu { + master_ccu: master_ccu@3f001000 { compatible = BCM21664_DT_MASTER_CCU_COMPAT; reg = <0x3f001000 0x0f00>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index fbfca83bd28f..ead6e9804dbf 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -21,7 +21,7 @@ model = "BCM28155 AP board"; compatible = "brcm,bcm28155-ap", "brcm,bcm11351"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 9777644c6c2b..4b21ddb26aa5 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -431,6 +431,8 @@ reg = <0x7e204000 0x1000>; interrupts = <2 22>; clocks = <&clocks BCM2835_CLOCK_VPU>; + dmas = <&dma 6>, <&dma 7>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts index 1c6f561ac52b..6a96655d8626 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -69,8 +69,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; rfkill { label = "WiFi"; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts index e550799a6ae0..3b0029e61b4c 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -53,8 +53,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; brightness { label = "Backlight"; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index 7bfa2238f70b..90f57bad6b24 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200 earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; @@ -99,8 +99,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts index fd361c9b1374..41548d6d479a 100644 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts @@ -16,15 +16,13 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts index 7c34360d3285..cd797b4202ad 100644 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts @@ -17,15 +17,13 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 969b8d78e492..e58c8077be1d 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -15,7 +15,7 @@ bootargs = "console=ttyS0,115200 earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -44,8 +44,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index b62854ee27ab..766db617455b 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200 earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -51,8 +51,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index 75f7b4ef35da..fed75e6ab58c 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -62,8 +62,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts index 148d16a9085e..79542e18915c 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -58,8 +58,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index eed3aab6679b..abd35a518046 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200 earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -93,8 +93,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; rfkill { label = "WiFi"; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts index fe842f2f1ca7..c29950b43a95 100644 --- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -59,8 +59,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 6fcbb0509ba0..4dcec6865469 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200 earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -90,8 +90,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; aoss { label = "AOSS"; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts index b3e8cc90b13f..0e349e39f608 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -95,8 +95,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index fdeaa895512f..b9d95011637d 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -15,7 +15,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -44,8 +44,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 0d510cb15ec3..0052e1b24130 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -16,7 +16,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -88,8 +88,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index 962e89edba11..01c390ed48ea 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -15,7 +15,7 @@ bootargs = "earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -76,8 +76,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; rfkill { label = "WiFi"; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index 658a56ff8a5c..911c65fbf251 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyS0,115200 earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -85,8 +85,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 5fd47eec4407..18d0ae46e76c 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -16,7 +16,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -24,8 +24,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index 6604be6ff0a0..50f7cd08cfbb 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -16,7 +16,7 @@ bootargs = "earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; @@ -43,8 +43,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index 567ebbd5a0e9..b47fb0700a1f 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -15,7 +15,7 @@ bootargs = "earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -42,8 +42,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index ac2d136ed334..bcc420f85b56 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -16,7 +16,7 @@ bootargs = "earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; @@ -43,8 +43,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index 74371e821b1a..ac7515423474 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -16,7 +16,7 @@ bootargs = "console=ttyS0,115200 earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; @@ -83,8 +83,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index b44af63ee310..6d28b7dacd05 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -16,7 +16,7 @@ bootargs = "earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; @@ -58,8 +58,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts index eebc0d43e220..f42a1703f4ab 100644 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -16,7 +16,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; @@ -64,8 +64,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; brightness { label = "Backlight"; diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts index 456045f17a00..ac3a4483dcb3 100644 --- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts +++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts @@ -13,7 +13,7 @@ compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708"; model = "Phicomm K3"; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; @@ -21,8 +21,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index eb59508578e4..57ca1cfaecd8 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -15,7 +15,7 @@ bootargs = "earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -38,8 +38,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 4c71f5e95e00..2e1a7e382cb7 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -15,7 +15,7 @@ bootargs = "earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -48,8 +48,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts index 5ad53ea52d0a..049cdfd92706 100644 --- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts @@ -15,7 +15,7 @@ bootargs = "console=ttyS0,115200 earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -58,8 +58,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; rfkill { label = "WiFi"; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index ac5266ee8d4c..372dc1eb88a0 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -19,7 +19,7 @@ #size-cells = <1>; interrupt-parent = <&gic>; - chipcommonA { + chipcommonA@18000000 { compatible = "simple-bus"; ranges = <0x00000000 0x18000000 0x00001000>; #address-cells = <1>; @@ -44,7 +44,7 @@ }; }; - mpcore { + mpcore@19000000 { compatible = "simple-bus"; ranges = <0x00000000 0x19000000 0x00023000>; #address-cells = <1>; @@ -148,7 +148,7 @@ }; }; - usb2_phy: usb2-phy { + usb2_phy: usb2-phy@1800c000 { compatible = "brcm,ns-usb2-phy"; reg = <0x1800c000 0x1000>; reg-names = "dmu"; @@ -357,7 +357,7 @@ #address-cells = <0>; }; - mdio-bus-mux { + mdio-bus-mux@18003000 { compatible = "mdio-mux-mmioreg"; mdio-parent-bus = <&mdio>; #address-cells = <1>; @@ -464,8 +464,6 @@ srab: srab@18007000 { compatible = "brcm,bcm5301x-srab"; reg = <0x18007000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index b29695bd4855..4af8e3293cff 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -32,7 +32,7 @@ }; }; - mpcore { + mpcore@18310000 { compatible = "simple-bus"; ranges = <0x00000000 0x18310000 0x00008000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index e6a41e1b27fd..9c0325cf9e22 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -41,9 +41,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <0>; - /* UBUS peripheral clock */ periph_clk: periph_clk { #clock-cells = <0>; @@ -94,7 +91,7 @@ reg = <0x1e000 0x100>; }; - gic: interrupt-controller@1e100 { + gic: interrupt-controller@1f000 { compatible = "arm,cortex-a9-gic"; reg = <0x1f000 0x1000 0x1e100 0x100>; @@ -125,7 +122,7 @@ IRQ_TYPE_LEVEL_HIGH)>; }; - armpll: armpll { + armpll: armpll@20000 { #clock-cells = <0>; compatible = "brcm,bcm63138-armpll"; clocks = <&periph_clk>; @@ -144,7 +141,7 @@ #reset-cells = <2>; }; - ahci: sata@8000 { + ahci: sata@a000 { compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci"; reg-names = "ahci", "top-ctrl"; reg = <0xa000 0x9ac>, <0x8040 0x24>; diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts index 8006c69a3fdf..8313b7cad542 100644 --- a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts +++ b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts @@ -6,7 +6,7 @@ model = "Broadcom STB (bcm7445), SVMB reference board"; compatible = "brcm,bcm7445", "brcm,brcmstb"; - memory { + memory@0 { device_type = "memory"; reg = <0x00 0x00000000 0x00 0x40000000>, <0x00 0x40000000 0x00 0x40000000>, diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index 504a63236a5e..58f67c9b830b 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -63,7 +63,7 @@ <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; }; - rdb { + rdb@f0000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -224,7 +224,7 @@ }; - memory_controllers { + memory_controllers@f1100000 { compatible = "simple-bus"; ranges = <0x0 0x0 0xf1100000 0x200000>; #address-cells = <1>; @@ -252,7 +252,7 @@ }; }; - memc@1 { + memc@80000 { compatible = "brcm,brcmstb-memc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -274,7 +274,7 @@ }; }; - memc@2 { + memc@100000 { compatible = "brcm,brcmstb-memc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index 53f990defd6a..b2d323f4a5ab 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -49,8 +49,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; hook { label = "HOOK"; diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts index 4991700ae6b0..b0b8c774a37f 100644 --- a/arch/arm/boot/dts/bcm947189acdbmr.dts +++ b/arch/arm/boot/dts/bcm947189acdbmr.dts @@ -17,7 +17,7 @@ bootargs = "console=ttyS0,115200 earlycon"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>; }; @@ -43,8 +43,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; restart { label = "Reset"; diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 250a1d6f2d05..957468224622 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -39,15 +39,13 @@ model = "NorthStar Enterprise Router (BCM953012ER)"; compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x8000000>; }; gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index 52c4c6c9d3f1..046c59fb4846 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -43,7 +43,7 @@ serial1 = &uart1; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 21479b4ce823..8c388eb8a08f 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -43,7 +43,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index cda3d790965b..c339771bb22e 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -43,7 +43,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index f86649812b59..1c72ec8288de 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -43,7 +43,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index df60602b054d..96a021cebd97 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -43,7 +43,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index 3893e7af343a..b2c7f21d471e 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -43,7 +43,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index cf226b02141f..a2c9de35ddfb 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -43,7 +43,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 10b3d512bb33..3fcca12d83c2 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -42,7 +42,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts index 29525686e51a..5b177274f182 100644 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -16,7 +16,7 @@ stdout-path = &serial0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index e39db14d805e..edd0f630e025 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -43,7 +43,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index f2d2b872333e..5b2b1ed04d51 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -188,6 +188,19 @@ }; }; +&cpu { + cpu-supply = <&vdcdc3_reg>; +}; + +/* + * The standard da850-evm kits and SOM's are 375MHz so enable this operating + * point by default. Higher frequencies must be enabled for custom boards with + * other variants of the SoC. + */ +&opp_375 { + status = "okay"; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index 2fd2a6838dab..e379d6e7ad49 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -154,12 +154,48 @@ }; }; }; + + cvdd: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "cvdd"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; }; &ref_clk { clock-frequency = <24000000>; }; +&cpu { + cpu-supply = <&cvdd>; +}; + +/* + * LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are + * valid. Unfortunately due to a problem with the DA8XX OHCI controller, we + * can't enable more than one OPP by default, since the controller sometimes + * becomes unresponsive after a transition. Fix the frequency at 456 MHz. + */ + +&opp_100 { + status = "disabled"; +}; + +&opp_200 { + status = "disabled"; +}; + +&opp_300 { + status = "disabled"; +}; + +&opp_456 { + status = "okay"; +}; + &pmx_core { status = "okay"; diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts index 09c3666def66..afd04a423856 100644 --- a/arch/arm/boot/dts/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/da850-lego-ev3.dts @@ -122,6 +122,15 @@ amp-supply = <&>; }; + cvdd: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "cvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + /* * This is a 5V current limiting regulator that is shared by USB, * the sensor (input) ports, the motor (output) ports and the A/DC. @@ -201,6 +210,27 @@ clock-frequency = <24000000>; }; +&cpu { + cpu-supply = <&cvdd>; +}; + +/* since we have a fixed regulator, we can't run at these points */ +&opp_100 { + status = "disabled"; +}; + +&opp_200 { + status = "disabled"; +}; + +/* + * The SoC is actually the 456MHz version, but because of the fixed regulator + * This is the fastest we can go. + */ +&opp_375 { + status = "okay"; +}; + &pmx_core { status = "okay"; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index e6e78b88cacb..7cf31b6e48b7 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -16,6 +16,56 @@ reg = <0xc0000000 0x0>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + clocks = <&psc0 14>; + operating-points-v2 = <&opp_table>; + }; + }; + + opp_table: opp-table { + compatible = "operating-points-v2"; + + opp_100: opp100-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000 950000 1050000>; + }; + + opp_200: opp110-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000 1050000 1160000>; + }; + + opp_300: opp120-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1200000 1140000 1320000>; + }; + + /* + * Original silicon was 300MHz max, so higher frequencies + * need to be enabled on a per-board basis if the chip is + * capable. + */ + + opp_375: opp120-375000000 { + status = "disabled"; + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <1200000 1140000 1320000>; + }; + + opp_456: opp130-456000000 { + status = "disabled"; + opp-hz = /bits/ 64 <456000000>; + opp-microvolt = <1300000 1250000 1350000>; + }; + }; + arm { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index abfff54d6de5..0a27f034dd6b 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -25,7 +25,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial1:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index ace50e194a45..dee35e3a5c4b 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -59,6 +59,11 @@ cpu0-supply = <&buck2_reg>; }; +&gpu { + mali-supply = <&buck3_reg>; + status = "okay"; +}; + &i2c_0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index e25765500e99..248bd372fe70 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -172,6 +172,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&buck3_reg>; + status = "okay"; +}; + &hsotg { vusb_d-supply = <&ldo15_reg>; vusb_a-supply = <&ldo12_reg>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 7479993755da..86c26a4edfd7 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -244,6 +244,11 @@ }; }; +&gpu { + mali-supply = <&buck3_reg>; + status = "okay"; +}; + &i2c_0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 8ce3a7786b19..5659c4a10729 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -462,6 +462,39 @@ status = "disabled"; }; + gpu: gpu@13000000 { + compatible = "samsung,exynos4210-mali", "arm,mali-400"; + reg = <0x13000000 0x10000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + clocks = <&cmu CLK_G3D>, + <&cmu CLK_SCLK_G3D>; + clock-names = "bus", "core"; + power-domains = <&pd_g3d>; + status = "disabled"; + /* TODO: operating points for DVFS, assigned clock as 134 MHz */ + }; + mfc: codec@13400000 { compatible = "samsung,mfc-v7"; reg = <0x13400000 0x10000>; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 36ccf227434d..1264cc431ff6 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -54,7 +54,7 @@ pmu: pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&combiner>; - interrupts = <2 2>, <3 2>; + status = "disabled"; }; soc: soc { @@ -415,6 +415,20 @@ }; }; + gpu: gpu@13000000 { + compatible = "samsung,exynos4210-mali", "arm,mali-400"; + reg = <0x13000000 0x10000>; + /* + * CLK_G3D is not actually bus clock but a IP-level clock. + * The bus clock is not described in hardware manual. + */ + clocks = <&clock CLK_G3D>, + <&clock CLK_SCLK_G3D>; + clock-names = "bus", "core"; + power-domains = <&pd_g3d>; + status = "disabled"; + }; + i2s1: i2s@13960000 { compatible = "samsung,s3c6410-i2s"; reg = <0x13960000 0x100>; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 36b1edea254a..0d1e1a9c2f6e 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -132,6 +132,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&buck3_reg>; + status = "okay"; +}; + &hsotg { vusb_d-supply = <&ldo3_reg>; vusb_a-supply = <&ldo8_reg>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 6882480dbaf7..7c39dd1c4d3a 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -239,6 +239,10 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + &hsotg { vusb_d-supply = <&vusb_reg>; vusb_a-supply = <&vusbdac_reg>; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index bf092e97e14f..82a8b5449978 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -262,6 +262,11 @@ }; }; +&gpu { + mali-supply = <&buck2_reg>; + status = "okay"; +}; + &hdmi { hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b491c345b2e8..f220716239db 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -8,7 +8,7 @@ * www.linaro.org * * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in @@ -381,13 +381,13 @@ trips { cpu_alert0: cpu-alert-0 { - temperature = <85000>; /* millicelsius */ + temperature = <85000>; /* millicelsius */ }; cpu_alert1: cpu-alert-1 { - temperature = <100000>; /* millicelsius */ + temperature = <100000>; /* millicelsius */ }; cpu_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ + temperature = <110000>; /* millicelsius */ }; }; }; @@ -449,6 +449,43 @@ samsung,lcd-wb; }; +&gpu { + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + }; +}; + &mdma1 { power-domains = <&pd_lcd0>; }; @@ -461,6 +498,12 @@ <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; }; +&pmu { + interrupts = <2 2>, <3 2>; + interrupt-affinity = <&cpu0>, <&cpu1>; + status = "okay"; +}; + &pmu_system_controller { clock-names = "clkout0", "clkout1", "clkout2", "clkout3", "clkout4", "clkout8", "clkout9"; diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 30eee5942eff..ce87d2ff27aa 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -15,6 +15,24 @@ i2c10 = &i2c_cm36651; }; + aat1290 { + compatible = "skyworks,aat1290"; + flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; + enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "host", "isp"; + pinctrl-0 = <&camera_flash_host>; + pinctrl-1 = <&camera_flash_host>; + pinctrl-2 = <&camera_flash_isp>; + + flash-led { + label = "flash"; + led-max-microamp = <520833>; + flash-max-microamp = <1012500>; + flash-max-timeout-us = <1940000>; + }; + }; + lcd_vdd3_reg: voltage-regulator-6 { compatible = "regulator-fixed"; regulator-name = "LCD_VDD_2.2V"; @@ -131,6 +149,20 @@ regulator-max-microvolt = <2800000>; }; +&pinctrl_0 { + camera_flash_host: camera-flash-host { + samsung,pins = "gpj1-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-val = <0>; + }; + + camera_flash_isp: camera-flash-isp { + samsung,pins = "gpj1-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-val = <1>; + }; +}; + &s5c73m3 { standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ vdda-supply = <&ldo17_reg>; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index 0038465f38f1..462a5409b1de 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -115,6 +115,11 @@ cpu0-supply = <&buck2_reg>; }; +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + &hsotg { vusb_d-supply = <&ldo15_reg>; vusb_a-supply = <&ldo12_reg>; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 4c15cb616cdf..83be3a797411 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -453,6 +453,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + &hdmi { hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 08d3a0a7b4eb..ea55f377d17c 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -229,6 +229,11 @@ assigned-clock-rates = <0>, <176000000>; }; +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + &hdmi { hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos4412-prime.dtsi b/arch/arm/boot/dts/exynos4412-prime.dtsi index d83fbd4e434c..3731a225f779 100644 --- a/arch/arm/boot/dts/exynos4412-prime.dtsi +++ b/arch/arm/boot/dts/exynos4412-prime.dtsi @@ -38,3 +38,10 @@ cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, <&cpu2 15 15>, <&cpu3 15 15>; }; + +&gpu_opp_table { + opp-533000000 { + opp-hz = /bits/ 64 <533000000>; + opp-microvolt = <1075000>; + }; +}; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index e5c041ec0756..d20db2dfe8e2 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -716,6 +716,53 @@ cpu-offset = <0x4000>; }; +&gpu { + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <875000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <900000>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <950000>; + }; + opp-440000000 { + opp-hz = /bits/ 64 <440000000>; + opp-microvolt = <1025000>; + }; + }; +}; + &hdmi { compatible = "samsung,exynos4212-hdmi"; }; @@ -737,6 +784,8 @@ &pmu { interrupts = <2 2>, <3 2>, <18 2>, <19 2>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; }; &pmu_system_controller { diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 8f9e08f940ab..e0db251e253f 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -85,6 +85,11 @@ }; }; +&adc { + vdd-supply = <&ldo10_reg>; + status = "okay"; +}; + &audi2s0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 57fc9c949e54..e6f78b1cee7c 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -260,6 +260,12 @@ }; }; +&adc { + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + samsung,syscon-phandle = <&pmu_system_controller>; +}; + &arm_a15_pmu { interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; status = "okay"; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index dbf0306896f6..592d7b45ecc8 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -386,6 +386,10 @@ * (Linaro for Arndale Octa, v2012.07). */ regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo4_reg: LDO4 { @@ -411,6 +415,10 @@ regulator-name = "PVDD_ANAIP_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo8_reg: LDO8 { @@ -451,6 +459,10 @@ regulator-name = "PVDD_APIO_MMCOFF_2V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo14_reg: LDO14 { @@ -464,12 +476,20 @@ regulator-name = "PVDD_PERI_2V8"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; }; ldo16_reg: LDO16 { regulator-name = "PVDD_PERI_3V3"; regulator-min-microvolt = <2200000>; regulator-max-microvolt = <2200000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; }; ldo17_reg: LDO17 { @@ -483,12 +503,28 @@ regulator-name = "PVDD_EMMC_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + /* + * Must stay in "off" mode during shutdown for + * proper eMMC reset. The "off" mode is in + * fact controlled by LDO18EN. The eMMC does + * not have reset pin connected so the reset + * will be triggered by falling edge of + * LDO18EN. + */ + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo19_reg: LDO19 { regulator-name = "PVDD_TFLASH_2V8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo20_reg: LDO20 { @@ -515,12 +551,20 @@ regulator-min-microvolt = <800000>; regulator-max-microvolt = <1100000>; regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; }; ldo24_reg: LDO24 { regulator-name = "PVDD_CAM1_AVDD_2V8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; }; ldo25_reg: LDO25 { @@ -540,6 +584,10 @@ regulator-name = "PVDD_G3DS_1V0"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1100000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; }; ldo28_reg: LDO28 { @@ -615,55 +663,75 @@ buck1_reg: BUCK1 { regulator-name = "PVDD_MIF_1V1"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck2_reg: BUCK2 { regulator-name = "vdd_arm"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck3_reg: BUCK3 { regulator-name = "PVDD_INT_1V0"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck4_reg: BUCK4 { regulator-name = "PVDD_G3D_1V0"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck5_reg: BUCK5 { regulator-name = "PVDD_LPDDR3_1V2"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; regulator-always-on; }; buck6_reg: BUCK6 { regulator-name = "PVDD_KFC_1V0"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck7_reg: BUCK7 { regulator-name = "VIN_LLDO_1V4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; regulator-always-on; }; buck8_reg: BUCK8 { regulator-name = "VIN_MLDO_2V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; regulator-always-on; }; @@ -678,6 +746,18 @@ regulator-name = "PVDD_EMMCF_2V8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + /* + * Must stay in "off" mode during shutdown for + * proper eMMC reset. The "off" mode is in + * fact controlled by BUCK10EN. The eMMC does + * not have reset pin connected so the reset + * will be triggered by falling edge of + * BUCK10EN. + */ + + regulator-state-mem { + regulator-off-in-suspend; + }; }; }; }; @@ -700,7 +780,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - vmmc-supply = <&ldo10_reg>; + vmmc-supply = <&ldo18_reg>; vqmmc-supply = <&ldo3_reg>; bus-width = <8>; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 5fb2326875dc..55d4dbf6f83a 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -42,117 +42,119 @@ * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. */ - soc: soc { - cluster_a15_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <140000>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1175000>; - clock-latency-ns = <140000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <140000>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <140000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500>; - clock-latency-ns = <140000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = < 987500>; - clock-latency-ns = <140000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = < 962500>; - clock-latency-ns = <140000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = < 937500>; - clock-latency-ns = <140000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = < 912500>; - clock-latency-ns = <140000>; - }; + cluster_a15_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <140000>; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1175000>; + clock-latency-ns = <140000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <140000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <140000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1012500>; + clock-latency-ns = <140000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = < 987500>; + clock-latency-ns = <140000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = < 962500>; + clock-latency-ns = <140000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = < 937500>; + clock-latency-ns = <140000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = < 912500>; + clock-latency-ns = <140000>; }; + }; - cluster_a7_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1275000>; - clock-latency-ns = <140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1162500>; - clock-latency-ns = <140000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <140000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <975000>; - clock-latency-ns = <140000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <937500>; - clock-latency-ns = <140000>; - }; + cluster_a7_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1275000>; + clock-latency-ns = <140000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1162500>; + clock-latency-ns = <140000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <140000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <975000>; + clock-latency-ns = <140000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <937500>; + clock-latency-ns = <140000>; }; + }; + soc: soc { cci: cci@10d20000 { compatible = "arm,cci-400"; #address-cells = <1>; @@ -548,18 +550,6 @@ status = "disabled"; }; - adc: adc@12d10000 { - compatible = "samsung,exynos-adc-v2"; - reg = <0x12D10000 0x100>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - hsi2c_8: i2c@12e00000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E00000 0x1000>; @@ -1363,6 +1353,12 @@ }; }; +&adc { + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + samsung,syscon-phandle = <&pmu_system_controller>; +}; + &dp { clocks = <&clock CLK_DP1>; clock-names = "dp"; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25d95de15c9b..829147e320e0 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -177,6 +177,10 @@ regulator-name = "vdd_adc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo5_reg: LDO5 { @@ -184,6 +188,10 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo6_reg: LDO6 { @@ -191,6 +199,10 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo7_reg: LDO7 { @@ -198,6 +210,10 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo8_reg: LDO8 { @@ -205,6 +221,10 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo9_reg: LDO9 { @@ -212,6 +232,10 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo10_reg: LDO10 { @@ -219,6 +243,10 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo11_reg: LDO11 { @@ -226,6 +254,10 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo12_reg: LDO12 { @@ -239,6 +271,10 @@ regulator-name = "vddq_mmc2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo14_reg: LDO14 { @@ -253,6 +289,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo16_reg: LDO16 { @@ -267,18 +307,30 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo18_reg: LDO18 { regulator-name = "vdd_emmc_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo19_reg: LDO19 { regulator-name = "vdd_sd"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo20_reg: LDO20 { @@ -307,6 +359,10 @@ regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo24_reg: LDO24 { @@ -328,6 +384,10 @@ regulator-name = "vdd_ldo26"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo27_reg: LDO27 { @@ -335,6 +395,10 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo28_reg: LDO28 { @@ -342,6 +406,10 @@ regulator-name = "vdd_ldo28"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; ldo29_reg: LDO29 { @@ -420,6 +488,10 @@ regulator-max-microvolt = <1300000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck2_reg: BUCK2 { @@ -428,6 +500,10 @@ regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck3_reg: BUCK3 { @@ -436,6 +512,10 @@ regulator-max-microvolt = <1400000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck4_reg: BUCK4 { @@ -444,6 +524,10 @@ regulator-max-microvolt = <1400000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck5_reg: BUCK5 { @@ -460,20 +544,24 @@ regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; + regulator-name = "vdd_1.35v_ldo"; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; }; buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2.0v_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; regulator-always-on; regulator-boot-on; }; @@ -484,14 +572,20 @@ regulator-max-microvolt = <3750000>; regulator-always-on; regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; buck10_reg: BUCK10 { regulator-name = "vdd_vmem"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 93a48f2dda49..838872037493 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -360,6 +360,12 @@ }; }; +&buck10_reg { + /* Supplies vmmc-supply of mmc_0 */ + regulator-always-on; + regulator-boot-on; +}; + &hdmi { status = "okay"; ddc = <&i2c_2>; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index ae866bcc30c4..0b27bebf9528 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -96,6 +96,15 @@ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; }; + adc: adc@12d10000 { + compatible = "samsung,exynos-adc-v2"; + reg = <0x12d10000 0x100>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + /* i2c_0-3 are defined in exynos5.dtsi */ hsi2c_4: i2c@12ca0000 { compatible = "samsung,exynos5250-hsi2c"; diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index 3613f05f8a80..bfaa2de63a10 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -64,7 +64,7 @@ gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; num-chipselects = <1>; panel: display@0 { diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index bf0cb55809f8..4263a9339c2e 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -347,7 +347,7 @@ /* non-configurable replicators don't show up on the * AMBA bus. As such no need to add "arm,primecell". */ - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; out-ports { #address-cells = <1>; @@ -382,7 +382,7 @@ /* non-configurable replicators don't show up on the * AMBA bus. As such no need to add "arm,primecell". */ - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; out-ports { #address-cells = <1>; @@ -417,7 +417,7 @@ /* non-configurable replicators don't show up on the * AMBA bus. As such no need to add "arm,primecell". */ - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; out-ports { #address-cells = <1>; @@ -451,7 +451,7 @@ /* non-configurable replicators don't show up on the * AMBA bus. As such no need to add "arm,primecell". */ - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; out-ports { #address-cells = <1>; @@ -482,7 +482,7 @@ }; funnel@0,e3c41000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0xe3c41000 0 0x1000>; clocks = <&clk_375m>; @@ -531,7 +531,7 @@ }; funnel@0,e3c81000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0xe3c81000 0 0x1000>; clocks = <&clk_375m>; @@ -580,7 +580,7 @@ }; funnel@0,e3cc1000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0xe3cc1000 0 0x1000>; clocks = <&clk_375m>; @@ -629,7 +629,7 @@ }; funnel@0,e3d01000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0xe3d01000 0 0x1000>; clocks = <&clk_375m>; @@ -678,7 +678,7 @@ }; funnel@0,e3c04000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0xe3c04000 0 0x1000>; clocks = <&clk_375m>; diff --git a/arch/arm/boot/dts/ibm-power9-dual.dtsi b/arch/arm/boot/dts/ibm-power9-dual.dtsi new file mode 100644 index 000000000000..2abc42eda7b0 --- /dev/null +++ b/arch/arm/boot/dts/ibm-power9-dual.dtsi @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2018 IBM Corp + +&fsi { + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam0_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam0_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam0_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam0_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam0_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam0_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam0_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam0_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam1_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam1_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam1_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam1_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam1_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam1_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam1_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam1_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam1_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + +/ { + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c102 = &cfam0_i2c2; + i2c103 = &cfam0_i2c3; + i2c104 = &cfam0_i2c4; + i2c105 = &cfam0_i2c5; + i2c106 = &cfam0_i2c6; + i2c107 = &cfam0_i2c7; + i2c108 = &cfam0_i2c8; + i2c109 = &cfam0_i2c9; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c200 = &cfam1_i2c0; + i2c201 = &cfam1_i2c1; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c204 = &cfam1_i2c4; + i2c205 = &cfam1_i2c5; + i2c206 = &cfam1_i2c6; + i2c207 = &cfam1_i2c7; + i2c208 = &cfam1_i2c8; + i2c209 = &cfam1_i2c9; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c212 = &cfam1_i2c12; + i2c213 = &cfam1_i2c13; + i2c214 = &cfam1_i2c14; + }; +}; diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts index f0a3fde0739c..10acc5331ba6 100644 --- a/arch/arm/boot/dts/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/imx53-m53menlo.dts @@ -10,6 +10,25 @@ model = "MENLO M53 EMBEDDED DEVICE"; compatible = "menlo,m53menlo", "fsl,imx53"; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_power_button>; + pinctrl-names = "default"; + + power-button { + label = "Power button"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pinctrl_power_out>; + pinctrl-names = "default"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -30,7 +49,7 @@ eth { label = "EthLedYe"; gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; + linux,default-trigger = "netdev"; }; }; @@ -45,12 +64,19 @@ }; }; + beeper { + compatible = "gpio-beeper"; + pinctrl-0 = <&pinctrl_beeper>; + gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + }; + reg_usbh1_vbus: regulator-usbh1-vbus { compatible = "regulator-fixed"; regulator-name = "vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; @@ -74,6 +100,25 @@ assigned-clock-rates = <133333334>, <33333334>, <33333334>; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio2 27 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev@0 { + compatible = "menlo,m53cpld"; + spi-max-frequency = <25000000>; + reg = <0>; + }; + + spidev@1 { + compatible = "menlo,m53cpld"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; + &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; @@ -86,9 +131,82 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>; status = "okay"; }; +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "TestPin_SV2_3", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "", + "", "CPLD_JTAG_TDO", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "CPLD_JTAG_TCK", "KBD_intK", + "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]", + "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", + "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI"; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "", + "CPLD_reset", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "USB-OTG_OverCurrent", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -136,27 +254,37 @@ imx53-m53evk { hoggrp { fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 - MX53_PAD_EIM_EB3__GPIO2_31 0x1d5 - MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5 - MX53_PAD_GPIO_19__CCM_CLKO 0x1d5 - MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5 - MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5 - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5 - MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5 - MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5 + MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 + MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 + MX53_PAD_EIM_D25__GPIO3_25 0x1e4 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 + MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 >; }; pinctrl_led: ledgrp { fsl,pins = < - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5 + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 + >; + }; + + pinctrl_beeper: beepergrp { + fsl,pins = < + MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4 >; }; @@ -169,49 +297,66 @@ pinctrl_can2: can2grp { fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4 + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 >; }; pinctrl_display_gpio: display-gpiogrp { fsl,pins = < - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */ - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */ + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ + MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ + + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ >; }; pinctrl_edt_ft5x06: edt-ft5x06grp { fsl,pins = < - MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */ - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */ - MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */ + MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ + MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4 + MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4 + MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4 + MX53_PAD_EIM_RW__GPIO2_26 0xe4 + MX53_PAD_EIM_LBA__GPIO2_27 0xe4 >; }; pinctrl_esdhc1: esdhc1grp { fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 + MX53_PAD_GPIO_1__GPIO1_1 0x1c4 + MX53_PAD_GPIO_9__GPIO1_9 0x1e4 >; }; pinctrl_fec: fecgrp { fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 + MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 >; }; @@ -240,10 +385,24 @@ >; }; + pinctrl_power_button: powerbutgrp { + fsl,pins = < + MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 + >; + }; + + pinctrl_power_out: poweroutgrp { + fsl,pins = < + MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4 + MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4 >; }; @@ -251,13 +410,25 @@ fsl,pins = < MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4 + MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 >; }; pinctrl_usb: usbgrp { fsl,pins = < - MX53_PAD_GPIO_2__GPIO1_2 0x1d5 - MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5 + MX53_PAD_GPIO_2__GPIO1_2 0x1c4 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4 + MX53_PAD_GPIO_4__GPIO1_4 0x1c4 + MX53_PAD_GPIO_18__GPIO7_13 0x1c4 >; }; }; @@ -287,12 +458,21 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + linux,rs485-enabled-at-boot-time; status = "okay"; }; @@ -301,7 +481,7 @@ pinctrl-0 = <&pinctrl_usb>; vbus-supply = <®_usbh1_vbus>; phy_type = "utmi"; - dr_mode = "peripheral"; + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 09071ca11c6c..ec9fb8940ffa 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -185,6 +185,31 @@ >; }; + pinctrl_ipu_csi0: ipucsi0grp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4 + MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4 + MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4 + MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4 + MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4 + MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4 + MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4 + MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4 + MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4 + MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4 + MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4 + MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4 + >; + }; + + pinctrl_ov5642: ov5642grp { + fsl,pins = < + MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4 + MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4 + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 @@ -256,11 +281,47 @@ camera: ov5642@3c { compatible = "ovti,ov5642"; reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5642>; + assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>, + <&clks IMX5_CLK_SSI_EXT1_COM_SEL>; + assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>, + <&clks IMX5_CLK_SSI_EXT1_PODF>; + assigned-clock-rates = <0>, <24000000>; + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; + clock-names = "xclk"; + DVDD-supply = <&ldo9_reg>; + AVDD-supply = <&ldo7_reg>; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; + + port { + ov5642_to_ipu_csi0: endpoint { + remote-endpoint = <&ipu_csi0_from_parallel_sensor>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; }; pmic: dialog@48 { compatible = "dlg,da9053", "dlg,da9052"; reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + regulators { + ldo7_reg: ldo7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + }; + + ldo9_reg: ldo9 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <3650000>; + }; + }; }; }; @@ -271,3 +332,15 @@ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&ipu_csi0_from_parallel_sensor { + remote-endpoint = <&ov5642_to_ipu_csi0>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vsync-active = <1>; +}; + +&ipu_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_csi0>; +}; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 9b672ed2486d..ed341cfd9d09 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -31,6 +31,7 @@ i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; + ipu0 = &ipu; mmc0 = &esdhc1; mmc1 = &esdhc2; mmc2 = &esdhc3; @@ -71,6 +72,11 @@ ports = <&ipu_di0>, <&ipu_di1>; }; + capture_subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu_csi0>, <&ipu_csi1>; + }; + tzic: tz-interrupt-controller@fffc000 { compatible = "fsl,imx53-tzic", "fsl,tzic"; interrupt-controller; @@ -158,10 +164,16 @@ ipu_csi0: port@0 { reg = <0>; + + ipu_csi0_from_parallel_sensor: endpoint { + }; }; ipu_csi1: port@1 { reg = <1>; + + ipu_csi1_from_parallel_sensor: endpoint { + }; }; ipu_di0: port@2 { diff --git a/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi new file mode 100644 index 000000000000..a864fdbd5f16 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de> + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-kontron-samx6i.dtsi" + +/ { + model = "Kontron SMARC sAMX6i Dual-Lite/Solo"; + compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi new file mode 100644 index 000000000000..2618eccfe50d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de> + */ + +#include "imx6q.dtsi" +#include "imx6qdl-kontron-samx6i.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Kontron SMARC sAMX6i Quad/Dual"; + compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; +}; + +/* Quad/Dual SoMs have 3 chip-select signals */ +&ecspi4 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, + <&gpio3 29 GPIO_ACTIVE_HIGH>, + <&gpio3 25 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl_ecspi4 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + + /* SPI4_IMX_CS2# - connected to internal flash */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 + /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 + >; +}; diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi new file mode 100644 index 000000000000..81c7ebb4b3fb --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi @@ -0,0 +1,815 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017 (C) Priit Laes <plaes@plaes.org> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de> + * + * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + reg_1p0v_s0: regulator-1p0v-s0 { + compatible = "regulator-fixed"; + regulator-name = "V_1V0_S0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_smarc_suppy>; + }; + + reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V35_VCOREDIG_S5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_3p3v_s5>; + }; + + reg_1p8v_s5: regulator-1p8v-s5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_S5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_3p3v_s5>; + }; + + reg_3p3v_s0: regulator-3p3v-s0 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_3p3v_s5>; + }; + + reg_3p3v_s0: regulator-3p3v-s0 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_3p3v_s5>; + }; + + reg_3p3v_s5: regulator-3p3v-s5 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <®_smarc_suppy>; + }; + + reg_smarc_lcdbklt: regulator-smarc-lcdbklt { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdbklt_en>; + regulator-name = "LCD_BKLT_EN"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_smarc_lcdvdd: regulator-smarc-lcdvdd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdvdd_en>; + regulator-name = "LCD_VDD_EN"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_smarc_rtc: regulator-smarc-rtc { + compatible = "regulator-fixed"; + regulator-name = "V_IN_RTC_BATT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* Module supply range can be 3.00V ... 5.25V */ + reg_smarc_suppy: regulator-smarc-supply { + compatible = "regulator-fixed"; + regulator-name = "V_IN_WIDE"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + lcd: lcd { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + + lcd_out: endpoint { + }; + }; + }; + + lcd_backlight: lcd-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + pwm-names = "LCD_BKLT_PWM"; + + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <4>; + + power-supply = <®_smarc_lcdbklt>; + status = "disabled"; + }; + + i2c_intern: i2c-gpio-intern { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio_intern>; + sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_lcd: i2c-gpio-lcd { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabld"; + }; + + i2c_cam: i2c-gpio-cam { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio_cam>; + sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabld"; + }; +}; + +/* I2S0, I2S1 */ +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + + audmux_ssi1 { + fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) | + IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3) + >; + }; + + audmux_adu3 { + fsl,audmux-port = <MX51_AUDMUX_PORT3>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; + + audmux_ssi2 { + fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | + IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TCLKDIR) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) + >; + }; + + audmux_adu4 { + fsl,audmux-port = <MX51_AUDMUX_PORT4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1) + >; + }; +}; + +/* CAN0 */ +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* CAN1 */ +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* SPI1 */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, + <&gpio2 27 GPIO_ACTIVE_HIGH>; +}; + +/* SPI0 */ +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, + <&gpio3 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + /* default boot source: workaround #1 for errata ERR006282 */ + smarc_flash: spi-flash@0 { + compatible = "winbond,w25q16dw", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +/* GBE */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; +}; + +&i2c_intern { + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + reg_v_core_s0: sw1ab { + regulator-name = "V_CORE_S0"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vddsoc_s0: sw1c { + regulator-name = "V_VDDSOC_S0"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p15v_s0: sw2 { + regulator-name = "V_3V15_S0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* sw3a/b is used in dual mode, but driver does not + * support it. Although, there's no need to control + * DDR power - so just leaving dummy entries for sw3a + * and sw3b for now. + */ + sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v_s0: sw4 { + regulator-name = "V_1V8_S0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* Regulator for USB */ + reg_5p0v_s0: swbst { + regulator-name = "V_5V0_S0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + }; + + reg_vsnvs: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* + * Per schematics, of all VGEN's, only VGEN5 has some + * usage ... but even that - over DNI resistor + */ + vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + reg_2p5v_s0: vgen5 { + regulator-name = "V_2V5_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +/* I2C_GP */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; +}; + +/* HDMI_CTRL */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +/* I2C_PM */ +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + smarc_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + + /* AUDIO MCLK */ + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + + /* SPI_IMX_CS2# - connected to internal flash */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 + /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ + >; + }; + + pinctrl_i2c_gpio_cam: i2c-gpiocamgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */ + >; + }; + + pinctrl_i2c_gpio_intern: i2c-gpiointerngrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */ + >; + }; + + pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */ + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1 + + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */ + >; + }; + + pinctrl_lcdbklt_en: lcdbkltengrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1 + >; + }; + + pinctrl_lcdvdd_en: lcdvddengrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 + >; + }; + + pinctrl_mipi_csi: mipi-csigrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */ + >; + }; + + pinctrl_mgmt_gpios: mgmt-gpiosgrp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */ + MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */ + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0 + /* power, oc muxed but not used by the driver */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wdog1: wdog1rp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; + +&mipi_csi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; +}; + +/* LCD_BKLT_PWM */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +®_arm { + vin-supply = <®_v_core_s0>; +}; + +®_pu { + vin-supply = <®_vddsoc_s0>; +}; + +®_soc { + vin-supply = <®_vddsoc_s0>; +}; + +/* SER0 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; +}; + +/* SER1 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* SER2 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; +}; + +/* SER3 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +/* USB0 */ +&usbotg { + /* + * no 'imx6-usb-charger-detection' + * since USB_OTG_CHD_B pin is not wired + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; +}; + +/* USB1/2 via hub */ +&usbh1 { + vbus-supply = <®_5p0v_s0>; +}; + +/* SDIO */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + no-1-8-v; +}; + +/* SDMMC */ +&usdhc4 { + /* Internal eMMC, optional on some boards */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + vmmc-supply = <®_3p3v_s0>; + vqmmc-supply = <®_1p8v_s0>; +}; + +&wdog1 { + /* CPLD is feeded by watchdog (hardwired) */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 185fb17a3500..71ca76a5e4a5 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -745,10 +745,26 @@ vin-supply = <&sw1c_reg>; }; +®_vdd1p1 { + vin-supply = <&vgen5_reg>; +}; + +®_vdd3p0 { + vin-supply = <&sw2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&vgen5_reg>; +}; + &snvs_poweroff { status = "okay"; }; +&snvs_pwrkey { + status = "okay"; +}; + &ssi2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index b3a77bcf00d5..4b801935cad1 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -675,14 +675,14 @@ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_DUMMY>; + clocks = <&clks IMX6QDL_CLK_IPG>; }; wdog2: wdog@20c0000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_DUMMY>; + clocks = <&clks IMX6QDL_CLK_IPG>; status = "disabled"; }; @@ -701,7 +701,7 @@ <0 54 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; - regulator-1p1 { + reg_vdd1p1: regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <1000000>; @@ -716,7 +716,7 @@ anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_vdd3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -731,7 +731,7 @@ anatop-enable-bit = <0>; }; - regulator-2p5 { + reg_vdd2p5: regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2250000>; @@ -841,6 +841,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; linux,keycode = <KEY_POWER>; wakeup-source; + status = "disabled"; }; snvs_lpgpr: snvs-lpgpr { diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index f7a48e4622e1..4829aa682aeb 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -580,6 +580,18 @@ status = "okay"; }; +®_vdd1p1 { + vin-supply = <&sw2_reg>; +}; + +®_vdd3p0 { + vin-supply = <&sw2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&sw2_reg>; +}; + &snvs_poweroff { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 9ddbeea64b72..b36fc012ff06 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -495,7 +495,7 @@ compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_DUMMY>; + clocks = <&clks IMX6SL_CLK_IPG>; status = "disabled"; }; @@ -503,14 +503,14 @@ compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_DUMMY>; + clocks = <&clks IMX6SL_CLK_IPG>; }; wdog2: wdog@20c0000 { compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_DUMMY>; + clocks = <&clks IMX6SL_CLK_IPG>; status = "disabled"; }; @@ -531,7 +531,7 @@ <0 54 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; - regulator-1p1 { + reg_vdd1p1: regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <1000000>; @@ -546,7 +546,7 @@ anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_vdd3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -561,7 +561,7 @@ anatop-enable-bit = <0>; }; - regulator-2p5 { + reg_vdd2p5: regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2250000>; diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 4a31a415f88e..3e1d32fdf4b8 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -265,6 +265,18 @@ status = "okay"; }; +®_3p0 { + vin-supply = <&sw2_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 1b4899f0fcde..b0a77ff70b67 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -568,6 +568,7 @@ regmap = <&snvs>; offset = <0x38>; mask = <0x61>; + status = "disabled"; }; snvs_pwrkey: snvs-powerkey { @@ -576,6 +577,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; linux,keycode = <KEY_POWER>; wakeup-source; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 00c485482301..f1830ed387a5 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -154,3 +154,19 @@ enable-active-high; vin-supply = <®_can_en>; }; + +®_vdd1p1 { + vin-supply = <&vgen6_reg>; +}; + +®_vdd3p0 { + vin-supply = <&sw2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&vgen6_reg>; +}; + +&snvs_pwrkey { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 998e3e13a005..a8ee7087af5a 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -137,7 +137,23 @@ vin-supply = <&sw1a_reg>; }; +®_vdd1p1 { + vin-supply = <&vgen6_reg>; +}; + +®_vdd3p0 { + vin-supply = <&sw2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&vgen6_reg>; +}; + ®_can_stby { /* Transceiver EN/STBY is active low on RevB board */ gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; }; + +&snvs_pwrkey { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts index db0feb9b9f5d..205ea26484e3 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andreas Färber - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts index 5c7a2bb9141c..5817b4985391 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andreas Färber - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -53,3 +16,11 @@ reg = <0x80000000 0x40000000>; }; }; + +&i2c4 { /* Onboard Motion sensors */ + status = "okay"; +}; + +&uart3 { /* Bluetooth */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts index 13dfe2afaba5..96f4d89848a3 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andreas Färber - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -68,3 +31,11 @@ }; }; }; + +&i2c4 { /* Onboard Motion sensors */ + status = "okay"; +}; + +&uart3 { /* Bluetooth */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi index 53b3eac94f0d..25d4aa985a69 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi +++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andreas Färber - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "imx6sx.dtsi" @@ -107,18 +70,6 @@ startup-delay-us = <70000>; enable-active-high; }; - - reg_bt: regulator-bt { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_reg>; - enable-active-high; - gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>; - regulator-name = "bt_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; }; &fec1 { @@ -225,6 +176,20 @@ }; }; +&i2c2 { /* Brick snap in sensors connector */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c4 { /* Onboard Motion sensors */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <100000>; + status = "disabled"; +}; + &iomuxc { pinctrl_bt_reg: btreggrp { fsl,pins = @@ -256,6 +221,18 @@ <MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1>; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = + <MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1>, + <MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1>; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = + <MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x4001b8b1>, + <MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x4001b8b1>; + }; + pinctrl_uart1: uart1grp { fsl,pins = <MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1>, @@ -354,11 +331,19 @@ status = "disabled"; }; -&uart3 { /* Bluetooth */ +&uart3 { /* Bluetooth - only on Extended/Full versions */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; uart-has-rtscts; - status = "okay"; + status = "disabled"; + + bluetooth { + compatible = "ti,wl1831-st"; + enable-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_reg>; + max-speed = <921600>; + }; }; /* Arduino serial */ diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index b16a123990a2..bb25add90f19 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -600,7 +600,7 @@ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - regulator-1p1 { + reg_vdd1p1: regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <1000000>; @@ -615,7 +615,7 @@ anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_vdd3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -630,7 +630,7 @@ anatop-enable-bit = <0>; }; - regulator-2p5 { + reg_vdd2p5: regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2250000>; @@ -738,6 +738,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; linux,keycode = <KEY_POWER>; wakeup-source; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 9207d5d071f1..cbe61b61a212 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -238,6 +238,10 @@ status = "okay"; }; +&snvs_pwrkey { + status = "okay"; +}; + &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts index bc77f26a2f1d..21ddd359d3ed 100644 --- a/arch/arm/boot/dts/imx6ul-geam.dts +++ b/arch/arm/boot/dts/imx6ul-geam.dts @@ -169,7 +169,7 @@ display = <&display0>; status = "okay"; - display0: display { + display0: display0 { bits-per-pixel = <16>; bus-width = <18>; diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi index 213e802bf35c..b26d4f57c655 100644 --- a/arch/arm/boot/dts/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi @@ -161,7 +161,7 @@ display = <&display0>; status = "okay"; - display0: display { + display0: display0 { bits-per-pixel = <16>; bus-width = <18>; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index a7f6d1d58e20..81d4b4925127 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -59,6 +59,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clock-frequency = <696000000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; operating-points = < @@ -649,6 +650,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; linux,keycode = <KEY_POWER>; wakeup-source; + status = "disabled"; }; snvs_lpgpr: snvs-lpgpr { @@ -856,6 +858,8 @@ <&clks IMX6UL_CLK_USDHC1>, <&clks IMX6UL_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-step= <2>; + fsl,tuning-start-tap = <20>; bus-width = <4>; status = "disabled"; }; @@ -869,6 +873,8 @@ <&clks IMX6UL_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-step= <2>; + fsl,tuning-start-tap = <20>; status = "disabled"; }; @@ -962,6 +968,14 @@ status = "disabled"; }; + pxp: pxp@21cc000 { + compatible = "fsl,imx6ul-pxp"; + reg = <0x021cc000 0x4000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_PXP>; + clock-names = "axi"; + }; + qspi: spi@21e0000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index 006690ea98c0..b6147c76d159 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -145,13 +145,20 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; - no-1-8-v; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; disable-wp; wakeup-source; keep-power-in-suspend; vmmc-supply = <®_3v3>; + vqmmc-supply = <®_sd1_vmmc>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 9ad1da159768..d56728f03c35 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -545,6 +545,12 @@ >; }; + pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 + >; + }; + pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 22e4a307fa59..b7e67d121322 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -12,6 +12,7 @@ /delete-node/ &crypto; &cpu0 { + clock-frequency = <900000000>; operating-points = < /* kHz uV */ 900000 1275000 @@ -34,6 +35,12 @@ compatible = "fsl,imx6ull-ocotp", "syscon"; }; +&pxp { + compatible = "fsl,imx6ull-pxp"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; +}; + &usdhc1 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; }; diff --git a/arch/arm/boot/dts/imx7d-meerkat96.dts b/arch/arm/boot/dts/imx7d-meerkat96.dts new file mode 100644 index 000000000000..5339210b63d0 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-meerkat96.dts @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Linaro Ltd. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "96Boards Meerkat96 Board"; + compatible = "novtech,imx7d-meerkat96", "fsl,imx7d"; + + chosen { + stdout-path = &uart6; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512MB */ + }; + + reg_wlreg_on: regulator-wlreg-on { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlreg_on>; + regulator-name = "wlreg_on"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "green:user1"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user4"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led5 { + label = "yellow:wlan"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led6 { + label = "blue:bt"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7 &pinctrl_bt_gpios>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + device-wakeup-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + keep-power-in-suspend; + tuning-step = <2>; + vmmc-supply = <®_3p3v>; + no-1-8-v; + broken-cd; + status = "okay"; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + no-1-8-v; + no-mmc; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_wlreg_on>; + vqmmc-supply =<®_3p3v>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_irq>; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_bt_gpios: btgpiosgrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x59 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x1f + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59 + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX7D_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x79 + MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x79 + MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x79 + MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x79 + MX7D_PAD_SD1_WP__UART6_DCE_TX 0x79 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x79 + MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x79 + MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x79 + MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x0D + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + >; + }; + + pinctrl_wlan_irq: wlanirqgrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19 + >; + }; + + pinctrl_wlreg_on: wlregongrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x19 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 202922ed3754..869efbc4af42 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -263,8 +263,8 @@ }; sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -379,6 +379,18 @@ status = "okay"; }; +®_1p0d { + vin-supply = <&sw2_reg>; +}; + +®_1p2 { + vin-supply = <&sw2_reg>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts index 3e467a94e8a6..4a78ddc7513d 100644 --- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts @@ -16,7 +16,7 @@ compatible = "zii,imx7d-rpu2", "fsl,imx7d"; chosen { - stdout-path = &uart1; + stdout-path = &uart2; }; cs2000_ref: oscillator { @@ -775,13 +775,6 @@ >; }; - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f - MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f - >; - }; - pinctrl_i2c2: i2c2grp { fsl,pins = < MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f @@ -789,13 +782,6 @@ >; }; - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f - MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f - >; - }; - pinctrl_i2c3: i2c3grp { fsl,pins = < MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index f33b560821b8..42528d2812a2 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -12,6 +12,8 @@ clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; cpu1: cpu@1 { @@ -39,15 +41,23 @@ opp-792000000 { opp-hz = /bits/ 64 <792000000>; - opp-microvolt = <975000>; + opp-microvolt = <1000000>; clock-latency-ns = <150000>; + opp-supported-hw = <0xf>, <0xf>; }; opp-996000000 { opp-hz = /bits/ 64 <996000000>; - opp-microvolt = <1075000>; + opp-microvolt = <1100000>; clock-latency-ns = <150000>; - opp-suspend; + opp-supported-hw = <0xc>, <0xf>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0x8>, <0xf>; }; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 106711d2c01b..c1a4fff5ceda 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -117,7 +117,7 @@ * non-configurable replicators don't show up on the * AMBA bus. As such no need to add "arm,primecell" */ - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; out-ports { #address-cells = <1>; @@ -175,7 +175,7 @@ ranges; funnel@30041000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x30041000 0x1000>; clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; @@ -217,7 +217,7 @@ }; funnel@30083000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x30083000 0x1000>; clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; @@ -551,6 +551,10 @@ tempmon_temp_grade: temp-grade@10 { reg = <0x10 0x4>; }; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 0x4>; + }; }; anatop: anatop@30360000 { @@ -609,6 +613,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; linux,keycode = <KEY_POWER>; wakeup-source; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index a09026a6d22e..4245b33bb451 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -22,6 +22,25 @@ reg = <0x60000000 0x40000000>; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&tpm4 1 50000 0>; + brightness-levels = <0 20 25 30 35 40 100>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_vsd_3v3: regulator-vsd-3v3 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -40,6 +59,23 @@ status = "okay"; }; +&tpm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + &usdhc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc0>; @@ -57,6 +93,25 @@ bias-pull-up; }; + pinctrl_pwm0: pwm0grp { + fsl,pins = < + IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 + >; + }; + + pinctrl_usbotg1_vbus: otg1vbusgrp { + fsl,pins = < + IMX7ULP_PAD_PTC0__PTC0 0x20000 + >; + }; + + pinctrl_usbotg1_id: otg1idgrp { + fsl,pins = < + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 + IMX7ULP_PAD_PTC16__USB1_OC2 0x10003 + >; + }; + pinctrl_usdhc0: usdhc0grp { fsl,pins = < IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index e20483714be5..992747a57442 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -30,6 +30,7 @@ serial1 = &lpuart5; serial2 = &lpuart6; serial3 = &lpuart7; + usbphy0 = &usbphy1; }; cpus { @@ -147,6 +148,16 @@ status = "disabled"; }; + tpm4: pwm@40250000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x40250000 0x1000>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + tpm5: tpm@40260000 { compatible = "fsl,imx7ulp-tpm"; reg = <0x40260000 0x1000>; @@ -156,6 +167,33 @@ clock-names = "ipg", "per"; }; + usbotg1: usb@40330000 { + compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; + reg = <0x40330000 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc2 IMX7ULP_CLK_USB0>; + phys = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc1: usbmisc@40330200 { + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x40330200 0x200>; + }; + + usbphy1: usb-phy@0x40350000 { + compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; + reg = <0x40350000 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; + #phy-cells = <0>; + }; + usdhc0: mmc@40370000 { compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; reg = <0x40370000 0x10000>; diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 1612a869a4f7..602f74d2c758 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -62,6 +62,9 @@ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x24000000 0x02000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; fpga { diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index e2b1ab9b56e5..ae75a1db3d9a 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -87,7 +87,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1 1800000 0>; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts new file mode 100644 index 000000000000..07ac99b9cda6 --- /dev/null +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +/* + * There are two types of 4.3" LCD, Type 15 and Type 28. + * By default, type 15 was used. This device tree file + * uses the timing for the type 28 LCD + */ + +#include "logicpd-torpedo-37xx-devkit.dts" + +&lcd0 { + + label = "28"; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <3>; + vfront-porch = <2>; + vsync-len = <11>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; +}; diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts new file mode 100644 index 000000000000..5b7689094b70 --- /dev/null +++ b/arch/arm/boot/dts/ls1021a-tsn.dts @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright 2016-2018 NXP Semiconductors + * Copyright 2019 Vladimir Oltean <olteanv@gmail.com> + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "NXP LS1021A-TSN Board"; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_vdda_codec: regulator-3V3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vddio_codec: regulator-2V5 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + /* ADG704BRMZ 1:4 SPI mux/demux */ + sja1105: ethernet-switch@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,sja1105t"; + /* 12 MHz */ + spi-max-frequency = <12000000>; + /* Sample data on trailing clock edge */ + spi-cpha; + /* SPI controller settings for SJA1105 timing requirements */ + fsl,spi-cs-sck-delay = <1000>; + fsl,spi-sck-cs-delay = <1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + /* ETH5 written on chassis */ + label = "swp5"; + phy-handle = <&rgmii_phy6>; + phy-mode = "rgmii-id"; + reg = <0>; + }; + + port@1 { + /* ETH2 written on chassis */ + label = "swp2"; + phy-handle = <&rgmii_phy3>; + phy-mode = "rgmii-id"; + reg = <1>; + }; + + port@2 { + /* ETH3 written on chassis */ + label = "swp3"; + phy-handle = <&rgmii_phy4>; + phy-mode = "rgmii-id"; + reg = <2>; + }; + + port@3 { + /* ETH4 written on chassis */ + label = "swp4"; + phy-handle = <&rgmii_phy5>; + phy-mode = "rgmii-id"; + reg = <3>; + }; + + port@4 { + /* Internal port connected to eth2 */ + ethernet = <&enet2>; + phy-mode = "rgmii"; + reg = <4>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&enet0 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy2>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy1>; + phy-mode = "sgmii"; + status = "okay"; +}; + +/* RGMII delays added via PCB traces */ +&enet2 { + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&esdhc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + /* 3 axis accelerometer */ + accelerometer@1e { + compatible = "fsl,fxls8471"; + position = <0>; + reg = <0x1e>; + }; + + /* Audio codec (SAI2) */ + audio-codec@2a { + compatible = "fsl,sgtl5000"; + VDDIO-supply = <®_vddio_codec>; + VDDA-supply = <®_vdda_codec>; + #sound-dai-cells = <0>; + clocks = <&sys_mclk>; + reg = <0x2a>; + }; + + /* Current sensing circuit for 1V VDDCORE PMIC rail */ + current-sensor@44 { + compatible = "ti,ina220"; + shunt-resistor = <1000>; + reg = <0x44>; + }; + + /* Current sensing circuit for 12V VCC rail */ + current-sensor@45 { + compatible = "ti,ina220"; + shunt-resistor = <1000>; + reg = <0x45>; + }; + + /* Thermal monitor - case */ + temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + /* Thermal monitor - chip */ + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + }; + + /* Unsupported devices: + * - FXAS21002C Gyroscope at 0x20 + * - TI ADS7924 4-channel ADC at 0x49 + */ +}; + +&ifc { + status = "disabled"; +}; + +&lpuart0 { + status = "okay"; +}; + +&lpuart3 { + status = "okay"; +}; + +&mdio0 { + /* AR8031 */ + sgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + /* AR8031 */ + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + /* BCM5464 quad PHY */ + rgmii_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + rgmii_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + + rgmii_phy5: ethernet-phy@5 { + reg = <0x5>; + }; + + rgmii_phy6: ethernet-phy@6 { + reg = <0x6>; + }; + + /* SGMII PCS for enet0 */ + tbi0: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&mdio1 { + /* SGMII PCS for enet1 */ + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&qspi { + status = "okay"; + + flash@0 { + /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */ + compatible = "jedec,spi-nor", "s25fl256s1", "s25fl512s"; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "RCW"; + reg = <0x0 0x40000>; + }; + + partition@40000 { + label = "U-Boot"; + reg = <0x40000 0x300000>; + }; + + partition@340000 { + label = "U-Boot Env"; + reg = <0x340000 0x100000>; + }; + }; + }; +}; + +&sai2 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 8841783aceec..c4447f6c8b2c 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -1,48 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2014 Carlo Caione <carlo@caione.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts index 997e69c5963e..98e1c94c0261 100644 --- a/arch/arm/boot/dts/meson6-atv1200.dts +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -1,48 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2014 Carlo Caione <carlo@caione.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index 65585255910a..2d31b7ce3f8c 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -1,48 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2014 Carlo Caione <carlo@caione.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "meson.dtsi" diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts index 8686abd5de7f..61ec929ab86e 100644 --- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 40c11b6b217a..5a7e3e5caebe 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -1,46 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2014 Carlo Caione <carlo@caione.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/clock/meson8b-clkc.h> @@ -228,6 +188,28 @@ }; }; + mmcbus: bus@c8000000 { + compatible = "simple-bus"; + reg = <0xc8000000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8000000 0x8000>; + + dmcbus: bus@6000 { + compatible = "simple-bus"; + reg = <0x6000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x400>; + + canvas: video-lut@20 { + compatible = "amlogic,meson8-canvas", + "amlogic,canvas"; + reg = <0x20 0x14>; + }; + }; + }; + apb: bus@d0000000 { compatible = "simple-bus"; reg = <0xd0000000 0x200000>; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 9bf4249cb60d..96d239d8334e 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -234,10 +234,6 @@ phy-handle = <ð_phy0>; phy-mode = "rmii"; - snps,reset-gpio = <&gpio GPIOH_4 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; @@ -246,6 +242,11 @@ eth_phy0: ethernet-phy@0 { /* IC Plus IP101A/G (0x02430c54) */ reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; + icplus,select-interrupt; interrupt-parent = <&gpio_intc>; /* GPIOH_3 */ diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts index 08ddd7fb0bf8..bb27b34eb346 100644 --- a/arch/arm/boot/dts/meson8b-mxq.dts +++ b/arch/arm/boot/dts/meson8b-mxq.dts @@ -1,50 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2015 Endless Mobile, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; + +#include <dt-bindings/gpio/gpio.h> + #include "meson8b.dtsi" / { @@ -63,6 +26,127 @@ device_type = "memory"; reg = <0x40000000 0x40000000>; }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + + vcck: regulator-vcck { + compatible = "pwm-regulator"; + + regulator-name = "VCCK"; + regulator-min-microvolt = <860000>; + regulator-max-microvolt = <1140000>; + + pwms = <&pwm_cd 0 1148 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_5v>; + }; + + vcc_5v: regulator-vcc5v { + compatible = "regulator-fixed"; + + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&cpu0 { + cpu-supply = <&vcck>; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_rmii_pins>; + pinctrl-names = "default"; + + phy-handle = <ð_phy0>; + phy-mode = "rmii"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + /* IC Plus IP101A/G (0x02430c54) */ + reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; + + icplus,select-interrupt; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdio { + status = "okay"; + + pinctrl-0 = <&sd_b_pins>; + pinctrl-names = "default"; + + /* SD card */ + sd_card_slot: slot@1 { + compatible = "mmc-slot"; + reg = <1>; + status = "okay"; + + bus-width = <4>; + no-sdio; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vcc_3v3>; + }; +}; + +&pwm_cd { + status = "okay"; + pinctrl-0 = <&pwm_c1_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_XTAL>; + clock-names = "clkin0"; }; &uart_AO { @@ -70,3 +154,19 @@ pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + +&usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index f3ad9397f670..86c4614e0a38 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -1,47 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2015 Endless Mobile, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -216,10 +176,6 @@ ðmac { status = "okay"; - snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; @@ -235,6 +191,11 @@ /* Realtek RTL8211F (0x001cc916) */ eth_phy: ethernet-phy@0 { reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; /* GPIOH_3 */ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index ec67f49116d9..fba2c70c2fda 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -1,47 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2015 Endless Mobile, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/clock/meson8b-clkc.h> @@ -205,6 +165,28 @@ }; }; + mmcbus: bus@c8000000 { + compatible = "simple-bus"; + reg = <0xc8000000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8000000 0x8000>; + + dmcbus: bus@6000 { + compatible = "simple-bus"; + reg = <0x6000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x400>; + + canvas: video-lut@48 { + compatible = "amlogic,meson8b-canvas", + "amlogic,canvas"; + reg = <0x48 0x14>; + }; + }; + }; + apb: bus@d0000000 { compatible = "simple-bus"; reg = <0xd0000000 0x200000>; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index 29d830ae4bf4..d54477b1001c 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -73,10 +73,6 @@ amlogic,tx-delay-ns = <4>; - snps,reset-gpio = <&gpio GPIOH_4 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; @@ -85,6 +81,10 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; }; }; }; @@ -114,8 +114,9 @@ regulator-always-on; }; - DCDC2 { - regulator-name = "VDDAO"; + vddee: DCDC2 { + /* the output is also used as VDDAO */ + regulator-name = "VDD_EE"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; regulator-boot-on; @@ -189,6 +190,10 @@ }; }; +&mali { + mali-supply = <&vddee>; +}; + &saradc { status = "okay"; vref-supply = <&vddio_ao1v8>; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index bb87b251e16d..5bde7f502007 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -14,6 +14,16 @@ compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc"; }; +&dmcbus { + /* the offset of the canvas registers has changed compared to Meson8 */ + /delete-node/ video-lut@20; + + canvas: video-lut@48 { + compatible = "amlogic,meson8m2-canvas", "amlogic,canvas"; + reg = <0x48 0x14>; + }; +}; + ðmac { compatible = "amlogic,meson8m2-dwmac", "snps,dwmac"; reg = <0xc9410000 0x10000 diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 5059ecac4478..bea05dc4ef0f 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -1371,7 +1371,6 @@ target-module@20000 { /* 0x48020000, ap 3 06.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart3"; reg = <0x20050 0x4>, <0x20054 0x4>, <0x20058 0x4>; @@ -1728,7 +1727,6 @@ target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart1"; reg = <0x6a050 0x4>, <0x6a054 0x4>, <0x6a058 0x4>; @@ -1758,7 +1756,6 @@ target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart2"; reg = <0x6c050 0x4>, <0x6c054 0x4>, <0x6c058 0x4>; @@ -1788,7 +1785,6 @@ target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart4"; reg = <0x6e050 0x4>, <0x6e054 0x4>, <0x6e058 0x4>; @@ -2107,7 +2103,6 @@ target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc1"; reg = <0x9c000 0x4>, <0x9c010 0x4>; reg-names = "rev", "sysc"; @@ -2175,7 +2170,6 @@ target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc3"; reg = <0xad000 0x4>, <0xad010 0x4>; reg-names = "rev", "sysc"; @@ -2241,7 +2235,6 @@ target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc2"; reg = <0xb4000 0x4>, <0xb4010 0x4>; reg-names = "rev", "sysc"; @@ -2336,7 +2329,6 @@ target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc4"; reg = <0xd1000 0x4>, <0xd1010 0x4>; reg-names = "rev", "sysc"; @@ -2369,7 +2361,6 @@ target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc5"; reg = <0xd5000 0x4>, <0xd5010 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi index 8ac24e3c8513..8a6721d436bd 100644 --- a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi +++ b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi @@ -319,9 +319,9 @@ gpio_keys_pins: gpio-keys-pins { pinctrl-single,pins = < - MFP_PIN_PXA300(14) MFP_AF0 /* SCK */ - MFP_PIN_PXA300(115) MFP_AF0 /* MOSI */ - MFP_PIN_PXA300(119) MFP_AF0 /* MISO */ + MFP_PIN_PXA300(14) MFP_AF0 /* on-off */ + MFP_PIN_PXA300(115) MFP_AF0 /* rescue boot */ + MFP_PIN_PXA300(119) MFP_AF0 /* setup */ >; pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); }; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-controller.dts b/arch/arm/boot/dts/pxa300-raumfeld-controller.dts index 65d825091f0d..12b15945ac6d 100644 --- a/arch/arm/boot/dts/pxa300-raumfeld-controller.dts +++ b/arch/arm/boot/dts/pxa300-raumfeld-controller.dts @@ -41,6 +41,8 @@ }; charger: charger { + pinctrl-names = "default"; + pinctrl-0 = <&charger_pins>; compatible = "gpio-charger"; charger-type = "mains"; gpios = <&gpio 101 GPIO_ACTIVE_LOW>; @@ -109,9 +111,10 @@ }; &keys { + pinctrl-0 = <&gpio_keys_pins &dock_detect_pins>; dock-detect { label = "dock detect"; - gpios = <&gpio 116 GPIO_ACTIVE_HIGH>; + gpios = <&gpio 116 GPIO_ACTIVE_LOW>; linux,code = <KEY_F5>; }; }; @@ -236,6 +239,22 @@ pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); }; + charger_pins: charger_pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(31) MFP_AF0 /* PEN2 */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); + pinctrl-single,bias-pullup = MPF_PULL_UP; + }; + + dock_detect_pins: dock_detect_pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(116) MFP_AF0 /* DOCK_DETECT */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); + pinctrl-single,bias-pullup = MPF_PULL_UP; + }; + lcdc_pins: lcdc-pins { pinctrl-single,pins = < MFP_PIN_PXA300(54) MFP_AF1 /* LDD_0 */ diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts b/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts index 5f9e37585a28..a70560a8ea92 100644 --- a/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts +++ b/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts @@ -116,6 +116,9 @@ st,invalid-input-detect-mute; /* 2 (half-bridge) and 1 (full-bridge) on-board power */ st,output-conf = /bits/ 8 <0x1>; + st,ch1-output-mapping = /bits/ 8 <0>; + st,ch2-output-mapping = /bits/ 8 <1>; + st,ch3-output-mapping = /bits/ 8 <2>; st,needs_esd_watchdog; }; }; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index e1e607f53ce6..c237a0e4b12a 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -71,6 +71,14 @@ #define MFP_DS13X < (0x7 << 10) MFP_DSMSK > /* + * MFP bias pull mode for pins. + * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP; + */ +#define MPF_PULL_MSK (0x7 << 13) +#define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK > +#define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK > + +/* * MFP low power mode for pins. * Example of use: * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 65975df6a8c3..8b79b4112ee1 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1603,7 +1603,7 @@ }; replicator { - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; @@ -1636,7 +1636,7 @@ }; funnel@1a04000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x1a04000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index 643c57f84818..bf402ae39226 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -50,6 +50,12 @@ }; }; + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + vcc-supply = <&pm8941_l18>; + }; + smd { rpm { rpm_requests { diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index b3b04736a159..3487daf98e81 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -280,6 +280,16 @@ }; }; + i2c2_pins: i2c2 { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + + drive-strength = <2>; + bias-disable; + }; + }; + i2c3_pins: i2c3 { mux { pins = "gpio10", "gpio11"; @@ -289,6 +299,16 @@ }; }; + i2c11_pins: i2c11 { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + + drive-strength = <2>; + bias-disable; + }; + }; + i2c12_pins: i2c12 { mux { pins = "gpio87", "gpio88"; @@ -306,6 +326,35 @@ input-enable; }; }; + + touch_pin: touch { + int { + pins = "gpio5"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + input-enable; + }; + + reset { + pins = "gpio8"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + panel_pin: panel { + te { + pins = "gpio12"; + function = "mdp_vsync"; + + drive-strength = <2>; + bias-disable; + }; + }; }; sdhci@f9824900 { @@ -369,6 +418,30 @@ }; }; + i2c@f9967000 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c11_pins>; + clock-frequency = <355000>; + qcom,src-freq = <50000000>; + + led-controller@38 { + compatible = "ti,lm3630a"; + status = "ok"; + reg = <0x38>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0 1>; + label = "lcd-backlight"; + default-brightness = <200>; + }; + }; + }; + i2c@f9968000 { status = "ok"; pinctrl-names = "default"; @@ -424,6 +497,41 @@ }; }; + i2c@f9924000 { + status = "ok"; + + clock-frequency = <355000>; + qcom,src-freq = <50000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + synaptics@70 { + compatible = "syna,rmi4-i2c"; + reg = <0x70>; + + interrupts-extended = <&msmgpio 5 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; + }; + i2c@f9925000 { status = "ok"; pinctrl-names = "default"; @@ -466,6 +574,54 @@ }; }; }; + + mdss@fd900000 { + status = "ok"; + + mdp@fd900000 { + status = "ok"; + }; + + dsi@fd922800 { + status = "ok"; + + vdda-supply = <&pm8941_l2>; + vdd-supply = <&pm8941_lvs3>; + vddio-supply = <&pm8941_l12>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel: panel@0 { + reg = <0>; + compatible = "lg,acx467akm-7"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_pin>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + dsi-phy@fd922a00 { + status = "ok"; + + vddio-supply = <&pm8941_l12>; + }; + }; }; &spmi_bus { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 45b5c8ef0374..369e58f64145 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> +#include <dt-bindings/clock/qcom,mmcc-msm8974.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/reset/qcom,gcc-msm8974.h> #include <dt-bindings/gpio/gpio.h> @@ -897,7 +898,7 @@ }; funnel@fc31b000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0xfc31b000 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; @@ -931,7 +932,7 @@ }; funnel@fc31a000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0xfc31a000 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; @@ -969,7 +970,7 @@ }; funnel@fc345000 { /* KPSS funnel only 4 inputs are used */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0xfc345000 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; @@ -1085,6 +1086,137 @@ }; }; }; + + mdss: mdss@fd900000 { + status = "disabled"; + + compatible = "qcom,mdss"; + reg = <0xfd900000 0x100>, + <0xfd924000 0x1000>; + reg-names = "mdss_phys", + "vbif_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: mdp@fd900000 { + status = "disabled"; + + compatible = "qcom,mdp5"; + reg = <0xfd900100 0x22000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0 0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: dsi@fd922800 { + status = "disabled"; + + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xfd922800 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi_phy0 0>, + <&dsi_phy0 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&dsi_phy0>; + phy-names = "dsi-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi_phy0: dsi-phy@fd922a00 { + status = "disabled"; + + compatible = "qcom,dsi-phy-28nm-hpm"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x280>, + <0xfd922d80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + qcom,dsi-phy-index = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>; + clock-names = "iface"; + }; + }; }; smd { diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 474baa0c7cfc..07d611d2b7b5 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index ff24301dc1be..99acfe4fe11a 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r7s72100.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/r7s72100-pinctrl.h> / { @@ -28,6 +29,37 @@ reg = <0x08000000 0x02000000>; }; + keyboard { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + + key-1 { + interrupt-parent = <&irqc>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_1>; + label = "SW1"; + wakeup-source; + }; + + key-2 { + interrupt-parent = <&irqc>; + interrupts = <2 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_2>; + label = "SW2"; + wakeup-source; + }; + + key-3 { + interrupt-parent = <&irqc>; + interrupts = <5 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_3>; + label = "SW3"; + wakeup-source; + }; + }; + lbsc { #address-cells = <1>; #size-cells = <1>; @@ -101,6 +133,12 @@ <RZA1_PINMUX(1, 7, 1)>; /* RIIC3SDA */ }; + keyboard_pins: keyboard { + pinmux = <RZA1_PINMUX(1, 9, 3)>, /* IRQ3 */ + <RZA1_PINMUX(1, 8, 3)>, /* IRQ2 */ + <RZA1_PINMUX(1, 11, 3)>; /* IRQ5 */ + }; + /* Serial Console */ scif2_pins: serial2 { pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */ diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 2211f88ede2a..d03dcd919d6f 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -670,6 +670,25 @@ status = "disabled"; }; + irqc: interrupt-controller@fcfef800 { + compatible = "renesas,r7s72100-irqc", + "renesas,rza1-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0xfcfef800 0x6>; + interrupt-map = + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <7 0>; + }; + mtu2: timer@fcff0000 { compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; reg = <0xfcff0000 0x400>; diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts index 991e09de1219..d062d02865e7 100644 --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "r7s9210.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/r7s9210-pinctrl.h> / { @@ -17,6 +18,8 @@ aliases { serial0 = &scif4; + ethernet0 = ðer0; + ethernet1 = ðer1; }; chosen { @@ -24,9 +27,19 @@ stdout-path = "serial0:115200n8"; }; - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x00800000>; /* HyperRAM */ + keyboard { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + + key-3 { + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_3>; + label = "SW3"; + wakeup-source; + }; }; lbsc { @@ -44,6 +57,41 @@ gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; }; }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x00800000>; /* HyperRAM */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +ðer0 { + pinctrl-names = "default"; + pinctrl-0 = <ð0_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ðer1 { + pinctrl-names = "default"; + pinctrl-0 = <ð1_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + reg = <0>; + }; }; /* EXTAL */ @@ -51,26 +99,80 @@ clock-frequency = <24000000>; /* 24MHz */ }; -/* RTC_X1 */ -&rtc_x1_clk { - clock-frequency = <32768>; +/* High resolution System tick timers */ +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; }; &pinctrl { + eth0_pins: eth0 { + pinmux = <RZA2_PINMUX(PORTE, 0, 7)>, /* REF50CK0 */ + <RZA2_PINMUX(PORT6, 1, 7)>, /* RMMI0_TXDEN */ + <RZA2_PINMUX(PORT6, 2, 7)>, /* RMII0_TXD0 */ + <RZA2_PINMUX(PORT6, 3, 7)>, /* RMII0_TXD1 */ + <RZA2_PINMUX(PORTE, 4, 7)>, /* RMII0_CRSDV */ + <RZA2_PINMUX(PORTE, 1, 7)>, /* RMII0_RXD0 */ + <RZA2_PINMUX(PORTE, 2, 7)>, /* RMII0_RXD1 */ + <RZA2_PINMUX(PORTE, 3, 7)>, /* RMII0_RXER */ + <RZA2_PINMUX(PORTE, 5, 1)>, /* ET0_MDC */ + <RZA2_PINMUX(PORTE, 6, 1)>, /* ET0_MDIO */ + <RZA2_PINMUX(PORTL, 0, 5)>; /* IRQ4 */ + }; + + eth1_pins: eth1 { + pinmux = <RZA2_PINMUX(PORTK, 3, 7)>, /* REF50CK1 */ + <RZA2_PINMUX(PORTK, 0, 7)>, /* RMMI1_TXDEN */ + <RZA2_PINMUX(PORTK, 1, 7)>, /* RMII1_TXD0 */ + <RZA2_PINMUX(PORTK, 2, 7)>, /* RMII1_TXD1 */ + <RZA2_PINMUX(PORT3, 2, 7)>, /* RMII1_CRSDV */ + <RZA2_PINMUX(PORTK, 4, 7)>, /* RMII1_RXD0 */ + <RZA2_PINMUX(PORT3, 5, 7)>, /* RMII1_RXD1 */ + <RZA2_PINMUX(PORT3, 1, 7)>, /* RMII1_RXER */ + <RZA2_PINMUX(PORT3, 3, 1)>, /* ET1_MDC */ + <RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */ + <RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */ + }; + + keyboard_pins: keyboard { + pinmux = <RZA2_PINMUX(PORTJ, 1, 6)>; /* IRQ0 */ + }; + /* Serial Console */ scif4_pins: serial4 { pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */ <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */ }; -}; -/* High resolution System tick timers */ -&ostm0 { - status = "okay"; + sdhi0_pins: sdhi0 { + pinmux = <RZA2_PINMUX(PORT5, 0, 3)>, /* SD0_CD */ + <RZA2_PINMUX(PORT5, 1, 3)>; /* SD0_WP */ + }; + + sdhi1_pins: sdhi1 { + pinmux = <RZA2_PINMUX(PORT5, 4, 3)>, /* SD1_CD */ + <RZA2_PINMUX(PORT5, 5, 3)>; /* SD1_WP */ + }; + + usb0_pins: usb0 { + pinmux = <RZA2_PINMUX(PORT5, 2, 3)>, /* VBUSIN0 */ + <RZA2_PINMUX(PORTC, 6, 1)>, /* VBUSEN0 */ + <RZA2_PINMUX(PORTC, 7, 1)>; /* OVRCUR0 */ + }; + + usb1_pins: usb1 { + pinmux = <RZA2_PINMUX(PORTC, 0, 1)>, /* VBUSIN1 */ + <RZA2_PINMUX(PORTC, 5, 1)>, /* VBUSEN1 */ + <RZA2_PINMUX(PORT7, 5, 5)>; /* OVRCUR1 */ + }; }; -&ostm1 { - status = "okay"; +/* RTC_X1 */ +&rtc_x1_clk { + clock-frequency = <32768>; }; /* Serial Console */ @@ -80,3 +182,38 @@ status = "okay"; }; + +&sdhi0 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhi0_pins>; + bus-width = <4>; + status = "okay"; +}; + +&sdhi1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhi1_pins>; + bus-width = <4>; + status = "okay"; +}; + +/* USB-0 as Host */ +&usb2_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + dr_mode = "host"; /* Requires JP3 to be fitted */ + status = "okay"; +}; + +/* USB-1 as Host */ +&usb2_phy1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; + dr_mode = "host"; + status = "okay"; +}; + +/* USB_X1 */ +&usb_x1_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi index 22baa96f5974..72b79770e336 100644 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -30,6 +30,13 @@ clock-frequency = <0>; }; + usb_x1_clk: usb_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value (48000000) must be set by board */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -146,6 +153,152 @@ status = "disabled"; }; + spi0: spi@e800c800 { + compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; + reg = <0xe800c800 0x24>; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD 97>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@e800d000 { + compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; + reg = <0xe800d000 0x24>; + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD 96>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@e800d800 { + compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; + reg = <0xe800d800 0x24>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD 95>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ether0: ethernet@e8204000 { + compatible = "renesas,ether-r7s9210"; + reg = <0xe8204000 0x200>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 65>; + power-domains = <&cpg>; + + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ether1: ethernet@e8204200 { + compatible = "renesas,ether-r7s9210"; + reg = <0xe8204200 0x200>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 64>; + power-domains = <&cpg>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@e803a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; + reg = <0xe803a000 0x44>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 87>; + power-domains = <&cpg>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@e803a400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; + reg = <0xe803a400 0x44>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 86>; + power-domains = <&cpg>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@e803a800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; + reg = <0xe803a800 0x44>; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 85>; + power-domains = <&cpg>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@e803ac00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; + reg = <0xe803ac00 0x44>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 84>; + power-domains = <&cpg>; + clock-frequency = <100000>; + status = "disabled"; + }; + ostm0: timer@e803b000 { compatible = "renesas,r7s9210-ostm", "renesas,ostm"; reg = <0xe803b000 0x30>; @@ -176,6 +329,120 @@ status = "disabled"; }; + ohci0: usb@e8218000 { + compatible = "generic-ohci"; + reg = <0xe8218000 0x100>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 61>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@e8218100 { + compatible = "generic-ehci"; + reg = <0xe8218100 0x100>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 61>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@e8218200 { + compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; + reg = <0xe8218200 0x700>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>; + clock-names = "fck", "usb_x1"; + power-domains = <&cpg>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbhs0: usb@e8219000 { + compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; + reg = <0xe8219000 0x724>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 61>; + renesas,buswait = <7>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@e821a000 { + compatible = "generic-ohci"; + reg = <0xe821a000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 60>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@e821a100 { + compatible = "generic-ehci"; + reg = <0xe821a100 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 60>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@e821a200 { + compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; + reg = <0xe821a200 0x700>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>; + clock-names = "fck", "usb_x1"; + power-domains = <&cpg>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbhs1: usb@e821b000 { + compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; + reg = <0xe821b000 0x724>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 60>; + renesas,buswait = <7>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi0: sd@e8228000 { + compatible = "renesas,sdhi-r7s9210"; + reg = <0xe8228000 0x8c0>; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>; + clock-names = "core", "cd"; + power-domains = <&cpg>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sd@e822a000 { + compatible = "renesas,sdhi-r7s9210"; + reg = <0xe822a000 0x8c0>; + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>; + clock-names = "core", "cd"; + power-domains = <&cpg>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + gic: interrupt-controller@e8221000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -206,6 +473,25 @@ reg = <0xfcfe8004 4>; }; + irqc: interrupt-controller@fcfef800 { + compatible = "renesas,r7s9210-irqc", + "renesas,rza1-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0xfcfef800 0x6>; + interrupt-map = + <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <7 0>; + }; + pinctrl: pin-controller@fcffe000 { compatible = "renesas,r7s9210-pinctrl"; reg = <0xfcffe000 0x1000>; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index f70f4a3e5c43..a5351ddbf506 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -19,7 +19,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 32757caa2584..758360a2edc3 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -21,7 +21,7 @@ }; chosen { - bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=dhcp rw"; + bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=on rw"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts index ca0e0fc9b246..807e7d0d6b62 100644 --- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -17,7 +17,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index 1db220cfc1a1..ce6603b0994b 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -42,7 +42,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial3:115200n8"; }; diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts index 655b10bb42d5..db72a801abe5 100644 --- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -17,7 +17,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 2840eb0d6fd4..450efe923008 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -18,7 +18,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial1:115200n8"; }; @@ -63,7 +63,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1 1800000 0>; diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index 0b49956069fc..6c7b07c4b9d3 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -25,7 +25,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index d4bee1ec9044..c755f0b8fd0d 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -21,7 +21,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 7b9508e83d46..83cc619861b2 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -56,7 +56,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; @@ -423,6 +423,8 @@ */ i2cpwr: i2c-13 { compatible = "i2c-demux-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; i2c-parent = <&iic3>, <&i2c3>; i2c-bus-name = "i2c-pwr"; #address-cells = <1>; @@ -615,6 +617,11 @@ function = "iic3"; }; + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + hsusb_pins: hsusb { groups = "usb0_ovc_vbus"; function = "usb0"; diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts index 7a7d3b84d1a6..a315ba749aa4 100644 --- a/arch/arm/boot/dts/r8a7790-stout.dts +++ b/arch/arm/boot/dts/r8a7790-stout.dts @@ -19,7 +19,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; @@ -179,6 +179,11 @@ function = "iic3"; }; + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + usb0_pins: usb0 { groups = "usb0"; function = "usb0"; @@ -317,7 +322,7 @@ &iic3 { pinctrl-names = "default"; - pinctrl-0 = <&iic3_pins>; + pinctrl-0 = <&iic3_pins &pmic_irq_pins>; status = "okay"; pmic@58 { diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index e6580aa0cea3..af6bd8fcd5a4 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -56,7 +56,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; @@ -540,6 +540,11 @@ function = "intc"; }; + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -776,6 +781,8 @@ }; &i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; status = "okay"; clock-frequency = <100000>; diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index fefdf8238bbe..d6cf16aac14d 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -31,7 +31,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; @@ -228,6 +228,11 @@ function = "intc"; }; + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -373,6 +378,8 @@ }; &i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; status = "okay"; clock-frequency = <100000>; diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index b6fa80c3b07e..248eb717eb35 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -21,7 +21,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; @@ -234,6 +234,11 @@ groups = "du1_rgb666", "du1_sync", "du1_disp"; function = "du1"; }; + + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; }; &rwdt { @@ -314,6 +319,8 @@ pmic@58 { compatible = "dlg,da9063"; reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; interrupt-parent = <&irqc>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index f46f4567b3d4..bd2a63bdab3d 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 38fb43d11b27..c4ea2d676030 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -875,6 +875,40 @@ compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7792-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7792-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; }; timer { diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index f51601af89a2..42f3313e6988 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -52,7 +52,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; @@ -514,6 +514,11 @@ function = "intc"; }; + pmic_irq_pins: pmicirq { + groups = "intc_irq2"; + function = "intc"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -711,6 +716,8 @@ }; &i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins>; status = "okay"; clock-frequency = <100000>; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 0ab3d8d57f6d..1d22fcdc5d22 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -22,7 +22,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 60e91ebfa65d..b3177aea45d1 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -34,7 +34,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index da102fff96a2..340ed6ccb08f 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -143,6 +143,11 @@ #clock-cells = <0>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + i2s1: i2s1@100b0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100b0000 0x4000>; @@ -529,6 +534,17 @@ status = "disabled"; }; + hdmi_phy: hdmi-phy@12030000 { + compatible = "rockchip,rk3228-hdmi-phy"; + reg = <0x12030000 0x10000>; + clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; + clock-names = "sysclk", "refoclk", "refpclk"; + #clock-cells = <0>; + clock-output-names = "hdmiphy_phy"; + #phy-cells = <0>; + status = "disabled"; + }; + gpu: gpu@20000000 { compatible = "rockchip,rk3228-mali", "arm,mali-400"; reg = <0x20000000 0x10000>; @@ -572,6 +588,28 @@ status = "disabled"; }; + vop: vop@20050000 { + compatible = "rockchip,rk3228-vop"; + reg = <0x20050000 0x1ffc>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + vop_mmu: iommu@20053f00 { compatible = "rockchip,iommu"; reg = <0x20053f00 0x100>; @@ -579,7 +617,7 @@ interrupt-names = "vop_mmu"; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "iface"; - iommu-cells = <0>; + #iommu-cells = <0>; status = "disabled"; }; @@ -594,6 +632,36 @@ status = "disabled"; }; + hdmi: hdmi@200a0000 { + compatible = "rockchip,rk3228-dw-hdmi"; + reg = <0x200a0000 0x20000>; + reg-io-width = <4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_HDMI_PHY>; + assigned-clock-parents = <&hdmi_phy>; + clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; + clock-names = "isfr", "iahb", "cec"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; + resets = <&cru SRST_HDMI_P>; + reset-names = "hdmi"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + }; + sdmmc: dwmmc@30000000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30000000 0x4000>; @@ -922,6 +990,21 @@ }; }; + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; + }; + + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, + <0 RK_PA7 2 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index fbef34578100..1cadb522fd0d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -70,6 +70,21 @@ pinctrl-0 = <&ac_present_ap>; }; + lid_switch: lid-switch { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&ap_lid_int_l>; + + lid { + label = "Lid"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + debounce-interval = <1>; + }; + }; + panel: panel { compatible ="innolux,n116bge", "simple-panel"; status = "okay"; @@ -149,18 +164,6 @@ status = "okay"; }; -&gpio_keys { - pinctrl-0 = <&pwr_key_l &ap_lid_int_l>; - lid { - label = "Lid"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = <0>; /* SW_LID */ - linux,input-type = <5>; /* EV_SW */ - debounce-interval = <1>; - }; -}; - &pwm0 { status = "okay"; }; @@ -234,6 +237,7 @@ /* Wake only */ &suspend_l_wake + &bt_dev_wake_awake >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ @@ -243,6 +247,7 @@ /* Sleep only */ &suspend_l_sleep + &bt_dev_wake_sleep >; backlight { diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index e248f55ee8d2..fcd119168cb6 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -135,6 +135,213 @@ pinctrl-0 = <&vcc50_hdmi_en>; }; +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "DDRIO_PWROFF", + "DDRIO_RETEN", + "TS3A227E_INT_L", + "PMIC_INT_L", + "PWR_KEY_L", + "AP_LID_INT_L", + "EC_IN_RW", + + "AC_PRESENT_AP", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OTP_OUT", + "HOST1_PWR_EN", + "USBOTG_PWREN_H", + "AP_WARM_RESET_H", + "nFALUT2", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "SUSPEND_L", + "USB_INT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "", + "EMMC_RST_L", + "", + "", + "BL_PWR_EN", + "AVDD_1V8_DISP_EN"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS", + "UART0_RTS", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "BT_DEV_WAKE", /* Maybe missing from mighty? */ + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "SPI0_CLK", + "SPI0_CS0", + "SPI0_TXD", + "SPI0_RXD", + + "", + "", + "", + "VCC50_HDMI_EN"; +}; + +&gpio6 { + gpio-line-names = "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI", + "I2S0_SDO0", + "HP_DET_H", + "ALS_INT", + "INT_CODEC", + + "I2S0_CLK", + "I2C2_SDA", + "I2C2_SCL", + "MICDET", + "", + "", + "", + "", + + "SDMMC_D0", + "SDMMC_D1", + "SDMMC_D2", + "SDMMC_D3", + "SDMMC_CLK", + "SDMMC_CMD"; +}; + +&gpio7 { + gpio-line-names = "LCDC_BL", + "PWM_LOG", + "BL_EN", + "TRACKPAD_INT", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "EC_INT", + + "CPU_NMI", + "DVSOK", + "SDMMC_WP", /* mighty only */ + "EDP_HPD", + "DVS1", + "nFALUT1", /* nFAULT1 on jaq */ + "LCD_EN", + "DVS2", + + "VCC5V_GOOD_H", + "I2C4_SDA_TP", + "I2C4_SCL_TP", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "5V_DRV", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + &pinctrl { backlight { bl_pwr_en: bl_pwr_en { diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index b1613af83d5d..164561f04c1d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -103,6 +103,213 @@ pinctrl-0 = <&vcc50_hdmi_en>; }; +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "DDRIO_PWROFF", + "DDRIO_RETEN", + "TS3A227E_INT_L", + "PMIC_INT_L", + "PWR_KEY_L", + "AP_LID_INT_L", + "EC_IN_RW", + + "AC_PRESENT_AP", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OTP_OUT", + "HOST1_PWR_EN", + "USBOTG_PWREN_H", + "AP_WARM_RESET_H", + "nFAULT2", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "SUSPEND_L", + "USB_INT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "", + "EMMC_RST_L", + "", + "", + "BL_PWR_EN", + "AVDD_1V8_DISP_EN"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS", + "UART0_RTS", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "BT_DEV_WAKE", + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "SPI0_CLK", + "SPI0_CS0", + "SPI0_TXD", + "SPI0_RXD", + + "", + "", + "", + "VCC50_HDMI_EN"; +}; + +&gpio6 { + gpio-line-names = "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI", + "I2S0_SDO0", + "HP_DET_H", + "", + "INT_CODEC", + + "I2S0_CLK", + "I2C2_SDA", + "I2C2_SCL", + "MICDET", + "", + "", + "", + "", + + "SDMMC_D0", + "SDMMC_D1", + "SDMMC_D2", + "SDMMC_D3", + "SDMMC_CLK", + "SDMMC_CMD"; +}; + +&gpio7 { + gpio-line-names = "LCDC_BL", + "PWM_LOG", + "BL_EN", + "TRACKPAD_INT", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "EC_INT", + + "CPU_NMI", + "DVSOK", + "", + "EDP_HPD", + "DVS1", + "nFAULT1", + "LCD_EN", + "DVS2", + + "VCC5V_GOOD_H", + "I2C4_SDA_TP", + "I2C4_SCL_TP", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "5V_DRV", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + &pinctrl { backlight { bl_pwr_en: bl_pwr_en { diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts index e852594417b5..aa352d40c991 100644 --- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts +++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts @@ -75,9 +75,7 @@ cooling-maps { /* * After 1st level, throttle the CPU down to as low as 1.4 GHz - * and don't let the GPU go faster than 400 MHz. Note that we - * won't throttle the GPU lower than 400 MHz due to CPU - * heat--we'll let the GPU do the rest itself. + * and don't let the GPU go faster than 400 MHz. */ cpu_warm_limit_cpu { trip = <&cpu_alert_warm>; @@ -86,6 +84,10 @@ <&cpu2 THERMAL_NO_LIMIT 4>, <&cpu3 THERMAL_NO_LIMIT 4>; }; + cpu_warm_limit_gpu { + trip = <&cpu_alert_warm>; + cooling-device = <&gpu 1 1>; + }; /* * Add some discrete steps to help throttling system deal @@ -125,11 +127,80 @@ <&cpu2 8 THERMAL_NO_LIMIT>, <&cpu3 8 THERMAL_NO_LIMIT>; }; + + /* At very hot, don't let GPU go over 300 MHz */ + cpu_very_hot_limit_gpu { + trip = <&cpu_alert_very_hot>; + cooling-device = <&gpu 2 2>; + }; }; }; -&emmc { - /delete-property/mmc-hs200-1_8v; +&gpu_thermal { + /delete-node/ trips; + /delete-node/ cooling-maps; + + trips { + gpu_alert_warmish: gpu_alert_warmish { + temperature = <60000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert_warm: gpu_alert_warm { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert_hotter: gpu_alert_hotter { + temperature = <84000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert_very_very_hot: gpu_alert_very_very_hot { + temperature = <86000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* After 1st level throttle the GPU down to as low as 400 MHz */ + gpu_warmish_limit_gpu { + trip = <&gpu_alert_warmish>; + cooling-device = <&gpu THERMAL_NO_LIMIT 1>; + }; + + /* + * Slightly after we throttle the GPU, we'll also make sure that + * the CPU can't go faster than 1.4 GHz. Note that we won't + * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll + * let the CPU do the rest itself. + */ + gpu_warm_limit_cpu { + trip = <&gpu_alert_warm>; + cooling-device = <&cpu0 4 4>, + <&cpu1 4 4>, + <&cpu2 4 4>, + <&cpu3 4 4>; + }; + + /* When hot, GPU goes down to 300 MHz */ + gpu_hotter_limit_gpu { + trip = <&gpu_alert_hotter>; + cooling-device = <&gpu 2 2>; + }; + + /* When really hot, don't let GPU go _above_ 300 MHz */ + gpu_very_very_hot_limit_gpu { + trip = <&gpu_alert_very_very_hot>; + cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; + }; + }; }; &i2c2 { @@ -142,8 +213,6 @@ &i2s { status = "okay"; - clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; }; &rk808 { @@ -183,6 +252,157 @@ }; }; +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "", + "", + "", + "PMIC_INT_L", + "POWER_BUTTON_L", + "", + "", + + "", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OT_RESET", + "", + "", + "AP_WARM_RESET_H", + "", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "", + "nFALUT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "", + "EMMC_RST_L"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS_L", + "UART0_RTS_L", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "BT_DEV_WAKE", + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio7 { + gpio-line-names = "", + "PWM_LOG", + "", + "", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "", + + "CPU_NMI", + "DVSOK", + "HDMI_WAKE", + "POWER_HDMI_ON", + "DVS1", + "", + "", + "DVS2", + + "HDMI_CEC", + "", + "", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + &pinctrl { hdmi { power_hdmi_on: power-hdmi-on { diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 468a1818545d..9008e703c07e 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -48,6 +48,26 @@ regulator-boot-on; vin-supply = <&vcc18_wl>; }; + + volume_buttons: volume-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&volum_down_l &volum_up_l>; + + volum_down { + label = "Volum_down"; + gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <100>; + }; + + volum_up { + label = "Volum_up"; + gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <100>; + }; + }; }; &backlight { @@ -86,30 +106,6 @@ 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; power-supply = <&backlight_regulator>; - post-pwm-on-delay-ms = <200>; - pwm-off-delay-ms = <200>; -}; - -&emmc { - /delete-property/mmc-hs200-1_8v; -}; - -&gpio_keys { - pinctrl-0 = <&pwr_key_l &ap_lid_int_l &volum_down_l &volum_up_l>; - - volum_down { - label = "Volum_down"; - gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <100>; - }; - - volum_up { - label = "Volum_up"; - gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <100>; - }; }; &i2c_tunnel { @@ -188,6 +184,218 @@ pinctrl-0 = <&vcc50_hdmi_en>; }; +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "DDRIO_PWROFF", + "DDRIO_RETEN", + "TS3A227E_INT_L", + "PMIC_INT_L", + "PWR_KEY_L", + "AP_LID_INT_L", + "EC_IN_RW", + + "AC_PRESENT_AP", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OTP_OUT", + "HOST1_PWR_EN", + "USBOTG_PWREN_H", + "AP_WARM_RESET_H", + "nFALUT2", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "SUSPEND_L", + "USB_INT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "PROCHOT#", + "EMMC_RST_L", + "", + "", + "BL_PWR_EN", + "AVDD_1V8_DISP_EN", + "TOUCH_INT", + "TOUCH_RST", + + "I2C3_SCL_TP", + "I2C3_SDA_TP"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS", + "UART0_RTS", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "dev_wake", + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "Volum_Up#", + "Volum_Down#", + "SPI0_CLK", + "SPI0_CS0", + "SPI0_TXD", + "SPI0_RXD", + + "", + "", + "", + "VCC50_HDMI_EN"; +}; + +&gpio6 { + gpio-line-names = "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI", + "I2S0_SDO0", + "HP_DET_H", + "", + "INT_CODEC", + + "I2S0_CLK", + "I2C2_SDA", + "I2C2_SCL", + "MICDET", + "", + "", + "", + "", + + "SDMMC_D0", + "SDMMC_D1", + "SDMMC_D2", + "SDMMC_D3", + "SDMMC_CLK", + "SDMMC_CMD"; +}; + +&gpio7 { + gpio-line-names = "LCDC_BL", + "PWM_LOG", + "BL_EN", + "TRACKPAD_INT", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "EC_INT", + + "CPU_NMI", + "DVS_OK", + "SDMMC_WP", + "EDP_HPD", + "DVS1", + "nFALUT1", + "LCD_EN", + "DVS2", + + "VCC5V_GOOD_H", + "I2C4_SDA_TP", + "I2C4_SCL_TP", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "5V_DRV", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + &pinctrl { backlight { bl_pwr_en: bl_pwr_en { diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 9645be7b3d8c..9b6f4d9b03b6 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -35,7 +35,7 @@ force-hpd; }; -&gpio_keys { +&lid_switch { pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; power { diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index 2ac8748a3a0c..9b140db04456 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -64,6 +64,10 @@ temperature = <70000>; }; +&cpu_crit { + temperature = <90000>; +}; + &edp { /delete-property/pinctrl-names; /delete-property/pinctrl-0; @@ -71,6 +75,14 @@ force-hpd; }; +&gpu_alert0 { + temperature = <80000>; +}; + +&gpu_crit { + temperature = <90000>; +}; + &panel { power-supply= <&panel_regulator>; }; @@ -101,6 +113,213 @@ pinctrl-0 = <&vcc50_hdmi_en>; }; +&gpio0 { + gpio-line-names = "PMIC_SLEEP_AP", + "DDRIO_PWROFF", + "DDRIO_RETEN", + "TS3A227E_INT_L", + "PMIC_INT_L", + "PWR_KEY_L", + "AP_LID_INT_L", + "EC_IN_RW", + + "AC_PRESENT_AP", + /* + * RECOVERY_SW_L is Chrome OS ABI. Schematics call + * it REC_MODE_L. + */ + "RECOVERY_SW_L", + "OTP_OUT", + "HOST1_PWR_EN", + "USBOTG_PWREN_H", + "AP_WARM_RESET_H", + "nFALUT2", + "I2C0_SDA_PMIC", + + "I2C0_SCL_PMIC", + "SUSPEND_L", + "USB_INT"; +}; + +&gpio2 { + gpio-line-names = "CONFIG0", + "CONFIG1", + "CONFIG2", + "", + "", + "", + "", + "CONFIG3", + + "PWRLIMIT#_CPU", + "EMMC_RST_L", + "", + "", + "BL_PWR_EN", + "AVDD_1V8_DISP_EN"; +}; + +&gpio3 { + gpio-line-names = "FLASH0_D0", + "FLASH0_D1", + "FLASH0_D2", + "FLASH0_D3", + "FLASH0_D4", + "FLASH0_D5", + "FLASH0_D6", + "FLASH0_D7", + + "", + "", + "", + "", + "", + "", + "", + "", + + "FLASH0_CS2/EMMC_CMD", + "", + "FLASH0_DQS/EMMC_CLKO"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "", + "", + "", + "", + + "UART0_RXD", + "UART0_TXD", + "UART0_CTS", + "UART0_RTS", + "SDIO0_D0", + "SDIO0_D1", + "SDIO0_D2", + "SDIO0_D3", + + "SDIO0_CMD", + "SDIO0_CLK", + "BT_DEV_WAKE", + "", + "WIFI_ENABLE_H", + "BT_ENABLE_L", + "WIFI_HOST_WAKE", + "BT_HOST_WAKE"; +}; + +&gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + + "", + "", + "", + "", + "SPI0_CLK", + "SPI0_CS0", + "SPI0_TXD", + "SPI0_RXD", + + "", + "", + "", + "VCC50_HDMI_EN"; +}; + +&gpio6 { + gpio-line-names = "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI", + "I2S0_SDO0", + "HP_DET_H", + "ALS_INT", /* not connected */ + "INT_CODEC", + + "I2S0_CLK", + "I2C2_SDA", + "I2C2_SCL", + "MICDET", + "", + "", + "", + "", + + "SDMMC_D0", + "SDMMC_D1", + "SDMMC_D2", + "SDMMC_D3", + "SDMMC_CLK", + "SDMMC_CMD"; +}; + +&gpio7 { + gpio-line-names = "LCDC_BL", + "PWM_LOG", + "BL_EN", + "TRACKPAD_INT", + "TPM_INT_H", + "SDMMC_DET_L", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", + "EC_INT", + + "CPU_NMI", + "DVS_OK", + "", + "EDP_HOTPLUG", + "DVS1", + "nFALUT1", + "LCD_EN", + "DVS2", + + "VCC5V_GOOD_H", + "I2C4_SDA_TP", + "I2C4_SCL_TP", + "I2C5_SDA_HDMI", + "I2C5_SCL_HDMI", + "5V_DRV", + "UART2_RXD", + "UART2_TXD"; +}; + +&gpio8 { + gpio-line-names = "RAM_ID0", + "RAM_ID1", + "RAM_ID2", + "RAM_ID3", + "I2C1_SDA_TPM", + "I2C1_SCL_TPM", + "SPI2_CLK", + "SPI2_CS0", + + "SPI2_RXD", + "SPI2_TXD"; +}; + &pinctrl { backlight { bl_pwr_en: bl_pwr_en { diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 1d8bfed7830c..8fc8eac699bf 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -23,11 +23,36 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - gpio_keys: gpio-keys { + bt_activity: bt-activity { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake>; + + /* + * HACK: until we have an LPM driver, we'll use an + * ugly GPIO key to allow Bluetooth to wake from S3. + * This is expected to only be used by BT modules that + * use UART for comms. For BT modules that talk over + * SDIO we should use a wakeup mechanism related to SDIO. + * + * Use KEY_RESERVED here since that will work as a wakeup but + * doesn't get reported to higher levels (so doesn't confuse + * Chrome). + */ + bt-wake { + label = "BT Wakeup"; + gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_RESERVED>; + wakeup-source; + }; + + }; + power_button: power-button { + compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pwr_key_l>; + power { label = "Power"; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; @@ -123,6 +148,10 @@ cpu0-supply = <&vdd_cpu>; }; +&cpu_crit { + temperature = <100000>; +}; + /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ &cpu_opp_table { /delete-node/ opp-312000000; @@ -162,8 +191,18 @@ status = "okay"; }; +&gpu_alert0 { + temperature = <72500>; +}; + +&gpu_crit { + temperature = <100000>; +}; + &hdmi { - ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default", "unwedge"; + pinctrl-0 = <&hdmi_ddc>; + pinctrl-1 = <&hdmi_ddc_unwedge>; status = "okay"; }; @@ -334,14 +373,6 @@ i2c-scl-rising-time-ns = <300>; /* 225ns measured */ }; -&i2c5 { - status = "okay"; - - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <300>; - i2c-scl-rising-time-ns = <1000>; -}; - &io_domains { status = "okay"; @@ -394,6 +425,7 @@ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-temp = <125000>; }; &uart0 { @@ -455,12 +487,18 @@ &ddr0_retention &ddrio_pwroff &global_pwroff + + /* Wake only */ + &bt_dev_wake_awake >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ &ddr0_retention &ddrio_pwroff &global_pwroff + + /* Sleep only */ + &bt_dev_wake_sleep >; pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { @@ -544,6 +582,10 @@ rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; + bt_host_wake: bt-host-wake { + rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + /* * We run sdio0 at max speed; bump up drive strength. * We also have external pulls, so disable the internal ones. @@ -562,6 +604,20 @@ sdio0_clk: sdio0-clk { rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; }; + + /* + * These pins are only present on very new veyron boards; on + * older boards bt_dev_wake is simply always high. Note that + * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt + * to map this pin everywhere + */ + bt_dev_wake_sleep: bt-dev-wake-sleep { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + bt_dev_wake_awake: bt-dev-wake-awake { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; + }; }; tpm { diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index aa017abf4f42..cc893e154fe5 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -231,6 +231,7 @@ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clock-frequency = <24000000>; + arm,no-tick-in-suspend; }; timer: timer@ff810000 { @@ -551,10 +552,7 @@ map0 { trip = <&gpu_alert0>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -682,7 +680,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -693,7 +691,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -704,7 +702,7 @@ #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -712,10 +710,10 @@ pwm3: pwm@ff680030 { compatible = "rockchip,rk3288-pwm"; reg = <0x0 0xff680030 0x0 0x10>; - #pwm-cells = <2>; + #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; + clocks = <&cru PCLK_RKPWM>; clock-names = "pwm"; status = "disabled"; }; @@ -1285,6 +1283,7 @@ interrupt-names = "job", "mmu", "gpu"; clocks = <&cru ACLK_GPU>; operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ power-domains = <&power RK3288_PD_GPU>; status = "disabled"; }; @@ -1308,10 +1307,6 @@ opp-hz = /bits/ 64 <400000000>; opp-microvolt = <1100000>; }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1200000>; - }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1250000>; @@ -1552,6 +1547,15 @@ rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, <7 RK_PC4 2 &pcfg_pull_none>; }; + + hdmi_ddc_unwedge: hdmi-ddc-unwedge { + rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, + <7 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + pcfg_output_low: pcfg-output-low { + output-low; }; pcfg_pull_up: pcfg-pull-up { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 3bbc84bf8dbf..f770aace0efd 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1371,30 +1371,11 @@ status = "disabled"; }; - sckc@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; + clk32k: sckc@fffffe50 { + compatible = "atmel,sama5d3-sckc"; reg = <0xfffffe50 0x4>; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - atmel,startup-time-usec = <75>; - }; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - atmel,startup-time-usec = <1200000>; - }; - - clk32k: slowck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; + clocks = <&slow_xtal>; + #clock-cells = <0>; }; rtc@fffffeb0 { diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index daac0c6078c5..1916f31a30ff 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -36,7 +36,7 @@ }; chosen { - bootargs = "root=/dev/nfs ip=dhcp ignore_loglevel rw"; + bootargs = "root=/dev/nfs ip=on ignore_loglevel rw"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index ae24599d5829..a0a6d8507265 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -418,7 +418,7 @@ }; gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; altr,sysmgr-syscon = <&sysmgr 0x44 0>; reg = <0xff800000 0x2000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; @@ -431,15 +431,15 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x48 0>; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x48 8>; reg = <0xff802000 0x2000>; interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -451,15 +451,15 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x4C 0>; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x4C 16>; reg = <0xff804000 0x2000>; interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -470,8 +470,9 @@ tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; - resets = <&rst EMAC2_RESET>; clock-names = "stmmaceth"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 360dae5a5b12..0efbeccc5cd2 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -48,6 +48,13 @@ }; }; + ref_033v: 033-v-ref { + compatible = "regulator-fixed"; + regulator-name = "0.33V"; + regulator-min-microvolt = <330000>; + regulator-max-microvolt = <330000>; + }; + soc { clkmgr@ffd04000 { clocks { @@ -128,6 +135,18 @@ i2c-sda-falling-time-ns = <6000>; i2c-scl-falling-time-ns = <6000>; + adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&ref_033v>; + }; + + adc@16 { + compatible = "lltc,ltc2497"; + reg = <0x16>; + vref-supply = <&ref_033v>; + }; + eeprom@51 { compatible = "atmel,24c32"; reg = <0x51>; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index d90b0d1e18c7..2b1664884ae7 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -44,6 +44,7 @@ #include "stm32f746.dtsi" #include "stm32f746-pinctrl.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> / { model = "STMicroelectronics STM32746g-EVAL board"; @@ -69,9 +70,15 @@ gpios = <&gpiof 10 1>; linux,default-trigger = "heartbeat"; }; + orange { + gpios = <&stmfx_pinctrl 17 1>; + }; red { gpios = <&gpiob 7 1>; }; + blue { + gpios = <&stmfx_pinctrl 19 1>; + }; }; gpio_keys { @@ -86,6 +93,43 @@ }; }; + joystick { + compatible = "gpio-keys"; + #size-cells = <0>; + pinctrl-0 = <&joystick_pins>; + pinctrl-names = "default"; + button-0 { + label = "JoySel"; + linux,code = <KEY_ENTER>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + button-1 { + label = "JoyDown"; + linux,code = <KEY_DOWN>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + button-2 { + label = "JoyLeft"; + linux,code = <KEY_LEFT>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; + button-3 { + label = "JoyRight"; + linux,code = <KEY_RIGHT>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; + button-4 { + label = "JoyUp"; + linux,code = <KEY_UP>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; @@ -115,6 +159,28 @@ i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; + + stmfx: stmfx@42 { + compatible = "st,stmfx-0300"; + reg = <0x42>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpioi>; + + stmfx_pinctrl: stmfx-pin-controller { + compatible = "st,stmfx-0300-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&stmfx_pinctrl 0 0 24>; + + joystick_pins: joystick { + pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; + drive-push-pull; + bias-pull-up; + }; + }; + }; }; &rtc { diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 85c417d9983b..df6470133574 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -26,6 +26,7 @@ st,bank-name = "GPIOA"; ngpios = <16>; gpio-ranges = <&pinctrl 0 0 16>; + status = "disabled"; }; gpiob: gpio@50003000 { @@ -38,6 +39,7 @@ st,bank-name = "GPIOB"; ngpios = <16>; gpio-ranges = <&pinctrl 0 16 16>; + status = "disabled"; }; gpioc: gpio@50004000 { @@ -50,6 +52,7 @@ st,bank-name = "GPIOC"; ngpios = <16>; gpio-ranges = <&pinctrl 0 32 16>; + status = "disabled"; }; gpiod: gpio@50005000 { @@ -62,6 +65,7 @@ st,bank-name = "GPIOD"; ngpios = <16>; gpio-ranges = <&pinctrl 0 48 16>; + status = "disabled"; }; gpioe: gpio@50006000 { @@ -74,6 +78,7 @@ st,bank-name = "GPIOE"; ngpios = <16>; gpio-ranges = <&pinctrl 0 64 16>; + status = "disabled"; }; gpiof: gpio@50007000 { @@ -86,6 +91,7 @@ st,bank-name = "GPIOF"; ngpios = <16>; gpio-ranges = <&pinctrl 0 80 16>; + status = "disabled"; }; gpiog: gpio@50008000 { @@ -98,6 +104,7 @@ st,bank-name = "GPIOG"; ngpios = <16>; gpio-ranges = <&pinctrl 0 96 16>; + status = "disabled"; }; gpioh: gpio@50009000 { @@ -110,6 +117,7 @@ st,bank-name = "GPIOH"; ngpios = <16>; gpio-ranges = <&pinctrl 0 112 16>; + status = "disabled"; }; gpioi: gpio@5000a000 { @@ -122,6 +130,7 @@ st,bank-name = "GPIOI"; ngpios = <16>; gpio-ranges = <&pinctrl 0 128 16>; + status = "disabled"; }; gpioj: gpio@5000b000 { @@ -134,6 +143,7 @@ st,bank-name = "GPIOJ"; ngpios = <16>; gpio-ranges = <&pinctrl 0 144 16>; + status = "disabled"; }; gpiok: gpio@5000c000 { @@ -146,6 +156,7 @@ st,bank-name = "GPIOK"; ngpios = <8>; gpio-ranges = <&pinctrl 0 160 8>; + status = "disabled"; }; cec_pins_a: cec-0 { @@ -178,6 +189,47 @@ }; }; + dcmi_pins_a: dcmi-0 { + pins { + pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ + <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ + <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ + <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ + <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ + <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_a: dcmi-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ + <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ + <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ + <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ + <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ + <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -241,6 +293,23 @@ }; }; + i2c1_pins_b: i2c1-2 { + pins { + pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_pins_sleep_b: i2c1-3 { + pins { + pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ + }; + }; + i2c2_pins_a: i2c2-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ @@ -258,6 +327,21 @@ }; }; + i2c2_pins_b1: i2c2-2 { + pins { + pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_b1: i2c2-3 { + pins { + pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ + }; + }; + i2c5_pins_a: i2c5-0 { pins { pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ @@ -276,6 +360,25 @@ }; }; + i2s2_pins_a: i2s2-0 { + pins { + pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ + <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ + <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + i2s2_pins_sleep_a: i2s2-1 { + pins { + pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ + <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ + <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ + }; + }; + ltdc_pins_a: ltdc-a-0 { pins { pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ @@ -470,6 +573,12 @@ }; }; + qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ + }; + }; + qspi_bk1_pins_a: qspi-bk1-0 { pins1 { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ @@ -488,6 +597,16 @@ }; }; + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ + <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + qspi_bk2_pins_a: qspi-bk2-0 { pins1 { pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ @@ -506,6 +625,89 @@ }; }; + qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ + <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ + <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ + }; + }; + + sai2a_pins_a: sai2a-0 { + pins { + pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ + <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ + <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_a: sai2a-1 { + pins { + pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ + <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ + <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ + }; + }; + + sai2b_pins_a: sai2b-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ + <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ + <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_a: sai2b-1 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ + <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ + <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ + <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ + }; + }; + + sai2b_pins_b: sai2b-2 { + pins { + pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_b: sai2b-3 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ + }; + }; + + sai4a_pins_a: sai4a-0 { + pins { + pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai4a_sleep_pins_a: sai4a-1 { + pins { + pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -599,6 +801,34 @@ bias-disable; }; }; + + uart4_pins_b: uart4-1 { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */ + <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */ + <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */ + bias-disable; + }; + }; }; pinctrl_z: pin-controller-z@54004000 { @@ -621,6 +851,22 @@ st,bank-ioport = <11>; ngpios = <8>; gpio-ranges = <&pinctrl_z 0 400 8>; + status = "disabled"; + }; + + i2c2_pins_b2: i2c2-0 { + pins { + pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_b2: i2c2-1 { + pins { + pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ + }; }; i2c4_pins_a: i2c4-0 { diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts new file mode 100644 index 000000000000..2e4742c53d04 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + */ + +/dts-v1/; + +#include "stm32mp157c.dtsi" +#include "stm32mp157xac-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + model = "Arrow Electronics STM32MP157A Avenger96 board"; + compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x40000000>; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "green:user1"; + gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user3"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led5 { + label = "yellow:wifi"; + gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led6 { + label = "blue:bt"; + gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@7 { + reg = <7>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + st,main-control-register = <0x04>; + st,vin-control-register = <0xc0>; + st,usb-control-register = <0x30>; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask_reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO1 0>; + interrupt-parent = <&pmic>; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = <IT_CURLIM_LDO2 0>; + interrupt-parent = <&pmic>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + interrupt-parent = <&pmic>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + interrupt-parent = <&pmic>; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO6 0>; + interrupt-parent = <&pmic>; + regulator-enable-ramp-delay = <300000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + interrupt-parent = <&pmic>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + interrupt-parent = <&pmic>; + regulator-active-discharge; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + interrupt-parent = <&pmic>; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + status = "okay"; +}; + +&uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 098dbfb06b61..f3f0e37aad4d 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -7,7 +7,7 @@ /dts-v1/; #include "stm32mp157c.dtsi" -#include "stm32mp157-pinctrl.dtsi" +#include "stm32mp157xac-pinctrl.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mfd/st,stpmic1.h> @@ -28,6 +28,17 @@ reg = <0xc0000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpu_reserved: gpu@d4000000 { + reg = <0xd4000000 0x4000000>; + no-map; + }; + }; + led { compatible = "gpio-leds"; blue { @@ -51,7 +62,7 @@ pinctrl-0 = <ðernet0_rgmii_pins_a>; pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>; @@ -65,6 +76,47 @@ }; }; +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_pins_sleep_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + hdmi-transmitter@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + iovcc-supply = <&v3v3_hdmi>; + cvcc12-supply = <&v1v2_hdmi>; + reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_a>; + pinctrl-1 = <<dc_pins_sleep_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sii9022_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; + }; +}; &i2c4 { pinctrl-names = "default"; @@ -223,6 +275,20 @@ status = "okay"; }; +<dc { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in>; + }; + }; +}; + &rng1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 62a8c78e7e2e..4fe7f71a74d3 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "stm32mp157c.dtsi" -#include "stm32mp157-pinctrl.dtsi" +#include "stm32mp157xaa-pinctrl.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mfd/st,stpmic1.h> @@ -23,6 +23,17 @@ reg = <0xC0000000 0x40000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpu_reserved: gpu@e8000000 { + reg = <0xe8000000 0x8000000>; + no-map; + }; + }; + aliases { serial0 = &uart4; }; @@ -61,6 +72,11 @@ status = "okay"; }; +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index b6aca40b9b90..feb8f7727270 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -7,6 +7,7 @@ #include "stm32mp157c-ed1.dts" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -21,6 +22,51 @@ ethernet0 = ðernet0; }; + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + joystick { + compatible = "gpio-keys"; + #size-cells = <0>; + pinctrl-0 = <&joystick_pins>; + pinctrl-names = "default"; + button-0 { + label = "JoySel"; + linux,code = <KEY_ENTER>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + }; + button-1 { + label = "JoyDown"; + linux,code = <KEY_DOWN>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + }; + button-2 { + label = "JoyLeft"; + linux,code = <KEY_LEFT>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + }; + button-3 { + label = "JoyRight"; + linux,code = <KEY_RIGHT>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; + button-4 { + label = "JoyUp"; + linux,code = <KEY_UP>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + }; + }; + panel_backlight: panel-backlight { compatible = "gpio-backlight"; gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; @@ -35,6 +81,23 @@ status = "okay"; }; +&dcmi { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_a>; + pinctrl-1 = <&dcmi_sleep_pins_a>; + + port { + dcmi_0: endpoint { + remote-endpoint = <&ov5640_0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; +}; + &dsi { #address-cells = <1>; #size-cells = <0>; @@ -64,6 +127,7 @@ reg = <0>; reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; backlight = <&panel_backlight>; + power-supply = <&v3v3>; status = "okay"; port { @@ -79,7 +143,7 @@ pinctrl-0 = <ðernet0_rgmii_pins_a>; pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>; @@ -99,6 +163,60 @@ i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&ov5640_pins>; + reg = <0x3c>; + clocks = <&clk_ext_camera>; + clock-names = "xclk"; + DOVDD-supply = <&v2v8>; + powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>; + reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>; + rotation = <180>; + status = "okay"; + + port { + ov5640_0: endpoint { + remote-endpoint = <&dcmi_0>; + bus-width = <8>; + data-shift = <2>; /* lines 9:2 are used */ + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; + }; + + stmfx: stmfx@42 { + compatible = "st,stmfx-0300"; + reg = <0x42>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpioi>; + vdd-supply = <&v3v3>; + + stmfx_pinctrl: stmfx-pin-controller { + compatible = "st,stmfx-0300-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&stmfx_pinctrl 0 0 24>; + + joystick_pins: joystick { + pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; + drive-push-pull; + bias-pull-down; + }; + + ov5640_pins: camera { + pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */ + drive-push-pull; + output-low; + }; + }; + }; }; &i2c5 { @@ -131,14 +249,16 @@ }; &qspi { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: mx66l51235l@0 { + compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; @@ -147,6 +267,7 @@ }; flash1: mx66l51235l@1 { + compatible = "jedec,spi-nor"; reg = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 2afeee65c3ea..0c4e6ebc3529 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -365,6 +365,17 @@ status = "disabled"; }; + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi3: spi@4000c000 { #address-cells = <1>; #size-cells = <0>; @@ -379,6 +390,17 @@ status = "disabled"; }; + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000c000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spdifrx: audio-controller@4000d000 { compatible = "st,stm32h7-spdifrx"; #sound-dai-cells = <0>; @@ -607,6 +629,17 @@ status = "disabled"; }; + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x44004000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi4: spi@44005000 { #address-cells = <1>; #size-cells = <0>; @@ -708,6 +741,100 @@ status = "disabled"; }; + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400a000 0x400>; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI1_R>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + #sound-dai-cells = <0>; + + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x1c>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; + + sai1b: audio-controller@4400a024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x1c>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; + + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400b000 0x400>; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI2_R>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x1c>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; + + sai2b: audio-controller@4400b024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x1c>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; + + sai3: sai@4400c000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400c000 0x400>; + reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI3_R>; + status = "disabled"; + + sai3a: audio-controller@4400c004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x1c>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 113 0x400 0x01>; + status = "disabled"; + }; + + sai3b: audio-controller@4400c024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x1c>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 114 0x400 0x01>; + status = "disabled"; + }; + }; + dfsdm: dfsdm@4400d000 { compatible = "st,stm32mp1-dfsdm"; reg = <0x4400d000 0x800>; @@ -914,6 +1041,18 @@ status = "disabled"; }; + dcmi: dcmi@4c006000 { + compatible = "st,stm32-dcmi"; + reg = <0x4c006000 0x400>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc CAMITF_R>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; + dmas = <&dmamux1 75 0x400 0x0d>; + dma-names = "tx"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -1020,6 +1159,37 @@ status = "disabled"; }; + sai4: sai@50027000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50027000 0x400>; + reg = <0x50027000 0x4>, <0x500273f0 0x10>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI4_R>; + status = "disabled"; + + sai4a: audio-controller@50027004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x1c>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 99 0x400 0x01>; + status = "disabled"; + }; + + sai4b: audio-controller@50027024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x1c>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 100 0x400 0x01>; + status = "disabled"; + }; + }; + dts: thermal@50028000 { compatible = "st,stm32-thermal"; reg = <0x50028000 0x100>; @@ -1149,6 +1319,16 @@ status = "disabled"; }; + gpu: gpu@59000000 { + compatible = "vivante,gc"; + reg = <0x59000000 0x800>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc GPU>, <&rcc GPU_K>; + clock-names = "bus" ,"core"; + resets = <&rcc GPU_R>; + status = "disabled"; + }; + dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; diff --git a/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi new file mode 100644 index 000000000000..875adf5e1e30 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> + */ + +#include "stm32mp157-pinctrl.dtsi" +/ { + soc { + pinctrl: pin-controller@50002000 { + st,package = <STM32MP_PKG_AA>; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@5000a000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@5000b000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@5000c000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; + }; + + pinctrl_z: pin-controller-z@54004000 { + st,package = <STM32MP_PKG_AA>; + + gpioz: gpio@54004000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl_z 0 400 8>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi new file mode 100644 index 000000000000..961fa12a59c3 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> + */ + +#include "stm32mp157-pinctrl.dtsi" +/ { + soc { + pinctrl: pin-controller@50002000 { + st,package = <STM32MP_PKG_AB>; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <6>; + gpio-ranges = <&pinctrl 6 86 6>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl 6 102 10>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <2>; + gpio-ranges = <&pinctrl 0 112 2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi new file mode 100644 index 000000000000..26600f188d25 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> + */ + +#include "stm32mp157-pinctrl.dtsi" +/ { + soc { + pinctrl: pin-controller@50002000 { + st,package = <STM32MP_PKG_AC>; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@5000a000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; + }; + + pinctrl_z: pin-controller-z@54004000 { + st,package = <STM32MP_PKG_AC>; + + gpioz: gpio@54004000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl_z 0 400 8>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi new file mode 100644 index 000000000000..910113f3e69a --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> + */ + +#include "stm32mp157-pinctrl.dtsi" +/ { + soc { + pinctrl: pin-controller@50002000 { + st,package = <STM32MP_PKG_AD>; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <6>; + gpio-ranges = <&pinctrl 6 86 6>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl 6 102 10>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <2>; + gpio-ranges = <&pinctrl 0 112 2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index d003b895a696..4c20d731a9c6 100644 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -150,7 +150,7 @@ }; pcf8563: rtc@51 { - compatible = "phg,pcf8563"; + compatible = "nxp,pcf8563"; reg = <0x51>; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index c04efad81bbc..dcddc3392460 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -216,6 +216,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; @@ -223,7 +224,8 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-accuracy = <50000>; + clock-output-names = "ext_osc32k"; }; /* @@ -588,7 +590,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun6i-a31-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -601,7 +603,7 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -987,6 +989,8 @@ dma-names = "rx", "tx"; resets = <&ccu RST_AHB1_SPI0>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; spi1: spi@1c69000 { @@ -999,6 +1003,8 @@ dma-names = "rx", "tx"; resets = <&ccu RST_AHB1_SPI1>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; spi2: spi@1c6a000 { @@ -1011,6 +1017,8 @@ dma-names = "rx", "tx"; resets = <&ccu RST_AHB1_SPI2>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; spi3: spi@1c6b000 { @@ -1023,6 +1031,8 @@ dma-names = "rx", "tx"; resets = <&ccu RST_AHB1_SPI3>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; gic: interrupt-controller@1c81000 { @@ -1279,10 +1289,13 @@ }; rtc: rtc@1f00000 { + #clock-cells = <1>; compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc32k>; + clock-output-names = "osc32k"; }; nmi_intc: interrupt-controller@1f00c00 { @@ -1300,7 +1313,7 @@ ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, + clocks = <&rtc 0>, <&osc24M>, <&ccu CLK_PLL_PERIPH>, <&ccu CLK_PLL_PERIPH>; clock-output-names = "ar100"; @@ -1335,7 +1348,7 @@ ir_clk: ir_clk { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; + clocks = <&rtc 0>, <&osc24M>; clock-output-names = "ir"; }; @@ -1365,7 +1378,7 @@ reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts index 949494730aee..7449aac3f43b 100644 --- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts +++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts @@ -49,7 +49,8 @@ / { model = "ICnova-A20 SWAC"; - compatible = "swac,icnova-a20-swac", "incircuit,icnova-a20", "allwinner,sun7i-a20"; + compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20", + "allwinner,sun7i-a20"; aliases { serial0 = &uart0; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index 95c6f8949076..56f451c07f93 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -194,6 +194,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 66d078053d5f..568b90ece342 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -224,14 +224,14 @@ vref-supply = <®_aldo2>; status = "okay"; - button@210 { + button-210 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <210000>; }; - button@410 { + button-410 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 392b0cabbf0d..ada6d08bc540 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -679,6 +679,20 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + /omit-if-no-ref/ + csi_8bit_parallel_pins: csi-8bit-parallel-pins { + pins = "PE0", "PE2", "PE3", "PE6", "PE7", + "PE8", "PE9", "PE10", "PE11", + "PE12", "PE13"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi_mclk_pin: csi-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + emac_rgmii_pins: emac-rgmii-pins { pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD11", "PD12", "PD13", "PD14", "PD18", @@ -997,6 +1011,21 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; + csi: camera@1cb0000 { + compatible = "allwinner,sun8i-a83t-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + csi_in: port { + }; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun8i-a83t-dw-hdmi"; reg = <0x01ee0000 0x10000>; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 78a37a47185a..d277d043031b 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -59,8 +59,7 @@ gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ enable-active-high; gpios-states = <0x1>; - states = <1100000 0x0 - 1300000 0x1>; + states = <1100000 0>, <1300000 1>; }; wifi_pwrseq: wifi_pwrseq { diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index 4970eda2877e..f19ed981da9d 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -102,8 +102,7 @@ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ enable-active-high; gpios-states = <1>; - states = <1100000 0 - 1300000 1>; + states = <1100000 0>, <1300000 1>; }; wifi_pwrseq: wifi_pwrseq { diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index 6277f13f3eb3..ac9e26b1d906 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -90,6 +90,8 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; sound_spdif { @@ -155,6 +157,8 @@ &mmc1 { vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; non-removable; status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 840849169bed..4759ba3f2986 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -109,8 +109,7 @@ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ enable-active-high; gpios-states = <0x1>; - states = <1100000 0x0 - 1300000 0x1>; + states = <1100000 0>, <1300000 1>; }; }; diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index c488aaacbd68..42d62d1ba1dc 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -201,10 +201,15 @@ &pio { pinctrl-names = "default"; pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; }; ®_aldo2 { - regulator-always-on; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-name = "vcc-pa"; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index bb856e53b806..6007d0cc252d 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -318,8 +318,7 @@ }; rtc: rtc@1c20400 { - compatible = "allwinner,sun8i-r40-rtc", - "allwinner,sun8i-h3-rtc"; + compatible = "allwinner,sun8i-r40-rtc"; reg = <0x01c20400 0x400>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clock-output-names = "osc32k", "osc32k-out"; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index df72b1719c34..d7aef128acb3 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -84,6 +84,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; @@ -91,7 +92,8 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-accuracy = <50000>; + clock-output-names = "ext-osc32k"; }; }; @@ -264,17 +266,20 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; }; rtc: rtc@1c20400 { - compatible = "allwinner,sun6i-a31-rtc"; + #clock-cells = <1>; + compatible = "allwinner,sun8i-v3-rtc"; reg = <0x01c20400 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc32k>; + clock-output-names = "osc32k", "osc32k-out"; }; pio: pinctrl@1c20800 { @@ -282,7 +287,7 @@ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index f05cabd34b8e..15c22b06fc4b 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -50,6 +50,7 @@ compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; aliases { + ethernet0 = &gmac; serial0 = &uart0; }; @@ -57,6 +58,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -84,14 +96,52 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; }; }; +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo3>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + &ehci1 { /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ status = "okay"; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_dc1sw>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { status = "okay"; @@ -123,6 +173,23 @@ status = "okay"; }; +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; +}; + +®_aldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa"; +}; + ®_aldo3 { regulator-always-on; regulator-min-microvolt = <2700000>; @@ -130,6 +197,12 @@ regulator-name = "avcc"; }; +®_dc1sw { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-gmac-phy"; +}; + ®_dcdc1 { regulator-always-on; regulator-min-microvolt = <3000000>; @@ -164,18 +237,68 @@ regulator-name = "vcc-wifi-io"; }; +/* + * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same + * time, with the two being in sync, to be able to meet maximum power + * consumption during transmits. Since this is not really supported + * right now, just use the two as always on, and we will fix it later. + */ + ®_dldo2 { + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc-wifi"; }; +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; +}; + +®_dldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd2v5-sata"; +}; + +®_eldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd1v2-sata"; +}; + +&tcon_tv0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&ccu CLK_OUTA>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + /* TODO host wake line connected to PMIC GPIO pins */ + shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ + max-speed = <1500000>; + }; +}; + &usbphy { usb1_vbus-supply = <®_vcc5v0>; status = "okay"; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi index 53edd1faee99..22466afd38a3 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi @@ -21,8 +21,7 @@ regulator-ramp-delay = <50>; /* 4ms */ gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ gpios-states = <0x1>; - states = <1100000 0x0 - 1300000 0x1>; + states = <1100000 0>, <1300000 1>; }; }; diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts index 3aaca10f6644..f2d060f403cc 100644 --- a/arch/arm/boot/dts/uniphier-ld4-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts @@ -77,4 +77,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index c2706cef0b8a..58cd4e8fa5be 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -403,9 +403,11 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand2cs>; + pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts index 3d9080ee7aef..60994b6e8b99 100644 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -90,4 +90,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts index 28038b17bbb3..854f2eba3e72 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -98,4 +98,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 97d051ef4968..7f64e5a616d6 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -593,6 +593,8 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 365738739412..eff74717b37c 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -458,9 +458,11 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand2cs>; + pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 06a049f6edf8..4eddbb8d7fca 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -766,9 +766,11 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand2cs>; + pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts index 01bf94c6b93a..cf9ea0b15065 100644 --- a/arch/arm/boot/dts/uniphier-sld8-ref.dts +++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts @@ -81,4 +81,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index efce02768b6f..cbebb6e4c616 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -407,9 +407,11 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand2cs>; + pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index 269e6bf99ccb..37bd41ff8dff 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -161,6 +161,9 @@ compatible = "arm,versatile-flash", "cfi-flash"; reg = <0x34000000 0x04000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; i2c0: i2c@10002000 { diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index d3963e9eaf48..d6a1fc269241 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -30,11 +30,14 @@ #interrupt-cells = <1>; ranges; - flash@0,00000000 { + nor_flash: flash@0,00000000 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; psram@1,00000000 { diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index 798c97aff7fa..8e57e15307e2 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -35,6 +35,9 @@ reg = <0 0x00000000 0x04000000>, <1 0x00000000 0x04000000>; bank-width = <4>; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; psram@2,00000000 { diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 00cd9f5bef2e..1de0a658adf1 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -440,7 +440,7 @@ /* non-configurable replicators don't show up on the * AMBA bus. As such no need to add "arm,primecell". */ - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; out-ports { #address-cells = <1>; @@ -471,7 +471,7 @@ }; funnel@20040000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x20040000 0 0x1000>; clocks = <&oscclk6a>; @@ -680,3 +680,12 @@ <0 3 &gic 0 39 4>; }; }; + +&nor_flash { + /* + * Unfortunately, accessing the flash disturbs the CPU idle states + * (suspend) and CPU hotplug of this platform. For this reason, flash + * hardware access is disabled by default on this platform alone. + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 0507e6dcbb21..a1b4ccee2a10 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -177,6 +177,36 @@ status = "okay"; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + status = "okay"; + + /* + * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR + * modes, so, spi-max-frequency is limited to 90MHz + */ + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <90000000>; + spi-rx-bus-width = <4>; + reg = <0>; + m25p,fast-read; + }; + + flash@2 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <90000000>; + spi-rx-bus-width = <4>; + reg = <2>; + m25p,fast-read; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -360,12 +390,18 @@ pinctrl_qspi0: qspi0grp { fsl,pins = < - VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 - VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff - VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 + VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2 + VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2 + VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3 + VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3 + VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3 + VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3 + VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2 + VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2 + VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3 + VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3 + VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3 + VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3 >; }; @@ -385,8 +421,8 @@ pinctrl_uart2: uart2grp { fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD23__UART2_TX 0x21a2 + VF610_PAD_PTD22__UART2_RX 0x21a1 >; }; diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c index e24ad60891b2..8a9aeeb504dd 100644 --- a/arch/arm/common/mcpm_entry.c +++ b/arch/arm/common/mcpm_entry.c @@ -21,7 +21,7 @@ /* * The public API for this code is documented in arch/arm/include/asm/mcpm.h. * For a comprehensive description of the main algorithm used here, please - * see Documentation/arm/cluster-pm-race-avoidance.txt. + * see Documentation/arm/cluster-pm-race-avoidance.rst. */ struct sync_struct mcpm_sync; diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S index d5bd75dd576d..291d969bc719 100644 --- a/arch/arm/common/mcpm_head.S +++ b/arch/arm/common/mcpm_head.S @@ -5,7 +5,7 @@ * Created by: Nicolas Pitre, March 2012 * Copyright: (C) 2012-2013 Linaro Limited * - * Refer to Documentation/arm/cluster-pm-race-avoidance.txt + * Refer to Documentation/arm/cluster-pm-race-avoidance.rst * for details of the synchronisation algorithms used here. */ diff --git a/arch/arm/common/vlock.S b/arch/arm/common/vlock.S index 9675cc15d0c4..f1c7fd44f1b1 100644 --- a/arch/arm/common/vlock.S +++ b/arch/arm/common/vlock.S @@ -6,7 +6,7 @@ * Copyright: (C) 2012-2013 Linaro Limited * * This algorithm is described in more detail in - * Documentation/arm/vlocks.txt. + * Documentation/arm/vlocks.rst. */ #include <linux/linkage.h> diff --git a/arch/arm/configs/acs5k_defconfig b/arch/arm/configs/acs5k_defconfig index d04ee19e5b75..bcb8bda09158 100644 --- a/arch/arm/configs/acs5k_defconfig +++ b/arch/arm/configs/acs5k_defconfig @@ -30,7 +30,6 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/arm/configs/acs5k_tiny_defconfig b/arch/arm/configs/acs5k_tiny_defconfig index 25c593df41d1..e802cdebfd0b 100644 --- a/arch/arm/configs/acs5k_tiny_defconfig +++ b/arch/arm/configs/acs5k_tiny_defconfig @@ -25,7 +25,6 @@ CONFIG_INET=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig index 8c9b6ea46188..622436f44783 100644 --- a/arch/arm/configs/am200epdkit_defconfig +++ b/arch/arm/configs/am200epdkit_defconfig @@ -37,7 +37,6 @@ CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig index 190d6e9d3296..019828d7b251 100644 --- a/arch/arm/configs/aspeed_g4_defconfig +++ b/arch/arm/configs/aspeed_g4_defconfig @@ -64,7 +64,6 @@ CONFIG_VLAN_8021Q=y CONFIG_NET_NCSI=y CONFIG_BPF_STREAM_PARSER=y # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set @@ -78,8 +77,6 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y CONFIG_BLK_DEV_LOOP=y -CONFIG_ASPEED_LPC_CTRL=y -CONFIG_ASPEED_LPC_SNOOP=y CONFIG_EEPROM_AT24=y CONFIG_NETDEVICES=y CONFIG_NETCONSOLE=y @@ -169,6 +166,10 @@ CONFIG_SENSORS_UCD9200=y CONFIG_SENSORS_TMP421=y CONFIG_SENSORS_W83773G=y CONFIG_WATCHDOG_SYSFS=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_ASPEED=y CONFIG_DRM=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y @@ -207,8 +208,12 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_RV8803=y +CONFIG_RTC_DRV_ASPEED=y # CONFIG_VIRTIO_MENU is not set # CONFIG_IOMMU_SUPPORT is not set +CONFIG_ASPEED_LPC_CTRL=y +CONFIG_ASPEED_LPC_SNOOP=y +CONFIG_ASPEED_P2A_CTRL=y CONFIG_IIO=y CONFIG_ASPEED_ADC=y CONFIG_MAX1363=y diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig index 407ffb7655a8..28fe392c7dfa 100644 --- a/arch/arm/configs/aspeed_g5_defconfig +++ b/arch/arm/configs/aspeed_g5_defconfig @@ -64,7 +64,6 @@ CONFIG_VLAN_8021Q=y CONFIG_NET_NCSI=y CONFIG_BPF_STREAM_PARSER=y # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set @@ -78,8 +77,6 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y CONFIG_BLK_DEV_LOOP=y -CONFIG_ASPEED_LPC_CTRL=y -CONFIG_ASPEED_LPC_SNOOP=y CONFIG_EEPROM_AT24=y CONFIG_NETDEVICES=y CONFIG_NETCONSOLE=y @@ -169,7 +166,12 @@ CONFIG_SENSORS_UCD9200=y CONFIG_SENSORS_TMP421=y CONFIG_SENSORS_W83773G=y CONFIG_WATCHDOG_SYSFS=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_ASPEED=y CONFIG_DRM=y +CONFIG_DRM_ASPEED_GFX=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_DYNAMIC_MINORS=y @@ -203,16 +205,23 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_EDAC=y +CONFIG_EDAC_ASPEED=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_RV8803=y +CONFIG_RTC_DRV_ASPEED=y # CONFIG_VIRTIO_MENU is not set # CONFIG_IOMMU_SUPPORT is not set +CONFIG_ASPEED_LPC_CTRL=y +CONFIG_ASPEED_LPC_SNOOP=y +CONFIG_ASPEED_P2A_CTRL=y CONFIG_IIO=y CONFIG_ASPEED_ADC=y CONFIG_MAX1363=y CONFIG_BMP280=y +CONFIG_RAS=y CONFIG_FSI=y CONFIG_FSI_MASTER_GPIO=y CONFIG_FSI_MASTER_HUB=y diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index a88e31449880..309c55a8d107 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -46,7 +46,6 @@ CONFIG_IP_PNP_RARP=y CONFIG_IPV6_SIT_6RD=y CONFIG_CFG80211=y CONFIG_MAC80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set diff --git a/arch/arm/configs/axm55xx_defconfig b/arch/arm/configs/axm55xx_defconfig index 53864316bee1..31bfe1647d28 100644 --- a/arch/arm/configs/axm55xx_defconfig +++ b/arch/arm/configs/axm55xx_defconfig @@ -78,7 +78,6 @@ CONFIG_INET_IPCOMP=y CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_BRIDGE=y # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig index 5344434df652..fa997ae2673e 100644 --- a/arch/arm/configs/cm_x2xx_defconfig +++ b/arch/arm/configs/cm_x2xx_defconfig @@ -45,7 +45,6 @@ CONFIG_BT_RFCOMM=m CONFIG_BT_BNEP=m CONFIG_BT_HIDP=m CONFIG_LIB80211=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y @@ -103,7 +102,6 @@ CONFIG_FB=y CONFIG_FB_PXA=y CONFIG_FB_PXA_PARAMETERS=y CONFIG_FB_MBX=m -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set # CONFIG_BACKLIGHT_CLASS_DEVICE is not set # CONFIG_VGA_CONSOLE is not set diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig index 3707a014cbc4..2f7acde2d921 100644 --- a/arch/arm/configs/cm_x300_defconfig +++ b/arch/arm/configs/cm_x300_defconfig @@ -45,7 +45,6 @@ CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m CONFIG_BT_HCIBTUSB=m CONFIG_LIB80211=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_RAW_NAND=y @@ -86,7 +85,6 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_DA903X=y CONFIG_FB=y CONFIG_FB_PXA=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_TDO24M=y # CONFIG_BACKLIGHT_GENERIC is not set diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig index 419b73564f29..89df0a55a065 100644 --- a/arch/arm/configs/cns3420vb_defconfig +++ b/arch/arm/configs/cns3420vb_defconfig @@ -27,7 +27,6 @@ CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait" -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig index 8d484e4d51cc..52bad9a544a0 100644 --- a/arch/arm/configs/colibri_pxa270_defconfig +++ b/arch/arm/configs/colibri_pxa270_defconfig @@ -49,7 +49,6 @@ CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m CONFIG_CFG80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_CONNECTOR=y CONFIG_MTD=y CONFIG_MTD_BLOCK=y @@ -102,7 +101,6 @@ CONFIG_WATCHDOG=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_PXA=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig index d282e8b0bf33..446134c70a33 100644 --- a/arch/arm/configs/colibri_pxa300_defconfig +++ b/arch/arm/configs/colibri_pxa300_defconfig @@ -14,7 +14,6 @@ CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_SYN_COOKIES=y CONFIG_IPV6=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y @@ -33,7 +32,6 @@ CONFIG_DEBUG_GPIO=y # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_PXA=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig index d398ae53aba7..e6df11e906ba 100644 --- a/arch/arm/configs/collie_defconfig +++ b/arch/arm/configs/collie_defconfig @@ -63,7 +63,6 @@ CONFIG_MCP_UCB1200_TS=y CONFIG_FB=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_SA1100=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig index d99725984947..e4f6442588e7 100644 --- a/arch/arm/configs/corgi_defconfig +++ b/arch/arm/configs/corgi_defconfig @@ -81,7 +81,6 @@ CONFIG_BT_HCIBT3C=m CONFIG_BT_HCIBLUECARD=m CONFIG_BT_HCIBTUART=m CONFIG_BT_HCIVHCI=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -132,7 +131,6 @@ CONFIG_SPI=y CONFIG_SPI_PXA2XX=y CONFIG_FB=y CONFIG_FB_W100=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_CORGI=y CONFIG_BACKLIGHT_CLASS_DEVICE=y diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 4a8cad4d3707..9a32a8c0f873 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -45,6 +45,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_PERFORMANCE=m CONFIG_CPU_FREQ_GOV_POWERSAVE=m CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPUFREQ_DT=m CONFIG_CPU_IDLE=y CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 2f01e84b3d8c..e70c997d5f4c 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -31,7 +31,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig index 61228a25ba8d..d08f02014755 100644 --- a/arch/arm/configs/em_x270_defconfig +++ b/arch/arm/configs/em_x270_defconfig @@ -41,7 +41,6 @@ CONFIG_BT_BNEP=m CONFIG_BT_HIDP=m CONFIG_BT_HCIBTUSB=m CONFIG_LIB80211=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y @@ -101,7 +100,6 @@ CONFIG_FB=y CONFIG_FB_PXA=y CONFIG_FB_PXA_PARAMETERS=y CONFIG_FB_MBX=m -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_TDO24M=y # CONFIG_BACKLIGHT_GENERIC is not set diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig index 14889a785f07..ef2d2a820c30 100644 --- a/arch/arm/configs/ep93xx_defconfig +++ b/arch/arm/configs/ep93xx_defconfig @@ -50,7 +50,6 @@ CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TUNNEL is not set # CONFIG_INET6_XFRM_MODE_BEET is not set # CONFIG_IPV6_SIT is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig index b85575867d21..56452fa03d56 100644 --- a/arch/arm/configs/eseries_pxa_defconfig +++ b/arch/arm/configs/eseries_pxa_defconfig @@ -40,7 +40,6 @@ CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_MAC80211_RC_PID=y # CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set CONFIG_MTD=m CONFIG_MTD_RAW_NAND=m @@ -74,7 +73,6 @@ CONFIG_MFD_TC6393XB=y CONFIG_FB=y CONFIG_FB_PXA=y CONFIG_FB_W100=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 9b959afaaa12..2e6a863d25aa 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -1,22 +1,16 @@ CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y CONFIG_PERF_EVENTS=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_EXYNOS=y -CONFIG_ARCH_EXYNOS3=y CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y CONFIG_SMP=y CONFIG_BIG_LITTLE=y CONFIG_NR_CPUS=8 -CONFIG_PREEMPT=y -CONFIG_AEABI=y CONFIG_HIGHMEM=y -CONFIG_CMA=y CONFIG_SECCOMP=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -38,6 +32,16 @@ CONFIG_NEON=y CONFIG_KERNEL_MODE_NEON=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA256_ARM=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -61,10 +65,7 @@ CONFIG_BT_HCIBTSDIO=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y -CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_INTEL=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIBCM203X=m @@ -87,8 +88,6 @@ CONFIG_NFC_SHDLC=y CONFIG_NFC_S3FWRN5_I2C=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DMA_CMA=y -CONFIG_CMA_SIZE_MBYTES=96 CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y @@ -156,8 +155,6 @@ CONFIG_THERMAL_EMULATION=y CONFIG_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y CONFIG_MFD_CROS_EC=y -CONFIG_CROS_EC_I2C=y -CONFIG_CROS_EC_SPI=y CONFIG_MFD_MAX14577=y CONFIG_MFD_MAX77686=y CONFIG_MFD_MAX77693=y @@ -216,6 +213,8 @@ CONFIG_DRM_NXP_PTN3460=y CONFIG_DRM_PARADE_PS8622=y CONFIG_DRM_SII9234=y CONFIG_DRM_TOSHIBA_TC358764=y +CONFIG_DRM_LIMA=y +CONFIG_DRM_PANFROST=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_PWM=y @@ -283,16 +282,16 @@ CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y -CONFIG_CROS_EC_CHARDEV=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_SPI=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_PM_DEVFREQ=y +CONFIG_EXYNOS_IOMMU=y CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y -CONFIG_EXYNOS_IOMMU=y CONFIG_EXTCON=y CONFIG_EXTCON_MAX14577=y CONFIG_EXTCON_MAX77693=y @@ -320,21 +319,9 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y -CONFIG_PRINTK_TIME=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_SOFTLOCKUP_DETECTOR=y -# CONFIG_DETECT_HUNG_TASK is not set -CONFIG_PROVE_LOCKING=y -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_DEBUG_USER=y -CONFIG_CRYPTO_RSA=m -CONFIG_CRYPTO_DH=m CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_DH=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_XTS=m CONFIG_CRYPTO_MD5=m @@ -349,12 +336,18 @@ CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_DEV_EXYNOS_RNG=y CONFIG_CRYPTO_DEV_S5P=y -CONFIG_ARM_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM_NEON=m -CONFIG_CRYPTO_SHA256_ARM=m -CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_AES_ARM_BS=m -CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_CRC_CCITT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=96 CONFIG_FONTS=y CONFIG_FONT_7x14=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_PROVE_LOCKING=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig index e3afca5bd9d6..4e28771beecd 100644 --- a/arch/arm/configs/ezx_defconfig +++ b/arch/arm/configs/ezx_defconfig @@ -160,7 +160,6 @@ CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_CONNECTOR=m CONFIG_MTD=y @@ -247,7 +246,6 @@ CONFIG_FB=y CONFIG_FB_PXA=y CONFIG_FB_PXA_OVERLAY=y CONFIG_FB_PXA_PARAMETERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y diff --git a/arch/arm/configs/gemini_defconfig b/arch/arm/configs/gemini_defconfig index ef9aae89907d..f012e81a2fe4 100644 --- a/arch/arm/configs/gemini_defconfig +++ b/arch/arm/configs/gemini_defconfig @@ -22,7 +22,6 @@ CONFIG_PM=y CONFIG_NET=y CONFIG_UNIX=y CONFIG_INET=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_MTD=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig index 175881b7da7c..4d91e41cb628 100644 --- a/arch/arm/configs/h3600_defconfig +++ b/arch/arm/configs/h3600_defconfig @@ -25,7 +25,6 @@ CONFIG_IRLAN=m CONFIG_IRNET=m CONFIG_IRCOMM=m # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig index e90d1dfeb188..3946c6087327 100644 --- a/arch/arm/configs/h5000_defconfig +++ b/arch/arm/configs/h5000_defconfig @@ -32,7 +32,6 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig index 9b779e13e05d..770469f61c3e 100644 --- a/arch/arm/configs/imote2_defconfig +++ b/arch/arm/configs/imote2_defconfig @@ -138,7 +138,6 @@ CONFIG_BRIDGE=m # CONFIG_BRIDGE_IGMP_SNOOPING is not set CONFIG_IEEE802154=y # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_FW_LOADER=m @@ -228,7 +227,6 @@ CONFIG_FB=y CONFIG_FB_PXA=y CONFIG_FB_PXA_OVERLAY=y CONFIG_FB_PXA_PARAMETERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index f2cf0722e8e1..2b2d617e279d 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -47,7 +47,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_IMX_WEIM=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 8116648a8efd..a53b29251ed4 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -57,6 +57,7 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPUFREQ_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_VFP=y @@ -211,9 +212,11 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_FSL_DSPI=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SIOX=m CONFIG_GPIO_MAX732X=y CONFIG_GPIO_MC9S08DZ60=y CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCF857X=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_74X164=y CONFIG_POWER_RESET=y @@ -223,6 +226,7 @@ CONFIG_POWER_SUPPLY=y CONFIG_SENSORS_MC13783_ADC=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_IIO_HWMON=y +CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y @@ -266,6 +270,7 @@ CONFIG_VIDEO_CODA=m CONFIG_VIDEO_IMX_PXP=y # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_OV2680=m CONFIG_VIDEO_OV5640=m CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y @@ -399,11 +404,15 @@ CONFIG_MPL3115=y CONFIG_PWM=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX27=y +CONFIG_PWM_IMX_TPM=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_VF610_OCOTP=y +CONFIG_NVMEM_SNVS_LPGPR=y CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_MUX_MMIO=y +CONFIG_SIOX=m +CONFIG_SIOX_BUS_GPIO=m CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig index 747550c7af2f..2f0a762dc3a0 100644 --- a/arch/arm/configs/integrator_defconfig +++ b/arch/arm/configs/integrator_defconfig @@ -61,7 +61,6 @@ CONFIG_FB_MODE_HELPERS=y CONFIG_FB_MATROX=y CONFIG_FB_MATROX_MILLENIUM=y CONFIG_FB_MATROX_MYSTIQUE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set CONFIG_LOGO=y diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig index a73b6a31a4ab..30cdb287e1b4 100644 --- a/arch/arm/configs/iop13xx_defconfig +++ b/arch/arm/configs/iop13xx_defconfig @@ -34,7 +34,6 @@ CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TUNNEL is not set # CONFIG_INET6_XFRM_MODE_BEET is not set # CONFIG_IPV6_SIT is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig index f63362b665eb..18a21faa834c 100644 --- a/arch/arm/configs/iop32x_defconfig +++ b/arch/arm/configs/iop32x_defconfig @@ -30,7 +30,6 @@ CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TUNNEL is not set # CONFIG_INET6_XFRM_MODE_BEET is not set # CONFIG_IPV6_SIT is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig index d22f832ccfd6..089eca43214a 100644 --- a/arch/arm/configs/iop33x_defconfig +++ b/arch/arm/configs/iop33x_defconfig @@ -28,7 +28,6 @@ CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TUNNEL is not set # CONFIG_INET6_XFRM_MODE_BEET is not set # CONFIG_IPV6_SIT is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig index 39ebcce3bc2f..27e7c0714b96 100644 --- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -104,7 +104,6 @@ CONFIG_NET_CLS_RSVP6=m CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y CONFIG_NET_PKTGEN=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig index 65d37ad6e6b8..9f079be2b84b 100644 --- a/arch/arm/configs/jornada720_defconfig +++ b/arch/arm/configs/jornada720_defconfig @@ -24,7 +24,6 @@ CONFIG_IRDA=m CONFIG_IRLAN=m CONFIG_IRCOMM=m CONFIG_SA1100_FIR=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_SD=y @@ -47,7 +46,6 @@ CONFIG_LEGACY_PTY_COUNT=32 # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_S1D13XXX=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig index 72fee57aad2f..3d5f5b501330 100644 --- a/arch/arm/configs/keystone_defconfig +++ b/arch/arm/configs/keystone_defconfig @@ -115,7 +115,6 @@ CONFIG_VLAN_8021Q=y CONFIG_CAN=m CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DMA_CMA=y diff --git a/arch/arm/configs/ks8695_defconfig b/arch/arm/configs/ks8695_defconfig index b8b91d790e9b..df62d4dfbbb7 100644 --- a/arch/arm/configs/ks8695_defconfig +++ b/arch/arm/configs/ks8695_defconfig @@ -28,7 +28,6 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig index e3d5e15d66d1..e518168a0627 100644 --- a/arch/arm/configs/lpc18xx_defconfig +++ b/arch/arm/configs/lpc18xx_defconfig @@ -119,7 +119,6 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_DRM=y CONFIG_DRM_PL111=y CONFIG_FB_MODE_HELPERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index 4b3b2c693c29..0cdc6c7974b3 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -40,7 +40,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FW_LOADER is not set @@ -110,7 +109,6 @@ CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PL111=y CONFIG_FB_MODE_HELPERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig index de5be2fc7306..e6486c959220 100644 --- a/arch/arm/configs/magician_defconfig +++ b/arch/arm/configs/magician_defconfig @@ -53,7 +53,6 @@ CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m CONFIG_BT_HCIBTUSB=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -96,7 +95,6 @@ CONFIG_FB=y CONFIG_FB_PXA=y CONFIG_FB_PXA_OVERLAY=y CONFIG_FB_W100=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 7d26ca0b1302..301f29a1fcc3 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -4,6 +4,16 @@ CONFIG_POSIX_MQUEUE=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_COMPAT_BRK is not set +CONFIG_ARCH_S3C24XX=y +CONFIG_S3C_ADC=y +CONFIG_S3C24XX_PWM=y +# CONFIG_CPU_S3C2410 is not set +CONFIG_CPU_S3C2440=y +CONFIG_MACH_MINI2440=y +CONFIG_AEABI=y +CONFIG_KEXEC=y +CONFIG_CPU_IDLE=y +CONFIG_APM_EMULATION=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y @@ -16,17 +26,7 @@ CONFIG_MINIX_SUBPARTITION=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_UNIXWARE_DISKLABEL=y CONFIG_LDM_PARTITION=y -CONFIG_ARCH_S3C24XX=y -# CONFIG_CPU_S3C2410 is not set -CONFIG_CPU_S3C2440=y -CONFIG_MACH_MINI2440=y -CONFIG_S3C_ADC=y -CONFIG_S3C24XX_PWM=y -CONFIG_AEABI=y -CONFIG_KEXEC=y -CONFIG_CPU_IDLE=y CONFIG_BINFMT_MISC=m -CONFIG_APM_EMULATION=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -46,9 +46,6 @@ CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set CONFIG_INET_DIAG=m # CONFIG_IPV6 is not set CONFIG_NETFILTER=y @@ -76,7 +73,6 @@ CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_CONNECTOR=m CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y @@ -126,7 +122,6 @@ CONFIG_LIBERTAS=m CONFIG_LIBERTAS_SDIO=m CONFIG_ZD1211RW=m CONFIG_ZD1211RW_DEBUG=y -CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m # CONFIG_KEYBOARD_ATKBD is not set @@ -160,7 +155,6 @@ CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y CONFIG_FB_S3C2410=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y @@ -174,12 +168,9 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_SOUND=y CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_SEQUENCER=m CONFIG_SND_SEQ_DUMMY=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_DYNAMIC_MINORS=y # CONFIG_SND_DRIVERS is not set # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set @@ -297,13 +288,6 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m -CONFIG_DEBUG_INFO=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_USER=y CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m @@ -342,3 +326,10 @@ CONFIG_LIBCRC32C=m CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_MINI_4x6=y +CONFIG_DEBUG_INFO=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig index 94deb0ed0541..a5e8d2235a1a 100644 --- a/arch/arm/configs/mmp2_defconfig +++ b/arch/arm/configs/mmp2_defconfig @@ -50,7 +50,6 @@ CONFIG_MFD_MAX8925=y CONFIG_REGULATOR=y CONFIG_REGULATOR_MAX8649=y CONFIG_REGULATOR_MAX8925=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_MAX8925=y diff --git a/arch/arm/configs/moxart_defconfig b/arch/arm/configs/moxart_defconfig index 6a11669fa536..9b98761e51c9 100644 --- a/arch/arm/configs/moxart_defconfig +++ b/arch/arm/configs/moxart_defconfig @@ -38,7 +38,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index 63b5a8824f0f..201237002c65 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -72,7 +72,6 @@ CONFIG_NET_DSA=y CONFIG_NET_PKTGEN=m CONFIG_CFG80211=y CONFIG_MAC80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_IMX_WEIM=y @@ -96,8 +95,6 @@ CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_ATMEL_TCLIB=y CONFIG_ATMEL_SSC=m -CONFIG_ASPEED_LPC_CTRL=m -CONFIG_ASPEED_LPC_SNOOP=m CONFIG_EEPROM_AT24=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y @@ -178,10 +175,12 @@ CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SOC_CAMERA=y +CONFIG_VIDEO_ASPEED=m CONFIG_VIDEO_ATMEL_ISI=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=m CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_ASPEED_GFX=m CONFIG_FB_IMX=y CONFIG_FB_ATMEL=y CONFIG_BACKLIGHT_ATMEL_LCDC=y @@ -226,6 +225,8 @@ CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_GADGET=y CONFIG_USB_AT91=m CONFIG_USB_ATMEL_USBA=m +CONFIG_USB_ASPEED_VHUB=m +CONFIG_USB_CONFIGFS=m CONFIG_MMC=y CONFIG_SDIO_UART=y CONFIG_MMC_ATMELMCI=y @@ -245,11 +246,15 @@ CONFIG_RTC_DRV_RV3029C2=m CONFIG_RTC_DRV_AT91RM9200=m CONFIG_RTC_DRV_AT91SAM9=m CONFIG_RTC_DRV_MV=y +CONFIG_RTC_DRV_ASPEED=m CONFIG_DMADEVICES=y CONFIG_AT_HDMAC=y CONFIG_MV_XOR=y CONFIG_STAGING=y CONFIG_FB_XGI=y +CONFIG_ASPEED_LPC_CTRL=m +CONFIG_ASPEED_LPC_SNOOP=m +CONFIG_ASPEED_P2A_CTRL=m CONFIG_IIO=m CONFIG_ASPEED_ADC=m CONFIG_AT91_ADC=m diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 6b748f214eae..6a40bc2ef271 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -413,6 +413,7 @@ CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_AS3722=y CONFIG_PINCTRL_RZA2=y +CONFIG_PINCTRL_STMFX=y CONFIG_PINCTRL_PALMAS=y CONFIG_PINCTRL_APQ8064=y CONFIG_PINCTRL_APQ8084=y @@ -656,6 +657,8 @@ CONFIG_DRM_VC4=m CONFIG_DRM_ETNAVIV=m CONFIG_DRM_MXSFB=m CONFIG_DRM_PL111=m +CONFIG_DRM_LIMA=m +CONFIG_DRM_PANFROST=m CONFIG_FB_EFI=y CONFIG_FB_WM8505=y CONFIG_FB_SH_MOBILE_LCDC=y @@ -940,7 +943,6 @@ CONFIG_ARCH_TEGRA_2x_SOC=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_ARCH_TEGRA_114_SOC=y CONFIG_ARCH_TEGRA_124_SOC=y -CONFIG_PM_DEVFREQ=y CONFIG_ARM_TEGRA_DEVFREQ=m CONFIG_TI_AEMIF=y CONFIG_IIO=y diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index e9567513f068..b39b1300a459 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -36,7 +36,6 @@ CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set CONFIG_NET_PKTGEN=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig index 0e5577a31851..226f2e97c6e2 100644 --- a/arch/arm/configs/mvebu_v5_defconfig +++ b/arch/arm/configs/mvebu_v5_defconfig @@ -62,7 +62,6 @@ CONFIG_NET_SWITCHDEV=y CONFIG_NET_PKTGEN=m CONFIG_CFG80211=y CONFIG_MAC80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index 3ac2e84fdeaa..cddce57fe4b9 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -40,7 +40,6 @@ CONFIG_BT=y CONFIG_BT_MRVL=y CONFIG_BT_MRVL_SDIO=y CONFIG_CFG80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index ed570a0d1f2a..2773899c21b3 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -96,7 +96,6 @@ CONFIG_DRM=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig deleted file mode 100644 index cc5c5f9ef720..000000000000 --- a/arch/arm/configs/netx_defconfig +++ /dev/null @@ -1,80 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_ARCH_NETX=y -CONFIG_MACH_NXDKN=y -CONFIG_MACH_NXDB500=y -CONFIG_MACH_NXEB500HMI=y -CONFIG_PREEMPT=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySMX0,115200" -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_NET_IPGRE=m -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_NETFILTER=y -CONFIG_NET_PKTGEN=m -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PLATRAM=y -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_NETX=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_NETX=y -CONFIG_SERIAL_NETX_CONSOLE=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FB_ARMCLCD=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_RTC_CLASS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRC_CCITT=m -CONFIG_LIBCRC32C=m diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index cfc094189d09..3f35761dc9ff 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -45,7 +45,6 @@ CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIVHCI=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_TESTS=m CONFIG_MTD_CMDLINE_PARTS=y @@ -98,7 +97,6 @@ CONFIG_REGULATOR=y CONFIG_DRM=y CONFIG_DRM_PANEL_TPO_TPG110=y CONFIG_DRM_PL111=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y diff --git a/arch/arm/configs/nuc910_defconfig b/arch/arm/configs/nuc910_defconfig index c0d152c02fba..63dba62c3326 100644 --- a/arch/arm/configs/nuc910_defconfig +++ b/arch/arm/configs/nuc910_defconfig @@ -13,7 +13,6 @@ CONFIG_AEABI=y CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M" CONFIG_KEXEC=y CONFIG_FPE_NWFPE=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/arm/configs/nuc950_defconfig b/arch/arm/configs/nuc950_defconfig index 8dde1186c2ef..cb5a8788ebe8 100644 --- a/arch/arm/configs/nuc950_defconfig +++ b/arch/arm/configs/nuc950_defconfig @@ -19,7 +19,6 @@ CONFIG_KEXEC=y CONFIG_FPE_NWFPE=y CONFIG_BINFMT_AOUT=y CONFIG_BINFMT_MISC=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/arm/configs/nuc960_defconfig b/arch/arm/configs/nuc960_defconfig index 6bb784f8eb5b..f7af84e23a05 100644 --- a/arch/arm/configs/nuc960_defconfig +++ b/arch/arm/configs/nuc960_defconfig @@ -19,7 +19,6 @@ CONFIG_KEXEC=y CONFIG_FPE_NWFPE=y CONFIG_BINFMT_AOUT=y CONFIG_BINFMT_MISC=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 82af77c093f1..0c43c589f191 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -79,7 +79,6 @@ CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=y CONFIG_BT_HIDP=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_CONNECTOR=y @@ -154,7 +153,6 @@ CONFIG_FB_OMAP_LCDC_EXTERNAL=y CONFIG_FB_OMAP_LCDC_HWA742=y CONFIG_FB_OMAP_MANUAL_UPDATE=y CONFIG_FB_OMAP_LCD_MIPID=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index 077e0fde1ff9..4bdbb036ac26 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -59,7 +59,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set CONFIG_NET_DSA=y CONFIG_NET_PKTGEN=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig index e0a614272561..4a3fd82c2a0c 100644 --- a/arch/arm/configs/palmz72_defconfig +++ b/arch/arm/configs/palmz72_defconfig @@ -30,7 +30,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_EVDEV=y @@ -49,7 +48,6 @@ CONFIG_PDA_POWER=y # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_PXA=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig index 9c88a193490c..a8c53228b0c1 100644 --- a/arch/arm/configs/pcm027_defconfig +++ b/arch/arm/configs/pcm027_defconfig @@ -35,7 +35,6 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig index 7cc8e8e4d296..be19aa127595 100644 --- a/arch/arm/configs/prima2_defconfig +++ b/arch/arm/configs/prima2_defconfig @@ -16,7 +16,6 @@ CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_KEXEC=y CONFIG_BINFMT_MISC=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig index e7c7b91b6de2..0947f022954d 100644 --- a/arch/arm/configs/pxa168_defconfig +++ b/arch/arm/configs/pxa168_defconfig @@ -24,7 +24,6 @@ CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_BLK_DEV is not set diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig index 7681eea60127..06bbc7a59b60 100644 --- a/arch/arm/configs/pxa3xx_defconfig +++ b/arch/arm/configs/pxa3xx_defconfig @@ -26,7 +26,6 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_MTD=y @@ -72,7 +71,6 @@ CONFIG_REGULATOR_DEBUG=y CONFIG_REGULATOR_DA903X=y CONFIG_FB=y CONFIG_FB_PXA=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_TDO24M=y CONFIG_BACKLIGHT_CLASS_DEVICE=y diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig index 3aff71e6dae5..b21196372158 100644 --- a/arch/arm/configs/pxa910_defconfig +++ b/arch/arm/configs/pxa910_defconfig @@ -24,7 +24,6 @@ CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_BLK_DEV is not set diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index 07ebbdce3645..787c3f9be414 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -156,7 +156,6 @@ CONFIG_MAC80211=m CONFIG_RFKILL=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_CONNECTOR=y @@ -462,7 +461,6 @@ CONFIG_PXA3XX_GCU=m CONFIG_FB_MBX=m CONFIG_FB_VIRTUAL=m CONFIG_FB_SIMPLE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CORGI=m CONFIG_LCD_PLATFORM=m CONFIG_LCD_TOSA=m diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index c1854751c99a..34433bf5885d 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -37,6 +37,7 @@ CONFIG_ARM_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -146,12 +147,13 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_MEDIA_SUPPORT=y CONFIG_DRM=y +CONFIG_DRM_PANEL_SIMPLE=y CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_LM3630A=y CONFIG_BACKLIGHT_LP855X=y CONFIG_SOUND=y CONFIG_SND=y @@ -183,6 +185,7 @@ CONFIG_USB_CONFIGFS_NCM=y CONFIG_USB_CONFIGFS_ECM=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_ULPI_BUS=y +CONFIG_USB_ETH=m CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y @@ -262,6 +265,8 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_INFO=y diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig index cc9fa24d4b8f..8a056cc0c1ec 100644 --- a/arch/arm/configs/realview_defconfig +++ b/arch/arm/configs/realview_defconfig @@ -34,7 +34,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_AFS_PARTS=y @@ -65,7 +64,6 @@ CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PL111=y CONFIG_FB_MODE_HELPERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 39c648594d93..95b5a4ffddea 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -4,13 +4,8 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_BLK_DEV_INITRD=y CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_SOLARIS_X86_PARTITION=y CONFIG_ARCH_S3C24XX=y +CONFIG_S3C_ADC=y CONFIG_CPU_S3C2412=y CONFIG_CPU_S3C2416=y CONFIG_CPU_S3C2440=y @@ -40,13 +35,18 @@ CONFIG_ARCH_S3C2440=y CONFIG_MACH_NEO1973_GTA02=y CONFIG_MACH_RX1950=y CONFIG_MACH_SMDK2443=y -CONFIG_S3C_ADC=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0" CONFIG_FPE_NWFPE=y CONFIG_FPE_NWFPE_XP=y CONFIG_APM_EMULATION=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_SOLARIS_X86_PARTITION=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -74,7 +74,6 @@ CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m CONFIG_IPV6_TUNNEL=m CONFIG_NETFILTER=y CONFIG_NF_CONNTRACK=m @@ -129,7 +128,6 @@ CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m CONFIG_IP_VS=m -CONFIG_NF_CONNTRACK_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -148,7 +146,6 @@ CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -181,11 +178,10 @@ CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -291,11 +287,8 @@ CONFIG_BACKLIGHT_PWM=m CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_SOUND=y CONFIG_SND=y -CONFIG_SND_SEQUENCER=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_SEQUENCER_OSS=y CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_SEQUENCER=m # CONFIG_SND_DRIVERS is not set # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index 6e2656567da6..59a258d504aa 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -2,9 +2,6 @@ CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_MULTI_V6=y # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_S3C64XX=y @@ -18,10 +15,11 @@ CONFIG_MACH_HMT=y CONFIG_MACH_SMARTQ5=y CONFIG_MACH_SMARTQ7=y CONFIG_MACH_WLF_CRAGG_6410=y -CONFIG_AEABI=y CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x51000000,6M ramdisk_size=6144" CONFIG_VFP=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_S3C2410=y @@ -40,15 +38,12 @@ CONFIG_SPI_GPIO=m CONFIG_SPI_S3C64XX=m CONFIG_FB=y CONFIG_FB_S3C=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_LTV350QV=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_SOUND=y CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m CONFIG_SND_SOC=m CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y @@ -61,8 +56,8 @@ CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_PL2303=m CONFIG_MMC=y -CONFIG_MMC_DEBUG=y CONFIG_SDIO_UART=y +CONFIG_MMC_DEBUG=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S3C=y CONFIG_RTC_CLASS=y diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig index fd4f28aabda6..70919716f815 100644 --- a/arch/arm/configs/s5pv210_defconfig +++ b/arch/arm/configs/s5pv210_defconfig @@ -40,7 +40,6 @@ CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_BCM=y CONFIG_CFG80211=m CONFIG_MAC80211=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_BLK_DEV_LOOP=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index d5341b0bd88d..ef785340e6f8 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -56,7 +56,6 @@ CONFIG_CAN_M_CAN=y CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_MAC80211_LEDS=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set @@ -154,7 +153,6 @@ CONFIG_SOC_CAMERA_OV2640=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index eb02ba9ec6e6..c6c70355141c 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -197,7 +197,6 @@ CONFIG_PWM=y CONFIG_PWM_RCAR=y CONFIG_PWM_RENESAS_TPU=y CONFIG_RESET_CONTROLLER=y -CONFIG_GENERIC_PHY=y CONFIG_PHY_RCAR_GEN2=y CONFIG_PHY_RCAR_GEN3_USB2=y # CONFIG_DNOTIFY is not set diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index 6701a975e785..fe2e1e82e233 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -44,7 +44,6 @@ CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCIE_ALTERA=y CONFIG_PCIE_ALTERA_MSI=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig index 8ee3679ca8b2..3b206a31902f 100644 --- a/arch/arm/configs/spear13xx_defconfig +++ b/arch/arm/configs/spear13xx_defconfig @@ -28,7 +28,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_NET_IPIP=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig index ddd73b25f75e..fc5f71c765ed 100644 --- a/arch/arm/configs/spear3xx_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -13,7 +13,6 @@ CONFIG_MACH_SPEAR310=y CONFIG_MACH_SPEAR320=y CONFIG_BINFMT_MISC=y CONFIG_NET=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y CONFIG_MTD_BLOCK=y @@ -54,7 +53,6 @@ CONFIG_WATCHDOG=y CONFIG_ARM_SP805_WATCHDOG=y CONFIG_DRM=y CONFIG_DRM_PL111=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig index 5b410f0a365b..52a56b8ce6a7 100644 --- a/arch/arm/configs/spear6xx_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -10,7 +10,6 @@ CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR6XX=y CONFIG_BINFMT_MISC=y CONFIG_NET=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig index f6d2f674517c..4fb51d665abb 100644 --- a/arch/arm/configs/spitz_defconfig +++ b/arch/arm/configs/spitz_defconfig @@ -78,7 +78,6 @@ CONFIG_BT_HCIBT3C=m CONFIG_BT_HCIBLUECARD=m CONFIG_BT_HCIBTUART=m CONFIG_BT_HCIVHCI=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -126,7 +125,6 @@ CONFIG_SPI=y CONFIG_SPI_PXA2XX=y CONFIG_FB=y CONFIG_FB_PXA=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_CORGI=y CONFIG_BACKLIGHT_CLASS_DEVICE=y diff --git a/arch/arm/configs/tango4_defconfig b/arch/arm/configs/tango4_defconfig index 68eb16e583ac..cbc9ade78f14 100644 --- a/arch/arm/configs/tango4_defconfig +++ b/arch/arm/configs/tango4_defconfig @@ -33,7 +33,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig index d0a9e5dd9135..3a9503fe84cb 100644 --- a/arch/arm/configs/tct_hammer_defconfig +++ b/arch/arm/configs/tct_hammer_defconfig @@ -22,7 +22,6 @@ CONFIG_FPE_NWFPE=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_MTD=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig index ecad22501b48..d66f0c287d41 100644 --- a/arch/arm/configs/trizeps4_defconfig +++ b/arch/arm/configs/trizeps4_defconfig @@ -136,7 +136,6 @@ CONFIG_SA1100_WATCHDOG=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_PXA=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig index bedf397c75de..8223397db047 100644 --- a/arch/arm/configs/u300_defconfig +++ b/arch/arm/configs/u300_defconfig @@ -22,7 +22,6 @@ CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072" CONFIG_CPU_IDLE=y # CONFIG_SUSPEND is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y @@ -43,7 +42,6 @@ CONFIG_WATCHDOG=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_FB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_USB_SUPPORT is not set diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index e2151a7aaf49..e6b98b6eb88d 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -38,7 +38,6 @@ CONFIG_CFG80211_DEBUGFS=y CONFIG_MAC80211=y CONFIG_MAC80211_LEDS=y CONFIG_CAIF=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_BLK_DEV_RAM=y diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig index 5282324c7cef..fe4d4b596585 100644 --- a/arch/arm/configs/versatile_defconfig +++ b/arch/arm/configs/versatile_defconfig @@ -62,7 +62,6 @@ CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_DUMB_VGA_DAC=y CONFIG_DRM_PL111=y CONFIG_FB_MODE_HELPERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_LOGO=y CONFIG_SOUND=y diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig index 484d77a7f589..25753552277a 100644 --- a/arch/arm/configs/vexpress_defconfig +++ b/arch/arm/configs/vexpress_defconfig @@ -45,7 +45,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_WIRELESS is not set CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DMA_CMA=y CONFIG_MTD=y @@ -86,7 +85,6 @@ CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_SII902X=y CONFIG_DRM_PL111=y CONFIG_FB_MODE_HELPERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig index 070e5074f1ee..2ff16168d9c2 100644 --- a/arch/arm/configs/viper_defconfig +++ b/arch/arm/configs/viper_defconfig @@ -41,7 +41,6 @@ CONFIG_BT_BNEP=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y @@ -110,7 +109,6 @@ CONFIG_WATCHDOG=y CONFIG_FB=y CONFIG_FB_PXA=m CONFIG_FB_PXA_PARAMETERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_PWM=m # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig index 2eda24635e65..f1fbdfc5c8c6 100644 --- a/arch/arm/configs/xcep_defconfig +++ b/arch/arm/configs/xcep_defconfig @@ -43,7 +43,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set CONFIG_MTD_COMPLEX_MAPPINGS=y diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig index 09e7050d5653..aa3023c9a011 100644 --- a/arch/arm/configs/zeus_defconfig +++ b/arch/arm/configs/zeus_defconfig @@ -39,7 +39,6 @@ CONFIG_BT_HCIUART_BCSP=y CONFIG_CFG80211=m CONFIG_LIB80211=m CONFIG_MAC80211=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y @@ -110,7 +109,6 @@ CONFIG_WATCHDOG=y CONFIG_FB=y CONFIG_FB_PXA=m CONFIG_FB_PXA_PARAMETERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig index dfc061d87d2f..c4070c19ea6c 100644 --- a/arch/arm/configs/zx_defconfig +++ b/arch/arm/configs/zx_defconfig @@ -41,7 +41,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="console=ttyAMA0,115200 debug earlyprintk root=/dev/ram rw rootwait" #CONFIG_NET is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DMA_CMA=y diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 64714c869f9f..3cb6f22f510b 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -302,6 +302,8 @@ extern struct platform_device iop3xx_dma_1_channel; extern struct platform_device iop3xx_aau_channel; extern struct platform_device iop3xx_i2c0_device; extern struct platform_device iop3xx_i2c1_device; +extern struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup; +extern struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup; #endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index f11c35cf0b74..7a0596fcb2e7 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -30,7 +30,6 @@ * ISA I/O bus memory addresses are 1:1 with the physical address. */ #define isa_virt_to_bus virt_to_phys -#define isa_page_to_bus page_to_phys #define isa_bus_to_virt phys_to_virt /* diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 77e5582c2259..67d20712cb48 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -5,7 +5,7 @@ * Copyright (C) 1997-1999 Russell King * * Structure passed to kernel to tell it about the - * hardware it's running on. See Documentation/arm/Setup + * hardware it's running on. See Documentation/arm/setup.rst * for more info. */ #ifndef __ASMARM_SETUP_H diff --git a/arch/arm/include/debug/netx.S b/arch/arm/include/debug/netx.S deleted file mode 100644 index 08afc58885d3..000000000000 --- a/arch/arm/include/debug/netx.S +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks -*/ - -#define UART_DATA 0 -#define UART_FLAG 0x18 -#define UART_FLAG_BUSY (1 << 3) - - .macro addruart, rp, rv, tmp - ldr \rp, =CONFIG_DEBUG_UART_PHYS - ldr \rv, =CONFIG_DEBUG_UART_VIRT - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #UART_DATA] - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #UART_FLAG] - tst \rd, #UART_FLAG_BUSY - bne 1002b - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #UART_FLAG] - tst \rd, #UART_FLAG_BUSY - bne 1001b - .endm diff --git a/arch/arm/include/uapi/asm/setup.h b/arch/arm/include/uapi/asm/setup.h index 6b335a9ff8c8..25ceda63b284 100644 --- a/arch/arm/include/uapi/asm/setup.h +++ b/arch/arm/include/uapi/asm/setup.h @@ -9,7 +9,7 @@ * published by the Free Software Foundation. * * Structure passed to kernel to tell it about the - * hardware it's running on. See Documentation/arm/Setup + * hardware it's running on. See Documentation/arm/setup.rst * for more info. */ #ifndef _UAPI__ASMARM_SETUP_H diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 0b8cfdd60b90..858d4e541532 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -826,7 +826,7 @@ ENDPROC(__switch_to) * existing ones. This mechanism should be used only for things that are * really small and justified, and not be abused freely. * - * See Documentation/arm/kernel_user_helpers.txt for formal definitions. + * See Documentation/arm/kernel_user_helpers.rst for formal definitions. */ THUMB( .arm ) diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index b3d439c41c7b..deef17f34bd2 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -55,6 +55,13 @@ void *module_alloc(unsigned long size) } #endif +bool module_exit_section(const char *name) +{ + return strstarts(name, ".exit") || + strstarts(name, ".ARM.extab.exit") || + strstarts(name, ".ARM.exidx.exit"); +} + int apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, unsigned int relindex, struct module *module) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 0bff0176db2c..b25c54585048 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -31,7 +31,6 @@ else endif ifeq ($(CONFIG_ARCH_RPC),y) - lib-y += ecard.o io-acorn.o floppydma.o AFLAGS_delay-loop.o += -march=armv4 endif diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index da85e64143e9..d5af6aedc02c 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -15,6 +15,7 @@ #include <linux/suspend.h> #include <linux/clk/at91_pmc.h> +#include <linux/platform_data/atmel.h> #include <asm/cacheflush.h> #include <asm/fncpy.h> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 4ef1e55f4a0b..5e5f1fabc3d4 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -208,6 +208,7 @@ config ARCH_BCM_63XX config ARCH_BRCMSTB bool "Broadcom BCM7XXX based boards" depends on ARCH_MULTI_V7 + select ARCH_HAS_RESET_CONTROLLER select ARM_GIC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER @@ -217,6 +218,7 @@ config ARCH_BRCMSTB select ZONE_DMA if ARM_LPAE select SOC_BRCMSTB select SOC_BUS + select PINCTRL help Say Y if you intend to run the kernel on a Broadcom ARM-based STB chipset. diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 8fd23b263c60..b59c813b1af4 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -40,9 +40,6 @@ obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o # Support for secure monitor traps obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o -ifeq ($(call as-instr,.arch_extension sec,as_has_sec),as_has_sec) -CFLAGS_bcm_kona_smc.o += -Wa,-march=armv7-a+sec -DREQUIRES_SEC -endif # BCM2835 obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o diff --git a/arch/arm/mach-bcm/bcm63xx_smp.c b/arch/arm/mach-bcm/bcm63xx_smp.c index 83dd0c10fa47..641e1f8fcf5e 100644 --- a/arch/arm/mach-bcm/bcm63xx_smp.c +++ b/arch/arm/mach-bcm/bcm63xx_smp.c @@ -141,6 +141,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu, * return */ ret = bcm63xx_pmb_power_on_cpu(dn); + of_node_put(dn); if (ret) goto out; out: diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index a55a7ecf146a..541e850a736c 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -125,9 +125,7 @@ static int bcm_kona_do_smc(u32 service_id, u32 buffer_phys) __asmeq("%2", "r4") __asmeq("%3", "r5") __asmeq("%4", "r6") -#ifdef REQUIRES_SEC ".arch_extension sec\n" -#endif " smc #0\n" : "=r" (ip), "=r" (r0) : "r" (r4), "r" (r5), "r" (r6) diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c index b81bb386951d..1238ac801530 100644 --- a/arch/arm/mach-bcm/board_bcm281xx.c +++ b/arch/arm/mach-bcm/board_bcm281xx.c @@ -38,6 +38,7 @@ static void bcm281xx_restart(enum reboot_mode mode, const char *cmd) return; } base = of_iomap(np_wdog, 0); + of_node_put(np_wdog); if (!base) { pr_emerg("Couldn't map brcm,kona-wdt\n"); return; diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c index 12379960e982..4555f21e7077 100644 --- a/arch/arm/mach-bcm/platsmp-brcmstb.c +++ b/arch/arm/mach-bcm/platsmp-brcmstb.c @@ -334,11 +334,14 @@ static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus) rc = setup_hifcpubiuctrl_regs(np); if (rc) - return; + goto out_put_node; rc = setup_hifcont_regs(np); if (rc) - return; + goto out_put_node; + +out_put_node: + of_node_put(np); } static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle) diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 31ae3be5741d..0628e7d7dcf3 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -631,13 +631,12 @@ static void da850_evm_bb_keys_init(unsigned gpio) } } -#define DA850_N_BB_USER_LED 2 - static struct gpio_led da850_evm_bb_leds[] = { - [0 ... DA850_N_BB_USER_LED - 1] = { - .active_low = 1, - .gpio = -1, /* assigned at runtime */ - .name = NULL, /* assigned at runtime */ + { + .name = "user_led2", + }, + { + .name = "user_led1", }, }; @@ -646,6 +645,20 @@ static struct gpio_led_platform_data da850_evm_bb_leds_pdata = { .num_leds = ARRAY_SIZE(da850_evm_bb_leds), }; +static struct gpiod_lookup_table da850_evm_bb_leds_gpio_table = { + .dev_id = "leds-gpio", + .table = { + GPIO_LOOKUP_IDX("i2c-bb-expander", + DA850_EVM_BB_EXP_USER_LED2, NULL, + 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("i2c-bb-expander", + DA850_EVM_BB_EXP_USER_LED2 + 1, NULL, + 1, GPIO_ACTIVE_LOW), + + { }, + }, +}; + static struct platform_device da850_evm_bb_leds_device = { .name = "leds-gpio", .id = -1, @@ -654,20 +667,6 @@ static struct platform_device da850_evm_bb_leds_device = { } }; -static void da850_evm_bb_leds_init(unsigned gpio) -{ - int i; - struct gpio_led *led; - - for (i = 0; i < DA850_N_BB_USER_LED; i++) { - led = &da850_evm_bb_leds[i]; - - led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i; - led->name = - da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i]; - } -} - static int da850_evm_bb_expander_setup(struct i2c_client *client, unsigned gpio, unsigned ngpio, void *c) @@ -685,7 +684,7 @@ static int da850_evm_bb_expander_setup(struct i2c_client *client, goto io_exp_setup_sw_fail; } - da850_evm_bb_leds_init(gpio); + gpiod_add_lookup_table(&da850_evm_bb_leds_gpio_table); ret = platform_device_register(&da850_evm_bb_leds_device); if (ret) { pr_warn("Could not register baseboard GPIO expander LEDs"); @@ -729,10 +728,12 @@ static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { }, { I2C_BOARD_INFO("tca6416", 0x20), + .dev_name = "ui-expander", .platform_data = &da850_evm_ui_expander_info, }, { I2C_BOARD_INFO("tca6416", 0x21), + .dev_name = "bb-expander", .platform_data = &da850_evm_bb_expander_info, }, }; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 1c518b8ee520..d7422233a130 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -49,6 +49,7 @@ config S5P_DEV_MFC config ARCH_EXYNOS3 bool "SAMSUNG EXYNOS3" + default y select ARM_CPU_SUSPEND if PM help Samsung EXYNOS3 (Cortex-A7) SoC based systems @@ -106,7 +107,7 @@ config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y depends on ARCH_EXYNOS5 - select MCPM if SMP + select EXYNOS_MCPM if SMP select ARM_CCI400_PORT_CTRL select ARM_CPU_SUSPEND @@ -115,6 +116,10 @@ config SOC_EXYNOS5800 default y depends on SOC_EXYNOS5420 +config EXYNOS_MCPM + bool + select MCPM + config EXYNOS_CPU_SUSPEND bool select ARM_CPU_SUSPEND diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 264dbaa89c3d..0fd3fcf8bfb0 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -14,9 +14,5 @@ obj-$(CONFIG_PM_SLEEP) += suspend.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o -plus_sec := $(call as-instr,.arch_extension sec,+sec) -AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) -AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec) - -obj-$(CONFIG_MCPM) += mcpm-exynos.o +obj-$(CONFIG_EXYNOS_MCPM) += mcpm-exynos.o CFLAGS_mcpm-exynos.o += -march=armv7-a diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index c93356a8d662..56411bb63d45 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -106,7 +106,7 @@ void exynos_firmware_init(void); #define C2_STATE (1 << 3) /* * Magic values for bootloader indicating chosen low power mode. - * See also Documentation/arm/Samsung/Bootloader-interface.txt + * See also Documentation/arm/samsung/bootloader-interface.rst */ #define EXYNOS_SLEEP_MAGIC 0x00000bad #define EXYNOS_AFTR_MAGIC 0xfcba0d10 diff --git a/arch/arm/mach-exynos/exynos-smc.S b/arch/arm/mach-exynos/exynos-smc.S index d259532ba937..6da31e6a7acb 100644 --- a/arch/arm/mach-exynos/exynos-smc.S +++ b/arch/arm/mach-exynos/exynos-smc.S @@ -10,7 +10,8 @@ /* * Function signature: void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3) */ - + .arch armv7-a + .arch_extension sec ENTRY(exynos_smc) stmfd sp!, {r4-r11, lr} dsb diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index 2783c3a0c06a..ed93f91853b8 100644 --- a/arch/arm/mach-exynos/sleep.S +++ b/arch/arm/mach-exynos/sleep.S @@ -44,7 +44,8 @@ ENTRY(exynos_cpu_resume) ENDPROC(exynos_cpu_resume) .align - + .arch armv7-a + .arch_extension sec ENTRY(exynos_cpu_resume_ns) mrc p15, 0, r0, c0, c0, 0 ldr r1, =CPU_MASK diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index be122af0de8f..6a0d3448ea00 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -268,7 +268,7 @@ static int exynos5420_cpu_suspend(unsigned long arg) unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); - if (IS_ENABLED(CONFIG_MCPM)) { + if (IS_ENABLED(CONFIG_EXYNOS_MCPM)) { mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); mcpm_cpu_suspend(); } @@ -285,7 +285,7 @@ static void exynos_pm_set_wakeup_mask(void) * Set wake-up mask registers * EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend. */ - pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); + pmu_raw_writel(exynos_irqwake_intmask & ~BIT(31), S5P_WAKEUP_MASK); } static void exynos_pm_enter_sleep_mode(void) @@ -351,7 +351,7 @@ static void exynos5420_pm_prepare(void) exynos_pm_enter_sleep_mode(); /* ensure at least INFORM0 has the resume address */ - if (IS_ENABLED(CONFIG_MCPM)) + if (IS_ENABLED(CONFIG_EXYNOS_MCPM)) pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0); tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0)); @@ -455,7 +455,7 @@ static void exynos5420_prepare_pm_resume(void) mpidr = read_cpuid_mpidr(); cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); - if (IS_ENABLED(CONFIG_MCPM)) + if (IS_ENABLED(CONFIG_EXYNOS_MCPM)) WARN_ON(mcpm_cpu_powered_up()); if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) { diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile index 7e6732c16862..71cc68041d92 100644 --- a/arch/arm/mach-highbank/Makefile +++ b/arch/arm/mach-highbank/Makefile @@ -1,7 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y := highbank.o system.o smc.o -plus_sec := $(call as-instr,.arch_extension sec,+sec) -AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) - obj-$(CONFIG_PM_SLEEP) += pm.o diff --git a/arch/arm/mach-highbank/smc.S b/arch/arm/mach-highbank/smc.S index b16c0442e812..78b3f19e7f37 100644 --- a/arch/arm/mach-highbank/smc.S +++ b/arch/arm/mach-highbank/smc.S @@ -13,7 +13,8 @@ * the monitor API number. * Function signature : void highbank_smc1(u32 fn, u32 arg) */ - + .arch armv7-a + .arch_extension sec ENTRY(highbank_smc1) stmfd sp!, {r4-r11, lr} mov r12, r0 diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index a2441ed6b673..39a7d9393641 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -14,22 +14,22 @@ #include "hardware.h" static int num_idle_cpus = 0; -static DEFINE_SPINLOCK(cpuidle_lock); +static DEFINE_RAW_SPINLOCK(cpuidle_lock); static int imx6q_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - spin_lock(&cpuidle_lock); + raw_spin_lock(&cpuidle_lock); if (++num_idle_cpus == num_online_cpus()) imx6_set_lpm(WAIT_UNCLOCKED); - spin_unlock(&cpuidle_lock); + raw_spin_unlock(&cpuidle_lock); cpu_do_idle(); - spin_lock(&cpuidle_lock); + raw_spin_lock(&cpuidle_lock); if (num_idle_cpus-- == num_online_cpus()) imx6_set_lpm(WAIT_CLOCKED); - spin_unlock(&cpuidle_lock); + raw_spin_unlock(&cpuidle_lock); return index; } diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index dec5d90a66ce..95713450591a 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -94,6 +94,12 @@ static void __init imx7d_init_machine(void) imx7d_enet_init(); } +static void __init imx7d_init_late(void) +{ + if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) + platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); +} + static void __init imx7d_init_irq(void) { imx_init_revision_from_anatop(); @@ -110,5 +116,6 @@ static const char *const imx7d_dt_compat[] __initconst = { DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") .init_irq = imx7d_init_irq, .init_machine = imx7d_init_machine, + .init_late = imx7d_init_late, .dt_compat = imx7d_dt_compat, MACHINE_END diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c index 493de4fd8b2e..61a1e593f9ec 100644 --- a/arch/arm/mach-iop32x/em7210.c +++ b/arch/arm/mach-iop32x/em7210.c @@ -20,6 +20,7 @@ #include <linux/platform_device.h> #include <linux/i2c.h> #include <linux/gpio.h> +#include <linux/gpio/machine.h> #include <mach/hardware.h> #include <linux/io.h> #include <linux/irq.h> @@ -207,6 +208,8 @@ static void __init em7210_init_machine(void) { register_iop32x_gpio(); platform_device_register(&em7210_serial_device); + gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); + gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); platform_device_register(&em7210_flash_device); diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 84cdb4587b34..5a45d616d9ac 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -21,6 +21,7 @@ #include <linux/i2c.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/gpio/machine.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -185,6 +186,8 @@ static void glantank_power_off(void) static void __init glantank_init_machine(void) { register_iop32x_gpio(); + gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); + gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); platform_device_register(&glantank_flash_device); diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index b177e3900616..8755aa87e591 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -22,6 +22,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/gpio/machine.h> #include <mach/hardware.h> #include <asm/cputype.h> #include <asm/irq.h> @@ -281,6 +282,8 @@ void ep80219_power_off(void) static void __init iq31244_init_machine(void) { register_iop32x_gpio(); + gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); + gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); platform_device_register(&iq31244_flash_device); diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 815b9f070007..e12699d1c540 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -19,6 +19,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/gpio/machine.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -168,6 +169,8 @@ static struct platform_device iq80321_serial_device = { static void __init iq80321_init_machine(void) { register_iop32x_gpio(); + gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); + gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); platform_device_register(&iq80321_flash_device); diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index 1948180594f4..26d76b377e79 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -27,6 +27,7 @@ #include <linux/reboot.h> #include <linux/io.h> #include <linux/gpio.h> +#include <linux/gpio/machine.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -341,6 +342,7 @@ device_initcall(n2100_request_gpios); static void __init n2100_init_machine(void) { register_iop32x_gpio(); + gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&n2100_flash_device); platform_device_register(&n2100_serial_device); diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index fc5378b00f3d..f7211b57b1e7 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -33,7 +33,7 @@ config MACH_AVILA help Say 'Y' here if you want your kernel to support the Gateworks Avila Network Platform. For more information on this platform, - see <file:Documentation/arm/IXP4xx>. + see <file:Documentation/arm/ixp4xx.rst>. config MACH_LOFT bool "Loft" @@ -49,7 +49,7 @@ config ARCH_ADI_COYOTE help Say 'Y' here if you want your kernel to support the ADI Engineering Coyote Gateway Reference Platform. For more - information on this platform, see <file:Documentation/arm/IXP4xx>. + information on this platform, see <file:Documentation/arm/ixp4xx.rst>. config MACH_GATEWAY7001 bool "Gateway 7001" @@ -72,21 +72,21 @@ config ARCH_IXDP425 help Say 'Y' here if you want your kernel to support Intel's IXDP425 Development Platform (Also known as Richfield). - For more information on this platform, see <file:Documentation/arm/IXP4xx>. + For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>. config MACH_IXDPG425 bool "IXDPG425" help Say 'Y' here if you want your kernel to support Intel's IXDPG425 Development Platform (Also known as Montajade). - For more information on this platform, see <file:Documentation/arm/IXP4xx>. + For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>. config MACH_IXDP465 bool "IXDP465" help Say 'Y' here if you want your kernel to support Intel's IXDP465 Development Platform (Also known as BMP). - For more information on this platform, see <file:Documentation/arm/IXP4xx>. + For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>. config MACH_GORAMO_MLR bool "GORAMO Multi Link Router" @@ -99,7 +99,7 @@ config MACH_KIXRP435 help Say 'Y' here if you want your kernel to support Intel's KIXRP435 Reference Platform. - For more information on this platform, see <file:Documentation/arm/IXP4xx>. + For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>. # # IXCDP1100 is the exact same HW as IXDP425, but with a different machine @@ -116,7 +116,7 @@ config ARCH_PRPMC1100 help Say 'Y' here if you want your kernel to support the Motorola PrPCM1100 Processor Mezanine Module. For more information on - this platform, see <file:Documentation/arm/IXP4xx>. + this platform, see <file:Documentation/arm/ixp4xx.rst>. config MACH_NAS100D bool diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index f8b0dccac8dc..739b38be5696 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -1,9 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-y := keystone.o smc.o -plus_sec := $(call as-instr,.arch_extension sec,+sec) -AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) - obj-$(CONFIG_SMP) += platsmp.o # PM domain driver for Keystone SOCs diff --git a/arch/arm/mach-keystone/smc.S b/arch/arm/mach-keystone/smc.S index 76d0bf6ac73c..21ef75cf5370 100644 --- a/arch/arm/mach-keystone/smc.S +++ b/arch/arm/mach-keystone/smc.S @@ -18,6 +18,7 @@ * * Return: Non zero value on failure */ + .arch_extension sec ENTRY(keystone_cpu_smc) stmfd sp!, {r4-r11, lr} smc #0 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 85d1b13c9215..600650551621 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -41,18 +41,10 @@ obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o -plus_sec := $(call as-instr,.arch_extension sec,+sec) -AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) -AFLAGS_omap-smc.o :=-Wa,-march=armv7-a$(plus_sec) -AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec) - # Functions loaded to SRAM obj-$(CONFIG_SOC_OMAP2420) += sram242x.o obj-$(CONFIG_SOC_OMAP2430) += sram243x.o -AFLAGS_sram242x.o :=-Wa,-march=armv6 -AFLAGS_sram243x.o :=-Wa,-march=armv6 - # Restart code (OMAP4/5 currently in omap4-common.c) obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o @@ -94,11 +86,6 @@ obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o -AFLAGS_sleep24xx.o :=-Wa,-march=armv6 -AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) -AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec) -AFLAGS_sleep43xx.o :=-Wa,-march=armv7-a$(plus_sec) - endif ifeq ($(CONFIG_CPU_IDLE),y) diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 7d0db77ab8cb..1762f919941f 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -55,6 +55,8 @@ ENDPROC(omap5_secondary_startup) * omap5_secondary_startup if the primary CPU was put into HYP mode by * the boot loader. */ + .arch armv7-a + .arch_extension sec ENTRY(omap5_secondary_hyp_startup) wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 ldr r0, [r2] diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S index 630b9bd099e0..fd2bcd91f4a1 100644 --- a/arch/arm/mach-omap2/omap-smc.S +++ b/arch/arm/mach-omap2/omap-smc.S @@ -20,7 +20,8 @@ * link register "lr". * Function signature : void omap_smc1(u32 fn, u32 arg) */ - + .arch armv7-a + .arch_extension sec ENTRY(omap_smc1) stmfd sp!, {r2-r12, lr} mov r12, r0 diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e0350476feaa..203664c40d3d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -3442,6 +3442,7 @@ static int omap_hwmod_check_module(struct device *dev, * @dev: struct device * @oh: module * @sysc_fields: sysc register bits + * @clockdomain: clockdomain * @rev_offs: revision register offset * @sysc_offs: sysconfig register offset * @syss_offs: sysstatus register offset @@ -3453,6 +3454,7 @@ static int omap_hwmod_check_module(struct device *dev, static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh, const struct ti_sysc_module_data *data, struct sysc_regbits *sysc_fields, + struct clockdomain *clkdm, s32 rev_offs, s32 sysc_offs, s32 syss_offs, u32 sysc_flags, u32 idlemodes) @@ -3460,8 +3462,6 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh, struct omap_hwmod_class_sysconfig *sysc; struct omap_hwmod_class *class = NULL; struct omap_hwmod_ocp_if *oi = NULL; - struct clockdomain *clkdm = NULL; - struct clk *clk = NULL; void __iomem *regs = NULL; unsigned long flags; @@ -3508,36 +3508,6 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh, oi->user = OCP_USER_MPU | OCP_USER_SDMA; } - if (!oh->_clk) { - struct clk_hw_omap *hwclk; - - clk = of_clk_get_by_name(dev->of_node, "fck"); - if (!IS_ERR(clk)) - clk_prepare(clk); - else - clk = NULL; - - /* - * Populate clockdomain based on dts clock. It is needed for - * clkdm_deny_idle() and clkdm_allow_idle() until we have have - * interconnect driver and reset driver capable of blocking - * clockdomain idle during reset, enable and idle. - */ - if (clk) { - hwclk = to_clk_hw_omap(__clk_get_hw(clk)); - if (hwclk && hwclk->clkdm_name) - clkdm = clkdm_lookup(hwclk->clkdm_name); - } - - /* - * Note that we assume interconnect driver manages the clocks - * and do not need to populate oh->_clk for dynamically - * allocated modules. - */ - clk_unprepare(clk); - clk_put(clk); - } - spin_lock_irqsave(&oh->_lock, flags); if (regs) oh->_mpu_rt_va = regs; @@ -3623,7 +3593,7 @@ int omap_hwmod_init_module(struct device *dev, u32 sysc_flags, idlemodes; int error; - if (!dev || !data) + if (!dev || !data || !data->name || !cookie) return -EINVAL; oh = _lookup(data->name); @@ -3694,7 +3664,8 @@ int omap_hwmod_init_module(struct device *dev, return error; return omap_hwmod_allocate_module(dev, oh, data, sysc_fields, - rev_offs, sysc_offs, syss_offs, + cookie->clkdm, rev_offs, + sysc_offs, syss_offs, sysc_flags, idlemodes); } diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 4c3543bae562..adb6271f819b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -529,7 +529,7 @@ static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { .sysc_fields = &omap_hwmod_sysc_type1, }; -struct omap_hwmod_class am33xx_gpio_hwmod_class = { +static struct omap_hwmod_class am33xx_gpio_hwmod_class = { .name = "gpio", .sysc = &am33xx_gpio_sysc, }; @@ -539,7 +539,7 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, }; -struct omap_hwmod am33xx_gpio1_hwmod = { +static struct omap_hwmod am33xx_gpio1_hwmod = { .name = "gpio2", .class = &am33xx_gpio_hwmod_class, .clkdm_name = "l4ls_clkdm", @@ -559,7 +559,7 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { { .role = "dbclk", .clk = "gpio2_dbclk" }, }; -struct omap_hwmod am33xx_gpio2_hwmod = { +static struct omap_hwmod am33xx_gpio2_hwmod = { .name = "gpio3", .class = &am33xx_gpio_hwmod_class, .clkdm_name = "l4ls_clkdm", @@ -579,7 +579,7 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { { .role = "dbclk", .clk = "gpio3_dbclk" }, }; -struct omap_hwmod am33xx_gpio3_hwmod = { +static struct omap_hwmod am33xx_gpio3_hwmod = { .name = "gpio4", .class = &am33xx_gpio_hwmod_class, .clkdm_name = "l4ls_clkdm", diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index b0f8c9a70c68..6c6f8fce854e 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -26,6 +26,7 @@ #include <linux/platform_data/wkup_m3.h> #include <linux/platform_data/asoc-ti-mcbsp.h> +#include "clockdomain.h" #include "common.h" #include "common-board-devices.h" #include "control.h" @@ -460,6 +461,62 @@ static void __init dra7x_evm_mmc_quirk(void) } #endif +static struct clockdomain *ti_sysc_find_one_clockdomain(struct clk *clk) +{ + struct clockdomain *clkdm = NULL; + struct clk_hw_omap *hwclk; + + hwclk = to_clk_hw_omap(__clk_get_hw(clk)); + if (hwclk && hwclk->clkdm_name) + clkdm = clkdm_lookup(hwclk->clkdm_name); + + return clkdm; +} + +/** + * ti_sysc_clkdm_init - find clockdomain based on clock + * @fck: device functional clock + * @ick: device interface clock + * @dev: struct device + * + * Populate clockdomain based on clock. It is needed for + * clkdm_deny_idle() and clkdm_allow_idle() for blocking clockdomain + * clockdomain idle during reset, enable and idle. + * + * Note that we assume interconnect driver manages the clocks + * and do not need to populate oh->_clk for dynamically + * allocated modules. + */ +static int ti_sysc_clkdm_init(struct device *dev, + struct clk *fck, struct clk *ick, + struct ti_sysc_cookie *cookie) +{ + if (fck) + cookie->clkdm = ti_sysc_find_one_clockdomain(fck); + if (cookie->clkdm) + return 0; + if (ick) + cookie->clkdm = ti_sysc_find_one_clockdomain(ick); + if (cookie->clkdm) + return 0; + + return -ENODEV; +} + +static void ti_sysc_clkdm_deny_idle(struct device *dev, + const struct ti_sysc_cookie *cookie) +{ + if (cookie->clkdm) + clkdm_deny_idle(cookie->clkdm); +} + +static void ti_sysc_clkdm_allow_idle(struct device *dev, + const struct ti_sysc_cookie *cookie) +{ + if (cookie->clkdm) + clkdm_allow_idle(cookie->clkdm); +} + static int ti_sysc_enable_module(struct device *dev, const struct ti_sysc_cookie *cookie) { @@ -491,6 +548,9 @@ static struct of_dev_auxdata omap_auxdata_lookup[]; static struct ti_sysc_platform_data ti_sysc_pdata = { .auxdata = omap_auxdata_lookup, + .init_clockdomain = ti_sysc_clkdm_init, + .clkdm_deny_idle = ti_sysc_clkdm_deny_idle, + .clkdm_allow_idle = ti_sysc_clkdm_allow_idle, .init_module = omap_hwmod_init_module, .enable_module = ti_sysc_enable_module, .idle_module = ti_sysc_idle_module, diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S index 47a816468cdb..68fee339d3f1 100644 --- a/arch/arm/mach-omap2/sleep33xx.S +++ b/arch/arm/mach-omap2/sleep33xx.S @@ -24,6 +24,7 @@ #define BIT(nr) (1 << (nr)) .arm + .arch armv7-a .align 3 ENTRY(am33xx_do_wfi) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 75ea4723ec0e..ac1324c6453b 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -83,6 +83,8 @@ ENDPROC(enable_omap3630_toggle_l2_on_restore) * * r0 = physical address of the parameters */ + .arch armv7-a + .arch_extension sec ENTRY(save_secure_ram_context) stmfd sp!, {r4 - r11, lr} @ save registers on stack mov r3, r0 @ physical address of parameters diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S index 0c1031442571..c1f4e4852644 100644 --- a/arch/arm/mach-omap2/sleep43xx.S +++ b/arch/arm/mach-omap2/sleep43xx.S @@ -56,6 +56,8 @@ #define RTC_PMIC_EXT_WAKEUP_EN BIT(0) .arm + .arch armv7-a + .arch_extension sec .align 3 ENTRY(am43xx_do_wfi) diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S index 934033ad847f..f60f6a9aed73 100644 --- a/arch/arm/mach-omap2/sleep44xx.S +++ b/arch/arm/mach-omap2/sleep44xx.S @@ -18,8 +18,11 @@ #include "omap44xx.h" #include "omap4-sar-layout.h" + .arch armv7-a + #if defined(CONFIG_SMP) && defined(CONFIG_PM) + .arch_extension sec .macro DO_SMC dsb smc #0 diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h index 72b5c3db37dc..a3af4a2f9446 100644 --- a/arch/arm/mach-pxa/include/mach/lubbock.h +++ b/arch/arm/mach-pxa/include/mach/lubbock.h @@ -47,7 +47,3 @@ #define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) #define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32) - -#ifndef __ASSEMBLY__ -extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); -#endif diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index a3ecccc24ec5..742d18a1f7dc 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -116,12 +116,11 @@ void lubbock_set_hexled(uint32_t value) static struct gpio_chip *lubbock_misc_wr_gc; -void lubbock_set_misc_wr(unsigned int mask, unsigned int set) +static void lubbock_set_misc_wr(unsigned int mask, unsigned int set) { unsigned long m = mask, v = set; lubbock_misc_wr_gc->set_multiple(lubbock_misc_wr_gc, &m, &v); } -EXPORT_SYMBOL(lubbock_set_misc_wr); static int lubbock_udc_is_connected(void) { diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 909fffee0240..649e0a54784c 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -269,19 +269,25 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) sram_base_addr = of_iomap(node, 0); if (!sram_base_addr) { pr_err("%s: could not map sram registers\n", __func__); + of_node_put(node); return; } - if (has_pmu && rockchip_smp_prepare_pmu()) + if (has_pmu && rockchip_smp_prepare_pmu()) { + of_node_put(node); return; + } if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { - if (rockchip_smp_prepare_sram(node)) + if (rockchip_smp_prepare_sram(node)) { + of_node_put(node); return; + } /* enable the SCU power domain */ pmu_set_power_domain(PMU_PWRDN_SCU, true); + of_node_put(node); node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); if (!node) { pr_err("%s: missing scu\n", __func__); @@ -291,6 +297,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) scu_base_addr = of_iomap(node, 0); if (!scu_base_addr) { pr_err("%s: could not map scu registers\n", __func__); + of_node_put(node); return; } @@ -309,6 +316,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); ncores = ((l2ctlr >> 24) & 0x3) + 1; } + of_node_put(node); /* Make sure that all cores except the first are really off */ for (i = 1; i < ncores; i++) diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index 744b5b332e42..87389d9456b9 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -257,12 +257,14 @@ static int __init rk3288_suspend_init(struct device_node *np) rk3288_bootram_base = of_iomap(sram_np, 0); if (!rk3288_bootram_base) { pr_err("%s: could not map bootram base\n", __func__); + of_node_put(sram_np); return -ENOMEM; } ret = of_address_to_resource(sram_np, 0, &res); if (ret) { pr_err("%s: could not get bootram phy addr\n", __func__); + of_node_put(sram_np); return ret; } rk3288_bootram_phy = res.start; diff --git a/arch/arm/mach-rpc/Makefile b/arch/arm/mach-rpc/Makefile index 056ef5460290..90a645a18444 100644 --- a/arch/arm/mach-rpc/Makefile +++ b/arch/arm/mach-rpc/Makefile @@ -5,4 +5,5 @@ # Object file lists. -obj-y := dma.o ecard.o fiq.o irq.o riscpc.o time.o +obj-y :=dma.o ecard.o ecard-loader.o fiq.o floppydma.o io-acorn.o irq.o \ + riscpc.o time.o diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c index 488d5c3b37f4..50e0f97afd75 100644 --- a/arch/arm/mach-rpc/dma.c +++ b/arch/arm/mach-rpc/dma.c @@ -24,10 +24,11 @@ struct iomd_dma { struct dma_struct dma; - unsigned int state; - unsigned long base; /* Controller base address */ + void __iomem *base; /* Controller base address */ int irq; /* Controller IRQ */ - struct scatterlist cur_sg; /* Current controller buffer */ + unsigned int state; + dma_addr_t cur_addr; + unsigned int cur_len; dma_addr_t dma_addr; unsigned int dma_len; }; @@ -50,13 +51,13 @@ typedef enum { #define CR (IOMD_IO0CR - IOMD_IO0CURA) #define ST (IOMD_IO0ST - IOMD_IO0CURA) -static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma) +static void iomd_get_next_sg(struct iomd_dma *idma) { unsigned long end, offset, flags = 0; if (idma->dma.sg) { - sg->dma_address = idma->dma_addr; - offset = sg->dma_address & ~PAGE_MASK; + idma->cur_addr = idma->dma_addr; + offset = idma->cur_addr & ~PAGE_MASK; end = offset + idma->dma_len; @@ -66,7 +67,7 @@ static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma) if (offset + TRANSFER_SIZE >= end) flags |= DMA_END_L; - sg->length = end - TRANSFER_SIZE; + idma->cur_len = end - TRANSFER_SIZE; idma->dma_len -= end - offset; idma->dma_addr += end - offset; @@ -84,52 +85,49 @@ static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma) } } else { flags = DMA_END_S | DMA_END_L; - sg->dma_address = 0; - sg->length = 0; + idma->cur_addr = 0; + idma->cur_len = 0; } - sg->length |= flags; + idma->cur_len |= flags; } static irqreturn_t iomd_dma_handle(int irq, void *dev_id) { struct iomd_dma *idma = dev_id; - unsigned long base = idma->base; + void __iomem *base = idma->base; + unsigned int state = idma->state; + unsigned int status, cur, end; do { - unsigned int status; - - status = iomd_readb(base + ST); + status = readb(base + ST); if (!(status & DMA_ST_INT)) - return IRQ_HANDLED; - - if ((idma->state ^ status) & DMA_ST_AB) - iomd_get_next_sg(&idma->cur_sg, idma); - - switch (status & (DMA_ST_OFL | DMA_ST_AB)) { - case DMA_ST_OFL: /* OIA */ - case DMA_ST_AB: /* .IB */ - iomd_writel(idma->cur_sg.dma_address, base + CURA); - iomd_writel(idma->cur_sg.length, base + ENDA); - idma->state = DMA_ST_AB; - break; - - case DMA_ST_OFL | DMA_ST_AB: /* OIB */ - case 0: /* .IA */ - iomd_writel(idma->cur_sg.dma_address, base + CURB); - iomd_writel(idma->cur_sg.length, base + ENDB); - idma->state = 0; - break; + goto out; + + if ((state ^ status) & DMA_ST_AB) + iomd_get_next_sg(idma); + + // This efficiently implements state = OFL != AB ? AB : 0 + state = ((status >> 2) ^ status) & DMA_ST_AB; + if (state) { + cur = CURA; + end = ENDA; + } else { + cur = CURB; + end = ENDB; } + writel(idma->cur_addr, base + cur); + writel(idma->cur_len, base + end); if (status & DMA_ST_OFL && - idma->cur_sg.length == (DMA_END_S|DMA_END_L)) + idma->cur_len == (DMA_END_S|DMA_END_L)) break; } while (1); - idma->state = ~DMA_ST_AB; - disable_irq(irq); - + state = ~DMA_ST_AB; + disable_irq_nosync(irq); +out: + idma->state = state; return IRQ_HANDLED; } @@ -157,7 +155,7 @@ static struct device isa_dma_dev = { static void iomd_enable_dma(unsigned int chan, dma_t *dma) { struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); - unsigned long dma_base = idma->base; + void __iomem *base = idma->base; unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E; if (idma->dma.invalid) { @@ -177,27 +175,30 @@ static void iomd_enable_dma(unsigned int chan, dma_t *dma) DMA_FROM_DEVICE : DMA_TO_DEVICE); } - iomd_writeb(DMA_CR_C, dma_base + CR); + idma->dma_addr = idma->dma.sg->dma_address; + idma->dma_len = idma->dma.sg->length; + + writeb(DMA_CR_C, base + CR); idma->state = DMA_ST_AB; } if (idma->dma.dma_mode == DMA_MODE_READ) ctrl |= DMA_CR_D; - iomd_writeb(ctrl, dma_base + CR); + writeb(ctrl, base + CR); enable_irq(idma->irq); } static void iomd_disable_dma(unsigned int chan, dma_t *dma) { struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); - unsigned long dma_base = idma->base; + void __iomem *base = idma->base; unsigned long flags; local_irq_save(flags); if (idma->state != ~DMA_ST_AB) disable_irq(idma->irq); - iomd_writeb(0, dma_base + CR); + writeb(0, base + CR); local_irq_restore(flags); } @@ -360,17 +361,17 @@ static int __init rpc_dma_init(void) */ iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT); - iomd_dma[DMA_0].base = IOMD_IO0CURA; + iomd_dma[DMA_0].base = IOMD_BASE + IOMD_IO0CURA; iomd_dma[DMA_0].irq = IRQ_DMA0; - iomd_dma[DMA_1].base = IOMD_IO1CURA; + iomd_dma[DMA_1].base = IOMD_BASE + IOMD_IO1CURA; iomd_dma[DMA_1].irq = IRQ_DMA1; - iomd_dma[DMA_2].base = IOMD_IO2CURA; + iomd_dma[DMA_2].base = IOMD_BASE + IOMD_IO2CURA; iomd_dma[DMA_2].irq = IRQ_DMA2; - iomd_dma[DMA_3].base = IOMD_IO3CURA; + iomd_dma[DMA_3].base = IOMD_BASE + IOMD_IO3CURA; iomd_dma[DMA_3].irq = IRQ_DMA3; - iomd_dma[DMA_S0].base = IOMD_SD0CURA; + iomd_dma[DMA_S0].base = IOMD_BASE + IOMD_SD0CURA; iomd_dma[DMA_S0].irq = IRQ_DMAS0; - iomd_dma[DMA_S1].base = IOMD_SD1CURA; + iomd_dma[DMA_S1].base = IOMD_BASE + IOMD_SD1CURA; iomd_dma[DMA_S1].irq = IRQ_DMAS1; for (i = DMA_0; i <= DMA_S1; i++) { diff --git a/arch/arm/lib/ecard.S b/arch/arm/mach-rpc/ecard-loader.S index eb8ac0412da6..eb8ac0412da6 100644 --- a/arch/arm/lib/ecard.S +++ b/arch/arm/mach-rpc/ecard-loader.S diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c index cf0593bc42d2..75cfad2cb143 100644 --- a/arch/arm/mach-rpc/ecard.c +++ b/arch/arm/mach-rpc/ecard.c @@ -67,17 +67,21 @@ struct expcard_blacklist { unsigned short manufacturer; unsigned short product; const char *type; + void (*init)(ecard_t *ec); }; static ecard_t *cards; static ecard_t *slot_to_expcard[MAX_ECARDS]; static unsigned int ectcr; +static void atomwide_3p_quirk(ecard_t *ec); + /* List of descriptions of cards which don't have an extended * identification, or chunk directories containing a description. */ static struct expcard_blacklist __initdata blacklist[] = { - { MANU_ACORN, PROD_ACORN_ETHER1, "Acorn Ether1" } + { MANU_ACORN, PROD_ACORN_ETHER1, "Acorn Ether1" }, + { MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, NULL, atomwide_3p_quirk }, }; asmlinkage extern int @@ -493,18 +497,21 @@ static void ecard_dump_irq_state(void) printk("Expansion card IRQ state:\n"); for (ec = cards; ec; ec = ec->next) { + const char *claimed; + if (ec->slot_no == 8) continue; - printk(" %d: %sclaimed, ", - ec->slot_no, ec->claimed ? "" : "not "); + claimed = ec->claimed ? "" : "not "; if (ec->ops && ec->ops->irqpending && ec->ops != &ecard_default_ops) - printk("irq %spending\n", + printk(" %d: %sclaimed irq %spending\n", + ec->slot_no, claimed, ec->ops->irqpending(ec) ? "" : "not "); else - printk("irqaddr %p, mask = %02X, status = %02X\n", + printk(" %d: %sclaimed irqaddr %p, mask = %02X, status = %02X\n", + ec->slot_no, claimed, ec->irqaddr, ec->irqmask, readb(ec->irqaddr)); } } @@ -865,6 +872,16 @@ void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, } EXPORT_SYMBOL(ecardm_iomap); +static void atomwide_3p_quirk(ecard_t *ec) +{ + void __iomem *addr = __ecard_address(ec, ECARD_IOC, ECARD_SYNC); + unsigned int i; + + /* Disable interrupts on each port */ + for (i = 0x2000; i <= 0x2800; i += 0x0400) + writeb(0, addr + i + 4); +} + /* * Probe for an expansion card. * @@ -921,7 +938,10 @@ static int __init ecard_probe(int slot, unsigned irq, card_type_t type) for (i = 0; i < ARRAY_SIZE(blacklist); i++) if (blacklist[i].manufacturer == ec->cid.manufacturer && blacklist[i].product == ec->cid.product) { - ec->card_desc = blacklist[i].type; + if (blacklist[i].type) + ec->card_desc = blacklist[i].type; + if (blacklist[i].init) + blacklist[i].init(ec); break; } diff --git a/arch/arm/lib/floppydma.S b/arch/arm/mach-rpc/floppydma.S index 6698b83050dc..6698b83050dc 100644 --- a/arch/arm/lib/floppydma.S +++ b/arch/arm/mach-rpc/floppydma.S diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h index a023b5f9bbbb..1fbe7eb956fd 100644 --- a/arch/arm/mach-rpc/include/mach/uncompress.h +++ b/arch/arm/mach-rpc/include/mach/uncompress.h @@ -115,29 +115,22 @@ static void arch_decomp_setup(void) struct tag *t = (struct tag *)params; unsigned int nr_pages = 0, page_size = PAGE_SIZE; - if (t->hdr.tag == ATAG_CORE) - { - for (; t->hdr.size; t = tag_next(t)) - { - if (t->hdr.tag == ATAG_VIDEOTEXT) - { + if (t->hdr.tag == ATAG_CORE) { + for (; t->hdr.size; t = tag_next(t)) { + if (t->hdr.tag == ATAG_VIDEOTEXT) { video_num_rows = t->u.videotext.video_lines; video_num_cols = t->u.videotext.video_cols; - bytes_per_char_h = t->u.videotext.video_points; - bytes_per_char_v = t->u.videotext.video_points; video_x = t->u.videotext.x; video_y = t->u.videotext.y; - } - - if (t->hdr.tag == ATAG_MEM) - { + } else if (t->hdr.tag == ATAG_VIDEOLFB) { + bytes_per_char_h = t->u.videolfb.lfb_depth; + bytes_per_char_v = 8; + } else if (t->hdr.tag == ATAG_MEM) { page_size = PAGE_SIZE; nr_pages += (t->u.mem.size / PAGE_SIZE); } } - } - else - { + } else { nr_pages = params->nr_pages; page_size = params->page_size; video_num_rows = params->video_num_rows; diff --git a/arch/arm/lib/io-acorn.S b/arch/arm/mach-rpc/io-acorn.S index b9082a2a2a01..b9082a2a2a01 100644 --- a/arch/arm/lib/io-acorn.S +++ b/arch/arm/mach-rpc/io-acorn.S diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index b8a61cb11207..803aeb126f0e 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -8,117 +8,71 @@ #include <asm/irq.h> #include <asm/fiq.h> -static void iomd_ack_irq_a(struct irq_data *d) -{ - unsigned int val, mask; - - mask = 1 << d->irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val & ~mask, IOMD_IRQMASKA); - iomd_writeb(mask, IOMD_IRQCLRA); -} - -static void iomd_mask_irq_a(struct irq_data *d) -{ - unsigned int val, mask; +// These are offsets from the stat register for each IRQ bank +#define STAT 0x00 +#define REQ 0x04 +#define CLR 0x04 +#define MASK 0x08 - mask = 1 << d->irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val & ~mask, IOMD_IRQMASKA); -} - -static void iomd_unmask_irq_a(struct irq_data *d) +static void __iomem *iomd_get_base(struct irq_data *d) { - unsigned int val, mask; + void *cd = irq_data_get_irq_chip_data(d); - mask = 1 << d->irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val | mask, IOMD_IRQMASKA); + return (void __iomem *)(unsigned long)cd; } -static struct irq_chip iomd_a_chip = { - .irq_ack = iomd_ack_irq_a, - .irq_mask = iomd_mask_irq_a, - .irq_unmask = iomd_unmask_irq_a, -}; - -static void iomd_mask_irq_b(struct irq_data *d) +static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask) { - unsigned int val, mask; + struct irq_data *d = irq_get_irq_data(irq); - mask = 1 << (d->irq & 7); - val = iomd_readb(IOMD_IRQMASKB); - iomd_writeb(val & ~mask, IOMD_IRQMASKB); + d->mask = mask; + irq_set_chip_data(irq, (void *)(unsigned long)base); } -static void iomd_unmask_irq_b(struct irq_data *d) +static void iomd_irq_mask_ack(struct irq_data *d) { - unsigned int val, mask; + void __iomem *base = iomd_get_base(d); + unsigned int val, mask = d->mask; - mask = 1 << (d->irq & 7); - val = iomd_readb(IOMD_IRQMASKB); - iomd_writeb(val | mask, IOMD_IRQMASKB); + val = readb(base + MASK); + writeb(val & ~mask, base + MASK); + writeb(mask, base + CLR); } -static struct irq_chip iomd_b_chip = { - .irq_ack = iomd_mask_irq_b, - .irq_mask = iomd_mask_irq_b, - .irq_unmask = iomd_unmask_irq_b, -}; - -static void iomd_mask_irq_dma(struct irq_data *d) +static void iomd_irq_mask(struct irq_data *d) { - unsigned int val, mask; + void __iomem *base = iomd_get_base(d); + unsigned int val, mask = d->mask; - mask = 1 << (d->irq & 7); - val = iomd_readb(IOMD_DMAMASK); - iomd_writeb(val & ~mask, IOMD_DMAMASK); + val = readb(base + MASK); + writeb(val & ~mask, base + MASK); } -static void iomd_unmask_irq_dma(struct irq_data *d) +static void iomd_irq_unmask(struct irq_data *d) { - unsigned int val, mask; + void __iomem *base = iomd_get_base(d); + unsigned int val, mask = d->mask; - mask = 1 << (d->irq & 7); - val = iomd_readb(IOMD_DMAMASK); - iomd_writeb(val | mask, IOMD_DMAMASK); + val = readb(base + MASK); + writeb(val | mask, base + MASK); } -static struct irq_chip iomd_dma_chip = { - .irq_ack = iomd_mask_irq_dma, - .irq_mask = iomd_mask_irq_dma, - .irq_unmask = iomd_unmask_irq_dma, +static struct irq_chip iomd_chip_clr = { + .irq_mask_ack = iomd_irq_mask_ack, + .irq_mask = iomd_irq_mask, + .irq_unmask = iomd_irq_unmask, }; -static void iomd_mask_irq_fiq(struct irq_data *d) -{ - unsigned int val, mask; - - mask = 1 << (d->irq & 7); - val = iomd_readb(IOMD_FIQMASK); - iomd_writeb(val & ~mask, IOMD_FIQMASK); -} - -static void iomd_unmask_irq_fiq(struct irq_data *d) -{ - unsigned int val, mask; - - mask = 1 << (d->irq & 7); - val = iomd_readb(IOMD_FIQMASK); - iomd_writeb(val | mask, IOMD_FIQMASK); -} - -static struct irq_chip iomd_fiq_chip = { - .irq_ack = iomd_mask_irq_fiq, - .irq_mask = iomd_mask_irq_fiq, - .irq_unmask = iomd_unmask_irq_fiq, +static struct irq_chip iomd_chip_noclr = { + .irq_mask = iomd_irq_mask, + .irq_unmask = iomd_irq_unmask, }; extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end; void __init rpc_init_irq(void) { - unsigned int irq, clr, set = 0; + unsigned int irq, clr, set; iomd_writeb(0, IOMD_IRQMASKA); iomd_writeb(0, IOMD_IRQMASKB); @@ -130,6 +84,7 @@ void __init rpc_init_irq(void) for (irq = 0; irq < NR_IRQS; irq++) { clr = IRQ_NOREQUEST; + set = 0; if (irq <= 6 || (irq >= 9 && irq <= 15)) clr |= IRQ_NOPROBE; @@ -140,30 +95,37 @@ void __init rpc_init_irq(void) switch (irq) { case 0 ... 7: - irq_set_chip_and_handler(irq, &iomd_a_chip, + irq_set_chip_and_handler(irq, &iomd_chip_clr, handle_level_irq); irq_modify_status(irq, clr, set); + iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATA, + BIT(irq)); break; case 8 ... 15: - irq_set_chip_and_handler(irq, &iomd_b_chip, + irq_set_chip_and_handler(irq, &iomd_chip_noclr, handle_level_irq); irq_modify_status(irq, clr, set); + iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATB, + BIT(irq - 8)); break; case 16 ... 21: - irq_set_chip_and_handler(irq, &iomd_dma_chip, + irq_set_chip_and_handler(irq, &iomd_chip_noclr, handle_level_irq); irq_modify_status(irq, clr, set); + iomd_set_base_mask(irq, IOMD_BASE + IOMD_DMASTAT, + BIT(irq - 16)); break; case 64 ... 71: - irq_set_chip(irq, &iomd_fiq_chip); + irq_set_chip(irq, &iomd_chip_noclr); irq_modify_status(irq, clr, set); + iomd_set_base_mask(irq, IOMD_BASE + IOMD_FIQSTAT, + BIT(irq - 64)); break; } } init_FIQ(FIQ_START); } - diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c index e97f93a0af1d..1d750152b160 100644 --- a/arch/arm/mach-rpc/time.c +++ b/arch/arm/mach-rpc/time.c @@ -10,7 +10,7 @@ * 04-Dec-1997 RMK Updated for new arch/arm/time.c * 13=Jun-2004 DS Moved to arch/arm/common b/c shared w/CLPS7500 */ -#include <linux/timex.h> +#include <linux/clocksource.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> @@ -24,11 +24,15 @@ #define RPC_CLOCK_FREQ 2000000 #define RPC_LATCH DIV_ROUND_CLOSEST(RPC_CLOCK_FREQ, HZ) -static u32 ioc_timer_gettimeoffset(void) +static u32 ioc_time; + +static u64 ioc_timer_read(struct clocksource *cs) { unsigned int count1, count2, status; - long offset; + unsigned long flags; + u32 ticks; + local_irq_save(flags); ioc_writeb (0, IOC_T0LATCH); barrier (); count1 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8); @@ -38,27 +42,34 @@ static u32 ioc_timer_gettimeoffset(void) ioc_writeb (0, IOC_T0LATCH); barrier (); count2 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8); + ticks = ioc_time + RPC_LATCH - count2; + local_irq_restore(flags); - offset = count2; if (count2 < count1) { /* - * We have not had an interrupt between reading count1 - * and count2. + * The timer has not reloaded between reading count1 and + * count2, check whether an interrupt was actually pending. */ if (status & (1 << 5)) - offset -= RPC_LATCH; + ticks += RPC_LATCH; } else if (count2 > count1) { /* - * We have just had another interrupt between reading - * count1 and count2. + * The timer has reloaded, so count2 indicates the new + * count since the wrap. The interrupt would not have + * been processed, so add the missed ticks. */ - offset -= RPC_LATCH; + ticks += RPC_LATCH; } - offset = (RPC_LATCH - offset) * (tick_nsec / 1000); - return DIV_ROUND_CLOSEST(offset, RPC_LATCH) * 1000; + return ticks; } +static struct clocksource ioctime_clocksource = { + .read = ioc_timer_read, + .mask = CLOCKSOURCE_MASK(32), + .rating = 100, +}; + void __init ioctime_init(void) { ioc_writeb(RPC_LATCH & 255, IOC_T0LTCHL); @@ -69,6 +80,7 @@ void __init ioctime_init(void) static irqreturn_t ioc_timer_interrupt(int irq, void *dev_id) { + ioc_time += RPC_LATCH; timer_tick(); return IRQ_HANDLED; } @@ -83,7 +95,7 @@ static struct irqaction ioc_timer_irq = { */ void __init ioc_timer_init(void) { - arch_gettimeoffset = ioc_timer_gettimeoffset; + WARN_ON(clocksource_register_hz(&ioctime_clocksource, RPC_CLOCK_FREQ)); ioctime_init(); setup_irq(IRQ_TIMER0, &ioc_timer_irq); } diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c index adcb90645460..c64988c609ad 100644 --- a/arch/arm/mach-s3c24xx/pm.c +++ b/arch/arm/mach-s3c24xx/pm.c @@ -5,7 +5,7 @@ // // S3C24XX Power Manager (Suspend-To-RAM) support // -// See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information +// See Documentation/arm/samsung-s3c24xx/suspend.rst for more information // // Parts based on arch/arm/mach-pxa/pm.c // diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index dd8d13fb8450..d96a101e5504 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -519,6 +519,29 @@ static const struct gpio_keys_platform_data assabet_keys_pdata = { .rep = 0, }; +static struct gpiod_lookup_table assabet_uart1_gpio_table = { + .dev_id = "sa11x0-uart.1", + .table = { + GPIO_LOOKUP("assabet", 16, "dtr", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("assabet", 17, "rts", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("assabet", 25, "dcd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("assabet", 26, "cts", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("assabet", 27, "dsr", GPIO_ACTIVE_LOW), + { }, + }, +}; + +static struct gpiod_lookup_table assabet_uart3_gpio_table = { + .dev_id = "sa11x0-uart.3", + .table = { + GPIO_LOOKUP("assabet", 28, "cts", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("assabet", 29, "dsr", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("assabet", 30, "dcd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("assabet", 31, "rng", GPIO_ACTIVE_LOW), + { }, + }, +}; + static void __init assabet_init(void) { /* @@ -565,7 +588,10 @@ static void __init assabet_init(void) neponset_resources, ARRAY_SIZE(neponset_resources)); #endif } else { + gpiod_add_lookup_table(&assabet_uart1_gpio_table); + gpiod_add_lookup_table(&assabet_uart3_gpio_table); gpiod_add_lookup_table(&assabet_cf_vcc_gpio_table); + sa11x0_register_fixed_regulator(0, &assabet_cf_vcc_pdata, assabet_cf_vcc_consumers, ARRAY_SIZE(assabet_cf_vcc_consumers), @@ -655,74 +681,13 @@ static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate) { if (port->mapbase == _Ser1UTCR0) { if (state) - ASSABET_BCR_clear(ASSABET_BCR_RS232EN | - ASSABET_BCR_COM_RTS | - ASSABET_BCR_COM_DTR); - else - ASSABET_BCR_set(ASSABET_BCR_RS232EN | - ASSABET_BCR_COM_RTS | - ASSABET_BCR_COM_DTR); - } -} - -/* - * Assabet uses COM_RTS and COM_DTR for both UART1 (com port) - * and UART3 (radio module). We only handle them for UART1 here. - */ -static void assabet_set_mctrl(struct uart_port *port, u_int mctrl) -{ - if (port->mapbase == _Ser1UTCR0) { - u_int set = 0, clear = 0; - - if (mctrl & TIOCM_RTS) - clear |= ASSABET_BCR_COM_RTS; + ASSABET_BCR_clear(ASSABET_BCR_RS232EN); else - set |= ASSABET_BCR_COM_RTS; - - if (mctrl & TIOCM_DTR) - clear |= ASSABET_BCR_COM_DTR; - else - set |= ASSABET_BCR_COM_DTR; - - ASSABET_BCR_clear(clear); - ASSABET_BCR_set(set); - } -} - -static u_int assabet_get_mctrl(struct uart_port *port) -{ - u_int ret = 0; - u_int bsr = ASSABET_BSR; - - /* need 2 reads to read current value */ - bsr = ASSABET_BSR; - - if (port->mapbase == _Ser1UTCR0) { - if (bsr & ASSABET_BSR_COM_DCD) - ret |= TIOCM_CD; - if (bsr & ASSABET_BSR_COM_CTS) - ret |= TIOCM_CTS; - if (bsr & ASSABET_BSR_COM_DSR) - ret |= TIOCM_DSR; - } else if (port->mapbase == _Ser3UTCR0) { - if (bsr & ASSABET_BSR_RAD_DCD) - ret |= TIOCM_CD; - if (bsr & ASSABET_BSR_RAD_CTS) - ret |= TIOCM_CTS; - if (bsr & ASSABET_BSR_RAD_DSR) - ret |= TIOCM_DSR; - if (bsr & ASSABET_BSR_RAD_RI) - ret |= TIOCM_RI; - } else { - ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; + ASSABET_BCR_set(ASSABET_BCR_RS232EN); } - - return ret; } static struct sa1100_port_fns assabet_port_fns __initdata = { - .set_mctrl = assabet_set_mctrl, - .get_mctrl = assabet_get_mctrl, .pm = assabet_uart_pm, }; diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c index bc0e0e24ecb7..de79f3502045 100644 --- a/arch/arm/mach-sa1100/badge4.c +++ b/arch/arm/mach-sa1100/badge4.c @@ -311,8 +311,6 @@ badge4_uart_pm(struct uart_port *port, u_int state, u_int oldstate) } static struct sa1100_port_fns badge4_port_fns __initdata = { - //.get_mctrl = badge4_get_mctrl, - //.set_mctrl = badge4_set_mctrl, .pm = badge4_uart_pm, }; diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index 6199e87447ca..e8691921c69a 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -2,176 +2,144 @@ /* * linux/arch/arm/mach-sa1100/clock.c */ -#include <linux/module.h> #include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> -#include <linux/string.h> #include <linux/clk.h> -#include <linux/spinlock.h> -#include <linux/mutex.h> -#include <linux/io.h> #include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/spinlock.h> #include <mach/hardware.h> #include <mach/generic.h> -struct clkops { - void (*enable)(struct clk *); - void (*disable)(struct clk *); - unsigned long (*get_rate)(struct clk *); +static const char * const clk_tucr_parents[] = { + "clk32768", "clk3686400", }; -struct clk { - const struct clkops *ops; - unsigned int enabled; -}; - -#define DEFINE_CLK(_name, _ops) \ -struct clk clk_##_name = { \ - .ops = _ops, \ - } - -static DEFINE_SPINLOCK(clocks_lock); - -/* Dummy clk routine to build generic kernel parts that may be using them */ -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - return clk_get_rate(clk); -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - return 0; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - return 0; -} -EXPORT_SYMBOL(clk_set_parent); +static DEFINE_SPINLOCK(tucr_lock); -struct clk *clk_get_parent(struct clk *clk) +static int clk_gpio27_enable(struct clk_hw *hw) { - return NULL; -} -EXPORT_SYMBOL(clk_get_parent); + unsigned long flags; -static void clk_gpio27_enable(struct clk *clk) -{ /* * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: * (SA-1110 Developer's Manual, section 9.1.2.1) */ + local_irq_save(flags); GAFR |= GPIO_32_768kHz; GPDR |= GPIO_32_768kHz; - TUCR = TUCR_3_6864MHz; + local_irq_restore(flags); + + return 0; } -static void clk_gpio27_disable(struct clk *clk) +static void clk_gpio27_disable(struct clk_hw *hw) { - TUCR = 0; + unsigned long flags; + + local_irq_save(flags); GPDR &= ~GPIO_32_768kHz; GAFR &= ~GPIO_32_768kHz; + local_irq_restore(flags); } -static void clk_cpu_enable(struct clk *clk) -{ -} +static const struct clk_ops clk_gpio27_ops = { + .enable = clk_gpio27_enable, + .disable = clk_gpio27_disable, +}; -static void clk_cpu_disable(struct clk *clk) -{ -} +static const char * const clk_gpio27_parents[] = { + "tucr-mux", +}; -static unsigned long clk_cpu_get_rate(struct clk *clk) +static const struct clk_init_data clk_gpio27_init_data __initconst = { + .name = "gpio27", + .ops = &clk_gpio27_ops, + .parent_names = clk_gpio27_parents, + .num_parents = ARRAY_SIZE(clk_gpio27_parents), +}; + +/* + * Derived from the table 8-1 in the SA1110 manual, the MPLL appears to + * multiply its input rate by 4 x (4 + PPCR). This calculation gives + * the exact rate. The figures given in the table are the rates rounded + * to 100kHz. Stick with sa11x0_getspeed() for the time being. + */ +static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw, + unsigned long prate) { return sa11x0_getspeed(0) * 1000; } -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - if (clk) { - spin_lock_irqsave(&clocks_lock, flags); - if (clk->enabled++ == 0) - clk->ops->enable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - } - - return 0; -} -EXPORT_SYMBOL(clk_enable); +static const struct clk_ops clk_mpll_ops = { + .recalc_rate = clk_mpll_recalc_rate, +}; -void clk_disable(struct clk *clk) -{ - unsigned long flags; +static const char * const clk_mpll_parents[] = { + "clk3686400", +}; - if (clk) { - WARN_ON(clk->enabled == 0); - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->enabled == 0) - clk->ops->disable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - } -} -EXPORT_SYMBOL(clk_disable); +static const struct clk_init_data clk_mpll_init_data __initconst = { + .name = "mpll", + .ops = &clk_mpll_ops, + .parent_names = clk_mpll_parents, + .num_parents = ARRAY_SIZE(clk_mpll_parents), + .flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL, +}; -unsigned long clk_get_rate(struct clk *clk) +int __init sa11xx_clk_init(void) { - if (clk && clk->ops && clk->ops->get_rate) - return clk->ops->get_rate(clk); - - return 0; -} -EXPORT_SYMBOL(clk_get_rate); + struct clk_hw *hw; + int ret; -const struct clkops clk_gpio27_ops = { - .enable = clk_gpio27_enable, - .disable = clk_gpio27_disable, -}; + hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768); + if (IS_ERR(hw)) + return PTR_ERR(hw); -const struct clkops clk_cpu_ops = { - .enable = clk_cpu_enable, - .disable = clk_cpu_disable, - .get_rate = clk_cpu_get_rate, -}; + clk_hw_register_clkdev(hw, NULL, "sa1100-rtc"); -static DEFINE_CLK(gpio27, &clk_gpio27_ops); + hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400); + if (IS_ERR(hw)) + return PTR_ERR(hw); -static DEFINE_CLK(cpu, &clk_cpu_ops); + clk_hw_register_clkdev(hw, "OSTIMER0", NULL); -static unsigned long clk_36864_get_rate(struct clk *clk) -{ - return 3686400; -} + hw = kzalloc(sizeof(*hw), GFP_KERNEL); + if (!hw) + return -ENOMEM; + hw->init = &clk_mpll_init_data; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(hw); + return ret; + } -static struct clkops clk_36864_ops = { - .enable = clk_cpu_enable, - .disable = clk_cpu_disable, - .get_rate = clk_36864_get_rate, -}; + clk_hw_register_clkdev(hw, NULL, "sa11x0-fb"); + clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia"); + clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.0"); + clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.1"); + clk_hw_register_clkdev(hw, NULL, "1800"); + + hw = clk_hw_register_mux(NULL, "tucr-mux", clk_tucr_parents, + ARRAY_SIZE(clk_tucr_parents), 0, + (void __iomem *)&TUCR, FShft(TUCR_TSEL), + FAlnMsk(TUCR_TSEL), 0, &tucr_lock); + clk_set_rate(hw->clk, 3686400); + + hw = kzalloc(sizeof(*hw), GFP_KERNEL); + if (!hw) + return -ENOMEM; + hw->init = &clk_gpio27_init_data; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(hw); + return ret; + } -static DEFINE_CLK(36864, &clk_36864_ops); - -static struct clk_lookup sa11xx_clkregs[] = { - CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), - CLKDEV_INIT("sa1100-rtc", NULL, NULL), - CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu), - CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu), - CLKDEV_INIT("sa11x0-pcmcia.0", NULL, &clk_cpu), - CLKDEV_INIT("sa11x0-pcmcia.1", NULL, &clk_cpu), - /* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */ - CLKDEV_INIT("1800", NULL, &clk_cpu), - CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864), -}; + clk_hw_register_clkdev(hw, NULL, "sa1111.0"); -int __init sa11xx_clk_init(void) -{ - clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); return 0; } diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c index e93e3a1d60d5..d685f03f51f3 100644 --- a/arch/arm/mach-sa1100/h3xxx.c +++ b/arch/arm/mach-sa1100/h3xxx.c @@ -83,57 +83,6 @@ static struct resource h3xxx_flash_resource = /* * H3xxx uart support */ -static struct gpio h3xxx_uart_gpio[] = { - { H3XXX_GPIO_COM_DCD, GPIOF_IN, "COM DCD" }, - { H3XXX_GPIO_COM_CTS, GPIOF_IN, "COM CTS" }, - { H3XXX_GPIO_COM_RTS, GPIOF_OUT_INIT_LOW, "COM RTS" }, -}; - -static bool h3xxx_uart_request_gpios(void) -{ - static bool h3xxx_uart_gpio_ok; - int rc; - - if (h3xxx_uart_gpio_ok) - return true; - - rc = gpio_request_array(h3xxx_uart_gpio, ARRAY_SIZE(h3xxx_uart_gpio)); - if (rc) - pr_err("h3xxx_uart_request_gpios: error %d\n", rc); - else - h3xxx_uart_gpio_ok = true; - - return h3xxx_uart_gpio_ok; -} - -static void h3xxx_uart_set_mctrl(struct uart_port *port, u_int mctrl) -{ - if (port->mapbase == _Ser3UTCR0) { - if (!h3xxx_uart_request_gpios()) - return; - gpio_set_value(H3XXX_GPIO_COM_RTS, !(mctrl & TIOCM_RTS)); - } -} - -static u_int h3xxx_uart_get_mctrl(struct uart_port *port) -{ - u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; - - if (port->mapbase == _Ser3UTCR0) { - if (!h3xxx_uart_request_gpios()) - return ret; - /* - * DCD and CTS bits are inverted in GPLR by RS232 transceiver - */ - if (gpio_get_value(H3XXX_GPIO_COM_DCD)) - ret &= ~TIOCM_CD; - if (gpio_get_value(H3XXX_GPIO_COM_CTS)) - ret &= ~TIOCM_CTS; - } - - return ret; -} - static void h3xxx_uart_pm(struct uart_port *port, u_int state, u_int oldstate) { if (port->mapbase == _Ser3UTCR0) { @@ -166,12 +115,20 @@ static int h3xxx_uart_set_wake(struct uart_port *port, u_int enable) } static struct sa1100_port_fns h3xxx_port_fns __initdata = { - .set_mctrl = h3xxx_uart_set_mctrl, - .get_mctrl = h3xxx_uart_get_mctrl, .pm = h3xxx_uart_pm, .set_wake = h3xxx_uart_set_wake, }; +static struct gpiod_lookup_table h3xxx_uart3_gpio_table = { + .dev_id = "sa11x0-uart.3", + .table = { + GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_DCD, "dcd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_CTS, "cts", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_RTS, "rts", GPIO_ACTIVE_LOW), + { }, + }, +}; + /* * EGPIO */ @@ -279,6 +236,7 @@ static struct gpiod_lookup_table h3xxx_pcmcia_gpio_table = { void __init h3xxx_mach_init(void) { gpiod_add_lookup_table(&h3xxx_pcmcia_gpio_table); + gpiod_add_lookup_table(&h3xxx_uart3_gpio_table); sa1100_register_uart_fns(&h3xxx_port_fns); sa11x0_register_mtd(&h3xxx_flash_data, &h3xxx_flash_resource, 1); platform_add_devices(h3xxx_devices, ARRAY_SIZE(h3xxx_devices)); diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c index 4f4c1bb890e0..6d37d263e0d2 100644 --- a/arch/arm/mach-sa1100/hackkit.c +++ b/arch/arm/mach-sa1100/hackkit.c @@ -45,8 +45,6 @@ /* init funcs */ static void __init hackkit_map_io(void); -static u_int hackkit_get_mctrl(struct uart_port *port); -static void hackkit_set_mctrl(struct uart_port *port, u_int mctrl); static void hackkit_uart_pm(struct uart_port *port, u_int state, u_int oldstate); /********************************************************************** @@ -67,8 +65,6 @@ static struct map_desc hackkit_io_desc[] __initdata = { }; static struct sa1100_port_fns hackkit_port_fns __initdata = { - .set_mctrl = hackkit_set_mctrl, - .get_mctrl = hackkit_get_mctrl, .pm = hackkit_uart_pm, }; @@ -101,50 +97,6 @@ static void hackkit_uart_pm(struct uart_port *port, u_int state, u_int oldstate) /* TODO: switch on/off uart in powersave mode */ } -/* - * Note! this can be called from IRQ context. - * FIXME: No modem ctrl lines yet. - */ -static void hackkit_set_mctrl(struct uart_port *port, u_int mctrl) -{ -#if 0 - if (port->mapbase == _Ser1UTCR0) { - u_int set = 0, clear = 0; - - if (mctrl & TIOCM_RTS) - set |= PT_CTRL2_RS1_RTS; - else - clear |= PT_CTRL2_RS1_RTS; - - if (mctrl & TIOCM_DTR) - set |= PT_CTRL2_RS1_DTR; - else - clear |= PT_CTRL2_RS1_DTR; - - PTCTRL2_clear(clear); - PTCTRL2_set(set); - } -#endif -} - -static u_int hackkit_get_mctrl(struct uart_port *port) -{ - u_int ret = 0; -#if 0 - u_int irqsr = PT_IRQSR; - - /* need 2 reads to read current value */ - irqsr = PT_IRQSR; - - /* TODO: check IRQ source register for modem/com - status lines and set them correctly. */ -#endif - - ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; - - return ret; -} - static struct mtd_partition hackkit_partitions[] = { { .name = "BLOB", diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index a671e4c994cf..6876bc1e33b4 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -11,7 +11,6 @@ #include <linux/irq.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/platform_data/sa11x0-serial.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/serial_core.h> @@ -49,23 +48,8 @@ #define IRR_SA1111 (1 << 2) #define NCR_NGPIO 7 - -#define MDM_CTL0_RTS1 (1 << 0) -#define MDM_CTL0_DTR1 (1 << 1) -#define MDM_CTL0_RTS2 (1 << 2) -#define MDM_CTL0_DTR2 (1 << 3) #define MDM_CTL0_NGPIO 4 - -#define MDM_CTL1_CTS1 (1 << 0) -#define MDM_CTL1_DSR1 (1 << 1) -#define MDM_CTL1_DCD1 (1 << 2) -#define MDM_CTL1_CTS2 (1 << 3) -#define MDM_CTL1_DSR2 (1 << 4) -#define MDM_CTL1_DCD2 (1 << 5) #define MDM_CTL1_NGPIO 6 - -#define AUD_SEL_1341 (1 << 0) -#define AUD_MUTE_1341 (1 << 1) #define AUD_NGPIO 2 extern void sa1110_mb_disable(void); @@ -97,6 +81,30 @@ struct neponset_drvdata { struct gpio_chip *gpio[4]; }; +static struct gpiod_lookup_table neponset_uart1_gpio_table = { + .dev_id = "sa11x0-uart.1", + .table = { + GPIO_LOOKUP("neponset-mdm-ctl0", 2, "rts", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("neponset-mdm-ctl0", 3, "dtr", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("neponset-mdm-ctl1", 3, "cts", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("neponset-mdm-ctl1", 4, "dsr", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("neponset-mdm-ctl1", 5, "dcd", GPIO_ACTIVE_LOW), + { }, + }, +}; + +static struct gpiod_lookup_table neponset_uart3_gpio_table = { + .dev_id = "sa11x0-uart.3", + .table = { + GPIO_LOOKUP("neponset-mdm-ctl0", 0, "rts", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("neponset-mdm-ctl0", 1, "dtr", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("neponset-mdm-ctl1", 0, "cts", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("neponset-mdm-ctl1", 1, "dsr", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("neponset-mdm-ctl1", 2, "dcd", GPIO_ACTIVE_LOW), + { }, + }, +}; + static struct gpiod_lookup_table neponset_pcmcia_table = { .dev_id = "1800", .table = { @@ -124,69 +132,6 @@ void neponset_ncr_frob(unsigned int mask, unsigned int val) } EXPORT_SYMBOL(neponset_ncr_frob); -static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) -{ - struct neponset_drvdata *n = nep; - unsigned long mask, val = 0; - - if (!n) - return; - - if (port->mapbase == _Ser1UTCR0) { - mask = MDM_CTL0_RTS2 | MDM_CTL0_DTR2; - - if (!(mctrl & TIOCM_RTS)) - val |= MDM_CTL0_RTS2; - - if (!(mctrl & TIOCM_DTR)) - val |= MDM_CTL0_DTR2; - } else if (port->mapbase == _Ser3UTCR0) { - mask = MDM_CTL0_RTS1 | MDM_CTL0_DTR1; - - if (!(mctrl & TIOCM_RTS)) - val |= MDM_CTL0_RTS1; - - if (!(mctrl & TIOCM_DTR)) - val |= MDM_CTL0_DTR1; - } - - n->gpio[1]->set_multiple(n->gpio[1], &mask, &val); -} - -static u_int neponset_get_mctrl(struct uart_port *port) -{ - void __iomem *base = nep->base; - u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; - u_int mdm_ctl1; - - if (!base) - return ret; - - mdm_ctl1 = readb_relaxed(base + MDM_CTL_1); - if (port->mapbase == _Ser1UTCR0) { - if (mdm_ctl1 & MDM_CTL1_DCD2) - ret &= ~TIOCM_CD; - if (mdm_ctl1 & MDM_CTL1_CTS2) - ret &= ~TIOCM_CTS; - if (mdm_ctl1 & MDM_CTL1_DSR2) - ret &= ~TIOCM_DSR; - } else if (port->mapbase == _Ser3UTCR0) { - if (mdm_ctl1 & MDM_CTL1_DCD1) - ret &= ~TIOCM_CD; - if (mdm_ctl1 & MDM_CTL1_CTS1) - ret &= ~TIOCM_CTS; - if (mdm_ctl1 & MDM_CTL1_DSR1) - ret &= ~TIOCM_DSR; - } - - return ret; -} - -static struct sa1100_port_fns neponset_port_fns = { - .set_mctrl = neponset_set_mctrl, - .get_mctrl = neponset_get_mctrl, -}; - /* * Install handler for Neponset IRQ. Note that we have to loop here * since the ETHERNET and USAR IRQs are level based, and we need to @@ -388,6 +333,8 @@ static int neponset_probe(struct platform_device *dev) d->base + AUD_CTL, AUD_NGPIO, false, neponset_aud_names); + gpiod_add_lookup_table(&neponset_uart1_gpio_table); + gpiod_add_lookup_table(&neponset_uart3_gpio_table); gpiod_add_lookup_table(&neponset_pcmcia_table); /* @@ -402,8 +349,6 @@ static int neponset_probe(struct platform_device *dev) d->irq_base, d->irq_base + NEP_IRQ_NR - 1); nep = d; - sa1100_register_uart_fns(&neponset_port_fns); - /* Ensure that the memory bus request/grant signals are setup */ sa1110_mb_disable(); @@ -442,6 +387,8 @@ static int neponset_remove(struct platform_device *dev) platform_device_unregister(d->smc91x); gpiod_remove_lookup_table(&neponset_pcmcia_table); + gpiod_remove_lookup_table(&neponset_uart3_gpio_table); + gpiod_remove_lookup_table(&neponset_uart1_gpio_table); irq_set_chained_handler(irq, NULL); irq_free_descs(d->irq_base, NEP_IRQ_NR); diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index eea60b20c6b4..9e4bc1865f84 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -17,6 +17,7 @@ #include <linux/of.h> #include <linux/of_fdt.h> #include <linux/of_platform.h> +#include <linux/psci.h> #include <asm/mach/arch.h> #include <asm/secure_cntvoff.h> #include "common.h" @@ -60,9 +61,24 @@ static unsigned int __init get_extal_freq(void) void __init rcar_gen2_timer_init(void) { + bool need_update = true; void __iomem *base; u32 freq; + /* + * If PSCI is available then most likely we are running on PSCI-enabled + * U-Boot which, we assume, has already taken care of resetting CNTVOFF + * and updating counter module before switching to non-secure mode + * and we don't need to. + */ +#ifdef CONFIG_ARM_PSCI_FW + if (psci_ops.cpu_on) + need_update = false; +#endif + + if (need_update == false) + goto skip_update; + secure_cntvoff_init(); if (of_machine_is_compatible("renesas,r8a7745") || @@ -102,6 +118,7 @@ void __init rcar_gen2_timer_init(void) iounmap(base); +skip_update: of_clk_init(NULL); timer_probe(); } diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 05d6b5aada80..57699bd8f107 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig ARCH_STM32 - bool "STMicroelectronics STM32 family" if ARM_SINGLE_ARMV7M || ARCH_MULTI_V7 + bool "STMicroelectronics STM32 family" + depends on ARM_SINGLE_ARMV7M || ARCH_MULTI_V7 select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 select ARM_GIC if ARCH_MULTI_V7 diff --git a/arch/arm/mach-tango/Makefile b/arch/arm/mach-tango/Makefile index da6c633d3cc0..97cd04508fa1 100644 --- a/arch/arm/mach-tango/Makefile +++ b/arch/arm/mach-tango/Makefile @@ -1,7 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -plus_sec := $(call as-instr,.arch_extension sec,+sec) -AFLAGS_smc.o := -Wa,-march=armv7-a$(plus_sec) - obj-y += setup.o smc.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_SUSPEND) += pm.o diff --git a/arch/arm/mach-tango/smc.S b/arch/arm/mach-tango/smc.S index 361a8dc89804..b1752aaa72bc 100644 --- a/arch/arm/mach-tango/smc.S +++ b/arch/arm/mach-tango/smc.S @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ #include <linux/linkage.h> + .arch armv7-a + .arch_extension sec ENTRY(tango_smc) push {lr} mov ip, r1 diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c index 0b763239c0f8..c00ea4f77af6 100644 --- a/arch/arm/mach-versatile/versatile_dt.c +++ b/arch/arm/mach-versatile/versatile_dt.c @@ -16,8 +16,6 @@ #include <linux/of_platform.h> #include <linux/slab.h> #include <linux/amba/bus.h> -#include <linux/amba/clcd.h> -#include <linux/platform_data/video-clcd-versatile.h> #include <linux/amba/mmci.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -34,14 +32,12 @@ */ #define VERSATILE_SYS_PCICTL_OFFSET 0x44 #define VERSATILE_SYS_MCI_OFFSET 0x48 -#define VERSATILE_SYS_CLCD_OFFSET 0x50 /* * VERSATILE peripheral addresses */ #define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */ #define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */ -#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */ #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ #define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */ #define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000) @@ -84,158 +80,6 @@ static struct mmci_platform_data mmc1_plat_data = { }; /* - * CLCD support. - */ -#define SYS_CLCD_MODE_MASK (3 << 0) -#define SYS_CLCD_MODE_888 (0 << 0) -#define SYS_CLCD_MODE_5551 (1 << 0) -#define SYS_CLCD_MODE_565_RLSB (2 << 0) -#define SYS_CLCD_MODE_565_BLSB (3 << 0) -#define SYS_CLCD_NLCDIOON (1 << 2) -#define SYS_CLCD_VDDPOSSWITCH (1 << 3) -#define SYS_CLCD_PWR3V5SWITCH (1 << 4) -#define SYS_CLCD_ID_MASK (0x1f << 8) -#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8) -#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8) -#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8) -#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) -#define SYS_CLCD_ID_VGA (0x1f << 8) - -static bool is_sanyo_2_5_lcd; - -/* - * Disable all display connectors on the interface module. - */ -static void versatile_clcd_disable(struct clcd_fb *fb) -{ - void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET; - u32 val; - - val = readl(sys_clcd); - val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; - writel(val, sys_clcd); - - /* - * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off - */ - if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) { - unsigned long ctrl; - - ctrl = readl(versatile_ib2_ctrl); - ctrl &= ~0x01; - writel(ctrl, versatile_ib2_ctrl); - } -} - -/* - * Enable the relevant connector on the interface module. - */ -static void versatile_clcd_enable(struct clcd_fb *fb) -{ - struct fb_var_screeninfo *var = &fb->fb.var; - void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET; - u32 val; - - val = readl(sys_clcd); - val &= ~SYS_CLCD_MODE_MASK; - - switch (var->green.length) { - case 5: - val |= SYS_CLCD_MODE_5551; - break; - case 6: - if (var->red.offset == 0) - val |= SYS_CLCD_MODE_565_RLSB; - else - val |= SYS_CLCD_MODE_565_BLSB; - break; - case 8: - val |= SYS_CLCD_MODE_888; - break; - } - - /* - * Set the MUX - */ - writel(val, sys_clcd); - - /* - * And now enable the PSUs - */ - val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; - writel(val, sys_clcd); - - /* - * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on - */ - if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) { - unsigned long ctrl; - - ctrl = readl(versatile_ib2_ctrl); - ctrl |= 0x01; - writel(ctrl, versatile_ib2_ctrl); - } -} - -/* - * Detect which LCD panel is connected, and return the appropriate - * clcd_panel structure. Note: we do not have any information on - * the required timings for the 8.4in panel, so we presently assume - * VGA timings. - */ -static int versatile_clcd_setup(struct clcd_fb *fb) -{ - void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET; - const char *panel_name; - u32 val; - - is_sanyo_2_5_lcd = false; - - val = readl(sys_clcd) & SYS_CLCD_ID_MASK; - if (val == SYS_CLCD_ID_SANYO_3_8) - panel_name = "Sanyo TM38QV67A02A"; - else if (val == SYS_CLCD_ID_SANYO_2_5) { - panel_name = "Sanyo QVGA Portrait"; - is_sanyo_2_5_lcd = true; - } else if (val == SYS_CLCD_ID_EPSON_2_2) - panel_name = "Epson L2F50113T00"; - else if (val == SYS_CLCD_ID_VGA) - panel_name = "VGA"; - else { - printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n", - val); - panel_name = "VGA"; - } - - fb->panel = versatile_clcd_get_panel(panel_name); - if (!fb->panel) - return -EINVAL; - - return versatile_clcd_setup_dma(fb, SZ_1M); -} - -static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs) -{ - clcdfb_decode(fb, regs); - - /* Always clear BGR for RGB565: we do the routing externally */ - if (fb->fb.var.green.length == 6) - regs->cntl &= ~CNTL_BGR; -} - -static struct clcd_board clcd_plat_data = { - .name = "Versatile", - .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888, - .check = clcdfb_check, - .decode = versatile_clcd_decode, - .disable = versatile_clcd_disable, - .enable = versatile_clcd_enable, - .setup = versatile_clcd_setup, - .mmap = versatile_clcd_mmap_dma, - .remove = versatile_clcd_remove_dma, -}; - -/* * Lookup table for attaching a specific name and platform_data pointer to * devices as they get created by of_platform_populate(). Ideally this table * would not exist, but the current clock implementation depends on some devices @@ -244,7 +88,6 @@ static struct clcd_board clcd_plat_data = { struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data), OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data), - OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data), {} }; @@ -299,12 +142,12 @@ static void __init versatile_dt_pci_init(void) * driver had it so we will keep it. */ writel(1, versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET); - return; + goto out_put_node; } newprop = kzalloc(sizeof(*newprop), GFP_KERNEL); if (!newprop) - return; + goto out_put_node; newprop->name = kstrdup("status", GFP_KERNEL); newprop->value = kstrdup("disabled", GFP_KERNEL); @@ -312,6 +155,9 @@ static void __init versatile_dt_pci_init(void) of_update_property(np, newprop); pr_info("Not plugged into PCI backplane!\n"); + +out_put_node: + of_node_put(np); } static void __init versatile_dt_init(void) diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index cc798115aa9b..820b60a50125 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -709,7 +709,7 @@ config ARM_VIRT_EXT assistance. A compliant bootloader is required in order to make maximum - use of this feature. Refer to Documentation/arm/Booting for + use of this feature. Refer to Documentation/arm/booting.rst for details. config SWP_EMULATE @@ -875,7 +875,7 @@ config KUSER_HELPERS the CPU type fitted to the system. This permits binaries to be run on ARMv4 through to ARMv7 without modification. - See Documentation/arm/kernel_user_helpers.txt for details. + See Documentation/arm/kernel_user_helpers.rst for details. However, the fixed address nature of these helpers can be used by ROP (return orientated programming) authors when creating diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 0e417233dad7..890eeaac3cbb 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -27,28 +27,6 @@ #ifdef CONFIG_MMU -#ifdef CONFIG_KPROBES -static inline int notify_page_fault(struct pt_regs *regs, unsigned int fsr) -{ - int ret = 0; - - if (!user_mode(regs)) { - /* kprobe_running() needs smp_processor_id() */ - preempt_disable(); - if (kprobe_running() && kprobe_fault_handler(regs, fsr)) - ret = 1; - preempt_enable(); - } - - return ret; -} -#else -static inline int notify_page_fault(struct pt_regs *regs, unsigned int fsr) -{ - return 0; -} -#endif - /* * This is useful to dump out the page tables associated with * 'addr' in mm 'mm'. @@ -265,7 +243,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) vm_fault_t fault; unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; - if (notify_page_fault(regs, fsr)) + if (kprobe_page_fault(regs, fsr)) return 0; tsk = current; diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c index 7a79213db3e1..dfbd7c332866 100644 --- a/arch/arm/plat-iop/i2c.c +++ b/arch/arm/plat-iop/i2c.c @@ -16,6 +16,7 @@ #include <linux/tty.h> #include <linux/serial_core.h> #include <linux/io.h> +#include <linux/gpio/machine.h> #include <asm/pgtable.h> #include <asm/page.h> #include <asm/mach/map.h> @@ -34,6 +35,29 @@ #define IRQ_IOP3XX_I2C_1 IRQ_IOP33X_I2C_1 #endif +/* + * Each of the I2C busses have corresponding GPIO lines, and the driver + * need to access these directly to drive the bus low at times. + */ + +struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup = { + .dev_id = "IOP3xx-I2C.0", + .table = { + GPIO_LOOKUP("gpio-iop", 7, "scl", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-iop", 6, "sda", GPIO_ACTIVE_HIGH), + { } + }, +}; + +struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup = { + .dev_id = "IOP3xx-I2C.1", + .table = { + GPIO_LOOKUP("gpio-iop", 5, "scl", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-iop", 4, "sda", GPIO_ACTIVE_HIGH), + { } + }, +}; + static struct resource iop3xx_i2c0_resources[] = { [0] = { .start = 0xfffff680, diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 53da57fba39c..301e572651c0 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -243,7 +243,7 @@ config SAMSUNG_PM_DEBUG depends on DEBUG_EXYNOS_UART || DEBUG_S3C24XX_UART || DEBUG_S3C2410_UART help Say Y here if you want verbose debugging from the PM Suspend and - Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> + Resume code. See <file:Documentation/arm/samsung-s3c24xx/suspend.rst> for more information. config S3C_PM_DEBUG_LED_SMDK @@ -268,7 +268,7 @@ config SAMSUNG_PM_CHECK Note, this can take several seconds depending on memory size and CPU speed. - See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> + See <file:Documentation/arm/samsung-s3c24xx/suspend.rst> config SAMSUNG_PM_CHECK_CHUNKSIZE int "S3C2410 PM Suspend CRC Chunksize (KiB)" @@ -280,7 +280,7 @@ config SAMSUNG_PM_CHECK_CHUNKSIZE the CRC data block will take more memory, but will identify any faults with better precision. - See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> + See <file:Documentation/arm/samsung-s3c24xx/suspend.rst> config SAMSUNG_WAKEMASK bool diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 4eac94c1eb6f..9e74c7ff6b04 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -7,7 +7,7 @@ # http://www.arm.linux.org.uk/developer/machines/download.php # # Please do not send patches to this file; it is automatically generated! -# To add an entry into this database, please see Documentation/arm/README, +# To add an entry into this database, please see Documentation/arm/arm.rst, # or visit: # # http://www.arm.linux.org.uk/developer/machines/?action=new diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile index ca85df247775..87b7769214e0 100644 --- a/arch/arm/vdso/Makefile +++ b/arch/arm/vdso/Makefile @@ -13,8 +13,7 @@ ccflags-y += -DDISABLE_BRANCH_PROFILING ldflags-$(CONFIG_CPU_ENDIAN_BE8) := --be8 ldflags-y := -Bsymbolic --no-undefined -soname=linux-vdso.so.1 \ -z max-page-size=4096 -nostdlib -shared $(ldflags-y) \ - $(call ld-option, --hash-style=sysv) \ - $(call ld-option, --build-id) \ + --hash-style=sysv --build-id \ -T obj-$(CONFIG_VDSO) += vdso.o diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a36ff61321ce..3adcec05b1f6 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -24,6 +24,7 @@ config ARM64 select ARCH_HAS_KCOV select ARCH_HAS_KEEPINITRD select ARCH_HAS_MEMBARRIER_SYNC_CORE + select ARCH_HAS_PTE_DEVMAP select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_SETUP_DMA_OPS select ARCH_HAS_SET_DIRECT_MAP @@ -72,6 +73,7 @@ config ARM64 select ARCH_SUPPORTS_NUMA_BALANCING select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT select ARCH_WANT_FRAME_POINTERS + select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) select ARCH_HAS_UBSAN_SANITIZE_ALL select ARM_AMBA select ARM_ARCH_TIMER @@ -905,7 +907,6 @@ config SYS_SUPPORTS_HUGETLBFS def_bool y config ARCH_WANT_HUGE_PMD_SHARE - def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) config ARCH_HAS_CACHE_LINE_SIZE def_bool y @@ -996,7 +997,7 @@ config CRASH_DUMP reserved region and then later executed after a crash by kdump/kexec. - For more details see Documentation/kdump/kdump.rst + For more details see Documentation/admin-guide/kdump/kdump.rst config XEN_DOM0 def_bool y @@ -1142,7 +1143,7 @@ config KUSER_HELPERS the system. This permits binaries to be run on ARMv4 through to ARMv8 without modification. - See Documentation/arm/kernel_user_helpers.txt for details. + See Documentation/arm/kernel_user_helpers.rst for details. However, the fixed address nature of these helpers can be used by ROP (return orientated programming) authors when creating diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index d07fc063c930..4778c775de1b 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -66,8 +66,11 @@ config ARCH_BITMAIN config ARCH_BRCMSTB bool "Broadcom Set-Top-Box SoCs" + select ARCH_HAS_RESET_CONTROLLER + select BCM7038_L1_IRQ select BRCMSTB_L2_IRQ select GENERIC_IRQ_CHIP + select PINCTRL help This enables support for Broadcom's ARMv8 Set Top Box SoCs diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi index c3a618e1279a..f0349ef4bfdd 100644 --- a/arch/arm64/boot/dts/allwinner/axp803.dtsi +++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi @@ -185,4 +185,10 @@ status = "disabled"; }; }; + + usb_power_supply: usb-power-supply { + compatible = "x-powers,axp803-usb-power-supply", + "x-powers,axp813-usb-power-supply"; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts index 019ae09ea0fd..5634245d11db 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts @@ -85,8 +85,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; sensor@48 { @@ -99,6 +97,22 @@ bias-pull-up; }; +&i2c1 { + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt5663"; + reg = <0x5d>; + AVDD28-supply = <®_ldo_io0>; /* VCC-CTP: GPIO0-LDO */ + interrupt-parent = <&pio>; + interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ + reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH8 */ + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; @@ -262,6 +276,13 @@ regulator-name = "vdd-cpus"; }; +®_ldo_io0 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-ctp"; + status = "okay"; +}; + ®_rtc_ldo { regulator-name = "vcc-rtc"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 0a56c0c23ba1..208373efee49 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -145,8 +145,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; @@ -394,8 +392,13 @@ status = "okay"; }; +&usb_power_supply { + status = "okay"; +}; + &usbphy { usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index f4e78531f639..9b9d9157128c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -120,12 +120,6 @@ }; /* i2c1 connected with gpio headers like pine64, bananapi */ -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; -}; - &i2c1_pins { bias-pull-up; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts index 6a2154525d1e..787ebd805a3b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts @@ -37,6 +37,22 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + AVDD28-supply = <®_ldo_io0>; /* VDD_CTP: GPIO0-LDO */ + interrupt-parent = <&pio>; + interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ + reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH11 */ + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -52,6 +68,13 @@ regulator-name = "vcc-phy"; }; +®_ldo_io0 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vdd-ctp"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index 510f661229dc..5ef3c62c765e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -109,6 +109,8 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; @@ -170,6 +172,14 @@ bus-width = <4>; non-removable; status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ + interrupt-names = "host-wake"; + }; }; &ohci0 { @@ -342,7 +352,20 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <1500000>; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo4>; + device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; }; /* On Pi-2 connector, RTS/CTS optional */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index b7ac6374b178..409523cb0950 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -122,8 +122,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index 0ec46b969a75..1069e7012c9c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -79,6 +79,25 @@ compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; + + speaker_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&r_pio 0 12 GPIO_ACTIVE_HIGH>; /* PL12 */ + sound-name-prefix = "Speaker Amp"; + }; +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&dai { + status = "okay"; }; &ehci1 { @@ -92,8 +111,6 @@ */ &i2c0 { clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; }; @@ -279,6 +296,29 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; + simple-audio-card,widgets = "Headphone", "Headphone Jack", + "Microphone", "Headset Microphone", + "Microphone", "Internal Microphone", + "Speaker", "Internal Speaker"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Headphone Jack", "HP", + "Speaker Amp INL", "LINEOUT", + "Speaker Amp INR", "LINEOUT", + "Internal Speaker", "Speaker Amp OUTL", + "Internal Speaker", "Speaker Amp OUTR", + "Internal Microphone", "MBIAS", + "MIC1", "Internal Microphone", + "Headset Microphone", "HBIAS", + "MIC2", "Headset Microphone"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8c5b521e6389..9cc9bdde81ac 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -611,6 +611,16 @@ function = "i2c1"; }; + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD6", "PD7", "PD8", "PD9", + "PD10", "PD11", "PD12", "PD13", + "PD14", "PD15", "PD16", "PD17", + "PD18", "PD19", "PD20", "PD21"; + function = "lcd0"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -730,6 +740,14 @@ status = "disabled"; }; + lradc: lradc@1c21800 { + compatible = "allwinner,sun50i-a64-lradc", + "allwinner,sun8i-a83t-r-lradc"; + reg = <0x01c21800 0x400>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2s0: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-i2s", @@ -842,6 +860,8 @@ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -853,6 +873,8 @@ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts index 62409afbaf06..c924090331d0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts @@ -55,8 +55,7 @@ regulator-ramp-delay = <50>; /* 4ms */ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ gpios-states = <0x1>; - states = <1100000 0x0 - 1300000 0x1>; + states = <1100000 0>, <1300000 1>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts index 9887948d5c86..1c7dde84e54d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts @@ -104,8 +104,7 @@ regulator-ramp-delay = <50>; /* 4ms */ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; gpios-states = <0x1>; - states = <1100000 0x0 - 1300000 0x1>; + states = <1100000 0>, <1300000 1>; }; wifi_pwrseq: wifi_pwrseq { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 4802902e128f..189834518391 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -127,6 +127,12 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_bldo2>; + vcc-pd-supply = <®_cldo1>; + vcc-pg-supply = <®_aldo1>; +}; + &r_i2c { status = "okay"; @@ -243,10 +249,16 @@ pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; #clock-cells = <0>; }; }; +&r_pio { + vcc-pm-supply = <®_aldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 16c5c3d0fd81..7628a7c83096 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -203,11 +203,32 @@ #reset-cells = <1>; }; + dma: dma-controller@3002000 { + compatible = "allwinner,sun50i-h6-dma"; + reg = <0x03002000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + dma-channels = <16>; + dma-requests = <46>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + sid: sid@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; }; + watchdog: watchdog@30090a0 { + compatible = "allwinner,sun50i-h6-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x030090a0 0x20>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + /* Broken on some H6 boards */ + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; @@ -622,6 +643,13 @@ #reset-cells = <1>; }; + r_watchdog: watchdog@7020400 { + compatible = "allwinner,sun50i-h6-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x07020400 0x20>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + r_intc: interrupt-controller@7021000 { compatible = "allwinner,sun50i-h6-r-intc", "allwinner,sun6i-a31-r-intc"; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 4b0f674df849..b05d78164fc1 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -138,7 +138,7 @@ }; gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff800000 0x2000>; interrupts = <0 90 4>; interrupt-names = "macirq"; @@ -156,7 +156,7 @@ }; gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff802000 0x2000>; interrupts = <0 91 4>; interrupt-names = "macirq"; @@ -169,12 +169,12 @@ rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; iommus = <&smmu 2>; - altr,sysmgr-syscon = <&sysmgr 0x48 0>; + altr,sysmgr-syscon = <&sysmgr 0x48 8>; status = "disabled"; }; gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff804000 0x2000>; interrupts = <0 92 4>; interrupt-names = "macirq"; @@ -187,7 +187,7 @@ rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; iommus = <&smmu 3>; - altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + altr,sysmgr-syscon = <&sysmgr 0x4c 16>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index e129c03ced14..07b861fe5fa5 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 75fe1a2c49d0..4cd2d5951822 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -482,8 +482,8 @@ /* emmc storage */ &sd_emmc_c { - status = "disabled"; - pinctrl-0 = <&emmc_pins>; + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; pinctrl-1 = <&emmc_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 34704fecf756..6219337033a0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -171,7 +171,9 @@ ranges; ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; + compatible = "amlogic,meson-axg-dwmac", + "snps,dwmac-3.70a", + "snps,dwmac"; reg = <0x0 0xff3f0000 0x0 0x10000 0x0 0xff634540 0x0 0x8>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -299,7 +301,7 @@ }; emmc_pins: emmc { - mux { + mux-0 { groups = "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", @@ -308,14 +310,26 @@ "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", - "emmc_clk", - "emmc_cmd", - "emmc_ds"; + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + }; + + mux-1 { + groups = "emmc_clk"; function = "emmc"; bias-disable; }; }; + emmc_ds_pins: emmc_ds { + mux { + groups = "emmc_ds"; + function = "emmc"; + bias-pull-down; + }; + }; + emmc_clk_gate_pins: emmc_clk_gate { mux { groups = "BOOT_8"; @@ -559,13 +573,18 @@ }; sdio_pins: sdio { - mux { + mux-0 { groups = "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", - "sdio_cmd", - "sdio_clk"; + "sdio_cmd"; + function = "sdio"; + bias-pull-up; + }; + + mux-1 { + groups = "sdio_clk"; function = "sdio"; bias-disable; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index 34b40587e5ef..c7a87368850b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -9,15 +9,12 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/meson-g12a-gpio.h> +#include <dt-bindings/sound/meson-g12a-tohdmitx.h> / { compatible = "seirobotics,sei510", "amlogic,g12a"; model = "SEI Robotics SEI510"; - aliases { - serial0 = &uart_AO; - }; - adc_keys { compatible = "adc-keys"; io-channels = <&saradc 0>; @@ -31,13 +28,25 @@ }; }; - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + mono_dac: audio-codec-0 { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + sound-name-prefix = "U16"; + sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; + }; + + dmics: audio-codec-1 { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <50>; + status = "okay"; + sound-name-prefix = "MIC"; }; chosen { @@ -54,21 +63,9 @@ }; }; - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; }; hdmi-connector { @@ -87,12 +84,30 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; + ao_5v: regulator-ao_5v { + compatible = "regulator-fixed"; + regulator-name = "AO_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + dc_in: regulator-dc_in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + emmc_1v8: regulator-emmc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; }; vddao_3v3: regulator-vddao_3v3 { @@ -122,6 +137,146 @@ vin-supply = <&vddao_3v3>; regulator-always-on; }; + + reserved-memory { + /* TEE Reserved Memory */ + bl32_reserved: bl32@5000000 { + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "G12A-SEI510"; + audio-aux-devs = <&tdmout_a>, <&tdmout_b>, + <&tdmin_a>, <&tdmin_b>; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", + "TDM_A Playback", "TDMOUT_A OUT", + "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "TODDR_A IN 4", "PDM Capture", + "TODDR_B IN 4", "PDM Capture", + "TODDR_C IN 4", "PDM Capture", + "TDMIN_A IN 0", "TDM_A Capture", + "TDMIN_A IN 3", "TDM_A Loopback", + "TDMIN_B IN 0", "TDM_A Capture", + "TDMIN_B IN 3", "TDM_A Loopback", + "TDMIN_A IN 1", "TDM_B Capture", + "TDMIN_A IN 4", "TDM_B Loopback", + "TDMIN_B IN 1", "TDM_B Capture", + "TDMIN_B IN 4", "TDM_B Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT", + "TODDR_A IN 1", "TDMIN_B OUT", + "TODDR_B IN 1", "TDMIN_B OUT", + "TODDR_C IN 1", "TDMIN_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + dai-link-3 { + sound-dai = <&toddr_a>; + }; + + dai-link-4 { + sound-dai = <&toddr_b>; + }; + + dai-link-5 { + sound-dai = <&toddr_c>; + }; + + /* internal speaker interface */ + dai-link-6 { + sound-dai = <&tdmif_a>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&mono_dac>; + }; + + codec-1 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; + }; + }; + + /* 8ch hdmi interface */ + dai-link-7 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec@0 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* internal digital mics */ + dai-link-8 { + sound-dai = <&pdm>; + + codec { + sound-dai = <&dmics>; + }; + }; + + /* hdmi glue */ + dai-link-9 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; }; &cec_AO { @@ -138,27 +293,32 @@ hdmi-phandle = <&hdmi_tx>; }; +&clkc_audio { + status = "okay"; +}; + &cvbs_vdac_port { cvbs_vdac_out: endpoint { remote-endpoint = <&cvbs_connector_in>; }; }; -&saradc { +ðmac { status = "okay"; - vref-supply = <&vddio_ao1v8>; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; }; -&uart_A { +&frddr_a { status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; +}; - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - }; +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; }; &hdmi_tx { @@ -173,6 +333,163 @@ }; }; +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&pdm { + pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>, + <&pdm_din2_z_pins>, <&pdm_din3_z_pins>, + <&pdm_dclk_z_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao1v8>; +}; + +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&tdmif_a { + pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; + pinctrl-names = "default"; + status = "okay"; + + assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, + <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; + assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>; + assigned-clock-rates = <0>, <0>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmin_a { + status = "okay"; +}; + +&tdmin_b { + status = "okay"; +}; + +&tdmout_a { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + vbat-supply = <&vddao_3v3>; + vddio-supply = <&vddio_ao1v8>; + }; +}; + &uart_AO { status = "okay"; pinctrl-0 = <&uart_ao_a_pins>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index 0e8045b8a915..8551fbd4a488 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -15,14 +15,12 @@ aliases { serial0 = &uart_AO; + ethernet0 = ðmac; }; + chosen { stdout-path = "serial0:115200n8"; }; - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; cvbs-connector { compatible = "composite-video-connector"; @@ -34,13 +32,9 @@ }; }; - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; }; hdmi-connector { @@ -54,6 +48,20 @@ }; }; + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + flash_1v8: regulator-flash_1v8 { + compatible = "regulator-fixed"; + regulator-name = "FLASH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + main_12v: regulator-main_12v { compatible = "regulator-fixed"; regulator-name = "12V"; @@ -62,6 +70,17 @@ regulator-always-on; }; + usb_pwr_en: regulator-usb_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + vcc_1v8: regulator-vcc_1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; @@ -92,17 +111,6 @@ enable-active-high; }; - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - vddao_1v8: regulator-vddao_1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; @@ -143,6 +151,12 @@ }; }; +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; @@ -156,6 +170,70 @@ }; }; +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +/* i2c Touch */ +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>; + pinctrl-names = "default"; +}; + +/* i2c CM */ +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>; + pinctrl-names = "default"; +}; + +/* i2c Audio */ +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; + &uart_AO { status = "okay"; pinctrl-0 = <&uart_ao_a_pins>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index b3d913f28f12..fe4013cca876 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -8,6 +8,7 @@ #include "meson-g12a.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/meson-g12a-gpio.h> +#include <dt-bindings/sound/meson-g12a-tohdmitx.h> / { compatible = "amediatech,x96-max", "amlogic,u200", "amlogic,g12a"; @@ -15,7 +16,16 @@ aliases { serial0 = &uart_AO; + ethernet0 = ðmac; }; + + spdif_dit: audio-codec-1 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -45,6 +55,18 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + flash_1v8: regulator-flash_1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; @@ -109,6 +131,97 @@ vin-supply = <&dc_in>; regulator-always-on; }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "G12A-X96-MAX"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "SPDIFOUT IN 0", "FRDDR_A OUT 3", + "SPDIFOUT IN 1", "FRDDR_B OUT 3", + "SPDIFOUT IN 2", "FRDDR_C OUT 3"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* spdif hdmi or toslink interface */ + dai-link-4 { + sound-dai = <&spdifout>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + + codec-1 { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; + }; + }; + + /* spdif hdmi interface */ + dai-link-5 { + sound-dai = <&spdifout_b>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-6 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; +}; + +&arb { + status = "okay"; }; &cec_AO { @@ -125,12 +238,28 @@ hdmi-phandle = <&hdmi_tx>; }; +&clkc_audio { + status = "okay"; +}; + &cvbs_vdac_port { cvbs_vdac_out: endpoint { remote-endpoint = <&cvbs_connector_in>; }; }; +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; @@ -144,6 +273,46 @@ }; }; +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + eee-broken-1000t; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + &uart_A { status = "okay"; pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; @@ -153,6 +322,9 @@ bluetooth { compatible = "brcm,bcm43438-bt"; shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; }; }; @@ -166,3 +338,88 @@ status = "okay"; dr_mode = "host"; }; + +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_1v8>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; + +&spdifout { + pinctrl-0 = <&spdif_out_h_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spdifout_b { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 9f72396ba710..f8d43e3dcf20 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -5,10 +5,12 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/axg-audio-clkc.h> #include <dt-bindings/clock/g12a-clkc.h> #include <dt-bindings/clock/g12a-aoclkc.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> #include <dt-bindings/reset/amlogic,meson-g12a-reset.h> / { @@ -18,6 +20,39 @@ #address-cells = <2>; #size-cells = <2>; + tdmif_a: audio-controller-0 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_A"; + clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, + <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_b: audio-controller-1 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_B"; + clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, + <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_c: audio-controller-2 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_C"; + clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, + <&clkc_audio AUD_CLKID_MST_C_SCLK>, + <&clkc_audio AUD_CLKID_MST_C_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + cpus { #address-cells = <0x2>; #size-cells = <0x0>; @@ -102,6 +137,27 @@ #size-cells = <2>; ranges; + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,meson-axg-dwmac", + "snps,dwmac-3.70a", + "snps,dwmac"; + reg = <0x0 0xff3f0000 0x0 0x10000 + 0x0 0xff634540 0x0 0x8>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + status = "disabled"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + }; + apb: bus@ff600000 { compatible = "simple-bus"; reg = <0x0 0xff600000 0x0 0x200000>; @@ -123,6 +179,7 @@ clock-names = "isfr", "iahb", "venci"; #address-cells = <1>; #size-cells = <0>; + #sound-dai-cells = <0>; status = "disabled"; /* VPU VENC Input */ @@ -140,6 +197,19 @@ }; }; + apb_efuse: bus@30000 { + compatible = "simple-bus"; + reg = <0x0 0x30000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; + + hwrng: rng@218 { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x218 0x0 0x4>; + }; + }; + periphs: bus@34400 { compatible = "simple-bus"; reg = <0x0 0x34400 0x0 0x400>; @@ -185,12 +255,55 @@ }; }; + emmc_pins: emmc { + mux-0 { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "emmc_clk"; + function = "emmc"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_nand_ds"; + function = "emmc"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + hdmitx_ddc_pins: hdmitx_ddc { mux { groups = "hdmitx_sda", "hdmitx_sck"; function = "hdmitx"; bias-disable; + drive-strength-microamp = <4000>; }; }; @@ -202,6 +315,1040 @@ }; }; + + i2c0_sda_c_pins: i2c0-sda-c { + mux { + groups = "i2c0_sda_c"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + + }; + }; + + i2c0_sck_c_pins: i2c0-sck-c { + mux { + groups = "i2c0_sck_c"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sda_z0_pins: i2c0-sda-z0 { + mux { + groups = "i2c0_sda_z0"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sck_z1_pins: i2c0-sck-z1 { + mux { + groups = "i2c0_sck_z1"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sda_z7_pins: i2c0-sda-z7 { + mux { + groups = "i2c0_sda_z7"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sda_z8_pins: i2c0-sda-z8 { + mux { + groups = "i2c0_sda_z8"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sda_x_pins: i2c1-sda-x { + mux { + groups = "i2c1_sda_x"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sck_x_pins: i2c1-sck-x { + mux { + groups = "i2c1_sck_x"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sda_h2_pins: i2c1-sda-h2 { + mux { + groups = "i2c1_sda_h2"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sck_h3_pins: i2c1-sck-h3 { + mux { + groups = "i2c1_sck_h3"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sda_h6_pins: i2c1-sda-h6 { + mux { + groups = "i2c1_sda_h6"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sck_h7_pins: i2c1-sck-h7 { + mux { + groups = "i2c1_sck_h7"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sda_x_pins: i2c2-sda-x { + mux { + groups = "i2c2_sda_x"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sck_x_pins: i2c2-sck-x { + mux { + groups = "i2c2_sck_x"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sda_z_pins: i2c2-sda-z { + mux { + groups = "i2c2_sda_z"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sck_z_pins: i2c2-sck-z { + mux { + groups = "i2c2_sck_z"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sda_h_pins: i2c3-sda-h { + mux { + groups = "i2c3_sda_h"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sck_h_pins: i2c3-sck-h { + mux { + groups = "i2c3_sck_h"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sda_a_pins: i2c3-sda-a { + mux { + groups = "i2c3_sda_a"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sck_a_pins: i2c3-sck-a { + mux { + groups = "i2c3_sck_a"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk0_a_pins: mclk0-a { + mux { + groups = "mclk0_a"; + function = "mclk0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk1_a_pins: mclk1-a { + mux { + groups = "mclk1_a"; + function = "mclk1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk1_x_pins: mclk1-x { + mux { + groups = "mclk1_x"; + function = "mclk1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk1_z_pins: mclk1-z { + mux { + groups = "mclk1_z"; + function = "mclk1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + pdm_din0_a_pins: pdm-din0-a { + mux { + groups = "pdm_din0_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din0_c_pins: pdm-din0-c { + mux { + groups = "pdm_din0_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din0_x_pins: pdm-din0-x { + mux { + groups = "pdm_din0_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din0_z_pins: pdm-din0-z { + mux { + groups = "pdm_din0_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_a_pins: pdm-din1-a { + mux { + groups = "pdm_din1_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_c_pins: pdm-din1-c { + mux { + groups = "pdm_din1_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_x_pins: pdm-din1-x { + mux { + groups = "pdm_din1_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_z_pins: pdm-din1-z { + mux { + groups = "pdm_din1_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_a_pins: pdm-din2-a { + mux { + groups = "pdm_din2_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_c_pins: pdm-din2-c { + mux { + groups = "pdm_din2_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_x_pins: pdm-din2-x { + mux { + groups = "pdm_din2_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_z_pins: pdm-din2-z { + mux { + groups = "pdm_din2_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_a_pins: pdm-din3-a { + mux { + groups = "pdm_din3_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_c_pins: pdm-din3-c { + mux { + groups = "pdm_din3_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_x_pins: pdm-din3-x { + mux { + groups = "pdm_din3_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_z_pins: pdm-din3-z { + mux { + groups = "pdm_din3_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_dclk_a_pins: pdm-dclk-a { + mux { + groups = "pdm_dclk_a"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pdm_dclk_c_pins: pdm-dclk-c { + mux { + groups = "pdm_dclk_c"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pdm_dclk_x_pins: pdm-dclk-x { + mux { + groups = "pdm_dclk_x"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pdm_dclk_z_pins: pdm-dclk-z { + mux { + groups = "pdm_dclk_z"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pwm_a_pins: pwm-a { + mux { + groups = "pwm_a"; + function = "pwm_a"; + bias-disable; + }; + }; + + pwm_b_x7_pins: pwm-b-x7 { + mux { + groups = "pwm_b_x7"; + function = "pwm_b"; + bias-disable; + }; + }; + + pwm_b_x19_pins: pwm-b-x19 { + mux { + groups = "pwm_b_x19"; + function = "pwm_b"; + bias-disable; + }; + }; + + pwm_c_c_pins: pwm-c-c { + mux { + groups = "pwm_c_c"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_c_x5_pins: pwm-c-x5 { + mux { + groups = "pwm_c_x5"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_c_x8_pins: pwm-c-x8 { + mux { + groups = "pwm_c_x8"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_d_x3_pins: pwm-d-x3 { + mux { + groups = "pwm_d_x3"; + function = "pwm_d"; + bias-disable; + }; + }; + + pwm_d_x6_pins: pwm-d-x6 { + mux { + groups = "pwm_d_x6"; + function = "pwm_d"; + bias-disable; + }; + }; + + pwm_e_pins: pwm-e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + bias-disable; + }; + }; + + pwm_f_x_pins: pwm-f-x { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + bias-disable; + }; + }; + + pwm_f_h_pins: pwm-f-h { + mux { + groups = "pwm_f_h"; + function = "pwm_f"; + bias-disable; + }; + }; + + sdcard_c_pins: sdcard_c { + mux-0 { + groups = "sdcard_d0_c", + "sdcard_d1_c", + "sdcard_d2_c", + "sdcard_d3_c", + "sdcard_cmd_c"; + function = "sdcard"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "sdcard_clk_c"; + function = "sdcard"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_clk_gate_c_pins: sdcard_clk_gate_c { + mux { + groups = "GPIOC_4"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_z_pins: sdcard_z { + mux-0 { + groups = "sdcard_d0_z", + "sdcard_d1_z", + "sdcard_d2_z", + "sdcard_d3_z", + "sdcard_cmd_z"; + function = "sdcard"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "sdcard_clk_z"; + function = "sdcard"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_clk_gate_z_pins: sdcard_clk_gate_z { + mux { + groups = "GPIOZ_6"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_clk", + "sdio_cmd"; + function = "sdio"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + spdif_in_a10_pins: spdif-in-a10 { + mux { + groups = "spdif_in_a10"; + function = "spdif_in"; + bias-disable; + }; + }; + + spdif_in_a12_pins: spdif-in-a12 { + mux { + groups = "spdif_in_a12"; + function = "spdif_in"; + bias-disable; + }; + }; + + spdif_in_h_pins: spdif-in-h { + mux { + groups = "spdif_in_h"; + function = "spdif_in"; + bias-disable; + }; + }; + + spdif_out_h_pins: spdif-out-h { + mux { + groups = "spdif_out_h"; + function = "spdif_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + spdif_out_a11_pins: spdif-out-a11 { + mux { + groups = "spdif_out_a11"; + function = "spdif_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + spdif_out_a13_pins: spdif-out-a13 { + mux { + groups = "spdif_out_a13"; + function = "spdif_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + tdm_a_din0_pins: tdm-a-din0 { + mux { + groups = "tdm_a_din0"; + function = "tdm_a"; + bias-disable; + }; + }; + + + tdm_a_din1_pins: tdm-a-din1 { + mux { + groups = "tdm_a_din1"; + function = "tdm_a"; + bias-disable; + }; + }; + + tdm_a_dout0_pins: tdm-a-dout0 { + mux { + groups = "tdm_a_dout0"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_dout1_pins: tdm-a-dout1 { + mux { + groups = "tdm_a_dout1"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_fs_pins: tdm-a-fs { + mux { + groups = "tdm_a_fs"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_sclk_pins: tdm-a-sclk { + mux { + groups = "tdm_a_sclk"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_slv_fs_pins: tdm-a-slv-fs { + mux { + groups = "tdm_a_slv_fs"; + function = "tdm_a"; + bias-disable; + }; + }; + + + tdm_a_slv_sclk_pins: tdm-a-slv-sclk { + mux { + groups = "tdm_a_slv_sclk"; + function = "tdm_a"; + bias-disable; + }; + }; + + tdm_b_din0_pins: tdm-b-din0 { + mux { + groups = "tdm_b_din0"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din1_pins: tdm-b-din1 { + mux { + groups = "tdm_b_din1"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din2_pins: tdm-b-din2 { + mux { + groups = "tdm_b_din2"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din3_a_pins: tdm-b-din3-a { + mux { + groups = "tdm_b_din3_a"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din3_h_pins: tdm-b-din3-h { + mux { + groups = "tdm_b_din3_h"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_dout0_pins: tdm-b-dout0 { + mux { + groups = "tdm_b_dout0"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout1_pins: tdm-b-dout1 { + mux { + groups = "tdm_b_dout1"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout2_pins: tdm-b-dout2 { + mux { + groups = "tdm_b_dout2"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout3_a_pins: tdm-b-dout3-a { + mux { + groups = "tdm_b_dout3_a"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout3_h_pins: tdm-b-dout3-h { + mux { + groups = "tdm_b_dout3_h"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_fs_pins: tdm-b-fs { + mux { + groups = "tdm_b_fs"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_sclk_pins: tdm-b-sclk { + mux { + groups = "tdm_b_sclk"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_slv_fs_pins: tdm-b-slv-fs { + mux { + groups = "tdm_b_slv_fs"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_slv_sclk_pins: tdm-b-slv-sclk { + mux { + groups = "tdm_b_slv_sclk"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_c_din0_a_pins: tdm-c-din0-a { + mux { + groups = "tdm_c_din0_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din0_z_pins: tdm-c-din0-z { + mux { + groups = "tdm_c_din0_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din1_a_pins: tdm-c-din1-a { + mux { + groups = "tdm_c_din1_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din1_z_pins: tdm-c-din1-z { + mux { + groups = "tdm_c_din1_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din2_a_pins: tdm-c-din2-a { + mux { + groups = "tdm_c_din2_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + eth_leds_pins: eth-leds { + mux { + groups = "eth_link_led", + "eth_act_led"; + function = "eth"; + bias-disable; + }; + }; + + eth_pins: eth { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_txen", + "eth_txd0", + "eth_txd1"; + function = "eth"; + drive-strength-microamp = <4000>; + bias-disable; + }; + }; + + eth_rgmii_pins: eth-rgmii { + mux { + groups = "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength-microamp = <4000>; + bias-disable; + }; + }; + + tdm_c_din2_z_pins: tdm-c-din2-z { + mux { + groups = "tdm_c_din2_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din3_a_pins: tdm-c-din3-a { + mux { + groups = "tdm_c_din3_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din3_z_pins: tdm-c-din3-z { + mux { + groups = "tdm_c_din3_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_dout0_a_pins: tdm-c-dout0-a { + mux { + groups = "tdm_c_dout0_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout0_z_pins: tdm-c-dout0-z { + mux { + groups = "tdm_c_dout0_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout1_a_pins: tdm-c-dout1-a { + mux { + groups = "tdm_c_dout1_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout1_z_pins: tdm-c-dout1-z { + mux { + groups = "tdm_c_dout1_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout2_a_pins: tdm-c-dout2-a { + mux { + groups = "tdm_c_dout2_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout2_z_pins: tdm-c-dout2-z { + mux { + groups = "tdm_c_dout2_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout3_a_pins: tdm-c-dout3-a { + mux { + groups = "tdm_c_dout3_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout3_z_pins: tdm-c-dout3-z { + mux { + groups = "tdm_c_dout3_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_fs_a_pins: tdm-c-fs-a { + mux { + groups = "tdm_c_fs_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_fs_z_pins: tdm-c-fs-z { + mux { + groups = "tdm_c_fs_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_sclk_a_pins: tdm-c-sclk-a { + mux { + groups = "tdm_c_sclk_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_sclk_z_pins: tdm-c-sclk-z { + mux { + groups = "tdm_c_sclk_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { + mux { + groups = "tdm_c_slv_fs_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { + mux { + groups = "tdm_c_slv_fs_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { + mux { + groups = "tdm_c_slv_sclk_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { + mux { + groups = "tdm_c_slv_sclk_z"; + function = "tdm_c"; + bias-disable; + }; + }; + uart_a_pins: uart-a { mux { groups = "uart_a_tx", @@ -303,6 +1450,282 @@ }; }; + pdm: audio-controller@40000 { + compatible = "amlogic,g12a-pdm", + "amlogic,axg-pdm"; + reg = <0x0 0x40000 0x0 0x34>; + #sound-dai-cells = <0>; + sound-name-prefix = "PDM"; + clocks = <&clkc_audio AUD_CLKID_PDM>, + <&clkc_audio AUD_CLKID_PDM_DCLK>, + <&clkc_audio AUD_CLKID_PDM_SYSCLK>; + clock-names = "pclk", "dclk", "sysclk"; + status = "disabled"; + }; + + audio: bus@42000 { + compatible = "simple-bus"; + reg = <0x0 0x42000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; + + clkc_audio: clock-controller@0 { + status = "disabled"; + compatible = "amlogic,g12a-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + + resets = <&reset RESET_AUDIO>; + }; + + toddr_a: audio-controller@100 { + compatible = "amlogic,g12a-toddr", + "amlogic,axg-toddr"; + reg = <0x0 0x100 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_A"; + interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_TODDR_A>; + resets = <&arb AXG_ARB_TODDR_A>; + status = "disabled"; + }; + + toddr_b: audio-controller@140 { + compatible = "amlogic,g12a-toddr", + "amlogic,axg-toddr"; + reg = <0x0 0x140 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_B"; + interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_TODDR_B>; + resets = <&arb AXG_ARB_TODDR_B>; + status = "disabled"; + }; + + toddr_c: audio-controller@180 { + compatible = "amlogic,g12a-toddr", + "amlogic,axg-toddr"; + reg = <0x0 0x180 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_C"; + interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_TODDR_C>; + resets = <&arb AXG_ARB_TODDR_C>; + status = "disabled"; + }; + + frddr_a: audio-controller@1c0 { + compatible = "amlogic,g12a-frddr", + "amlogic,axg-frddr"; + reg = <0x0 0x1c0 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_A"; + interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; + resets = <&arb AXG_ARB_FRDDR_A>; + status = "disabled"; + }; + + frddr_b: audio-controller@200 { + compatible = "amlogic,g12a-frddr", + "amlogic,axg-frddr"; + reg = <0x0 0x200 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_B"; + interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; + resets = <&arb AXG_ARB_FRDDR_B>; + status = "disabled"; + }; + + frddr_c: audio-controller@240 { + compatible = "amlogic,g12a-frddr", + "amlogic,axg-frddr"; + reg = <0x0 0x240 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_C"; + interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; + resets = <&arb AXG_ARB_FRDDR_C>; + status = "disabled"; + }; + + arb: reset-controller@280 { + status = "disabled"; + compatible = "amlogic,meson-axg-audio-arb"; + reg = <0x0 0x280 0x0 0x4>; + #reset-cells = <1>; + clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; + }; + + tdmin_a: audio-controller@300 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x300 0x0 0x40>; + sound-name-prefix = "TDMIN_A"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_b: audio-controller@340 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x340 0x0 0x40>; + sound-name-prefix = "TDMIN_B"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_c: audio-controller@380 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x380 0x0 0x40>; + sound-name-prefix = "TDMIN_C"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_lb: audio-controller@3c0 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x3c0 0x0 0x40>; + sound-name-prefix = "TDMIN_LB"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + spdifin: audio-controller@400 { + compatible = "amlogic,g12a-spdifin", + "amlogic,axg-spdifin"; + reg = <0x0 0x400 0x0 0x30>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFIN"; + interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, + <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; + clock-names = "pclk", "refclk"; + status = "disabled"; + }; + + spdifout: audio-controller@480 { + compatible = "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg = <0x0 0x480 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names = "pclk", "mclk"; + status = "disabled"; + }; + + tdmout_a: audio-controller@500 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x0 0x500 0x0 0x40>; + sound-name-prefix = "TDMOUT_A"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_b: audio-controller@540 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x0 0x540 0x0 0x40>; + sound-name-prefix = "TDMOUT_B"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_c: audio-controller@580 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x0 0x580 0x0 0x40>; + sound-name-prefix = "TDMOUT_C"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + spdifout_b: audio-controller@680 { + compatible = "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg = <0x0 0x680 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT_B"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, + <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; + clock-names = "pclk", "mclk"; + status = "disabled"; + }; + + tohdmitx: audio-controller@744 { + compatible = "amlogic,g12a-tohdmitx"; + reg = <0x0 0x744 0x0 0x4>; + #sound-dai-cells = <1>; + sound-name-prefix = "TOHDMITX"; + status = "disabled"; + }; + }; + usb3_pcie_phy: phy@46000 { compatible = "amlogic,g12a-usb3-pcie-phy"; reg = <0x0 0x46000 0x0 0x2000>; @@ -314,6 +1737,38 @@ assigned-clock-rates = <100000000>; #phy-cells = <1>; }; + + eth_phy: mdio-multiplexer@4c000 { + compatible = "amlogic,g12a-mdio-mux"; + reg = <0x0 0x4c000 0x0 0xa4>; + clocks = <&clkc CLKID_ETH_PHY>, + <&xtal>, + <&clkc CLKID_MPLL_50M>; + clock-names = "pclk", "clkin0", "clkin1"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + + ext_mdio: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + int_mdio: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + internal_ephy: ethernet_phy@8 { + compatible = "ethernet-phy-id0180.3301", + "ethernet-phy-ieee802.3-c22"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <8>; + max-speed = <100>; + }; + }; + }; }; aobus: bus@ff800000 { @@ -401,6 +1856,145 @@ gpio-ranges = <&ao_pinctrl 0 0 15>; }; + i2c_ao_sck_pins: i2c_ao_sck_pins { + mux { + groups = "i2c_ao_sck"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c_ao_sda_pins: i2c_ao_sda { + mux { + groups = "i2c_ao_sda"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c_ao_sck_e_pins: i2c_ao_sck_e { + mux { + groups = "i2c_ao_sck_e"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c_ao_sda_e_pins: i2c_ao_sda_e { + mux { + groups = "i2c_ao_sda_e"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk0_ao_pins: mclk0-ao { + mux { + groups = "mclk0_ao"; + function = "mclk0_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_din0_pins: tdm-ao-b-din0 { + mux { + groups = "tdm_ao_b_din0"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + spdif_ao_out_pins: spdif-ao-out { + mux { + groups = "spdif_ao_out"; + function = "spdif_ao_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + tdm_ao_b_din1_pins: tdm-ao-b-din1 { + mux { + groups = "tdm_ao_b_din1"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + tdm_ao_b_din2_pins: tdm-ao-b-din2 { + mux { + groups = "tdm_ao_b_din2"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { + mux { + groups = "tdm_ao_b_dout0"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { + mux { + groups = "tdm_ao_b_dout1"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { + mux { + groups = "tdm_ao_b_dout2"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_fs_pins: tdm-ao-b-fs { + mux { + groups = "tdm_ao_b_fs"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_sclk_pins: tdm-ao-b-sclk { + mux { + groups = "tdm_ao_b_sclk"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { + mux { + groups = "tdm_ao_b_slv_fs"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { + mux { + groups = "tdm_ao_b_slv_sclk"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + uart_ao_a_pins: uart-a-ao { mux { groups = "uart_ao_a_tx", @@ -418,6 +2012,69 @@ bias-disable; }; }; + + pwm_ao_a_pins: pwm-ao-a { + mux { + groups = "pwm_ao_a"; + function = "pwm_ao_a"; + bias-disable; + }; + }; + + pwm_ao_b_pins: pwm-ao-b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + bias-disable; + }; + }; + + pwm_ao_c_4_pins: pwm-ao-c-4 { + mux { + groups = "pwm_ao_c_4"; + function = "pwm_ao_c"; + bias-disable; + }; + }; + + pwm_ao_c_6_pins: pwm-ao-c-6 { + mux { + groups = "pwm_ao_c_6"; + function = "pwm_ao_c"; + bias-disable; + }; + }; + + pwm_ao_d_5_pins: pwm-ao-d-5 { + mux { + groups = "pwm_ao_d_5"; + function = "pwm_ao_d"; + bias-disable; + }; + }; + + pwm_ao_d_10_pins: pwm-ao-d-10 { + mux { + groups = "pwm_ao_d_10"; + function = "pwm_ao_d"; + bias-disable; + }; + }; + + pwm_ao_d_e_pins: pwm-ao-d-e { + mux { + groups = "pwm_ao_d_e"; + function = "pwm_ao_d"; + }; + }; + + remote_input_ao_pins: remote-input-ao { + mux { + groups = "remote_ao_input"; + function = "remote_ao_input"; + bias-disable; + }; + }; }; }; @@ -445,12 +2102,19 @@ status = "disabled"; }; + pwm_AO_cd: pwm@2000 { + compatible = "amlogic,meson-g12a-ao-pwm-cd"; + reg = <0x0 0x2000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart_AO: serial@3000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&xtal>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; @@ -460,11 +2124,35 @@ "amlogic,meson-ao-uart"; reg = <0x0 0x4000 0x0 0x18>; interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&xtal>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + i2c_AO: i2c@5000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x05000 0x0 0x20>; + interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + pwm_AO_ab: pwm@7000 { + compatible = "amlogic,meson-g12a-ao-pwm-ab"; + reg = <0x0 0x7000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@8000 { + compatible = "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8000 0x0 0x20>; + interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + saradc: adc@9000 { compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; @@ -533,6 +2221,76 @@ #reset-cells = <1>; }; + gpio_intc: interrupt-controller@f080 { + compatible = "amlogic,meson-g12a-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0xf080 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + }; + + pwm_ef: pwm@19000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x19000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@1a000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ab: pwm@1b000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2c3: i2c@1c000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1c000 0x0 0x20>; + interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + i2c2: i2c@1d000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1d000 0x0 0x20>; + interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + i2c1: i2c@1e000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1e000 0x0 0x20>; + interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + i2c0: i2c@1f000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1f000 0x0 0x20>; + interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + clk_msr: clock-measure@18000 { compatible = "amlogic,meson-g12a-clk-measure"; reg = <0x0 0x18000 0x0 0x10>; @@ -566,6 +2324,43 @@ }; }; + sd_emmc_a: sd@ffe03000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xffe03000 0x0 0x800>; + interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; + amlogic,dram-access-quirk; + }; + + sd_emmc_b: sd@ffe05000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xffe05000 0x0 0x800>; + interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; + }; + + sd_emmc_c: mmc@ffe07000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xffe07000 0x0 0x800>; + interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; + }; + usb: usb@ffe09000 { status = "disabled"; compatible = "amlogic,meson-g12a-usb-ctrl"; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts new file mode 100644 index 000000000000..81780ffcc7f0 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/dts-v1/; + +#include "meson-g12b.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/meson-g12a-gpio.h> +#include <dt-bindings/sound/meson-g12a-tohdmitx.h> + +/ { + compatible = "hardkernel,odroid-n2", "amlogic,g12b"; + model = "Hardkernel ODROID-N2"; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "n2:blue"; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + tflash_vdd: regulator-tflash_vdd { + compatible = "regulator-fixed"; + + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tf_io: gpio-regulator-tf_io { + compatible = "regulator-gpio"; + + regulator-name = "TF_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0 + 1800000 1>; + }; + + flash_1v8: regulator-flash_1v8 { + compatible = "regulator-fixed"; + regulator-name = "FLASH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + main_12v: regulator-main_12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&main_12v>; + }; + + vcc_1v8: regulator-vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + /* FIXME: actually controlled by VDDCPU_B_EN */ + }; + + hub_5v: regulator-hub_5v { + compatible = "regulator-fixed"; + regulator-name = "HUB_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to the Hub CHIPENABLE, LOW sets low power state */ + gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_pwr_en: regulator-usb_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to the microUSB port power enable */ + gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddao_1v8: regulator-vddao_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_12v>; + regulator-always-on; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "G12A-ODROIDN2"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&clkc_audio { + status = "okay"; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&gpio { + /* + * WARNING: The USB Hub on the Odroid-N2 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&vcc_5v>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&tf_io>; + +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_pwr_en>; +}; + +&usb2_phy0 { + phy-supply = <&vcc_5v>; +}; + +&usb2_phy1 { + /* Enable the hub which is connected to this port */ + phy-supply = <&hub_5v>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi new file mode 100644 index 000000000000..9e88e513b22d --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include "meson-g12a.dtsi" + +/ { + compatible = "amlogic,g12b"; + + cpus { + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu100>; + }; + + core1 { + cpu = <&cpu101>; + }; + + core2 { + cpu = <&cpu102>; + }; + + core3 { + cpu = <&cpu103>; + }; + }; + }; + + /delete-node/ cpu@2; + /delete-node/ cpu@3; + + cpu100: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu101: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu102: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x102>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu103: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x103>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; +}; + +&clkc { + compatible = "amlogic,g12b-clkc"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index 016641a41694..a9b778571cf5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -164,7 +164,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; non-removable; disable-wp; @@ -184,7 +184,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 6772709b9e19..74d03fc706be 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -486,7 +486,9 @@ }; ethmac: ethernet@c9410000 { - compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; + compatible = "amlogic,meson-gxbb-dwmac", + "snps,dwmac-3.70a", + "snps,dwmac"; reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index ade2ee09ae96..c34c1c90ccb6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -154,10 +154,6 @@ amlogic,tx-delay-ns = <2>; - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; @@ -166,6 +162,11 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_15 */ interrupts = <29 IRQ_TYPE_LEVEL_LOW>; @@ -273,7 +274,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <200000000>; + max-frequency = <50000000>; non-removable; disable-wp; @@ -301,8 +302,8 @@ sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; - sd-uhs-sdr104; - max-frequency = <200000000>; + sd-uhs-ddr50; + max-frequency = <100000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index 25105ac96d55..b636912a2715 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -162,10 +162,6 @@ phy-handle = <ð_phy0>; phy-mode = "rmii"; - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; @@ -174,6 +170,10 @@ eth_phy0: ethernet-phy@0 { /* IC Plus IP101GR (0x02430c54) */ reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; }; }; }; @@ -235,7 +235,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 1cc9dc68ef00..9972b1515da6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -126,10 +126,6 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - amlogic,tx-delay-ns = <2>; mdio { @@ -140,6 +136,11 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_15 */ interrupts = <29 IRQ_TYPE_LEVEL_LOW>; @@ -255,6 +256,10 @@ bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; max-frequency = <100000000>; disable-wp; @@ -272,7 +277,7 @@ pinctrl-names = "default", "clk-gate"; bus-width = <8>; - max-frequency = <100000000>; + max-frequency = <200000000>; non-removable; disable-wp; cap-mmc-highspeed; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts index 9d2406a7c4fa..3c93d1898b40 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts @@ -68,10 +68,6 @@ amlogic,tx-delay-ns = <2>; - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; @@ -80,6 +76,11 @@ eth_phy0: ethernet-phy@3 { /* Micrel KSZ9031 (0x00221620) */ reg = <3>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_15 */ interrupts = <29 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 0be0f2a5d2fe..e8f925871edf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -165,7 +165,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; non-removable; disable-wp; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index ad4d50bd9d77..43b11e3dfe11 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -28,10 +28,10 @@ }; }; - usb_vbus: regulator-usb0-vbus { + usb_pwr: regulator-usb-pwrs { compatible = "regulator-fixed"; - regulator-name = "USB0_VBUS"; + regulator-name = "USB_PWR"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -40,20 +40,34 @@ enable-active-high; }; - vcc_3v3: regulator-vcc_3v3 { + vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_1v8: regulator-vcc_1v8 { + vddio_ao18: regulator-vddio_ao18 { compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; + regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + emmc_pwrseq: emmc-pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; @@ -66,15 +80,32 @@ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>, - <&gpio GPIOX_20 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; clocks = <&wifi32k>; clock-names = "ext_clock"; }; }; +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + ðmac { status = "okay"; pinctrl-0 = <ð_rgmii_pins>; @@ -85,10 +116,6 @@ amlogic,tx-delay-ns = <2>; - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; @@ -97,10 +124,30 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_15 */ + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; }; }; }; +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>; @@ -115,10 +162,15 @@ clock-names = "clkin0"; }; +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + /* Wireless SDIO Module */ &sd_emmc_a { status = "okay"; - pinctrl-0 = <&sdio_pins &sdio_irq_pins>; + pinctrl-0 = <&sdio_pins>; pinctrl-1 = <&sdio_clk_gate_pins>; pinctrl-names = "default", "clk-gate"; #address-cells = <1>; @@ -126,15 +178,15 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; non-removable; disable-wp; mmc-pwrseq = <&sdio_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; brcmf: wifi@1 { reg = <1>; @@ -151,12 +203,13 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vcc_3v3>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vcc_3v3>; }; /* eMMC */ @@ -176,9 +229,22 @@ mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v3>; - vmmcq-sumpply = <&vcc_1v8>; + vqmmc-supply = <&vddio_boot>; +}; + +/* This is connected to the Bluetooth module: */ +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; + }; }; +/* This UART is brought out to the DB9 connector */ &uart_AO { status = "okay"; pinctrl-0 = <&uart_ao_a_pins>; @@ -187,7 +253,7 @@ &usb0_phy { status = "okay"; - phy-supply = <&usb_vbus>; + phy-supply = <&usb_pwr>; }; &usb1_phy { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index 2d2db783c44c..4c539881fbb7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -59,6 +59,13 @@ regulator-max-microvolt = <3300000>; }; + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vcc_3v3: regulator-vcc_3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; @@ -130,10 +137,6 @@ amlogic,tx-delay-ns = <2>; - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; @@ -142,6 +145,10 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; }; }; }; @@ -172,6 +179,11 @@ clock-names = "clkin0"; }; +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + /* Wireless SDIO Module */ &sd_emmc_a { status = "okay"; @@ -183,7 +195,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; non-removable; disable-wp; @@ -208,7 +220,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; @@ -237,6 +249,19 @@ vqmmc-supply = <&vddio_boot>; }; +/* This is connected to the Bluetooth module: */ +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; + }; +}; + /* This UART is brought out to the DB9 connector */ &uart_AO { status = "okay"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index a60d3652beee..f734faaf7b78 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -381,10 +381,15 @@ }; emmc_pins: emmc { - mux { + mux-0 { groups = "emmc_nand_d07", - "emmc_cmd", - "emmc_clk"; + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + }; + + mux-1 { + groups = "emmc_clk"; function = "emmc"; bias-disable; }; @@ -394,7 +399,7 @@ mux { groups = "emmc_ds"; function = "emmc"; - bias-disable; + bias-pull-down; }; }; @@ -436,13 +441,18 @@ }; sdcard_pins: sdcard { - mux { + mux-0 { groups = "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", - "sdcard_cmd", - "sdcard_clk"; + "sdcard_cmd"; + function = "sdcard"; + bias-pull-up; + }; + + mux-1 { + groups = "sdcard_clk"; function = "sdcard"; bias-disable; }; @@ -457,13 +467,18 @@ }; sdio_pins: sdio { - mux { + mux-0 { groups = "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", - "sdio_cmd", - "sdio_clk"; + "sdio_cmd"; + function = "sdio"; + bias-pull-up; + }; + + mux-1 { + groups = "sdio_clk"; function = "sdio"; bias-disable; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index 70433e023fda..3a1484e5b8e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -160,7 +160,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; non-removable; disable-wp; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index 0c8e8305b1f3..b08c4537f260 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -70,20 +70,21 @@ amlogic,tx-delay-ns = <2>; - /* External PHY reset is shared with internal PHY Led signals */ - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - /* External PHY is in RGMII */ phy-mode = "rgmii"; }; &external_mdio { external_phy: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; + /* Realtek RTL8211F (0x001cc916) */ reg = <0>; max-speed = <1000>; + + /* External PHY reset is shared with internal PHY Led signal */ + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; interrupts = <29 IRQ_TYPE_LEVEL_LOW>; eee-broken-1000t; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index 255cede7b447..4b8ce738e213 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -115,11 +115,13 @@ regulator-max-microvolt = <1800000>; }; + /* This is provided by LDOs on the eMMC daugther card */ vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; }; }; @@ -235,7 +237,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; @@ -253,9 +255,9 @@ bus-width = <8>; cap-mmc-highspeed; - mmc-ddr-3_3v; - max-frequency = <50000000>; - non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; disable-wp; mmc-pwrseq = <&emmc_pwrseq>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts index 9cbdb85fb591..26907ac82930 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts @@ -180,7 +180,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi index bc811a2faf42..e3c16f50814b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi @@ -114,7 +114,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; non-removable; disable-wp; @@ -134,7 +134,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 3093ae421b17..c959456bacc6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -326,10 +326,15 @@ }; emmc_pins: emmc { - mux { + mux-0 { groups = "emmc_nand_d07", - "emmc_cmd", - "emmc_clk"; + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + }; + + mux-1 { + groups = "emmc_clk"; function = "emmc"; bias-disable; }; @@ -339,7 +344,7 @@ mux { groups = "emmc_ds"; function = "emmc"; - bias-disable; + bias-pull-down; }; }; @@ -381,13 +386,18 @@ }; sdcard_pins: sdcard { - mux { + mux-0 { groups = "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", - "sdcard_cmd", - "sdcard_clk"; + "sdcard_cmd"; + function = "sdcard"; + bias-pull-up; + }; + + mux-1 { + groups = "sdcard_clk"; function = "sdcard"; bias-disable; }; @@ -402,13 +412,18 @@ }; sdio_pins: sdio { - mux { + mux-0 { groups = "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", - "sdio_cmd", - "sdio_clk"; + "sdio_cmd"; + function = "sdio"; + bias-pull-up; + }; + + mux-1 { + groups = "sdio_clk"; function = "sdio"; bias-disable; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 3f086ed7de05..989d33ac6eae 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -18,7 +18,6 @@ aliases { serial0 = &uart_AO; - serial1 = &uart_A; serial2 = &uart_AO_B; }; @@ -63,11 +62,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; - button@0 { + power-button { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; @@ -242,11 +239,6 @@ amlogic,tx-delay-ns = <2>; - /* External PHY reset is shared with internal PHY Led signals */ - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - /* External PHY is in RGMII */ phy-mode = "rgmii"; @@ -257,6 +249,11 @@ external_phy: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_15 */ interrupts = <25 IRQ_TYPE_LEVEL_LOW>; @@ -324,12 +321,13 @@ &sd_emmc_a { status = "okay"; pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; #address-cells = <1>; #size-cells = <0>; bus-width = <4>; - max-frequency = <100000000>; + max-frequency = <50000000>; non-removable; disable-wp; @@ -349,11 +347,12 @@ &sd_emmc_b { status = "okay"; pinctrl-0 = <&sdcard_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; @@ -366,17 +365,16 @@ &sd_emmc_c { status = "okay"; pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <8>; - cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <200000000>; non-removable; disable-wp; mmc-ddr-1_8v; mmc-hs200-1_8v; - mmc-hs400-1_8v; mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v3>; @@ -404,8 +402,14 @@ /* This one is connected to the Bluetooth module */ &uart_A { status = "okay"; - pinctrl-0 = <&uart_a_pins>; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; }; /* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts index 25f3b6b14043..c2bd4dbbf38c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts @@ -101,19 +101,19 @@ amlogic,tx-delay-ns = <2>; - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - /* External PHY is in RGMII */ phy-mode = "rgmii"; }; &external_mdio { external_phy: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; + /* Realtek RTL8211F (0x001cc916) */ reg = <0>; max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; }; }; @@ -144,7 +144,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts index 73d656e4aade..ea45ae0c71b7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts @@ -52,20 +52,21 @@ amlogic,tx-delay-ns = <2>; - /* External PHY reset is shared with internal PHY Led signals */ - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - /* External PHY is in RGMII */ phy-mode = "rgmii"; }; &external_mdio { external_phy: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; + /* Realtek RTL8211F (0x001cc916) */ reg = <0>; max-speed = <1000>; + + /* External PHY reset is shared with internal PHY Led signal */ + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_15 */ interrupts = <25 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts index 7fa20a8ede17..5cd4d35006d0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts @@ -101,10 +101,6 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; - amlogic,tx-delay-ns = <2>; /* External PHY is in RGMII */ @@ -113,9 +109,13 @@ &external_mdio { external_phy: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; + /* Realtek RTL8211F (0x001cc916) */ reg = <0>; max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; }; }; @@ -143,7 +143,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; non-removable; disable-wp; @@ -167,7 +167,7 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 7446e0dc154d..26a039a028b8 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -150,7 +150,7 @@ /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ main_funnel: funnel@20040000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x20040000 0 0x1000>; clocks = <&soc_smc50mhz>; @@ -281,7 +281,7 @@ }; funnel@220c0000 { /* cluster0 funnel */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x220c0000 0 0x1000>; clocks = <&soc_smc50mhz>; @@ -366,7 +366,7 @@ }; funnel@230c0000 { /* cluster1 funnel */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x230c0000 0 0x1000>; clocks = <&soc_smc50mhz>; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi index cf285152deab..eda3d9e18af6 100644 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 / { funnel@20130000 { /* cssys1 */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x20130000 0 0x1000>; clocks = <&soc_smc50mhz>; @@ -47,7 +47,7 @@ }; funnel@20150000 { /* cssys2 */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x20150000 0 0x1000>; clocks = <&soc_smc50mhz>; diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index 1792b074e9a3..9f60dacb4f80 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -106,7 +106,6 @@ flash@0,00000000 { /* 2 * 32MiB NOR Flash memory mounted on CS0 */ compatible = "arm,vexpress-flash", "cfi-flash"; - linux,part-probe = "afs"; reg = <0 0x00000000 0x04000000>; bank-width = <4>; /* @@ -116,6 +115,9 @@ * flash hardware access is disabled by default. */ status = "disabled"; + partitions { + compatible = "arm,arm-firmware-suite"; + }; }; ethernet@2,00000000 { diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi new file mode 100644 index 000000000000..55259f973b5a --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +/* + *Copyright(c) 2018 Broadcom + */ + usb { + compatible = "simple-bus"; + dma-ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x68500000 0x00400000>; + + usbphy0: usb-phy@0 { + compatible = "brcm,sr-usb-combo-phy"; + reg = <0x00000000 0x100>; + #phy-cells = <1>; + status = "disabled"; + }; + + xhci0: usb@1000 { + compatible = "generic-xhci"; + reg = <0x00001000 0x1000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy0 1>, <&usbphy0 0>; + phy-names = "phy0", "phy1"; + dma-coherent; + status = "disabled"; + }; + + bdc0: usb@2000 { + compatible = "brcm,bdc-v0.16"; + reg = <0x00002000 0x1000>; + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy0 0>, <&usbphy0 1>; + phy-names = "phy0", "phy1"; + dma-coherent; + status = "disabled"; + }; + + usbphy1: usb-phy@10000 { + compatible = "brcm,sr-usb-combo-phy"; + reg = <0x00010000 0x100>; + #phy-cells = <1>; + status = "disabled"; + }; + + usbphy2: usb-phy@20000 { + compatible = "brcm,sr-usb-hs-phy"; + reg = <0x00020000 0x100>; + #phy-cells = <0>; + status = "disabled"; + }; + + xhci1: usb@11000 { + compatible = "generic-xhci"; + reg = <0x00011000 0x1000>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy1 1>, <&usbphy2>, <&usbphy1 0>; + phy-names = "phy0", "phy1", "phy2"; + dma-coherent; + status = "disabled"; + }; + + bdc1: usb@21000 { + compatible = "brcm,bdc-v0.16"; + reg = <0x00021000 0x1000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy2>; + phy-names = "phy0"; + dma-coherent; + status = "disabled"; + }; + }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 35c4670c00d1..71e2e34400d4 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -287,6 +287,7 @@ #include "stingray-fs4.dtsi" #include "stingray-sata.dtsi" #include "stingray-pcie.dtsi" + #include "stingray-usb.dtsi" hsls { compatible = "simple-bus"; @@ -612,4 +613,111 @@ status = "disabled"; }; }; + + tmons { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x8f100000 0x100>; + + tmon: tmon@0 { + compatible = "brcm,sr-thermal"; + reg = <0x0 0x40>; + brcm,tmon-mask = <0x3f>; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + ihost0_thermal: ihost0-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 0>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost1_thermal: ihost1-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 1>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost2_thermal: ihost2-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 2>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost3_thermal: ihost3-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 3>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + crmu_thermal: crmu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 4>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + nitro_thermal: nitro-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 5>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + nic-hsls { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x7fffffff>; + + nic_i2c0: i2c@60826100 { + compatible = "brcm,iproc-nic-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60826100 0x100>, + <0x60e00408 0x1000>; + brcm,ape-hsls-addr-mask = <0x03400000>; + clock-frequency = <100000>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index d2de16645e10..6f90b0e62cba 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -350,6 +350,11 @@ pinctrl-0 = <&te_irq>; }; +&gpu { + mali-supply = <&buck6_reg>; + status = "okay"; +}; + &hdmi { hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index d29d13f4694f..a76f620f7f35 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -249,6 +249,57 @@ }; }; + gpu: gpu@14ac0000 { + compatible = "samsung,exynos5433-mali", "arm,mali-t760"; + reg = <0x14ac0000 0x5000>; + interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cmu_g3d CLK_ACLK_G3D>; + clock-names = "core"; + power-domains = <&pd_g3d>; + operating-points-v2 = <&gpu_opp_table>; + status = "disabled"; + + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <1000000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1000000>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <1025000>; + }; + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <1025000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1075000>; + }; + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-microvolt = <1125000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1150000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <1150000>; + }; + }; + }; + psci { compatible = "arm,psci"; method = "smc"; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 00dd89b92b42..080e0f56e108 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -59,6 +59,11 @@ clock-frequency = <24000000>; }; +&gpu { + mali-supply = <&buck6_reg>; + status = "okay"; +}; + &serial_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 077d23478901..bcb9d8cee267 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -78,6 +78,17 @@ }; }; + gpu: gpu@14ac0000 { + compatible = "samsung,exynos5433-mali", "arm,mali-t760"; + reg = <0x14ac0000 0x5000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu"; + status = "disabled"; + /* TODO: operating points for DVFS, cooling device */ + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0bd122f60549..c043aca66572 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index b359068d9605..de6ef39f3118 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -17,6 +17,7 @@ compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; aliases { + crypto = &crypto; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -47,6 +48,15 @@ regulator-always-on; }; + sb_3v3: regulator-sb3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -117,6 +127,12 @@ #size-cells = <0>; reg = <0x3>; + temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + }; + rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; @@ -153,3 +169,7 @@ &sai1 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index f9c272fb0738..9fb911317ecd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -16,6 +16,7 @@ compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; aliases { + crypto = &crypto; serial0 = &duart0; serial1 = &duart1; }; @@ -43,6 +44,15 @@ regulator-always-on; }; + sb_3v3: regulator-sb3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -115,6 +125,12 @@ #size-cells = <0>; reg = <0x3>; + temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + }; + rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; @@ -151,3 +167,7 @@ &sai4 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 22a1c74dddf3..7975519b4f56 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -70,6 +70,27 @@ clock-output-names = "sysclk"; }; + dpclk: clock-dp { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names= "dpclk"; + }; + + aclk: clock-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <650000000>; + clock-output-names= "aclk"; + }; + + pclk: clock-apb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <650000000>; + clock-output-names= "pclk"; + }; + reboot { compatible ="syscon-reboot"; regmap = <&dcfg>; @@ -285,13 +306,24 @@ #interrupt-cells = <2>; }; - wdog0: watchdog@23c0000 { - compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt"; - reg = <0x0 0x23c0000 0x0 0x10000>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 1>; - big-endian; - status = "disabled"; + usb0: usb@3100000 { + compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,dis_rxdet_inp3_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + }; + + usb1: usb@3110000 { + compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,dis_rxdet_inp3_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; sata: sata@3200000 { @@ -356,6 +388,79 @@ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; }; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qdma: dma-controller@8380000 { + compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8390000 0x0 0x10000>, /* Status regs */ + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "qdma-error", "qdma-queue0", + "qdma-queue1", "qdma-queue2", "qdma-queue3"; + dma-channels = <8>; + block-number = <1>; + block-offset = <0x10000>; + fsl,dma-queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + }; + + cluster1_core0_watchdog: watchdog@c000000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clock-names = "apb_pclk", "wdog_clk"; + }; + + cluster1_core1_watchdog: watchdog@c010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + clocks = <&clockgen 4 15>, <&clockgen 4 15>; + clock-names = "apb_pclk", "wdog_clk"; + }; + sai1: audio-controller@f100000 { #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; @@ -439,4 +544,21 @@ }; }; }; + + malidp0: display@f080000 { + compatible = "arm,mali-dp500"; + reg = <0x0 0xf080000 0x0 0x10000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "DE", "SE"; + clocks = <&dpclk>, <&aclk>, <&aclk>, <&pclk>; + clock-names = "pxlclk", "mclk", "aclk", "pclk"; + arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; + + port { + dp0_out: endpoint { + + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 2d5d89475b76..ee7f2b2fc1ff 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -37,6 +37,41 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + wm8524: audio-codec { + #sound-dai-cells = <0>; + compatible = "wlf,wm8524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_wlf>; + wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8524-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; + simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + simple-audio-card,routing = + "Left Line Out Jack", "LINEVOUTL", + "Right Line Out Jack", "LINEVOUTR"; + + cpudai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8524>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; }; &fec1 { @@ -61,6 +96,19 @@ }; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -95,6 +143,120 @@ status = "okay"; }; +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; @@ -124,12 +286,40 @@ >; }; + pinctrl_gpio_wlf: gpiowlfgrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { fsl,pins = < MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 6b407a94c06e..232a7412755a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -53,6 +53,8 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; A53_1: cpu@1 { @@ -100,14 +102,23 @@ opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <850000>; + opp-supported-hw = <0xe>, <0x7>; clock-latency-ns = <150000>; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; + opp-supported-hw = <0xc>, <0x7>; + clock-latency-ns = <150000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1000000>; + /* Consumer only but rely on speed grading */ + opp-supported-hw = <0x8>, <0x7>; clock-latency-ns = <150000>; - opp-suspend; }; }; @@ -158,15 +169,6 @@ clock-output-names = "clk_ext4"; }; - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ - <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - }; - psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -189,7 +191,23 @@ arm,no-tick-in-suspend; }; - soc { + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -199,13 +217,80 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x30000000 0x30000000 0x400000>; + + sai1: sai@30010000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30010000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + <&clk IMX8MM_CLK_SAI1_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai2: sai@30020000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30020000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, + <&clk IMX8MM_CLK_SAI2_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@30030000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30030000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + <&clk IMX8MM_CLK_SAI3_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai5: sai@30050000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30050000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, + <&clk IMX8MM_CLK_SAI5_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai6: sai@30060000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30060000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI6_IPG>, + <&clk IMX8MM_CLK_SAI6_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; gpio1: gpio@30200000 { compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -217,6 +302,7 @@ reg = <0x30210000 0x10000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -228,6 +314,7 @@ reg = <0x30220000 0x10000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -239,6 +326,7 @@ reg = <0x30230000 0x10000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -250,6 +338,7 @@ reg = <0x30240000 0x10000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -319,6 +408,10 @@ /* For nvmem subnodes */ #address-cells = <1>; #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; }; anatop: anatop@30360000 { @@ -336,6 +429,8 @@ offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "snvs-rtc"; }; snvs_pwrkey: snvs-powerkey { @@ -344,6 +439,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; linux,keycode = <KEY_POWER>; wakeup-source; + status = "disabled"; }; }; @@ -369,7 +465,7 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x30400000 0x30400000 0x400000>; pwm1: pwm@30660000 { compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; @@ -420,7 +516,7 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x30800000 0x30800000 0x400000>; ecspi1: spi@30820000 { compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; @@ -639,7 +735,7 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x32c00000 0x32c00000 0x400000>; usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; @@ -656,14 +752,6 @@ status = "disabled"; }; - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; - usbmisc1: usbmisc@32e40200 { compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; #index-cells = <1>; @@ -685,14 +773,6 @@ status = "disabled"; }; - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; - usbmisc2: usbmisc@32e50200 { compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; #index-cells = <1>; @@ -729,5 +809,14 @@ dma-names = "rx-tx"; status = "disabled"; }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x38800000 0x10000>, /* GIC Dist */ + <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index b2038be8bbd7..e3df9b8cd9ca 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -242,6 +242,10 @@ power-supply = <&sw1a_reg>; }; +&snvs_pwrkey { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts new file mode 100644 index 000000000000..5179e22f5126 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -0,0 +1,809 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 Purism SPC + */ + +/dts-v1/; + +#include "dt-bindings/input/input.h" +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/usb/pd.h" +#include "imx8mq.dtsi" + +/ { + model = "Purism Librem 5 devkit"; + compatible = "purism,librem5-devkit", "fsl,imx8mq"; + + backlight_dsi: backlight-dsi { + compatible = "pwm-backlight"; + /* 200 Hz for the PAM2841 */ + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + /* Default brightness level (index into the array defined by */ + /* the "brightness-levels" property) */ + default-brightness-level = <0>; + power-supply = <®_22v4_p>; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + btn1 { + label = "VOL_UP"; + gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = <KEY_VOLUMEUP>; + }; + + btn2 { + label = "VOL_DOWN"; + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = <KEY_VOLUMEDOWN>; + }; + + hp-det { + label = "HP_DET"; + gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = <KEY_HP>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "LED 1"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pmic_osc: clock-pmic { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic_osc"; + }; + + reg_1v8_p: regulator-1v8-p { + compatible = "regulator-fixed"; + regulator-name = "1v8_p"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_pwr_en>; + }; + + reg_2v8_p: regulator-2v8-p { + compatible = "regulator-fixed"; + regulator-name = "2v8_p"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_pwr_en>; + }; + + reg_3v3_p: regulator-3v3-p { + compatible = "regulator-fixed"; + regulator-name = "3v3_p"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_pwr_en>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + reg_5v_p: regulator-5v-p { + compatible = "regulator-fixed"; + regulator-name = "5v_p"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_pwr_en>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + reg_22v4_p: regulator-22v4-p { + compatible = "regulator-fixed"; + regulator-name = "22v4_P"; + regulator-min-microvolt = <22400000>; + regulator-max-microvolt = <22400000>; + vin-supply = <®_pwr_en>; + }; + + reg_pwr_en: regulator-pwr-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwr_en>; + regulator-name = "PWR_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + vibrator { + compatible = "gpio-vibrator"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_haptic>; + enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + vcc-supply = <®_3v3_p>; + }; + + wifi_pwr_en: regulator-wifi-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + regulator-name = "WIFI_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&clk { + assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; + assigned-clock-rates = <786432000>, <722534400>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + phy-supply = <®_3v3_p>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@4b { + compatible = "rohm,bd71837"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + clocks = <&pmic_osc>; + clock-names = "osc"; + clock-output-names = "pmic_clk"; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + interrupt-names = "irq"; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <900000>; + rohm,dvs-idle-voltage = <850000>; + rohm,dvs-suspend-voltage = <800000>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + rohm,dvs-run-voltage = <1000000>; + }; + + buck4_reg: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + rohm,dvs-run-voltage = <1000000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + /* leave on for snvs power button */ + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + /* leave on for snvs power button */ + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + typec_ptn5100: usb_typec@52 { + compatible = "nxp,ptn5110"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 2000, + PDO_FIXED_USB_COMM | + PDO_FIXED_DUAL_ROLE | + PDO_FIXED_DATA_SWAP )>; + sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM | + PDO_FIXED_DUAL_ROLE | + PDO_FIXED_DATA_SWAP ) + PDO_VAR(5000, 3000, 3000)>; + op-sink-microwatt = <10000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usb_con_ss: endpoint { + remote-endpoint = <&typec_ss>; + }; + }; + }; + }; + }; + + rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + }; + + charger@6b { /* bq25896 */ + compatible = "ti,bq25890"; + reg = <0x6b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger>; + interrupt-parent = <&gpio3>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + ti,battery-regulation-voltage = <4192000>; /* 4.192V */ + ti,charge-current = <1600000>; /* 1.6A */ + ti,termination-current = <66000>; /* 66mA */ + ti,precharge-current = <130000>; /* 130mA */ + ti,minimum-sys-voltage = <3000000>; /* 3V */ + ti,boost-voltage = <5000000>; /* 5V */ + ti,boost-max-current = <50000>; /* 50mA */ + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + magnetometer@1e { + compatible = "st,lsm9ds1-magn"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <®_3v3_p>; + vddio-supply = <®_3v3_p>; + }; + + touchscreen@5d { + compatible = "goodix,gt5688"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + interrupt-parent = <&gpio3>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1440>; + AVDD28-supply = <®_2v8_p>; + VDDIO-supply = <®_1v8_p>; + }; +}; + +&iomuxc { + pinctrl_bl: blgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ + >; + }; + + pinctrl_bt: btgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ + MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ + >; + }; + + pinctrl_charger: chargergrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f + >; + }; + + pinctrl_ts: tsgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 + >; + }; + + pinctrl_gpio_keys: gpiokeygrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 + MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */ + >; + }; + + pinctrl_haptic: hapticgrp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f + >; + }; + + pinctrl_imu: imugrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ + >; + }; + + pinctrl_pwr_en: pwrengrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 + MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_pwr: usdhc2grppwr { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 + >; + }; + + pinctrl_wwan: wwangrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ + MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ + >; + }; +}; + +&pgc_gpu { + power-supply = <&buck3_reg>; +}; + +&pgc_vpu { + power-supply = <&buck4_reg>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bl>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { /* GNSS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; + uart-has-rtscts; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_5v_p>; + status = "okay"; +}; + +&usb_dwc3_0 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "otg"; + status = "okay"; + + port@0 { + reg = <0>; + + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_ss: endpoint { + remote-endpoint = <&usb_con_ss>; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + power-supply = <&wifi_pwr_en>; + non-removable; + disable-wp; + cap-sdio-irq; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 6d635ba0904c..d09b808eff87 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/power/imx8mq-power.h> #include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/gpio/gpio.h> +#include "dt-bindings/input/input.h" #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> #include "imx8mq-pinfunc.h" @@ -19,6 +20,11 @@ #size-cells = <2>; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; @@ -95,6 +101,8 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; A53_1: cpu@1 { @@ -145,14 +153,32 @@ opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <900000>; + /* Industrial only */ + opp-supported-hw = <0xf>, <0x4>; + clock-latency-ns = <150000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <900000>; + /* Consumer only */ + opp-supported-hw = <0xe>, <0x3>; clock-latency-ns = <150000>; }; opp-1300000000 { opp-hz = /bits/ 64 <1300000000>; opp-microvolt = <1000000>; + opp-supported-hw = <0xc>, <0x7>; + clock-latency-ns = <150000>; + }; + + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1000000>; + /* Consumer only but rely on speed grading */ + opp-supported-hw = <0x8>, <0x7>; clock-latency-ns = <150000>; - opp-suspend; }; }; @@ -415,6 +441,10 @@ clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; #address-cells = <1>; #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; }; anatop: syscon@30360000 { @@ -433,8 +463,18 @@ offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; + clock-names = "snvs-rtc"; }; + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + status = "disabled"; + }; }; clk: clock-controller@30380000 { @@ -815,6 +855,25 @@ }; }; + bus@32c00000 { /* AIPS4 */ + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x32c00000 0x32c00000 0x400000>; + + irqsteer: interrupt-controller@32e2d000 { + compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; + reg = <0x32e2d000 0x1000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <64>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + gpu: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x40000>; @@ -903,7 +962,6 @@ status = "disabled"; }; - pcie0: pcie@33800000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33800000 0x400000>, diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 0683ee2a48ae..05fa0b7f36bb 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -17,11 +17,19 @@ #size-cells = <2>; aliases { + gpio0 = &lsio_gpio0; + gpio1 = &lsio_gpio1; + gpio2 = &lsio_gpio2; + gpio3 = &lsio_gpio3; + gpio4 = &lsio_gpio4; + gpio5 = &lsio_gpio5; + gpio6 = &lsio_gpio6; + gpio7 = &lsio_gpio7; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; - serial0 = &adma_lpuart0; mu1 = &lsio_mu1; + serial0 = &adma_lpuart0; }; cpus { @@ -141,6 +149,12 @@ compatible = "fsl,imx8qxp-iomuxc"; }; + ocotp: imx8qx-ocotp { + compatible = "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + }; + pd: imx8qx-pd { compatible = "fsl,imx8qxp-scu-pd"; #power-domain-cells = <1>; @@ -149,6 +163,11 @@ rtc: rtc { compatible = "fsl,imx8qxp-sc-rtc"; }; + + watchdog { + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; }; timer { @@ -378,56 +397,25 @@ }; }; - lsio_subsys: bus@5d000000 { + ddr_subsyss: bus@5c000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; - - lsio_lpcg: clock-controller@5d400000 { - compatible = "fsl,imx8qxp-lpcg-lsio"; - reg = <0x5d400000 0x400000>; - #clock-cells = <1>; - }; + ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; - lsio_mu0: mailbox@5d1b0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1b0000 0x10000>; - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu1: mailbox@5d1c0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1c0000 0x10000>; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - }; - - lsio_mu2: mailbox@5d1d0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1d0000 0x10000>; - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu3: mailbox@5d1e0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1e0000 0x10000>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - status = "disabled"; + ddr-pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x5c020000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; }; + }; - lsio_mu4: mailbox@5d1f0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1f0000 0x10000>; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - status = "disabled"; - }; + lsio_subsys: bus@5d000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; lsio_gpio0: gpio@5d080000 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; @@ -516,10 +504,58 @@ #interrupt-cells = <2>; power-domains = <&pd IMX_SC_R_GPIO_7>; }; - }; - watchdog { - compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; - timeout-sec = <60>; + lsio_mu0: mailbox@5d1b0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1b0000 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu1: mailbox@5d1c0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1c0000 0x10000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + lsio_mu2: mailbox@5d1d0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1d0000 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu3: mailbox@5d1e0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1e0000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu4: mailbox@5d1f0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1f0000 0x10000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lsio_mu13: mailbox@5d280000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d280000 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_13A>; + }; + + lsio_lpcg: clock-controller@5d400000 { + compatible = "fsl,imx8qxp-lpcg-lsio"; + reg = <0x5d400000 0x400000>; + #clock-cells = <1>; + }; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi new file mode 100644 index 000000000000..d607f2f6698c --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * dtsi for Hisilicon Hi3660 Coresight + * + * Copyright (C) 2016-2018 Hisilicon Ltd. + * + * Author: Wanglai Shi <shiwanglai@hisilicon.com> + * + */ +/ { + soc { + /* A53 cluster internals */ + etm@ecc40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xecc40000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in0>; + }; + }; + }; + }; + + etm@ecd40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xecd40000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in1>; + }; + }; + }; + }; + + etm@ece40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xece40000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in2>; + }; + }; + }; + }; + + etm@ecf40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xecf40000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in3>; + }; + }; + }; + }; + + funnel@ec801000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xec801000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + cluster0_funnel_out: endpoint { + remote-endpoint = + <&cluster0_etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + cluster0_funnel_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + cluster0_funnel_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + cluster0_funnel_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + cluster0_funnel_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + }; + + etf@ec802000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xec802000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + cluster0_etf_in: endpoint { + remote-endpoint = + <&cluster0_funnel_out>; + }; + }; + }; + + out-ports { + port { + cluster0_etf_out: endpoint { + remote-endpoint = + <&combo_funnel_in0>; + }; + }; + }; + }; + + /* A73 cluster internals */ + etm@ed440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xed440000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in0>; + }; + }; + }; + }; + + etm@ed540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xed540000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in1>; + }; + }; + }; + }; + + etm@ed640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xed640000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in2>; + }; + }; + }; + }; + + etm@ed740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xed740000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in3>; + }; + }; + }; + }; + + funnel@ed001000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xed001000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + out-ports { + port { + cluster1_funnel_out: endpoint { + remote-endpoint = + <&cluster1_etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + cluster1_funnel_in0: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@1 { + reg = <1>; + cluster1_funnel_in1: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@2 { + reg = <2>; + cluster1_funnel_in2: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@3 { + reg = <3>; + cluster1_funnel_in3: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + etf@ed002000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xed002000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + cluster1_etf_in: endpoint { + remote-endpoint = + <&cluster1_funnel_out>; + }; + }; + }; + + out-ports { + port { + cluster1_etf_out: endpoint { + remote-endpoint = + <&combo_funnel_in1>; + }; + }; + }; + }; + + /* An invisible combo funnel between clusters and top funnel */ + funnel { + compatible = "arm,coresight-static-funnel"; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + combo_funnel_out: endpoint { + remote-endpoint = + <&top_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + combo_funnel_in0: endpoint { + remote-endpoint = + <&cluster0_etf_out>; + }; + }; + + port@1 { + reg = <1>; + combo_funnel_in1: endpoint { + remote-endpoint = + <&cluster1_etf_out>; + }; + }; + }; + }; + + /* Top internals */ + funnel@ec031000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0xec031000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + top_funnel_out: endpoint { + remote-endpoint = + <&top_etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + top_funnel_in: endpoint { + remote-endpoint = + <&combo_funnel_out>; + }; + }; + }; + }; + + etf@ec036000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xec036000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + top_etf_in: endpoint { + remote-endpoint = + <&top_funnel_out>; + }; + }; + }; + + out-ports { + port { + top_etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = + <&top_etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator0_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + + port@1 { + reg = <1>; + replicator0_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + }; + + etr@ec033000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xec033000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator0_out0>; + }; + }; + }; + }; + + tpiu@ec032000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xec032000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = + <&replicator0_out1>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index aa6a8ad31be2..253cc345f143 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1154,3 +1154,5 @@ }; }; }; + +#include "hi3660-coresight.dtsi" diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 30f54b77c2f1..651771a73ed6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -11,7 +11,7 @@ / { soc { funnel@f6401000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0xf6401000 0 0x1000>; clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; clock-names = "apb_pclk"; @@ -61,7 +61,7 @@ }; replicator { - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; clock-names = "apb_pclk"; @@ -129,7 +129,7 @@ }; funnel@f6501000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0xf6501000 0 0x1000>; clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; clock-names = "apb_pclk"; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 6be019e1888e..fbcf03f86c96 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -95,25 +95,9 @@ flash@0 { reg = <0>; - compatible = "winbond,w25q32dw", "jedec,spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <104000000>; m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0 0x180000>; - }; - - partition@180000 { - label = "ubootenv"; - reg = <0x180000 0x10000>; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index d20d84ce7ca8..f34ee87a0f56 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -28,6 +28,32 @@ ethernet2 = &cp0_eth2; }; + cp0_exp_usb3_0_current_regulator: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "cp0-usb3-0-current-regulator"; + regulator-type = "current"; + regulator-min-microamp = <500000>; + regulator-max-microamp = <900000>; + gpios = <&expander0 4 GPIO_ACTIVE_HIGH>; + states = <500000 0x0 + 900000 0x1>; + enable-active-high; + gpios-states = <0>; + }; + + cp0_exp_usb3_1_current_regulator: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "cp0-usb3-1-current-regulator"; + regulator-type = "current"; + regulator-min-microamp = <500000>; + regulator-max-microamp = <900000>; + gpios = <&expander0 5 GPIO_ACTIVE_HIGH>; + states = <500000 0x0 + 900000 0x1>; + enable-active-high; + gpios-states = <0>; + }; + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { compatible = "regulator-fixed"; regulator-name = "usb3h0-vbus"; @@ -35,6 +61,7 @@ regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + vin-supply = <&cp0_exp_usb3_0_current_regulator>; }; cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { @@ -44,6 +71,7 @@ regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + vin-supply = <&cp0_exp_usb3_1_current_regulator>; }; cp0_usb3_0_phy: cp0-usb3-0-phy { diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 9143aa13ceb1..f275d9420d5b 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -63,6 +63,7 @@ tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>; + maximum-power-milliwatt = <2000>; }; leds { diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 9f4f939ab65f..d6e9c014c2f9 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -27,6 +27,8 @@ ethernet1 = &cp0_eth2; ethernet2 = &cp1_eth0; ethernet3 = &cp1_eth1; + i2c1 = &cp0_i2c0; + i2c2 = &cp1_i2c0; }; cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { @@ -72,11 +74,6 @@ }; }; -&i2c0 { - status = "okay"; - clock-frequency = <100000>; -}; - &spi0 { status = "okay"; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index 329f8ceeebea..205071b45a32 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -184,6 +184,8 @@ num-lanes = <4>; num-viewport = <8>; reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; + ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000 + 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 861fd21922c4..9024a2d9db07 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -20,12 +20,14 @@ compatible = "arm,cortex-a72"; reg = <0x000>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x001>; enable-method = "psci"; + #cooling-cells = <2>; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index 2baafe12ebd4..ea13ae78f50d 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -20,24 +20,29 @@ compatible = "arm,cortex-a72"; reg = <0x000>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x001>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x100>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x101>; enable-method = "psci"; + #cooling-cells = <2>; }; }; + }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 91dad7e4ee59..96228f93b272 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -297,8 +297,6 @@ * * Only one thermal zone per AP/CP may trigger interrupts at a time, the * first one that will have a critical trip point will be chosen. - * - * The cooling maps are always empty as there are no cooling devices. */ thermal-zones { ap_thermal_ic: ap-thermal-ic { @@ -318,44 +316,136 @@ cooling-maps { }; }; - ap_thermal_cpu1: ap-thermal-cpu1 { + ap_thermal_cpu0: ap-thermal-cpu0 { polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&ap_thermal 1>; - trips { }; - cooling-maps { }; + trips { + cpu0_hot: cpu0-hot { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_emerg: cpu0-emerg { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map0_hot: map0-hot { + trip = <&cpu0_hot>; + cooling-device = <&cpu0 1 2>, + <&cpu1 1 2>; + }; + map0_emerg: map0-ermerg { + trip = <&cpu0_emerg>; + cooling-device = <&cpu0 3 3>, + <&cpu1 3 3>; + }; + }; }; - ap_thermal_cpu2: ap-thermal-cpu2 { + ap_thermal_cpu1: ap-thermal-cpu1 { polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&ap_thermal 2>; - trips { }; - cooling-maps { }; + trips { + cpu1_hot: cpu1-hot { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_emerg: cpu1-emerg { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map1_hot: map1-hot { + trip = <&cpu1_hot>; + cooling-device = <&cpu0 1 2>, + <&cpu1 1 2>; + }; + map1_emerg: map1-emerg { + trip = <&cpu1_emerg>; + cooling-device = <&cpu0 3 3>, + <&cpu1 3 3>; + }; + }; }; - ap_thermal_cpu3: ap-thermal-cpu3 { + ap_thermal_cpu2: ap-thermal-cpu2 { polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&ap_thermal 3>; - trips { }; - cooling-maps { }; + trips { + cpu2_hot: cpu2-hot { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_emerg: cpu2-emerg { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map2_hot: map2-hot { + trip = <&cpu2_hot>; + cooling-device = <&cpu2 1 2>, + <&cpu3 1 2>; + }; + map2_emerg: map2-emerg { + trip = <&cpu2_emerg>; + cooling-device = <&cpu2 3 3>, + <&cpu3 3 3>; + }; + }; }; - ap_thermal_cpu4: ap-thermal-cpu4 { + ap_thermal_cpu3: ap-thermal-cpu3 { polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&ap_thermal 4>; - trips { }; - cooling-maps { }; + trips { + cpu3_hot: cpu3-hot { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu3_emerg: cpu3-emerg { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map3_hot: map3-bhot { + trip = <&cpu3_hot>; + cooling-device = <&cpu2 1 2>, + <&cpu3 1 2>; + }; + map3_emerg: map3-emerg { + trip = <&cpu3_emerg>; + cooling-device = <&cpu2 3 3>, + <&cpu3 3 3>; + }; + }; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index 4d6e4a097f72..f71afb1de18f 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -238,6 +238,7 @@ <85 IRQ_TYPE_LEVEL_HIGH>, <84 IRQ_TYPE_LEVEL_HIGH>, <83 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; status = "disabled"; }; @@ -253,6 +254,7 @@ <81 IRQ_TYPE_LEVEL_HIGH>, <80 IRQ_TYPE_LEVEL_HIGH>, <79 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index e8f952fb279b..458bbc422a94 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts new file mode 100644 index 000000000000..d8e555cbb5d3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Ben Ho <ben.ho@mediatek.com> + * Erin Lo <erin.lo@mediatek.com> + */ + +/dts-v1/; +#include "mt8183.dtsi" + +/ { + model = "MediaTek MT8183 evaluation board"; + compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&auxadc { + status = "okay"; +}; + +&pio { + spi_pins_0: spi0{ + pins_spi{ + pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, + <PINMUX_GPIO86__FUNC_SPI0_CSB>, + <PINMUX_GPIO87__FUNC_SPI0_MO>, + <PINMUX_GPIO88__FUNC_SPI0_CLK>; + bias-disable; + }; + }; + + spi_pins_1: spi1{ + pins_spi{ + pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, + <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, + <PINMUX_GPIO163__FUNC_SPI1_A_MO>, + <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; + bias-disable; + }; + }; + + spi_pins_2: spi2{ + pins_spi{ + pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, + <PINMUX_GPIO1__FUNC_SPI2_MO>, + <PINMUX_GPIO2__FUNC_SPI2_CLK>, + <PINMUX_GPIO94__FUNC_SPI2_MI>; + bias-disable; + }; + }; + + spi_pins_3: spi3{ + pins_spi{ + pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, + <PINMUX_GPIO22__FUNC_SPI3_CSB>, + <PINMUX_GPIO23__FUNC_SPI3_MO>, + <PINMUX_GPIO24__FUNC_SPI3_CLK>; + bias-disable; + }; + }; + + spi_pins_4: spi4{ + pins_spi{ + pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, + <PINMUX_GPIO18__FUNC_SPI4_CSB>, + <PINMUX_GPIO19__FUNC_SPI4_MO>, + <PINMUX_GPIO20__FUNC_SPI4_CLK>; + bias-disable; + }; + }; + + spi_pins_5: spi5{ + pins_spi{ + pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, + <PINMUX_GPIO14__FUNC_SPI5_CSB>, + <PINMUX_GPIO15__FUNC_SPI5_MO>, + <PINMUX_GPIO16__FUNC_SPI5_CLK>; + bias-disable; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_0>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_1>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_2>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi3 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_3>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_4>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi5 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_5>; + mediatek,pad-select = <0>; + status = "okay"; + +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi new file mode 100644 index 000000000000..c2749c4631bc --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Ben Ho <ben.ho@mediatek.com> + * Erin Lo <erin.lo@mediatek.com> + */ + +#include <dt-bindings/clock/mt8183-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "mt8183-pinfunc.h" + +/ { + compatible = "mediatek,mt8183"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x002>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x003>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + }; + + pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; + }; + + pmu-a73 { + compatible = "arm,cortex-a73-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + soc_data: soc_data@8000000 { + compatible = "mediatek,mt8183-efuse", + "mediatek,efuse"; + reg = <0 0x08000000 0 0x0010>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c100000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + mcucfg: syscon@c530000 { + compatible = "mediatek,mt8183-mcucfg", "syscon"; + reg = <0 0x0c530000 0 0x1000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@c530a80 { + compatible = "mediatek,mt8183-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c530a80 0 0x50>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8183-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8183-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8183-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11e80000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11e90000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg1", "iocfg2", + "iocfg3", "iocfg4", "iocfg5", + "iocfg6", "iocfg7", "iocfg8", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 192>; + interrupt-controller; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8183-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8183-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, + <&infracfg CLK_INFRA_PMIC_AP>; + clock-names = "spi", "wrap"; + }; + + auxadc: auxadc@11001000 { + compatible = "mediatek,mt8183-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8183-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8183-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8183-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x1000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + audiosys: syscon@11220000 { + compatible = "mediatek,mt8183-audiosys", "syscon"; + reg = <0 0x11220000 0 0x1000>; + #clock-cells = <1>; + }; + + efuse: efuse@11f10000 { + compatible = "mediatek,mt8183-efuse", + "mediatek,efuse"; + reg = <0 0x11f10000 0 0x1000>; + }; + + mfgcfg: syscon@13000000 { + compatible = "mediatek,mt8183-mfgcfg", "syscon"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8183-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: syscon@15020000 { + compatible = "mediatek,mt8183-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8183-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt8183-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + ipu_conn: syscon@19000000 { + compatible = "mediatek,mt8183-ipu_conn", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; + }; + + ipu_adl: syscon@19010000 { + compatible = "mediatek,mt8183-ipu_adl", "syscon"; + reg = <0 0x19010000 0 0x1000>; + #clock-cells = <1>; + }; + + ipu_core0: syscon@19180000 { + compatible = "mediatek,mt8183-ipu_core0", "syscon"; + reg = <0 0x19180000 0 0x1000>; + #clock-cells = <1>; + }; + + ipu_core1: syscon@19280000 { + compatible = "mediatek,mt8183-ipu_core1", "syscon"; + reg = <0 0x19280000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: syscon@1a000000 { + compatible = "mediatek,mt8183-camsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 14d7fea82daf..bdace01561ba 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -7,18 +7,70 @@ #include "tegra186-p3310.dtsi" / { - model = "NVIDIA Tegra186 P2771-0000 Development Board"; + model = "NVIDIA Jetson TX2 Developer Kit"; compatible = "nvidia,p2771-0000", "nvidia,tegra186"; + aconnect { + status = "okay"; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + i2c@3160000 { power-monitor@42 { compatible = "ti,ina3221"; reg = <0x42>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0x0>; + label = "VDD_MUX"; + shunt-resistor-micro-ohms = <20000>; + }; + + channel@1 { + reg = <0x1>; + label = "VDD_5V0_IO_SYS"; + shunt-resistor-micro-ohms = <5000>; + }; + + channel@2 { + reg = <0x2>; + label = "VDD_3V3_SYS"; + shunt-resistor-micro-ohms = <10000>; + }; }; power-monitor@43 { compatible = "ti,ina3221"; reg = <0x43>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0x0>; + label = "VDD_3V3_IO_SLP"; + shunt-resistor-micro-ohms = <10000>; + }; + + channel@1 { + reg = <0x1>; + label = "VDD_1V8_IO"; + shunt-resistor-micro-ohms = <10000>; + }; + + channel@2 { + reg = <0x2>; + label = "VDD_M2_IN"; + shunt-resistor-micro-ohms = <10000>; + }; }; exp1: gpio@74 { @@ -31,6 +83,8 @@ #gpio-cells = <2>; gpio-controller; + + vcc-supply = <&vdd_3v3_sys>; }; exp2: gpio@77 { @@ -43,6 +97,8 @@ #gpio-cells = <2>; gpio-controller; + + vcc-supply = <&vdd_1v8>; }; }; @@ -145,6 +201,19 @@ phy-names = "usb2-0", "usb2-1", "usb3-0"; }; + i2c@c250000 { + /* carrier board ID EEPROM */ + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + + address-bits = <8>; + page-size = <8>; + size = <256>; + read-only; + }; + }; + pcie@10003000 { status = "okay"; @@ -278,7 +347,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_5v0_sys>; @@ -292,7 +361,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_5v0_sys>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 64686b033c38..5e18acf5cfad 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -4,7 +4,7 @@ #include <dt-bindings/mfd/max77620.h> / { - model = "NVIDIA Tegra186 P3310 Processor Module"; + model = "NVIDIA Jetson TX2"; compatible = "nvidia,p3310", "nvidia,tegra186"; aliases { @@ -67,11 +67,51 @@ power-monitor@40 { compatible = "ti,ina3221"; reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0x0>; + label = "VDD_SYS_GPU"; + shunt-resistor-micro-ohms = <10000>; + }; + + channel@1 { + reg = <0x1>; + label = "VDD_SYS_SOC"; + shunt-resistor-micro-ohms = <10000>; + }; + + channel@2 { + reg = <0x2>; + label = "VDD_3V8_WIFI"; + shunt-resistor-micro-ohms = <10000>; + }; }; power-monitor@41 { compatible = "ti,ina3221"; reg = <0x41>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0x0>; + label = "VDD_IN"; + shunt-resistor-micro-ohms = <5000>; + }; + + channel@1 { + reg = <0x1>; + label = "VDD_SYS_CPU"; + shunt-resistor-micro-ohms = <10000>; + }; + + channel@2 { + reg = <0x2>; + label = "VDD_5V0_DDR"; + shunt-resistor-micro-ohms = <10000>; + }; }; }; @@ -124,6 +164,17 @@ i2c@c250000 { status = "okay"; + + /* module ID EEPROM */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + address-bits = <8>; + page-size = <8>; + size = <256>; + read-only; + }; }; rtc@c2a0000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 426ac0bdf6a6..47cd831fcf44 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -70,6 +70,75 @@ snps,rxpbl = <8>; }; + aconnect { + compatible = "nvidia,tegra186-aconnect", + "nvidia,tegra210-aconnect"; + clocks = <&bpmp TEGRA186_CLK_APE>, + <&bpmp TEGRA186_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900000 0x0 0x02900000 0x200000>; + status = "disabled"; + + dma-controller@2930000 { + compatible = "nvidia,tegra186-adma"; + reg = <0x02930000 0x20000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&bpmp TEGRA186_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: interrupt-controller@2a40000 { + compatible = "nvidia,tegra186-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x02a41000 0x1000>, + <0x02a42000 0x2000>; + interrupts = <GIC_SPI 145 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&bpmp TEGRA186_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; + }; + memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; reg = <0x0 0x02c00000 0x0 0xb0000>; @@ -173,6 +242,9 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C4>; reset-names = "i2c"; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&state_dpaux1_i2c>; + pinctrl-1 = <&state_dpaux1_off>; status = "disabled"; }; @@ -201,6 +273,9 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C6>; reset-names = "i2c"; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&state_dpaux_i2c>; + pinctrl-1 = <&state_dpaux_off>; status = "disabled"; }; @@ -1121,6 +1196,30 @@ }; }; + bpmp: bpmp { + compatible = "nvidia,tegra186-bpmp"; + iommus = <&smmu TEGRA186_SID_BPMP>; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + bpmp_i2c: i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + bpmp_thermal: thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -1128,61 +1227,97 @@ cpu@0 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; + i-cache-size = <0x20000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_DENVER>; reg = <0x000>; }; cpu@1 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; + i-cache-size = <0x20000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_DENVER>; reg = <0x001>; }; cpu@2 { compatible = "arm,cortex-a57"; device_type = "cpu"; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_A57>; reg = <0x100>; }; cpu@3 { compatible = "arm,cortex-a57"; device_type = "cpu"; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_A57>; reg = <0x101>; }; cpu@4 { compatible = "arm,cortex-a57"; device_type = "cpu"; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_A57>; reg = <0x102>; }; cpu@5 { compatible = "arm,cortex-a57"; device_type = "cpu"; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_A57>; reg = <0x103>; }; - }; - bpmp: bpmp { - compatible = "nvidia,tegra186-bpmp"; - iommus = <&smmu TEGRA186_SID_BPMP>; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - bpmp_i2c: i2c { - compatible = "nvidia,tegra186-bpmp-i2c"; - nvidia,bpmp-bus-id = <5>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + L2_DENVER: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; }; - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; + L2_A57: l2-cache1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; }; }; @@ -1294,5 +1429,6 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&gic>; + always-on; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 0fd5bd29fbf9..62e07e1197cc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -4,7 +4,7 @@ #include <dt-bindings/mfd/max77620.h> / { - model = "NVIDIA Tegra194 P2888 Processor Module"; + model = "NVIDIA Jetson AGX Xavier"; compatible = "nvidia,p2888", "nvidia,tegra194"; aliases { @@ -191,7 +191,7 @@ regulator-boot-on; }; - sd3 { + vdd_1v8ao: sd3 { regulator-name = "VDD_1V8AO"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 73801b48d1d8..23597d53c9c9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -7,10 +7,22 @@ #include "tegra194-p2888.dtsi" / { - model = "NVIDIA Jetson AGX Xavier Development Kit"; + model = "NVIDIA Jetson AGX Xavier Developer Kit"; compatible = "nvidia,p2972-0000", "nvidia,tegra194"; cbb { + aconnect { + status = "okay"; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + ddc: i2c@31c0000 { status = "okay"; }; @@ -52,6 +64,47 @@ }; }; + pcie@14100000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + phys = <&p2u_hsio_0>; + phy-names = "p2u-0"; + }; + + pcie@14140000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + phys = <&p2u_hsio_7>; + phy-names = "p2u-0"; + }; + + pcie@14180000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, + <&p2u_hsio_5>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + pcie@141a0000 { + status = "disabled"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; + fan: fan { compatible = "pwm-fan"; pwms = <&pwm4 0 45334>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c77ca211fa8f..adebbbf36bd0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -59,6 +59,77 @@ snps,rxpbl = <8>; }; + aconnect { + compatible = "nvidia,tegra194-aconnect", + "nvidia,tegra210-aconnect"; + clocks = <&bpmp TEGRA194_CLK_APE>, + <&bpmp TEGRA194_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900000 0x02900000 0x200000>; + status = "disabled"; + + dma-controller@2930000 { + compatible = "nvidia,tegra194-adma", + "nvidia,tegra186-adma"; + reg = <0x02930000 0x20000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&bpmp TEGRA194_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: interrupt-controller@2a40000 { + compatible = "nvidia,tegra194-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x02a41000 0x1000>, + <0x02a42000 0x2000>; + interrupts = <GIC_SPI 145 + (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&bpmp TEGRA194_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>; @@ -423,6 +494,166 @@ #mbox-cells = <2>; }; + p2u_hsio_0: phy@3e10000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e10000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_1: phy@3e20000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e20000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_2: phy@3e30000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e30000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_3: phy@3e40000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e40000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_4: phy@3e50000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e50000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_5: phy@3e60000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e60000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_6: phy@3e70000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e70000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_7: phy@3e80000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e80000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_8: phy@3e90000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e90000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_9: phy@3ea0000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03ea0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_0: phy@3eb0000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03eb0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_1: phy@3ec0000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03ec0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_2: phy@3ed0000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03ed0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_3: phy@3ee0000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03ee0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_4: phy@3ef0000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03ef0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_5: phy@3f00000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03f00000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_6: phy@3f10000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03f10000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_7: phy@3f20000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03f20000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_10: phy@3f30000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03f30000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_11: phy@3f40000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03f40000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + hsp_aon: hsp@c150000 { compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; reg = <0x0c150000 0xa0000>; @@ -886,6 +1117,283 @@ }; }; + pcie@14100000 { + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ + 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ + 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <1>; + + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; + clock-names = "core"; + + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_1>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 1>; + + supports-clkreq; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ + 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ + 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + }; + + pcie@14120000 { + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ + 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ + 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <2>; + + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; + clock-names = "core"; + + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_2>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 2>; + + supports-clkreq; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ + 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ + 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + }; + + pcie@14140000 { + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ + 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ + 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <3>; + + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; + clock-names = "core"; + + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_3>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 3>; + + supports-clkreq; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ + 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ + 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + }; + + pcie@14160000 { + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ + 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ + 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <4>; + + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; + clock-names = "core"; + + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_4>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 4>; + + supports-clkreq; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ + 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ + 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + }; + + pcie@14180000 { + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ + 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ + 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + num-viewport = <8>; + linux,pci-domain = <0>; + + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; + clock-names = "core"; + + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_0>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 0>; + + supports-clkreq; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ + 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ + 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + }; + + pcie@141a0000 { + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ + 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ + 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + num-viewport = <8>; + linux,pci-domain = <5>; + + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, + <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; + clock-names = "core", "core_m"; + + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA194_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + nvidia,bpmp = <&bpmp 5>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + + supports-clkreq; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ + 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ + 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + }; + sysram@40000000 { compatible = "nvidia,tegra194-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x50000>; @@ -1053,5 +1561,6 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&gic>; + always-on; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 4dcd0d36189a..27723829d033 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -264,6 +264,19 @@ }; }; + i2c@7000c500 { + /* module ID EEPROM */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + address-bits = <8>; + page-size = <8>; + size = <256>; + read-only; + }; + }; + pmc@7000e400 { nvidia,invert-interrupt; }; @@ -328,7 +341,8 @@ regulator-max-microvolt = <1320000>; enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; regulator-ramp-delay = <80>; - regulator-enable-ramp-delay = <1000>; + regulator-enable-ramp-delay = <2000>; + regulator-settling-time-us = <160>; }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 5a57396b5948..a3cafe39ba4c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -79,6 +79,19 @@ }; }; + i2c@7000c500 { + /* carrier board ID EEPROM */ + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + + address-bits = <8>; + page-size = <8>; + size = <256>; + read-only; + }; + }; + clock@70110000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 5d0181908f45..9d17ec707bce 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -88,6 +88,35 @@ status = "okay"; }; + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + address-bits = <8>; + page-size = <8>; + size = <256>; + read-only; + }; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + + address-bits = <8>; + page-size = <8>; + size = <256>; + read-only; + }; + }; + hdmi_ddc: i2c@7000c700 { status = "okay"; clock-frequency = <100000>; @@ -515,6 +544,12 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + cpu-sleep { + status = "okay"; + }; + }; }; gpio-keys { @@ -633,17 +668,16 @@ }; vdd_gpu: regulator@6 { - compatible = "regulator-fixed"; + compatible = "pwm-regulator"; reg = <6>; - + pwms = <&pwm 1 4880>; regulator-name = "VDD_GPU"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-enable-ramp-delay = <250>; - - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - + regulator-min-microvolt = <710000>; + regulator-max-microvolt = <1320000>; + regulator-ramp-delay = <80>; + regulator-enable-ramp-delay = <2000>; + regulator-settling-time-us = <160>; + enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; vin-supply = <&vdd_5v0_sys>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a550c0a4d572..659753118e96 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -48,6 +48,11 @@ <&tegra_car 72>, <&tegra_car 74>; reset-names = "pex", "afi", "pcie_x"; + + pinctrl-names = "default", "idle"; + pinctrl-0 = <&pex_dpd_disable>; + pinctrl-1 = <&pex_dpd_enable>; + status = "disabled"; pci@1,0 { @@ -848,6 +853,20 @@ pins = "sdmmc3"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; + + pex_dpd_disable: pex_en { + pex-dpd-disable { + pins = "pex-bias", "pex-clk1", "pex-clk2"; + low-power-disable; + }; + }; + + pex_dpd_enable: pex_dis { + pex-dpd-enable { + pins = "pex-bias", "pex-clk1", "pex-clk2"; + low-power-enable; + }; + }; }; fuse@7000f800 { @@ -1258,7 +1277,7 @@ compatible = "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x702f9000 0x2000>, + reg = <0x702f9000 0x1000>, <0x702fa000 0x2000>; interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&tegra_car TEGRA210_CLK_APE>; @@ -1430,6 +1449,7 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&gic>; + arm,no-tick-in-suspend; }; soctherm: thermal-sensor@700e2000 { diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 21d548f02d39..0a7e5dfce6f7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -7,6 +7,10 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index dacd465fc62e..5ea9fb8f2f87 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -102,7 +102,7 @@ reg = <0x0>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -114,7 +114,7 @@ reg = <0x1>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -126,7 +126,7 @@ reg = <0x2>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -138,7 +138,7 @@ reg = <0x3>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -150,8 +150,11 @@ }; idle-states { - CPU_SPC: spc { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; arm,psci-suspend-param = <0x40000002>; entry-latency-us = <130>; exit-latency-us = <150>; @@ -1164,7 +1167,7 @@ }; funnel@821000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x821000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; @@ -1277,7 +1280,7 @@ }; funnel@841000 { /* APSS funnel only 4 inputs are used */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x841000 0x1000>; clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 942465d8aeb7..96c0a481f454 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -94,6 +94,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -106,6 +108,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; }; @@ -114,6 +118,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -126,6 +132,8 @@ compatible = "qcom,kryo"; reg = <0x0 0x101>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; }; @@ -150,6 +158,19 @@ }; }; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <130>; + exit-latency-us = <80>; + min-residency-us = <300>; + }; + }; }; thermal-zones { @@ -846,10 +867,11 @@ clock-names = "ref_clk_src", "ref_clk"; clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>; + resets = <&ufshc 0>; status = "disabled"; }; - ufshc@624000 { + ufshc: ufshc@624000 { compatible = "qcom,ufshc"; reg = <0x624000 0x2500>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; @@ -905,6 +927,7 @@ <0 0>; lanes-per-direction = <1>; + #reset-cells = <1>; status = "disabled"; ufs_variant { @@ -1154,7 +1177,6 @@ clock-names = "iface", "bus"; #iommu-cells = <1>; - status = "disabled"; }; camss: camss@a00000 { @@ -1307,8 +1329,6 @@ clock-names = "iface", "bus"; power-domains = <&mmcc GPU_GDSC>; - - status = "disabled"; }; mdp_smmu: arm,smmu@d00000 { @@ -1325,8 +1345,6 @@ clock-names = "iface", "bus"; power-domains = <&mmcc MDSS_GDSC>; - - status = "disabled"; }; lpass_q6_smmu: arm,smmu-lpass_q6@1600000 { @@ -1353,7 +1371,6 @@ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; clock-names = "iface", "bus"; - status = "disabled"; }; agnoc@0 { @@ -1674,7 +1691,7 @@ #interrupt-cells = <1>; clocks = <&mmcc MDSS_AHB_CLK>; - clock-names = "iface_clk"; + clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; @@ -1693,11 +1710,11 @@ <&mmcc MDSS_MDP_CLK>, <&mmcc SMMU_MDP_AXI_CLK>, <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface_clk", - "bus_clk", - "core_clk", - "iommu_clk", - "vsync_clk"; + clock-names = "iface", + "bus", + "core", + "iommu", + "vsync"; iommus = <&mdp_smmu 0>; @@ -1732,11 +1749,11 @@ <&mmcc MDSS_HDMI_AHB_CLK>, <&mmcc MDSS_EXTPCLK_CLK>; clock-names = - "mdp_core_clk", - "iface_clk", - "core_clk", - "alt_iface_clk", - "extp_clk"; + "mdp_core", + "iface", + "core", + "alt_iface", + "extp"; phys = <&hdmi_phy>; phy-names = "hdmi_phy"; @@ -1773,8 +1790,8 @@ clocks = <&mmcc MDSS_AHB_CLK>, <&gcc GCC_HDMI_CLKREF_CLK>; - clock-names = "iface_clk", - "ref_clk"; + clock-names = "iface", + "ref"; }; }; }; @@ -1814,7 +1831,7 @@ power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; compatible = "qcom,apr-v2"; qcom,smd-channels = "apr_audio_svc"; - reg = <APR_DOMAIN_ADSP>; + qcom,apr-domain = <APR_DOMAIN_ADSP>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 574be78a936e..c13ed7aeb1e0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8998.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/gpio/gpio.h> / { @@ -78,6 +79,7 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -96,6 +98,7 @@ compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L1_I_1: l1-icache { compatible = "arm,arch-cache"; @@ -110,6 +113,7 @@ compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L1_I_2: l1-icache { compatible = "arm,arch-cache"; @@ -124,6 +128,7 @@ compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L1_I_3: l1-icache { compatible = "arm,arch-cache"; @@ -138,6 +143,7 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -156,6 +162,7 @@ compatible = "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L1_I_101: l1-icache { compatible = "arm,arch-cache"; @@ -170,6 +177,7 @@ compatible = "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L1_I_102: l1-icache { compatible = "arm,arch-cache"; @@ -184,6 +192,7 @@ compatible = "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L1_I_103: l1-icache { compatible = "arm,arch-cache"; @@ -230,6 +239,48 @@ }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-retention"; + arm,psci-suspend-param = <0x00000002>; + entry-latency-us = <81>; + exit-latency-us = <86>; + min-residency-us = <200>; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <273>; + exit-latency-us = <612>; + min-residency-us = <1000>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-retention"; + arm,psci-suspend-param = <0x00000002>; + entry-latency-us = <79>; + exit-latency-us = <82>; + min-residency-us = <200>; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <336>; + exit-latency-us = <525>; + min-residency-us = <1000>; + local-timer-stop; + }; + }; }; firmware { @@ -264,6 +315,56 @@ compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,msm8998-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <16>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <32>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <48>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <64>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <128>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <192>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <256>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <320>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <384>; + }; + + rpmpd_opp_turbo_plus: opp10 { + opp-level = <512>; + }; + }; + }; }; }; @@ -758,6 +859,90 @@ #thermal-sensor-cells = <1>; }; + anoc1_smmu: iommu@1680000 { + compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; + reg = <0x01680000 0x10000>; + #iommu-cells = <1>; + + #global-interrupts = <0>; + interrupts = + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; + }; + + pcie0: pci@1c00000 { + compatible = "qcom,pcie-msm8996"; + reg = <0x01c00000 0x2000>, + <0x1b000000 0xf1d>, + <0x1b000f20 0xa8>, + <0x1b100000 0x100000>; + reg-names = "parf", "dbi", "elbi", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + num-lanes = <1>; + phys = <&pciephy>; + phy-names = "pciephy"; + + ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, + <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; + + #interrupt-cells = <1>; + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>; + clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; + + power-domains = <&gcc PCIE_0_GDSC>; + iommu-map = <0x100 &anoc1_smmu 0x1480 1>; + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + }; + + phy@1c06000 { + compatible = "qcom,msm8998-qmp-pcie-phy"; + reg = <0x01c06000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy", "common"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + + pciephy: lane@1c06800 { + reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "pcie_0_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index d3ca35a940fb..051a52df80f9 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -39,7 +39,7 @@ #size-cells = <0>; pm8998_pon: pon@800 { - compatible = "qcom,pm8916-pon"; + compatible = "qcom,pm8998-pon"; reg = <0x800>; mode-bootloader = <0x2>; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index e8e186bc1ea7..14240fedd916 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -98,7 +98,7 @@ qcom,pre-scaling = <1 1>; }; - vph_pwr { + pon_1: vph_pwr { reg = <ADC5_VPH_PWR>; qcom,pre-scaling = <1 3>; }; @@ -108,18 +108,24 @@ qcom,pre-scaling = <1 1>; }; - xo_therm_100k_pu { - reg = <ADC5_XO_THERM_100K_PU>; + pa_therm1: thermistor1 { + reg = <ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; - amux_thm1_100k_pu { - reg = <ADC5_AMUX_THM1_100K_PU>; + pa_therm3: thermistor3 { + reg = <ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; - amux_thm3_100k_pu { - reg = <ADC5_AMUX_THM3_100K_PU>; + xo_therm: xo_temp { + reg = <ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 2c3127167e3c..11c0a7137823 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2018, Linaro Limited +#include <dt-bindings/gpio/gpio.h> #include "qcs404.dtsi" #include "pms405.dtsi" @@ -56,18 +57,41 @@ qcom,controlled-remotely; }; +&gcc { + protected-clocks = <GCC_BIMC_CDSP_CLK>, + <GCC_CDSP_CFG_AHB_CLK>, + <GCC_CDSP_BIMC_CLK_SRC>, + <GCC_CDSP_TBU_CLK>; +}; + &pms405_spmi_regulators { - vdd_s3-supply = <&pms405_s3>; + vdd_s3-supply = <&vph_pwr>; pms405_s3: s3 { regulator-always-on; regulator-boot-on; regulator-name = "vdd_apc"; regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1352000>; + regulator-max-microvolt = <1384000>; }; }; +&pcie { + status = "ok"; + + perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&perst_state>; +}; + +&pcie_phy { + status = "ok"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; +}; + &remoteproc_adsp { status = "ok"; }; @@ -118,7 +142,7 @@ }; vreg_l3_1p05: l3 { - regulator-min-microvolt = <1050000>; + regulator-min-microvolt = <1048000>; regulator-max-microvolt = <1160000>; }; @@ -184,6 +208,15 @@ }; &tlmm { + perst_state: perst { + pins = "gpio43"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-low; + }; + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; @@ -200,7 +233,7 @@ data { pins = "sdc1_data"; bias-pull-up; - dreive-strength = <10>; + drive-strength = <10>; }; rclk { @@ -225,7 +258,7 @@ data { pins = "sdc1_data"; bias-pull-up; - dreive-strength = <2>; + drive-strength = <2>; }; rclk { diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ffedf9640af7..3d0789775009 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -3,7 +3,10 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-qcs404.h> +#include <dt-bindings/clock/qcom,turingcc-qcs404.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -30,7 +33,9 @@ compatible = "arm,cortex-a53"; reg = <0x100>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; + #cooling-cells = <2>; }; CPU1: cpu@101 { @@ -38,7 +43,9 @@ compatible = "arm,cortex-a53"; reg = <0x101>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; + #cooling-cells = <2>; }; CPU2: cpu@102 { @@ -46,7 +53,9 @@ compatible = "arm,cortex-a53"; reg = <0x102>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; + #cooling-cells = <2>; }; CPU3: cpu@103 { @@ -54,13 +63,29 @@ compatible = "arm,cortex-a53"; reg = <0x103>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; + #cooling-cells = <2>; }; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <125>; + exit-latency-us = <180>; + min-residency-us = <595>; + local-timer-stop; + }; + }; }; firmware { @@ -81,99 +106,6 @@ method = "smc"; }; - remoteproc_adsp: remoteproc-adsp { - compatible = "qcom,qcs404-adsp-pas"; - - interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_fw_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; - - qcom,remote-pid = <2>; - mboxes = <&apcs_glb 8>; - - label = "adsp"; - }; - }; - - remoteproc_cdsp: remoteproc-cdsp { - compatible = "qcom,qcs404-cdsp-pas"; - - interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&cdsp_fw_mem>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; - - qcom,remote-pid = <5>; - mboxes = <&apcs_glb 12>; - - label = "cdsp"; - }; - }; - - remoteproc_wcss: remoteproc-wcss { - compatible = "qcom,qcs404-wcss-pas"; - - interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&wlan_fw_mem>; - - qcom,smem-states = <&wcss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; - - qcom,remote-pid = <1>; - mboxes = <&apcs_glb 16>; - - label = "wcss"; - }; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -230,6 +162,60 @@ compatible = "qcom,rpmcc-qcs404"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,qcs404-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <16>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <32>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <48>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <64>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <128>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <192>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <256>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <320>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <384>; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = <416>; + }; + + rpmpd_opp_turbo_plus: opp11 { + opp-level = <512>; + }; + }; + }; }; }; @@ -254,11 +240,32 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + turingcc: clock-controller@800000 { + compatible = "qcom,qcs404-turingcc"; + reg = <0x00800000 0x30000>; + clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + + status = "disabled"; + }; + rpm_msg_ram: memory@60000 { compatible = "qcom,rpm-msg-ram"; reg = <0x00060000 0x6000>; }; + qfprom: qfprom@a4000 { + compatible = "qcom,qfprom"; + reg = <0x000a4000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@d0 { + reg = <0x1f8 0x14>; + }; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; @@ -266,6 +273,67 @@ clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + remoteproc_cdsp: remoteproc@b00000 { + compatible = "qcom,qcs404-cdsp-pas"; + reg = <0x00b00000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>, + <&gcc GCC_CDSP_CFG_AHB_CLK>, + <&gcc GCC_CDSP_TBU_CLK>, + <&gcc GCC_BIMC_CDSP_CLK>, + <&turingcc TURING_WRAPPER_AON_CLK>, + <&turingcc TURING_Q6SS_AHBS_AON_CLK>, + <&turingcc TURING_Q6SS_AHBM_AON_CLK>, + <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; + clock-names = "xo", + "sway", + "tbu", + "bimc", + "ahb_aon", + "q6ss_slave", + "q6ss_master", + "q6_axim"; + + resets = <&gcc GCC_CDSP_RESTART>; + reset-names = "restart"; + + qcom,halt-regs = <&tcsr 0x19004>; + + memory-region = <&cdsp_fw_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; + + qcom,remote-pid = <5>; + mboxes = <&apcs_glb 12>; + + label = "cdsp"; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, @@ -383,6 +451,7 @@ compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #reset-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; @@ -393,6 +462,11 @@ reg = <0x01905000 0x20000>; }; + tcsr: syscon@1937000 { + compatible = "syscon"; + reg = <0x01937000 0x25000>; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, @@ -411,6 +485,53 @@ #interrupt-cells = <4>; }; + remoteproc_wcss: remoteproc@7400000 { + compatible = "qcom,qcs404-wcss-pas"; + reg = <0x07400000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&wlan_fw_mem>; + + qcom,smem-states = <&wcss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 16>; + + label = "wcss"; + }; + }; + + pcie_phy: phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc 21>; + reset-names = "phy", "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + + status = "disabled"; + }; + sdcc1: sdcc@7804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; @@ -796,6 +917,88 @@ status = "disabled"; }; }; + + remoteproc_adsp: remoteproc@c700000 { + compatible = "qcom,qcs404-adsp-pas"; + reg = <0x0c700000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_fw_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; + + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + + label = "adsp"; + }; + }; + + pcie: pci@10000000 { + compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x07780000 0x2000>, + <0x10001000 0x2000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ + <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ + + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "iface", "aux", "master_bus", "slave_bus"; + + resets = <&gcc 18>, + <&gcc 17>, + <&gcc 15>, + <&gcc 19>, + <&gcc GCC_PCIE_0_BCR>, + <&gcc 16>; + reset-names = "axi_m", + "axi_s", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb"; + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; }; timer { @@ -865,4 +1068,251 @@ #interrupt-cells = <2>; }; }; + + thermal-zones { + aoss-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + aoss_alert0: trip-point@0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + q6_hvx_alert0: trip-point@0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + lpass-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + lpass_alert0: trip-point@0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + wlan_alert0: trip-point@0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + cluster_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cluster_crit: cluster_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cluster_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu0_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu0_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: cpu_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu0_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu1_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu1_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_crit: cpu_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu2_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu2_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_crit: cpu_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu3_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu3_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu3_crit: cpu_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + gpu_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts new file mode 100644 index 000000000000..bd7c25bb8d35 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Cheza board device tree source + * + * Copyright 2018 Google LLC. + */ + +/dts-v1/; + +#include "sdm845-cheza.dtsi" + +/ { + model = "Google Cheza (rev1)"; + compatible = "google,cheza-rev1", "qcom,sdm845"; + + /* + * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children + */ + + /* + * NOTE: Technically pp3500_a is not the exact same signal as + * pp3500_a_vbob (there's a load switch between them and the EC can + * control pp3500_a via "en_pp3300_a"), but from the AP's point of + * view they are the same. + */ + pp3500_a: + pp3500_a_vbob: pp3500-a-vbob-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob"; + + /* + * Comes on automatically when pp5000_ldo comes on, which + * comes on automatically when ppvar_sys comes on + */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3500000>; + regulator-max-microvolt = <3500000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_dx_edp: pp3300-dx-edp-regulator { + /* Yes, it's really 3.5 despite the name of the signal */ + regulator-min-microvolt = <3500000>; + regulator-max-microvolt = <3500000>; + + vin-supply = <&pp3500_a>; + }; +}; + +/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ + +/* + * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware + * that limits them to 3.0, and trying to run at 3.3V with that old firmware + * prevents the system from booting. + */ +&src_pp3000_l19a { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; +}; + +&src_pp3300_l22a { + /delete-property/regulator-boot-on; + /delete-property/regulator-always-on; +}; + +&src_pp3300_l28a { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; +}; + +&src_vreg_bob { + regulator-min-microvolt = <3500000>; + regulator-max-microvolt = <3500000>; + vin-supply = <&pp3500_a_vbob>; +}; + +/* + * NON-REGULATOR OVERRIDES + * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label + */ + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "", + "FP_RST_L", + "FCAM_EN", + "", + "EDP_BRIJ_IRQ", + "EC_IN_RW_ODL", + "", + "RCAM_MCLK", + "FCAM_MCLK", + "", + "RCAM_EN", + "CCI0_SDA", + "CCI0_SCL", + "CCI1_SDA", + "CCI1_SCL", + "FCAM_RST_L", + "", + "PEN_RST_L", + "PEN_IRQ_L", + "", + "RCAM_VSYNC", + "ESIM_MISO", + "ESIM_MOSI", + "ESIM_CLK", + "ESIM_CS_L", + "AP_PEN_1V8_SDA", + "AP_PEN_1V8_SCL", + "AP_TS_I2C_SDA", + "AP_TS_I2C_SCL", + "RCAM_RST_L", + "", + "AP_EDP_BKLTEN", + "AP_BRD_ID1", + "BOOT_CONFIG_4", + "AMP_IRQ_L", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "EN_PP3300_DX_EDP", + "SD_CD_ODL", + "BT_UART_RTS", + "BT_UART_CTS", + "BT_UART_RXD", + "BT_UART_TXD", + "AMP_I2C_SDA", + "AMP_I2C_SCL", + "AP_BRD_ID3", + "", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DOUT", + "AMP_DIN", + "AP_BRD_ID2", + "PEN_PDCT_L", + "HP_MCLK", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "", + "", + "", + "", + "BT_SLIMBUS_DATA", + "BT_SLIMBUS_CLK", + "AMP_RESET_L", + "", + "FCAM_VSYNC", + "", + "AP_SKU_ID1", + "EC_WOV_BCLK", + "EC_WOV_LRCLK", + "EC_WOV_DOUT", + "", + "", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "AP_SPI_CS0_L", + "AP_SPI_MOSI", + "AP_SPI_MISO", + "", + "", + "AP_SPI_CLK", + "", + "RFFE6_CLK", + "RFFE6_DATA", + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_0", + "EDP_BRIJ_EN", + "", + "USB_HS_TX_EN", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "AP_SKU_ID2", + "SDM_GRFC_8", + "SDM_GRFC_9", + "AP_RST_REQ", + "HP_IRQ", + "TS_RESET_L", + "PEN_EJECT_ODL", + "HUB_RST_L", + "FP_TO_AP_IRQ", + "AP_EC_INT_L", + "", + "", + "TS_INT_L", + "AP_SUSPEND_L", + "SDM_GRFC_3", + "", + "H1_AP_INT_ODL", + "QLINK_REQ", + "QLINK_EN", + "SDM_GRFC_2", + "BOOT_CONFIG_3", + "WMSS_RESET_L", + "SDM_GRFC_0", + "SDM_GRFC_1", + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "RFFE4_CLK", + "RFFE5_DATA", + "RFFE5_CLK", + "GNSS_EN", + "WCI2_LTE_COEX_RXD", + "WCI2_LTE_COEX_TXD", + "AP_RAM_ID1", + "AP_RAM_ID2", + "RFFE1_DATA", + "RFFE1_CLK"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts new file mode 100644 index 000000000000..2b7230594ecb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Cheza board device tree source + * + * Copyright 2018 Google LLC. + */ + +/dts-v1/; + +#include "sdm845-cheza.dtsi" + +/ { + model = "Google Cheza (rev2)"; + compatible = "google,cheza-rev2", "qcom,sdm845"; + + /* + * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children + */ + + /* + * NOTE: Technically pp3500_a is not the exact same signal as + * pp3500_a_vbob (there's a load switch between them and the EC can + * control pp3500_a via "en_pp3300_a"), but from the AP's point of + * view they are the same. + */ + pp3500_a: + pp3500_a_vbob: pp3500-a-vbob-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob"; + + /* + * Comes on automatically when pp5000_ldo comes on, which + * comes on automatically when ppvar_sys comes on + */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3500000>; + regulator-max-microvolt = <3500000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_dx_edp: pp3300-dx-edp-regulator { + /* Yes, it's really 3.5 despite the name of the signal */ + regulator-min-microvolt = <3500000>; + regulator-max-microvolt = <3500000>; + + vin-supply = <&pp3500_a>; + }; +}; + +/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ + +/* + * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware + * that limits them to 3.0, and trying to run at 3.3V with that old firmware + * prevents the system from booting. + */ +&src_pp3000_l19a { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; +}; + +&src_pp3300_l22a { + /delete-property/regulator-boot-on; + /delete-property/regulator-always-on; +}; + +&src_pp3300_l28a { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; +}; + +&src_vreg_bob { + regulator-min-microvolt = <3500000>; + regulator-max-microvolt = <3500000>; + vin-supply = <&pp3500_a_vbob>; +}; + +/* + * NON-REGULATOR OVERRIDES + * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label + */ + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "BRIJ_SUSPEND", + "FP_RST_L", + "FCAM_EN", + "", + "EDP_BRIJ_IRQ", + "EC_IN_RW_ODL", + "", + "RCAM_MCLK", + "FCAM_MCLK", + "", + "RCAM_EN", + "CCI0_SDA", + "CCI0_SCL", + "CCI1_SDA", + "CCI1_SCL", + "FCAM_RST_L", + "FPMCU_BOOT0", + "PEN_RST_L", + "PEN_IRQ_L", + "FPMCU_SEL_OD", + "RCAM_VSYNC", + "ESIM_MISO", + "ESIM_MOSI", + "ESIM_CLK", + "ESIM_CS_L", + "AP_PEN_1V8_SDA", + "AP_PEN_1V8_SCL", + "AP_TS_I2C_SDA", + "AP_TS_I2C_SCL", + "RCAM_RST_L", + "", + "AP_EDP_BKLTEN", + "AP_BRD_ID1", + "BOOT_CONFIG_4", + "AMP_IRQ_L", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "EN_PP3300_DX_EDP", + "SD_CD_ODL", + "BT_UART_RTS", + "BT_UART_CTS", + "BT_UART_RXD", + "BT_UART_TXD", + "AMP_I2C_SDA", + "AMP_I2C_SCL", + "AP_BRD_ID3", + "", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DOUT", + "AMP_DIN", + "AP_BRD_ID2", + "PEN_PDCT_L", + "HP_MCLK", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "", + "", + "", + "", + "BT_SLIMBUS_DATA", + "BT_SLIMBUS_CLK", + "AMP_RESET_L", + "", + "FCAM_VSYNC", + "", + "AP_SKU_ID1", + "EC_WOV_BCLK", + "EC_WOV_LRCLK", + "EC_WOV_DOUT", + "", + "", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "AP_SPI_CS0_L", + "AP_SPI_MOSI", + "AP_SPI_MISO", + "", + "", + "AP_SPI_CLK", + "", + "RFFE6_CLK", + "RFFE6_DATA", + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_0", + "EDP_BRIJ_EN", + "", + "USB_HS_TX_EN", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "AP_SKU_ID2", + "SDM_GRFC_8", + "SDM_GRFC_9", + "AP_RST_REQ", + "HP_IRQ", + "TS_RESET_L", + "PEN_EJECT_ODL", + "HUB_RST_L", + "FP_TO_AP_IRQ", + "AP_EC_INT_L", + "", + "", + "TS_INT_L", + "AP_SUSPEND_L", + "SDM_GRFC_3", + "", + "H1_AP_INT_ODL", + "QLINK_REQ", + "QLINK_EN", + "SDM_GRFC_2", + "BOOT_CONFIG_3", + "WMSS_RESET_L", + "SDM_GRFC_0", + "SDM_GRFC_1", + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "RFFE4_CLK", + "RFFE5_DATA", + "RFFE5_CLK", + "GNSS_EN", + "WCI2_LTE_COEX_RXD", + "WCI2_LTE_COEX_TXD", + "AP_RAM_ID1", + "AP_RAM_ID2", + "RFFE1_DATA", + "RFFE1_CLK"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts new file mode 100644 index 000000000000..1ba67be08f81 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Cheza board device tree source + * + * Copyright 2018 Google LLC. + */ + +/dts-v1/; + +#include "sdm845-cheza.dtsi" + +/ { + model = "Google Cheza (rev3+)"; + compatible = "google,cheza", "qcom,sdm845"; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "BRIJ_SUSPEND", + "FP_RST_L", + "FCAM_EN", + "", + "EDP_BRIJ_IRQ", + "EC_IN_RW_ODL", + "", + "RCAM_MCLK", + "FCAM_MCLK", + "", + "RCAM_EN", + "CCI0_SDA", + "CCI0_SCL", + "CCI1_SDA", + "CCI1_SCL", + "FCAM_RST_L", + "FPMCU_BOOT0", + "PEN_RST_L", + "PEN_IRQ_L", + "FPMCU_SEL_OD", + "RCAM_VSYNC", + "ESIM_MISO", + "ESIM_MOSI", + "ESIM_CLK", + "ESIM_CS_L", + "AP_PEN_1V8_SDA", + "AP_PEN_1V8_SCL", + "AP_TS_I2C_SDA", + "AP_TS_I2C_SCL", + "RCAM_RST_L", + "", + "AP_EDP_BKLTEN", + "AP_BRD_ID0", + "BOOT_CONFIG_4", + "AMP_IRQ_L", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "EN_PP3300_DX_EDP", + "SD_CD_ODL", + "BT_UART_RTS", + "BT_UART_CTS", + "BT_UART_RXD", + "BT_UART_TXD", + "AMP_I2C_SDA", + "AMP_I2C_SCL", + "AP_BRD_ID2", + "", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DOUT", + "AMP_DIN", + "AP_BRD_ID1", + "PEN_PDCT_L", + "HP_MCLK", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "", + "", + "", + "", + "BT_SLIMBUS_DATA", + "BT_SLIMBUS_CLK", + "AMP_RESET_L", + "", + "FCAM_VSYNC", + "", + "AP_SKU_ID0", + "EC_WOV_BCLK", + "EC_WOV_LRCLK", + "EC_WOV_DOUT", + "", + "", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "AP_SPI_CS0_L", + "AP_SPI_MOSI", + "AP_SPI_MISO", + "", + "", + "AP_SPI_CLK", + "", + "RFFE6_CLK", + "RFFE6_DATA", + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_0", + "EDP_BRIJ_EN", + "", + "USB_HS_TX_EN", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "AP_SKU_ID1", + "SDM_GRFC_8", + "SDM_GRFC_9", + "AP_RST_REQ", + "HP_IRQ", + "TS_RESET_L", + "PEN_EJECT_ODL", + "HUB_RST_L", + "FP_TO_AP_IRQ", + "AP_EC_INT_L", + "", + "", + "TS_INT_L", + "AP_SUSPEND_L", + "SDM_GRFC_3", + /* + * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics + * call it BIOS_FLASH_WP_R_L. + */ + "AP_FLASH_WP_L", + "H1_AP_INT_ODL", + "QLINK_REQ", + "QLINK_EN", + "SDM_GRFC_2", + "BOOT_CONFIG_3", + "WMSS_RESET_L", + "SDM_GRFC_0", + "SDM_GRFC_1", + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "RFFE4_CLK", + "RFFE5_DATA", + "RFFE5_CLK", + "GNSS_EN", + "WCI2_LTE_COEX_RXD", + "WCI2_LTE_COEX_TXD", + "AP_RAM_ID0", + "AP_RAM_ID1", + "RFFE1_DATA", + "RFFE1_CLK"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi new file mode 100644 index 000000000000..1ebbd568dfd7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -0,0 +1,1326 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Cheza device tree source (common between revisions) + * + * Copyright 2018 Google LLC. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sdm845.dtsi" + +/* PMICs depend on spmi_bus label and so must come after SoC */ +#include "pm8005.dtsi" +#include "pm8998.dtsi" + +/ { + aliases { + bluetooth0 = &bluetooth; + hsuart0 = &uart6; + serial0 = &uart9; + wifi0 = &wifi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&cros_ec_pwm 0>; + enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + power-supply = <&ppvar_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_edp_bklten>; + }; + + /* FIXED REGULATORS - parents above children */ + + /* This is the top level supply and variable voltage */ + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + /* This divides ppvar_sys by 2, so voltage is variable */ + src_vph_pwr: src-vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "src_vph_pwr"; + + /* EC turns on with switchcap_on_l; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; + + pp5000_a: pp5000-a-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp5000_a"; + + /* EC turns on with en_pp5000_a; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&ppvar_sys>; + }; + + src_vreg_bob: src-vreg-bob-regulator { + compatible = "regulator-fixed"; + regulator-name = "src_vreg_bob"; + + /* EC turns on with vbob_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_dx_edp: pp3300-dx-edp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_dx_edp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_dx_edp>; + }; + + /* + * Apparently RPMh does not provide support for PM8998 S4 because it + * is always-on; model it as a fixed regulator. + */ + src_pp1800_s4a: pm8998-smps4 { + compatible = "regulator-fixed"; + regulator-name = "src_pp1800_s4a"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&src_vph_pwr>; + }; + + /* BOARD-SPECIFIC TOP LEVEL NODES */ + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pen_eject_odl>; + + pen-insert { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; + linux,code = <SW_PEN_INSERTED>; + linux,input-type = <EV_SW>; + wakeup-source; + }; + }; + + panel: panel { + compatible ="innolux,p120zdg-bf1"; + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + no-hpd; + + ports { + panel_in: port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; +}; + +/* + * Reserved memory changes + * + * Putting this all together (out of order with the rest of the file) to keep + * all modifications to the memory map (from sdm845.dtsi) in one place. + */ + +/* + * Our mpss_region is 8MB bigger than the default one and that conflicts + * with venus_mem and cdsp_mem. + * + * For venus_mem we'll delete and re-create at a different address. + * + * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but + * that also means we need to delete cdsp_pas. + */ +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &cdsp_pas; + +/* Increase the size from 120 MB to 128 MB */ +&mpss_region { + reg = <0 0x8e000000 0 0x8000000>; +}; + +/* Increase the size from 2MB to 8MB */ +&rmtfs_mem { + reg = <0 0x88f00000 0 0x800000>; +}; + +/ { + reserved-memory { + venus_mem: memory@96000000 { + reg = <0 0x96000000 0 0x500000>; + no-map; + }; + }; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* + * In theory chip supports up to 104 MHz and controller up + * to 80 MHz, but above 25 MHz wasn't reliable so we'll use + * that for now. b:117440651 + */ + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&src_vph_pwr>; + vdd-s2-supply = <&src_vph_pwr>; + vdd-s3-supply = <&src_vph_pwr>; + vdd-s4-supply = <&src_vph_pwr>; + vdd-s5-supply = <&src_vph_pwr>; + vdd-s6-supply = <&src_vph_pwr>; + vdd-s7-supply = <&src_vph_pwr>; + vdd-s8-supply = <&src_vph_pwr>; + vdd-s9-supply = <&src_vph_pwr>; + vdd-s10-supply = <&src_vph_pwr>; + vdd-s11-supply = <&src_vph_pwr>; + vdd-s12-supply = <&src_vph_pwr>; + vdd-s13-supply = <&src_vph_pwr>; + vdd-l1-l27-supply = <&src_pp1025_s7a>; + vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; + vdd-l3-l11-supply = <&src_pp1025_s7a>; + vdd-l4-l5-supply = <&src_pp1025_s7a>; + vdd-l6-supply = <&src_vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; + vdd-l9-supply = <&src_pp2040_s5a>; + vdd-l10-l23-l25-supply = <&src_vreg_bob>; + vdd-l13-l19-l21-supply = <&src_vreg_bob>; + vdd-l16-l28-supply = <&src_vreg_bob>; + vdd-l18-l22-supply = <&src_vreg_bob>; + vdd-l20-l24-supply = <&src_vreg_bob>; + vdd-l26-supply = <&src_pp1350_s3a>; + vin-lvs-1-2-supply = <&src_pp1800_s4a>; + + src_pp1125_s2a: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + src_pp1350_s3a: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + src_pp2040_s5a: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + src_pp1025_s7a: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + src_pp875_l1a: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_10: + src_pp1200_l2a: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + + /* TODO: why??? */ + regulator-always-on; + }; + + pp1000_l3a_sdr845: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + src_pp800_l5a: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_13: + src_pp1800_l6a: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pp1800_l7a_wcn3990: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + src_pp1200_l8a: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pp1800_dx_pen: + src_pp1800_l9a: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + src_pp1800_l10a: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pp1000_l11a_sdr845: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + src_pp1800_l12a: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_2: + src_pp2950_l13a: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + src_pp1800_l14a: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + src_pp1800_l15a: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pp2700_l16a: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + src_pp1300_l17a: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pp2700_l18a: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* + * NOTE: this rail should have been called + * src_pp3300_l19a in the schematic + */ + src_pp3000_l19a: ldo19 { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + src_pp2950_l20a: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + src_pp2950_l21a: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pp3300_hub: + src_pp3300_l22a: ldo22 { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + /* + * HACK: Should add a usb hub node and driver + * to turn this on and off at suspend/resume time + */ + regulator-boot-on; + regulator-always-on; + }; + + pp3300_l23a_ch1_wcn3990: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_qusb_hs0_3p1: + src_pp3075_l24a: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pp3300_l25a_ch0_wcn3990: ldo25 { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pp1200_hub: + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + src_pp1200_l26a: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pp3300_dx_pen: + src_pp3300_l28a: ldo28 { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + src_pp1800_lvs1: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + src_pp1800_lvs2: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&src_vph_pwr>; + vdd-s2-supply = <&src_vph_pwr>; + vdd-s3-supply = <&src_vph_pwr>; + vdd-s4-supply = <&src_vph_pwr>; + + src_pp600_s3c: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + +edp_brij_i2c: &i2c3 { + status = "okay"; + clock-frequency = <400000>; + + sn65dsi86_bridge: bridge@2d { + compatible = "ti,sn65dsi86"; + reg = <0x2d>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_brij_en &edp_brij_irq>; + + interrupt-parent = <&tlmm>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&src_pp1800_s4a>; + vccio-supply = <&src_pp1800_s4a>; + vcca-supply = <&src_pp1200_l2a>; + vcc-supply = <&src_pp1200_l2a>; + + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + clock-names = "refclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; +}; + +ap_pen_1v8: &i2c11 { + status = "okay"; + clock-frequency = <400000>; + + digitizer@9 { + compatible = "wacom,w9013", "hid-over-i2c"; + reg = <0x9>; + pinctrl-names = "default"; + pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; + + vdd-supply = <&pp3300_dx_pen>; + vddl-supply = <&pp1800_dx_pen>; + post-power-on-delay-ms = <100>; + + interrupt-parent = <&tlmm>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x1>; + }; +}; + +amp_i2c: &i2c12 { + status = "okay"; + clock-frequency = <400000>; +}; + +ap_ts_i2c: &i2c14 { + status = "okay"; + clock-frequency = <400000>; + + touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l &ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <125 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&src_pp3300_l28a>; + + reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; + }; +}; + +&lpasscc { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; + + vmmc-supply = <&src_pp2950_l21a>; + vqmmc-supply = <&vddpx_2>; + + cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; +}; + +&spi0 { + status = "okay"; +}; + +&spi10 { + status = "okay"; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <122 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_ap_int_l>; + spi-max-frequency = <3000000>; + + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pdupdate { + compatible = "google,cros-ec-pd-update"; + }; + }; +}; + +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi> + +&uart6 { + status = "okay"; + + bluetooth: wcn3990-bt { + compatible = "qcom,wcn3990-bt"; + vddio-supply = <&src_pp1800_s4a>; + vddxo-supply = <&pp1800_l7a_wcn3990>; + vddrf-supply = <&src_pp1300_l17a>; + vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; + max-speed = <3200000>; + }; +}; + +&uart9 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + pinctrl-names = "init", "default"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + vcc-supply = <&src_pp2950_l20a>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + +&usb_1 { + status = "okay"; + + /* We'll use this as USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; +}; + +&usb_1_dwc3 { + /* + * The hardware design intends this port to be hooked up in peripheral + * mode, so we'll hardcode it here. Some details: + * - SDM845 expects only a single Type C connector so it has only one + * native Type C port but cheza has two Type C connectors. + * - The only source of DP is the single native Type C port. + * - On cheza we want to be able to hook DP up to _either_ of the + * two Type C connectors and want to be able to achieve 4 lanes of DP. + * - When you configure a Type C port for 4 lanes of DP you lose USB3. + * - In order to make everything work, the native Type C port is always + * configured as 4-lanes DP so it's always available. + * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then + * sent to the two Type C connectors. + * - The extra USB2 lines from the native Type C port are always + * setup as "peripheral" so that we can mux them over to one connector + * or the other if someone needs the connector configured as a gadget + * (but they only get USB2 speeds). + * + * All the hardware muxes would allow us to hook things up in different + * ways to some potential benefit for static configurations (you could + * achieve extra USB2 bandwidth by using two different ports for the + * two conenctors or possibly even get USB3 peripheral mode), but in + * each case you end up forcing to disconnect/reconnect an in-use + * USB session in some cases depending on what you hotplug into the + * other connector. Thus hardcoding this as peripheral makes sense. + */ + dr_mode = "peripheral"; + + /* + * We always need the high speed pins as 4-lanes DP in case someone + * hotplugs a DP peripheral. Thus limit this port to a max of high + * speed. + */ + maximum-speed = "high-speed"; + + /* + * We don't need the usb3-phy since we run in highspeed mode always, so + * re-define these properties removing the superspeed USB PHY reference. + */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + /* We have this hooked up to a hub and we always use in host mode */ + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdd-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; + vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; + vdd-1.3-rfa-supply = <&src_pp1300_l17a>; + vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ + +&qspi_cs0 { + pinconf { + pins = "gpio90"; + bias-disable; + }; +}; + +&qspi_clk { + pinconf { + pins = "gpio95"; + bias-disable; + }; +}; + +&qspi_data01 { + pinconf { + pins = "gpio91", "gpio92"; + + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; + }; +}; + +&qup_i2c3_default { + pinconf { + pins = "gpio41", "gpio42"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c11_default { + pinconf { + pins = "gpio31", "gpio32"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c12_default { + pinconf { + pins = "gpio49", "gpio50"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c14_default { + pinconf { + pins = "gpio33", "gpio34"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_spi0_default { + pinconf { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi5_default { + pinconf { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi10_default { + pinconf { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_uart6_default { + /* Change pinmux to all 4 pins since CTS and RTS are connected */ + pinmux { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + }; + + pinconf-cts { + /* + * Configure a pull-down on 45 (CTS) to match the pull of + * the Bluetooth module. + */ + pins = "gpio45"; + bias-pull-down; + }; + + pinconf-rts-tx { + /* We'll drive 46 (RTS) and 47 (TX), so no pull */ + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-rx { + /* + * Configure a pull-up on 48 (RX). This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + pins = "gpio48"; + bias-pull-up; + }; +}; + +&qup_uart9_default { + pinconf-tx { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +/* PINCTRL - board-specific pinctrl */ +&pm8005_gpio { + gpio-line-names = "", + "", + "SLB", + ""; +}; + +&pm8998_adc { + adc-chan@ADC5_AMUX_THM1_100K_PU { + reg = <ADC5_AMUX_THM1_100K_PU>; + label = "sdm_temp"; + }; + + adc-chan@ADC5_AMUX_THM2_100K_PU { + reg = <ADC5_AMUX_THM2_100K_PU>; + label = "quiet_temp"; + }; + + adc-chan@ADC5_AMUX_THM3_100K_PU { + reg = <ADC5_AMUX_THM3_100K_PU>; + label = "lte_temp_1"; + }; + + adc-chan@ADC5_AMUX_THM4_100K_PU { + reg = <ADC5_AMUX_THM4_100K_PU>; + label = "lte_temp_2"; + }; + + adc-chan@ADC5_AMUX_THM5_100K_PU { + reg = <ADC5_AMUX_THM5_100K_PU>; + label = "charger_temp"; + }; +}; + +&pm8998_gpio { + gpio-line-names = "", + "", + "SW_CTRL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "CFG_OPT1", + "WCSS_PWR_REQ", + "", + "CFG_OPT2", + "SLB"; +}; + +&tlmm { + /* + * pinctrl settings for pins that have no real owners. + */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&bios_flash_wp_r_l>, + <&ap_suspend_l_deassert>; + + pinctrl-1 = <&bios_flash_wp_r_l>, + <&ap_suspend_l_assert>; + + /* + * Hogs prevent usermode from changing the value. A GPIO can be both + * here and in the pinctrl section. + */ + ap-suspend-l-hog { + gpio-hog; + gpios = <126 GPIO_ACTIVE_LOW>; + output-low; + }; + + ap_edp_bklten: ap-edp-bklten { + pinmux { + pins = "gpio37"; + function = "gpio"; + }; + + pinconf { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + + bios_flash_wp_r_l: bios-flash-wp-r-l { + pinmux { + pins = "gpio128"; + function = "gpio"; + input-enable; + }; + + pinconf { + pins = "gpio128"; + bias-disable; + }; + }; + + ec_ap_int_l: ec-ap-int-l { + pinmux { + pins = "gpio122"; + function = "gpio"; + input-enable; + }; + + pinconf { + pins = "gpio122"; + bias-pull-up; + }; + }; + + edp_brij_en: edp-brij-en { + pinmux { + pins = "gpio102"; + function = "gpio"; + }; + + pinconf { + pins = "gpio102"; + drive-strength = <2>; + bias-disable; + }; + }; + + edp_brij_irq: edp-brij-irq { + pinmux { + pins = "gpio10"; + function = "gpio"; + }; + + pinconf { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + en_pp3300_dx_edp: en-pp3300-dx-edp { + pinmux { + pins = "gpio43"; + function = "gpio"; + }; + + pinconf { + pins = "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + + h1_ap_int_odl: h1-ap-int-odl { + pinmux { + pins = "gpio129"; + function = "gpio"; + input-enable; + }; + + pinconf { + pins = "gpio129"; + bias-pull-up; + }; + }; + + pen_eject_odl: pen-eject-odl { + pinmux { + pins = "gpio119"; + function = "gpio"; + bias-pull-up; + }; + }; + + pen_irq_l: pen-irq-l { + pinmux { + pins = "gpio24"; + function = "gpio"; + }; + + pinconf { + pins = "gpio24"; + + /* Has external pullup */ + bias-disable; + }; + }; + + pen_pdct_l: pen-pdct-l { + pinmux { + pins = "gpio63"; + function = "gpio"; + }; + + pinconf { + pins = "gpio63"; + + /* Has external pullup */ + bias-disable; + }; + }; + + pen_rst_l: pen-rst-l { + pinmux { + pins = "gpio23"; + function = "gpio"; + }; + + pinconf { + pins = "gpio23"; + bias-disable; + drive-strength = <2>; + + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; + }; + }; + + sdc2_clk: sdc2-clk { + pinconf { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16. + */ + drive-strength = <16>; + }; + }; + + sdc2_cmd: sdc2-cmd { + pinconf { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sdc2_data: sdc2-data { + pinconf { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sd_cd_odl: sd-cd-odl { + pinmux { + pins = "gpio44"; + function = "gpio"; + }; + + pinconf { + pins = "gpio44"; + bias-pull-up; + }; + }; + + ts_int_l: ts-int-l { + pinmux { + pins = "gpio125"; + function = "gpio"; + }; + + pinconf { + pins = "gpio125"; + bias-pull-up; + }; + }; + + ts_reset_l: ts-reset-l { + pinmux { + pins = "gpio118"; + function = "gpio"; + }; + + pinconf { + pins = "gpio118"; + bias-disable; + drive-strength = <2>; + }; + }; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + ap_suspend_l_assert: ap_suspend_l_assert { + config { + pins = "gpio126"; + function = "gpio"; + bias-no-pull; + drive-strength = <2>; + output-low; + }; + }; + + ap_suspend_l_deassert: ap_suspend_l_deassert { + config { + pins = "gpio126"; + function = "gpio"; + bias-no-pull; + drive-strength = <2>; + output-high; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts new file mode 100644 index 000000000000..71bd717a4251 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019, Linaro Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/ { + model = "Thundercomm Dragonboard 845c"; + compatible = "thundercomm,db845c", "qcom,sdm845"; + + aliases { + serial0 = &uart9; + hsuart0 = &uart6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dc12v: dc12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "DC12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + gpio_keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin_a>; + + vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + user4 { + label = "green:user4"; + gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "panic-indicator"; + default-state = "off"; + }; + + wlan { + label = "yellow:wlan"; + gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt { + label = "blue:bt"; + gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; + + lt9611_1v8: lt9611-vdd18-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V8"; + + vin-supply = <&vdc_5v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lt9611_3v3: lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + // TODO: make it possible to drive same GPIO from two clients + // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + // enable-active-high; + }; + + pcie0_1p05v: pcie-0-1p05v-regulator { + compatible = "regulator-fixed"; + regulator-name = "PCIE0_1.05V"; + + vin-supply = <&vbat>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + + // TODO: make it possible to drive same GPIO from two clients + // gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; + // enable-active-high; + }; + + pcie0_3p3v_dual: vldo-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VLDO_3V3"; + + vin-supply = <&vbat>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pwren_state>; + }; + + v5p0_hdmiout: v5p0-hdmiout-regulator { + compatible = "regulator-fixed"; + regulator-name = "V5P0_HDMIOUT"; + + vin-supply = <&vdc_5v>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + + // TODO: make it possible to drive same GPIO from two clients + // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + // enable-active-high; + }; + + vbat: vbat-regulator { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + + vin-supply = <&dc12v>; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + }; + + vbat_som: vbat-som-regulator { + compatible = "regulator-fixed"; + regulator-name = "VBAT_SOM"; + + vin-supply = <&dc12v>; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + }; + + vdc_3v3: vdc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDC_3V3"; + vin-supply = <&dc12v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdc_5v: vdc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDC_5V"; + + vin-supply = <&dc12v>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + regulator-always-on; + }; + + vreg_s4a_1p8: vreg-s4a-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + + vin-supply = <&vbat_som>; + }; +}; + +&adsp_pas { + status = "okay"; + + firmware-name = "qcom/db845c/adsp.mdt"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-bypass; + }; + }; +}; + +&cdsp_pas { + status = "okay"; + firmware-name = "qcom/db845c/cdsp.mdt"; +}; + +&gcc { + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>; +}; + +&pm8998_gpio { + vol_up_pin_a: vol-up-active { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + }; +}; + +&pm8998_pon { + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_VOLUMEDOWN>; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + bus-width = <4>; + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; +}; + +&tlmm { + pcie0_pwren_state: pcie0-pwren { + pins = "gpio90"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdc2_default_state: sdc2-default { + clk { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + */ + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_card_det_n: sd-card-det-n { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&uart9 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; +}; + +&ufs_mem_hc { + status = "okay"; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <800000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ + +&qup_uart6_default { + pinmux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + cts { + pins = "gpio45"; + bias-disable; + }; + + rts-tx { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio48"; + bias-pull-up; + }; +}; + +&qup_uart9_default { + pinconf-tx { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 02b8357c8ce8..2e78638eb73b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -404,8 +404,8 @@ }; &usb_1_dwc3 { - /* Until we have Type C hooked up we'll force this as host. */ - dr_mode = "host"; + /* Until we have Type C hooked up we'll force this as peripheral. */ + dr_mode = "peripheral"; }; &usb_1_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index fcb93300ca62..4babff5f19b5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -190,6 +190,9 @@ compatible = "qcom,kryo385"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <607>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -208,6 +211,9 @@ compatible = "qcom,kryo385"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <607>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -223,6 +229,9 @@ compatible = "qcom,kryo385"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <607>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -238,6 +247,9 @@ compatible = "qcom,kryo385"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <607>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -254,6 +266,9 @@ reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_400>; @@ -269,6 +284,9 @@ reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_500>; @@ -284,6 +302,9 @@ reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_600>; @@ -299,6 +320,9 @@ reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_700>; @@ -325,26 +349,78 @@ core3 { cpu = <&CPU3>; }; - }; - cluster1 { - core0 { + core4 { cpu = <&CPU4>; }; - core1 { + core5 { cpu = <&CPU5>; }; - core2 { + core6 { cpu = <&CPU6>; }; - core3 { + core7 { cpu = <&CPU7>; }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <350>; + exit-latency-us = <461>; + min-residency-us = <1890>; + local-timer-stop; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <360>; + exit-latency-us = <531>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <264>; + exit-latency-us = <621>; + min-residency-us = <952>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "cluster-power-down"; + arm,psci-suspend-param = <0x400000F4>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; }; pmu { @@ -1671,6 +1747,64 @@ }; }; + mss_pil: remoteproc@4080000 { + compatible = "qcom,sdm845-mss-pil"; + reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = + <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_PRNG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "prng", "xo"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + + power-domains = <&aoss_qmp 2>, + <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>, + <&rpmhpd SDM845_MSS>; + power-domain-names = "load_state", "cx", "mx", "mss"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + glink-edge { + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; reg = <0 0x05090000 0 0x9000>; @@ -2106,6 +2240,133 @@ }; }; + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + zap-shader { + memory-region = <&gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-414000000 { + opp-hz = /bits/ 64 <414000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x5040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + + reg = <0 0x506a000 0 0x30000>, + <0 0xb280000 0 0x10000>, + <0 0xb480000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0 0x0af00000 0 0x10000>; @@ -2142,6 +2403,16 @@ #reset-cells = <1>; }; + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 6cde526547e4..42b74c283289 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb +dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi new file mode 100644 index 000000000000..3311a982fff8 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2[MN] main board common parts + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + hdmi0-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; + }; + + led1 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + + led2 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + + led3 { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + x302_clk: x302-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x304_clk: x304-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&gpio6 { + usb1-reset { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-low; + line-name = "usb1-reset"; + }; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + versaclock5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x304_clk>; + clock-names = "xin"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; + function = "sdhi3"; + power-source = <1800>; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + mux { + groups = "usb1"; + function = "usb1"; + }; + + ovc { + pins = "GP_6_27"; + bias-pull-up; + }; + }; + + usb30_pins: usb30 { + groups = "usb30"; + function = "usb30"; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; +}; + +&usb_extal_clk { + clock-frequency = <50000000>; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb3_peri0 { + phys = <&usb3_phy0>; + phy-names = "usb"; + + companion = <&xhci0>; + + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3s0_clk { + clock-frequency = <100000000>; +}; + +&xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi new file mode 100644 index 000000000000..07a6eeaed12e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/G2[MN] HiHope sub board common parts + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +/ { + aliases { + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; +}; + +&pciec0 { + status = "okay"; +}; + +&pciec1 { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts new file mode 100644 index 000000000000..6e33a3b27706 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M sub board + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +#include "r8a774a1-hihope-rzg2m.dts" +#include "hihope-rzg2-ex.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2M with sub board"; + compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", + "renesas,r8a774a1"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts new file mode 100644 index 000000000000..93ca973c856c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M main board + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774a1.dtsi" +#include "hihope-common.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2M main board based on r8a774a1"; + compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index de282c4794ed..f209457c7807 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -56,10 +56,78 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a57_0>; + }; + core1 { + cpu = <&a57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a53_0>; + }; + core1 { + cpu = <&a53_1>; + }; + core2 { + cpu = <&a53_2>; + }; + core3 { + cpu = <&a53_3>; + }; + }; + }; + a57_0: cpu@0 { compatible = "arm,cortex-a57"; reg = <0x0>; @@ -67,7 +135,11 @@ power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; }; a57_1: cpu@1 { @@ -78,6 +150,9 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; }; a53_0: cpu@100 { @@ -87,7 +162,11 @@ power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; a53_1: cpu@101 { @@ -98,6 +177,8 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; a53_2: cpu@102 { @@ -108,6 +189,8 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; a53_3: cpu@103 { @@ -118,6 +201,8 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; L2_CA57: cache-controller-0 { @@ -326,6 +411,76 @@ reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a774a1-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a774a1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a774a1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a774a1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a774a1-cpg-mssr"; reg = <0 0xe6150000 0 0x0bb0>; @@ -377,6 +532,71 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; @@ -601,15 +821,15 @@ "renesas,rcar-gen3-usbhs"; reg = <0 0xe6590000 0 0x200>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 704>; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; renesas,buswait = <11>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 3>; phy-names = "usb"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 704>; + resets = <&cpg 704>, <&cpg 703>; status = "disabled"; }; @@ -686,6 +906,14 @@ resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7300000 { @@ -720,6 +948,14 @@ resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; }; dmac2: dma-controller@e7310000 { @@ -754,6 +990,14 @@ resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; ipmmu_ds0: mmu@e6740000 { @@ -869,6 +1113,7 @@ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1629,6 +1874,14 @@ resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, + <&ipmmu_mp 2>, <&ipmmu_mp 3>, + <&ipmmu_mp 4>, <&ipmmu_mp 5>, + <&ipmmu_mp 6>, <&ipmmu_mp 7>, + <&ipmmu_mp 8>, <&ipmmu_mp 9>, + <&ipmmu_mp 10>, <&ipmmu_mp 11>, + <&ipmmu_mp 12>, <&ipmmu_mp 13>, + <&ipmmu_mp 14>, <&ipmmu_mp 15>; }; audma1: dma-controller@ec720000 { @@ -1663,6 +1916,14 @@ resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, + <&ipmmu_mp 18>, <&ipmmu_mp 19>, + <&ipmmu_mp 20>, <&ipmmu_mp 21>, + <&ipmmu_mp 22>, <&ipmmu_mp 23>, + <&ipmmu_mp 24>, <&ipmmu_mp 25>, + <&ipmmu_mp 26>, <&ipmmu_mp 27>, + <&ipmmu_mp 28>, <&ipmmu_mp 29>, + <&ipmmu_mp 30>, <&ipmmu_mp 31>; }; xhci0: usb@ee000000 { @@ -1691,11 +1952,11 @@ compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; phy-names = "usb"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; }; @@ -1704,7 +1965,7 @@ reg = <0 0xee0a0000 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; + phys = <&usb2_phy1 1>; phy-names = "usb"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 702>; @@ -1715,12 +1976,12 @@ compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; }; @@ -1729,7 +1990,7 @@ reg = <0 0xee0a0100 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; + phys = <&usb2_phy1 2>; phy-names = "usb"; companion = <&ohci1>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -1742,10 +2003,10 @@ "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 703>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>; - #phy-cells = <0>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; status = "disabled"; }; @@ -1756,7 +2017,7 @@ clocks = <&cpg CPG_MOD 702>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 702>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -1825,6 +2086,70 @@ resets = <&cpg 408>; }; + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774a1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774a1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; @@ -1877,6 +2202,61 @@ iommus = <&ipmmu_vc0 19>; }; + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x5000>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 621>; + + renesas,fcp = <&fcpvd2>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + csi20: csi2@fea80000 { compatible = "renesas,r8a774a1-csi2"; reg = <0 0xfea80000 0 0x10000>; @@ -1988,6 +2368,101 @@ }; }; + hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a774a1-hdmi", + "renesas,rcar-gen3-hdmi"; + reg = <0 0xfead0000 0 0x10000>; + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A774A1_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; + }; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a774a1"; + reg = <0 0xfeb00000 0 0x70000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>; + clock-names = "du.0", "du.1", "du.2"; + status = "disabled"; + + vsps = <&vspd0 &vspd1 &vspd2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a774a1-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; @@ -1999,6 +2474,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; + sustainable-power = <3874>; trips { sensor1_crit: sensor1-crit { @@ -2013,6 +2489,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; + sustainable-power = <3874>; trips { sensor2_crit: sensor2-crit { @@ -2021,21 +2498,39 @@ type = "critical"; }; }; - }; sensor_thermal3: sensor-thermal3 { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; + sustainable-power = <3874>; trips { + target: trip-point1 { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + sensor3_crit: sensor3-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 0 2>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index 013a48c01211..46a77eefa536 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r8a774c0.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/display/tda998x.h> / { model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; @@ -15,13 +16,25 @@ aliases { serial0 = &scif2; + serial1 = &hscif2; }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&tda19988_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -52,6 +65,23 @@ reg = <0x0 0x48000000 0x0 0x78000000>; }; + sound: sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "CAT874 HDMI sound"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&tda19988>; + }; + }; + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; @@ -74,6 +104,46 @@ states = <3300000 1 1800000 0>; }; + + wlan_en_reg: fixedregulator { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <70000>; + + gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + x13_clk: x13 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&x13_clk>; + clock-names = "du.0", "du.1", "dclkin.0"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&tda19988_in>; + }; + }; + }; }; &ehci0 { @@ -85,6 +155,81 @@ clock-frequency = <48000000>; }; +&hscif2 { + pinctrl-0 = <&hscif2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + hd3ss3220@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + interrupt-parent = <&gpio6>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + hd3ss3220_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; + }; + + tda19988: tda19988@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + + video-ports = <0x234501>; + + #sound-dai-cells = <0>; + audio-ports = <TDA998x_I2S 0x03>; + clocks = <&rcar_sound 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tda19988_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + tda19988_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; @@ -98,6 +243,13 @@ }; }; +&lvds0 { + status = "okay"; + + clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; + clock-names = "fck", "dclkin.0", "extal"; +}; + &ohci0 { dr_mode = "host"; status = "okay"; @@ -113,11 +265,22 @@ }; &pfc { + du_pins: du { + groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp", + "du_clk_in_0"; + function = "du"; + }; + i2c1_pins: i2c1 { groups = "i2c1_b"; function = "i2c1"; }; + hscif2_pins: hscif2 { + groups = "hscif2_data_a", "hscif2_ctrl_a"; + function = "hscif2"; + }; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; @@ -134,6 +297,47 @@ function = "sdhi0"; power-source = <1800>; }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clkout1_a"; + function = "audio_clk"; + }; + + usb30_pins: usb30 { + groups = "usb30", "usb30_id"; + function = "usb30"; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <11289600>; + + status = "okay"; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src0 &dvc0>; + }; + }; }; &rwdt { @@ -162,7 +366,47 @@ status = "okay"; }; +&sdhi3 { + status = "okay"; + pinctrl-0 = <&sdhi3_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + &usb2_phy0 { renesas,no-otg-pins; status = "okay"; }; + +&usb3_peri0 { + companion = <&xhci0>; + status = "okay"; + usb-role-switch; + + port { + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_ep>; + }; + }; +}; + +&xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 3f86db199dbf..e7b5bf23f978 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -70,7 +70,7 @@ #size-cells = <0>; a53_0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; @@ -81,7 +81,7 @@ }; a53_1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <1>; device_type = "cpu"; power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; @@ -684,7 +684,7 @@ <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; renesas,buswait = <11>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 3>; phy-names = "usb"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 704>, <&cpg 703>; @@ -1580,7 +1580,7 @@ reg = <0 0xee080000 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 1>; phy-names = "usb"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; @@ -1592,7 +1592,7 @@ reg = <0 0xee080100 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -1608,7 +1608,7 @@ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 097538cc4b1f..1745ac4b307e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -155,6 +155,7 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -207,6 +208,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -812,7 +815,7 @@ <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; renesas,buswait = <11>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 3>; phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 704>, <&cpg 703>; @@ -829,7 +832,7 @@ <&usb_dmac3 0>, <&usb_dmac3 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; renesas,buswait = <11>; - phys = <&usb2_phy3>; + phys = <&usb2_phy3 3>; phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 705>, <&cpg 700>; @@ -1450,6 +1453,17 @@ status = "disabled"; }; + tpu: pwm@e6e80000 { + compatible = "renesas,tpu-r8a7795", "renesas,tpu"; + reg = <0 0xe6e80000 0 0x148>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a7795", "renesas,rcar-gen3-msiof"; @@ -2405,7 +2419,7 @@ reg = <0 0xee080000 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 1>; phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; @@ -2417,7 +2431,7 @@ reg = <0 0xee0a0000 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; + phys = <&usb2_phy1 1>; phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 702>; @@ -2429,7 +2443,7 @@ reg = <0 0xee0c0000 0 0x100>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2>; + phys = <&usb2_phy2 1>; phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 701>; @@ -2441,7 +2455,7 @@ reg = <0 0xee0e0000 0 0x100>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - phys = <&usb2_phy3>; + phys = <&usb2_phy3 1>; phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 700>, <&cpg 705>; @@ -2453,7 +2467,7 @@ reg = <0 0xee080100 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2466,7 +2480,7 @@ reg = <0 0xee0a0100 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; + phys = <&usb2_phy1 2>; phy-names = "usb"; companion = <&ohci1>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2479,7 +2493,7 @@ reg = <0 0xee0c0100 0 0x100>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2>; + phys = <&usb2_phy2 2>; phy-names = "usb"; companion = <&ohci2>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2492,7 +2506,7 @@ reg = <0 0xee0e0100 0 0x100>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - phys = <&usb2_phy3>; + phys = <&usb2_phy3 2>; phy-names = "usb"; companion = <&ohci3>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2508,7 +2522,7 @@ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -2519,7 +2533,7 @@ clocks = <&cpg CPG_MOD 702>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 702>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -2530,7 +2544,7 @@ clocks = <&cpg CPG_MOD 701>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 701>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -2542,7 +2556,7 @@ clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 700>, <&cpg 705>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -3168,58 +3182,30 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; + sustainable-power = <6313>; trips { - sensor1_passive: sensor1-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&sensor1_passive>; - cooling-device = <&a57_0 4 4>, - <&a57_1 4 4>, - <&a57_2 4 4>, - <&a57_3 4 4>; - }; - }; }; sensor_thermal2: sensor-thermal2 { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; + sustainable-power = <6313>; trips { - sensor2_passive: sensor2-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; sensor2_crit: sensor2-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&sensor2_passive>; - cooling-device = <&a57_0 4 4>, - <&a57_1 4 4>, - <&a57_2 4 4>, - <&a57_3 4 4>; - }; - }; }; sensor_thermal3: sensor-thermal3 { @@ -3228,11 +3214,12 @@ thermal-sensors = <&tsc 2>; trips { - sensor3_passive: sensor3-passive { - temperature = <95000>; + target: trip-point1 { + temperature = <100000>; hysteresis = <1000>; type = "passive"; }; + sensor3_crit: sensor3-crit { temperature = <120000>; hysteresis = <1000>; @@ -3242,11 +3229,15 @@ cooling-maps { map0 { - trip = <&sensor3_passive>; - cooling-device = <&a57_0 4 4>, - <&a57_1 4 4>, - <&a57_2 4 4>, - <&a57_3 4 4>; + trip = <&target>; + cooling-device = <&a57_0 2 4>; + contribution = <1024>; + }; + + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index d5e2f4af83a4..26df5b88efd7 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -160,6 +160,7 @@ power-domains = <&sysc R8A7796_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -186,6 +187,8 @@ power-domains = <&sysc R8A7796_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -783,7 +786,7 @@ <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; renesas,buswait = <11>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 3>; phy-names = "usb"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 704>, <&cpg 703>; @@ -1319,6 +1322,17 @@ status = "disabled"; }; + tpu: pwm@e6e80000 { + compatible = "renesas,tpu-r8a7796", "renesas,tpu"; + reg = <0 0xe6e80000 0 0x148>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a7796", "renesas,rcar-gen3-msiof"; @@ -2275,7 +2289,7 @@ reg = <0 0xee080000 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 1>; phy-names = "usb"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; @@ -2287,7 +2301,7 @@ reg = <0 0xee0a0000 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; + phys = <&usb2_phy1 1>; phy-names = "usb"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 702>; @@ -2299,7 +2313,7 @@ reg = <0 0xee080100 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -2312,7 +2326,7 @@ reg = <0 0xee0a0100 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; + phys = <&usb2_phy1 2>; phy-names = "usb"; companion = <&ohci1>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -2328,7 +2342,7 @@ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -2339,7 +2353,7 @@ clocks = <&cpg CPG_MOD 702>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 702>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -2814,76 +2828,61 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; + sustainable-power = <3874>; trips { - sensor1_passive: sensor1-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&sensor1_passive>; - cooling-device = <&a57_0 5 5>, <&a57_1 5 5>; - }; - }; }; sensor_thermal2: sensor-thermal2 { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; + sustainable-power = <3874>; trips { - sensor2_passive: sensor2-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; sensor2_crit: sensor2-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&sensor2_passive>; - cooling-device = <&a57_0 5 5>, <&a57_1 5 5>; - }; - }; }; sensor_thermal3: sensor-thermal3 { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; + sustainable-power = <3874>; trips { - sensor3_passive: sensor3-passive { - temperature = <95000>; + target: trip-point1 { + temperature = <100000>; hysteresis = <1000>; type = "passive"; }; + sensor3_crit: sensor3-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; - cooling-maps { map0 { - trip = <&sensor3_passive>; - cooling-device = <&a57_0 5 5>, <&a57_1 5 5>; + trip = <&target>; + cooling-device = <&a57_0 2 4>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 2554b1742dbf..131f895ab778 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -111,6 +111,8 @@ power-domains = <&sysc R8A77965_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; operating-points-v2 = <&cluster0_opp>; }; @@ -667,7 +669,7 @@ <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; renesas,buswait = <11>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 3>; phy-names = "usb"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 704>, <&cpg 703>; @@ -1195,6 +1197,17 @@ status = "disabled"; }; + tpu: pwm@e6e80000 { + compatible = "renesas,tpu-r8a77965", "renesas,tpu"; + reg = <0 0xe6e80000 0 0x148>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a77965", "renesas,rcar-gen3-msiof"; @@ -2015,7 +2028,7 @@ reg = <0 0xee080000 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 1>; phy-names = "usb"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; @@ -2027,7 +2040,7 @@ reg = <0 0xee0a0000 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; + phys = <&usb2_phy1 1>; phy-names = "usb"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 702>; @@ -2039,7 +2052,7 @@ reg = <0 0xee080100 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -2052,7 +2065,7 @@ reg = <0 0xee0a0100 0 0x100>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; + phys = <&usb2_phy1 2>; phy-names = "usb"; companion = <&ohci1>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -2068,7 +2081,7 @@ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -2079,7 +2092,7 @@ clocks = <&cpg CPG_MOD 702>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 702>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -2519,6 +2532,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; + sustainable-power = <2439>; trips { sensor1_crit: sensor1-crit { @@ -2533,6 +2547,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; + sustainable-power = <2439>; trips { sensor2_crit: sensor2-crit { @@ -2547,14 +2562,30 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; + sustainable-power = <2439>; trips { + target: trip-point1 { + /* miliCelsius */ + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + sensor3_crit: sensor3-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 2 4>; + contribution = <1024>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index b6d53321576b..233f26fbec17 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -19,7 +19,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index c72772589953..83fc13ac3fa1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -19,7 +19,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; @@ -262,7 +262,6 @@ &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; - renesas,no-ether-link; phy-handle = <&phy0>; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 56cb566ffa09..b4318661f35e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -84,9 +84,11 @@ compatible = "arm,cortex-a53"; reg = <0>; device_type = "cpu"; + #cooling-cells = <2>; power-domains = <&sysc R8A77990_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + dynamic-power-coefficient = <277>; clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -630,7 +632,7 @@ <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; renesas,buswait = <11>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 3>; phy-names = "usb"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 704>, <&cpg 703>; @@ -1537,7 +1539,7 @@ reg = <0 0xee080000 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 1>; phy-names = "usb"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; @@ -1549,7 +1551,7 @@ reg = <0 0xee080100 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -1565,7 +1567,7 @@ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -1758,7 +1760,7 @@ du: display@feb00000 { compatible = "renesas,du-r8a77990"; - reg = <0 0xfeb00000 0 0x80000>; + reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 724>, @@ -1801,6 +1803,8 @@ resets = <&cpg 727>; status = "disabled"; + renesas,companion = <&lvds1>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1856,11 +1860,18 @@ thermal-zones { cpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&thermal>; + polling-delay = <0>; + thermal-sensors = <&thermal 0>; + sustainable-power = <717>; trips { - cpu-crit { + target: trip-point1 { + temperature = <100000>; + hysteresis = <2000>; + type = "passive"; + }; + + sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; @@ -1868,6 +1879,11 @@ }; cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index a7dc11e36fd9..0711170b26b1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; @@ -511,12 +511,7 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - + port { vin4_in: endpoint { remote-endpoint = <&adv7180_out>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 5bf3af246e14..0a344eb55094 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -354,7 +354,7 @@ <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; renesas,buswait = <11>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 3>; phy-names = "usb"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 704>, <&cpg 703>; @@ -875,7 +875,7 @@ reg = <0 0xee080000 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 1>; phy-names = "usb"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; @@ -887,7 +887,7 @@ reg = <0 0xee080100 0 0x100>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0>; + phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -903,7 +903,7 @@ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <0>; + #phy-cells = <1>; status = "disabled"; }; @@ -1038,6 +1038,8 @@ resets = <&cpg 727>; status = "disabled"; + renesas,companion = <&lvds1>; + ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 2dba1328acfa..5c2c84723ec5 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -39,7 +39,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 7a09576b3112..27851a77f538 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -38,6 +38,18 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + wlan_en: regulator-wlan_en { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_exp_74 4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; }; &can0 { @@ -88,6 +100,13 @@ line-name = "Audio_Out_OFF"; }; + sd-wifi-mux { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; /* Connect WL1837 */ + line-name = "SD WiFi mux"; + }; + hub_pwen { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; @@ -254,6 +273,12 @@ function = "scif1"; }; + sdhi3_pins: sdhi3 { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <3300>; + }; + usb0_pins: usb0 { groups = "usb0"; function = "usb0"; @@ -273,6 +298,30 @@ status = "okay"; }; +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&wlan_en>; + vqmmc-supply = <&wlan_en>; + bus-width = <4>; + no-1-8-v; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + max-frequency = <26000000>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + }; +}; + &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index e70e1bac2be4..7e498b46e9ae 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -26,7 +26,7 @@ }; chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 5f2687acbf94..daa2c78e22c3 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -16,6 +16,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index 5d499c9086fb..bb40c163b05d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -141,10 +141,12 @@ phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmiim1_pins>; - snps,force_thresh_dma_mode; + snps,aal; snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; + snps,rxpbl = <0x4>; + snps,txpbl = <0x4>; tx_delay = <0x24>; rx_delay = <0x18>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 994468671b19..e9fefd8a7e02 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -407,6 +407,7 @@ compatible = "snps,dw-wdt"; reg = <0x0 0xff1a0000 0x0 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_WDT>; }; pwm0: pwm@ff1b0000 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts index 6b059bd7a04f..ebe2ee77ba1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts @@ -146,6 +146,12 @@ }; }; +&spi1 { + /* On both Low speed and High speed expansion */ + cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>; + status = "okay"; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts new file mode 100644 index 000000000000..0d1f5f9a0de9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/dts-v1/; +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/input/input.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Hugsun X99 TV BOX"; + compatible = "hugsun,x99", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + dc_5v: dc-5v { + compatible = "regulator-fixed"; + regulator-name = "dc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&dc_5v>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc1v8_s0: vcc1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_5v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-initial-mode = <1>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rtc_clko_wifi"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v0_sd: LDO_REG5 { + regulator-name = "vcc3v0_sd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <40>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + status = "okay"; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + audio-supply = <&vcc1v8_s0>; + bt656-supply = <&vcc1v8_s0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sd>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pinctrl { + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gmac { + rgmii_sleep_pins: rgmii-sleep-pins { + rockchip,pins = + <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + /* external pullup to VCC1V8_PMUPLL */ + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg_on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&saradc { + vref-supply = <&vcc1v8_s0>; + status = "okay"; +}; + +&sdmmc { + clock-frequency = <150000000>; + clock-freq-min-max = <200000 150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + card-detect-delay = <800>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + supports-emmc; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&spdif { + status = "okay"; + pinctrl-0 = <&spdif_bus_1>; + #sound-dai-cells = <0>; +}; + +&spi1 { + status = "okay"; + max-freq = <10000000>; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + rockchip,hw-tshut-temp = <110000>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; + + u2phy0_otg: otg-port { + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; + + u2phy1_otg: otg-port { + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-captain.dts b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-captain.dts new file mode 100644 index 000000000000..8302e51def52 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-captain.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge-Captain"; + compatible = "khadas,edge-captain", "rockchip,rk3399"; +}; + +&gmac { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-v.dts b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-v.dts new file mode 100644 index 000000000000..f5dcb99dc349 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-v.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge-V"; + compatible = "khadas,edge-v", "rockchip,rk3399"; +}; + +&gmac { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dts b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dts new file mode 100644 index 000000000000..31616e7ad89d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge"; + compatible = "khadas,edge", "rockchip,rk3399"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi new file mode 100644 index 000000000000..4944d78a0a1c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi @@ -0,0 +1,804 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vsys_5v0>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vsys_3v3>; + }; + + vsys: vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: vsys-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys>; + }; + + vsys_5v0: vsys-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vsys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <18000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_gpio>, <&user_led_gpio>; + + sys-led { + label = "sys_led"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + user-led { + label = "user_led"; + default-state = "off"; + gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 150 200 255>; + #cooling-cells = <2>; + fan-supply = <&vsys_5v0>; + pwms = <&pwm0 0 40000 0>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_thermal { + trips { + gpu_warm: gpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + gpu_hot: gpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&gpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map2 { + trip = <&gpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vsys_3v3>; + vcc2-supply = <&vsys_3v3>; + vcc3-supply = <&vsys_3v3>; + vcc4-supply = <&vsys_3v3>; + vcc6-supply = <&vsys_3v3>; + vcc7-supply = <&vsys_3v3>; + vcc8-supply = <&vsys_3v3>; + vcc9-supply = <&vsys_3v3>; + vcc10-supply = <&vsys_3v3>; + vcc11-supply = <&vsys_3v3>; + vcc12-supply = <&vsys_3v3>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_apio2: LDO_REG1 { + regulator-name = "vcc1v8_apio2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_vldo2: LDO_REG2 { + regulator-name = "vcc_vldo2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-name = "vcc1v8_pmupll"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_vldo5: LDO_REG5 { + regulator-name = "vcc_vldo5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc1v8_codec: LDO_REG7 { + regulator-name = "vcc1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsys_3v3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsys_3v3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc1v8_apio2>; + audio-supply = <&vcc1v8_codec>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + sys_led_gpio: sys_led-gpio { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led_gpio: user_led-gpio { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdio0 { + /* WiFi & BT combo module Ampak AP6356S */ + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + vqmmc-supply = <&vcc1v8_s3>; + vmmc-supply = <&vccio_sd>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vsys_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts index e030627159c6..1ae1ebd4efdd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts @@ -25,6 +25,15 @@ #clock-cells = <0>; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + vcc12v_dcin: dc-12v { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -169,6 +178,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; @@ -451,12 +464,46 @@ }; &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + sdio0 { + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + <2 20 RK_FUNC_1 &pcfg_pull_up_20ma>, + <2 21 RK_FUNC_1 &pcfg_pull_up_20ma>, + <2 22 RK_FUNC_1 &pcfg_pull_up_20ma>, + <2 23 RK_FUNC_1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = + <2 24 RK_FUNC_1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = + <2 25 RK_FUNC_1 &pcfg_pull_none_20ma>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -482,6 +529,17 @@ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm2 { @@ -494,6 +552,32 @@ vref-supply = <&vcc_1v8>; }; +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; @@ -557,6 +641,23 @@ }; }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts index 12285c51cceb..437a75f31ad4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts @@ -114,6 +114,55 @@ }; }; +&spi0 { + /* On Low speed expansion (LS-SPI0) */ + status = "okay"; +}; + +&spi4 { + /* On High speed expansion (HS-SPI1) */ + status = "okay"; +}; + +&thermal_zones { + cpu_thermal: cpu { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&tsadc 0>; + sustainable-power = <1550>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <65000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + + trip = <&cpu_alert1>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + &usbdrd_dwc3_0 { dr_mode = "otg"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index 20ec7d1c25d7..eb5594062006 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -513,6 +513,20 @@ gpio1830-supply = <&vcc_3v0>; }; +&pcie0 { + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_perst>; + vpcie12v-supply = <&vcc12v_dcin>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + &pmu_io_domains { pmu1830-supply = <&vcc_3v0>; status = "okay"; @@ -542,6 +556,10 @@ }; pcie { + pcie_perst: pcie-perst { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 04623e52ac5d..1bc1579674e5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -565,12 +565,11 @@ status = "okay"; u2phy0_otg: otg-port { - phy-supply = <&vcc5v0_typec0>; status = "okay"; }; u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; + phy-supply = <&vcc5v0_typec0>; status = "okay"; }; }; @@ -620,7 +619,7 @@ &usbdrd_dwc3_0 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &usbdrd3_1 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 196ac9b78076..cede1ad81be2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -414,6 +414,9 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, + <&cru SCLK_USB3OTG0_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; dr_mode = "otg"; phys = <&u2phy0_otg>, <&tcphy0_usb3>; phy-names = "usb2-phy", "usb3-phy"; @@ -447,6 +450,9 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, + <&cru SCLK_USB3OTG1_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; dr_mode = "otg"; phys = <&u2phy1_otg>, <&tcphy1_usb3>; phy-names = "usb2-phy", "usb3-phy"; @@ -821,15 +827,6 @@ type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; }; @@ -1706,11 +1703,11 @@ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "isp0_mmu"; - clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; + clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>; + power-domains = <&power RK3399_PD_ISP0>; rockchip,disable-mmu-reset; - status = "disabled"; }; isp1_mmu: iommu@ff924000 { @@ -1718,11 +1715,11 @@ reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "isp1_mmu"; - clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; + clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>; + power-domains = <&power RK3399_PD_ISP1>; rockchip,disable-mmu-reset; - status = "disabled"; }; hdmi_sound: hdmi-sound { diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi new file mode 100644 index 000000000000..bb5ebf6608b9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + +#include "rk3399.dtsi" + +/ { + compatible = "rockchip,rk3399pro"; +}; + +/* Default to enabled since AP talk to NPU part over pcie */ +&pcie_phy { + status = "okay"; +}; + +/* Default to enabled since AP talk to NPU part over pcie */ +&pcie0 { + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts index 7968d524351b..f72f048a0c9d 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts @@ -163,4 +163,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index a3cd475b48d2..8ec40a0b8b1e 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -8,8 +8,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/uniphier-gpio.h> -/memreserve/ 0x80000000 0x02000000; - / { compatible = "socionext,uniphier-ld11"; #address-cells = <2>; @@ -110,6 +108,17 @@ <1 10 4>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-memory@81000000 { + reg = <0x0 0x81000000 0x0 0x01000000>; + no-map; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -617,6 +626,8 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 017f6328c191..b658f2b641e2 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -9,8 +9,6 @@ #include <dt-bindings/gpio/uniphier-gpio.h> #include <dt-bindings/thermal/thermal.h> -/memreserve/ 0x80000000 0x02000000; - / { compatible = "socionext,uniphier-ld20"; #address-cells = <2>; @@ -215,6 +213,17 @@ }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-memory@81000000 { + reg = <0x0 0x81000000 0x0 0x01000000>; + no-map; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -921,6 +930,8 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index 1965e4dfe4a4..754315bbd1c8 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -115,4 +115,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index bb97abe1a55f..d6f6cee4d549 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -8,8 +8,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/uniphier-gpio.h> -/memreserve/ 0x80000000 0x02000000; - / { compatible = "socionext,uniphier-pxs3"; #address-cells = <2>; @@ -138,6 +136,17 @@ <1 10 4>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-memory@81000000 { + reg = <0x0 0x81000000 0x0 0x01000000>; + no-map; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -779,6 +788,8 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi index 286d7173f94f..231436be0e3f 100644 --- a/arch/arm64/boot/dts/sprd/sc9836.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi @@ -60,7 +60,7 @@ }; funnel@10001000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x10001000 0 0x1000>; clocks = <&clk26mhz>; clock-names = "apb_pclk"; diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index b25d19977170..e27eb3ed1d47 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -300,7 +300,7 @@ }; funnel@10001000 { /* SoC Funnel */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x10001000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; @@ -367,7 +367,7 @@ }; funnel@11001000 { /* Cluster0 Funnel */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x11001000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; @@ -415,7 +415,7 @@ }; funnel@11002000 { /* Cluster1 Funnel */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x11002000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; @@ -513,7 +513,7 @@ }; funnel@11005000 { /* Main Funnel */ - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x11005000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index 4bb862c6b083..79b9591c37aa 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -130,6 +130,34 @@ clock-names = "enable"; clocks = <&apahb_gate CLK_DMA_EB>; }; + + sdio3: sdio@50430000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x50430000 0 0x1000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + + clock-names = "sdio", "enable", "2x_enable"; + clocks = <&aon_prediv CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>, + <&aon_gate CLK_EMMC_2X_EN>; + assigned-clocks = <&aon_prediv CLK_EMMC_2X>; + assigned-clock-parents = <&clk_l0_409m6>; + + sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; + sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; + sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; + sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; + vmmc-supply = <&vddemmccore>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + mmc-hs400-enhanced-strobe; + mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + }; }; aon { @@ -272,4 +300,11 @@ clock-frequency = <100000000>; clock-output-names = "ext-rco-100m"; }; + + clk_l0_409m6: clk_l0_409m6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <409600000>; + clock-output-names = "ext-409m6"; + }; }; diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 63e619d0b5b8..b397945fdf73 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -7,3 +7,5 @@ # dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb + +dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 752455269fab..ca70ff73f171 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -4,6 +4,7 @@ * * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ */ +#include <dt-bindings/phy/phy-am654-serdes.h> &cbass_main { msmc_ram: sram@70000000 { @@ -44,6 +45,7 @@ gic_its: gic-its@18200000 { compatible = "arm,gic-v3-its"; reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; msi-controller; #msi-cells = <1>; }; @@ -60,6 +62,36 @@ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; }; + serdes0: serdes@900000 { + compatible = "ti,phy-am654-serdes"; + reg = <0x0 0x900000 0x0 0x2000>; + reg-names = "serdes"; + #phy-cells = <2>; + power-domains = <&k3_pds 153>; + clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; + clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; + ti,serdes-clk = <&serdes0_clk>; + #clock-cells = <1>; + mux-controls = <&serdes_mux 0>; + }; + + serdes1: serdes@910000 { + compatible = "ti,phy-am654-serdes"; + reg = <0x0 0x910000 0x0 0x2000>; + reg-names = "serdes"; + #phy-cells = <2>; + power-domains = <&k3_pds 154>; + clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; + clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; + assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; + ti,serdes-clk = <&serdes1_clk>; + #clock-cells = <1>; + mux-controls = <&serdes_mux 1>; + }; + main_uart0: serial@2800000 { compatible = "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -232,6 +264,38 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; + + pcie0_mode: pcie-mode@4060 { + compatible = "syscon"; + reg = <0x00004060 0x4>; + }; + + pcie1_mode: pcie-mode@4070 { + compatible = "syscon"; + reg = <0x00004070 0x4>; + }; + + pcie_devid: pcie-devid@210 { + compatible = "syscon"; + reg = <0x00000210 0x4>; + }; + + serdes0_clk: serdes_clk@4080 { + compatible = "syscon"; + reg = <0x00004080 0x4>; + }; + + serdes1_clk: serdes_clk@4090 { + compatible = "syscon"; + reg = <0x00004090 0x4>; + }; + + serdes_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ + <0x4090 0x3>; /* SERDES1 lane select */ + }; }; dwc3_0: dwc3@4000000 { @@ -309,4 +373,141 @@ clock-names = "wkupclk", "refclk"; #phy-cells = <0>; }; + + intr_main_gpio: interrupt-controller0 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <2>; + ti,sci = <&dmsc>; + ti,sci-dst-id = <56>; + ti,sci-rm-range-girq = <0x1>; + }; + + cbass_main_navss: interconnect0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + intr_main_navss: interrupt-controller1 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <2>; + ti,sci = <&dmsc>; + ti,sci-dst-id = <56>; + ti,sci-rm-range-girq = <0x0>, <0x2>; + }; + + inta_main_udmass: interrupt-controller@33d00000 { + compatible = "ti,sci-inta"; + reg = <0x0 0x33d00000 0x0 0x100000>; + interrupt-controller; + interrupt-parent = <&intr_main_navss>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <179>; + ti,sci-rm-range-vint = <0x0>; + ti,sci-rm-range-global-event = <0x1>; + }; + }; + + main_gpio0: main_gpio0@600000 { + compatible = "ti,am654-gpio", "ti,keystone-gpio"; + reg = <0x0 0x600000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&intr_main_gpio>; + interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>, + <57 261>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <96>; + ti,davinci-gpio-unbanked = <0>; + clocks = <&k3_clks 57 0>; + clock-names = "gpio"; + }; + + main_gpio1: main_gpio1@601000 { + compatible = "ti,am654-gpio", "ti,keystone-gpio"; + reg = <0x0 0x601000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&intr_main_gpio>; + interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>, + <58 261>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <90>; + ti,davinci-gpio-unbanked = <0>; + clocks = <&k3_clks 58 0>; + clock-names = "gpio"; + }; + + pcie0_rc: pcie@5500000 { + compatible = "ti,am654-pcie-rc"; + reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; + reg-names = "app", "dbics", "config", "atu"; + power-domains = <&k3_pds 120>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 + 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; + ti,syscon-pcie-id = <&pcie_devid>; + ti,syscon-pcie-mode = <&pcie0_mode>; + bus-range = <0x0 0xff>; + num-viewport = <16>; + max-link-speed = <3>; + dma-coherent; + interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + }; + + pcie0_ep: pcie-ep@5500000 { + compatible = "ti,am654-pcie-ep"; + reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; + reg-names = "app", "dbics", "addr_space", "atu"; + power-domains = <&k3_pds 120>; + ti,syscon-pcie-mode = <&pcie0_mode>; + num-ib-windows = <16>; + num-ob-windows = <16>; + max-link-speed = <3>; + dma-coherent; + interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; + }; + + pcie1_rc: pcie@5600000 { + compatible = "ti,am654-pcie-rc"; + reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; + reg-names = "app", "dbics", "config", "atu"; + power-domains = <&k3_pds 121>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 + 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; + ti,syscon-pcie-id = <&pcie_devid>; + ti,syscon-pcie-mode = <&pcie1_mode>; + bus-range = <0x0 0xff>; + num-viewport = <16>; + max-link-speed = <3>; + dma-coherent; + interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; + msi-map = <0x0 &gic_its 0x10000 0x10000>; + }; + + pcie1_ep: pcie-ep@5600000 { + compatible = "ti,am654-pcie-ep"; + reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; + reg-names = "app", "dbics", "addr_space", "atu"; + power-domains = <&k3_pds 121>; + ti,syscon-pcie-mode = <&pcie1_mode>; + num-ib-windows = <16>; + num-ob-windows = <16>; + max-link-speed = <3>; + dma-coherent; + interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 6f7d2b316ded..afc29eaa2638 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -17,6 +17,14 @@ power-domains = <&k3_pds 149>; }; + mcu_ram: sram@41c00000 { + compatible = "mmio-sram"; + reg = <0x00 0x41c00000 0x00 0x80000>; + ranges = <0x0 0x00 0x41c00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + }; + mcu_i2c0: i2c@40b00000 { compatible = "ti,am654-i2c", "ti,omap4-i2c"; reg = <0x0 0x40b00000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 7cbdc0912ab7..9cf2c0849a24 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -7,7 +7,7 @@ &cbass_wakeup { dmsc: dmsc { - compatible = "ti,k2g-sci"; + compatible = "ti,am654-sci"; ti,host-id = <12>; #address-cells = <1>; #size-cells = <1>; @@ -63,4 +63,30 @@ clocks = <&k3_clks 115 1>; power-domains = <&k3_pds 115>; }; + + intr_wkup_gpio: interrupt-controller2 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <2>; + ti,sci = <&dmsc>; + ti,sci-dst-id = <56>; + ti,sci-rm-range-girq = <0x4>; + }; + + wkup_gpio0: wkup_gpio0@42110000 { + compatible = "ti,am654-gpio", "ti,keystone-gpio"; + reg = <0x42110000 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&intr_wkup_gpio>; + interrupts = <59 128>, <59 129>, <59 130>, <59 131>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <56>; + ti,davinci-gpio-unbanked = <0>; + clocks = <&k3_clks 59 0>; + clock-names = "gpio"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 50f4be2047a9..82edf10b2378 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -68,9 +68,14 @@ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ + <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ /* MCUSS Range */ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, @@ -82,6 +87,9 @@ #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index cf1aa276a1ea..52c245d36db9 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-am654.dtsi" +#include <dt-bindings/input/input.h> / { compatible = "ti,am654-evm", "ti,am654"; @@ -33,6 +34,25 @@ no-map; }; }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&push_button_pins_default>; + + sw5 { + label = "GPIO Key USER1"; + linux,code = <BTN_0>; + gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>; + }; + + sw6 { + label = "GPIO Key USER2"; + linux,code = <BTN_1>; + gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; + }; + }; }; &wkup_pmx0 { @@ -42,6 +62,13 @@ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ >; }; + + push_button_pins_default: push_button__pins_default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ + AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ + >; + }; }; &main_pmx0 { @@ -228,3 +255,27 @@ ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; + +&serdes0 { + status = "disabled"; +}; + +&serdes1 { + status = "disabled"; +}; + +&pcie0_rc { + status = "disabled"; +}; + +&pcie0_ep { + status = "disabled"; +}; + +&pcie1_rc { + status = "disabled"; +}; + +&pcie1_ep { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts new file mode 100644 index 000000000000..c680123f067c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721e-som-p0.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; +}; + +&wkup_uart0 { + /* Wakeup UART is used by System firmware */ + status = "disabled"; +}; + +&main_uart3 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart5 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart6 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart7 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart8 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart9 { + /* UART not brought out */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi new file mode 100644 index 000000000000..a01308142f77 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721E SoC Family Main Domain peripherals + * + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&cbass_main { + msmc_ram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x0 0x70000000 0x0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x70000000 0x800000>; + + atf-sram@0 { + reg = <0x0 0x20000>; + }; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01900000 0x00 0x100000>; /* GICR */ + + /* vcpumntirq: virtual CPU interface maintenance interrupt */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: gic-its@18200000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + smmu0: smmu@36600000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x36600000 0x0 0x100000>; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror"; + #iommu-cells = <1>; + }; + + main_gpio_intr: interrupt-controller0 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <2>; + ti,sci = <&dmsc>; + ti,sci-dst-id = <14>; + ti,sci-rm-range-girq = <0x1>; + }; + + cbass_main_navss: interconnect0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + main_navss_intr: interrupt-controller1 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <2>; + ti,sci = <&dmsc>; + ti,sci-dst-id = <14>; + ti,sci-rm-range-girq = <0>, <2>; + }; + + main_udmass_inta: interrupt-controller@33d00000 { + compatible = "ti,sci-inta"; + reg = <0x0 0x33d00000 0x0 0x100000>; + interrupt-controller; + interrupt-parent = <&main_navss_intr>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <209>; + ti,sci-rm-range-vint = <0xa>; + ti,sci-rm-range-global-event = <0xd>; + }; + }; + + secure_proxy_main: mailbox@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x32c00000 0x00 0x100000>, + <0x00 0x32400000 0x00 0x100000>, + <0x00 0x32800000 0x00 0x100000>; + interrupt-names = "rx_011"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + }; + + main_pmx0: pinmux@11c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x0 0x11c000 0x0 0x2b4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 146>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 278>; + clocks = <&k3_clks 278 0>; + clock-names = "fclk"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 279>; + clocks = <&k3_clks 279 0>; + clock-names = "fclk"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 280>; + clocks = <&k3_clks 280 0>; + clock-names = "fclk"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 281>; + clocks = <&k3_clks 281 0>; + clock-names = "fclk"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 282>; + clocks = <&k3_clks 282 0>; + clock-names = "fclk"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 283>; + clocks = <&k3_clks 283 0>; + clock-names = "fclk"; + }; + + main_uart7: serial@2870000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02870000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 284>; + clocks = <&k3_clks 284 0>; + clock-names = "fclk"; + }; + + main_uart8: serial@2880000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02880000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 285>; + clocks = <&k3_clks 285 0>; + clock-names = "fclk"; + }; + + main_uart9: serial@2890000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02890000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 286>; + clocks = <&k3_clks 286 0>; + clock-names = "fclk"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi new file mode 100644 index 000000000000..07b58eeebceb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals + * + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&cbass_mcu_wakeup { + dmsc: dmsc@44083000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + + mbox-names = "rx", "tx"; + + mboxes= <&secure_proxy_main 11>, + <&secure_proxy_main 13>; + + reg-names = "debug_messages"; + reg = <0x00 0x44083000 0x0 0x1000>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <1>; + }; + + k3_clks: clocks { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + wkup_pmx0: pinmux@4301c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c000 0x00 0x178>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + mcu_ram: sram@41c00000 { + compatible = "mmio-sram"; + reg = <0x00 0x41c00000 0x00 0x100000>; + ranges = <0x0 0x00 0x41c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wkup_uart0: serial@42300000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x42300000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 287>; + clocks = <&k3_clks 287 0>; + clock-names = "fclk"; + }; + + mcu_uart0: serial@40a00000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <96000000>; + current-speed = <115200>; + power-domains = <&k3_pds 149>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + }; + + wkup_gpio_intr: interrupt-controller2 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <2>; + ti,sci = <&dmsc>; + ti,sci-dst-id = <14>; + ti,sci-rm-range-girq = <0x5>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi new file mode 100644 index 000000000000..1884fc70148f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721e.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi new file mode 100644 index 000000000000..f8dd74b17bfb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721E SoC Family + * + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/k3.h> + +/ { + model = "Texas Instruments K3 J721E SoC"; + compatible = "ti,j721e"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial5 = &main_uart3; + serial6 = &main_uart4; + serial7 = &main_uart5; + serial8 = &main_uart6; + serial9 = &main_uart7; + serial10 = &main_uart8; + serial11 = &main_uart9; + }; + + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a72"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a72"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a72_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + cbass_main: interconnect@100000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ + <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ + <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ + <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ + <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ + <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ + <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ + <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ + + /* MCUSS_WKUP Range */ + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + cbass_mcu_wakeup: interconnect@28380000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-j721e-main.dtsi" +#include "k3-j721e-mcu-wakeup.dtsi" diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index dd827e64e5fe..0e58ef02880c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -83,6 +83,7 @@ CONFIG_CPUFREQ_DT=y CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_ARM_ARMADA_37XX_CPUFREQ=y CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=m CONFIG_ARM_TEGRA186_CPUFREQ=y CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_RASPBERRYPI_FIRMWARE=y @@ -192,7 +193,7 @@ CONFIG_PCIE_QCOM=y CONFIG_PCIE_ARMADA_8K=y CONFIG_PCIE_KIRIN=y CONFIG_PCIE_HISI_STB=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_PCIE_TEGRA194=m CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_HISILICON_LPC=y @@ -216,6 +217,7 @@ CONFIG_BLK_DEV_SD=y CONFIG_SCSI_SAS_ATA=y CONFIG_SCSI_HISI_SAS=y CONFIG_SCSI_HISI_SAS_PCI=y +CONFIG_SCSI_MPT3SAS=m CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_QCOM=m @@ -231,6 +233,11 @@ CONFIG_SATA_SIL24=y CONFIG_SATA_RCAR=y CONFIG_PATA_PLATFORM=y CONFIG_PATA_OF_PLATFORM=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m CONFIG_NETDEVICES=y CONFIG_MACVLAN=m CONFIG_MACVTAP=m @@ -240,6 +247,7 @@ CONFIG_VIRTIO_NET=y CONFIG_AMD_XGBE=y CONFIG_NET_XGENE=y CONFIG_ATL1C=m +CONFIG_BNX2X=m CONFIG_MACB=y CONFIG_THUNDER_NIC_PF=y CONFIG_FEC=y @@ -252,6 +260,15 @@ CONFIG_HNS3_ENET=y CONFIG_E1000E=y CONFIG_IGB=y CONFIG_IGBVF=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_MPFS=y CONFIG_MVNETA=y CONFIG_MVPP2=y CONFIG_SKY2=y @@ -291,6 +308,7 @@ CONFIG_WLCORE_SDIO=m CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_ADC=m CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SNVS_PWRKEY=m CONFIG_KEYBOARD_CROS_EC=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=m @@ -344,6 +362,7 @@ CONFIG_I2C_BCM2835=m CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_GPIO=m CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y CONFIG_I2C_PXA=y @@ -359,6 +378,7 @@ CONFIG_SPI_ARMADA_3700=y CONFIG_SPI_BCM2835=m CONFIG_SPI_BCM2835AUX=m CONFIG_SPI_NXP_FLEXSPI=y +CONFIG_SPI_IMX=m CONFIG_SPI_MESON_SPICC=m CONFIG_SPI_MESON_SPIFC=m CONFIG_SPI_ORION=y @@ -371,6 +391,7 @@ CONFIG_SPI_SUN6I=y CONFIG_SPMI=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_IMX8MM=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IPQ8074=y @@ -389,6 +410,7 @@ CONFIG_GPIO_RCAR=y CONFIG_GPIO_UNIPHIER=y CONFIG_GPIO_XGENE=y CONFIG_GPIO_XGENE_SB=y +CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_MAX77620=y @@ -405,9 +427,11 @@ CONFIG_SENSORS_LM90=m CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_THERMAL_EMULATION=y +CONFIG_QORIQ_THERMAL=m CONFIG_ROCKCHIP_THERMAL=m CONFIG_RCAR_THERMAL=y CONFIG_RCAR_GEN3_THERMAL=y @@ -421,7 +445,9 @@ CONFIG_UNIPHIER_THERMAL=y CONFIG_WATCHDOG=y CONFIG_ARM_SP805_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y +CONFIG_SUNXI_WATCHDOG=m CONFIG_IMX2_WDT=y +CONFIG_IMX_SC_WDT=m CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_WATCHDOG=m CONFIG_RENESAS_WDT=y @@ -440,8 +466,10 @@ CONFIG_MFD_MAX77620=y CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_RK808=y CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_ROHM_BD718XX=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_BD718XX=y CONFIG_REGULATOR_BD9571MWV=y CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_GPIO=y @@ -479,6 +507,7 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_RENESAS_FCP=m CONFIG_VIDEO_RENESAS_VSP1=m CONFIG_DRM=m +CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_NOUVEAU=m CONFIG_DRM_EXYNOS=m CONFIG_DRM_EXYNOS5433_DECON=y @@ -506,6 +535,8 @@ CONFIG_DRM_HISI_HIBMC=m CONFIG_DRM_HISI_KIRIN=m CONFIG_DRM_MESON=m CONFIG_DRM_PL111=m +CONFIG_DRM_LIMA=m +CONFIG_DRM_PANFROST=m CONFIG_FB=y CONFIG_FB_MODE_HELPERS=y CONFIG_BACKLIGHT_GENERIC=m @@ -561,6 +592,8 @@ CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_USB_RENESAS_USB3=m +CONFIG_TYPEC=m +CONFIG_TYPEC_HD3SS3220=m CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y @@ -611,11 +644,13 @@ CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_ARMADA38X=y CONFIG_RTC_DRV_TEGRA=y +CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y CONFIG_FSL_EDMA=y CONFIG_DMA_BCM2835=m +CONFIG_DMA_SUN6I=m CONFIG_K3_DMA=y CONFIG_MV_XOR=y CONFIG_MV_XOR_V2=y @@ -641,6 +676,7 @@ CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_QORIQ=y CONFIG_COMMON_CLK_PWM=y +CONFIG_CLK_IMX8MM=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y CONFIG_TI_SCI_CLK=y @@ -675,6 +711,7 @@ CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_RPMSG_QCOM_GLINK_SMEM=m CONFIG_RPMSG_QCOM_SMD=y CONFIG_RASPBERRYPI_POWER=y +CONFIG_IMX_SCU_SOC=y CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_GENI_SE=y CONFIG_QCOM_GLINK_SSR=m @@ -698,6 +735,7 @@ CONFIG_ARCH_TEGRA_210_SOC=y CONFIG_ARCH_TEGRA_186_SOC=y CONFIG_ARCH_TEGRA_194_SOC=y CONFIG_ARCH_K3_AM6_SOC=y +CONFIG_ARCH_K3_J721E_SOC=y CONFIG_SOC_TI=y CONFIG_TI_SCI_PM_DOMAINS=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y @@ -710,7 +748,9 @@ CONFIG_ROCKCHIP_SARADC=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m CONFIG_IIO_CROS_EC_SENSORS=m CONFIG_IIO_CROS_EC_LIGHT_PROX=m +CONFIG_SENSORS_ISL29018=m CONFIG_IIO_CROS_EC_BARO=m +CONFIG_MPL3115=m CONFIG_PWM=y CONFIG_PWM_BCM2835=m CONFIG_PWM_CROS_EC=m @@ -743,6 +783,9 @@ CONFIG_PHY_TEGRA_XUSB=y CONFIG_HISI_PMU=y CONFIG_QCOM_L2_PMU=y CONFIG_QCOM_L3_PMU=y +CONFIG_NVMEM_SUNXI_SID=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_OCOTP_SCU=y CONFIG_QCOM_QFPROM=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_UNIPHIER_EFUSE=y diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h index f318258a14be..92d2e9f28f28 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -16,6 +16,7 @@ #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ #define PTE_DIRTY (_AT(pteval_t, 1) << 55) #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) +#define PTE_DEVMAP (_AT(pteval_t, 1) << 57) #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */ #ifndef __ASSEMBLY__ diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 3052381baaeb..87a4b2ddc1a1 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -79,6 +79,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) +#define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) #define pte_cont_addr_end(addr, end) \ ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ @@ -206,6 +207,11 @@ static inline pmd_t pmd_mkcont(pmd_t pmd) return __pmd(pmd_val(pmd) | PMD_SECT_CONT); } +static inline pte_t pte_mkdevmap(pte_t pte) +{ + return set_pte_bit(pte, __pgprot(PTE_DEVMAP)); +} + static inline void set_pte(pte_t *ptep, pte_t pte) { WRITE_ONCE(*ptep, pte); @@ -388,6 +394,11 @@ static inline int pmd_protnone(pmd_t pmd) #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +#define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) +#endif +#define pmd_mkdevmap(pmd) pte_pmd(pte_mkdevmap(pmd_pte(pmd))) + #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) @@ -673,6 +684,16 @@ static inline int pmdp_set_access_flags(struct vm_area_struct *vma, { return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); } + +static inline int pud_devmap(pud_t pud) +{ + return 0; +} + +static inline int pgd_devmap(pgd_t pgd) +{ + return 0; +} #endif /* diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index a7522fca1105..06ebcfef73df 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -9,7 +9,7 @@ #ifndef __ASM_SYSREG_H #define __ASM_SYSREG_H -#include <linux/const.h> +#include <linux/bits.h> #include <linux/stringify.h> /* @@ -478,31 +478,31 @@ #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) /* Common SCTLR_ELx flags. */ -#define SCTLR_ELx_DSSBS (_BITUL(44)) -#define SCTLR_ELx_ENIA (_BITUL(31)) -#define SCTLR_ELx_ENIB (_BITUL(30)) -#define SCTLR_ELx_ENDA (_BITUL(27)) -#define SCTLR_ELx_EE (_BITUL(25)) -#define SCTLR_ELx_IESB (_BITUL(21)) -#define SCTLR_ELx_WXN (_BITUL(19)) -#define SCTLR_ELx_ENDB (_BITUL(13)) -#define SCTLR_ELx_I (_BITUL(12)) -#define SCTLR_ELx_SA (_BITUL(3)) -#define SCTLR_ELx_C (_BITUL(2)) -#define SCTLR_ELx_A (_BITUL(1)) -#define SCTLR_ELx_M (_BITUL(0)) +#define SCTLR_ELx_DSSBS (BIT(44)) +#define SCTLR_ELx_ENIA (BIT(31)) +#define SCTLR_ELx_ENIB (BIT(30)) +#define SCTLR_ELx_ENDA (BIT(27)) +#define SCTLR_ELx_EE (BIT(25)) +#define SCTLR_ELx_IESB (BIT(21)) +#define SCTLR_ELx_WXN (BIT(19)) +#define SCTLR_ELx_ENDB (BIT(13)) +#define SCTLR_ELx_I (BIT(12)) +#define SCTLR_ELx_SA (BIT(3)) +#define SCTLR_ELx_C (BIT(2)) +#define SCTLR_ELx_A (BIT(1)) +#define SCTLR_ELx_M (BIT(0)) #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) /* SCTLR_EL2 specific flags. */ -#define SCTLR_EL2_RES1 ((_BITUL(4)) | (_BITUL(5)) | (_BITUL(11)) | (_BITUL(16)) | \ - (_BITUL(18)) | (_BITUL(22)) | (_BITUL(23)) | (_BITUL(28)) | \ - (_BITUL(29))) -#define SCTLR_EL2_RES0 ((_BITUL(6)) | (_BITUL(7)) | (_BITUL(8)) | (_BITUL(9)) | \ - (_BITUL(10)) | (_BITUL(13)) | (_BITUL(14)) | (_BITUL(15)) | \ - (_BITUL(17)) | (_BITUL(20)) | (_BITUL(24)) | (_BITUL(26)) | \ - (_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \ +#define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ + (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ + (BIT(29))) +#define SCTLR_EL2_RES0 ((BIT(6)) | (BIT(7)) | (BIT(8)) | (BIT(9)) | \ + (BIT(10)) | (BIT(13)) | (BIT(14)) | (BIT(15)) | \ + (BIT(17)) | (BIT(20)) | (BIT(24)) | (BIT(26)) | \ + (BIT(27)) | (BIT(30)) | (BIT(31)) | \ (0xffffefffUL << 32)) #ifdef CONFIG_CPU_BIG_ENDIAN @@ -524,23 +524,23 @@ #endif /* SCTLR_EL1 specific flags. */ -#define SCTLR_EL1_UCI (_BITUL(26)) -#define SCTLR_EL1_E0E (_BITUL(24)) -#define SCTLR_EL1_SPAN (_BITUL(23)) -#define SCTLR_EL1_NTWE (_BITUL(18)) -#define SCTLR_EL1_NTWI (_BITUL(16)) -#define SCTLR_EL1_UCT (_BITUL(15)) -#define SCTLR_EL1_DZE (_BITUL(14)) -#define SCTLR_EL1_UMA (_BITUL(9)) -#define SCTLR_EL1_SED (_BITUL(8)) -#define SCTLR_EL1_ITD (_BITUL(7)) -#define SCTLR_EL1_CP15BEN (_BITUL(5)) -#define SCTLR_EL1_SA0 (_BITUL(4)) - -#define SCTLR_EL1_RES1 ((_BITUL(11)) | (_BITUL(20)) | (_BITUL(22)) | (_BITUL(28)) | \ - (_BITUL(29))) -#define SCTLR_EL1_RES0 ((_BITUL(6)) | (_BITUL(10)) | (_BITUL(13)) | (_BITUL(17)) | \ - (_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \ +#define SCTLR_EL1_UCI (BIT(26)) +#define SCTLR_EL1_E0E (BIT(24)) +#define SCTLR_EL1_SPAN (BIT(23)) +#define SCTLR_EL1_NTWE (BIT(18)) +#define SCTLR_EL1_NTWI (BIT(16)) +#define SCTLR_EL1_UCT (BIT(15)) +#define SCTLR_EL1_DZE (BIT(14)) +#define SCTLR_EL1_UMA (BIT(9)) +#define SCTLR_EL1_SED (BIT(8)) +#define SCTLR_EL1_ITD (BIT(7)) +#define SCTLR_EL1_CP15BEN (BIT(5)) +#define SCTLR_EL1_SA0 (BIT(4)) + +#define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ + (BIT(29))) +#define SCTLR_EL1_RES0 ((BIT(6)) | (BIT(10)) | (BIT(13)) | (BIT(17)) | \ + (BIT(27)) | (BIT(30)) | (BIT(31)) | \ (0xffffefffUL << 32)) #ifdef CONFIG_CPU_BIG_ENDIAN @@ -756,13 +756,13 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff -#define CPACR_EL1_ZEN_EL1EN (_BITUL(16)) /* enable EL1 access */ -#define CPACR_EL1_ZEN_EL0EN (_BITUL(17)) /* enable EL0 access, if EL1EN set */ +#define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ +#define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ -#define SYS_MPIDR_SAFE_VAL (_BITUL(31)) +#define SYS_MPIDR_SAFE_VAL (BIT(31)) #ifdef __ASSEMBLY__ diff --git a/arch/arm64/kernel/kuser32.S b/arch/arm64/kernel/kuser32.S index 49825e9e421e..42bd8c0c60e0 100644 --- a/arch/arm64/kernel/kuser32.S +++ b/arch/arm64/kernel/kuser32.S @@ -10,7 +10,7 @@ * aarch32_setup_additional_pages() and are provided for compatibility * reasons with 32 bit (aarch32) applications that need them. * - * See Documentation/arm/kernel_user_helpers.txt for formal definitions. + * See Documentation/arm/kernel_user_helpers.rst for formal definitions. */ #include <asm/unistd.h> diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index 575bd5517d21..570988c7a7ff 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -164,6 +164,7 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) struct acpi_pci_generic_root_info *ri; struct pci_bus *bus, *child; struct acpi_pci_root_ops *root_ops; + struct pci_host_bridge *host; ri = kzalloc(sizeof(*ri), GFP_KERNEL); if (!ri) @@ -189,8 +190,16 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) if (!bus) return NULL; - pci_bus_size_bridges(bus); - pci_bus_assign_resources(bus); + /* If we must preserve the resource configuration, claim now */ + host = pci_find_host_bridge(bus); + if (host->preserve_config) + pci_bus_claim_resources(bus); + + /* + * Assign whatever was left unassigned. If we didn't claim above, + * this will reassign everything. + */ + pci_assign_unassigned_root_bus_resources(bus); list_for_each_entry(child, &bus->children, node) pcie_bus_configure_settings(child); diff --git a/arch/arm64/kernel/vdso32/Makefile b/arch/arm64/kernel/vdso32/Makefile index 288c14d30b45..60a4c6239712 100644 --- a/arch/arm64/kernel/vdso32/Makefile +++ b/arch/arm64/kernel/vdso32/Makefile @@ -96,8 +96,8 @@ VDSO_LDFLAGS := $(VDSO_CPPFLAGS) VDSO_LDFLAGS += -Wl,-Bsymbolic -Wl,--no-undefined -Wl,-soname=linux-vdso.so.1 VDSO_LDFLAGS += -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096 VDSO_LDFLAGS += -nostdlib -shared -mfloat-abi=soft -VDSO_LDFLAGS += $(call cc32-ldoption,-Wl$(comma)--hash-style=sysv) -VDSO_LDFLAGS += $(call cc32-ldoption,-Wl$(comma)--build-id) +VDSO_LDFLAGS += -Wl,--hash-style=sysv +VDSO_LDFLAGS += -Wl,--build-id VDSO_LDFLAGS += $(call cc32-ldoption,-fuse-ld=bfd) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index c8c61b1eb479..9568c116ac7f 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -59,28 +59,6 @@ static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr) return debug_fault_info + DBG_ESR_EVT(esr); } -#ifdef CONFIG_KPROBES -static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) -{ - int ret = 0; - - /* kprobe_running() needs smp_processor_id() */ - if (!user_mode(regs)) { - preempt_disable(); - if (kprobe_running() && kprobe_fault_handler(regs, esr)) - ret = 1; - preempt_enable(); - } - - return ret; -} -#else -static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) -{ - return 0; -} -#endif - static void data_abort_decode(unsigned int esr) { pr_alert("Data abort info:\n"); @@ -434,7 +412,7 @@ static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, unsigned long vm_flags = VM_READ | VM_WRITE; unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; - if (notify_page_fault(regs, esr)) + if (kprobe_page_fault(regs, esr)) return 0; /* diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 1b49c08dfa2b..750a69dde39b 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -942,6 +942,11 @@ void *__init fixmap_remap_fdt(phys_addr_t dt_phys) return dt_virt; } +int __init arch_ioremap_p4d_supported(void) +{ + return 0; +} + int __init arch_ioremap_pud_supported(void) { /* @@ -1069,4 +1074,21 @@ int arch_add_memory(int nid, u64 start, u64 size, return __add_pages(nid, start >> PAGE_SHIFT, size >> PAGE_SHIFT, restrictions); } +void arch_remove_memory(int nid, u64 start, u64 size, + struct vmem_altmap *altmap) +{ + unsigned long start_pfn = start >> PAGE_SHIFT; + unsigned long nr_pages = size >> PAGE_SHIFT; + struct zone *zone; + + /* + * FIXME: Cleanup page tables (also in arch_add_memory() in case + * adding fails). Until then, this function should only be used + * during memory hotplug (adding memory), not for memory + * unplug. ARCH_ENABLE_MEMORY_HOTREMOVE must not be + * unlocked yet. + */ + zone = page_zone(pfn_to_page(start_pfn)); + __remove_pages(zone, start_pfn, nr_pages, altmap); +} #endif diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig index cf798a1628cf..3973847b5f42 100644 --- a/arch/csky/Kconfig +++ b/arch/csky/Kconfig @@ -10,6 +10,9 @@ config CSKY select COMMON_CLK select CLKSRC_MMIO select CLKSRC_OF + select CSKY_MPINTC if CPU_CK860 + select CSKY_MP_TIMER if CPU_CK860 + select CSKY_APB_INTC select DMA_DIRECT_REMAP select IRQ_DOMAIN select HANDLE_DOMAIN_IRQ @@ -30,6 +33,7 @@ config CSKY select GENERIC_IRQ_MULTI_HANDLER select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD + select GX6605S_TIMER if CPU_CK610 select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_AUDITSYSCALL select HAVE_DYNAMIC_FTRACE diff --git a/arch/csky/abiv1/Makefile b/arch/csky/abiv1/Makefile index e52b42beac97..601ce3b2fb85 100644 --- a/arch/csky/abiv1/Makefile +++ b/arch/csky/abiv1/Makefile @@ -5,5 +5,4 @@ obj-y += bswapsi.o obj-y += cacheflush.o obj-y += mmap.o obj-y += memcpy.o -obj-y += memset.o obj-y += strksyms.o diff --git a/arch/csky/abiv1/inc/abi/ckmmu.h b/arch/csky/abiv1/inc/abi/ckmmu.h index 81f37715c0d2..ba8eb5870835 100644 --- a/arch/csky/abiv1/inc/abi/ckmmu.h +++ b/arch/csky/abiv1/inc/abi/ckmmu.h @@ -78,6 +78,12 @@ static inline void tlb_invalid_all(void) cpwcr("cpcr8", 0x04000000); } + +static inline void local_tlb_invalid_all(void) +{ + tlb_invalid_all(); +} + static inline void tlb_invalid_indexed(void) { cpwcr("cpcr8", 0x02000000); diff --git a/arch/csky/abiv1/inc/abi/string.h b/arch/csky/abiv1/inc/abi/string.h index 5abe80be044d..0cd43384f8d2 100644 --- a/arch/csky/abiv1/inc/abi/string.h +++ b/arch/csky/abiv1/inc/abi/string.h @@ -7,7 +7,4 @@ #define __HAVE_ARCH_MEMCPY extern void *memcpy(void *, const void *, __kernel_size_t); -#define __HAVE_ARCH_MEMSET -extern void *memset(void *, int, __kernel_size_t); - #endif /* __ABI_CSKY_STRING_H */ diff --git a/arch/csky/abiv1/memset.c b/arch/csky/abiv1/memset.c deleted file mode 100644 index b4aa75b99c5d..000000000000 --- a/arch/csky/abiv1/memset.c +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. - -#include <linux/types.h> - -void *memset(void *dest, int c, size_t l) -{ - char *d = dest; - int ch = c & 0xff; - int tmp = (ch | ch << 8 | ch << 16 | ch << 24); - - while (((uintptr_t)d & 0x3) && l--) - *d++ = ch; - - while (l >= 16) { - *(((u32 *)d)) = tmp; - *(((u32 *)d)+1) = tmp; - *(((u32 *)d)+2) = tmp; - *(((u32 *)d)+3) = tmp; - l -= 16; - d += 16; - } - - while (l > 3) { - *(((u32 *)d)) = tmp; - l -= 4; - d += 4; - } - - while (l) { - *d = ch; - l--; - d++; - } - - return dest; -} diff --git a/arch/csky/abiv1/strksyms.c b/arch/csky/abiv1/strksyms.c index 436995c9b75c..c7ccbb27e8d7 100644 --- a/arch/csky/abiv1/strksyms.c +++ b/arch/csky/abiv1/strksyms.c @@ -4,4 +4,3 @@ #include <linux/module.h> EXPORT_SYMBOL(memcpy); -EXPORT_SYMBOL(memset); diff --git a/arch/csky/abiv2/inc/abi/ckmmu.h b/arch/csky/abiv2/inc/abi/ckmmu.h index e4480e6bc3b3..73ded7c72482 100644 --- a/arch/csky/abiv2/inc/abi/ckmmu.h +++ b/arch/csky/abiv2/inc/abi/ckmmu.h @@ -85,6 +85,16 @@ static inline void tlb_invalid_all(void) #endif } +static inline void local_tlb_invalid_all(void) +{ +#ifdef CONFIG_CPU_HAS_TLBI + asm volatile("tlbi.all\n":::"memory"); + sync_is(); +#else + tlb_invalid_all(); +#endif +} + static inline void tlb_invalid_indexed(void) { mtcr("cr<8, 15>", 0x02000000); diff --git a/arch/csky/include/asm/asid.h b/arch/csky/include/asm/asid.h new file mode 100644 index 000000000000..ac08b0ffbe1f --- /dev/null +++ b/arch/csky/include/asm/asid.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_ASM_ASID_H +#define __ASM_ASM_ASID_H + +#include <linux/atomic.h> +#include <linux/compiler.h> +#include <linux/cpumask.h> +#include <linux/percpu.h> +#include <linux/spinlock.h> + +struct asid_info +{ + atomic64_t generation; + unsigned long *map; + atomic64_t __percpu *active; + u64 __percpu *reserved; + u32 bits; + /* Lock protecting the structure */ + raw_spinlock_t lock; + /* Which CPU requires context flush on next call */ + cpumask_t flush_pending; + /* Number of ASID allocated by context (shift value) */ + unsigned int ctxt_shift; + /* Callback to locally flush the context. */ + void (*flush_cpu_ctxt_cb)(void); +}; + +#define NUM_ASIDS(info) (1UL << ((info)->bits)) +#define NUM_CTXT_ASIDS(info) (NUM_ASIDS(info) >> (info)->ctxt_shift) + +#define active_asid(info, cpu) *per_cpu_ptr((info)->active, cpu) + +void asid_new_context(struct asid_info *info, atomic64_t *pasid, + unsigned int cpu, struct mm_struct *mm); + +/* + * Check the ASID is still valid for the context. If not generate a new ASID. + * + * @pasid: Pointer to the current ASID batch + * @cpu: current CPU ID. Must have been acquired throught get_cpu() + */ +static inline void asid_check_context(struct asid_info *info, + atomic64_t *pasid, unsigned int cpu, + struct mm_struct *mm) +{ + u64 asid, old_active_asid; + + asid = atomic64_read(pasid); + + /* + * The memory ordering here is subtle. + * If our active_asid is non-zero and the ASID matches the current + * generation, then we update the active_asid entry with a relaxed + * cmpxchg. Racing with a concurrent rollover means that either: + * + * - We get a zero back from the cmpxchg and end up waiting on the + * lock. Taking the lock synchronises with the rollover and so + * we are forced to see the updated generation. + * + * - We get a valid ASID back from the cmpxchg, which means the + * relaxed xchg in flush_context will treat us as reserved + * because atomic RmWs are totally ordered for a given location. + */ + old_active_asid = atomic64_read(&active_asid(info, cpu)); + if (old_active_asid && + !((asid ^ atomic64_read(&info->generation)) >> info->bits) && + atomic64_cmpxchg_relaxed(&active_asid(info, cpu), + old_active_asid, asid)) + return; + + asid_new_context(info, pasid, cpu, mm); +} + +int asid_allocator_init(struct asid_info *info, + u32 bits, unsigned int asid_per_ctxt, + void (*flush_cpu_ctxt_cb)(void)); + +#endif diff --git a/arch/csky/include/asm/mmu.h b/arch/csky/include/asm/mmu.h index cb344675ccc4..b382a14ea4ec 100644 --- a/arch/csky/include/asm/mmu.h +++ b/arch/csky/include/asm/mmu.h @@ -5,7 +5,7 @@ #define __ASM_CSKY_MMU_H typedef struct { - unsigned long asid[NR_CPUS]; + atomic64_t asid; void *vdso; } mm_context_t; diff --git a/arch/csky/include/asm/mmu_context.h b/arch/csky/include/asm/mmu_context.h index 734db3a122e1..0285b0ad18b6 100644 --- a/arch/csky/include/asm/mmu_context.h +++ b/arch/csky/include/asm/mmu_context.h @@ -16,122 +16,32 @@ #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ setup_pgd(__pa(pgd), false) + #define TLBMISS_HANDLER_SETUP_PGD_KERNEL(pgd) \ setup_pgd(__pa(pgd), true) -#define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) -#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) -#define asid_cache(cpu) (cpu_data[cpu].asid_cache) +#define ASID_MASK ((1 << CONFIG_CPU_ASID_BITS) - 1) +#define cpu_asid(mm) (atomic64_read(&mm->context.asid) & ASID_MASK) -#define ASID_FIRST_VERSION (1 << CONFIG_CPU_ASID_BITS) -#define ASID_INC 0x1 -#define ASID_MASK (ASID_FIRST_VERSION - 1) -#define ASID_VERSION_MASK ~ASID_MASK +#define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.asid, 0); 0; }) +#define activate_mm(prev,next) switch_mm(prev, next, current) #define destroy_context(mm) do {} while (0) #define enter_lazy_tlb(mm, tsk) do {} while (0) #define deactivate_mm(tsk, mm) do {} while (0) -/* - * All unused by hardware upper bits will be considered - * as a software asid extension. - */ -static inline void -get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) -{ - unsigned long asid = asid_cache(cpu); - - asid += ASID_INC; - if (!(asid & ASID_MASK)) { - flush_tlb_all(); /* start new asid cycle */ - if (!asid) /* fix version if needed */ - asid = ASID_FIRST_VERSION; - } - cpu_context(cpu, mm) = asid_cache(cpu) = asid; -} - -/* - * Initialize the context related info for a new mm_struct - * instance. - */ -static inline int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - int i; - - for_each_online_cpu(i) - cpu_context(i, mm) = 0; - return 0; -} - -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - unsigned int cpu = smp_processor_id(); - unsigned long flags; - - local_irq_save(flags); - /* Check if our ASID is of an older version and thus invalid */ - if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) - get_new_mmu_context(next, cpu); - write_mmu_entryhi(cpu_asid(cpu, next)); - TLBMISS_HANDLER_SETUP_PGD(next->pgd); - - /* - * Mark current->active_mm as not "active" anymore. - * We don't want to mislead possible IPI tlb flush routines. - */ - cpumask_clear_cpu(cpu, mm_cpumask(prev)); - cpumask_set_cpu(cpu, mm_cpumask(next)); +void check_and_switch_context(struct mm_struct *mm, unsigned int cpu); - local_irq_restore(flags); -} - -/* - * After we have set current->mm to a new value, this activates - * the context for the new mm so we see the new mappings. - */ static inline void -activate_mm(struct mm_struct *prev, struct mm_struct *next) +switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) { - unsigned long flags; - int cpu = smp_processor_id(); - - local_irq_save(flags); + unsigned int cpu = smp_processor_id(); - /* Unconditionally get a new ASID. */ - get_new_mmu_context(next, cpu); + if (prev != next) + check_and_switch_context(next, cpu); - write_mmu_entryhi(cpu_asid(cpu, next)); TLBMISS_HANDLER_SETUP_PGD(next->pgd); - - /* mark mmu ownership change */ - cpumask_clear_cpu(cpu, mm_cpumask(prev)); - cpumask_set_cpu(cpu, mm_cpumask(next)); - - local_irq_restore(flags); -} - -/* - * If mm is currently active_mm, we can't really drop it. Instead, - * we will get a new one for it. - */ -static inline void -drop_mmu_context(struct mm_struct *mm, unsigned int cpu) -{ - unsigned long flags; - - local_irq_save(flags); - - if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { - get_new_mmu_context(mm, cpu); - write_mmu_entryhi(cpu_asid(cpu, mm)); - } else { - /* will get a new context next time */ - cpu_context(cpu, mm) = 0; - } - - local_irq_restore(flags); + write_mmu_entryhi(next->context.asid.counter); } - #endif /* __ASM_CSKY_MMU_CONTEXT_H */ diff --git a/arch/csky/include/asm/pgtable.h b/arch/csky/include/asm/pgtable.h index dcea277c09ae..c429a6f347de 100644 --- a/arch/csky/include/asm/pgtable.h +++ b/arch/csky/include/asm/pgtable.h @@ -290,8 +290,6 @@ static inline pte_t *pte_offset(pmd_t *dir, unsigned long address) extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern void paging_init(void); -extern void show_jtlb_table(void); - void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *pte); diff --git a/arch/csky/kernel/perf_event.c b/arch/csky/kernel/perf_event.c index 376c972f5f37..4c1a1934d76a 100644 --- a/arch/csky/kernel/perf_event.c +++ b/arch/csky/kernel/perf_event.c @@ -9,17 +9,44 @@ #include <linux/platform_device.h> #define CSKY_PMU_MAX_EVENTS 32 +#define DEFAULT_COUNT_WIDTH 48 + +#define HPCR "<0, 0x0>" /* PMU Control reg */ +#define HPSPR "<0, 0x1>" /* Start PC reg */ +#define HPEPR "<0, 0x2>" /* End PC reg */ +#define HPSIR "<0, 0x3>" /* Soft Counter reg */ +#define HPCNTENR "<0, 0x4>" /* Count Enable reg */ +#define HPINTENR "<0, 0x5>" /* Interrupt Enable reg */ +#define HPOFSR "<0, 0x6>" /* Interrupt Status reg */ + +/* The events for a given PMU register set. */ +struct pmu_hw_events { + /* + * The events that are active on the PMU for the given index. + */ + struct perf_event *events[CSKY_PMU_MAX_EVENTS]; -#define HPCR "<0, 0x0>" /* PMU Control reg */ -#define HPCNTENR "<0, 0x4>" /* Count Enable reg */ + /* + * A 1 bit for an index indicates that the counter is being used for + * an event. A 0 means that the counter can be used. + */ + unsigned long used_mask[BITS_TO_LONGS(CSKY_PMU_MAX_EVENTS)]; +}; static uint64_t (*hw_raw_read_mapping[CSKY_PMU_MAX_EVENTS])(void); static void (*hw_raw_write_mapping[CSKY_PMU_MAX_EVENTS])(uint64_t val); -struct csky_pmu_t { - struct pmu pmu; - uint32_t hpcr; +static struct csky_pmu_t { + struct pmu pmu; + struct pmu_hw_events __percpu *hw_events; + struct platform_device *plat_device; + uint32_t count_width; + uint32_t hpcr; + u64 max_period; } csky_pmu; +static int csky_pmu_irq; + +#define to_csky_pmu(p) (container_of(p, struct csky_pmu, pmu)) #define cprgr(reg) \ ({ \ @@ -701,6 +728,20 @@ static const int csky_pmu_hw_map[PERF_COUNT_HW_MAX] = { #define CACHE_OP_UNSUPPORTED 0xffff static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [C(L1D)] = { +#ifdef CONFIG_CPU_CK810 + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = 0x5, + [C(RESULT_MISS)] = 0x6, + }, +#else [C(OP_READ)] = { [C(RESULT_ACCESS)] = 0x14, [C(RESULT_MISS)] = 0x15, @@ -710,9 +751,10 @@ static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [C(RESULT_MISS)] = 0x17, }, [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = 0x5, - [C(RESULT_MISS)] = 0x6, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, +#endif }, [C(L1I)] = { [C(OP_READ)] = { @@ -729,6 +771,20 @@ static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, }, [C(LL)] = { +#ifdef CONFIG_CPU_CK810 + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = 0x7, + [C(RESULT_MISS)] = 0x8, + }, +#else [C(OP_READ)] = { [C(RESULT_ACCESS)] = 0x18, [C(RESULT_MISS)] = 0x19, @@ -738,29 +794,48 @@ static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [C(RESULT_MISS)] = 0x1b, }, [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = 0x7, - [C(RESULT_MISS)] = 0x8, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, +#endif }, [C(DTLB)] = { +#ifdef CONFIG_CPU_CK810 [C(OP_READ)] = { - [C(RESULT_ACCESS)] = 0x5, - [C(RESULT_MISS)] = 0xb, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, +#else + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = 0x14, + [C(RESULT_MISS)] = 0xb, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = 0x16, + [C(RESULT_MISS)] = 0xb, + }, +#endif [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(ITLB)] = { +#ifdef CONFIG_CPU_CK810 + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, +#else [C(OP_READ)] = { [C(RESULT_ACCESS)] = 0x3, [C(RESULT_MISS)] = 0xa, }, +#endif [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, @@ -800,11 +875,57 @@ static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { }, }; +int csky_pmu_event_set_period(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + s64 left = local64_read(&hwc->period_left); + s64 period = hwc->sample_period; + int ret = 0; + + if (unlikely(left <= -period)) { + left = period; + local64_set(&hwc->period_left, left); + hwc->last_period = period; + ret = 1; + } + + if (unlikely(left <= 0)) { + left += period; + local64_set(&hwc->period_left, left); + hwc->last_period = period; + ret = 1; + } + + if (left > (s64)csky_pmu.max_period) + left = csky_pmu.max_period; + + /* + * The hw event starts counting from this event offset, + * mark it to be able to extract future "deltas": + */ + local64_set(&hwc->prev_count, (u64)(-left)); + + if (hw_raw_write_mapping[hwc->idx] != NULL) + hw_raw_write_mapping[hwc->idx]((u64)(-left) & + csky_pmu.max_period); + + cpwcr(HPOFSR, ~BIT(hwc->idx) & cprcr(HPOFSR)); + + perf_event_update_userpage(event); + + return ret; +} + static void csky_perf_event_update(struct perf_event *event, struct hw_perf_event *hwc) { uint64_t prev_raw_count = local64_read(&hwc->prev_count); - uint64_t new_raw_count = hw_raw_read_mapping[hwc->idx](); + /* + * Sign extend count value to 64bit, otherwise delta calculation + * would be incorrect when overflow occurs. + */ + uint64_t new_raw_count = sign_extend64( + hw_raw_read_mapping[hwc->idx](), csky_pmu.count_width - 1); int64_t delta = new_raw_count - prev_raw_count; /* @@ -816,6 +937,11 @@ static void csky_perf_event_update(struct perf_event *event, local64_sub(delta, &hwc->period_left); } +static void csky_pmu_reset(void *info) +{ + cpwcr(HPCR, BIT(31) | BIT(30) | BIT(1)); +} + static void csky_pmu_read(struct perf_event *event) { csky_perf_event_update(event, &event->hw); @@ -844,15 +970,6 @@ static int csky_pmu_event_init(struct perf_event *event) struct hw_perf_event *hwc = &event->hw; int ret; - if (event->attr.exclude_user) - csky_pmu.hpcr = BIT(2); - else if (event->attr.exclude_kernel) - csky_pmu.hpcr = BIT(3); - else - csky_pmu.hpcr = BIT(2) | BIT(3); - - csky_pmu.hpcr |= BIT(1) | BIT(0); - switch (event->attr.type) { case PERF_TYPE_HARDWARE: if (event->attr.config >= PERF_COUNT_HW_MAX) @@ -861,21 +978,32 @@ static int csky_pmu_event_init(struct perf_event *event) if (ret == HW_OP_UNSUPPORTED) return -ENOENT; hwc->idx = ret; - return 0; + break; case PERF_TYPE_HW_CACHE: ret = csky_pmu_cache_event(event->attr.config); if (ret == CACHE_OP_UNSUPPORTED) return -ENOENT; hwc->idx = ret; - return 0; + break; case PERF_TYPE_RAW: if (hw_raw_read_mapping[event->attr.config] == NULL) return -ENOENT; hwc->idx = event->attr.config; - return 0; + break; default: return -ENOENT; } + + if (event->attr.exclude_user) + csky_pmu.hpcr = BIT(2); + else if (event->attr.exclude_kernel) + csky_pmu.hpcr = BIT(3); + else + csky_pmu.hpcr = BIT(2) | BIT(3); + + csky_pmu.hpcr |= BIT(1) | BIT(0); + + return 0; } /* starts all counters */ @@ -892,6 +1020,7 @@ static void csky_pmu_disable(struct pmu *pmu) static void csky_pmu_start(struct perf_event *event, int flags) { + unsigned long flg; struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; @@ -903,16 +1032,34 @@ static void csky_pmu_start(struct perf_event *event, int flags) hwc->state = 0; + csky_pmu_event_set_period(event); + + local_irq_save(flg); + + cpwcr(HPINTENR, BIT(idx) | cprcr(HPINTENR)); cpwcr(HPCNTENR, BIT(idx) | cprcr(HPCNTENR)); + + local_irq_restore(flg); } -static void csky_pmu_stop(struct perf_event *event, int flags) +static void csky_pmu_stop_event(struct perf_event *event) { + unsigned long flg; struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; + local_irq_save(flg); + + cpwcr(HPINTENR, ~BIT(idx) & cprcr(HPINTENR)); + cpwcr(HPCNTENR, ~BIT(idx) & cprcr(HPCNTENR)); + + local_irq_restore(flg); +} + +static void csky_pmu_stop(struct perf_event *event, int flags) +{ if (!(event->hw.state & PERF_HES_STOPPED)) { - cpwcr(HPCNTENR, ~BIT(idx) & cprcr(HPCNTENR)); + csky_pmu_stop_event(event); event->hw.state |= PERF_HES_STOPPED; } @@ -925,22 +1072,26 @@ static void csky_pmu_stop(struct perf_event *event, int flags) static void csky_pmu_del(struct perf_event *event, int flags) { + struct pmu_hw_events *hw_events = this_cpu_ptr(csky_pmu.hw_events); + struct hw_perf_event *hwc = &event->hw; + csky_pmu_stop(event, PERF_EF_UPDATE); + hw_events->events[hwc->idx] = NULL; + perf_event_update_userpage(event); } /* allocate hardware counter and optionally start counting */ static int csky_pmu_add(struct perf_event *event, int flags) { + struct pmu_hw_events *hw_events = this_cpu_ptr(csky_pmu.hw_events); struct hw_perf_event *hwc = &event->hw; - local64_set(&hwc->prev_count, 0); - - if (hw_raw_write_mapping[hwc->idx] != NULL) - hw_raw_write_mapping[hwc->idx](0); + hw_events->events[hwc->idx] = event; hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; + if (flags & PERF_EF_START) csky_pmu_start(event, PERF_EF_RELOAD); @@ -949,8 +1100,110 @@ static int csky_pmu_add(struct perf_event *event, int flags) return 0; } -int __init init_hw_perf_events(void) +static irqreturn_t csky_pmu_handle_irq(int irq_num, void *dev) +{ + struct perf_sample_data data; + struct pmu_hw_events *cpuc = this_cpu_ptr(csky_pmu.hw_events); + struct pt_regs *regs; + int idx; + + /* + * Did an overflow occur? + */ + if (!cprcr(HPOFSR)) + return IRQ_NONE; + + /* + * Handle the counter(s) overflow(s) + */ + regs = get_irq_regs(); + + csky_pmu_disable(&csky_pmu.pmu); + + for (idx = 0; idx < CSKY_PMU_MAX_EVENTS; ++idx) { + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc; + + /* Ignore if we don't have an event. */ + if (!event) + continue; + /* + * We have a single interrupt for all counters. Check that + * each counter has overflowed before we process it. + */ + if (!(cprcr(HPOFSR) & BIT(idx))) + continue; + + hwc = &event->hw; + csky_perf_event_update(event, &event->hw); + perf_sample_data_init(&data, 0, hwc->last_period); + csky_pmu_event_set_period(event); + + if (perf_event_overflow(event, &data, regs)) + csky_pmu_stop_event(event); + } + + csky_pmu_enable(&csky_pmu.pmu); + + /* + * Handle the pending perf events. + * + * Note: this call *must* be run with interrupts disabled. For + * platforms that can have the PMU interrupts raised as an NMI, this + * will not work. + */ + irq_work_run(); + + return IRQ_HANDLED; +} + +static int csky_pmu_request_irq(irq_handler_t handler) { + int err, irqs; + struct platform_device *pmu_device = csky_pmu.plat_device; + + if (!pmu_device) + return -ENODEV; + + irqs = min(pmu_device->num_resources, num_possible_cpus()); + if (irqs < 1) { + pr_err("no irqs for PMUs defined\n"); + return -ENODEV; + } + + csky_pmu_irq = platform_get_irq(pmu_device, 0); + if (csky_pmu_irq < 0) + return -ENODEV; + err = request_percpu_irq(csky_pmu_irq, handler, "csky-pmu", + this_cpu_ptr(csky_pmu.hw_events)); + if (err) { + pr_err("unable to request IRQ%d for CSKY PMU counters\n", + csky_pmu_irq); + return err; + } + + return 0; +} + +static void csky_pmu_free_irq(void) +{ + int irq; + struct platform_device *pmu_device = csky_pmu.plat_device; + + irq = platform_get_irq(pmu_device, 0); + if (irq >= 0) + free_percpu_irq(irq, this_cpu_ptr(csky_pmu.hw_events)); +} + +int init_hw_perf_events(void) +{ + csky_pmu.hw_events = alloc_percpu_gfp(struct pmu_hw_events, + GFP_KERNEL); + if (!csky_pmu.hw_events) { + pr_info("failed to allocate per-cpu PMU data.\n"); + return -ENOMEM; + } + csky_pmu.pmu = (struct pmu) { .pmu_enable = csky_pmu_enable, .pmu_disable = csky_pmu_disable, @@ -1022,10 +1275,97 @@ int __init init_hw_perf_events(void) hw_raw_write_mapping[0x1a] = csky_pmu_write_l2wac; hw_raw_write_mapping[0x1b] = csky_pmu_write_l2wmc; - csky_pmu.pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; + return 0; +} - cpwcr(HPCR, BIT(31) | BIT(30) | BIT(1)); +static int csky_pmu_starting_cpu(unsigned int cpu) +{ + enable_percpu_irq(csky_pmu_irq, 0); + return 0; +} - return perf_pmu_register(&csky_pmu.pmu, "cpu", PERF_TYPE_RAW); +static int csky_pmu_dying_cpu(unsigned int cpu) +{ + disable_percpu_irq(csky_pmu_irq); + return 0; } -arch_initcall(init_hw_perf_events); + +int csky_pmu_device_probe(struct platform_device *pdev, + const struct of_device_id *of_table) +{ + struct device_node *node = pdev->dev.of_node; + int ret; + + ret = init_hw_perf_events(); + if (ret) { + pr_notice("[perf] failed to probe PMU!\n"); + return ret; + } + + if (of_property_read_u32(node, "count-width", + &csky_pmu.count_width)) { + csky_pmu.count_width = DEFAULT_COUNT_WIDTH; + } + csky_pmu.max_period = BIT(csky_pmu.count_width) - 1; + + csky_pmu.plat_device = pdev; + + /* Ensure the PMU has sane values out of reset. */ + on_each_cpu(csky_pmu_reset, &csky_pmu, 1); + + ret = csky_pmu_request_irq(csky_pmu_handle_irq); + if (ret) { + csky_pmu.pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; + pr_notice("[perf] PMU request irq fail!\n"); + } + + ret = cpuhp_setup_state(CPUHP_AP_PERF_ONLINE, "AP_PERF_ONLINE", + csky_pmu_starting_cpu, + csky_pmu_dying_cpu); + if (ret) { + csky_pmu_free_irq(); + free_percpu(csky_pmu.hw_events); + return ret; + } + + ret = perf_pmu_register(&csky_pmu.pmu, "cpu", PERF_TYPE_RAW); + if (ret) { + csky_pmu_free_irq(); + free_percpu(csky_pmu.hw_events); + } + + return ret; +} + +const static struct of_device_id csky_pmu_of_device_ids[] = { + {.compatible = "csky,csky-pmu"}, + {}, +}; + +static int csky_pmu_dev_probe(struct platform_device *pdev) +{ + return csky_pmu_device_probe(pdev, csky_pmu_of_device_ids); +} + +static struct platform_driver csky_pmu_driver = { + .driver = { + .name = "csky-pmu", + .of_match_table = csky_pmu_of_device_ids, + }, + .probe = csky_pmu_dev_probe, +}; + +static int __init csky_pmu_probe(void) +{ + int ret; + + ret = platform_driver_register(&csky_pmu_driver); + if (ret) + pr_notice("[perf] PMU initialization failed\n"); + else + pr_notice("[perf] PMU initialization done\n"); + + return ret; +} + +device_initcall(csky_pmu_probe); diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c index b07a534b3062..b753d382e4ce 100644 --- a/arch/csky/kernel/smp.c +++ b/arch/csky/kernel/smp.c @@ -212,8 +212,6 @@ void csky_start_secondary(void) TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); TLBMISS_HANDLER_SETUP_PGD_KERNEL(swapper_pg_dir); - asid_cache(smp_processor_id()) = ASID_FIRST_VERSION; - #ifdef CONFIG_CPU_HAS_FPU init_fpu(); #endif diff --git a/arch/csky/kernel/traps.c b/arch/csky/kernel/traps.c index 2792e9601ac5..b057480e7463 100644 --- a/arch/csky/kernel/traps.c +++ b/arch/csky/kernel/traps.c @@ -120,6 +120,7 @@ asmlinkage void trap_c(struct pt_regs *regs) switch (vector) { case VEC_ZERODIV: + die_if_kernel("Kernel mode ZERO DIV", regs, vector); sig = SIGFPE; break; /* ptrace */ @@ -128,6 +129,7 @@ asmlinkage void trap_c(struct pt_regs *regs) sig = SIGTRAP; break; case VEC_ILLEGAL: + die_if_kernel("Kernel mode ILLEGAL", regs, vector); #ifndef CONFIG_CPU_NO_USER_BKPT if (*(uint16_t *)instruction_pointer(regs) != USR_BKPT) #endif @@ -139,6 +141,7 @@ asmlinkage void trap_c(struct pt_regs *regs) case VEC_TRAP1: /* jtagserver breakpoint */ case VEC_BREAKPOINT: + die_if_kernel("Kernel mode BKPT", regs, vector); info.si_code = TRAP_BRKPT; sig = SIGTRAP; break; @@ -150,8 +153,10 @@ asmlinkage void trap_c(struct pt_regs *regs) #endif #ifdef CONFIG_CPU_HAS_FPU case VEC_FPE: + die_if_kernel("Kernel mode FPE", regs, vector); return fpu_fpe(regs); case VEC_PRIV: + die_if_kernel("Kernel mode PRIV", regs, vector); if (fpu_libc_helper(regs)) return; #endif diff --git a/arch/csky/mm/Makefile b/arch/csky/mm/Makefile index 4eebebdcd1bf..c94ef6481098 100644 --- a/arch/csky/mm/Makefile +++ b/arch/csky/mm/Makefile @@ -12,3 +12,5 @@ obj-y += init.o obj-y += ioremap.o obj-y += syscache.o obj-y += tlb.o +obj-y += asid.o +obj-y += context.o diff --git a/arch/csky/mm/asid.c b/arch/csky/mm/asid.c new file mode 100644 index 000000000000..b2e914745c1d --- /dev/null +++ b/arch/csky/mm/asid.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Generic ASID allocator. + * + * Based on arch/arm/mm/context.c + * + * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved. + * Copyright (C) 2012 ARM Ltd. + */ + +#include <linux/slab.h> +#include <linux/mm_types.h> + +#include <asm/asid.h> + +#define reserved_asid(info, cpu) *per_cpu_ptr((info)->reserved, cpu) + +#define ASID_MASK(info) (~GENMASK((info)->bits - 1, 0)) +#define ASID_FIRST_VERSION(info) (1UL << ((info)->bits)) + +#define asid2idx(info, asid) (((asid) & ~ASID_MASK(info)) >> (info)->ctxt_shift) +#define idx2asid(info, idx) (((idx) << (info)->ctxt_shift) & ~ASID_MASK(info)) + +static void flush_context(struct asid_info *info) +{ + int i; + u64 asid; + + /* Update the list of reserved ASIDs and the ASID bitmap. */ + bitmap_clear(info->map, 0, NUM_CTXT_ASIDS(info)); + + for_each_possible_cpu(i) { + asid = atomic64_xchg_relaxed(&active_asid(info, i), 0); + /* + * If this CPU has already been through a + * rollover, but hasn't run another task in + * the meantime, we must preserve its reserved + * ASID, as this is the only trace we have of + * the process it is still running. + */ + if (asid == 0) + asid = reserved_asid(info, i); + __set_bit(asid2idx(info, asid), info->map); + reserved_asid(info, i) = asid; + } + + /* + * Queue a TLB invalidation for each CPU to perform on next + * context-switch + */ + cpumask_setall(&info->flush_pending); +} + +static bool check_update_reserved_asid(struct asid_info *info, u64 asid, + u64 newasid) +{ + int cpu; + bool hit = false; + + /* + * Iterate over the set of reserved ASIDs looking for a match. + * If we find one, then we can update our mm to use newasid + * (i.e. the same ASID in the current generation) but we can't + * exit the loop early, since we need to ensure that all copies + * of the old ASID are updated to reflect the mm. Failure to do + * so could result in us missing the reserved ASID in a future + * generation. + */ + for_each_possible_cpu(cpu) { + if (reserved_asid(info, cpu) == asid) { + hit = true; + reserved_asid(info, cpu) = newasid; + } + } + + return hit; +} + +static u64 new_context(struct asid_info *info, atomic64_t *pasid, + struct mm_struct *mm) +{ + static u32 cur_idx = 1; + u64 asid = atomic64_read(pasid); + u64 generation = atomic64_read(&info->generation); + + if (asid != 0) { + u64 newasid = generation | (asid & ~ASID_MASK(info)); + + /* + * If our current ASID was active during a rollover, we + * can continue to use it and this was just a false alarm. + */ + if (check_update_reserved_asid(info, asid, newasid)) + return newasid; + + /* + * We had a valid ASID in a previous life, so try to re-use + * it if possible. + */ + if (!__test_and_set_bit(asid2idx(info, asid), info->map)) + return newasid; + } + + /* + * Allocate a free ASID. If we can't find one, take a note of the + * currently active ASIDs and mark the TLBs as requiring flushes. We + * always count from ASID #2 (index 1), as we use ASID #0 when setting + * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd + * pairs. + */ + asid = find_next_zero_bit(info->map, NUM_CTXT_ASIDS(info), cur_idx); + if (asid != NUM_CTXT_ASIDS(info)) + goto set_asid; + + /* We're out of ASIDs, so increment the global generation count */ + generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION(info), + &info->generation); + flush_context(info); + + /* We have more ASIDs than CPUs, so this will always succeed */ + asid = find_next_zero_bit(info->map, NUM_CTXT_ASIDS(info), 1); + +set_asid: + __set_bit(asid, info->map); + cur_idx = asid; + cpumask_clear(mm_cpumask(mm)); + return idx2asid(info, asid) | generation; +} + +/* + * Generate a new ASID for the context. + * + * @pasid: Pointer to the current ASID batch allocated. It will be updated + * with the new ASID batch. + * @cpu: current CPU ID. Must have been acquired through get_cpu() + */ +void asid_new_context(struct asid_info *info, atomic64_t *pasid, + unsigned int cpu, struct mm_struct *mm) +{ + unsigned long flags; + u64 asid; + + raw_spin_lock_irqsave(&info->lock, flags); + /* Check that our ASID belongs to the current generation. */ + asid = atomic64_read(pasid); + if ((asid ^ atomic64_read(&info->generation)) >> info->bits) { + asid = new_context(info, pasid, mm); + atomic64_set(pasid, asid); + } + + if (cpumask_test_and_clear_cpu(cpu, &info->flush_pending)) + info->flush_cpu_ctxt_cb(); + + atomic64_set(&active_asid(info, cpu), asid); + cpumask_set_cpu(cpu, mm_cpumask(mm)); + raw_spin_unlock_irqrestore(&info->lock, flags); +} + +/* + * Initialize the ASID allocator + * + * @info: Pointer to the asid allocator structure + * @bits: Number of ASIDs available + * @asid_per_ctxt: Number of ASIDs to allocate per-context. ASIDs are + * allocated contiguously for a given context. This value should be a power of + * 2. + */ +int asid_allocator_init(struct asid_info *info, + u32 bits, unsigned int asid_per_ctxt, + void (*flush_cpu_ctxt_cb)(void)) +{ + info->bits = bits; + info->ctxt_shift = ilog2(asid_per_ctxt); + info->flush_cpu_ctxt_cb = flush_cpu_ctxt_cb; + /* + * Expect allocation after rollover to fail if we don't have at least + * one more ASID than CPUs. ASID #0 is always reserved. + */ + WARN_ON(NUM_CTXT_ASIDS(info) - 1 <= num_possible_cpus()); + atomic64_set(&info->generation, ASID_FIRST_VERSION(info)); + info->map = kcalloc(BITS_TO_LONGS(NUM_CTXT_ASIDS(info)), + sizeof(*info->map), GFP_KERNEL); + if (!info->map) + return -ENOMEM; + + raw_spin_lock_init(&info->lock); + + return 0; +} diff --git a/arch/csky/mm/context.c b/arch/csky/mm/context.c new file mode 100644 index 000000000000..0d95bdd93846 --- /dev/null +++ b/arch/csky/mm/context.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. + +#include <linux/bitops.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/mm.h> + +#include <asm/asid.h> +#include <asm/mmu_context.h> +#include <asm/smp.h> +#include <asm/tlbflush.h> + +static DEFINE_PER_CPU(atomic64_t, active_asids); +static DEFINE_PER_CPU(u64, reserved_asids); + +struct asid_info asid_info; + +void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) +{ + asid_check_context(&asid_info, &mm->context.asid, cpu, mm); +} + +static void asid_flush_cpu_ctxt(void) +{ + local_tlb_invalid_all(); +} + +static int asids_init(void) +{ + BUG_ON(((1 << CONFIG_CPU_ASID_BITS) - 1) <= num_possible_cpus()); + + if (asid_allocator_init(&asid_info, CONFIG_CPU_ASID_BITS, 1, + asid_flush_cpu_ctxt)) + panic("Unable to initialize ASID allocator for %lu ASIDs\n", + NUM_ASIDS(&asid_info)); + + asid_info.active = &active_asids; + asid_info.reserved = &reserved_asids; + + pr_info("ASID allocator initialised with %lu entries\n", + NUM_CTXT_ASIDS(&asid_info)); + + return 0; +} +early_initcall(asids_init); diff --git a/arch/csky/mm/init.c b/arch/csky/mm/init.c index 66e597053488..eb0dc9e5065f 100644 --- a/arch/csky/mm/init.c +++ b/arch/csky/mm/init.c @@ -114,8 +114,6 @@ void __init pre_mmu_init(void) TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); TLBMISS_HANDLER_SETUP_PGD_KERNEL(swapper_pg_dir); - asid_cache(smp_processor_id()) = ASID_FIRST_VERSION; - /* Setup page mask to 4k */ write_mmu_pagemask(0); } diff --git a/arch/csky/mm/tlb.c b/arch/csky/mm/tlb.c index 08b8394e5b8f..eb3ba6c9c927 100644 --- a/arch/csky/mm/tlb.c +++ b/arch/csky/mm/tlb.c @@ -10,7 +10,12 @@ #include <asm/pgtable.h> #include <asm/setup.h> -#define CSKY_TLB_SIZE CONFIG_CPU_TLB_SIZE +/* + * One C-SKY MMU TLB entry contain two PFN/page entry, ie: + * 1VPN -> 2PFN + */ +#define TLB_ENTRY_SIZE (PAGE_SIZE * 2) +#define TLB_ENTRY_SIZE_MASK (PAGE_MASK << 1) void flush_tlb_all(void) { @@ -19,201 +24,148 @@ void flush_tlb_all(void) void flush_tlb_mm(struct mm_struct *mm) { - int cpu = smp_processor_id(); - - if (cpu_context(cpu, mm) != 0) - drop_mmu_context(mm, cpu); - +#ifdef CONFIG_CPU_HAS_TLBI + asm volatile("tlbi.asids %0"::"r"(cpu_asid(mm))); +#else tlb_invalid_all(); +#endif } +/* + * MMU operation regs only could invalid tlb entry in jtlb and we + * need change asid field to invalid I-utlb & D-utlb. + */ +#ifndef CONFIG_CPU_HAS_TLBI #define restore_asid_inv_utlb(oldpid, newpid) \ do { \ - if ((oldpid & ASID_MASK) == newpid) \ + if (oldpid == newpid) \ write_mmu_entryhi(oldpid + 1); \ write_mmu_entryhi(oldpid); \ } while (0) +#endif void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) + unsigned long end) { - struct mm_struct *mm = vma->vm_mm; - int cpu = smp_processor_id(); - - if (cpu_context(cpu, mm) != 0) { - unsigned long size, flags; - int newpid = cpu_asid(cpu, mm); - - local_irq_save(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - if (size <= CSKY_TLB_SIZE/2) { - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); -#ifdef CONFIG_CPU_HAS_TLBI - while (start < end) { - asm volatile("tlbi.vaas %0" - ::"r"(start | newpid)); - start += (PAGE_SIZE << 1); - } - sync_is(); -#else - { - int oldpid = read_mmu_entryhi(); - - while (start < end) { - int idx; - - write_mmu_entryhi(start | newpid); - start += (PAGE_SIZE << 1); - tlb_probe(); - idx = read_mmu_index(); - if (idx >= 0) - tlb_invalid_indexed(); - } - restore_asid_inv_utlb(oldpid, newpid); - } -#endif - } else { - drop_mmu_context(mm, cpu); - } - local_irq_restore(flags); - } -} + unsigned long newpid = cpu_asid(vma->vm_mm); -void flush_tlb_kernel_range(unsigned long start, unsigned long end) -{ - unsigned long size, flags; + start &= TLB_ENTRY_SIZE_MASK; + end += TLB_ENTRY_SIZE - 1; + end &= TLB_ENTRY_SIZE_MASK; - local_irq_save(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - if (size <= CSKY_TLB_SIZE) { - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); #ifdef CONFIG_CPU_HAS_TLBI - while (start < end) { - asm volatile("tlbi.vaas %0"::"r"(start)); - start += (PAGE_SIZE << 1); - } - sync_is(); -#else - { - int oldpid = read_mmu_entryhi(); - - while (start < end) { - int idx; - - write_mmu_entryhi(start); - start += (PAGE_SIZE << 1); - tlb_probe(); - idx = read_mmu_index(); - if (idx >= 0) - tlb_invalid_indexed(); - } - restore_asid_inv_utlb(oldpid, 0); - } -#endif - } else { - flush_tlb_all(); + while (start < end) { + asm volatile("tlbi.vas %0"::"r"(start | newpid)); + start += 2*PAGE_SIZE; } + sync_is(); +#else + { + unsigned long flags, oldpid; + + local_irq_save(flags); + oldpid = read_mmu_entryhi() & ASID_MASK; + while (start < end) { + int idx; + write_mmu_entryhi(start | newpid); + start += 2*PAGE_SIZE; + tlb_probe(); + idx = read_mmu_index(); + if (idx >= 0) + tlb_invalid_indexed(); + } + restore_asid_inv_utlb(oldpid, newpid); local_irq_restore(flags); + } +#endif } -void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - int cpu = smp_processor_id(); - int newpid = cpu_asid(cpu, vma->vm_mm); - - if (!vma || cpu_context(cpu, vma->vm_mm) != 0) { - page &= (PAGE_MASK << 1); + start &= TLB_ENTRY_SIZE_MASK; + end += TLB_ENTRY_SIZE - 1; + end &= TLB_ENTRY_SIZE_MASK; #ifdef CONFIG_CPU_HAS_TLBI - asm volatile("tlbi.vaas %0"::"r"(page | newpid)); - sync_is(); + while (start < end) { + asm volatile("tlbi.vaas %0"::"r"(start)); + start += 2*PAGE_SIZE; + } + sync_is(); #else - { - int oldpid, idx; - unsigned long flags; + { + unsigned long flags, oldpid; - local_irq_save(flags); - oldpid = read_mmu_entryhi(); - write_mmu_entryhi(page | newpid); + local_irq_save(flags); + oldpid = read_mmu_entryhi() & ASID_MASK; + while (start < end) { + int idx; + + write_mmu_entryhi(start | oldpid); + start += 2*PAGE_SIZE; tlb_probe(); idx = read_mmu_index(); if (idx >= 0) tlb_invalid_indexed(); - - restore_asid_inv_utlb(oldpid, newpid); - local_irq_restore(flags); - } -#endif } + restore_asid_inv_utlb(oldpid, oldpid); + local_irq_restore(flags); + } +#endif } -/* - * Remove one kernel space TLB entry. This entry is assumed to be marked - * global so we don't do the ASID thing. - */ -void flush_tlb_one(unsigned long page) +void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - int oldpid; + int newpid = cpu_asid(vma->vm_mm); - oldpid = read_mmu_entryhi(); - page &= (PAGE_MASK << 1); + addr &= TLB_ENTRY_SIZE_MASK; #ifdef CONFIG_CPU_HAS_TLBI - page = page | (oldpid & 0xfff); - asm volatile("tlbi.vaas %0"::"r"(page)); + asm volatile("tlbi.vas %0"::"r"(addr | newpid)); sync_is(); #else { - int idx; + int oldpid, idx; unsigned long flags; - page = page | (oldpid & 0xff); - local_irq_save(flags); - write_mmu_entryhi(page); + oldpid = read_mmu_entryhi() & ASID_MASK; + write_mmu_entryhi(addr | newpid); tlb_probe(); idx = read_mmu_index(); if (idx >= 0) tlb_invalid_indexed(); - restore_asid_inv_utlb(oldpid, oldpid); + + restore_asid_inv_utlb(oldpid, newpid); local_irq_restore(flags); } #endif } -EXPORT_SYMBOL(flush_tlb_one); -/* show current 32 jtlbs */ -void show_jtlb_table(void) +void flush_tlb_one(unsigned long addr) { + addr &= TLB_ENTRY_SIZE_MASK; + +#ifdef CONFIG_CPU_HAS_TLBI + asm volatile("tlbi.vaas %0"::"r"(addr)); + sync_is(); +#else + { + int oldpid, idx; unsigned long flags; - int entryhi, entrylo0, entrylo1; - int entry; - int oldpid; local_irq_save(flags); - entry = 0; - pr_info("\n\n\n"); - - oldpid = read_mmu_entryhi(); - while (entry < CSKY_TLB_SIZE) { - write_mmu_index(entry); - tlb_read(); - entryhi = read_mmu_entryhi(); - entrylo0 = read_mmu_entrylo0(); - entrylo0 = entrylo0; - entrylo1 = read_mmu_entrylo1(); - entrylo1 = entrylo1; - pr_info("jtlb[%d]: entryhi - 0x%x; entrylo0 - 0x%x;" - " entrylo1 - 0x%x\n", - entry, entryhi, entrylo0, entrylo1); - entry++; - } - write_mmu_entryhi(oldpid); + oldpid = read_mmu_entryhi() & ASID_MASK; + write_mmu_entryhi(addr | oldpid); + tlb_probe(); + idx = read_mmu_index(); + if (idx >= 0) + tlb_invalid_indexed(); + + restore_asid_inv_utlb(oldpid, oldpid); local_irq_restore(flags); + } +#endif } +EXPORT_SYMBOL(flush_tlb_one); diff --git a/arch/h8300/include/asm/bitops.h b/arch/h8300/include/asm/bitops.h index 647a83bd40b7..7aa16c732aa9 100644 --- a/arch/h8300/include/asm/bitops.h +++ b/arch/h8300/include/asm/bitops.h @@ -51,12 +51,6 @@ static inline void FNAME(int nr, volatile unsigned long *addr) \ } \ } -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - H8300_GEN_BITOP(set_bit, "bset") H8300_GEN_BITOP(clear_bit, "bclr") H8300_GEN_BITOP(change_bit, "bnot") diff --git a/arch/hexagon/include/asm/pgalloc.h b/arch/hexagon/include/asm/pgalloc.h index 3c9e1bd9a3e9..d6544dc71258 100644 --- a/arch/hexagon/include/asm/pgalloc.h +++ b/arch/hexagon/include/asm/pgalloc.h @@ -11,6 +11,8 @@ #include <asm/mem-layout.h> #include <asm/atomic.h> +#include <asm-generic/pgalloc.h> /* for pte_{alloc,free}_one */ + #define check_pgt_cache() do {} while (0) extern unsigned long long kmap_generation; @@ -46,38 +48,6 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) free_page((unsigned long) pgd); } -static inline struct page *pte_alloc_one(struct mm_struct *mm) -{ - struct page *pte; - - pte = alloc_page(GFP_KERNEL | __GFP_ZERO); - if (!pte) - return NULL; - if (!pgtable_page_ctor(pte)) { - __free_page(pte); - return NULL; - } - return pte; -} - -/* _kernel variant gets to use a different allocator */ -static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm) -{ - gfp_t flags = GFP_KERNEL | __GFP_ZERO; - return (pte_t *) __get_free_page(flags); -} - -static inline void pte_free(struct mm_struct *mm, struct page *pte) -{ - pgtable_page_dtor(pte); - __free_page(pte); -} - -static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) -{ - free_page((unsigned long)pte); -} - static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t pte) { diff --git a/arch/hexagon/include/asm/syscall.h b/arch/hexagon/include/asm/syscall.h index 4f054b1ddef5..f6e454f18038 100644 --- a/arch/hexagon/include/asm/syscall.h +++ b/arch/hexagon/include/asm/syscall.h @@ -9,6 +9,8 @@ #define _ASM_HEXAGON_SYSCALL_H #include <uapi/linux/audit.h> +#include <linux/err.h> +#include <asm/ptrace.h> typedef long (*syscall_fn)(unsigned long, unsigned long, unsigned long, unsigned long, @@ -31,6 +33,18 @@ static inline void syscall_get_arguments(struct task_struct *task, memcpy(args, &(®s->r00)[0], 6 * sizeof(args[0])); } +static inline long syscall_get_error(struct task_struct *task, + struct pt_regs *regs) +{ + return IS_ERR_VALUE(regs->r00) ? regs->r00 : 0; +} + +static inline long syscall_get_return_value(struct task_struct *task, + struct pt_regs *regs) +{ + return regs->r00; +} + static inline int syscall_get_arch(struct task_struct *task) { return AUDIT_ARCH_HEXAGON; diff --git a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c index 8f106638913c..3795d18276c4 100644 --- a/arch/ia64/kernel/efi.c +++ b/arch/ia64/kernel/efi.c @@ -852,7 +852,7 @@ valid_phys_addr_range (phys_addr_t phys_addr, unsigned long size) * /dev/mem reads and writes use copy_to_user(), which implicitly * uses a granule-sized kernel identity mapping. It's really * only safe to do this for regions in kern_memmap. For more - * details, see Documentation/ia64/aliasing.txt. + * details, see Documentation/ia64/aliasing.rst. */ attr = kern_mem_attribute(phys_addr, size); if (attr & EFI_MEMORY_WB || attr & EFI_MEMORY_UC) diff --git a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S index d80c99a5f55d..0750a716adc7 100644 --- a/arch/ia64/kernel/fsys.S +++ b/arch/ia64/kernel/fsys.S @@ -28,7 +28,7 @@ #include <asm/native/inst.h> /* - * See Documentation/ia64/fsys.txt for details on fsyscalls. + * See Documentation/ia64/fsys.rst for details on fsyscalls. * * On entry to an fsyscall handler: * r10 = 0 (i.e., defaults to "successful syscall return") diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index 7c52bd2695a2..a23c3938a1c4 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -39,6 +39,7 @@ #include <linux/smp.h> #include <linux/pagemap.h> #include <linux/mount.h> +#include <linux/pseudo_fs.h> #include <linux/bitops.h> #include <linux/capability.h> #include <linux/rcupdate.h> @@ -600,17 +601,19 @@ pfm_unprotect_ctx_ctxsw(pfm_context_t *x, unsigned long f) /* forward declaration */ static const struct dentry_operations pfmfs_dentry_operations; -static struct dentry * -pfmfs_mount(struct file_system_type *fs_type, int flags, const char *dev_name, void *data) +static int pfmfs_init_fs_context(struct fs_context *fc) { - return mount_pseudo(fs_type, "pfm:", NULL, &pfmfs_dentry_operations, - PFMFS_MAGIC); + struct pseudo_fs_context *ctx = init_pseudo(fc, PFMFS_MAGIC); + if (!ctx) + return -ENOMEM; + ctx->dops = &pfmfs_dentry_operations; + return 0; } static struct file_system_type pfm_fs_type = { - .name = "pfmfs", - .mount = pfmfs_mount, - .kill_sb = kill_anon_super, + .name = "pfmfs", + .init_fs_context = pfmfs_init_fs_context, + .kill_sb = kill_anon_super, }; MODULE_ALIAS_FS("pfmfs"); diff --git a/arch/ia64/kernel/syscalls/syscall.tbl b/arch/ia64/kernel/syscalls/syscall.tbl index ecc44926737b..36d5faf4c86c 100644 --- a/arch/ia64/kernel/syscalls/syscall.tbl +++ b/arch/ia64/kernel/syscalls/syscall.tbl @@ -355,3 +355,4 @@ 432 common fsmount sys_fsmount 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open +# 435 reserved for clone3 diff --git a/arch/ia64/mm/fault.c b/arch/ia64/mm/fault.c index 3c3a283d3172..c2f299fe9e04 100644 --- a/arch/ia64/mm/fault.c +++ b/arch/ia64/mm/fault.c @@ -21,28 +21,6 @@ extern int die(char *, struct pt_regs *, long); -#ifdef CONFIG_KPROBES -static inline int notify_page_fault(struct pt_regs *regs, int trap) -{ - int ret = 0; - - if (!user_mode(regs)) { - /* kprobe_running() needs smp_processor_id() */ - preempt_disable(); - if (kprobe_running() && kprobe_fault_handler(regs, trap)) - ret = 1; - preempt_enable(); - } - - return ret; -} -#else -static inline int notify_page_fault(struct pt_regs *regs, int trap) -{ - return 0; -} -#endif - /* * Return TRUE if ADDRESS points at a page in the kernel's mapped segment * (inside region 5, on ia64) and that page is present. @@ -116,7 +94,7 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re /* * This is to handle the kprobes on user space access instructions */ - if (notify_page_fault(regs, TRAP_BRKPT)) + if (kprobe_page_fault(regs, TRAP_BRKPT)) return; if (user_mode(regs)) diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c index d28e29103bdb..aae75fd7b810 100644 --- a/arch/ia64/mm/init.c +++ b/arch/ia64/mm/init.c @@ -681,7 +681,6 @@ int arch_add_memory(int nid, u64 start, u64 size, return ret; } -#ifdef CONFIG_MEMORY_HOTREMOVE void arch_remove_memory(int nid, u64 start, u64 size, struct vmem_altmap *altmap) { @@ -693,4 +692,3 @@ void arch_remove_memory(int nid, u64 start, u64 size, __remove_pages(zone, start_pfn, nr_pages, altmap); } #endif -#endif diff --git a/arch/ia64/mm/ioremap.c b/arch/ia64/mm/ioremap.c index 5e3e7b1fdac5..0c0de2c4ec69 100644 --- a/arch/ia64/mm/ioremap.c +++ b/arch/ia64/mm/ioremap.c @@ -42,7 +42,7 @@ ioremap (unsigned long phys_addr, unsigned long size) /* * For things in kern_memmap, we must use the same attribute * as the rest of the kernel. For more details, see - * Documentation/ia64/aliasing.txt. + * Documentation/ia64/aliasing.rst. */ attr = kern_mem_attribute(phys_addr, size); if (attr & EFI_MEMORY_WB) diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c index e308196c2229..165e561dc81a 100644 --- a/arch/ia64/pci/pci.c +++ b/arch/ia64/pci/pci.c @@ -450,7 +450,7 @@ pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, return -ENOSYS; /* - * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt + * Avoid attribute aliasing. See Documentation/ia64/aliasing.rst * for more details. */ if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) diff --git a/arch/m68k/kernel/syscalls/syscall.tbl b/arch/m68k/kernel/syscalls/syscall.tbl index 9a3eb2558568..a88a285a0e5f 100644 --- a/arch/m68k/kernel/syscalls/syscall.tbl +++ b/arch/m68k/kernel/syscalls/syscall.tbl @@ -434,3 +434,4 @@ 432 common fsmount sys_fsmount 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open +# 435 reserved for clone3 diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c index ba32825ae58a..b3ffe7c898eb 100644 --- a/arch/mips/ar7/setup.c +++ b/arch/mips/ar7/setup.c @@ -57,6 +57,7 @@ const char *get_system_type(void) case TITAN_CHIP_1060: return "TI AR7 (TNETV1060)"; } + /* fall through */ default: return "TI AR7 (unknown)"; } diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index f22538cae0ab..ea385a865781 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -153,7 +153,7 @@ static void __init ath79_detect_sys_type(void) case REV_ID_MAJOR_QCA9533_V2: ver = 2; ath79_soc_rev = 2; - /* drop through */ + /* fall through */ case REV_ID_MAJOR_QCA9533: ath79_soc = ATH79_SOC_QCA9533; diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c index 172dd8397178..a1093934c616 100644 --- a/arch/mips/bcm63xx/dev-flash.c +++ b/arch/mips/bcm63xx/dev-flash.c @@ -94,6 +94,7 @@ static int __init bcm63xx_detect_flash_type(void) case STRAPBUS_6368_BOOT_SEL_PARALLEL: return BCM63XX_FLASH_TYPE_PARALLEL; } + /* fall through */ default: return -EINVAL; } diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 1738a06396f9..2f81a94c71a6 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -162,7 +162,7 @@ void __init plat_mem_setup(void) ioport_resource.start = 0; ioport_resource.end = ~0; - /* intended to somewhat resemble ARM; see Documentation/arm/Booting */ + /* intended to somewhat resemble ARM; see Documentation/arm/booting.rst */ if (fw_arg0 == 0 && fw_arg1 == 0xffffffff) dtb = phys_to_virt(fw_arg2); else if (fw_passed_dtb) /* UHI interface or appended dtb */ diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi index 9ff7e8faaecc..61f8621e88b3 100644 --- a/arch/mips/boot/dts/ralink/mt7628a.dtsi +++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 + / { #address-cells = <1>; #size-cells = <1>; @@ -36,7 +38,113 @@ sysc: system-controller@0 { compatible = "ralink,mt7620a-sysc", "syscon"; - reg = <0x0 0x100>; + reg = <0x0 0x60>; + }; + + pinmux: pinmux@60 { + compatible = "pinctrl-single"; + reg = <0x60 0x8>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x1>; + + pinmux_gpio_gpio: pinmux_gpio_gpio { + pinctrl-single,bits = <0x0 0x0 0x3>; + }; + + pinmux_spi_cs1_cs: pinmux_spi_cs1_cs { + pinctrl-single,bits = <0x0 0x0 0x30>; + }; + + pinmux_i2s_gpio: pinmux_i2s_gpio { + pinctrl-single,bits = <0x0 0x40 0xc0>; + }; + + pinmux_uart0_uart: pinmux_uart0_uart0 { + pinctrl-single,bits = <0x0 0x0 0x300>; + }; + + pinmux_sdmode_sdxc: pinmux_sdmode_sdxc { + pinctrl-single,bits = <0x0 0x0 0xc00>; + }; + + pinmux_sdmode_gpio: pinmux_sdmode_gpio { + pinctrl-single,bits = <0x0 0x400 0xc00>; + }; + + pinmux_spi_spi: pinmux_spi_spi { + pinctrl-single,bits = <0x0 0x0 0x1000>; + }; + + pinmux_refclk_gpio: pinmux_refclk_gpio { + pinctrl-single,bits = <0x0 0x40000 0x40000>; + }; + + pinmux_i2c_i2c: pinmux_i2c_i2c { + pinctrl-single,bits = <0x0 0x0 0x300000>; + }; + + pinmux_uart1_uart: pinmux_uart1_uart1 { + pinctrl-single,bits = <0x0 0x0 0x3000000>; + }; + + pinmux_uart2_uart: pinmux_uart2_uart { + pinctrl-single,bits = <0x0 0x0 0xc000000>; + }; + + pinmux_pwm0_pwm: pinmux_pwm0_pwm { + pinctrl-single,bits = <0x0 0x0 0x30000000>; + }; + + pinmux_pwm0_gpio: pinmux_pwm0_gpio { + pinctrl-single,bits = <0x0 0x10000000 + 0x30000000>; + }; + + pinmux_pwm1_pwm: pinmux_pwm1_pwm { + pinctrl-single,bits = <0x0 0x0 0xc0000000>; + }; + + pinmux_pwm1_gpio: pinmux_pwm1_gpio { + pinctrl-single,bits = <0x0 0x40000000 + 0xc0000000>; + }; + + pinmux_p0led_an_gpio: pinmux_p0led_an_gpio { + pinctrl-single,bits = <0x4 0x4 0xc>; + }; + + pinmux_p1led_an_gpio: pinmux_p1led_an_gpio { + pinctrl-single,bits = <0x4 0x10 0x30>; + }; + + pinmux_p2led_an_gpio: pinmux_p2led_an_gpio { + pinctrl-single,bits = <0x4 0x40 0xc0>; + }; + + pinmux_p3led_an_gpio: pinmux_p3led_an_gpio { + pinctrl-single,bits = <0x4 0x100 0x300>; + }; + + pinmux_p4led_an_gpio: pinmux_p4led_an_gpio { + pinctrl-single,bits = <0x4 0x400 0xc00>; + }; + }; + + watchdog: watchdog@100 { + compatible = "mediatek,mt7621-wdt"; + reg = <0x100 0x30>; + + resets = <&resetc 8>; + reset-names = "wdt"; + + interrupt-parent = <&intc>; + interrupts = <24>; + + status = "disabled"; }; intc: interrupt-controller@200 { @@ -62,10 +170,42 @@ reg = <0x300 0x100>; }; + gpio: gpio@600 { + compatible = "mediatek,mt7621-gpio"; + reg = <0x600 0x100>; + + gpio-controller; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <6>; + }; + + spi: spi@b00 { + compatible = "ralink,mt7621-spi"; + reg = <0xb00 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_spi_spi>; + + resets = <&resetc 18>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + uart0: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart0_uart>; + resets = <&resetc 12>; reset-names = "uart0"; @@ -79,6 +219,9 @@ compatible = "ns16550a"; reg = <0xd00 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart1_uart>; + resets = <&resetc 19>; reset-names = "uart1"; @@ -92,6 +235,9 @@ compatible = "ns16550a"; reg = <0xe00 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart2_uart>; + resets = <&resetc 20>; reset-names = "uart2"; diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c index 676fab50dd2b..b077597c668a 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-pko.c +++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c @@ -485,11 +485,11 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, config.s.qos_mask = 0xff; break; case CVMX_PKO_QUEUE_STATIC_PRIORITY: - /* Pass 1 will fall through to the error case */ if (!cvmx_octeon_is_pass1()) { config.s.qos_mask = 0xff; break; } + /* fall through - to the error case, when Pass 1 */ default: cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid " "priority %llu\n", diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig index c83fdf649327..cef2754bd408 100644 --- a/arch/mips/configs/ar7_defconfig +++ b/arch/mips/configs/ar7_defconfig @@ -71,7 +71,6 @@ CONFIG_NET_ACT_POLICE=y CONFIG_HAMRADIO=y CONFIG_CFG80211=m CONFIG_MAC80211=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/mips/configs/ath25_defconfig b/arch/mips/configs/ath25_defconfig index 5dd6b1939e9c..c35add2fd716 100644 --- a/arch/mips/configs/ath25_defconfig +++ b/arch/mips/configs/ath25_defconfig @@ -37,7 +37,6 @@ CONFIG_IP_ADVANCED_ROUTER=y CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_MAC80211_DEBUGFS=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2 diff --git a/arch/mips/configs/ath79_defconfig b/arch/mips/configs/ath79_defconfig index 6f981af67826..4ffc59cab436 100644 --- a/arch/mips/configs/ath79_defconfig +++ b/arch/mips/configs/ath79_defconfig @@ -37,7 +37,6 @@ CONFIG_IP_ADVANCED_ROUTER=y CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_MAC80211_DEBUGFS=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2 diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig index d22fe62adad3..54e2f9a659fb 100644 --- a/arch/mips/configs/bcm63xx_defconfig +++ b/arch/mips/configs/bcm63xx_defconfig @@ -34,7 +34,6 @@ CONFIG_INET=y CONFIG_CFG80211=y CONFIG_NL80211_TESTMODE=y CONFIG_MAC80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_MTD=y diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 597bc0aa2653..66566026409d 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -99,7 +99,6 @@ CONFIG_BPQETHER=m CONFIG_BAYCOM_SER_FDX=m CONFIG_BAYCOM_SER_HDX=m CONFIG_YAM=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m diff --git a/arch/mips/configs/bmips_be_defconfig b/arch/mips/configs/bmips_be_defconfig index 8a91f0101134..f669a40e085b 100644 --- a/arch/mips/configs/bmips_be_defconfig +++ b/arch/mips/configs/bmips_be_defconfig @@ -26,7 +26,6 @@ CONFIG_INET=y CONFIG_CFG80211=y CONFIG_NL80211_TESTMODE=y CONFIG_MAC80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set diff --git a/arch/mips/configs/bmips_stb_defconfig b/arch/mips/configs/bmips_stb_defconfig index 39adcca46bb0..a0b775893dba 100644 --- a/arch/mips/configs/bmips_stb_defconfig +++ b/arch/mips/configs/bmips_stb_defconfig @@ -35,7 +35,6 @@ CONFIG_INET=y CONFIG_CFG80211=y CONFIG_NL80211_TESTMODE=y CONFIG_MAC80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig index d7abb648b8a0..b6695367aa33 100644 --- a/arch/mips/configs/cavium_octeon_defconfig +++ b/arch/mips/configs/cavium_octeon_defconfig @@ -42,7 +42,6 @@ CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y # CONFIG_FW_LOADER is not set CONFIG_MTD=y diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index 50bebce28500..cb4aa23a2bf4 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -44,7 +44,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y # CONFIG_FW_LOADER is not set # CONFIG_ALLOW_DEV_COREDUMP is not set diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index 20c62841827f..c6a652ad34f7 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -14,7 +14,6 @@ CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_CFI_AMDSTD=y diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig index 8bcb61a6ec15..7a7af706e898 100644 --- a/arch/mips/configs/fuloong2e_defconfig +++ b/arch/mips/configs/fuloong2e_defconfig @@ -83,7 +83,6 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_PHONET=m CONFIG_NET_9P=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=m CONFIG_MTD_BLOCK=m diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig index 9d9af5f923c3..9085f4d6c698 100644 --- a/arch/mips/configs/gpr_defconfig +++ b/arch/mips/configs/gpr_defconfig @@ -249,7 +249,6 @@ CONFIG_WATCHDOG_NOWAYOUT=y CONFIG_SSB=m CONFIG_SSB_DRIVER_PCICORE=y # CONFIG_VGA_ARB is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 54db5dedf776..82d942a6026e 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -91,7 +91,6 @@ CONFIG_NET_ACT_SKBEDIT=m CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_RFKILL=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_CDROM_PKTCDVD=m diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index 8f6d8af2e3c0..572cab91670c 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -42,7 +42,6 @@ CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_TUNNEL=m CONFIG_NETWORK_SECMARK=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_CONNECTOR=y CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index 300127b0f5b7..d44f1469cf64 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -77,7 +77,6 @@ CONFIG_MAC80211=m CONFIG_MAC80211_LEDS=y CONFIG_RFKILL=m CONFIG_RFKILL_INPUT=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_RAM=y @@ -144,7 +143,6 @@ CONFIG_FB_TILEBLITTING=y CONFIG_FB_SIS=y CONFIG_FB_SIS_300=y CONFIG_FB_SIS_315=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GENERIC=m diff --git a/arch/mips/configs/loongson1b_defconfig b/arch/mips/configs/loongson1b_defconfig index 3d390a7494d6..25e70423e17d 100644 --- a/arch/mips/configs/loongson1b_defconfig +++ b/arch/mips/configs/loongson1b_defconfig @@ -34,7 +34,6 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set diff --git a/arch/mips/configs/loongson1c_defconfig b/arch/mips/configs/loongson1c_defconfig index 247d56e94c0a..3a158d4d2fab 100644 --- a/arch/mips/configs/loongson1c_defconfig +++ b/arch/mips/configs/loongson1c_defconfig @@ -35,7 +35,6 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig index 1322adb705c8..90ee0084d786 100644 --- a/arch/mips/configs/loongson3_defconfig +++ b/arch/mips/configs/loongson3_defconfig @@ -97,7 +97,6 @@ CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m CONFIG_RFKILL=m CONFIG_RFKILL_INPUT=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=m diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 0de92ac1ca64..59eedf55419d 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -214,7 +214,6 @@ CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_MAC80211_MESH=y CONFIG_RFKILL=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_CONNECTOR=m CONFIG_MTD=y diff --git a/arch/mips/configs/malta_kvm_defconfig b/arch/mips/configs/malta_kvm_defconfig index efc3abace048..8ef612552a19 100644 --- a/arch/mips/configs/malta_kvm_defconfig +++ b/arch/mips/configs/malta_kvm_defconfig @@ -219,7 +219,6 @@ CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_MAC80211_MESH=y CONFIG_RFKILL=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_CONNECTOR=m CONFIG_MTD=y diff --git a/arch/mips/configs/malta_kvm_guest_defconfig b/arch/mips/configs/malta_kvm_guest_defconfig index c6ceeca4394d..d2a008c9907c 100644 --- a/arch/mips/configs/malta_kvm_guest_defconfig +++ b/arch/mips/configs/malta_kvm_guest_defconfig @@ -216,7 +216,6 @@ CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_MAC80211_MESH=y CONFIG_RFKILL=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_CONNECTOR=m CONFIG_MTD=y diff --git a/arch/mips/configs/maltaup_xpa_defconfig b/arch/mips/configs/maltaup_xpa_defconfig index 56861aef2756..970df6d42728 100644 --- a/arch/mips/configs/maltaup_xpa_defconfig +++ b/arch/mips/configs/maltaup_xpa_defconfig @@ -216,7 +216,6 @@ CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_MAC80211_MESH=y CONFIG_RFKILL=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_CONNECTOR=m diff --git a/arch/mips/configs/mips_paravirt_defconfig b/arch/mips/configs/mips_paravirt_defconfig index 8dc5d96a08de..5599cde97030 100644 --- a/arch/mips/configs/mips_paravirt_defconfig +++ b/arch/mips/configs/mips_paravirt_defconfig @@ -39,7 +39,6 @@ CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_BLK_DEV_LOOP=y CONFIG_VIRTIO_BLK=y diff --git a/arch/mips/configs/omega2p_defconfig b/arch/mips/configs/omega2p_defconfig index 0649b8f06b7c..a39426e57e91 100644 --- a/arch/mips/configs/omega2p_defconfig +++ b/arch/mips/configs/omega2p_defconfig @@ -42,7 +42,6 @@ CONFIG_INET=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y # CONFIG_FW_LOADER is not set # CONFIG_ALLOW_DEV_COREDUMP is not set diff --git a/arch/mips/configs/pistachio_defconfig b/arch/mips/configs/pistachio_defconfig index 2f08d071ada6..24e07180c57d 100644 --- a/arch/mips/configs/pistachio_defconfig +++ b/arch/mips/configs/pistachio_defconfig @@ -214,7 +214,6 @@ CONFIG_IR_IMG_RC6=y CONFIG_MEDIA_SUPPORT=y CONFIG_FB=y CONFIG_FB_MODE_HELPERS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_SOUND=y diff --git a/arch/mips/configs/pnx8335_stb225_defconfig b/arch/mips/configs/pnx8335_stb225_defconfig index aa0b169800e0..738ba3b1374b 100644 --- a/arch/mips/configs/pnx8335_stb225_defconfig +++ b/arch/mips/configs/pnx8335_stb225_defconfig @@ -25,7 +25,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_INET_AH=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/mips/configs/qi_lb60_defconfig b/arch/mips/configs/qi_lb60_defconfig index 1a0677d04982..208da8a55f48 100644 --- a/arch/mips/configs/qi_lb60_defconfig +++ b/arch/mips/configs/qi_lb60_defconfig @@ -41,7 +41,6 @@ CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_WESTWOOD=y # CONFIG_TCP_CONG_HTCP is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_RAW_NAND=y @@ -77,7 +76,6 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_FB=y CONFIG_FB_JZ4740=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y # CONFIG_BACKLIGHT_CLASS_DEVICE is not set # CONFIG_VGA_CONSOLE is not set diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig index 864c70fbe668..5b947183852b 100644 --- a/arch/mips/configs/rb532_defconfig +++ b/arch/mips/configs/rb532_defconfig @@ -104,7 +104,6 @@ CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_PEDIT=m CONFIG_HAMRADIO=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK2MTD=y diff --git a/arch/mips/configs/rt305x_defconfig b/arch/mips/configs/rt305x_defconfig index 0392e38010e6..110948bc6b39 100644 --- a/arch/mips/configs/rt305x_defconfig +++ b/arch/mips/configs/rt305x_defconfig @@ -69,7 +69,6 @@ CONFIG_BRIDGE=y CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y CONFIG_HAMRADIO=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/mips/configs/sb1250_swarm_defconfig b/arch/mips/configs/sb1250_swarm_defconfig index ad8981666ee4..6883ea4477d4 100644 --- a/arch/mips/configs/sb1250_swarm_defconfig +++ b/arch/mips/configs/sb1250_swarm_defconfig @@ -43,7 +43,6 @@ CONFIG_NETWORK_SECMARK=y CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_RFKILL=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_CONNECTOR=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index f0a11a72307e..6547f84750b5 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig @@ -28,7 +28,6 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set CONFIG_NETWORK_SECMARK=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index 025e45656359..7e099f7c2286 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -26,7 +26,6 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set CONFIG_NETWORK_SECMARK=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index 68490248e3f1..0d881dd862c0 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -30,7 +30,6 @@ CONFIG_TCP_CONG_BIC=y CONFIG_TCP_CONG_CUBIC=m # CONFIG_IPV6 is not set CONFIG_NETWORK_SECMARK=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/mips/configs/vocore2_defconfig b/arch/mips/configs/vocore2_defconfig index ded3dce911d5..523b944fd527 100644 --- a/arch/mips/configs/vocore2_defconfig +++ b/arch/mips/configs/vocore2_defconfig @@ -42,7 +42,6 @@ CONFIG_INET=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y # CONFIG_FW_LOADER is not set # CONFIG_ALLOW_DEV_COREDUMP is not set diff --git a/arch/mips/configs/xway_defconfig b/arch/mips/configs/xway_defconfig index 203db83c3ee9..49b5ea6eff62 100644 --- a/arch/mips/configs/xway_defconfig +++ b/arch/mips/configs/xway_defconfig @@ -71,7 +71,6 @@ CONFIG_BRIDGE=y CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y CONFIG_HAMRADIO=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 6ad7d3cabd91..290369fa44a4 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -9,6 +9,8 @@ #ifndef _ASM_CPU_H #define _ASM_CPU_H +#include <linux/bits.h> + /* As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 register 15, select 0) is defined in this (backwards compatible) way: @@ -353,76 +355,69 @@ enum cpu_type_enum { MIPS_CPU_ISA_M64R6) /* - * Private version of BIT_ULL() to escape include file recursion hell. - * We soon will have to switch to another mechanism that will work with - * more than 64 bits anyway. - */ -#define MBIT_ULL(bit) (1ULL << (bit)) - -/* * CPU Option encodings */ -#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */ -#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */ -#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */ -#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */ -#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */ -#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */ -#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */ -#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */ -#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */ -#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */ -#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */ -#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */ -#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */ -#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */ -#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */ -#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */ -#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */ -#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */ -#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */ -#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */ -#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */ -#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */ -#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */ -#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */ -#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */ -#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */ -#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ -#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */ -#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */ -#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */ -#define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */ -#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */ -#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */ -#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */ -#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */ -#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */ -#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */ -#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */ -#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */ -#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */ -#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */ -#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */ -#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */ -#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */ -#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */ -#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */ -#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */ -#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */ -#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */ -#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */ -#define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */ +#define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */ +#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */ +#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */ +#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */ +#define MIPS_CPU_TX39_CACHE BIT_ULL( 4) /* TX3900-style caches */ +#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */ +#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */ +#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */ +#define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */ +#define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */ +#define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */ +#define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */ +#define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */ +#define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */ +#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */ +#define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */ +#define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */ +#define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */ +#define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */ +#define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */ +#define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */ +#define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */ +#define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */ +#define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */ +#define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ +#define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */ +#define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */ +#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */ +#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */ +#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */ +#define MIPS_CPU_BP_GHIST BIT_ULL(35) /* R12K+ Branch Prediction Global History */ +#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */ +#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */ +#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */ +#define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */ +#define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */ +#define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */ +#define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */ +#define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */ +#define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */ +#define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */ +#define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */ +#define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */ +#define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */ +#define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */ +#define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */ +#define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */ +#define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */ +#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */ #define MIPS_CPU_SHARED_FTLB_RAM \ - MBIT_ULL(54) /* CPU shares FTLB RAM with another */ + BIT_ULL(54) /* CPU shares FTLB RAM with another */ #define MIPS_CPU_SHARED_FTLB_ENTRIES \ - MBIT_ULL(55) /* CPU shares FTLB entries with another */ + BIT_ULL(55) /* CPU shares FTLB entries with another */ #define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \ - MBIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */ -#define MIPS_CPU_MMID MBIT_ULL(57) /* CPU supports MemoryMapIDs */ + BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */ +#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */ /* * CPU ASE encodings diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 29997e42480e..97a280640daf 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -149,8 +149,6 @@ static inline void *isa_bus_to_virt(unsigned long address) return phys_to_virt(address); } -#define isa_page_to_bus page_to_phys - /* * However PCI ones are not necessarily 1:1 and therefore these interfaces * are forbidden in portable PCI drivers. @@ -462,7 +460,12 @@ __BUILD_MEMORY_PFX(, bwlq, type, 0) BUILDIO_MEM(b, u8) BUILDIO_MEM(w, u16) BUILDIO_MEM(l, u32) +#ifdef CONFIG_64BIT BUILDIO_MEM(q, u64) +#else +__BUILD_MEMORY_PFX(__raw_, q, u64, 0) +__BUILD_MEMORY_PFX(__mem_, q, u64, 0) +#endif #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \ @@ -488,12 +491,16 @@ __BUILDIO(q, u64) #define readb_relaxed __relaxed_readb #define readw_relaxed __relaxed_readw #define readl_relaxed __relaxed_readl +#ifdef CONFIG_64BIT #define readq_relaxed __relaxed_readq +#endif #define writeb_relaxed __relaxed_writeb #define writew_relaxed __relaxed_writew #define writel_relaxed __relaxed_writel +#ifdef CONFIG_64BIT #define writeq_relaxed __relaxed_writeq +#endif #define readb_be(addr) \ __raw_readb((__force unsigned *)(addr)) @@ -516,8 +523,10 @@ __BUILDIO(q, u64) /* * Some code tests for these symbols */ +#ifdef CONFIG_64BIT #define readq readq #define writeq writeq +#endif #define __BUILD_MEMORY_STRING(bwlq, type) \ \ diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h index 3cf8e4d5fa28..68b1e5d458cf 100644 --- a/arch/mips/include/asm/kprobes.h +++ b/arch/mips/include/asm/kprobes.h @@ -41,6 +41,7 @@ do { \ #define kretprobe_blacklist_size 0 void arch_remove_kprobe(struct kprobe *p); +int kprobe_fault_handler(struct pt_regs *regs, int trapnr); /* Architecture specific copy of original instruction*/ struct arch_specific_insn { diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h deleted file mode 100644 index 600d5051691a..000000000000 --- a/arch/mips/include/asm/mach-jz4740/clock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> - */ - -#ifndef __ASM_JZ4740_CLOCK_H__ -#define __ASM_JZ4740_CLOCK_H__ - -enum jz4740_wait_mode { - JZ4740_WAIT_MODE_IDLE, - JZ4740_WAIT_MODE_SLEEP, -}; - -void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode); - -void jz4740_clock_suspend(void); -void jz4740_clock_resume(void); - -void jz4740_clock_udc_enable_auto_suspend(void); -void jz4740_clock_udc_disable_auto_suspend(void); - -#endif diff --git a/arch/mips/include/asm/mach-ralink/pinmux.h b/arch/mips/include/asm/mach-ralink/pinmux.h index e54d4e1533b4..048309348be0 100644 --- a/arch/mips/include/asm/mach-ralink/pinmux.h +++ b/arch/mips/include/asm/mach-ralink/pinmux.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * * Copyright (C) 2012 John Crispin <john@phrozen.org> */ diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h index acf80ae0a430..83bb439597d8 100644 --- a/arch/mips/include/asm/syscall.h +++ b/arch/mips/include/asm/syscall.h @@ -89,6 +89,12 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg, unreachable(); } +static inline long syscall_get_error(struct task_struct *task, + struct pt_regs *regs) +{ + return regs->regs[7] ? -regs->regs[2] : 0; +} + static inline long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) { diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 071e9d94eea7..4a7a80c358c7 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -37,8 +37,6 @@ #include <asm/mach-jz4740/platform.h> -#include "clock.h" - /* GPIOs */ #define QI_LB60_GPIO_KEYOUT(x) (JZ_GPIO_PORTC(10) + (x)) #define QI_LB60_GPIO_KEYIN(x) (JZ_GPIO_PORTD(18) + (x)) @@ -466,27 +464,27 @@ static unsigned long pin_cfg_bias_disable[] = { static struct pinctrl_map pin_map[] __initdata = { /* NAND pin configuration */ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand", - "10010000.jz4740-pinctrl", "nand", "nand-cs1"), + "10010000.pin-controller", "nand-cs1", "nand"), /* fbdev pin configuration */ PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT, - "10010000.jz4740-pinctrl", "lcd", "lcd-8bit"), + "10010000.pin-controller", "lcd-8bit", "lcd"), PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP, - "10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"), + "10010000.pin-controller", "lcd-no-pins", "lcd"), /* MMC pin configuration */ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0", - "10010000.jz4740-pinctrl", "mmc", "mmc-1bit"), + "10010000.pin-controller", "mmc-1bit", "mmc"), PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0", - "10010000.jz4740-pinctrl", "mmc", "mmc-4bit"), + "10010000.pin-controller", "mmc-4bit", "mmc"), PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0", - "10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable), + "10010000.pin-controller", "PD0", pin_cfg_bias_disable), PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0", - "10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable), + "10010000.pin-controller", "PD2", pin_cfg_bias_disable), /* PWM pin configuration */ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm", - "10010000.jz4740-pinctrl", "pwm4", "pwm4"), + "10010000.pin-controller", "pwm4", "pwm4"), }; diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c index 4b89abb17950..c74c99f5951d 100644 --- a/arch/mips/jz4740/platform.c +++ b/arch/mips/jz4740/platform.c @@ -21,8 +21,6 @@ #include <linux/serial_core.h> #include <linux/serial_8250.h> -#include "clock.h" - /* USB Device Controller */ struct platform_device jz4740_udc_xceiv_device = { .name = "usb_phy_generic", diff --git a/arch/mips/jz4740/pm.c b/arch/mips/jz4740/pm.c index bbdd2b801e6e..f9b551f01f42 100644 --- a/arch/mips/jz4740/pm.c +++ b/arch/mips/jz4740/pm.c @@ -9,21 +9,13 @@ #include <linux/delay.h> #include <linux/suspend.h> -#include <asm/mach-jz4740/clock.h> - static int jz4740_pm_enter(suspend_state_t state) { - jz4740_clock_suspend(); - - jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP); - __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0"); - jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE); - jz4740_clock_resume(); return 0; } diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c index a3260c754e65..cb768e560d8b 100644 --- a/arch/mips/jz4740/time.c +++ b/arch/mips/jz4740/time.c @@ -13,13 +13,10 @@ #include <linux/clockchips.h> #include <linux/sched_clock.h> -#include <asm/mach-jz4740/clock.h> #include <asm/mach-jz4740/irq.h> #include <asm/mach-jz4740/timer.h> #include <asm/time.h> -#include "clock.h" - #define TIMER_CLOCKEVENT 0 #define TIMER_CLOCKSOURCE 1 diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 4b5e1f2bfbce..2625232bfe52 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -333,20 +333,21 @@ void prepare_ftrace_return(unsigned long *parent_ra_addr, unsigned long self_ra, return; /* - * "parent_ra_addr" is the stack address saved the return address of - * the caller of _mcount. + * "parent_ra_addr" is the stack address where the return address of + * the caller of _mcount is saved. * - * if the gcc < 4.5, a leaf function does not save the return address - * in the stack address, so, we "emulate" one in _mcount's stack space, - * and hijack it directly, but for a non-leaf function, it save the - * return address to the its own stack space, we can not hijack it - * directly, but need to find the real stack address, - * ftrace_get_parent_addr() does it! + * If gcc < 4.5, a leaf function does not save the return address + * in the stack address, so we "emulate" one in _mcount's stack space, + * and hijack it directly. + * For a non-leaf function, it does save the return address to its own + * stack space, so we can not hijack it directly, but need to find the + * real stack address, which is done by ftrace_get_parent_addr(). * - * if gcc>= 4.5, with the new -mmcount-ra-address option, for a + * If gcc >= 4.5, with the new -mmcount-ra-address option, for a * non-leaf function, the location of the return address will be saved - * to $12 for us, and for a leaf function, only put a zero into $12. we - * do it in ftrace_graph_caller of mcount.S. + * to $12 for us. + * For a leaf function, it just puts a zero into $12, so we handle + * it in ftrace_graph_caller() of mcount.S. */ /* old_parent_ra = *parent_ra_addr; */ diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c index 81ba1d3c367c..6cfae2411c04 100644 --- a/arch/mips/kernel/kprobes.c +++ b/arch/mips/kernel/kprobes.c @@ -398,7 +398,7 @@ out: return 1; } -static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr) +int kprobe_fault_handler(struct pt_regs *regs, int trapnr) { struct kprobe *cur = kprobe_running(); struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index e0ebaa0a333e..a3e2da8391ea 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -790,15 +790,19 @@ static void reset_counters(void *arg) case 4: mipsxx_pmu_write_control(3, 0); mipspmu.write_counter(3, 0); + /* fall through */ case 3: mipsxx_pmu_write_control(2, 0); mipspmu.write_counter(2, 0); + /* fall through */ case 2: mipsxx_pmu_write_control(1, 0); mipspmu.write_counter(1, 0); + /* fall through */ case 1: mipsxx_pmu_write_control(0, 0); mipspmu.write_counter(0, 0); + /* fall through */ } } @@ -1380,7 +1384,7 @@ static int mipsxx_pmu_handle_shared_irq(void) struct perf_sample_data data; unsigned int counters = mipspmu.num_counters; u64 counter; - int handled = IRQ_NONE; + int n, handled = IRQ_NONE; struct pt_regs *regs; if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI)) @@ -1401,20 +1405,16 @@ static int mipsxx_pmu_handle_shared_irq(void) perf_sample_data_init(&data, 0, 0); - switch (counters) { -#define HANDLE_COUNTER(n) \ - case n + 1: \ - if (test_bit(n, cpuc->used_mask)) { \ - counter = mipspmu.read_counter(n); \ - if (counter & mipspmu.overflow) { \ - handle_associated_event(cpuc, n, &data, regs); \ - handled = IRQ_HANDLED; \ - } \ - } - HANDLE_COUNTER(3) - HANDLE_COUNTER(2) - HANDLE_COUNTER(1) - HANDLE_COUNTER(0) + for (n = counters - 1; n >= 0; n--) { + if (!test_bit(n, cpuc->used_mask)) + continue; + + counter = mipspmu.read_counter(n); + if (!(counter & mipspmu.overflow)) + continue; + + handle_associated_event(cpuc, n, &data, regs); + handled = IRQ_HANDLED; } #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS diff --git a/arch/mips/kernel/syscalls/syscall_n32.tbl b/arch/mips/kernel/syscalls/syscall_n32.tbl index 97035e19ad03..c9c879ec9b6d 100644 --- a/arch/mips/kernel/syscalls/syscall_n32.tbl +++ b/arch/mips/kernel/syscalls/syscall_n32.tbl @@ -373,3 +373,4 @@ 432 n32 fsmount sys_fsmount 433 n32 fspick sys_fspick 434 n32 pidfd_open sys_pidfd_open +# 435 reserved for clone3 diff --git a/arch/mips/kernel/syscalls/syscall_n64.tbl b/arch/mips/kernel/syscalls/syscall_n64.tbl index d7292722d3b0..bbce9159caa1 100644 --- a/arch/mips/kernel/syscalls/syscall_n64.tbl +++ b/arch/mips/kernel/syscalls/syscall_n64.tbl @@ -349,3 +349,4 @@ 432 n64 fsmount sys_fsmount 433 n64 fspick sys_fspick 434 n64 pidfd_open sys_pidfd_open +# 435 reserved for clone3 diff --git a/arch/mips/kernel/syscalls/syscall_o32.tbl b/arch/mips/kernel/syscalls/syscall_o32.tbl index dba084c92f14..9653591428ec 100644 --- a/arch/mips/kernel/syscalls/syscall_o32.tbl +++ b/arch/mips/kernel/syscalls/syscall_o32.tbl @@ -422,3 +422,4 @@ 432 o32 fsmount sys_fsmount 433 o32 fspick sys_fspick 434 o32 pidfd_open sys_pidfd_open +# 435 reserved for clone3 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index cfd87e662fcf..115b417dfb8e 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -20,13 +20,13 @@ #include <irq.h> /* register definitions - internal irqs */ -#define LTQ_ICU_IM0_ISR 0x0000 -#define LTQ_ICU_IM0_IER 0x0008 -#define LTQ_ICU_IM0_IOSR 0x0010 -#define LTQ_ICU_IM0_IRSR 0x0018 -#define LTQ_ICU_IM0_IMR 0x0020 -#define LTQ_ICU_IM1_ISR 0x0028 -#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) +#define LTQ_ICU_ISR 0x0000 +#define LTQ_ICU_IER 0x0008 +#define LTQ_ICU_IOSR 0x0010 +#define LTQ_ICU_IRSR 0x0018 +#define LTQ_ICU_IMR 0x0020 + +#define LTQ_ICU_IM_SIZE 0x28 /* register definitions - external irqs */ #define LTQ_EIU_EXIN_C 0x0000 @@ -46,24 +46,25 @@ */ #define LTQ_ICU_EBU_IRQ 22 -#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y)) -#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x)) +#define ltq_icu_w32(vpe, m, x, y) \ + ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y)) + +#define ltq_icu_r32(vpe, m, x) \ + ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x)) #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) -/* our 2 ipi interrupts for VSMP */ -#define MIPS_CPU_IPI_RESCHED_IRQ 0 -#define MIPS_CPU_IPI_CALL_IRQ 1 - /* we have a cascade of 8 irqs */ #define MIPS_CPU_IRQ_CASCADE 8 static int exin_avail; static u32 ltq_eiu_irq[MAX_EIU]; -static void __iomem *ltq_icu_membase[MAX_IM]; +static void __iomem *ltq_icu_membase[NR_CPUS]; static void __iomem *ltq_eiu_membase; static struct irq_domain *ltq_domain; +static DEFINE_SPINLOCK(ltq_eiu_lock); +static DEFINE_RAW_SPINLOCK(ltq_icu_lock); static int ltq_perfcount_irq; int ltq_eiu_get_irq(int exin) @@ -75,49 +76,84 @@ int ltq_eiu_get_irq(int exin) void ltq_disable_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; - int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + unsigned long im = offset / INT_NUM_IM_OFFSET; + unsigned long flags; + int vpe; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); + + raw_spin_lock_irqsave(<q_icu_lock, flags); + for_each_present_cpu(vpe) { + ltq_icu_w32(vpe, im, + ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset), + LTQ_ICU_IER); + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); } void ltq_mask_and_ack_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; - u32 isr = LTQ_ICU_IM0_ISR; - int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + unsigned long im = offset / INT_NUM_IM_OFFSET; + unsigned long flags; + int vpe; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); - ltq_icu_w32(im, BIT(offset), isr); + + raw_spin_lock_irqsave(<q_icu_lock, flags); + for_each_present_cpu(vpe) { + ltq_icu_w32(vpe, im, + ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset), + LTQ_ICU_IER); + ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR); + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); } static void ltq_ack_irq(struct irq_data *d) { - u32 isr = LTQ_ICU_IM0_ISR; - int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + unsigned long im = offset / INT_NUM_IM_OFFSET; + unsigned long flags; + int vpe; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, BIT(offset), isr); + + raw_spin_lock_irqsave(<q_icu_lock, flags); + for_each_present_cpu(vpe) { + ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR); + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); } void ltq_enable_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; - int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + unsigned long im = offset / INT_NUM_IM_OFFSET; + unsigned long flags; + int vpe; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); + + vpe = cpumask_first(irq_data_get_effective_affinity_mask(d)); + + /* This shouldn't be even possible, maybe during CPU hotplug spam */ + if (unlikely(vpe >= nr_cpu_ids)) + vpe = smp_processor_id(); + + raw_spin_lock_irqsave(<q_icu_lock, flags); + + ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset), + LTQ_ICU_IER); + + raw_spin_unlock_irqrestore(<q_icu_lock, flags); } static int ltq_eiu_settype(struct irq_data *d, unsigned int type) { int i; + unsigned long flags; for (i = 0; i < exin_avail; i++) { if (d->hwirq == ltq_eiu_irq[i]) { @@ -154,8 +190,11 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type) if (edge) irq_set_handler(d->hwirq, handle_edge_irq); - ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | - (val << (i * 4)), LTQ_EIU_EXIN_C); + spin_lock_irqsave(<q_eiu_lock, flags); + ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) & + (~(7 << (i * 4)))) | (val << (i * 4)), + LTQ_EIU_EXIN_C); + spin_unlock_irqrestore(<q_eiu_lock, flags); } } @@ -199,6 +238,21 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d) } } +#if defined(CONFIG_SMP) +static int ltq_icu_irq_set_affinity(struct irq_data *d, + const struct cpumask *cpumask, bool force) +{ + struct cpumask tmask; + + if (!cpumask_and(&tmask, cpumask, cpu_online_mask)) + return -EINVAL; + + irq_data_update_effective_affinity(d, &tmask); + + return IRQ_SET_MASK_OK; +} +#endif + static struct irq_chip ltq_irq_type = { .name = "icu", .irq_enable = ltq_enable_irq, @@ -207,6 +261,9 @@ static struct irq_chip ltq_irq_type = { .irq_ack = ltq_ack_irq, .irq_mask = ltq_disable_irq, .irq_mask_ack = ltq_mask_and_ack_irq, +#if defined(CONFIG_SMP) + .irq_set_affinity = ltq_icu_irq_set_affinity, +#endif }; static struct irq_chip ltq_eiu_type = { @@ -220,15 +277,19 @@ static struct irq_chip ltq_eiu_type = { .irq_mask = ltq_disable_irq, .irq_mask_ack = ltq_mask_and_ack_irq, .irq_set_type = ltq_eiu_settype, +#if defined(CONFIG_SMP) + .irq_set_affinity = ltq_icu_irq_set_affinity, +#endif }; static void ltq_hw_irq_handler(struct irq_desc *desc) { - int module = irq_desc_get_irq(desc) - 2; + unsigned int module = irq_desc_get_irq(desc) - 2; u32 irq; - int hwirq; + irq_hw_number_t hwirq; + int vpe = smp_processor_id(); - irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR); + irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR); if (irq == 0) return; @@ -249,6 +310,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc) static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { struct irq_chip *chip = <q_irq_type; + struct irq_data *data; int i; if (hw < MIPS_CPU_IRQ_CASCADE) @@ -258,6 +320,10 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) if (hw == ltq_eiu_irq[i]) chip = <q_eiu_type; + data = irq_get_irq_data(irq); + + irq_data_update_effective_affinity(data, cpumask_of(0)); + irq_set_chip_and_handler(irq, chip, handle_level_irq); return 0; @@ -272,28 +338,37 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) { struct device_node *eiu_node; struct resource res; - int i, ret; + int i, ret, vpe; - for (i = 0; i < MAX_IM; i++) { - if (of_address_to_resource(node, i, &res)) - panic("Failed to get icu memory range"); + /* load register regions of available ICUs */ + for_each_possible_cpu(vpe) { + if (of_address_to_resource(node, vpe, &res)) + panic("Failed to get icu%i memory range", vpe); if (!request_mem_region(res.start, resource_size(&res), res.name)) - pr_err("Failed to request icu memory"); + pr_err("Failed to request icu%i memory\n", vpe); - ltq_icu_membase[i] = ioremap_nocache(res.start, + ltq_icu_membase[vpe] = ioremap_nocache(res.start, resource_size(&res)); - if (!ltq_icu_membase[i]) - panic("Failed to remap icu memory"); + + if (!ltq_icu_membase[vpe]) + panic("Failed to remap icu%i memory", vpe); } /* turn off all irqs by default */ - for (i = 0; i < MAX_IM; i++) { - /* make sure all irqs are turned off by default */ - ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER); - /* clear all possibly pending interrupts */ - ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR); + for_each_possible_cpu(vpe) { + for (i = 0; i < MAX_IM; i++) { + /* make sure all irqs are turned off by default */ + ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER); + + /* clear all possibly pending interrupts */ + ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR); + ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR); + + /* clear resend */ + ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR); + } } mips_cpu_irq_init(); @@ -347,7 +422,7 @@ unsigned int get_c0_compare_int(void) return CP0_LEGACY_COMPARE_IRQ; } -static struct of_device_id __initdata of_irq_ids[] = { +static const struct of_device_id of_irq_ids[] __initconst = { { .compatible = "lantiq,icu", .data = icu_of_init }, {}, }; diff --git a/arch/nds32/include/asm/syscall.h b/arch/nds32/include/asm/syscall.h index 899b2fb4b52f..7b5180d78e20 100644 --- a/arch/nds32/include/asm/syscall.h +++ b/arch/nds32/include/asm/syscall.h @@ -26,7 +26,8 @@ struct pt_regs; * * It's only valid to call this when @task is known to be blocked. */ -int syscall_get_nr(struct task_struct *task, struct pt_regs *regs) +static inline int +syscall_get_nr(struct task_struct *task, struct pt_regs *regs) { return regs->syscallno; } @@ -47,7 +48,8 @@ int syscall_get_nr(struct task_struct *task, struct pt_regs *regs) * system call instruction. This may not be the same as what the * register state looked like at system call entry tracing. */ -void syscall_rollback(struct task_struct *task, struct pt_regs *regs) +static inline void +syscall_rollback(struct task_struct *task, struct pt_regs *regs) { regs->uregs[0] = regs->orig_r0; } @@ -62,7 +64,8 @@ void syscall_rollback(struct task_struct *task, struct pt_regs *regs) * It's only valid to call this when @task is stopped for tracing on exit * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. */ -long syscall_get_error(struct task_struct *task, struct pt_regs *regs) +static inline long +syscall_get_error(struct task_struct *task, struct pt_regs *regs) { unsigned long error = regs->uregs[0]; return IS_ERR_VALUE(error) ? error : 0; @@ -79,7 +82,8 @@ long syscall_get_error(struct task_struct *task, struct pt_regs *regs) * It's only valid to call this when @task is stopped for tracing on exit * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. */ -long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) +static inline long +syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) { return regs->uregs[0]; } @@ -99,8 +103,9 @@ long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) * It's only valid to call this when @task is stopped for tracing on exit * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. */ -void syscall_set_return_value(struct task_struct *task, struct pt_regs *regs, - int error, long val) +static inline void +syscall_set_return_value(struct task_struct *task, struct pt_regs *regs, + int error, long val) { regs->uregs[0] = (long)error ? error : val; } @@ -118,8 +123,9 @@ void syscall_set_return_value(struct task_struct *task, struct pt_regs *regs, * entry to a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. */ #define SYSCALL_MAX_ARGS 6 -void syscall_get_arguments(struct task_struct *task, struct pt_regs *regs, - unsigned long *args) +static inline void +syscall_get_arguments(struct task_struct *task, struct pt_regs *regs, + unsigned long *args) { args[0] = regs->orig_r0; args++; @@ -138,8 +144,9 @@ void syscall_get_arguments(struct task_struct *task, struct pt_regs *regs, * It's only valid to call this when @task is stopped for tracing on * entry to a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. */ -void syscall_set_arguments(struct task_struct *task, struct pt_regs *regs, - const unsigned long *args) +static inline void +syscall_set_arguments(struct task_struct *task, struct pt_regs *regs, + const unsigned long *args) { regs->orig_r0 = args[0]; args++; diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 42875ff15671..6d732e451071 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -277,7 +277,7 @@ config SMP machines, but will use only one CPU of a multiprocessor machine. On a uniprocessor machine, the kernel will run faster if you say N. - See also <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO + See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at <http://www.tldp.org/docs.html#howto>. If you don't know what to do here, say N. diff --git a/arch/parisc/include/asm/kprobes.h b/arch/parisc/include/asm/kprobes.h index e09cf2deeafe..904034da4974 100644 --- a/arch/parisc/include/asm/kprobes.h +++ b/arch/parisc/include/asm/kprobes.h @@ -50,6 +50,10 @@ struct kprobe_ctlblk { int __kprobes parisc_kprobe_break_handler(struct pt_regs *regs); int __kprobes parisc_kprobe_ss_handler(struct pt_regs *regs); +static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr) +{ + return 0; +} #endif /* CONFIG_KPROBES */ #endif /* _PARISC_KPROBES_H */ diff --git a/arch/parisc/include/asm/syscall.h b/arch/parisc/include/asm/syscall.h index 80757e43cf2c..00b127a5e09b 100644 --- a/arch/parisc/include/asm/syscall.h +++ b/arch/parisc/include/asm/syscall.h @@ -29,6 +29,13 @@ static inline void syscall_get_arguments(struct task_struct *tsk, args[0] = regs->gr[26]; } +static inline long syscall_get_error(struct task_struct *task, + struct pt_regs *regs) +{ + unsigned long error = regs->gr[28]; + return IS_ERR_VALUE(error) ? error : 0; +} + static inline long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) { diff --git a/arch/parisc/include/asm/unistd.h b/arch/parisc/include/asm/unistd.h index b0838dc4dfee..cd438e4150f6 100644 --- a/arch/parisc/include/asm/unistd.h +++ b/arch/parisc/include/asm/unistd.h @@ -166,6 +166,7 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \ #define __ARCH_WANT_SYS_FORK #define __ARCH_WANT_SYS_VFORK #define __ARCH_WANT_SYS_CLONE +#define __ARCH_WANT_SYS_CLONE3 #define __ARCH_WANT_COMPAT_SYS_SENDFILE #ifdef CONFIG_64BIT diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index 3e430590c1e1..d9d3387f7c47 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -1732,6 +1732,7 @@ ENDPROC_CFI(sys_\name\()_wrapper) .endm fork_like clone +fork_like clone3 fork_like fork fork_like vfork diff --git a/arch/parisc/kernel/kprobes.c b/arch/parisc/kernel/kprobes.c index d58960b33bda..5d7f2692ac5a 100644 --- a/arch/parisc/kernel/kprobes.c +++ b/arch/parisc/kernel/kprobes.c @@ -133,6 +133,9 @@ int __kprobes parisc_kprobe_ss_handler(struct pt_regs *regs) struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); struct kprobe *p = kprobe_running(); + if (!p) + return 0; + if (regs->iaoq[0] != (unsigned long)p->ainsn.insn+4) return 0; diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S index ba67893a1d72..df46b0e5a915 100644 --- a/arch/parisc/kernel/pacache.S +++ b/arch/parisc/kernel/pacache.S @@ -63,7 +63,7 @@ ENTRY_CFI(flush_tlb_all_local) /* Flush Instruction Tlb */ - LDREG ITLB_SID_BASE(%r1), %r20 +88: LDREG ITLB_SID_BASE(%r1), %r20 LDREG ITLB_SID_STRIDE(%r1), %r21 LDREG ITLB_SID_COUNT(%r1), %r22 LDREG ITLB_OFF_BASE(%r1), %arg0 @@ -103,6 +103,7 @@ fitonemiddle: /* Loop if LOOP = 1 */ add %r21, %r20, %r20 /* increment space */ fitdone: + ALTERNATIVE(88b, fitdone, ALT_COND_NO_SPLIT_TLB, INSN_NOP) /* Flush Data Tlb */ diff --git a/arch/parisc/kernel/ptrace.c b/arch/parisc/kernel/ptrace.c index f642ba378ffa..9f6ff7bc06f9 100644 --- a/arch/parisc/kernel/ptrace.c +++ b/arch/parisc/kernel/ptrace.c @@ -167,6 +167,9 @@ long arch_ptrace(struct task_struct *child, long request, if ((addr & (sizeof(unsigned long)-1)) || addr >= sizeof(struct pt_regs)) break; + if (addr == PT_IAOQ0 || addr == PT_IAOQ1) { + data |= 3; /* ensure userspace privilege */ + } if ((addr >= PT_GR1 && addr <= PT_GR31) || addr == PT_IAOQ0 || addr == PT_IAOQ1 || (addr >= PT_FR0 && addr <= PT_FR31 + 4) || @@ -228,16 +231,18 @@ long arch_ptrace(struct task_struct *child, long request, static compat_ulong_t translate_usr_offset(compat_ulong_t offset) { - if (offset < 0) - return sizeof(struct pt_regs); - else if (offset <= 32*4) /* gr[0..31] */ - return offset * 2 + 4; - else if (offset <= 32*4+32*8) /* gr[0..31] + fr[0..31] */ - return offset + 32*4; - else if (offset < sizeof(struct pt_regs)/2 + 32*4) - return offset * 2 + 4 - 32*8; + compat_ulong_t pos; + + if (offset < 32*4) /* gr[0..31] */ + pos = offset * 2 + 4; + else if (offset < 32*4+32*8) /* fr[0] ... fr[31] */ + pos = (offset - 32*4) + PT_FR0; + else if (offset < sizeof(struct pt_regs)/2 + 32*4) /* sr[0] ... ipsw */ + pos = (offset - 32*4 - 32*8) * 2 + PT_SR0 + 4; else - return sizeof(struct pt_regs); + pos = sizeof(struct pt_regs); + + return pos; } long compat_arch_ptrace(struct task_struct *child, compat_long_t request, @@ -281,9 +286,12 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, addr = translate_usr_offset(addr); if (addr >= sizeof(struct pt_regs)) break; + if (addr == PT_IAOQ0+4 || addr == PT_IAOQ1+4) { + data |= 3; /* ensure userspace privilege */ + } if (addr >= PT_FR0 && addr <= PT_FR31 + 4) { /* Special case, fp regs are 64 bits anyway */ - *(__u64 *) ((char *) task_regs(child) + addr) = data; + *(__u32 *) ((char *) task_regs(child) + addr) = data; ret = 0; } else if ((addr >= PT_GR1+4 && addr <= PT_GR31+4) || @@ -496,7 +504,8 @@ static void set_reg(struct pt_regs *regs, int num, unsigned long val) return; case RI(iaoq[0]): case RI(iaoq[1]): - regs->iaoq[num - RI(iaoq[0])] = val; + /* set 2 lowest bits to ensure userspace privilege: */ + regs->iaoq[num - RI(iaoq[0])] = val | 3; return; case RI(sar): regs->sar = val; return; diff --git a/arch/parisc/kernel/syscalls/syscall.tbl b/arch/parisc/kernel/syscalls/syscall.tbl index 5022b9e179c2..670d1371aca1 100644 --- a/arch/parisc/kernel/syscalls/syscall.tbl +++ b/arch/parisc/kernel/syscalls/syscall.tbl @@ -431,3 +431,4 @@ 432 common fsmount sys_fsmount 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open +435 common clone3 sys_clone3_wrapper diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 5c96d3c948cd..77f6ebf97113 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -130,6 +130,7 @@ config PPC select ARCH_HAS_MMIOWB if PPC64 select ARCH_HAS_PHYS_TO_DMA select ARCH_HAS_PMEM_API if PPC64 + select ARCH_HAS_PTE_DEVMAP if PPC_BOOK3S_64 select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_MEMBARRIER_CALLBACKS select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC64 @@ -137,7 +138,6 @@ config PPC select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UACCESS_FLUSHCACHE if PPC64 select ARCH_HAS_UBSAN_SANITIZE_ALL - select ARCH_HAS_ZONE_DEVICE if PPC_BOOK3S_64 select ARCH_HAVE_NMI_SAFE_CMPXCHG select ARCH_KEEP_MEMBLOCK select ARCH_MIGHT_HAVE_PC_PARPORT diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h index 62e6ea0a7650..8308f32e9782 100644 --- a/arch/powerpc/include/asm/book3s/64/pgtable.h +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h @@ -90,7 +90,6 @@ #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ -#define __HAVE_ARCH_PTE_DEVMAP /* * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE diff --git a/arch/powerpc/include/asm/syscall.h b/arch/powerpc/include/asm/syscall.h index 81abcf6a737b..38d62acfdce7 100644 --- a/arch/powerpc/include/asm/syscall.h +++ b/arch/powerpc/include/asm/syscall.h @@ -35,6 +35,16 @@ static inline void syscall_rollback(struct task_struct *task, regs->gpr[3] = regs->orig_gpr3; } +static inline long syscall_get_error(struct task_struct *task, + struct pt_regs *regs) +{ + /* + * If the system call failed, + * regs->gpr[3] contains a positive ERRORCODE. + */ + return (regs->ccr & 0x10000000UL) ? -regs->gpr[3] : 0; +} + static inline long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) { diff --git a/arch/powerpc/include/uapi/asm/kvm_para.h b/arch/powerpc/include/uapi/asm/kvm_para.h index 01555c6ae0f5..be48c2215fa2 100644 --- a/arch/powerpc/include/uapi/asm/kvm_para.h +++ b/arch/powerpc/include/uapi/asm/kvm_para.h @@ -31,7 +31,7 @@ * Struct fields are always 32 or 64 bit aligned, depending on them being 32 * or 64 bit wide respectively. * - * See Documentation/virtual/kvm/ppc-pv.txt + * See Documentation/virt/kvm/ppc-pv.txt */ struct kvm_vcpu_arch_shared { __u64 scratch1; diff --git a/arch/powerpc/include/uapi/asm/mman.h b/arch/powerpc/include/uapi/asm/mman.h index 65065ce32814..c0c737215b00 100644 --- a/arch/powerpc/include/uapi/asm/mman.h +++ b/arch/powerpc/include/uapi/asm/mman.h @@ -21,15 +21,11 @@ #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ + #define MCL_CURRENT 0x2000 /* lock all currently mapped pages */ #define MCL_FUTURE 0x4000 /* lock all additions to address space */ #define MCL_ONFAULT 0x8000 /* lock all pages that are faulted in */ -#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ -#define MAP_STACK 0x20000 /* give out an address that is best suited for process/thread stacks */ -#define MAP_HUGETLB 0x40000 /* create a huge page mapping */ - /* Override any generic PKEY permission defines */ #define PKEY_DISABLE_EXECUTE 0x4 #undef PKEY_ACCESS_MASK diff --git a/arch/powerpc/kernel/syscalls/syscall.tbl b/arch/powerpc/kernel/syscalls/syscall.tbl index f2c3bda2d39f..3331749aab20 100644 --- a/arch/powerpc/kernel/syscalls/syscall.tbl +++ b/arch/powerpc/kernel/syscalls/syscall.tbl @@ -516,3 +516,4 @@ 432 common fsmount sys_fsmount 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open +# 435 reserved for clone3 diff --git a/arch/powerpc/kvm/book3s_64_vio.c b/arch/powerpc/kvm/book3s_64_vio.c index 5bf05cc774e2..e99a14798ab0 100644 --- a/arch/powerpc/kvm/book3s_64_vio.c +++ b/arch/powerpc/kvm/book3s_64_vio.c @@ -19,6 +19,7 @@ #include <linux/anon_inodes.h> #include <linux/iommu.h> #include <linux/file.h> +#include <linux/mm.h> #include <asm/kvm_ppc.h> #include <asm/kvm_book3s.h> @@ -45,43 +46,6 @@ static unsigned long kvmppc_stt_pages(unsigned long tce_pages) return tce_pages + ALIGN(stt_bytes, PAGE_SIZE) / PAGE_SIZE; } -static long kvmppc_account_memlimit(unsigned long stt_pages, bool inc) -{ - long ret = 0; - - if (!current || !current->mm) - return ret; /* process exited */ - - down_write(¤t->mm->mmap_sem); - - if (inc) { - unsigned long locked, lock_limit; - - locked = current->mm->locked_vm + stt_pages; - lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT; - if (locked > lock_limit && !capable(CAP_IPC_LOCK)) - ret = -ENOMEM; - else - current->mm->locked_vm += stt_pages; - } else { - if (WARN_ON_ONCE(stt_pages > current->mm->locked_vm)) - stt_pages = current->mm->locked_vm; - - current->mm->locked_vm -= stt_pages; - } - - pr_debug("[%d] RLIMIT_MEMLOCK KVM %c%ld %ld/%ld%s\n", current->pid, - inc ? '+' : '-', - stt_pages << PAGE_SHIFT, - current->mm->locked_vm << PAGE_SHIFT, - rlimit(RLIMIT_MEMLOCK), - ret ? " - exceeded" : ""); - - up_write(¤t->mm->mmap_sem); - - return ret; -} - static void kvm_spapr_tce_iommu_table_free(struct rcu_head *head) { struct kvmppc_spapr_tce_iommu_table *stit = container_of(head, @@ -291,7 +255,7 @@ static int kvm_spapr_tce_release(struct inode *inode, struct file *filp) kvm_put_kvm(stt->kvm); - kvmppc_account_memlimit( + account_locked_vm(current->mm, kvmppc_stt_pages(kvmppc_tce_pages(stt->size)), false); call_rcu(&stt->rcu, release_spapr_tce_table); @@ -316,7 +280,7 @@ long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm, return -EINVAL; npages = kvmppc_tce_pages(size); - ret = kvmppc_account_memlimit(kvmppc_stt_pages(npages), true); + ret = account_locked_vm(current->mm, kvmppc_stt_pages(npages), true); if (ret) return ret; @@ -362,7 +326,7 @@ long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm, kfree(stt); fail_acct: - kvmppc_account_memlimit(kvmppc_stt_pages(npages), false); + account_locked_vm(current->mm, kvmppc_stt_pages(npages), false); return ret; } diff --git a/arch/powerpc/mm/book3s64/iommu_api.c b/arch/powerpc/mm/book3s64/iommu_api.c index 90ee3a89722c..b056cae3388b 100644 --- a/arch/powerpc/mm/book3s64/iommu_api.c +++ b/arch/powerpc/mm/book3s64/iommu_api.c @@ -14,6 +14,7 @@ #include <linux/hugetlb.h> #include <linux/swap.h> #include <linux/sizes.h> +#include <linux/mm.h> #include <asm/mmu_context.h> #include <asm/pte-walk.h> #include <linux/mm_inline.h> @@ -46,40 +47,6 @@ struct mm_iommu_table_group_mem_t { u64 dev_hpa; /* Device memory base address */ }; -static long mm_iommu_adjust_locked_vm(struct mm_struct *mm, - unsigned long npages, bool incr) -{ - long ret = 0, locked, lock_limit; - - if (!npages) - return 0; - - down_write(&mm->mmap_sem); - - if (incr) { - locked = mm->locked_vm + npages; - lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT; - if (locked > lock_limit && !capable(CAP_IPC_LOCK)) - ret = -ENOMEM; - else - mm->locked_vm += npages; - } else { - if (WARN_ON_ONCE(npages > mm->locked_vm)) - npages = mm->locked_vm; - mm->locked_vm -= npages; - } - - pr_debug("[%d] RLIMIT_MEMLOCK HASH64 %c%ld %ld/%ld\n", - current ? current->pid : 0, - incr ? '+' : '-', - npages << PAGE_SHIFT, - mm->locked_vm << PAGE_SHIFT, - rlimit(RLIMIT_MEMLOCK)); - up_write(&mm->mmap_sem); - - return ret; -} - bool mm_iommu_preregistered(struct mm_struct *mm) { return !list_empty(&mm->context.iommu_group_mem_list); @@ -96,7 +63,7 @@ static long mm_iommu_do_alloc(struct mm_struct *mm, unsigned long ua, unsigned long entry, chunk; if (dev_hpa == MM_IOMMU_TABLE_INVALID_HPA) { - ret = mm_iommu_adjust_locked_vm(mm, entries, true); + ret = account_locked_vm(mm, entries, true); if (ret) return ret; @@ -211,7 +178,7 @@ free_exit: kfree(mem); unlock_exit: - mm_iommu_adjust_locked_vm(mm, locked_entries, false); + account_locked_vm(mm, locked_entries, false); return ret; } @@ -311,7 +278,7 @@ long mm_iommu_put(struct mm_struct *mm, struct mm_iommu_table_group_mem_t *mem) unlock_exit: mutex_unlock(&mem_list_mutex); - mm_iommu_adjust_locked_vm(mm, unlock_entries, false); + account_locked_vm(mm, unlock_entries, false); return ret; } diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/book3s64/radix_pgtable.c index 65c2ba1e1783..b4ca9e95e678 100644 --- a/arch/powerpc/mm/book3s64/radix_pgtable.c +++ b/arch/powerpc/mm/book3s64/radix_pgtable.c @@ -1237,3 +1237,8 @@ int radix__ioremap_range(unsigned long ea, phys_addr_t pa, unsigned long size, return 0; } } + +int __init arch_ioremap_p4d_supported(void) +{ + return 0; +} diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index d989592b6fc8..8432c281de92 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -42,26 +42,6 @@ #include <asm/debug.h> #include <asm/kup.h> -static inline bool notify_page_fault(struct pt_regs *regs) -{ - bool ret = false; - -#ifdef CONFIG_KPROBES - /* kprobe_running() needs smp_processor_id() */ - if (!user_mode(regs)) { - preempt_disable(); - if (kprobe_running() && kprobe_fault_handler(regs, 11)) - ret = true; - preempt_enable(); - } -#endif /* CONFIG_KPROBES */ - - if (unlikely(debugger_fault_handler(regs))) - ret = true; - - return ret; -} - /* * Check whether the instruction inst is a store using * an update addressing form which will update r1. @@ -461,8 +441,9 @@ static int __do_page_fault(struct pt_regs *regs, unsigned long address, int is_write = page_fault_is_write(error_code); vm_fault_t fault, major = 0; bool must_retry = false; + bool kprobe_fault = kprobe_page_fault(regs, 11); - if (notify_page_fault(regs)) + if (unlikely(debugger_fault_handler(regs) || kprobe_fault)) return 0; if (unlikely(page_fault_is_bad(error_code))) { diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index b6beb86e5300..9191a66b3bc5 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c @@ -125,23 +125,14 @@ int __ref arch_add_memory(int nid, u64 start, u64 size, return __add_pages(nid, start_pfn, nr_pages, restrictions); } -#ifdef CONFIG_MEMORY_HOTREMOVE void __ref arch_remove_memory(int nid, u64 start, u64 size, struct vmem_altmap *altmap) { unsigned long start_pfn = start >> PAGE_SHIFT; unsigned long nr_pages = size >> PAGE_SHIFT; - struct page *page; + struct page *page = pfn_to_page(start_pfn) + vmem_altmap_offset(altmap); int ret; - /* - * If we have an altmap then we need to skip over any reserved PFNs - * when querying the zone. - */ - page = pfn_to_page(start_pfn); - if (altmap) - page += vmem_altmap_offset(altmap); - __remove_pages(page_zone(page), start_pfn, nr_pages, altmap); /* Remove htab bolted mappings for this section of memory */ @@ -159,7 +150,6 @@ void __ref arch_remove_memory(int nid, u64 start, u64 size, pr_warn("Hash collision while resizing HPT\n"); } #endif -#endif /* CONFIG_MEMORY_HOTPLUG */ #ifndef CONFIG_NEED_MULTIPLE_NODES void __init mem_topology_setup(void) diff --git a/arch/powerpc/platforms/powernv/memtrace.c b/arch/powerpc/platforms/powernv/memtrace.c index 5e53c1392d3b..eb2e75dac369 100644 --- a/arch/powerpc/platforms/powernv/memtrace.c +++ b/arch/powerpc/platforms/powernv/memtrace.c @@ -70,23 +70,23 @@ static int change_memblock_state(struct memory_block *mem, void *arg) /* called with device_hotplug_lock held */ static bool memtrace_offline_pages(u32 nid, u64 start_pfn, u64 nr_pages) { - u64 end_pfn = start_pfn + nr_pages - 1; + const unsigned long start = PFN_PHYS(start_pfn); + const unsigned long size = PFN_PHYS(nr_pages); - if (walk_memory_range(start_pfn, end_pfn, NULL, - check_memblock_online)) + if (walk_memory_blocks(start, size, NULL, check_memblock_online)) return false; - walk_memory_range(start_pfn, end_pfn, (void *)MEM_GOING_OFFLINE, - change_memblock_state); + walk_memory_blocks(start, size, (void *)MEM_GOING_OFFLINE, + change_memblock_state); if (offline_pages(start_pfn, nr_pages)) { - walk_memory_range(start_pfn, end_pfn, (void *)MEM_ONLINE, - change_memblock_state); + walk_memory_blocks(start, size, (void *)MEM_ONLINE, + change_memblock_state); return false; } - walk_memory_range(start_pfn, end_pfn, (void *)MEM_OFFLINE, - change_memblock_state); + walk_memory_blocks(start, size, (void *)MEM_OFFLINE, + change_memblock_state); return true; @@ -242,9 +242,8 @@ static int memtrace_online(void) */ if (!memhp_auto_online) { lock_device_hotplug(); - walk_memory_range(PFN_DOWN(ent->start), - PFN_UP(ent->start + ent->size - 1), - NULL, online_mem_block); + walk_memory_blocks(ent->start, ent->size, NULL, + online_mem_block); unlock_device_hotplug(); } diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 13a1c0d04e9e..59a4727ecd6c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -52,6 +52,8 @@ config RISCV select ARCH_HAS_MMIOWB select HAVE_EBPF_JIT if 64BIT select EDAC_SUPPORT + select ARCH_HAS_GIGANTIC_PAGE + select ARCH_WANT_HUGE_PMD_SHARE if 64BIT config MMU def_bool y @@ -66,6 +68,12 @@ config PAGE_OFFSET default 0xffffffff80000000 if 64BIT && MAXPHYSMEM_2GB default 0xffffffe000000000 if 64BIT && MAXPHYSMEM_128GB +config ARCH_WANT_GENERAL_HUGETLB + def_bool y + +config SYS_SUPPORTS_HUGETLBFS + def_bool y + config STACKTRACE_SUPPORT def_bool y @@ -97,6 +105,8 @@ config PGTABLE_LEVELS default 3 if 64BIT default 2 +source "arch/riscv/Kconfig.socs" + menu "Platform type" choice diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs new file mode 100644 index 000000000000..536c0ef4aee8 --- /dev/null +++ b/arch/riscv/Kconfig.socs @@ -0,0 +1,13 @@ +menu "SoC selection" + +config SOC_SIFIVE + bool "SiFive SoCs" + select SERIAL_SIFIVE + select SERIAL_SIFIVE_CONSOLE + select CLK_SIFIVE + select CLK_SIFIVE_FU540_PRCI + select SIFIVE_PLIC + help + This enables support for SiFive SoC platform hardware. + +endmenu diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index f8b3b07e4247..7a117be8297c 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -34,8 +34,6 @@ else KBUILD_LDFLAGS += -melf32lriscv endif -KBUILD_CFLAGS += -Wall - # ISA string setting riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile index baaeef9efdcb..6d6189e6e4af 100644 --- a/arch/riscv/boot/dts/sifive/Makefile +++ b/arch/riscv/boot/dts/sifive/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-y += hifive-unleashed-a00.dtb +dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 04944fb4fa7a..b7b749b18853 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -1,5 +1,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y @@ -12,6 +14,7 @@ CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_BPF_SYSCALL=y +CONFIG_SOC_SIFIVE=y CONFIG_SMP=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -49,8 +52,6 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y -CONFIG_SERIAL_SIFIVE=y -CONFIG_SERIAL_SIFIVE_CONSOLE=y CONFIG_HVC_RISCV_SBI=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_DRM=y @@ -66,9 +67,6 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_STORAGE=y CONFIG_USB_UAS=y CONFIG_VIRTIO_MMIO=y -CONFIG_CLK_SIFIVE=y -CONFIG_CLK_SIFIVE_FU540_PRCI=y -CONFIG_SIFIVE_PLIC=y CONFIG_SPI_SIFIVE=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index 1a911ed8e772..d5449ef805a3 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -1,5 +1,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index ad8678f1b54a..555b20b11dc3 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -6,11 +6,66 @@ #ifndef _ASM_RISCV_CACHEFLUSH_H #define _ASM_RISCV_CACHEFLUSH_H -#include <asm-generic/cacheflush.h> +#include <linux/mm.h> -#undef flush_icache_range -#undef flush_icache_user_range -#undef flush_dcache_page +#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 + +/* + * The cache doesn't need to be flushed when TLB entries change when + * the cache is mapped to physical memory, not virtual memory + */ +static inline void flush_cache_all(void) +{ +} + +static inline void flush_cache_mm(struct mm_struct *mm) +{ +} + +static inline void flush_cache_dup_mm(struct mm_struct *mm) +{ +} + +static inline void flush_cache_range(struct vm_area_struct *vma, + unsigned long start, + unsigned long end) +{ +} + +static inline void flush_cache_page(struct vm_area_struct *vma, + unsigned long vmaddr, + unsigned long pfn) +{ +} + +static inline void flush_dcache_mmap_lock(struct address_space *mapping) +{ +} + +static inline void flush_dcache_mmap_unlock(struct address_space *mapping) +{ +} + +static inline void flush_icache_page(struct vm_area_struct *vma, + struct page *page) +{ +} + +static inline void flush_cache_vmap(unsigned long start, unsigned long end) +{ +} + +static inline void flush_cache_vunmap(unsigned long start, unsigned long end) +{ +} + +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ + do { \ + memcpy(dst, src, len); \ + flush_icache_user_range(vma, page, vaddr, len); \ + } while (0) +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) static inline void local_flush_icache_all(void) { diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h index c207f6634b91..9c66033c3a54 100644 --- a/arch/riscv/include/asm/fixmap.h +++ b/arch/riscv/include/asm/fixmap.h @@ -21,6 +21,11 @@ */ enum fixed_addresses { FIX_HOLE, +#define FIX_FDT_SIZE SZ_1M + FIX_FDT_END, + FIX_FDT = FIX_FDT_END + FIX_FDT_SIZE / PAGE_SIZE - 1, + FIX_PTE, + FIX_PMD, FIX_EARLYCON_MEM_BASE, __end_of_fixed_addresses }; diff --git a/arch/riscv/include/asm/hugetlb.h b/arch/riscv/include/asm/hugetlb.h new file mode 100644 index 000000000000..728a5db66597 --- /dev/null +++ b/arch/riscv/include/asm/hugetlb.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_HUGETLB_H +#define _ASM_RISCV_HUGETLB_H + +#include <asm-generic/hugetlb.h> +#include <asm/page.h> + +static inline int is_hugepage_only_range(struct mm_struct *mm, + unsigned long addr, + unsigned long len) { + return 0; +} + +static inline void arch_clear_hugepage_flags(struct page *page) +{ +} + +#endif /* _ASM_RISCV_HUGETLB_H */ diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h new file mode 100644 index 000000000000..ef28e106f247 --- /dev/null +++ b/arch/riscv/include/asm/image.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __ASM_IMAGE_H +#define __ASM_IMAGE_H + +#define RISCV_IMAGE_MAGIC "RISCV" + +#define RISCV_IMAGE_FLAG_BE_SHIFT 0 +#define RISCV_IMAGE_FLAG_BE_MASK 0x1 + +#define RISCV_IMAGE_FLAG_LE 0 +#define RISCV_IMAGE_FLAG_BE 1 + +#ifdef CONFIG_CPU_BIG_ENDIAN +#error conversion of header fields to LE not yet implemented +#else +#define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE +#endif + +#define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \ + RISCV_IMAGE_FLAG_##field##_SHIFT) + +#define __HEAD_FLAGS (__HEAD_FLAG(BE)) + +#define RISCV_HEADER_VERSION_MAJOR 0 +#define RISCV_HEADER_VERSION_MINOR 1 + +#define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \ + RISCV_HEADER_VERSION_MINOR) + +#ifndef __ASSEMBLY__ +/** + * struct riscv_image_header - riscv kernel image header + * @code0: Executable code + * @code1: Executable code + * @text_offset: Image load offset (little endian) + * @image_size: Effective Image size (little endian) + * @flags: kernel flags (little endian) + * @version: version + * @res1: reserved + * @res2: reserved + * @magic: Magic number + * @res3: reserved (will be used for additional RISC-V specific + * header) + * @res4: reserved (will be used for PE COFF offset) + * + * The intention is for this header format to be shared between multiple + * architectures to avoid a proliferation of image header formats. + */ + +struct riscv_image_header { + u32 code0; + u32 code1; + u64 text_offset; + u64 image_size; + u64 flags; + u32 version; + u32 res1; + u64 res2; + u64 magic; + u32 res3; + u32 res4; +}; +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_IMAGE_H */ diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 8ddb6c7fedac..707e00a8430b 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -16,6 +16,16 @@ #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE - 1)) +#ifdef CONFIG_64BIT +#define HUGE_MAX_HSTATE 2 +#else +#define HUGE_MAX_HSTATE 1 +#endif +#define HPAGE_SHIFT PMD_SHIFT +#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) +#define HPAGE_MASK (~(HPAGE_SIZE - 1)) +#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) + /* * PAGE_OFFSET -- the first address of the first page of memory. * When not using MMU this corresponds to the first free page in @@ -115,8 +125,4 @@ extern unsigned long min_low_pfn; #include <asm-generic/memory_model.h> #include <asm-generic/getorder.h> -/* vDSO support */ -/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */ -#define __HAVE_ARCH_GATE_AREA - #endif /* _ASM_RISCV_PAGE_H */ diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index 45dfac2ac51f..74630989006d 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -70,6 +70,11 @@ static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot) return __pmd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); } +static inline unsigned long _pmd_pfn(pmd_t pmd) +{ + return pmd_val(pmd) >> _PAGE_PFN_SHIFT; +} + #define pmd_ERROR(e) \ pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index f7c3f7de15f2..a364aba23d55 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -59,6 +59,8 @@ #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) +#define PAGE_TABLE __pgprot(_PAGE_TABLE) + extern pgd_t swapper_pg_dir[]; /* MAP_PRIVATE permissions: xwr (copy-on-write) */ @@ -113,12 +115,16 @@ static inline void pmd_clear(pmd_t *pmdp) set_pmd(pmdp, __pmd(0)); } - static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) { return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); } +static inline unsigned long _pgd_pfn(pgd_t pgd) +{ + return pgd_val(pgd) >> _PAGE_PFN_SHIFT; +} + #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) /* Locate an entry in the page global directory */ @@ -250,6 +256,11 @@ static inline pte_t pte_mkspecial(pte_t pte) return __pte(pte_val(pte) | _PAGE_SPECIAL); } +static inline pte_t pte_mkhuge(pte_t pte) +{ + return pte; +} + /* Modify page protection bits */ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { @@ -396,6 +407,7 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, #define kern_addr_valid(addr) (1) /* FIXME */ #endif +extern void *dtb_early_va; extern void setup_bootmem(void); extern void paging_init(void); @@ -409,7 +421,7 @@ static inline void pgtable_cache_init(void) #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) /* - * Task size is 0x40000000000 for RV64 or 0xb800000 for RV32. + * Task size is 0x4000000000 for RV64 or 0xb800000 for RV32. * Note that PGDIR_SIZE must evenly divide TASK_SIZE. */ #ifdef CONFIG_64BIT diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4e46f31072da..0f1ba17e476f 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -11,9 +11,41 @@ #include <asm/thread_info.h> #include <asm/page.h> #include <asm/csr.h> +#include <asm/image.h> __INIT ENTRY(_start) + /* + * Image header expected by Linux boot-loaders. The image header data + * structure is described in asm/image.h. + * Do not modify it without modifying the structure and all bootloaders + * that expects this header format!! + */ + /* jump to start kernel */ + j _start_kernel + /* reserved */ + .word 0 + .balign 8 +#if __riscv_xlen == 64 + /* Image load offset(2MB) from start of RAM */ + .dword 0x200000 +#else + /* Image load offset(4MB) from start of RAM */ + .dword 0x400000 +#endif + /* Effective size of kernel image */ + .dword _end - _start + .dword __HEAD_FLAGS + .word RISCV_HEADER_VERSION + .word 0 + .dword 0 + .asciz RISCV_IMAGE_MAGIC + .word 0 + .balign 4 + .word 0 + +.global _start_kernel +_start_kernel: /* Mask all interrupts */ csrw CSR_SIE, zero csrw CSR_SIP, zero @@ -55,7 +87,9 @@ clear_bss_done: /* Initialize page tables and relocate to virtual addresses */ la sp, init_thread_union + THREAD_SIZE + mv a0, s1 call setup_vm + la a0, early_pg_dir call relocate /* Restore C environment */ @@ -64,25 +98,23 @@ clear_bss_done: la sp, init_thread_union + THREAD_SIZE /* Start the kernel */ - mv a0, s1 call parse_dtb tail start_kernel relocate: /* Relocate return address */ li a1, PAGE_OFFSET - la a0, _start - sub a1, a1, a0 + la a2, _start + sub a1, a1, a2 add ra, ra, a1 /* Point stvec to virtual address of intruction after satp write */ - la a0, 1f - add a0, a0, a1 - csrw CSR_STVEC, a0 + la a2, 1f + add a2, a2, a1 + csrw CSR_STVEC, a2 /* Compute satp for kernel page tables, but don't load it yet */ - la a2, swapper_pg_dir - srl a2, a2, PAGE_SHIFT + srl a2, a0, PAGE_SHIFT li a1, SATP_MODE or a2, a2, a1 @@ -148,6 +180,7 @@ relocate: fence /* Enable virtual memory and relocate to virtual address */ + la a0, swapper_pg_dir call relocate tail smp_callin diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index b92e6831d1ec..a990a6cb184f 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -39,11 +39,9 @@ struct screen_info screen_info = { atomic_t hart_lottery; unsigned long boot_cpu_hartid; -void __init parse_dtb(phys_addr_t dtb_phys) +void __init parse_dtb(void) { - void *dtb = __va(dtb_phys); - - if (early_init_dt_scan(dtb)) + if (early_init_dt_scan(dtb_early_va)) return; pr_err("No DTB passed to the kernel\n"); diff --git a/arch/riscv/kernel/vdso.c b/arch/riscv/kernel/vdso.c index a0084c36d270..c9c21e0d5641 100644 --- a/arch/riscv/kernel/vdso.c +++ b/arch/riscv/kernel/vdso.c @@ -92,22 +92,3 @@ const char *arch_vma_name(struct vm_area_struct *vma) return "[vdso]"; return NULL; } - -/* - * Function stubs to prevent linker errors when AT_SYSINFO_EHDR is defined - */ - -int in_gate_area_no_mm(unsigned long addr) -{ - return 0; -} - -int in_gate_area(struct mm_struct *mm, unsigned long addr) -{ - return 0; -} - -struct vm_area_struct *get_gate_vma(struct mm_struct *mm) -{ - return NULL; -} diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index fc51d3b7876e..74055e1d6f21 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -12,3 +12,5 @@ obj-y += ioremap.o obj-y += cacheflush.o obj-y += context.o obj-y += sifive_l2_cache.o + +obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o diff --git a/arch/riscv/mm/hugetlbpage.c b/arch/riscv/mm/hugetlbpage.c new file mode 100644 index 000000000000..0d4747e9d5b5 --- /dev/null +++ b/arch/riscv/mm/hugetlbpage.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <linux/hugetlb.h> +#include <linux/err.h> + +int pud_huge(pud_t pud) +{ + return pud_present(pud) && + (pud_val(pud) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); +} + +int pmd_huge(pmd_t pmd) +{ + return pmd_present(pmd) && + (pmd_val(pmd) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); +} + +static __init int setup_hugepagesz(char *opt) +{ + unsigned long ps = memparse(opt, &opt); + + if (ps == HPAGE_SIZE) { + hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT); + } else if (IS_ENABLED(CONFIG_64BIT) && ps == PUD_SIZE) { + hugetlb_add_hstate(PUD_SHIFT - PAGE_SHIFT); + } else { + hugetlb_bad_size(); + pr_err("hugepagesz: Unsupported page size %lu M\n", ps >> 20); + return 0; + } + + return 1; +} +__setup("hugepagesz=", setup_hugepagesz); + +#ifdef CONFIG_CONTIG_ALLOC +static __init int gigantic_pages_init(void) +{ + /* With CONTIG_ALLOC, we can allocate gigantic pages at runtime */ + if (IS_ENABLED(CONFIG_64BIT) && !size_to_hstate(1UL << PUD_SHIFT)) + hugetlb_add_hstate(PUD_SHIFT - PAGE_SHIFT); + return 0; +} +arch_initcall(gigantic_pages_init); +#endif diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 84747d7a1e85..42bf939693d3 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2019 Western Digital Corporation or its affiliates. */ #include <linux/init.h> @@ -21,6 +22,8 @@ unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] __page_aligned_bss; EXPORT_SYMBOL(empty_zero_page); +extern char _start[]; + static void __init zone_sizes_init(void) { unsigned long max_zone_pfns[MAX_NR_ZONES] = { 0, }; @@ -39,13 +42,6 @@ void setup_zero_page(void) memset((void *)empty_zero_page, 0, PAGE_SIZE); } -void __init paging_init(void) -{ - setup_zero_page(); - local_flush_tlb_all(); - zone_sizes_init(); -} - void __init mem_init(void) { #ifdef CONFIG_FLATMEM @@ -84,29 +80,20 @@ disable: initrd_start = 0; initrd_end = 0; } - -void __init free_initrd_mem(unsigned long start, unsigned long end) -{ - free_reserved_area((void *)start, (void *)end, -1, "initrd"); -} #endif /* CONFIG_BLK_DEV_INITRD */ void __init setup_bootmem(void) { struct memblock_region *reg; phys_addr_t mem_size = 0; + phys_addr_t vmlinux_end = __pa(&_end); + phys_addr_t vmlinux_start = __pa(&_start); /* Find the memory region containing the kernel */ for_each_memblock(memory, reg) { - phys_addr_t vmlinux_end = __pa(_end); phys_addr_t end = reg->base + reg->size; if (reg->base <= vmlinux_end && vmlinux_end <= end) { - /* - * Reserve from the start of the region to the end of - * the kernel - */ - memblock_reserve(reg->base, vmlinux_end - reg->base); mem_size = min(reg->size, (phys_addr_t)-PAGE_OFFSET); /* @@ -120,6 +107,9 @@ void __init setup_bootmem(void) } BUG_ON(mem_size == 0); + /* Reserve from the start of the kernel to the end of the kernel */ + memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start); + set_max_mapnr(PFN_DOWN(mem_size)); max_low_pfn = PFN_DOWN(memblock_end_of_DRAM()); @@ -147,17 +137,15 @@ EXPORT_SYMBOL(va_pa_offset); unsigned long pfn_base; EXPORT_SYMBOL(pfn_base); +void *dtb_early_va; pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss; -pgd_t trampoline_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE); +pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss; +pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss; +static bool mmu_enabled; -#ifndef __PAGETABLE_PMD_FOLDED -#define NUM_SWAPPER_PMDS ((uintptr_t)-PAGE_OFFSET >> PGDIR_SHIFT) -pmd_t swapper_pmd[PTRS_PER_PMD*((-PAGE_OFFSET)/PGDIR_SIZE)] __page_aligned_bss; -pmd_t trampoline_pmd[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE); -pmd_t fixmap_pmd[PTRS_PER_PMD] __page_aligned_bss; -#endif +#define MAX_EARLY_MAPPING_SIZE SZ_128M -pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss; +pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE); void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) { @@ -176,6 +164,156 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) } } +static pte_t *__init get_pte_virt(phys_addr_t pa) +{ + if (mmu_enabled) { + clear_fixmap(FIX_PTE); + return (pte_t *)set_fixmap_offset(FIX_PTE, pa); + } else { + return (pte_t *)((uintptr_t)pa); + } +} + +static phys_addr_t __init alloc_pte(uintptr_t va) +{ + /* + * We only create PMD or PGD early mappings so we + * should never reach here with MMU disabled. + */ + BUG_ON(!mmu_enabled); + + return memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE); +} + +static void __init create_pte_mapping(pte_t *ptep, + uintptr_t va, phys_addr_t pa, + phys_addr_t sz, pgprot_t prot) +{ + uintptr_t pte_index = pte_index(va); + + BUG_ON(sz != PAGE_SIZE); + + if (pte_none(ptep[pte_index])) + ptep[pte_index] = pfn_pte(PFN_DOWN(pa), prot); +} + +#ifndef __PAGETABLE_PMD_FOLDED + +pmd_t trampoline_pmd[PTRS_PER_PMD] __page_aligned_bss; +pmd_t fixmap_pmd[PTRS_PER_PMD] __page_aligned_bss; + +#if MAX_EARLY_MAPPING_SIZE < PGDIR_SIZE +#define NUM_EARLY_PMDS 1UL +#else +#define NUM_EARLY_PMDS (1UL + MAX_EARLY_MAPPING_SIZE / PGDIR_SIZE) +#endif +pmd_t early_pmd[PTRS_PER_PMD * NUM_EARLY_PMDS] __initdata __aligned(PAGE_SIZE); + +static pmd_t *__init get_pmd_virt(phys_addr_t pa) +{ + if (mmu_enabled) { + clear_fixmap(FIX_PMD); + return (pmd_t *)set_fixmap_offset(FIX_PMD, pa); + } else { + return (pmd_t *)((uintptr_t)pa); + } +} + +static phys_addr_t __init alloc_pmd(uintptr_t va) +{ + uintptr_t pmd_num; + + if (mmu_enabled) + return memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE); + + pmd_num = (va - PAGE_OFFSET) >> PGDIR_SHIFT; + BUG_ON(pmd_num >= NUM_EARLY_PMDS); + return (uintptr_t)&early_pmd[pmd_num * PTRS_PER_PMD]; +} + +static void __init create_pmd_mapping(pmd_t *pmdp, + uintptr_t va, phys_addr_t pa, + phys_addr_t sz, pgprot_t prot) +{ + pte_t *ptep; + phys_addr_t pte_phys; + uintptr_t pmd_index = pmd_index(va); + + if (sz == PMD_SIZE) { + if (pmd_none(pmdp[pmd_index])) + pmdp[pmd_index] = pfn_pmd(PFN_DOWN(pa), prot); + return; + } + + if (pmd_none(pmdp[pmd_index])) { + pte_phys = alloc_pte(va); + pmdp[pmd_index] = pfn_pmd(PFN_DOWN(pte_phys), PAGE_TABLE); + ptep = get_pte_virt(pte_phys); + memset(ptep, 0, PAGE_SIZE); + } else { + pte_phys = PFN_PHYS(_pmd_pfn(pmdp[pmd_index])); + ptep = get_pte_virt(pte_phys); + } + + create_pte_mapping(ptep, va, pa, sz, prot); +} + +#define pgd_next_t pmd_t +#define alloc_pgd_next(__va) alloc_pmd(__va) +#define get_pgd_next_virt(__pa) get_pmd_virt(__pa) +#define create_pgd_next_mapping(__nextp, __va, __pa, __sz, __prot) \ + create_pmd_mapping(__nextp, __va, __pa, __sz, __prot) +#define PTE_PARENT_SIZE PMD_SIZE +#define fixmap_pgd_next fixmap_pmd +#else +#define pgd_next_t pte_t +#define alloc_pgd_next(__va) alloc_pte(__va) +#define get_pgd_next_virt(__pa) get_pte_virt(__pa) +#define create_pgd_next_mapping(__nextp, __va, __pa, __sz, __prot) \ + create_pte_mapping(__nextp, __va, __pa, __sz, __prot) +#define PTE_PARENT_SIZE PGDIR_SIZE +#define fixmap_pgd_next fixmap_pte +#endif + +static void __init create_pgd_mapping(pgd_t *pgdp, + uintptr_t va, phys_addr_t pa, + phys_addr_t sz, pgprot_t prot) +{ + pgd_next_t *nextp; + phys_addr_t next_phys; + uintptr_t pgd_index = pgd_index(va); + + if (sz == PGDIR_SIZE) { + if (pgd_val(pgdp[pgd_index]) == 0) + pgdp[pgd_index] = pfn_pgd(PFN_DOWN(pa), prot); + return; + } + + if (pgd_val(pgdp[pgd_index]) == 0) { + next_phys = alloc_pgd_next(va); + pgdp[pgd_index] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); + nextp = get_pgd_next_virt(next_phys); + memset(nextp, 0, PAGE_SIZE); + } else { + next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_index])); + nextp = get_pgd_next_virt(next_phys); + } + + create_pgd_next_mapping(nextp, va, pa, sz, prot); +} + +static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size) +{ + uintptr_t map_size = PAGE_SIZE; + + /* Upgrade to PMD/PGDIR mappings whenever possible */ + if (!(base & (PTE_PARENT_SIZE - 1)) && + !(size & (PTE_PARENT_SIZE - 1))) + map_size = PTE_PARENT_SIZE; + + return map_size; +} + /* * setup_vm() is called from head.S with MMU-off. * @@ -195,55 +333,115 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) "not use absolute addressing." #endif -asmlinkage void __init setup_vm(void) +asmlinkage void __init setup_vm(uintptr_t dtb_pa) { - extern char _start; - uintptr_t i; - uintptr_t pa = (uintptr_t) &_start; - pgprot_t prot = __pgprot(pgprot_val(PAGE_KERNEL) | _PAGE_EXEC); + uintptr_t va, end_va; + uintptr_t load_pa = (uintptr_t)(&_start); + uintptr_t load_sz = (uintptr_t)(&_end) - load_pa; + uintptr_t map_size = best_map_size(load_pa, MAX_EARLY_MAPPING_SIZE); - va_pa_offset = PAGE_OFFSET - pa; - pfn_base = PFN_DOWN(pa); + va_pa_offset = PAGE_OFFSET - load_pa; + pfn_base = PFN_DOWN(load_pa); + + /* + * Enforce boot alignment requirements of RV32 and + * RV64 by only allowing PMD or PGD mappings. + */ + BUG_ON(map_size == PAGE_SIZE); /* Sanity check alignment and size */ BUG_ON((PAGE_OFFSET % PGDIR_SIZE) != 0); - BUG_ON((pa % (PAGE_SIZE * PTRS_PER_PTE)) != 0); + BUG_ON((load_pa % map_size) != 0); + BUG_ON(load_sz > MAX_EARLY_MAPPING_SIZE); + + /* Setup early PGD for fixmap */ + create_pgd_mapping(early_pg_dir, FIXADDR_START, + (uintptr_t)fixmap_pgd_next, PGDIR_SIZE, PAGE_TABLE); #ifndef __PAGETABLE_PMD_FOLDED - trampoline_pg_dir[(PAGE_OFFSET >> PGDIR_SHIFT) % PTRS_PER_PGD] = - pfn_pgd(PFN_DOWN((uintptr_t)trampoline_pmd), - __pgprot(_PAGE_TABLE)); - trampoline_pmd[0] = pfn_pmd(PFN_DOWN(pa), prot); + /* Setup fixmap PMD */ + create_pmd_mapping(fixmap_pmd, FIXADDR_START, + (uintptr_t)fixmap_pte, PMD_SIZE, PAGE_TABLE); + /* Setup trampoline PGD and PMD */ + create_pgd_mapping(trampoline_pg_dir, PAGE_OFFSET, + (uintptr_t)trampoline_pmd, PGDIR_SIZE, PAGE_TABLE); + create_pmd_mapping(trampoline_pmd, PAGE_OFFSET, + load_pa, PMD_SIZE, PAGE_KERNEL_EXEC); +#else + /* Setup trampoline PGD */ + create_pgd_mapping(trampoline_pg_dir, PAGE_OFFSET, + load_pa, PGDIR_SIZE, PAGE_KERNEL_EXEC); +#endif - for (i = 0; i < (-PAGE_OFFSET)/PGDIR_SIZE; ++i) { - size_t o = (PAGE_OFFSET >> PGDIR_SHIFT) % PTRS_PER_PGD + i; + /* + * Setup early PGD covering entire kernel which will allows + * us to reach paging_init(). We map all memory banks later + * in setup_vm_final() below. + */ + end_va = PAGE_OFFSET + load_sz; + for (va = PAGE_OFFSET; va < end_va; va += map_size) + create_pgd_mapping(early_pg_dir, va, + load_pa + (va - PAGE_OFFSET), + map_size, PAGE_KERNEL_EXEC); + + /* Create fixed mapping for early FDT parsing */ + end_va = __fix_to_virt(FIX_FDT) + FIX_FDT_SIZE; + for (va = __fix_to_virt(FIX_FDT); va < end_va; va += PAGE_SIZE) + create_pte_mapping(fixmap_pte, va, + dtb_pa + (va - __fix_to_virt(FIX_FDT)), + PAGE_SIZE, PAGE_KERNEL); + + /* Save pointer to DTB for early FDT parsing */ + dtb_early_va = (void *)fix_to_virt(FIX_FDT) + (dtb_pa & ~PAGE_MASK); +} - swapper_pg_dir[o] = - pfn_pgd(PFN_DOWN((uintptr_t)swapper_pmd) + i, - __pgprot(_PAGE_TABLE)); - } - for (i = 0; i < ARRAY_SIZE(swapper_pmd); i++) - swapper_pmd[i] = pfn_pmd(PFN_DOWN(pa + i * PMD_SIZE), prot); - - swapper_pg_dir[(FIXADDR_START >> PGDIR_SHIFT) % PTRS_PER_PGD] = - pfn_pgd(PFN_DOWN((uintptr_t)fixmap_pmd), - __pgprot(_PAGE_TABLE)); - fixmap_pmd[(FIXADDR_START >> PMD_SHIFT) % PTRS_PER_PMD] = - pfn_pmd(PFN_DOWN((uintptr_t)fixmap_pte), - __pgprot(_PAGE_TABLE)); -#else - trampoline_pg_dir[(PAGE_OFFSET >> PGDIR_SHIFT) % PTRS_PER_PGD] = - pfn_pgd(PFN_DOWN(pa), prot); +static void __init setup_vm_final(void) +{ + uintptr_t va, map_size; + phys_addr_t pa, start, end; + struct memblock_region *reg; - for (i = 0; i < (-PAGE_OFFSET)/PGDIR_SIZE; ++i) { - size_t o = (PAGE_OFFSET >> PGDIR_SHIFT) % PTRS_PER_PGD + i; + /* Set mmu_enabled flag */ + mmu_enabled = true; - swapper_pg_dir[o] = - pfn_pgd(PFN_DOWN(pa + i * PGDIR_SIZE), prot); + /* Setup swapper PGD for fixmap */ + create_pgd_mapping(swapper_pg_dir, FIXADDR_START, + __pa(fixmap_pgd_next), + PGDIR_SIZE, PAGE_TABLE); + + /* Map all memory banks */ + for_each_memblock(memory, reg) { + start = reg->base; + end = start + reg->size; + + if (start >= end) + break; + if (memblock_is_nomap(reg)) + continue; + if (start <= __pa(PAGE_OFFSET) && + __pa(PAGE_OFFSET) < end) + start = __pa(PAGE_OFFSET); + + map_size = best_map_size(start, end - start); + for (pa = start; pa < end; pa += map_size) { + va = (uintptr_t)__va(pa); + create_pgd_mapping(swapper_pg_dir, va, pa, + map_size, PAGE_KERNEL_EXEC); + } } - swapper_pg_dir[(FIXADDR_START >> PGDIR_SHIFT) % PTRS_PER_PGD] = - pfn_pgd(PFN_DOWN((uintptr_t)fixmap_pte), - __pgprot(_PAGE_TABLE)); -#endif + /* Clear fixmap PTE and PMD mappings */ + clear_fixmap(FIX_PTE); + clear_fixmap(FIX_PMD); + + /* Move to swapper page table */ + csr_write(sptbr, PFN_DOWN(__pa(swapper_pg_dir)) | SATP_MODE); + local_flush_tlb_all(); +} + +void __init paging_init(void) +{ + setup_vm_final(); + setup_zero_page(); + zone_sizes_init(); } diff --git a/arch/riscv/mm/sifive_l2_cache.c b/arch/riscv/mm/sifive_l2_cache.c index 4eb64619b3f4..2e637ad71c05 100644 --- a/arch/riscv/mm/sifive_l2_cache.c +++ b/arch/riscv/mm/sifive_l2_cache.c @@ -109,13 +109,14 @@ EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); static irqreturn_t l2_int_handler(int irq, void *device) { - unsigned int regval, add_h, add_l; + unsigned int add_h, add_l; if (irq == g_irq[DIR_CORR]) { add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH); add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW); pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); - regval = readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT); + /* Reading this register clears the DirError interrupt sig */ + readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT); atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, "DirECCFix"); } @@ -123,7 +124,8 @@ static irqreturn_t l2_int_handler(int irq, void *device) add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH); add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW); pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); - regval = readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT); + /* Reading this register clears the DataError interrupt sig */ + readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT); atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, "DatECCFix"); } @@ -131,7 +133,8 @@ static irqreturn_t l2_int_handler(int irq, void *device) add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH); add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW); pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); - regval = readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT); + /* Reading this register clears the DataFail interrupt sig */ + readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT); atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, "DatECCFail"); } diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 5d8570ed6cab..a4ad2733eedf 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -189,6 +189,7 @@ config S390 select VIRT_CPU_ACCOUNTING select ARCH_HAS_SCALED_CPUTIME select HAVE_NMI + select ARCH_HAS_FORCE_DMA_UNENCRYPTED select SWIOTLB select GENERIC_ALLOCATOR diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c index e4b58240ec53..aa738cad1338 100644 --- a/arch/s390/appldata/appldata_base.c +++ b/arch/s390/appldata/appldata_base.c @@ -220,15 +220,13 @@ appldata_timer_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) { int timer_active = appldata_timer_active; - int zero = 0; - int one = 1; int rc; struct ctl_table ctl_entry = { .procname = ctl->procname, .data = &timer_active, .maxlen = sizeof(int), - .extra1 = &zero, - .extra2 = &one, + .extra1 = SYSCTL_ZERO, + .extra2 = SYSCTL_ONE, }; rc = proc_douintvec_minmax(&ctl_entry, write, buffer, lenp, ppos); @@ -255,13 +253,12 @@ appldata_interval_handler(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) { int interval = appldata_interval; - int one = 1; int rc; struct ctl_table ctl_entry = { .procname = ctl->procname, .data = &interval, .maxlen = sizeof(int), - .extra1 = &one, + .extra1 = SYSCTL_ONE, }; rc = proc_dointvec_minmax(&ctl_entry, write, buffer, lenp, ppos); @@ -289,13 +286,11 @@ appldata_generic_handler(struct ctl_table *ctl, int write, struct list_head *lh; int rc, found; int active; - int zero = 0; - int one = 1; struct ctl_table ctl_entry = { .data = &active, .maxlen = sizeof(int), - .extra1 = &zero, - .extra2 = &one, + .extra1 = SYSCTL_ZERO, + .extra2 = SYSCTL_ONE, }; found = 0; diff --git a/arch/s390/include/asm/ctl_reg.h b/arch/s390/include/asm/ctl_reg.h index 0cf6b53587db..60f907516335 100644 --- a/arch/s390/include/asm/ctl_reg.h +++ b/arch/s390/include/asm/ctl_reg.h @@ -8,27 +8,27 @@ #ifndef __ASM_CTL_REG_H #define __ASM_CTL_REG_H -#include <linux/const.h> - -#define CR0_CLOCK_COMPARATOR_SIGN _BITUL(63 - 10) -#define CR0_EMERGENCY_SIGNAL_SUBMASK _BITUL(63 - 49) -#define CR0_EXTERNAL_CALL_SUBMASK _BITUL(63 - 50) -#define CR0_CLOCK_COMPARATOR_SUBMASK _BITUL(63 - 52) -#define CR0_CPU_TIMER_SUBMASK _BITUL(63 - 53) -#define CR0_SERVICE_SIGNAL_SUBMASK _BITUL(63 - 54) -#define CR0_UNUSED_56 _BITUL(63 - 56) -#define CR0_INTERRUPT_KEY_SUBMASK _BITUL(63 - 57) -#define CR0_MEASUREMENT_ALERT_SUBMASK _BITUL(63 - 58) - -#define CR2_GUARDED_STORAGE _BITUL(63 - 59) - -#define CR14_UNUSED_32 _BITUL(63 - 32) -#define CR14_UNUSED_33 _BITUL(63 - 33) -#define CR14_CHANNEL_REPORT_SUBMASK _BITUL(63 - 35) -#define CR14_RECOVERY_SUBMASK _BITUL(63 - 36) -#define CR14_DEGRADATION_SUBMASK _BITUL(63 - 37) -#define CR14_EXTERNAL_DAMAGE_SUBMASK _BITUL(63 - 38) -#define CR14_WARNING_SUBMASK _BITUL(63 - 39) +#include <linux/bits.h> + +#define CR0_CLOCK_COMPARATOR_SIGN BIT(63 - 10) +#define CR0_EMERGENCY_SIGNAL_SUBMASK BIT(63 - 49) +#define CR0_EXTERNAL_CALL_SUBMASK BIT(63 - 50) +#define CR0_CLOCK_COMPARATOR_SUBMASK BIT(63 - 52) +#define CR0_CPU_TIMER_SUBMASK BIT(63 - 53) +#define CR0_SERVICE_SIGNAL_SUBMASK BIT(63 - 54) +#define CR0_UNUSED_56 BIT(63 - 56) +#define CR0_INTERRUPT_KEY_SUBMASK BIT(63 - 57) +#define CR0_MEASUREMENT_ALERT_SUBMASK BIT(63 - 58) + +#define CR2_GUARDED_STORAGE BIT(63 - 59) + +#define CR14_UNUSED_32 BIT(63 - 32) +#define CR14_UNUSED_33 BIT(63 - 33) +#define CR14_CHANNEL_REPORT_SUBMASK BIT(63 - 35) +#define CR14_RECOVERY_SUBMASK BIT(63 - 36) +#define CR14_DEGRADATION_SUBMASK BIT(63 - 37) +#define CR14_EXTERNAL_DAMAGE_SUBMASK BIT(63 - 38) +#define CR14_WARNING_SUBMASK BIT(63 - 39) #ifndef __ASSEMBLY__ diff --git a/arch/s390/include/asm/nmi.h b/arch/s390/include/asm/nmi.h index 1e5dc4537bf2..b160da8fa14b 100644 --- a/arch/s390/include/asm/nmi.h +++ b/arch/s390/include/asm/nmi.h @@ -12,7 +12,7 @@ #ifndef _ASM_S390_NMI_H #define _ASM_S390_NMI_H -#include <linux/const.h> +#include <linux/bits.h> #include <linux/types.h> #define MCIC_SUBCLASS_MASK (1ULL<<63 | 1ULL<<62 | 1ULL<<61 | \ @@ -20,15 +20,15 @@ 1ULL<<55 | 1ULL<<54 | 1ULL<<53 | \ 1ULL<<52 | 1ULL<<47 | 1ULL<<46 | \ 1ULL<<45 | 1ULL<<44) -#define MCCK_CODE_SYSTEM_DAMAGE _BITUL(63) -#define MCCK_CODE_EXT_DAMAGE _BITUL(63 - 5) -#define MCCK_CODE_CP _BITUL(63 - 9) -#define MCCK_CODE_CPU_TIMER_VALID _BITUL(63 - 46) -#define MCCK_CODE_PSW_MWP_VALID _BITUL(63 - 20) -#define MCCK_CODE_PSW_IA_VALID _BITUL(63 - 23) -#define MCCK_CODE_CR_VALID _BITUL(63 - 29) -#define MCCK_CODE_GS_VALID _BITUL(63 - 36) -#define MCCK_CODE_FC_VALID _BITUL(63 - 43) +#define MCCK_CODE_SYSTEM_DAMAGE BIT(63) +#define MCCK_CODE_EXT_DAMAGE BIT(63 - 5) +#define MCCK_CODE_CP BIT(63 - 9) +#define MCCK_CODE_CPU_TIMER_VALID BIT(63 - 46) +#define MCCK_CODE_PSW_MWP_VALID BIT(63 - 20) +#define MCCK_CODE_PSW_IA_VALID BIT(63 - 23) +#define MCCK_CODE_CR_VALID BIT(63 - 29) +#define MCCK_CODE_GS_VALID BIT(63 - 36) +#define MCCK_CODE_FC_VALID BIT(63 - 43) #ifndef __ASSEMBLY__ diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h index 14883b1562e0..d56c519bc696 100644 --- a/arch/s390/include/asm/processor.h +++ b/arch/s390/include/asm/processor.h @@ -12,7 +12,7 @@ #ifndef __ASM_S390_PROCESSOR_H #define __ASM_S390_PROCESSOR_H -#include <linux/const.h> +#include <linux/bits.h> #define CIF_MCCK_PENDING 0 /* machine check handling is pending */ #define CIF_ASCE_PRIMARY 1 /* primary asce needs fixup / uaccess */ @@ -24,15 +24,15 @@ #define CIF_MCCK_GUEST 7 /* machine check happening in guest */ #define CIF_DEDICATED_CPU 8 /* this CPU is dedicated */ -#define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING) -#define _CIF_ASCE_PRIMARY _BITUL(CIF_ASCE_PRIMARY) -#define _CIF_ASCE_SECONDARY _BITUL(CIF_ASCE_SECONDARY) -#define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY) -#define _CIF_FPU _BITUL(CIF_FPU) -#define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ) -#define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT) -#define _CIF_MCCK_GUEST _BITUL(CIF_MCCK_GUEST) -#define _CIF_DEDICATED_CPU _BITUL(CIF_DEDICATED_CPU) +#define _CIF_MCCK_PENDING BIT(CIF_MCCK_PENDING) +#define _CIF_ASCE_PRIMARY BIT(CIF_ASCE_PRIMARY) +#define _CIF_ASCE_SECONDARY BIT(CIF_ASCE_SECONDARY) +#define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY) +#define _CIF_FPU BIT(CIF_FPU) +#define _CIF_IGNORE_IRQ BIT(CIF_IGNORE_IRQ) +#define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT) +#define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST) +#define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU) #ifndef __ASSEMBLY__ diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h index 6f70d81c40f2..f009a13afe71 100644 --- a/arch/s390/include/asm/ptrace.h +++ b/arch/s390/include/asm/ptrace.h @@ -7,7 +7,7 @@ #ifndef _S390_PTRACE_H #define _S390_PTRACE_H -#include <linux/const.h> +#include <linux/bits.h> #include <uapi/asm/ptrace.h> #define PIF_SYSCALL 0 /* inside a system call */ @@ -15,10 +15,10 @@ #define PIF_SYSCALL_RESTART 2 /* restart the current system call */ #define PIF_GUEST_FAULT 3 /* indicates program check in sie64a */ -#define _PIF_SYSCALL _BITUL(PIF_SYSCALL) -#define _PIF_PER_TRAP _BITUL(PIF_PER_TRAP) -#define _PIF_SYSCALL_RESTART _BITUL(PIF_SYSCALL_RESTART) -#define _PIF_GUEST_FAULT _BITUL(PIF_GUEST_FAULT) +#define _PIF_SYSCALL BIT(PIF_SYSCALL) +#define _PIF_PER_TRAP BIT(PIF_PER_TRAP) +#define _PIF_SYSCALL_RESTART BIT(PIF_SYSCALL_RESTART) +#define _PIF_GUEST_FAULT BIT(PIF_GUEST_FAULT) #ifndef __ASSEMBLY__ diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h index 925889d360c1..82deb8fc8319 100644 --- a/arch/s390/include/asm/setup.h +++ b/arch/s390/include/asm/setup.h @@ -6,7 +6,7 @@ #ifndef _ASM_S390_SETUP_H #define _ASM_S390_SETUP_H -#include <linux/const.h> +#include <linux/bits.h> #include <uapi/asm/setup.h> #define EP_OFFSET 0x10008 @@ -21,25 +21,25 @@ * Machine features detected in early.c */ -#define MACHINE_FLAG_VM _BITUL(0) -#define MACHINE_FLAG_KVM _BITUL(1) -#define MACHINE_FLAG_LPAR _BITUL(2) -#define MACHINE_FLAG_DIAG9C _BITUL(3) -#define MACHINE_FLAG_ESOP _BITUL(4) -#define MACHINE_FLAG_IDTE _BITUL(5) -#define MACHINE_FLAG_DIAG44 _BITUL(6) -#define MACHINE_FLAG_EDAT1 _BITUL(7) -#define MACHINE_FLAG_EDAT2 _BITUL(8) -#define MACHINE_FLAG_TOPOLOGY _BITUL(10) -#define MACHINE_FLAG_TE _BITUL(11) -#define MACHINE_FLAG_TLB_LC _BITUL(12) -#define MACHINE_FLAG_VX _BITUL(13) -#define MACHINE_FLAG_TLB_GUEST _BITUL(14) -#define MACHINE_FLAG_NX _BITUL(15) -#define MACHINE_FLAG_GS _BITUL(16) -#define MACHINE_FLAG_SCC _BITUL(17) - -#define LPP_MAGIC _BITUL(31) +#define MACHINE_FLAG_VM BIT(0) +#define MACHINE_FLAG_KVM BIT(1) +#define MACHINE_FLAG_LPAR BIT(2) +#define MACHINE_FLAG_DIAG9C BIT(3) +#define MACHINE_FLAG_ESOP BIT(4) +#define MACHINE_FLAG_IDTE BIT(5) +#define MACHINE_FLAG_DIAG44 BIT(6) +#define MACHINE_FLAG_EDAT1 BIT(7) +#define MACHINE_FLAG_EDAT2 BIT(8) +#define MACHINE_FLAG_TOPOLOGY BIT(10) +#define MACHINE_FLAG_TE BIT(11) +#define MACHINE_FLAG_TLB_LC BIT(12) +#define MACHINE_FLAG_VX BIT(13) +#define MACHINE_FLAG_TLB_GUEST BIT(14) +#define MACHINE_FLAG_NX BIT(15) +#define MACHINE_FLAG_GS BIT(16) +#define MACHINE_FLAG_SCC BIT(17) + +#define LPP_MAGIC BIT(31) #define LPP_PID_MASK _AC(0xffffffff, UL) /* Offsets to entry points in kernel/head.S */ diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h index ce4e17c9aad6..e582fbe59e20 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -8,7 +8,7 @@ #ifndef _ASM_THREAD_INFO_H #define _ASM_THREAD_INFO_H -#include <linux/const.h> +#include <linux/bits.h> /* * General size of kernel stacks @@ -82,21 +82,21 @@ void arch_setup_new_exec(void); #define TIF_SECCOMP 26 /* secure computing */ #define TIF_SYSCALL_TRACEPOINT 27 /* syscall tracepoint instrumentation */ -#define _TIF_NOTIFY_RESUME _BITUL(TIF_NOTIFY_RESUME) -#define _TIF_SIGPENDING _BITUL(TIF_SIGPENDING) -#define _TIF_NEED_RESCHED _BITUL(TIF_NEED_RESCHED) -#define _TIF_UPROBE _BITUL(TIF_UPROBE) -#define _TIF_GUARDED_STORAGE _BITUL(TIF_GUARDED_STORAGE) -#define _TIF_PATCH_PENDING _BITUL(TIF_PATCH_PENDING) -#define _TIF_ISOLATE_BP _BITUL(TIF_ISOLATE_BP) -#define _TIF_ISOLATE_BP_GUEST _BITUL(TIF_ISOLATE_BP_GUEST) - -#define _TIF_31BIT _BITUL(TIF_31BIT) -#define _TIF_SINGLE_STEP _BITUL(TIF_SINGLE_STEP) - -#define _TIF_SYSCALL_TRACE _BITUL(TIF_SYSCALL_TRACE) -#define _TIF_SYSCALL_AUDIT _BITUL(TIF_SYSCALL_AUDIT) -#define _TIF_SECCOMP _BITUL(TIF_SECCOMP) -#define _TIF_SYSCALL_TRACEPOINT _BITUL(TIF_SYSCALL_TRACEPOINT) +#define _TIF_NOTIFY_RESUME BIT(TIF_NOTIFY_RESUME) +#define _TIF_SIGPENDING BIT(TIF_SIGPENDING) +#define _TIF_NEED_RESCHED BIT(TIF_NEED_RESCHED) +#define _TIF_UPROBE BIT(TIF_UPROBE) +#define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE) +#define _TIF_PATCH_PENDING BIT(TIF_PATCH_PENDING) +#define _TIF_ISOLATE_BP BIT(TIF_ISOLATE_BP) +#define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST) + +#define _TIF_31BIT BIT(TIF_31BIT) +#define _TIF_SINGLE_STEP BIT(TIF_SINGLE_STEP) + +#define _TIF_SYSCALL_TRACE BIT(TIF_SYSCALL_TRACE) +#define _TIF_SYSCALL_AUDIT BIT(TIF_SYSCALL_AUDIT) +#define _TIF_SECCOMP BIT(TIF_SECCOMP) +#define _TIF_SYSCALL_TRACEPOINT BIT(TIF_SYSCALL_TRACEPOINT) #endif /* _ASM_THREAD_INFO_H */ diff --git a/arch/s390/kernel/syscalls/syscall.tbl b/arch/s390/kernel/syscalls/syscall.tbl index 6ebacfeaf853..a90d3e945445 100644 --- a/arch/s390/kernel/syscalls/syscall.tbl +++ b/arch/s390/kernel/syscalls/syscall.tbl @@ -437,3 +437,4 @@ 432 common fsmount sys_fsmount sys_fsmount 433 common fspick sys_fspick sys_fspick 434 common pidfd_open sys_pidfd_open sys_pidfd_open +# 435 reserved for clone3 diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c index 8964a3f60aad..2db6fb405a9a 100644 --- a/arch/s390/kernel/topology.c +++ b/arch/s390/kernel/topology.c @@ -587,15 +587,13 @@ static int topology_ctl_handler(struct ctl_table *ctl, int write, { int enabled = topology_is_enabled(); int new_mode; - int zero = 0; - int one = 1; int rc; struct ctl_table ctl_entry = { .procname = ctl->procname, .data = &enabled, .maxlen = sizeof(int), - .extra1 = &zero, - .extra2 = &one, + .extra1 = SYSCTL_ZERO, + .extra2 = SYSCTL_ONE, }; rc = proc_douintvec_minmax(&ctl_entry, write, buffer, lenp, ppos); diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index 9dde4d7d8704..b5fd6e85657c 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -1224,28 +1224,11 @@ no_timer: void kvm_s390_vcpu_wakeup(struct kvm_vcpu *vcpu) { - /* - * We cannot move this into the if, as the CPU might be already - * in kvm_vcpu_block without having the waitqueue set (polling) - */ vcpu->valid_wakeup = true; + kvm_vcpu_wake_up(vcpu); + /* - * This is mostly to document, that the read in swait_active could - * be moved before other stores, leading to subtle races. - * All current users do not store or use an atomic like update - */ - smp_mb__after_atomic(); - if (swait_active(&vcpu->wq)) { - /* - * The vcpu gave up the cpu voluntarily, mark it as a good - * yield-candidate. - */ - vcpu->preempted = true; - swake_up_one(&vcpu->wq); - vcpu->stat.halt_wakeup++; - } - /* - * The VCPU might not be sleeping but is executing the VSIE. Let's + * The VCPU might not be sleeping but rather executing VSIE. Let's * kick it, so it leaves the SIE to process the request. */ kvm_s390_vsie_kick(vcpu); diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index 0ba174f779da..63507662828f 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -67,20 +67,6 @@ static int __init fault_init(void) } early_initcall(fault_init); -static inline int notify_page_fault(struct pt_regs *regs) -{ - int ret = 0; - - /* kprobe_running() needs smp_processor_id() */ - if (kprobes_built_in() && !user_mode(regs)) { - preempt_disable(); - if (kprobe_running() && kprobe_fault_handler(regs, 14)) - ret = 1; - preempt_enable(); - } - return ret; -} - /* * Find out which address space caused the exception. */ @@ -412,7 +398,7 @@ static inline vm_fault_t do_exception(struct pt_regs *regs, int access) */ clear_pt_regs_flag(regs, PIF_PER_TRAP); - if (notify_page_fault(regs)) + if (kprobe_page_fault(regs, 14)) return 0; mm = tsk->mm; diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c index f0bee6af3960..20340a03ad90 100644 --- a/arch/s390/mm/init.c +++ b/arch/s390/mm/init.c @@ -30,7 +30,7 @@ #include <linux/export.h> #include <linux/cma.h> #include <linux/gfp.h> -#include <linux/dma-mapping.h> +#include <linux/dma-direct.h> #include <asm/processor.h> #include <linux/uaccess.h> #include <asm/pgtable.h> @@ -161,6 +161,11 @@ bool sev_active(void) return is_prot_virt_guest(); } +bool force_dma_unencrypted(struct device *dev) +{ + return sev_active(); +} + /* protected virtualization */ static void pv_init(void) { @@ -273,6 +278,9 @@ int arch_add_memory(int nid, u64 start, u64 size, unsigned long size_pages = PFN_DOWN(size); int rc; + if (WARN_ON_ONCE(restrictions->altmap)) + return -EINVAL; + rc = vmem_add_mapping(start, size); if (rc) return rc; @@ -283,16 +291,15 @@ int arch_add_memory(int nid, u64 start, u64 size, return rc; } -#ifdef CONFIG_MEMORY_HOTREMOVE void arch_remove_memory(int nid, u64 start, u64 size, struct vmem_altmap *altmap) { - /* - * There is no hardware or firmware interface which could trigger a - * hot memory remove on s390. So there is nothing that needs to be - * implemented. - */ - BUG(); + unsigned long start_pfn = start >> PAGE_SHIFT; + unsigned long nr_pages = size >> PAGE_SHIFT; + struct zone *zone; + + zone = page_zone(pfn_to_page(start_pfn)); + __remove_pages(zone, start_pfn, nr_pages, altmap); + vmem_remove_mapping(start, size); } -#endif #endif /* CONFIG_MEMORY_HOTPLUG */ diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 31a7d12db705..6b1b5941b618 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -626,7 +626,7 @@ config CRASH_DUMP to a memory address not used by the main kernel using PHYSICAL_START. - For more details see Documentation/kdump/kdump.rst + For more details see Documentation/admin-guide/kdump/kdump.rst config KEXEC_JUMP bool "kexec jump (EXPERIMENTAL)" @@ -679,7 +679,7 @@ config SMP People using multiprocessor machines who say Y here should also say Y to "Enhanced Real Time Clock Support", below. - See also <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO + See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at <http://www.tldp.org/docs.html#howto>. If you don't know what to do here, say N. diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index b9a37057b77a..cee24c308337 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -8,27 +8,19 @@ config SH_ALPHA_BOARD bool config SH_DEVICE_TREE - bool "Board Described by Device Tree" + bool select OF select OF_EARLY_FLATTREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY - help - Select Board Described by Device Tree to build a kernel that - does not hard-code any board-specific knowledge but instead uses - a device tree blob provided by the boot-loader. You must enable - drivers for any hardware you want to use separately. At this - time, only boards based on the open-hardware J-Core processors - have sufficient driver coverage to use this option; do not - select it if you are using original SuperH hardware. config SH_JCORE_SOC bool "J-Core SoC" - depends on SH_DEVICE_TREE && (CPU_SH2 || CPU_J2) + select SH_DEVICE_TREE select CLKSRC_JCORE_PIT select JCORE_AIC - default y if CPU_J2 + depends on CPU_J2 help Select this option to include drivers core components of the J-Core SoC, including interrupt controllers and timers. diff --git a/arch/sh/configs/ap325rxa_defconfig b/arch/sh/configs/ap325rxa_defconfig index 0ef3f1f9de5c..cc6e4ce53dac 100644 --- a/arch/sh/configs/ap325rxa_defconfig +++ b/arch/sh/configs/ap325rxa_defconfig @@ -28,7 +28,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/configs/apsh4a3a_defconfig b/arch/sh/configs/apsh4a3a_defconfig index 6c7cdc3beb28..530498f18990 100644 --- a/arch/sh/configs/apsh4a3a_defconfig +++ b/arch/sh/configs/apsh4a3a_defconfig @@ -29,7 +29,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/configs/apsh4ad0a_defconfig b/arch/sh/configs/apsh4ad0a_defconfig index d0d9ebc7165b..6dd0da73ca5a 100644 --- a/arch/sh/configs/apsh4ad0a_defconfig +++ b/arch/sh/configs/apsh4ad0a_defconfig @@ -53,7 +53,6 @@ CONFIG_NET_KEY=y CONFIG_INET=y # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_CFI=y diff --git a/arch/sh/configs/cayman_defconfig b/arch/sh/configs/cayman_defconfig index 5a90e24aa8a6..911437c163c7 100644 --- a/arch/sh/configs/cayman_defconfig +++ b/arch/sh/configs/cayman_defconfig @@ -19,7 +19,6 @@ CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y diff --git a/arch/sh/configs/dreamcast_defconfig b/arch/sh/configs/dreamcast_defconfig index 1d27666c029f..ae067e0b15e3 100644 --- a/arch/sh/configs/dreamcast_defconfig +++ b/arch/sh/configs/dreamcast_defconfig @@ -32,7 +32,6 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_FW_LOADER is not set CONFIG_GDROM=y diff --git a/arch/sh/configs/ecovec24-romimage_defconfig b/arch/sh/configs/ecovec24-romimage_defconfig index bdb61d1d0127..5c60e71d839e 100644 --- a/arch/sh/configs/ecovec24-romimage_defconfig +++ b/arch/sh/configs/ecovec24-romimage_defconfig @@ -26,7 +26,6 @@ CONFIG_INET=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set diff --git a/arch/sh/configs/ecovec24_defconfig b/arch/sh/configs/ecovec24_defconfig index ba67e3752938..2fb7db4957ce 100644 --- a/arch/sh/configs/ecovec24_defconfig +++ b/arch/sh/configs/ecovec24_defconfig @@ -31,7 +31,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set CONFIG_IRDA=y CONFIG_SH_SIR=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/configs/edosk7760_defconfig b/arch/sh/configs/edosk7760_defconfig index aab4ff1e247c..02ba62298576 100644 --- a/arch/sh/configs/edosk7760_defconfig +++ b/arch/sh/configs/edosk7760_defconfig @@ -31,7 +31,6 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_DEBUG_DRIVER=y CONFIG_DEBUG_DEVRES=y diff --git a/arch/sh/configs/espt_defconfig b/arch/sh/configs/espt_defconfig index 444d75947e70..a5b865a75d22 100644 --- a/arch/sh/configs/espt_defconfig +++ b/arch/sh/configs/espt_defconfig @@ -26,7 +26,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/configs/hp6xx_defconfig b/arch/sh/configs/hp6xx_defconfig index 91d43e2bffea..a92db6694ce2 100644 --- a/arch/sh/configs/hp6xx_defconfig +++ b/arch/sh/configs/hp6xx_defconfig @@ -18,7 +18,6 @@ CONFIG_HD64461_ENABLER=y CONFIG_PCCARD=y CONFIG_PM=y CONFIG_APM_EMULATION=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set CONFIG_BLK_DEV_SD=y CONFIG_ATA=y diff --git a/arch/sh/configs/kfr2r09-romimage_defconfig b/arch/sh/configs/kfr2r09-romimage_defconfig index 9cc37f29e3b4..04436b4fbd76 100644 --- a/arch/sh/configs/kfr2r09-romimage_defconfig +++ b/arch/sh/configs/kfr2r09-romimage_defconfig @@ -28,7 +28,6 @@ CONFIG_INET=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set diff --git a/arch/sh/configs/kfr2r09_defconfig b/arch/sh/configs/kfr2r09_defconfig index 46693d033644..1dc3f670c481 100644 --- a/arch/sh/configs/kfr2r09_defconfig +++ b/arch/sh/configs/kfr2r09_defconfig @@ -35,7 +35,6 @@ CONFIG_INET=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/configs/landisk_defconfig b/arch/sh/configs/landisk_defconfig index 467f4d2d8e87..567af752b1bb 100644 --- a/arch/sh/configs/landisk_defconfig +++ b/arch/sh/configs/landisk_defconfig @@ -26,7 +26,6 @@ CONFIG_IP_PNP=y # CONFIG_IPV6 is not set CONFIG_NETFILTER=y CONFIG_ATALK=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_IDE=y diff --git a/arch/sh/configs/lboxre2_defconfig b/arch/sh/configs/lboxre2_defconfig index 9e3edfdf9b2e..10f6d371ce2c 100644 --- a/arch/sh/configs/lboxre2_defconfig +++ b/arch/sh/configs/lboxre2_defconfig @@ -29,7 +29,6 @@ CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_PNP=y # CONFIG_IPV6 is not set CONFIG_NETFILTER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_SD=y diff --git a/arch/sh/configs/magicpanelr2_defconfig b/arch/sh/configs/magicpanelr2_defconfig index fb7415dbc102..664c4dee6e6a 100644 --- a/arch/sh/configs/magicpanelr2_defconfig +++ b/arch/sh/configs/magicpanelr2_defconfig @@ -35,7 +35,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_MTD=y diff --git a/arch/sh/configs/microdev_defconfig b/arch/sh/configs/microdev_defconfig index c3f7d5899922..ed84d1303acf 100644 --- a/arch/sh/configs/microdev_defconfig +++ b/arch/sh/configs/microdev_defconfig @@ -19,7 +19,6 @@ CONFIG_NET=y CONFIG_INET=y CONFIG_IP_PNP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_BLK_DEV_RAM=y CONFIG_IDE=y diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig index 121a75d65fb4..494a1675c226 100644 --- a/arch/sh/configs/migor_defconfig +++ b/arch/sh/configs/migor_defconfig @@ -26,7 +26,6 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y diff --git a/arch/sh/configs/polaris_defconfig b/arch/sh/configs/polaris_defconfig index 87641b7d6c4e..e3a1d3d2694a 100644 --- a/arch/sh/configs/polaris_defconfig +++ b/arch/sh/configs/polaris_defconfig @@ -37,7 +37,6 @@ CONFIG_IP_MULTICAST=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/configs/r7780mp_defconfig b/arch/sh/configs/r7780mp_defconfig index 435bcd66c667..0a18f8011c55 100644 --- a/arch/sh/configs/r7780mp_defconfig +++ b/arch/sh/configs/r7780mp_defconfig @@ -36,7 +36,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set CONFIG_BRIDGE=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=y CONFIG_MTD_CFI=y diff --git a/arch/sh/configs/r7785rp_defconfig b/arch/sh/configs/r7785rp_defconfig index 5877e6d1f285..7226ac5a1d44 100644 --- a/arch/sh/configs/r7785rp_defconfig +++ b/arch/sh/configs/r7785rp_defconfig @@ -43,7 +43,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set CONFIG_BRIDGE=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_SD=y diff --git a/arch/sh/configs/rsk7201_defconfig b/arch/sh/configs/rsk7201_defconfig index b195bc01e406..9f4f474705b7 100644 --- a/arch/sh/configs/rsk7201_defconfig +++ b/arch/sh/configs/rsk7201_defconfig @@ -31,7 +31,6 @@ CONFIG_BINFMT_ZFLAT=y CONFIG_BINFMT_SHARED_FLAT=y CONFIG_PM=y CONFIG_CPU_IDLE=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set diff --git a/arch/sh/configs/rsk7203_defconfig b/arch/sh/configs/rsk7203_defconfig index 8c471959bbc7..10a32bd4cf66 100644 --- a/arch/sh/configs/rsk7203_defconfig +++ b/arch/sh/configs/rsk7203_defconfig @@ -45,7 +45,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set diff --git a/arch/sh/configs/rsk7264_defconfig b/arch/sh/configs/rsk7264_defconfig index ad003ee469ea..2b0572b497c1 100644 --- a/arch/sh/configs/rsk7264_defconfig +++ b/arch/sh/configs/rsk7264_defconfig @@ -36,7 +36,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set CONFIG_BLK_DEV_LOOP=y diff --git a/arch/sh/configs/rsk7269_defconfig b/arch/sh/configs/rsk7269_defconfig index 27fc01d58cf8..fb9fa7faf635 100644 --- a/arch/sh/configs/rsk7269_defconfig +++ b/arch/sh/configs/rsk7269_defconfig @@ -25,7 +25,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y diff --git a/arch/sh/configs/rts7751r2d1_defconfig b/arch/sh/configs/rts7751r2d1_defconfig index 379d673f5ce8..6a3cfe08295f 100644 --- a/arch/sh/configs/rts7751r2d1_defconfig +++ b/arch/sh/configs/rts7751r2d1_defconfig @@ -22,7 +22,6 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_SD=y diff --git a/arch/sh/configs/rts7751r2dplus_defconfig b/arch/sh/configs/rts7751r2dplus_defconfig index 11177bceda83..2b3d7d280672 100644 --- a/arch/sh/configs/rts7751r2dplus_defconfig +++ b/arch/sh/configs/rts7751r2dplus_defconfig @@ -22,7 +22,6 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y diff --git a/arch/sh/configs/sdk7780_defconfig b/arch/sh/configs/sdk7780_defconfig index 95e5208b8260..d10a0414123a 100644 --- a/arch/sh/configs/sdk7780_defconfig +++ b/arch/sh/configs/sdk7780_defconfig @@ -41,7 +41,6 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_BEET is not set CONFIG_NET_SCHED=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_PARPORT=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y diff --git a/arch/sh/configs/sdk7786_defconfig b/arch/sh/configs/sdk7786_defconfig index 49a29338789b..7fa116b436c3 100644 --- a/arch/sh/configs/sdk7786_defconfig +++ b/arch/sh/configs/sdk7786_defconfig @@ -91,7 +91,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y diff --git a/arch/sh/configs/se7206_defconfig b/arch/sh/configs/se7206_defconfig index 3553acd5edb1..a93402b3a319 100644 --- a/arch/sh/configs/se7206_defconfig +++ b/arch/sh/configs/se7206_defconfig @@ -58,7 +58,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set diff --git a/arch/sh/configs/se7343_defconfig b/arch/sh/configs/se7343_defconfig index fc77a67b16e7..06d067c842cd 100644 --- a/arch/sh/configs/se7343_defconfig +++ b/arch/sh/configs/se7343_defconfig @@ -28,7 +28,6 @@ CONFIG_INET=y CONFIG_SYN_COOKIES=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/sh/configs/se7712_defconfig b/arch/sh/configs/se7712_defconfig index 1e116529735f..9a527f978106 100644 --- a/arch/sh/configs/se7712_defconfig +++ b/arch/sh/configs/se7712_defconfig @@ -63,7 +63,6 @@ CONFIG_NET_SCH_NETEM=y CONFIG_NET_CLS_TCINDEX=y CONFIG_NET_CLS_ROUTE4=y CONFIG_NET_CLS_FW=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/sh/configs/se7721_defconfig b/arch/sh/configs/se7721_defconfig index c66e512719ab..3b0e1eb6e874 100644 --- a/arch/sh/configs/se7721_defconfig +++ b/arch/sh/configs/se7721_defconfig @@ -62,7 +62,6 @@ CONFIG_NET_SCH_NETEM=y CONFIG_NET_CLS_TCINDEX=y CONFIG_NET_CLS_ROUTE4=y CONFIG_NET_CLS_FW=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/sh/configs/se7722_defconfig b/arch/sh/configs/se7722_defconfig index ccc7fc423fde..88bf9e849008 100644 --- a/arch/sh/configs/se7722_defconfig +++ b/arch/sh/configs/se7722_defconfig @@ -26,7 +26,6 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_SD=y diff --git a/arch/sh/configs/se7724_defconfig b/arch/sh/configs/se7724_defconfig index 9f6d46d58554..0e8d5cc1e107 100644 --- a/arch/sh/configs/se7724_defconfig +++ b/arch/sh/configs/se7724_defconfig @@ -30,7 +30,6 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/configs/sh03_defconfig b/arch/sh/configs/sh03_defconfig index 489ffdfb1517..e5beb625ab88 100644 --- a/arch/sh/configs/sh03_defconfig +++ b/arch/sh/configs/sh03_defconfig @@ -34,7 +34,6 @@ CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set diff --git a/arch/sh/configs/sh2007_defconfig b/arch/sh/configs/sh2007_defconfig index cbd6742eb423..99975db461d8 100644 --- a/arch/sh/configs/sh2007_defconfig +++ b/arch/sh/configs/sh2007_defconfig @@ -44,7 +44,6 @@ CONFIG_NET_IPIP=y # CONFIG_IPV6 is not set CONFIG_NETWORK_SECMARK=y CONFIG_NET_PKTGEN=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=y diff --git a/arch/sh/configs/sh7710voipgw_defconfig b/arch/sh/configs/sh7710voipgw_defconfig index 65a1aad899c8..c86f28442a80 100644 --- a/arch/sh/configs/sh7710voipgw_defconfig +++ b/arch/sh/configs/sh7710voipgw_defconfig @@ -32,7 +32,6 @@ CONFIG_NET_CLS_BASIC=y CONFIG_NET_CLS_TCINDEX=y CONFIG_NET_CLS_ROUTE4=y CONFIG_NET_CLS_U32=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/sh/configs/sh7724_generic_defconfig b/arch/sh/configs/sh7724_generic_defconfig index d04bc27aa816..9adee9010319 100644 --- a/arch/sh/configs/sh7724_generic_defconfig +++ b/arch/sh/configs/sh7724_generic_defconfig @@ -15,7 +15,6 @@ CONFIG_KEXEC=y CONFIG_KEXEC_JUMP=y CONFIG_HIBERNATION=y CONFIG_CPU_IDLE=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_INPUT is not set # CONFIG_SERIO is not set diff --git a/arch/sh/configs/sh7757lcr_defconfig b/arch/sh/configs/sh7757lcr_defconfig index b0c4bc830fb8..9f2aed0b3bca 100644 --- a/arch/sh/configs/sh7757lcr_defconfig +++ b/arch/sh/configs/sh7757lcr_defconfig @@ -33,7 +33,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IPV6=y # CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/configs/sh7763rdp_defconfig b/arch/sh/configs/sh7763rdp_defconfig index 405bf62d22d0..d0a0aa74cecf 100644 --- a/arch/sh/configs/sh7763rdp_defconfig +++ b/arch/sh/configs/sh7763rdp_defconfig @@ -26,7 +26,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLKDEVS=y diff --git a/arch/sh/configs/sh7770_generic_defconfig b/arch/sh/configs/sh7770_generic_defconfig index e5b733c2d988..c17590f0df67 100644 --- a/arch/sh/configs/sh7770_generic_defconfig +++ b/arch/sh/configs/sh7770_generic_defconfig @@ -17,7 +17,6 @@ CONFIG_KEXEC_JUMP=y CONFIG_PM=y CONFIG_HIBERNATION=y CONFIG_CPU_IDLE=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_INPUT is not set # CONFIG_SERIO is not set diff --git a/arch/sh/configs/sh7785lcr_32bit_defconfig b/arch/sh/configs/sh7785lcr_32bit_defconfig index a89ccc15af23..9b885c14c400 100644 --- a/arch/sh/configs/sh7785lcr_32bit_defconfig +++ b/arch/sh/configs/sh7785lcr_32bit_defconfig @@ -43,7 +43,6 @@ CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/sh/configs/sh7785lcr_defconfig b/arch/sh/configs/sh7785lcr_defconfig index 5201bb78c6f9..1b88929083f7 100644 --- a/arch/sh/configs/sh7785lcr_defconfig +++ b/arch/sh/configs/sh7785lcr_defconfig @@ -26,7 +26,6 @@ CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/configs/shx3_defconfig b/arch/sh/configs/shx3_defconfig index 755c4f73c718..dc2be2514b62 100644 --- a/arch/sh/configs/shx3_defconfig +++ b/arch/sh/configs/shx3_defconfig @@ -59,7 +59,6 @@ CONFIG_CAN=m CONFIG_CAN_RAW=m CONFIG_CAN_BCM=m CONFIG_CAN_VCAN=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_SD=y diff --git a/arch/sh/configs/titan_defconfig b/arch/sh/configs/titan_defconfig index 171ab05ce4fc..4ec961ace688 100644 --- a/arch/sh/configs/titan_defconfig +++ b/arch/sh/configs/titan_defconfig @@ -142,7 +142,6 @@ CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_PEDIT=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_CONNECTOR=m CONFIG_MTD=m diff --git a/arch/sh/configs/ul2_defconfig b/arch/sh/configs/ul2_defconfig index 1b7412df12e0..dc2e3061130f 100644 --- a/arch/sh/configs/ul2_defconfig +++ b/arch/sh/configs/ul2_defconfig @@ -33,7 +33,6 @@ CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_MAC80211_RC_PID=y # CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y diff --git a/arch/sh/configs/urquell_defconfig b/arch/sh/configs/urquell_defconfig index f891045e633a..cb2f56468fe0 100644 --- a/arch/sh/configs/urquell_defconfig +++ b/arch/sh/configs/urquell_defconfig @@ -46,7 +46,6 @@ CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y CONFIG_MTD_BLOCK=y diff --git a/arch/sh/kernel/kprobes.c b/arch/sh/kernel/kprobes.c index 1f8c0d30567f..318296f48f1a 100644 --- a/arch/sh/kernel/kprobes.c +++ b/arch/sh/kernel/kprobes.c @@ -485,7 +485,8 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self, struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); addr = (kprobe_opcode_t *) (args->regs->pc); - if (val == DIE_TRAP) { + if (val == DIE_TRAP && + args->trapnr == (BREAKPOINT_INSTRUCTION & 0xff)) { if (!kprobe_running()) { if (kprobe_handler(args->regs)) { ret = NOTIFY_STOP; diff --git a/arch/sh/kernel/syscalls/syscall.tbl b/arch/sh/kernel/syscalls/syscall.tbl index 834c9c7d79fa..b5ed26c4c005 100644 --- a/arch/sh/kernel/syscalls/syscall.tbl +++ b/arch/sh/kernel/syscalls/syscall.tbl @@ -437,3 +437,4 @@ 432 common fsmount sys_fsmount 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open +# 435 reserved for clone3 diff --git a/arch/sh/mm/fault.c b/arch/sh/mm/fault.c index 3093bc372138..5f51456f4fc7 100644 --- a/arch/sh/mm/fault.c +++ b/arch/sh/mm/fault.c @@ -24,20 +24,6 @@ #include <asm/tlbflush.h> #include <asm/traps.h> -static inline int notify_page_fault(struct pt_regs *regs, int trap) -{ - int ret = 0; - - if (kprobes_built_in() && !user_mode(regs)) { - preempt_disable(); - if (kprobe_running() && kprobe_fault_handler(regs, trap)) - ret = 1; - preempt_enable(); - } - - return ret; -} - static void force_sig_info_fault(int si_signo, int si_code, unsigned long address) { @@ -412,14 +398,14 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, if (unlikely(fault_in_kernel_space(address))) { if (vmalloc_fault(address) >= 0) return; - if (notify_page_fault(regs, vec)) + if (kprobe_page_fault(regs, vec)) return; bad_area_nosemaphore(regs, error_code, address); return; } - if (unlikely(notify_page_fault(regs, vec))) + if (unlikely(kprobe_page_fault(regs, vec))) return; /* Only enable interrupts if they were on before the fault */ diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index 13c6a6bb5fd9..dfdbaa50946e 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -429,7 +429,6 @@ int memory_add_physaddr_to_nid(u64 addr) EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid); #endif -#ifdef CONFIG_MEMORY_HOTREMOVE void arch_remove_memory(int nid, u64 start, u64 size, struct vmem_altmap *altmap) { @@ -440,5 +439,4 @@ void arch_remove_memory(int nid, u64 start, u64 size, zone = page_zone(pfn_to_page(start_pfn)); __remove_pages(zone, start_pfn, nr_pages, altmap); } -#endif #endif /* CONFIG_MEMORY_HOTPLUG */ diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index e9f5d62e9817..7926a2e11bdc 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -180,7 +180,7 @@ config SMP Y to "Enhanced Real Time Clock Support", below. The "Advanced Power Management" code will be disabled if you say Y here. - See also <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO + See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at <http://www.tldp.org/docs.html#howto>. If you don't know what to do here, say N. diff --git a/arch/sparc/include/uapi/asm/mman.h b/arch/sparc/include/uapi/asm/mman.h index f6f99ec65bb3..cec9f4109687 100644 --- a/arch/sparc/include/uapi/asm/mman.h +++ b/arch/sparc/include/uapi/asm/mman.h @@ -22,10 +22,4 @@ #define MCL_FUTURE 0x4000 /* lock all additions to address space */ #define MCL_ONFAULT 0x8000 /* lock all pages that are faulted in */ -#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ -#define MAP_STACK 0x20000 /* give out an address that is best suited for process/thread stacks */ -#define MAP_HUGETLB 0x40000 /* create a huge page mapping */ - - #endif /* _UAPI__SPARC_MMAN_H__ */ diff --git a/arch/sparc/kernel/syscalls/syscall.tbl b/arch/sparc/kernel/syscalls/syscall.tbl index c58e71f21129..8c8cc7537fb2 100644 --- a/arch/sparc/kernel/syscalls/syscall.tbl +++ b/arch/sparc/kernel/syscalls/syscall.tbl @@ -480,3 +480,4 @@ 432 common fsmount sys_fsmount 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open +# 435 reserved for clone3 diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c index 83fda4d9c3b2..2371fb6b97e4 100644 --- a/arch/sparc/mm/fault_64.c +++ b/arch/sparc/mm/fault_64.c @@ -38,20 +38,6 @@ int show_unhandled_signals = 1; -static inline __kprobes int notify_page_fault(struct pt_regs *regs) -{ - int ret = 0; - - /* kprobe_running() needs smp_processor_id() */ - if (kprobes_built_in() && !user_mode(regs)) { - preempt_disable(); - if (kprobe_running() && kprobe_fault_handler(regs, 0)) - ret = 1; - preempt_enable(); - } - return ret; -} - static void __kprobes unhandled_fault(unsigned long address, struct task_struct *tsk, struct pt_regs *regs) @@ -285,7 +271,7 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs) fault_code = get_thread_fault_code(); - if (notify_page_fault(regs)) + if (kprobe_page_fault(regs, 0)) goto exit_exception; si_code = SEGV_MAPERR; diff --git a/arch/sparc/vdso/Makefile b/arch/sparc/vdso/Makefile index 5a9e4e1f9f81..324a23947585 100644 --- a/arch/sparc/vdso/Makefile +++ b/arch/sparc/vdso/Makefile @@ -115,8 +115,7 @@ quiet_cmd_vdso = VDSO $@ -T $(filter %.lds,$^) $(filter %.o,$^) && \ sh $(srctree)/$(src)/checkundef.sh '$(OBJDUMP)' '$@' -VDSO_LDFLAGS = -shared $(call ld-option, --hash-style=both) \ - $(call ld-option, --build-id) -Bsymbolic +VDSO_LDFLAGS = -shared --hash-style=both --build-id -Bsymbolic GCOV_PROFILE := n # diff --git a/arch/um/Kconfig b/arch/um/Kconfig index 6b6eb938fcc1..3c3adfc486f2 100644 --- a/arch/um/Kconfig +++ b/arch/um/Kconfig @@ -184,6 +184,18 @@ config SECCOMP If unsure, say Y. +config UML_TIME_TRAVEL_SUPPORT + bool + prompt "Support time-travel mode (e.g. for test execution)" + help + Enable this option to support time travel inside the UML instance. + + After enabling this option, two modes are accessible at runtime + (selected by the kernel command line), see the kernel's command- + line help for more details. + + It is safe to say Y, but you probably don't need this. + endmenu source "arch/um/drivers/Kconfig" diff --git a/arch/um/configs/i386_defconfig b/arch/um/configs/i386_defconfig index 8f114e3b0a7a..73e98bb57bf5 100644 --- a/arch/um/configs/i386_defconfig +++ b/arch/um/configs/i386_defconfig @@ -36,7 +36,6 @@ CONFIG_XTERM_CHAN=y CONFIG_CON_CHAN="pts" CONFIG_SSL_CHAN="pts" CONFIG_UML_SOUND=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_BLK_DEV_UBD=y diff --git a/arch/um/configs/x86_64_defconfig b/arch/um/configs/x86_64_defconfig index 5d0875fc0db2..3281d7600225 100644 --- a/arch/um/configs/x86_64_defconfig +++ b/arch/um/configs/x86_64_defconfig @@ -34,7 +34,6 @@ CONFIG_XTERM_CHAN=y CONFIG_CON_CHAN="pts" CONFIG_SSL_CHAN="pts" CONFIG_UML_SOUND=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_BLK_DEV_UBD=y diff --git a/arch/um/drivers/chan_kern.c b/arch/um/drivers/chan_kern.c index a4e64edb8f38..749d2bf59599 100644 --- a/arch/um/drivers/chan_kern.c +++ b/arch/um/drivers/chan_kern.c @@ -171,19 +171,55 @@ int enable_chan(struct line *line) return err; } +/* Items are added in IRQ context, when free_irq can't be called, and + * removed in process context, when it can. + * This handles interrupt sources which disappear, and which need to + * be permanently disabled. This is discovered in IRQ context, but + * the freeing of the IRQ must be done later. + */ +static DEFINE_SPINLOCK(irqs_to_free_lock); +static LIST_HEAD(irqs_to_free); + +void free_irqs(void) +{ + struct chan *chan; + LIST_HEAD(list); + struct list_head *ele; + unsigned long flags; + + spin_lock_irqsave(&irqs_to_free_lock, flags); + list_splice_init(&irqs_to_free, &list); + spin_unlock_irqrestore(&irqs_to_free_lock, flags); + + list_for_each(ele, &list) { + chan = list_entry(ele, struct chan, free_list); + + if (chan->input && chan->enabled) + um_free_irq(chan->line->driver->read_irq, chan); + if (chan->output && chan->enabled) + um_free_irq(chan->line->driver->write_irq, chan); + chan->enabled = 0; + } +} + static void close_one_chan(struct chan *chan, int delay_free_irq) { + unsigned long flags; + if (!chan->opened) return; - /* we can safely call free now - it will be marked - * as free and freed once the IRQ stopped processing - */ - if (chan->input && chan->enabled) - um_free_irq(chan->line->driver->read_irq, chan); - if (chan->output && chan->enabled) - um_free_irq(chan->line->driver->write_irq, chan); - chan->enabled = 0; + if (delay_free_irq) { + spin_lock_irqsave(&irqs_to_free_lock, flags); + list_add(&chan->free_list, &irqs_to_free); + spin_unlock_irqrestore(&irqs_to_free_lock, flags); + } else { + if (chan->input && chan->enabled) + um_free_irq(chan->line->driver->read_irq, chan); + if (chan->output && chan->enabled) + um_free_irq(chan->line->driver->write_irq, chan); + chan->enabled = 0; + } if (chan->ops->close != NULL) (*chan->ops->close)(chan->fd, chan->data); diff --git a/arch/um/drivers/ssl.c b/arch/um/drivers/ssl.c index b8d14fa52059..7ae407d5337e 100644 --- a/arch/um/drivers/ssl.c +++ b/arch/um/drivers/ssl.c @@ -12,7 +12,6 @@ #include <linux/console.h> #include <asm/termbits.h> #include <asm/irq.h> -#include "ssl.h" #include "chan.h" #include <init.h> #include <irq_user.h> diff --git a/arch/um/drivers/ssl.h b/arch/um/drivers/ssl.h deleted file mode 100644 index 314d17725ce6..000000000000 --- a/arch/um/drivers/ssl.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2000 Jeff Dike (jdike@karaya.com) - * Licensed under the GPL - */ - -#ifndef __SSL_H__ -#define __SSL_H__ - -extern int ssl_read(int fd, int line); -extern void ssl_receive_char(int line, char ch); - -#endif - diff --git a/arch/um/include/asm/mmu_context.h b/arch/um/include/asm/mmu_context.h index 9f4b4bb78120..00cefd33afdd 100644 --- a/arch/um/include/asm/mmu_context.h +++ b/arch/um/include/asm/mmu_context.h @@ -52,7 +52,7 @@ static inline void activate_mm(struct mm_struct *old, struct mm_struct *new) * when the new ->mm is used for the first time. */ __switch_mm(&new->context.id); - down_write(&new->mmap_sem); + down_write_nested(&new->mmap_sem, 1); uml_setup_stubs(new); up_write(&new->mmap_sem); } diff --git a/arch/um/include/shared/os.h b/arch/um/include/shared/os.h index ebf23012a59b..4a62ac4251a5 100644 --- a/arch/um/include/shared/os.h +++ b/arch/um/include/shared/os.h @@ -250,15 +250,13 @@ extern void os_warn(const char *fmt, ...) /* time.c */ extern void os_idle_sleep(unsigned long long nsecs); -extern int os_timer_create(void* timer); -extern int os_timer_set_interval(void* timer, void* its); -extern int os_timer_one_shot(int ticks); -extern long long os_timer_disable(void); -extern long os_timer_remain(void* timer); +extern int os_timer_create(void); +extern int os_timer_set_interval(unsigned long long nsecs); +extern int os_timer_one_shot(unsigned long long nsecs); +extern void os_timer_disable(void); extern void uml_idle_timer(void); extern long long os_persistent_clock_emulation(void); extern long long os_nsecs(void); -extern long long os_vnsecs(void); /* skas/mem.c */ extern long run_syscall_stub(struct mm_id * mm_idp, diff --git a/arch/um/include/shared/timer-internal.h b/arch/um/include/shared/timer-internal.h index 03e6f217f807..8574338bf23b 100644 --- a/arch/um/include/shared/timer-internal.h +++ b/arch/um/include/shared/timer-internal.h @@ -10,4 +10,52 @@ #define TIMER_MULTIPLIER 256 #define TIMER_MIN_DELTA 500 +enum time_travel_mode { + TT_MODE_OFF, + TT_MODE_BASIC, + TT_MODE_INFCPU, +}; + +enum time_travel_timer_mode { + TT_TMR_DISABLED, + TT_TMR_ONESHOT, + TT_TMR_PERIODIC, +}; + +#ifdef CONFIG_UML_TIME_TRAVEL_SUPPORT +extern enum time_travel_mode time_travel_mode; +extern unsigned long long time_travel_time; +extern enum time_travel_timer_mode time_travel_timer_mode; +extern unsigned long long time_travel_timer_expiry; +extern unsigned long long time_travel_timer_interval; + +static inline void time_travel_set_time(unsigned long long ns) +{ + time_travel_time = ns; +} + +static inline void time_travel_set_timer(enum time_travel_timer_mode mode, + unsigned long long expiry) +{ + time_travel_timer_mode = mode; + time_travel_timer_expiry = expiry; +} +#else +#define time_travel_mode TT_MODE_OFF +#define time_travel_time 0 +#define time_travel_timer_expiry 0 +#define time_travel_timer_interval 0 + +static inline void time_travel_set_time(unsigned long long ns) +{ +} + +static inline void time_travel_set_timer(enum time_travel_timer_mode mode, + unsigned long long expiry) +{ +} + +#define time_travel_timer_mode TT_TMR_DISABLED +#endif + #endif diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c index 598d7b3d9355..efde1f16c603 100644 --- a/arch/um/kernel/irq.c +++ b/arch/um/kernel/irq.c @@ -21,6 +21,8 @@ #include <irq_user.h> +extern void free_irqs(void); + /* When epoll triggers we do not know why it did so * we can also have different IRQs for read and write. * This is why we keep a small irq_fd array for each fd - @@ -100,6 +102,8 @@ void sigio_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs) } } } + + free_irqs(); } static int assign_epoll_events_to_irq(struct irq_entry *irq_entry) @@ -380,10 +384,8 @@ EXPORT_SYMBOL(deactivate_fd); */ int deactivate_all_fds(void) { - unsigned long flags; struct irq_entry *to_free; - spin_lock_irqsave(&irq_lock, flags); /* Stop IO. The IRQ loop has no lock so this is our * only way of making sure we are safe to dispose * of all IRQ handlers @@ -399,8 +401,7 @@ int deactivate_all_fds(void) ); to_free = to_free->next; } - garbage_collect_irq_entries(); - spin_unlock_irqrestore(&irq_lock, flags); + /* don't garbage collect - we can no longer call kfree() here */ os_close_epoll_fd(); return 0; } diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c index 691b83b10649..67c0d1a860e9 100644 --- a/arch/um/kernel/process.c +++ b/arch/um/kernel/process.c @@ -203,10 +203,50 @@ void initial_thread_cb(void (*proc)(void *), void *arg) kmalloc_ok = save_kmalloc_ok; } +static void time_travel_sleep(unsigned long long duration) +{ + unsigned long long next = time_travel_time + duration; + + if (time_travel_mode != TT_MODE_INFCPU) + os_timer_disable(); + + if (time_travel_timer_mode != TT_TMR_DISABLED || + time_travel_timer_expiry < next) { + if (time_travel_timer_mode == TT_TMR_ONESHOT) + time_travel_set_timer(TT_TMR_DISABLED, 0); + /* + * time_travel_time will be adjusted in the timer + * IRQ handler so it works even when the signal + * comes from the OS timer + */ + deliver_alarm(); + } else { + time_travel_set_time(next); + } + + if (time_travel_mode != TT_MODE_INFCPU) { + if (time_travel_timer_mode == TT_TMR_PERIODIC) + os_timer_set_interval(time_travel_timer_interval); + else if (time_travel_timer_mode == TT_TMR_ONESHOT) + os_timer_one_shot(time_travel_timer_expiry - next); + } +} + +static void um_idle_sleep(void) +{ + unsigned long long duration = UM_NSEC_PER_SEC; + + if (time_travel_mode != TT_MODE_OFF) { + time_travel_sleep(duration); + } else { + os_idle_sleep(duration); + } +} + void arch_cpu_idle(void) { cpu_tasks[current_thread_info()->cpu].pid = os_getpid(); - os_idle_sleep(UM_NSEC_PER_SEC); + um_idle_sleep(); local_irq_enable(); } diff --git a/arch/um/kernel/skas/Makefile b/arch/um/kernel/skas/Makefile index 0b76d8869c94..5bd3edfcfedf 100644 --- a/arch/um/kernel/skas/Makefile +++ b/arch/um/kernel/skas/Makefile @@ -12,4 +12,6 @@ obj-y := clone.o mmu.o process.o syscall.o uaccess.o CFLAGS_clone.o := $(CFLAGS_NO_HARDENING) UNPROFILE_OBJS := clone.o +KCOV_INSTRUMENT := n + include arch/um/scripts/Makefile.rules diff --git a/arch/um/kernel/skas/syscall.c b/arch/um/kernel/skas/syscall.c index b783ac87d98a..44bb10785075 100644 --- a/arch/um/kernel/skas/syscall.c +++ b/arch/um/kernel/skas/syscall.c @@ -10,12 +10,23 @@ #include <sysdep/ptrace.h> #include <sysdep/ptrace_user.h> #include <sysdep/syscalls.h> +#include <shared/timer-internal.h> void handle_syscall(struct uml_pt_regs *r) { struct pt_regs *regs = container_of(r, struct pt_regs, regs); int syscall; + /* + * If we have infinite CPU resources, then make every syscall also a + * preemption point, since we don't have any other preemption in this + * case, and kernel threads would basically never run until userspace + * went to sleep, even if said userspace interacts with the kernel in + * various ways. + */ + if (time_travel_mode == TT_MODE_INFCPU) + schedule(); + /* Initialize the syscall number and default return value. */ UPT_SYSCALL_NR(r) = PT_SYSCALL_NR(r->gp); PT_REGS_SET_SYSCALL_RETURN(regs, -ENOSYS); diff --git a/arch/um/kernel/time.c b/arch/um/kernel/time.c index 0c572a48158e..6a051b078359 100644 --- a/arch/um/kernel/time.c +++ b/arch/um/kernel/time.c @@ -19,11 +19,29 @@ #include <kern_util.h> #include <os.h> #include <timer-internal.h> +#include <shared/init.h> + +#ifdef CONFIG_UML_TIME_TRAVEL_SUPPORT +enum time_travel_mode time_travel_mode; +unsigned long long time_travel_time; +enum time_travel_timer_mode time_travel_timer_mode; +unsigned long long time_travel_timer_expiry; +unsigned long long time_travel_timer_interval; + +static bool time_travel_start_set; +static unsigned long long time_travel_start; +#else +#define time_travel_start_set 0 +#define time_travel_start 0 +#endif void timer_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs) { unsigned long flags; + if (time_travel_mode != TT_MODE_OFF) + time_travel_set_time(time_travel_timer_expiry); + local_irq_save(flags); do_IRQ(TIMER_IRQ, regs); local_irq_restore(flags); @@ -31,26 +49,47 @@ void timer_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs) static int itimer_shutdown(struct clock_event_device *evt) { - os_timer_disable(); + if (time_travel_mode != TT_MODE_OFF) + time_travel_set_timer(TT_TMR_DISABLED, 0); + + if (time_travel_mode != TT_MODE_INFCPU) + os_timer_disable(); + return 0; } static int itimer_set_periodic(struct clock_event_device *evt) { - os_timer_set_interval(NULL, NULL); + unsigned long long interval = NSEC_PER_SEC / HZ; + + if (time_travel_mode != TT_MODE_OFF) + time_travel_set_timer(TT_TMR_PERIODIC, + time_travel_time + interval); + + if (time_travel_mode != TT_MODE_INFCPU) + os_timer_set_interval(interval); + return 0; } static int itimer_next_event(unsigned long delta, struct clock_event_device *evt) { - return os_timer_one_shot(delta); + delta += 1; + + if (time_travel_mode != TT_MODE_OFF) + time_travel_set_timer(TT_TMR_ONESHOT, + time_travel_time + delta); + + if (time_travel_mode != TT_MODE_INFCPU) + return os_timer_one_shot(delta); + + return 0; } static int itimer_one_shot(struct clock_event_device *evt) { - os_timer_one_shot(1); - return 0; + return itimer_next_event(0, evt); } static struct clock_event_device timer_clockevent = { @@ -87,6 +126,17 @@ static irqreturn_t um_timer(int irq, void *dev) static u64 timer_read(struct clocksource *cs) { + if (time_travel_mode != TT_MODE_OFF) { + /* + * We make reading the timer cost a bit so that we don't get + * stuck in loops that expect time to move more than the + * exact requested sleep amount, e.g. python's socket server, + * see https://bugs.python.org/issue37026. + */ + time_travel_set_time(time_travel_time + TIMER_MULTIPLIER); + return time_travel_time / TIMER_MULTIPLIER; + } + return os_nsecs() / TIMER_MULTIPLIER; } @@ -107,7 +157,7 @@ static void __init um_timer_setup(void) printk(KERN_ERR "register_timer : request_irq failed - " "errno = %d\n", -err); - err = os_timer_create(NULL); + err = os_timer_create(); if (err != 0) { printk(KERN_ERR "creation of timer failed - errno = %d\n", -err); return; @@ -123,7 +173,12 @@ static void __init um_timer_setup(void) void read_persistent_clock64(struct timespec64 *ts) { - long long nsecs = os_persistent_clock_emulation(); + long long nsecs; + + if (time_travel_start_set) + nsecs = time_travel_start + time_travel_time; + else + nsecs = os_persistent_clock_emulation(); set_normalized_timespec64(ts, nsecs / NSEC_PER_SEC, nsecs % NSEC_PER_SEC); @@ -134,3 +189,65 @@ void __init time_init(void) timer_set_signal_handler(); late_time_init = um_timer_setup; } + +#ifdef CONFIG_UML_TIME_TRAVEL_SUPPORT +unsigned long calibrate_delay_is_known(void) +{ + if (time_travel_mode == TT_MODE_INFCPU) + return 1; + return 0; +} + +int setup_time_travel(char *str) +{ + if (strcmp(str, "=inf-cpu") == 0) { + time_travel_mode = TT_MODE_INFCPU; + timer_clockevent.name = "time-travel-timer-infcpu"; + timer_clocksource.name = "time-travel-clock"; + return 1; + } + + if (!*str) { + time_travel_mode = TT_MODE_BASIC; + timer_clockevent.name = "time-travel-timer"; + timer_clocksource.name = "time-travel-clock"; + return 1; + } + + return -EINVAL; +} + +__setup("time-travel", setup_time_travel); +__uml_help(setup_time_travel, +"time-travel\n" +"This option just enables basic time travel mode, in which the clock/timers\n" +"inside the UML instance skip forward when there's nothing to do, rather than\n" +"waiting for real time to elapse. However, instance CPU speed is limited by\n" +"the real CPU speed, so e.g. a 10ms timer will always fire after ~10ms wall\n" +"clock (but quicker when there's nothing to do).\n" +"\n" +"time-travel=inf-cpu\n" +"This enables time travel mode with infinite processing power, in which there\n" +"are no wall clock timers, and any CPU processing happens - as seen from the\n" +"guest - instantly. This can be useful for accurate simulation regardless of\n" +"debug overhead, physical CPU speed, etc. but is somewhat dangerous as it can\n" +"easily lead to getting stuck (e.g. if anything in the system busy loops).\n"); + +int setup_time_travel_start(char *str) +{ + int err; + + err = kstrtoull(str, 0, &time_travel_start); + if (err) + return err; + + time_travel_start_set = 1; + return 1; +} + +__setup("time-travel-start", setup_time_travel_start); +__uml_help(setup_time_travel_start, +"time-travel-start=<seconds>\n" +"Configure the UML instance's wall clock to start at this value rather than\n" +"the host's wall clock at the time of UML boot.\n"); +#endif diff --git a/arch/um/os-Linux/time.c b/arch/um/os-Linux/time.c index 0e39b9978729..6d94ff52362c 100644 --- a/arch/um/os-Linux/time.c +++ b/arch/um/os-Linux/time.c @@ -26,11 +26,11 @@ static inline long long timeval_to_ns(const struct timeval *tv) static inline long long timespec_to_ns(const struct timespec *ts) { - return ((long long) ts->tv_sec * UM_NSEC_PER_SEC) + - ts->tv_nsec; + return ((long long) ts->tv_sec * UM_NSEC_PER_SEC) + ts->tv_nsec; } -long long os_persistent_clock_emulation (void) { +long long os_persistent_clock_emulation(void) +{ struct timespec realtime_tp; clock_gettime(CLOCK_REALTIME, &realtime_tp); @@ -40,94 +40,41 @@ long long os_persistent_clock_emulation (void) { /** * os_timer_create() - create an new posix (interval) timer */ -int os_timer_create(void* timer) { - - timer_t* t = timer; - - if(t == NULL) { - t = &event_high_res_timer; - } +int os_timer_create(void) +{ + timer_t *t = &event_high_res_timer; - if (timer_create( - CLOCK_MONOTONIC, - NULL, - t) == -1) { + if (timer_create(CLOCK_MONOTONIC, NULL, t) == -1) return -1; - } + return 0; } -int os_timer_set_interval(void* timer, void* i) +int os_timer_set_interval(unsigned long long nsecs) { struct itimerspec its; - unsigned long long nsec; - timer_t* t = timer; - struct itimerspec* its_in = i; - - if(t == NULL) { - t = &event_high_res_timer; - } - nsec = UM_NSEC_PER_SEC / UM_HZ; + its.it_value.tv_sec = nsecs / UM_NSEC_PER_SEC; + its.it_value.tv_nsec = nsecs % UM_NSEC_PER_SEC; - if(its_in != NULL) { - its.it_value.tv_sec = its_in->it_value.tv_sec; - its.it_value.tv_nsec = its_in->it_value.tv_nsec; - } else { - its.it_value.tv_sec = 0; - its.it_value.tv_nsec = nsec; - } + its.it_interval.tv_sec = nsecs / UM_NSEC_PER_SEC; + its.it_interval.tv_nsec = nsecs % UM_NSEC_PER_SEC; - its.it_interval.tv_sec = 0; - its.it_interval.tv_nsec = nsec; - - if(timer_settime(*t, 0, &its, NULL) == -1) { + if (timer_settime(event_high_res_timer, 0, &its, NULL) == -1) return -errno; - } return 0; } -/** - * os_timer_remain() - returns the remaining nano seconds of the given interval - * timer - * Because this is the remaining time of an interval timer, which correspondends - * to HZ, this value can never be bigger than one second. Just - * the nanosecond part of the timer is returned. - * The returned time is relative to the start time of the interval timer. - * Return an negative value in an error case. - */ -long os_timer_remain(void* timer) +int os_timer_one_shot(unsigned long long nsecs) { - struct itimerspec its; - timer_t* t = timer; - - if(t == NULL) { - t = &event_high_res_timer; - } - - if(timer_gettime(t, &its) == -1) { - return -errno; - } + struct itimerspec its = { + .it_value.tv_sec = nsecs / UM_NSEC_PER_SEC, + .it_value.tv_nsec = nsecs % UM_NSEC_PER_SEC, - return its.it_value.tv_nsec; -} - -int os_timer_one_shot(int ticks) -{ - struct itimerspec its; - unsigned long long nsec; - unsigned long sec; - - nsec = (ticks + 1); - sec = nsec / UM_NSEC_PER_SEC; - nsec = nsec % UM_NSEC_PER_SEC; - - its.it_value.tv_sec = nsec / UM_NSEC_PER_SEC; - its.it_value.tv_nsec = nsec; - - its.it_interval.tv_sec = 0; - its.it_interval.tv_nsec = 0; // we cheat here + .it_interval.tv_sec = 0, + .it_interval.tv_nsec = 0, // we cheat here + }; timer_settime(event_high_res_timer, 0, &its, NULL); return 0; @@ -135,24 +82,13 @@ int os_timer_one_shot(int ticks) /** * os_timer_disable() - disable the posix (interval) timer - * Returns the remaining interval timer time in nanoseconds */ -long long os_timer_disable(void) +void os_timer_disable(void) { struct itimerspec its; memset(&its, 0, sizeof(struct itimerspec)); - timer_settime(event_high_res_timer, 0, &its, &its); - - return its.it_value.tv_sec * UM_NSEC_PER_SEC + its.it_value.tv_nsec; -} - -long long os_vnsecs(void) -{ - struct timespec ts; - - clock_gettime(CLOCK_PROCESS_CPUTIME_ID,&ts); - return timespec_to_ns(&ts); + timer_settime(event_high_res_timer, 0, &its, NULL); } long long os_nsecs(void) @@ -169,21 +105,14 @@ long long os_nsecs(void) */ void os_idle_sleep(unsigned long long nsecs) { - struct timespec ts; - - if (nsecs <= 0) { - return; - } - - ts = ((struct timespec) { - .tv_sec = nsecs / UM_NSEC_PER_SEC, - .tv_nsec = nsecs % UM_NSEC_PER_SEC - }); + struct timespec ts = { + .tv_sec = nsecs / UM_NSEC_PER_SEC, + .tv_nsec = nsecs % UM_NSEC_PER_SEC + }; /* * Relay the signal if clock_nanosleep is interrupted. */ - if (clock_nanosleep(CLOCK_MONOTONIC, 0, &ts, NULL)) { + if (clock_nanosleep(CLOCK_MONOTONIC, 0, &ts, NULL)) deliver_alarm(); - } } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9df2d1cb7a9e..222855cc0158 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -70,6 +70,7 @@ config X86 select ARCH_HAS_KCOV if X86_64 select ARCH_HAS_MEMBARRIER_SYNC_CORE select ARCH_HAS_PMEM_API if X86_64 + select ARCH_HAS_PTE_DEVMAP if X86_64 select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_REFCOUNT select ARCH_HAS_UACCESS_FLUSHCACHE if X86_64 @@ -80,7 +81,6 @@ config X86 select ARCH_HAS_STRICT_MODULE_RWX select ARCH_HAS_SYNC_CORE_BEFORE_USERMODE select ARCH_HAS_UBSAN_SANITIZE_ALL - select ARCH_HAS_ZONE_DEVICE if X86_64 select ARCH_HAVE_NMI_SAFE_CMPXCHG select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI select ARCH_MIGHT_HAVE_PC_PARPORT @@ -94,6 +94,7 @@ config X86 select ARCH_USE_QUEUED_SPINLOCKS select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH select ARCH_WANTS_DYNAMIC_TASK_STRUCT + select ARCH_WANT_HUGE_PMD_SHARE select ARCH_WANTS_THP_SWAP if X86_64 select BUILDTIME_EXTABLE_SORT select CLKEVT_I8253 @@ -307,9 +308,6 @@ config ARCH_HIBERNATION_POSSIBLE config ARCH_SUSPEND_POSSIBLE def_bool y -config ARCH_WANT_HUGE_PMD_SHARE - def_bool y - config ARCH_WANT_GENERAL_HUGETLB def_bool y @@ -402,7 +400,7 @@ config SMP Management" code will be disabled if you say Y here. See also <file:Documentation/x86/i386/IO-APIC.rst>, - <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at + <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at <http://www.tldp.org/docs.html#howto>. If you don't know what to do here, say N. @@ -1528,6 +1526,7 @@ config AMD_MEM_ENCRYPT depends on X86_64 && CPU_SUP_AMD select DYNAMIC_PHYSICAL_MASK select ARCH_USE_MEMREMAP_PROT + select ARCH_HAS_FORCE_DMA_UNENCRYPTED ---help--- Say yes to enable support for the encryption of system memory. This requires an AMD processor that supports Secure Memory @@ -1959,7 +1958,7 @@ config EFI_STUB This kernel feature allows a bzImage to be loaded directly by EFI firmware without the use of a bootloader. - See Documentation/efi-stub.txt for more information. + See Documentation/admin-guide/efi-stub.rst for more information. config EFI_MIXED bool "EFI mixed-mode support" @@ -2057,7 +2056,7 @@ config CRASH_DUMP to a memory address not used by the main kernel or BIOS using PHYSICAL_START, or it must be built as a relocatable image (CONFIG_RELOCATABLE=y). - For more details see Documentation/kdump/kdump.rst + For more details see Documentation/admin-guide/kdump/kdump.rst config KEXEC_JUMP bool "kexec jump" @@ -2094,7 +2093,7 @@ config PHYSICAL_START the reserved region. In other words, it can be set based on the "X" value as specified in the "crashkernel=YM@XM" command line boot parameter passed to the panic-ed - kernel. Please take a look at Documentation/kdump/kdump.rst + kernel. Please take a look at Documentation/admin-guide/kdump/kdump.rst for more details about crash dumps. Usage of bzImage for capturing the crash dump is recommended as @@ -2482,7 +2481,7 @@ menuconfig APM machines with more than one CPU. In order to use APM, you will need supporting software. For location - and more information, read <file:Documentation/power/apm-acpi.txt> + and more information, read <file:Documentation/power/apm-acpi.rst> and the Battery Powered Linux mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>. @@ -2733,6 +2732,7 @@ config OLPC select OF select OF_PROMTREE select IRQ_DOMAIN + select OLPC_EC ---help--- Add support for detecting the unique features of the OLPC XO hardware. diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c index 220d1279d0e2..d6662fdef300 100644 --- a/arch/x86/boot/compressed/eboot.c +++ b/arch/x86/boot/compressed/eboot.c @@ -384,14 +384,11 @@ struct boot_params *make_boot_params(struct efi_config *c) struct apm_bios_info *bi; struct setup_header *hdr; efi_loaded_image_t *image; - void *options, *handle; + void *handle; efi_guid_t proto = LOADED_IMAGE_PROTOCOL_GUID; int options_size = 0; efi_status_t status; char *cmdline_ptr; - u16 *s2; - u8 *s1; - int i; unsigned long ramdisk_addr; unsigned long ramdisk_size; @@ -494,8 +491,6 @@ static void add_e820ext(struct boot_params *params, struct setup_data *e820ext, u32 nr_entries) { struct setup_data *data; - efi_status_t status; - unsigned long size; e820ext->type = SETUP_E820_EXT; e820ext->len = nr_entries * sizeof(struct boot_e820_entry); @@ -677,8 +672,6 @@ static efi_status_t exit_boot_func(efi_system_table_t *sys_table_arg, void *priv) { const char *signature; - __u32 nr_desc; - efi_status_t status; struct exit_boot_struct *p = priv; signature = efi_is_64bit() ? EFI64_LOADER_SIGNATURE @@ -747,7 +740,6 @@ struct boot_params * efi_main(struct efi_config *c, struct boot_params *boot_params) { struct desc_ptr *gdt = NULL; - efi_loaded_image_t *image; struct setup_header *hdr = &boot_params->hdr; efi_status_t status; struct desc_struct *desc; diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c index 24e65a0f756d..53ac0cb2396d 100644 --- a/arch/x86/boot/compressed/misc.c +++ b/arch/x86/boot/compressed/misc.c @@ -17,6 +17,7 @@ #include "pgtable.h" #include "../string.h" #include "../voffset.h" +#include <asm/bootparam_utils.h> /* * WARNING!! diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index d2f184165934..c8181392f70d 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -23,7 +23,6 @@ #include <asm/page.h> #include <asm/boot.h> #include <asm/bootparam.h> -#include <asm/bootparam_utils.h> #define BOOT_CTYPE_H #include <linux/acpi.h> diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c index f8debf7aeb4c..5f2d03067ae5 100644 --- a/arch/x86/boot/compressed/pgtable_64.c +++ b/arch/x86/boot/compressed/pgtable_64.c @@ -40,7 +40,6 @@ int cmdline_find_option_bool(const char *option); static unsigned long find_trampoline_placement(void) { unsigned long bios_start = 0, ebda_start = 0; - unsigned long trampoline_start; struct boot_e820_entry *entry; char *signature; int i; diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h index 9f1f9e3b8230..830bd984182b 100644 --- a/arch/x86/entry/calling.h +++ b/arch/x86/entry/calling.h @@ -343,3 +343,9 @@ For 32-bit we have the following conventions - kernel is built with .Lafter_call_\@: #endif .endm + +#ifdef CONFIG_PARAVIRT_XXL +#define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg +#else +#define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg +#endif diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index 90b473297299..2bb986f305ac 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -294,9 +294,11 @@ .Lfinished_frame_\@: .endm -.macro SAVE_ALL pt_regs_ax=%eax switch_stacks=0 +.macro SAVE_ALL pt_regs_ax=%eax switch_stacks=0 skip_gs=0 cld +.if \skip_gs == 0 PUSH_GS +.endif FIXUP_FRAME pushl %fs pushl %es @@ -313,13 +315,13 @@ movl %edx, %es movl $(__KERNEL_PERCPU), %edx movl %edx, %fs +.if \skip_gs == 0 SET_KERNEL_GS %edx - +.endif /* Switch to kernel stack if necessary */ .if \switch_stacks > 0 SWITCH_TO_KERNEL_STACK .endif - .endm .macro SAVE_ALL_NMI cr3_reg:req @@ -1441,39 +1443,46 @@ BUILD_INTERRUPT3(hv_stimer0_callback_vector, HYPERV_STIMER0_VECTOR, ENTRY(page_fault) ASM_CLAC - pushl $do_page_fault - ALIGN - jmp common_exception + pushl $0; /* %gs's slot on the stack */ + + SAVE_ALL switch_stacks=1 skip_gs=1 + + ENCODE_FRAME_POINTER + UNWIND_ESPFIX_STACK + + /* fixup %gs */ + GS_TO_REG %ecx + REG_TO_PTGS %ecx + SET_KERNEL_GS %ecx + + GET_CR2_INTO(%ecx) # might clobber %eax + + /* fixup orig %eax */ + movl PT_ORIG_EAX(%esp), %edx # get the error code + movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart + + TRACE_IRQS_OFF + movl %esp, %eax # pt_regs pointer + call do_page_fault + jmp ret_from_exception END(page_fault) common_exception: /* the function address is in %gs's slot on the stack */ - FIXUP_FRAME - pushl %fs - pushl %es - pushl %ds - pushl %eax - movl $(__USER_DS), %eax - movl %eax, %ds - movl %eax, %es - movl $(__KERNEL_PERCPU), %eax - movl %eax, %fs - pushl %ebp - pushl %edi - pushl %esi - pushl %edx - pushl %ecx - pushl %ebx - SWITCH_TO_KERNEL_STACK + SAVE_ALL switch_stacks=1 skip_gs=1 ENCODE_FRAME_POINTER - cld UNWIND_ESPFIX_STACK + + /* fixup %gs */ GS_TO_REG %ecx movl PT_GS(%esp), %edi # get the function address - movl PT_ORIG_EAX(%esp), %edx # get the error code - movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart REG_TO_PTGS %ecx SET_KERNEL_GS %ecx + + /* fixup orig %eax */ + movl PT_ORIG_EAX(%esp), %edx # get the error code + movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart + TRACE_IRQS_OFF movl %esp, %eax # pt_regs pointer CALL_NOSPEC %edi diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 0ea4831a72a4..3f5a978a02a7 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -864,18 +864,84 @@ apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt */ #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + (x) * 8) +.macro idtentry_part do_sym, has_error_code:req, read_cr2:req, paranoid:req, shift_ist=-1, ist_offset=0 + + .if \paranoid + call paranoid_entry + /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ + .else + call error_entry + .endif + UNWIND_HINT_REGS + + .if \read_cr2 + /* + * Store CR2 early so subsequent faults cannot clobber it. Use R12 as + * intermediate storage as RDX can be clobbered in enter_from_user_mode(). + * GET_CR2_INTO can clobber RAX. + */ + GET_CR2_INTO(%r12); + .endif + + .if \shift_ist != -1 + TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ + .else + TRACE_IRQS_OFF + .endif + + .if \paranoid == 0 + testb $3, CS(%rsp) + jz .Lfrom_kernel_no_context_tracking_\@ + CALL_enter_from_user_mode +.Lfrom_kernel_no_context_tracking_\@: + .endif + + movq %rsp, %rdi /* pt_regs pointer */ + + .if \has_error_code + movq ORIG_RAX(%rsp), %rsi /* get error code */ + movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ + .else + xorl %esi, %esi /* no error code */ + .endif + + .if \shift_ist != -1 + subq $\ist_offset, CPU_TSS_IST(\shift_ist) + .endif + + .if \read_cr2 + movq %r12, %rdx /* Move CR2 into 3rd argument */ + .endif + + call \do_sym + + .if \shift_ist != -1 + addq $\ist_offset, CPU_TSS_IST(\shift_ist) + .endif + + .if \paranoid + /* this procedure expect "no swapgs" flag in ebx */ + jmp paranoid_exit + .else + jmp error_exit + .endif + +.endm + /** * idtentry - Generate an IDT entry stub * @sym: Name of the generated entry point - * @do_sym: C function to be called - * @has_error_code: True if this IDT vector has an error code on the stack - * @paranoid: non-zero means that this vector may be invoked from + * @do_sym: C function to be called + * @has_error_code: True if this IDT vector has an error code on the stack + * @paranoid: non-zero means that this vector may be invoked from * kernel mode with user GSBASE and/or user CR3. * 2 is special -- see below. * @shift_ist: Set to an IST index if entries from kernel mode should - * decrement the IST stack so that nested entries get a + * decrement the IST stack so that nested entries get a * fresh stack. (This is for #DB, which has a nasty habit - * of recursing.) + * of recursing.) + * @create_gap: create a 6-word stack gap when coming from kernel mode. + * @read_cr2: load CR2 into the 3rd argument; done before calling any C code * * idtentry generates an IDT stub that sets up a usable kernel context, * creates struct pt_regs, and calls @do_sym. The stub has the following @@ -900,15 +966,19 @@ apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt * @paranoid == 2 is special: the stub will never switch stacks. This is for * #DF: if the thread stack is somehow unusable, we'll still get a useful OOPS. */ -.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 ist_offset=0 create_gap=0 +.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 ist_offset=0 create_gap=0 read_cr2=0 ENTRY(\sym) UNWIND_HINT_IRET_REGS offset=\has_error_code*8 /* Sanity check */ - .if \shift_ist != -1 && \paranoid == 0 + .if \shift_ist != -1 && \paranoid != 1 .error "using shift_ist requires paranoid=1" .endif + .if \create_gap && \paranoid + .error "using create_gap requires paranoid=0" + .endif + ASM_CLAC .if \has_error_code == 0 @@ -934,47 +1004,7 @@ ENTRY(\sym) .Lfrom_usermode_no_gap_\@: .endif - .if \paranoid - call paranoid_entry - .else - call error_entry - .endif - UNWIND_HINT_REGS - /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ - - .if \paranoid - .if \shift_ist != -1 - TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ - .else - TRACE_IRQS_OFF - .endif - .endif - - movq %rsp, %rdi /* pt_regs pointer */ - - .if \has_error_code - movq ORIG_RAX(%rsp), %rsi /* get error code */ - movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ - .else - xorl %esi, %esi /* no error code */ - .endif - - .if \shift_ist != -1 - subq $\ist_offset, CPU_TSS_IST(\shift_ist) - .endif - - call \do_sym - - .if \shift_ist != -1 - addq $\ist_offset, CPU_TSS_IST(\shift_ist) - .endif - - /* these procedures expect "no swapgs" flag in ebx */ - .if \paranoid - jmp paranoid_exit - .else - jmp error_exit - .endif + idtentry_part \do_sym, \has_error_code, \read_cr2, \paranoid, \shift_ist, \ist_offset .if \paranoid == 1 /* @@ -983,21 +1013,9 @@ ENTRY(\sym) * run in real process context if user_mode(regs). */ .Lfrom_usermode_switch_stack_\@: - call error_entry - - movq %rsp, %rdi /* pt_regs pointer */ - - .if \has_error_code - movq ORIG_RAX(%rsp), %rsi /* get error code */ - movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ - .else - xorl %esi, %esi /* no error code */ + idtentry_part \do_sym, \has_error_code, \read_cr2, paranoid=0 .endif - call \do_sym - - jmp error_exit - .endif _ASM_NOKPROBE(\sym) END(\sym) .endm @@ -1007,7 +1025,7 @@ idtentry overflow do_overflow has_error_code=0 idtentry bounds do_bounds has_error_code=0 idtentry invalid_op do_invalid_op has_error_code=0 idtentry device_not_available do_device_not_available has_error_code=0 -idtentry double_fault do_double_fault has_error_code=1 paranoid=2 +idtentry double_fault do_double_fault has_error_code=1 paranoid=2 read_cr2=1 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 idtentry invalid_TSS do_invalid_TSS has_error_code=1 idtentry segment_not_present do_segment_not_present has_error_code=1 @@ -1176,14 +1194,13 @@ idtentry stack_segment do_stack_segment has_error_code=1 #ifdef CONFIG_XEN_PV idtentry xennmi do_nmi has_error_code=0 idtentry xendebug do_debug has_error_code=0 -idtentry xenint3 do_int3 has_error_code=0 #endif idtentry general_protection do_general_protection has_error_code=1 -idtentry page_fault do_page_fault has_error_code=1 +idtentry page_fault do_page_fault has_error_code=1 read_cr2=1 #ifdef CONFIG_KVM_GUEST -idtentry async_page_fault do_async_page_fault has_error_code=1 +idtentry async_page_fault do_async_page_fault has_error_code=1 read_cr2=1 #endif #ifdef CONFIG_X86_MCE @@ -1282,18 +1299,9 @@ ENTRY(error_entry) movq %rax, %rsp /* switch stack */ ENCODE_FRAME_POINTER pushq %r12 - - /* - * We need to tell lockdep that IRQs are off. We can't do this until - * we fix gsbase, and we should do it before enter_from_user_mode - * (which can take locks). - */ - TRACE_IRQS_OFF - CALL_enter_from_user_mode ret .Lerror_entry_done: - TRACE_IRQS_OFF ret /* diff --git a/arch/x86/entry/thunk_64.S b/arch/x86/entry/thunk_64.S index cfdca8b42c70..cc20465b2867 100644 --- a/arch/x86/entry/thunk_64.S +++ b/arch/x86/entry/thunk_64.S @@ -12,9 +12,7 @@ /* rdi: arg1 ... normal C conventions. rax is saved/restored. */ .macro THUNK name, func, put_ret_addr_in_rdi=0 - .globl \name - .type \name, @function -\name: + ENTRY(\name) pushq %rbp movq %rsp, %rbp @@ -35,6 +33,7 @@ call \func jmp .L_restore + ENDPROC(\name) _ASM_NOKPROBE(\name) .endm diff --git a/arch/x86/entry/vdso/Makefile b/arch/x86/entry/vdso/Makefile index 39106111be86..8df549138193 100644 --- a/arch/x86/entry/vdso/Makefile +++ b/arch/x86/entry/vdso/Makefile @@ -56,8 +56,7 @@ VDSO_LDFLAGS_vdso.lds = -m elf_x86_64 -soname linux-vdso.so.1 --no-undefined \ -z max-page-size=4096 $(obj)/vdso64.so.dbg: $(obj)/vdso.lds $(vobjs) FORCE - $(call if_changed,vdso) - $(call if_changed,vdso_check) + $(call if_changed,vdso_and_check) HOST_EXTRACFLAGS += -I$(srctree)/tools/include -I$(srctree)/include/uapi -I$(srctree)/arch/$(SUBARCH)/include/uapi hostprogs-y += vdso2c @@ -127,8 +126,7 @@ $(obj)/%.so: $(obj)/%.so.dbg FORCE $(call if_changed,objcopy) $(obj)/vdsox32.so.dbg: $(obj)/vdsox32.lds $(vobjx32s) FORCE - $(call if_changed,vdso) - $(call if_changed,vdso_check) + $(call if_changed,vdso_and_check) CPPFLAGS_vdso32.lds = $(CPPFLAGS_vdso.lds) VDSO_LDFLAGS_vdso32.lds = -m elf_i386 -soname linux-gate.so.1 @@ -167,8 +165,7 @@ $(obj)/vdso32.so.dbg: FORCE \ $(obj)/vdso32/note.o \ $(obj)/vdso32/system_call.o \ $(obj)/vdso32/sigreturn.o - $(call if_changed,vdso) - $(call if_changed,vdso_check) + $(call if_changed,vdso_and_check) # # The DSO images are built using a special linker script. @@ -179,11 +176,13 @@ quiet_cmd_vdso = VDSO $@ -T $(filter %.lds,$^) $(filter %.o,$^) && \ sh $(srctree)/$(src)/checkundef.sh '$(NM)' '$@' -VDSO_LDFLAGS = -shared $(call ld-option, --hash-style=both) \ - $(call ld-option, --build-id) $(call ld-option, --eh-frame-hdr) \ - -Bsymbolic +VDSO_LDFLAGS = -shared --hash-style=both --build-id \ + $(call ld-option, --eh-frame-hdr) -Bsymbolic GCOV_PROFILE := n +quiet_cmd_vdso_and_check = VDSO $@ + cmd_vdso_and_check = $(cmd_vdso); $(cmd_vdso_check) + # # Install the unstripped copies of vdso*.so. If our toolchain supports # build-id, install .build-id links as well. diff --git a/arch/x86/entry/vdso/vdso32-setup.c b/arch/x86/entry/vdso/vdso32-setup.c index 42d4c89f990e..240626e7f55a 100644 --- a/arch/x86/entry/vdso/vdso32-setup.c +++ b/arch/x86/entry/vdso/vdso32-setup.c @@ -65,9 +65,6 @@ subsys_initcall(sysenter_setup); /* Register vsyscall32 into the ABI table */ #include <linux/sysctl.h> -static const int zero; -static const int one = 1; - static struct ctl_table abi_table2[] = { { .procname = "vsyscall32", @@ -75,8 +72,8 @@ static struct ctl_table abi_table2[] = { .maxlen = sizeof(int), .mode = 0644, .proc_handler = proc_dointvec_minmax, - .extra1 = (int *)&zero, - .extra2 = (int *)&one, + .extra1 = SYSCTL_ZERO, + .extra2 = SYSCTL_ONE, }, {} }; diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 85e6984c560b..a6ea07f2aa84 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -202,15 +202,22 @@ static int amd_uncore_event_init(struct perf_event *event) hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB; hwc->idx = -1; + if (event->cpu < 0) + return -EINVAL; + /* * SliceMask and ThreadMask need to be set for certain L3 events in * Family 17h. For other events, the two fields do not affect the count. */ - if (l3_mask) - hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK); + if (l3_mask && is_llc_event(event)) { + int thread = 2 * (cpu_data(event->cpu).cpu_core_id % 4); - if (event->cpu < 0) - return -EINVAL; + if (smp_num_siblings > 1) + thread += cpu_data(event->cpu).apicid & 1; + + hwc->config |= (1ULL << (AMD64_L3_THREAD_SHIFT + thread) & + AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK; + } uncore = event_to_amd_uncore(event); if (!uncore) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index bda450ff51ee..9e911a96972b 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2161,12 +2161,10 @@ static void intel_pmu_disable_event(struct perf_event *event) cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); cpuc->intel_cp_status &= ~(1ull << hwc->idx); - if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { + if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) intel_pmu_disable_fixed(hwc); - return; - } - - x86_pmu_disable_event(event); + else + x86_pmu_disable_event(event); /* * Needs to be called after x86_pmu_disable_event, diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c index 0e033ef11a9f..0d258688c8cf 100644 --- a/arch/x86/hyperv/hv_init.c +++ b/arch/x86/hyperv/hv_init.c @@ -60,8 +60,17 @@ static int hv_cpu_init(unsigned int cpu) if (!hv_vp_assist_page) return 0; - if (!*hvp) - *hvp = __vmalloc(PAGE_SIZE, GFP_KERNEL, PAGE_KERNEL); + /* + * The VP ASSIST PAGE is an "overlay" page (see Hyper-V TLFS's Section + * 5.2.1 "GPA Overlay Pages"). Here it must be zeroed out to make sure + * we always write the EOI MSR in hv_apic_eoi_write() *after* the + * EOI optimization is disabled in hv_cpu_die(), otherwise a CPU may + * not be stopped in the case of CPU offlining and the VM will hang. + */ + if (!*hvp) { + *hvp = __vmalloc(PAGE_SIZE, GFP_KERNEL | __GFP_ZERO, + PAGE_KERNEL); + } if (*hvp) { u64 val; diff --git a/arch/x86/ia32/sys_ia32.c b/arch/x86/ia32/sys_ia32.c index 64a6c952091e..21790307121e 100644 --- a/arch/x86/ia32/sys_ia32.c +++ b/arch/x86/ia32/sys_ia32.c @@ -239,6 +239,7 @@ COMPAT_SYSCALL_DEFINE5(x86_clone, unsigned long, clone_flags, { struct kernel_clone_args args = { .flags = (clone_flags & ~CSIGNAL), + .pidfd = parent_tidptr, .child_tid = child_tidptr, .parent_tid = parent_tidptr, .exit_signal = (clone_flags & CSIGNAL), @@ -246,5 +247,8 @@ COMPAT_SYSCALL_DEFINE5(x86_clone, unsigned long, clone_flags, .tls = tls_val, }; + if (!legacy_clone_args_valid(&args)) + return -EINVAL; + return _do_fork(&args); } diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 050e5f9ebf81..e647aa095867 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -49,7 +49,7 @@ static inline void generic_apic_probe(void) #ifdef CONFIG_X86_LOCAL_APIC -extern unsigned int apic_verbosity; +extern int apic_verbosity; extern int local_apic_timer_c2_ok; extern int disable_apic; diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h index 50a30f6c668b..e41cbf2ec41d 100644 --- a/arch/x86/include/asm/hypervisor.h +++ b/arch/x86/include/asm/hypervisor.h @@ -53,8 +53,20 @@ struct hypervisor_x86 { /* runtime callbacks */ struct x86_hyper_runtime runtime; + + /* ignore nopv parameter */ + bool ignore_nopv; }; +extern const struct hypervisor_x86 x86_hyper_vmware; +extern const struct hypervisor_x86 x86_hyper_ms_hyperv; +extern const struct hypervisor_x86 x86_hyper_xen_pv; +extern const struct hypervisor_x86 x86_hyper_kvm; +extern const struct hypervisor_x86 x86_hyper_jailhouse; +extern const struct hypervisor_x86 x86_hyper_acrn; +extern struct hypervisor_x86 x86_hyper_xen_hvm; + +extern bool nopv; extern enum x86_hypervisor_type x86_hyper_type; extern void init_hypervisor_platform(void); static inline bool hypervisor_is_type(enum x86_hypervisor_type type) diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index a06a9f8294ea..6bed97ff6db2 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -165,7 +165,6 @@ static inline unsigned int isa_virt_to_bus(volatile void *address) { return (unsigned int)virt_to_phys(address); } -#define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) #define isa_bus_to_virt phys_to_virt /* diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 0cc5b611a113..7b0a4ee77313 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -607,15 +607,16 @@ struct kvm_vcpu_arch { /* * QEMU userspace and the guest each have their own FPU state. - * In vcpu_run, we switch between the user, maintained in the - * task_struct struct, and guest FPU contexts. While running a VCPU, - * the VCPU thread will have the guest FPU context. + * In vcpu_run, we switch between the user and guest FPU contexts. + * While running a VCPU, the VCPU thread will have the guest FPU + * context. * * Note that while the PKRU state lives inside the fpu registers, * it is switched out separately at VMENTER and VMEXIT time. The * "guest_fpu" state here contains the guest FPU context, with the * host PRKU bits. */ + struct fpu *user_fpu; struct fpu *guest_fpu; u64 xcr0; @@ -1496,25 +1497,29 @@ enum { #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) +asmlinkage void __noreturn kvm_spurious_fault(void); + /* * Hardware virtualization extension instructions may fault if a * reboot turns off virtualization while processes are running. - * Trap the fault and ignore the instruction if that happens. + * Usually after catching the fault we just panic; during reboot + * instead the instruction is ignored. */ -asmlinkage void kvm_spurious_fault(void); - -#define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ - "666: " insn "\n\t" \ - "668: \n\t" \ - ".pushsection .fixup, \"ax\" \n" \ - "667: \n\t" \ - cleanup_insn "\n\t" \ - "cmpb $0, kvm_rebooting \n\t" \ - "jne 668b \n\t" \ - __ASM_SIZE(push) " $666b \n\t" \ - "jmp kvm_spurious_fault \n\t" \ - ".popsection \n\t" \ - _ASM_EXTABLE(666b, 667b) +#define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ + "666: \n\t" \ + insn "\n\t" \ + "jmp 668f \n\t" \ + "667: \n\t" \ + "call kvm_spurious_fault \n\t" \ + "668: \n\t" \ + ".pushsection .fixup, \"ax\" \n\t" \ + "700: \n\t" \ + cleanup_insn "\n\t" \ + "cmpb $0, kvm_rebooting\n\t" \ + "je 667b \n\t" \ + "jmp 668b \n\t" \ + ".popsection \n\t" \ + _ASM_EXTABLE(666b, 700b) #define __kvm_handle_fault_on_reboot(insn) \ ____kvm_handle_fault_on_reboot(insn, "") diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h index 5ed3cf1c3934..9b4df6eaa11a 100644 --- a/arch/x86/include/asm/kvm_para.h +++ b/arch/x86/include/asm/kvm_para.h @@ -92,7 +92,7 @@ void kvm_async_pf_task_wait(u32 token, int interrupt_kernel); void kvm_async_pf_task_wake(u32 token); u32 kvm_read_and_reset_pf_reason(void); extern void kvm_disable_steal_time(void); -void do_async_page_fault(struct pt_regs *regs, unsigned long error_code); +void do_async_page_fault(struct pt_regs *regs, unsigned long error_code, unsigned long address); #ifdef CONFIG_PARAVIRT_SPINLOCKS void __init kvm_spinlock_init(void); diff --git a/arch/x86/include/asm/olpc.h b/arch/x86/include/asm/olpc.h index c2bf1de5d901..6fe76282aceb 100644 --- a/arch/x86/include/asm/olpc.h +++ b/arch/x86/include/asm/olpc.h @@ -9,12 +9,10 @@ struct olpc_platform_t { int flags; uint32_t boardrev; - int ecver; }; #define OLPC_F_PRESENT 0x01 #define OLPC_F_DCON 0x02 -#define OLPC_F_EC_WIDE_SCI 0x04 #ifdef CONFIG_OLPC @@ -64,13 +62,6 @@ static inline int olpc_board_at_least(uint32_t rev) return olpc_platform_info.boardrev >= rev; } -extern void olpc_ec_wakeup_set(u16 value); -extern void olpc_ec_wakeup_clear(u16 value); -extern bool olpc_ec_wakeup_available(void); - -extern int olpc_ec_mask_write(u16 bits); -extern int olpc_ec_sci_query(u16 *sci_value); - #else static inline int machine_is_olpc(void) @@ -83,14 +74,6 @@ static inline int olpc_has_dcon(void) return 0; } -static inline void olpc_ec_wakeup_set(u16 value) { } -static inline void olpc_ec_wakeup_clear(u16 value) { } - -static inline bool olpc_ec_wakeup_available(void) -{ - return false; -} - #endif #ifdef CONFIG_OLPC_XO1_PM @@ -101,20 +84,6 @@ extern void olpc_xo1_pm_wakeup_clear(u16 value); extern int pci_olpc_init(void); -/* SCI source values */ - -#define EC_SCI_SRC_EMPTY 0x00 -#define EC_SCI_SRC_GAME 0x01 -#define EC_SCI_SRC_BATTERY 0x02 -#define EC_SCI_SRC_BATSOC 0x04 -#define EC_SCI_SRC_BATERR 0x08 -#define EC_SCI_SRC_EBOOK 0x10 /* XO-1 only */ -#define EC_SCI_SRC_WLAN 0x20 /* XO-1 only */ -#define EC_SCI_SRC_ACPWR 0x40 -#define EC_SCI_SRC_BATCRIT 0x80 -#define EC_SCI_SRC_GPWAKE 0x100 /* XO-1.5 only */ -#define EC_SCI_SRC_ALL 0x1FF - /* GPIO assignments */ #define OLPC_GPIO_MIC_AC 1 diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index c25c38a05c1c..dce26f1d13e1 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -116,7 +116,7 @@ static inline void write_cr0(unsigned long x) static inline unsigned long read_cr2(void) { - return PVOP_CALL0(unsigned long, mmu.read_cr2); + return PVOP_CALLEE0(unsigned long, mmu.read_cr2); } static inline void write_cr2(unsigned long x) @@ -746,6 +746,7 @@ bool __raw_callee_save___native_vcpu_is_preempted(long cpu); PV_RESTORE_ALL_CALLER_REGS \ FRAME_END \ "ret;" \ + ".size " PV_THUNK_NAME(func) ", .-" PV_THUNK_NAME(func) ";" \ ".popsection") /* Get a reference to a callee-save function */ @@ -909,13 +910,7 @@ extern void default_banner(void); ANNOTATE_RETPOLINE_SAFE; \ call PARA_INDIRECT(pv_ops+PV_CPU_swapgs); \ ) -#endif - -#define GET_CR2_INTO_RAX \ - ANNOTATE_RETPOLINE_SAFE; \ - call PARA_INDIRECT(pv_ops+PV_MMU_read_cr2); -#ifdef CONFIG_PARAVIRT_XXL #define USERGS_SYSRET64 \ PARA_SITE(PARA_PATCH(PV_CPU_usergs_sysret64), \ ANNOTATE_RETPOLINE_SAFE; \ @@ -929,9 +924,19 @@ extern void default_banner(void); call PARA_INDIRECT(pv_ops+PV_IRQ_save_fl); \ PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) #endif -#endif +#endif /* CONFIG_PARAVIRT_XXL */ +#endif /* CONFIG_X86_64 */ + +#ifdef CONFIG_PARAVIRT_XXL + +#define GET_CR2_INTO_AX \ + PARA_SITE(PARA_PATCH(PV_MMU_read_cr2), \ + ANNOTATE_RETPOLINE_SAFE; \ + call PARA_INDIRECT(pv_ops+PV_MMU_read_cr2); \ + ) + +#endif /* CONFIG_PARAVIRT_XXL */ -#endif /* CONFIG_X86_32 */ #endif /* __ASSEMBLY__ */ #else /* CONFIG_PARAVIRT */ diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index 946f8f1f1efc..639b2df445ee 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -220,7 +220,7 @@ struct pv_mmu_ops { void (*exit_mmap)(struct mm_struct *mm); #ifdef CONFIG_PARAVIRT_XXL - unsigned long (*read_cr2)(void); + struct paravirt_callee_save read_cr2; void (*write_cr2)(unsigned long); unsigned long (*read_cr3)(void); diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index 5e0509b41986..0bc530c4eb13 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -271,7 +271,7 @@ static inline int has_transparent_hugepage(void) return boot_cpu_has(X86_FEATURE_PSE); } -#ifdef __HAVE_ARCH_PTE_DEVMAP +#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP static inline int pmd_devmap(pmd_t pmd) { return !!(pmd_val(pmd) & _PAGE_DEVMAP); @@ -732,7 +732,7 @@ static inline int pte_present(pte_t a) return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); } -#ifdef __HAVE_ARCH_PTE_DEVMAP +#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP static inline int pte_devmap(pte_t a) { return (pte_flags(a) & _PAGE_DEVMAP) == _PAGE_DEVMAP; diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index d6ff0bbdb394..b5e49e6bac63 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -103,7 +103,6 @@ #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) #define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX) #define _PAGE_DEVMAP (_AT(u64, 1) << _PAGE_BIT_DEVMAP) -#define __HAVE_ARCH_PTE_DEVMAP #else #define _PAGE_NX (_AT(pteval_t, 0)) #define _PAGE_DEVMAP (_AT(pteval_t, 0)) diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 7d6f3f3fad78..b25e633033c3 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -40,7 +40,7 @@ asmlinkage void simd_coprocessor_error(void); asmlinkage void xen_divide_error(void); asmlinkage void xen_xennmi(void); asmlinkage void xen_xendebug(void); -asmlinkage void xen_xenint3(void); +asmlinkage void xen_int3(void); asmlinkage void xen_overflow(void); asmlinkage void xen_bounds(void); asmlinkage void xen_invalid_op(void); @@ -74,14 +74,14 @@ dotraplinkage void do_invalid_TSS(struct pt_regs *regs, long error_code); dotraplinkage void do_segment_not_present(struct pt_regs *regs, long error_code); dotraplinkage void do_stack_segment(struct pt_regs *regs, long error_code); #ifdef CONFIG_X86_64 -dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code); +dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code, unsigned long address); asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs); asmlinkage __visible notrace struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s); void __init trap_init(void); #endif dotraplinkage void do_general_protection(struct pt_regs *regs, long error_code); -dotraplinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code); +dotraplinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code, unsigned long address); dotraplinkage void do_spurious_interrupt_bug(struct pt_regs *regs, long error_code); dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code); dotraplinkage void do_alignment_check(struct pt_regs *regs, long error_code); diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index c82abd6e4ca3..9c4435307ff8 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -66,7 +66,9 @@ static inline bool __chk_range_not_ok(unsigned long addr, unsigned long size, un }) #ifdef CONFIG_DEBUG_ATOMIC_SLEEP -# define WARN_ON_IN_IRQ() WARN_ON_ONCE(!in_task()) +static inline bool pagefault_disabled(void); +# define WARN_ON_IN_IRQ() \ + WARN_ON_ONCE(!in_task() && !pagefault_disabled()) #else # define WARN_ON_IN_IRQ() #endif diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index b85a7c54c6a1..ac0934189017 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -301,6 +301,8 @@ extern struct x86_apic_ops x86_apic_ops; extern void x86_early_init_platform_quirks(void); extern void x86_init_noop(void); extern void x86_init_uint_noop(unsigned int unused); +extern bool bool_x86_init_noop(void); +extern void x86_op_int_noop(int cpu); extern bool x86_pnpbios_disabled(void); #endif diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/xen/hypervisor.h index 39171b3646bb..42e1245af0d8 100644 --- a/arch/x86/include/asm/xen/hypervisor.h +++ b/arch/x86/include/asm/xen/hypervisor.h @@ -44,14 +44,14 @@ static inline uint32_t xen_cpuid_base(void) } #ifdef CONFIG_XEN -extern bool xen_hvm_need_lapic(void); +extern bool __init xen_hvm_need_lapic(void); -static inline bool xen_x2apic_para_available(void) +static inline bool __init xen_x2apic_para_available(void) { return xen_hvm_need_lapic(); } #else -static inline bool xen_x2apic_para_available(void) +static inline bool __init xen_x2apic_para_available(void) { return (xen_cpuid_base() != 0); } diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h index e901b0ab116f..503d3f42da16 100644 --- a/arch/x86/include/uapi/asm/kvm.h +++ b/arch/x86/include/uapi/asm/kvm.h @@ -435,9 +435,12 @@ struct kvm_nested_state { /* for KVM_CAP_PMU_EVENT_FILTER */ struct kvm_pmu_event_filter { - __u32 action; - __u32 nevents; - __u64 events[0]; + __u32 action; + __u32 nevents; + __u32 fixed_counter_bitmap; + __u32 flags; + __u32 pad[4]; + __u64 events[0]; }; #define KVM_PMU_EVENT_ALLOW 0 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 1bd91cb7b320..f5291362da1a 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -183,7 +183,7 @@ EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); /* * Debug level, exported for io_apic.c */ -unsigned int apic_verbosity; +int apic_verbosity; int pic_mode; diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index da64452584b0..5c7ee3df4d0b 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -76,6 +76,7 @@ static void __used common(void) BLANK(); OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask); OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending); + OFFSET(XEN_vcpu_info_arch_cr2, vcpu_info, arch.cr2); #endif BLANK(); diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c index 87e39ad8d873..553bfbfc3a1b 100644 --- a/arch/x86/kernel/cpu/hypervisor.c +++ b/arch/x86/kernel/cpu/hypervisor.c @@ -26,14 +26,6 @@ #include <asm/processor.h> #include <asm/hypervisor.h> -extern const struct hypervisor_x86 x86_hyper_vmware; -extern const struct hypervisor_x86 x86_hyper_ms_hyperv; -extern const struct hypervisor_x86 x86_hyper_xen_pv; -extern const struct hypervisor_x86 x86_hyper_xen_hvm; -extern const struct hypervisor_x86 x86_hyper_kvm; -extern const struct hypervisor_x86 x86_hyper_jailhouse; -extern const struct hypervisor_x86 x86_hyper_acrn; - static const __initconst struct hypervisor_x86 * const hypervisors[] = { #ifdef CONFIG_XEN_PV @@ -58,6 +50,14 @@ static const __initconst struct hypervisor_x86 * const hypervisors[] = enum x86_hypervisor_type x86_hyper_type; EXPORT_SYMBOL(x86_hyper_type); +bool __initdata nopv; +static __init int parse_nopv(char *arg) +{ + nopv = true; + return 0; +} +early_param("nopv", parse_nopv); + static inline const struct hypervisor_x86 * __init detect_hypervisor_vendor(void) { @@ -65,6 +65,9 @@ detect_hypervisor_vendor(void) uint32_t pri, max_pri = 0; for (p = hypervisors; p < hypervisors + ARRAY_SIZE(hypervisors); p++) { + if (unlikely(nopv) && !(*p)->ignore_nopv) + continue; + pri = (*p)->detect(); if (pri > max_pri) { max_pri = pri; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index bf3034994754..a46dee8e78db 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2104,8 +2104,7 @@ static int rdt_init_fs_context(struct fs_context *fc) ctx->kfc.magic = RDTGROUP_SUPER_MAGIC; fc->fs_private = &ctx->kfc; fc->ops = &rdt_fs_context_ops; - if (fc->user_ns) - put_user_ns(fc->user_ns); + put_user_ns(fc->user_ns); fc->user_ns = get_user_ns(&init_user_ns); fc->global = true; return 0; diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index e69408bf664b..7da2bcd2b8eb 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -86,9 +86,9 @@ static bool _e820__mapped_any(struct e820_table *table, continue; if (entry->addr >= end || entry->addr + entry->size <= start) continue; - return 1; + return true; } - return 0; + return false; } bool e820__mapped_raw_any(u64 start, u64 end, enum e820_type type) diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c index 4b73f5937f41..024c3053dbba 100644 --- a/arch/x86/kernel/ftrace.c +++ b/arch/x86/kernel/ftrace.c @@ -373,7 +373,7 @@ static int add_brk_on_nop(struct dyn_ftrace *rec) return add_break(rec->ip, old); } -static int add_breakpoints(struct dyn_ftrace *rec, int enable) +static int add_breakpoints(struct dyn_ftrace *rec, bool enable) { unsigned long ftrace_addr; int ret; @@ -481,7 +481,7 @@ static int add_update_nop(struct dyn_ftrace *rec) return add_update_code(ip, new); } -static int add_update(struct dyn_ftrace *rec, int enable) +static int add_update(struct dyn_ftrace *rec, bool enable) { unsigned long ftrace_addr; int ret; @@ -527,7 +527,7 @@ static int finish_update_nop(struct dyn_ftrace *rec) return ftrace_write(ip, new, 1); } -static int finish_update(struct dyn_ftrace *rec, int enable) +static int finish_update(struct dyn_ftrace *rec, bool enable) { unsigned long ftrace_addr; int ret; diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index bcd206c8ac90..a6342c899be5 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -29,9 +29,7 @@ #ifdef CONFIG_PARAVIRT_XXL #include <asm/asm-offsets.h> #include <asm/paravirt.h> -#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg #else -#define GET_CR2_INTO(reg) movq %cr2, reg #define INTERRUPT_RETURN iretq #endif @@ -253,10 +251,10 @@ END(secondary_startup_64) * start_secondary() via .Ljump_to_C_code. */ ENTRY(start_cpu0) - movq initial_stack(%rip), %rsp UNWIND_HINT_EMPTY + movq initial_stack(%rip), %rsp jmp .Ljump_to_C_code -ENDPROC(start_cpu0) +END(start_cpu0) #endif /* Both SMP bootup and ACPI suspend change these variables */ @@ -323,7 +321,7 @@ early_idt_handler_common: cmpq $14,%rsi /* Page fault? */ jnz 10f - GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ + GET_CR2_INTO(%rdi) /* can clobber %rax if pv */ call early_make_pgtable andl %eax,%eax jz 20f /* All good */ diff --git a/arch/x86/kernel/itmt.c b/arch/x86/kernel/itmt.c index 838cf8a32c49..1cb3ca9bba49 100644 --- a/arch/x86/kernel/itmt.c +++ b/arch/x86/kernel/itmt.c @@ -65,8 +65,6 @@ static int sched_itmt_update_handler(struct ctl_table *table, int write, return ret; } -static unsigned int zero; -static unsigned int one = 1; static struct ctl_table itmt_kern_table[] = { { .procname = "sched_itmt_enabled", @@ -74,8 +72,8 @@ static struct ctl_table itmt_kern_table[] = { .maxlen = sizeof(unsigned int), .mode = 0644, .proc_handler = sched_itmt_update_handler, - .extra1 = &zero, - .extra2 = &one, + .extra1 = SYSCTL_ZERO, + .extra2 = SYSCTL_ONE, }, {} }; diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c index 6857b4577f17..3ad34f01de2a 100644 --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -217,4 +217,5 @@ const struct hypervisor_x86 x86_hyper_jailhouse __refconst = { .detect = jailhouse_detect, .init.init_platform = jailhouse_init_platform, .init.x2apic_available = jailhouse_x2apic_available, + .ignore_nopv = true, }; diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 82caf01b63dd..b7f34fe2171e 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -242,23 +242,23 @@ EXPORT_SYMBOL_GPL(kvm_read_and_reset_pf_reason); NOKPROBE_SYMBOL(kvm_read_and_reset_pf_reason); dotraplinkage void -do_async_page_fault(struct pt_regs *regs, unsigned long error_code) +do_async_page_fault(struct pt_regs *regs, unsigned long error_code, unsigned long address) { enum ctx_state prev_state; switch (kvm_read_and_reset_pf_reason()) { default: - do_page_fault(regs, error_code); + do_page_fault(regs, error_code, address); break; case KVM_PV_REASON_PAGE_NOT_PRESENT: /* page is swapped out by the host. */ prev_state = exception_enter(); - kvm_async_pf_task_wait((u32)read_cr2(), !user_mode(regs)); + kvm_async_pf_task_wait((u32)address, !user_mode(regs)); exception_exit(prev_state); break; case KVM_PV_REASON_PAGE_READY: rcu_irq_enter(); - kvm_async_pf_task_wake((u32)read_cr2()); + kvm_async_pf_task_wake((u32)address); rcu_irq_exit(); break; } @@ -838,6 +838,7 @@ asm( "cmpb $0, " __stringify(KVM_STEAL_TIME_preempted) "+steal_time(%rax);" "setne %al;" "ret;" +".size __raw_callee_save___kvm_vcpu_is_preempted, .-__raw_callee_save___kvm_vcpu_is_preempted;" ".popsection"); #endif diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index 1bfe5c6e6cfe..afac7ccce72f 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -546,17 +546,15 @@ void __init default_get_smp_config(unsigned int early) * local APIC has default address */ mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; - return; + goto out; } pr_info("Default MP configuration #%d\n", mpf->feature1); construct_default_ISA_mptable(mpf->feature1); } else if (mpf->physptr) { - if (check_physptr(mpf, early)) { - early_memunmap(mpf, sizeof(*mpf)); - return; - } + if (check_physptr(mpf, early)) + goto out; } else BUG(); @@ -565,7 +563,7 @@ void __init default_get_smp_config(unsigned int early) /* * Only use the first configuration found. */ - +out: early_memunmap(mpf, sizeof(*mpf)); } diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 98039d7fb998..0aa6256eedd8 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -370,7 +370,7 @@ struct paravirt_patch_template pv_ops = { .mmu.exit_mmap = paravirt_nop, #ifdef CONFIG_PARAVIRT_XXL - .mmu.read_cr2 = native_read_cr2, + .mmu.read_cr2 = __PV_IS_CALLEE_SAVE(native_read_cr2), .mmu.write_cr2 = native_write_cr2, .mmu.read_cr3 = __native_read_cr3, .mmu.write_cr3 = native_write_cr3, diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 250e4c4ac6d9..af64519b2695 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -143,17 +143,7 @@ void __show_regs(struct pt_regs *regs, enum show_regs_mode mode) void release_thread(struct task_struct *dead_task) { - if (dead_task->mm) { -#ifdef CONFIG_MODIFY_LDT_SYSCALL - if (dead_task->mm->context.ldt) { - pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n", - dead_task->comm, - dead_task->mm->context.ldt->entries, - dead_task->mm->context.ldt->nr_entries); - BUG(); - } -#endif - } + WARN_ON(dead_task->mm); } enum which_selector { diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c index 71691a8310e7..0fdbe89d0754 100644 --- a/arch/x86/kernel/ptrace.c +++ b/arch/x86/kernel/ptrace.c @@ -369,12 +369,22 @@ static int putreg(struct task_struct *child, case offsetof(struct user_regs_struct,fs_base): if (value >= TASK_SIZE_MAX) return -EIO; - x86_fsbase_write_task(child, value); + /* + * When changing the FS base, use do_arch_prctl_64() + * to set the index to zero and to set the base + * as requested. + */ + if (child->thread.fsbase != value) + return do_arch_prctl_64(child, ARCH_SET_FS, value); return 0; case offsetof(struct user_regs_struct,gs_base): + /* + * Exactly the same here as the %fs handling above. + */ if (value >= TASK_SIZE_MAX) return -EIO; - x86_gsbase_write_task(child, value); + if (child->thread.gsbase != value) + return do_arch_prctl_64(child, ARCH_SET_GS, value); return 0; #endif } diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 259d1d2be076..fdbd47ceb84d 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1368,8 +1368,6 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) pr_info("CPU0: "); print_cpu_info(&cpu_data(0)); - native_pv_lock_init(); - uv_system_init(); set_mtrr_aps_delayed_init(); @@ -1399,6 +1397,7 @@ void __init native_smp_prepare_boot_cpu(void) /* already set me in cpu_online_mask in boot_cpu_init() */ cpumask_set_cpu(me, cpu_callout_mask); cpu_set_state_online(me); + native_pv_lock_init(); } void __init calculate_max_logical_packages(void) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 87095a477154..4bb0f8447112 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -313,13 +313,10 @@ __visible void __noreturn handle_stack_overflow(const char *message, #ifdef CONFIG_X86_64 /* Runs on IST stack */ -dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) +dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code, unsigned long cr2) { static const char str[] = "double fault"; struct task_struct *tsk = current; -#ifdef CONFIG_VMAP_STACK - unsigned long cr2; -#endif #ifdef CONFIG_X86_ESPFIX64 extern unsigned char native_irq_return_iret[]; @@ -415,7 +412,6 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) * stack even if the actual trigger for the double fault was * something else. */ - cr2 = read_cr2(); if ((unsigned long)task_stack_page(tsk) - 1 - cr2 < PAGE_SIZE) handle_stack_overflow("kernel stack overflow (double-fault)", regs, cr2); #endif diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 50a2b492fdd6..1bef687faf22 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -29,8 +29,8 @@ void x86_init_noop(void) { } void __init x86_init_uint_noop(unsigned int unused) { } static int __init iommu_init_noop(void) { return 0; } static void iommu_shutdown_noop(void) { } -static bool __init bool_x86_init_noop(void) { return false; } -static void x86_op_int_noop(int cpu) { } +bool __init bool_x86_init_noop(void) { return false; } +void x86_op_int_noop(int cpu) { } /* * The platform setup functions are preset with the default functions diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index ead681210306..22c2720cd948 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -368,9 +368,13 @@ static inline void do_cpuid_7_mask(struct kvm_cpuid_entry2 *entry, int index) F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | F(MD_CLEAR); + /* cpuid 7.1.eax */ + const u32 kvm_cpuid_7_1_eax_x86_features = + F(AVX512_BF16); + switch (index) { case 0: - entry->eax = 0; + entry->eax = min(entry->eax, 1u); entry->ebx &= kvm_cpuid_7_0_ebx_x86_features; cpuid_mask(&entry->ebx, CPUID_7_0_EBX); /* TSC_ADJUST is emulated */ @@ -394,6 +398,12 @@ static inline void do_cpuid_7_mask(struct kvm_cpuid_entry2 *entry, int index) */ entry->edx |= F(ARCH_CAPABILITIES); break; + case 1: + entry->eax &= kvm_cpuid_7_1_eax_x86_features; + entry->ebx = 0; + entry->ecx = 0; + entry->edx = 0; + break; default: WARN_ON_ONCE(1); entry->eax = 0; diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 8e409ad448f9..718f7d9afedc 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -312,29 +312,42 @@ static void invalidate_registers(struct x86_emulate_ctxt *ctxt) static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); -#define FOP_FUNC(name) \ +#define __FOP_FUNC(name) \ ".align " __stringify(FASTOP_SIZE) " \n\t" \ ".type " name ", @function \n\t" \ name ":\n\t" -#define FOP_RET "ret \n\t" +#define FOP_FUNC(name) \ + __FOP_FUNC(#name) + +#define __FOP_RET(name) \ + "ret \n\t" \ + ".size " name ", .-" name "\n\t" + +#define FOP_RET(name) \ + __FOP_RET(#name) #define FOP_START(op) \ extern void em_##op(struct fastop *fake); \ asm(".pushsection .text, \"ax\" \n\t" \ ".global em_" #op " \n\t" \ - FOP_FUNC("em_" #op) + ".align " __stringify(FASTOP_SIZE) " \n\t" \ + "em_" #op ":\n\t" #define FOP_END \ ".popsection") +#define __FOPNOP(name) \ + __FOP_FUNC(name) \ + __FOP_RET(name) + #define FOPNOP() \ - FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \ - FOP_RET + __FOPNOP(__stringify(__UNIQUE_ID(nop))) #define FOP1E(op, dst) \ - FOP_FUNC(#op "_" #dst) \ - "10: " #op " %" #dst " \n\t" FOP_RET + __FOP_FUNC(#op "_" #dst) \ + "10: " #op " %" #dst " \n\t" \ + __FOP_RET(#op "_" #dst) #define FOP1EEX(op, dst) \ FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) @@ -366,8 +379,9 @@ static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); FOP_END #define FOP2E(op, dst, src) \ - FOP_FUNC(#op "_" #dst "_" #src) \ - #op " %" #src ", %" #dst " \n\t" FOP_RET + __FOP_FUNC(#op "_" #dst "_" #src) \ + #op " %" #src ", %" #dst " \n\t" \ + __FOP_RET(#op "_" #dst "_" #src) #define FASTOP2(op) \ FOP_START(op) \ @@ -405,8 +419,9 @@ static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); FOP_END #define FOP3E(op, dst, src, src2) \ - FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \ - #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET + __FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \ + #op " %" #src2 ", %" #src ", %" #dst " \n\t"\ + __FOP_RET(#op "_" #dst "_" #src "_" #src2) /* 3-operand, word-only, src2=cl */ #define FASTOP3WCL(op) \ @@ -423,7 +438,7 @@ static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); ".type " #op ", @function \n\t" \ #op ": \n\t" \ #op " %al \n\t" \ - FOP_RET + __FOP_RET(#op) asm(".pushsection .fixup, \"ax\"\n" ".global kvm_fastop_exception \n" @@ -449,7 +464,10 @@ FOP_SETCC(setle) FOP_SETCC(setnle) FOP_END; -FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET +FOP_START(salc) +FOP_FUNC(salc) +"pushf; sbb %al, %al; popf \n\t" +FOP_RET(salc) FOP_END; /* diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c index a39e38f13029..c10a8b10b203 100644 --- a/arch/x86/kvm/hyperv.c +++ b/arch/x86/kvm/hyperv.c @@ -1594,7 +1594,7 @@ int kvm_hv_hypercall(struct kvm_vcpu *vcpu) { u64 param, ingpa, outgpa, ret = HV_STATUS_SUCCESS; uint16_t code, rep_idx, rep_cnt; - bool fast, longmode, rep; + bool fast, rep; /* * hypercall generates UD from non zero cpl and real mode @@ -1605,9 +1605,14 @@ int kvm_hv_hypercall(struct kvm_vcpu *vcpu) return 1; } - longmode = is_64_bit_mode(vcpu); - - if (!longmode) { +#ifdef CONFIG_X86_64 + if (is_64_bit_mode(vcpu)) { + param = kvm_rcx_read(vcpu); + ingpa = kvm_rdx_read(vcpu); + outgpa = kvm_r8_read(vcpu); + } else +#endif + { param = ((u64)kvm_rdx_read(vcpu) << 32) | (kvm_rax_read(vcpu) & 0xffffffff); ingpa = ((u64)kvm_rbx_read(vcpu) << 32) | @@ -1615,13 +1620,6 @@ int kvm_hv_hypercall(struct kvm_vcpu *vcpu) outgpa = ((u64)kvm_rdi_read(vcpu) << 32) | (kvm_rsi_read(vcpu) & 0xffffffff); } -#ifdef CONFIG_X86_64 - else { - param = kvm_rcx_read(vcpu); - ingpa = kvm_rdx_read(vcpu); - outgpa = kvm_r8_read(vcpu); - } -#endif code = param & 0xffff; fast = !!(param & HV_HYPERCALL_FAST_BIT); diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c index 1add1bc881e2..d859ae8890d0 100644 --- a/arch/x86/kvm/ioapic.c +++ b/arch/x86/kvm/ioapic.c @@ -45,11 +45,6 @@ #include "lapic.h" #include "irq.h" -#if 0 -#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) -#else -#define ioapic_debug(fmt, arg...) -#endif static int ioapic_service(struct kvm_ioapic *vioapic, int irq, bool line_status); @@ -294,7 +289,6 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) default: index = (ioapic->ioregsel - 0x10) >> 1; - ioapic_debug("change redir index %x val %x\n", index, val); if (index >= IOAPIC_NUM_PINS) return; e = &ioapic->redirtbl[index]; @@ -343,12 +337,6 @@ static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status) entry->fields.remote_irr)) return -1; - ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " - "vector=%x trig_mode=%x\n", - entry->fields.dest_id, entry->fields.dest_mode, - entry->fields.delivery_mode, entry->fields.vector, - entry->fields.trig_mode); - irqe.dest_id = entry->fields.dest_id; irqe.vector = entry->fields.vector; irqe.dest_mode = entry->fields.dest_mode; @@ -515,7 +503,6 @@ static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, if (!ioapic_in_range(ioapic, addr)) return -EOPNOTSUPP; - ioapic_debug("addr %lx\n", (unsigned long)addr); ASSERT(!(addr & 0xf)); /* check alignment */ addr &= 0xff; @@ -558,8 +545,6 @@ static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, if (!ioapic_in_range(ioapic, addr)) return -EOPNOTSUPP; - ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", - (void*)addr, len, val); ASSERT(!(addr & 0xf)); /* check alignment */ switch (len) { diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index a232e76d8f23..0aa158657f20 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -52,9 +52,6 @@ #define PRIu64 "u" #define PRIo64 "o" -/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ -#define apic_debug(fmt, arg...) do {} while (0) - /* 14 is the version for Xeon and Pentium 8.4.8*/ #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) #define LAPIC_MMIO_LENGTH (1 << 12) @@ -121,6 +118,17 @@ static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) return apic->vcpu->vcpu_id; } +bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu) +{ + return pi_inject_timer && kvm_vcpu_apicv_active(vcpu); +} +EXPORT_SYMBOL_GPL(kvm_can_post_timer_interrupt); + +static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu) +{ + return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE; +} + static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map, u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) { switch (map->mode) { @@ -627,7 +635,7 @@ static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) { u8 val; if (pv_eoi_get_user(vcpu, &val) < 0) - apic_debug("Can't read EOI MSR value: 0x%llx\n", + printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n", (unsigned long long)vcpu->arch.pv_eoi.msr_val); return val & 0x1; } @@ -635,7 +643,7 @@ static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) { if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { - apic_debug("Can't set EOI MSR value: 0x%llx\n", + printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n", (unsigned long long)vcpu->arch.pv_eoi.msr_val); return; } @@ -645,7 +653,7 @@ static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) { if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { - apic_debug("Can't clear EOI MSR value: 0x%llx\n", + printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n", (unsigned long long)vcpu->arch.pv_eoi.msr_val); return; } @@ -679,9 +687,6 @@ static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) else ppr = isrv & 0xf0; - apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", - apic, ppr, isr, isrv); - *new_ppr = ppr; if (old_ppr != ppr) kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); @@ -758,8 +763,6 @@ static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) return ((logical_id >> 4) == (mda >> 4)) && (logical_id & mda & 0xf) != 0; default: - apic_debug("Bad DFR vcpu %d: %08x\n", - apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR)); return false; } } @@ -798,10 +801,6 @@ bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, struct kvm_lapic *target = vcpu->arch.apic; u32 mda = kvm_apic_mda(vcpu, dest, source, target); - apic_debug("target %p, source %p, dest 0x%x, " - "dest_mode 0x%x, short_hand 0x%x\n", - target, source, dest, dest_mode, short_hand); - ASSERT(target); switch (short_hand) { case APIC_DEST_NOSHORT: @@ -816,8 +815,6 @@ bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, case APIC_DEST_ALLBUT: return target != source; default: - apic_debug("kvm: apic: Bad dest shorthand value %x\n", - short_hand); return false; } } @@ -1095,15 +1092,10 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, smp_wmb(); kvm_make_request(KVM_REQ_EVENT, vcpu); kvm_vcpu_kick(vcpu); - } else { - apic_debug("Ignoring de-assert INIT to vcpu %d\n", - vcpu->vcpu_id); } break; case APIC_DM_STARTUP: - apic_debug("SIPI to vcpu %d vector 0x%02x\n", - vcpu->vcpu_id, vector); result = 1; apic->sipi_vector = vector; /* make sure sipi_vector is visible for the receiver */ @@ -1221,14 +1213,6 @@ static void apic_send_ipi(struct kvm_lapic *apic) trace_kvm_apic_ipi(icr_low, irq.dest_id); - apic_debug("icr_high 0x%x, icr_low 0x%x, " - "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " - "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, " - "msi_redir_hint 0x%x\n", - icr_high, icr_low, irq.shorthand, irq.dest_id, - irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, - irq.vector, irq.msi_redir_hint); - kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); } @@ -1282,7 +1266,6 @@ static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) switch (offset) { case APIC_ARBPRI: - apic_debug("Access APIC ARBPRI register which is for P6\n"); break; case APIC_TMCCT: /* Timer CCR */ @@ -1349,11 +1332,8 @@ int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, if (!apic_x2apic_mode(apic)) valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI); - if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset))) { - apic_debug("KVM_APIC_READ: read reserved register %x\n", - offset); + if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset))) return 1; - } result = __apic_read(apic, offset & ~0xf); @@ -1411,9 +1391,6 @@ static void update_divide_count(struct kvm_lapic *apic) tmp1 = tdcr & 0xf; tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; apic->divide_count = 0x1 << (tmp2 & 0x7); - - apic_debug("timer divide count is 0x%x\n", - apic->divide_count); } static void limit_periodic_timer_frequency(struct kvm_lapic *apic) @@ -1455,29 +1432,6 @@ static void apic_update_lvtt(struct kvm_lapic *apic) } } -static void apic_timer_expired(struct kvm_lapic *apic) -{ - struct kvm_vcpu *vcpu = apic->vcpu; - struct swait_queue_head *q = &vcpu->wq; - struct kvm_timer *ktimer = &apic->lapic_timer; - - if (atomic_read(&apic->lapic_timer.pending)) - return; - - atomic_inc(&apic->lapic_timer.pending); - kvm_set_pending_timer(vcpu); - - /* - * For x86, the atomic_inc() is serialized, thus - * using swait_active() is safe. - */ - if (swait_active(q)) - swake_up_one(q); - - if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) - ktimer->expired_tscdeadline = ktimer->tscdeadline; -} - /* * On APICv, this test will cause a busy wait * during a higher-priority task. @@ -1551,7 +1505,7 @@ static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu, apic->lapic_timer.timer_advance_ns = timer_advance_ns; } -void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) +static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) { struct kvm_lapic *apic = vcpu->arch.apic; u64 guest_tsc, tsc_deadline; @@ -1559,9 +1513,6 @@ void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) if (apic->lapic_timer.expired_tscdeadline == 0) return; - if (!lapic_timer_int_injected(vcpu)) - return; - tsc_deadline = apic->lapic_timer.expired_tscdeadline; apic->lapic_timer.expired_tscdeadline = 0; guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); @@ -1573,8 +1524,57 @@ void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) if (unlikely(!apic->lapic_timer.timer_advance_adjust_done)) adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta); } + +void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) +{ + if (lapic_timer_int_injected(vcpu)) + __kvm_wait_lapic_expire(vcpu); +} EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire); +static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic) +{ + struct kvm_timer *ktimer = &apic->lapic_timer; + + kvm_apic_local_deliver(apic, APIC_LVTT); + if (apic_lvtt_tscdeadline(apic)) + ktimer->tscdeadline = 0; + if (apic_lvtt_oneshot(apic)) { + ktimer->tscdeadline = 0; + ktimer->target_expiration = 0; + } +} + +static void apic_timer_expired(struct kvm_lapic *apic) +{ + struct kvm_vcpu *vcpu = apic->vcpu; + struct swait_queue_head *q = &vcpu->wq; + struct kvm_timer *ktimer = &apic->lapic_timer; + + if (atomic_read(&apic->lapic_timer.pending)) + return; + + if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) + ktimer->expired_tscdeadline = ktimer->tscdeadline; + + if (kvm_use_posted_timer_interrupt(apic->vcpu)) { + if (apic->lapic_timer.timer_advance_ns) + __kvm_wait_lapic_expire(vcpu); + kvm_apic_inject_pending_timer_irqs(apic); + return; + } + + atomic_inc(&apic->lapic_timer.pending); + kvm_set_pending_timer(vcpu); + + /* + * For x86, the atomic_inc() is serialized, thus + * using swait_active() is safe. + */ + if (swait_active(q)) + swake_up_one(q); +} + static void start_sw_tscdeadline(struct kvm_lapic *apic) { struct kvm_timer *ktimer = &apic->lapic_timer; @@ -1601,7 +1601,7 @@ static void start_sw_tscdeadline(struct kvm_lapic *apic) likely(ns > apic->lapic_timer.timer_advance_ns)) { expire = ktime_add_ns(now, ns); expire = ktime_sub_ns(expire, ktimer->timer_advance_ns); - hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_PINNED); + hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS); } else apic_timer_expired(apic); @@ -1648,16 +1648,6 @@ static bool set_target_expiration(struct kvm_lapic *apic) limit_periodic_timer_frequency(apic); - apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" - PRIx64 ", " - "timer initial count 0x%x, period %lldns, " - "expire @ 0x%016" PRIx64 ".\n", __func__, - APIC_BUS_CYCLE_NS, ktime_to_ns(now), - kvm_lapic_get_reg(apic, APIC_TMICT), - apic->lapic_timer.period, - ktime_to_ns(ktime_add_ns(now, - apic->lapic_timer.period))); - apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + nsec_to_cycles(apic->vcpu, apic->lapic_timer.period); apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period); @@ -1703,7 +1693,7 @@ static void start_sw_period(struct kvm_lapic *apic) hrtimer_start(&apic->lapic_timer.timer, apic->lapic_timer.target_expiration, - HRTIMER_MODE_ABS_PINNED); + HRTIMER_MODE_ABS); } bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu) @@ -1860,8 +1850,6 @@ static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; if (lvt0_in_nmi_mode) { - apic_debug("Receive NMI setting on APIC_LVT0 " - "for cpu %d\n", apic->vcpu->vcpu_id); atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); } else atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); @@ -1975,8 +1963,6 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) case APIC_TDCR: { uint32_t old_divisor = apic->divide_count; - if (val & 4) - apic_debug("KVM_WRITE:TDCR %x\n", val); kvm_lapic_set_reg(apic, APIC_TDCR, val); update_divide_count(apic); if (apic->divide_count != old_divisor && @@ -1988,10 +1974,8 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) break; } case APIC_ESR: - if (apic_x2apic_mode(apic) && val != 0) { - apic_debug("KVM_WRITE:ESR not zero %x\n", val); + if (apic_x2apic_mode(apic) && val != 0) ret = 1; - } break; case APIC_SELF_IPI: @@ -2004,8 +1988,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) ret = 1; break; } - if (ret) - apic_debug("Local APIC Write to read-only register %x\n", reg); + return ret; } EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); @@ -2033,20 +2016,12 @@ static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, * 32/64/128 bits registers must be accessed thru 32 bits. * Refer SDM 8.4.1 */ - if (len != 4 || (offset & 0xf)) { - /* Don't shout loud, $infamous_os would cause only noise. */ - apic_debug("apic write: bad size=%d %lx\n", len, (long)address); + if (len != 4 || (offset & 0xf)) return 0; - } val = *(u32*)data; - /* too common printing */ - if (offset != APIC_EOI) - apic_debug("%s: offset 0x%x with length 0x%x, and value is " - "0x%x\n", __func__, offset, len, val); - - kvm_lapic_reg_write(apic, offset, val); + kvm_lapic_reg_write(apic, offset & 0xff0, val); return 0; } @@ -2178,11 +2153,6 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) if ((value & MSR_IA32_APICBASE_ENABLE) && apic->base_address != APIC_DEFAULT_PHYS_BASE) pr_warn_once("APIC base relocation is unsupported by KVM"); - - /* with FSB delivery interrupt, we can restart APIC functionality */ - apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " - "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); - } void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) @@ -2193,8 +2163,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) if (!apic) return; - apic_debug("%s\n", __func__); - /* Stop the timer in case it's a reset to an active apic */ hrtimer_cancel(&apic->lapic_timer.timer); @@ -2247,11 +2215,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) vcpu->arch.apic_arb_prio = 0; vcpu->arch.apic_attention = 0; - - apic_debug("%s: vcpu=%p, id=0x%x, base_msr=" - "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, - vcpu, kvm_lapic_get_reg(apic, APIC_ID), - vcpu->arch.apic_base, apic->base_address); } /* @@ -2323,7 +2286,6 @@ int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns) struct kvm_lapic *apic; ASSERT(vcpu != NULL); - apic_debug("apic_init %d\n", vcpu->vcpu_id); apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT); if (!apic) @@ -2340,7 +2302,7 @@ int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns) apic->vcpu = vcpu; hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, - HRTIMER_MODE_ABS_PINNED); + HRTIMER_MODE_ABS); apic->lapic_timer.timer.function = apic_timer_fn; if (timer_advance_ns == -1) { apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_ADJUST_INIT; @@ -2397,13 +2359,7 @@ void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) struct kvm_lapic *apic = vcpu->arch.apic; if (atomic_read(&apic->lapic_timer.pending) > 0) { - kvm_apic_local_deliver(apic, APIC_LVTT); - if (apic_lvtt_tscdeadline(apic)) - apic->lapic_timer.tscdeadline = 0; - if (apic_lvtt_oneshot(apic)) { - apic->lapic_timer.tscdeadline = 0; - apic->lapic_timer.target_expiration = 0; - } + kvm_apic_inject_pending_timer_irqs(apic); atomic_set(&apic->lapic_timer.pending, 0); } } @@ -2525,12 +2481,13 @@ void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) { struct hrtimer *timer; - if (!lapic_in_kernel(vcpu)) + if (!lapic_in_kernel(vcpu) || + kvm_can_post_timer_interrupt(vcpu)) return; timer = &vcpu->arch.apic->lapic_timer.timer; if (hrtimer_cancel(timer)) - hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); + hrtimer_start_expires(timer, HRTIMER_MODE_ABS); } /* @@ -2678,11 +2635,8 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) return 1; - if (reg == APIC_DFR || reg == APIC_ICR2) { - apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", - reg); + if (reg == APIC_DFR || reg == APIC_ICR2) return 1; - } if (kvm_lapic_reg_read(apic, reg, 4, &low)) return 1; @@ -2780,8 +2734,6 @@ void kvm_apic_accept_events(struct kvm_vcpu *vcpu) /* evaluate pending_events before reading the vector */ smp_rmb(); sipi_vector = apic->sipi_vector; - apic_debug("vcpu %d received sipi with vector # %x\n", - vcpu->vcpu_id, sipi_vector); kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; } diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index 36747174e4a8..50053d2b8b7b 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -236,6 +236,7 @@ void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu); void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu); bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu); void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu); +bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu); static inline enum lapic_mode kvm_apic_mode(u64 apic_base) { diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 9a5814d8d194..24843cf49579 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -3466,7 +3466,7 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, /* * Currently, fast page fault only works for direct mapping * since the gfn is not stable for indirect shadow page. See - * Documentation/virtual/kvm/locking.txt to get more detail. + * Documentation/virt/kvm/locking.txt to get more detail. */ fault_handled = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte, @@ -4597,11 +4597,11 @@ static void update_permission_bitmask(struct kvm_vcpu *vcpu, */ /* Faults from writes to non-writable pages */ - u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0; + u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0; /* Faults from user mode accesses to supervisor pages */ - u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0; + u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0; /* Faults from fetches of non-executable pages*/ - u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0; + u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0; /* Faults from kernel mode fetches of user pages */ u8 smepf = 0; /* Faults from kernel mode accesses of user pages */ diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index aa5a2597305a..46875bbd0419 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -19,8 +19,8 @@ #include "lapic.h" #include "pmu.h" -/* This keeps the total size of the filter under 4k. */ -#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 63 +/* This is enough to filter the vast majority of currently defined events. */ +#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 /* NOTE: * - Each perf counter is defined as "struct kvm_pmc"; @@ -131,8 +131,8 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, intr ? kvm_perf_overflow_intr : kvm_perf_overflow, pmc); if (IS_ERR(event)) { - printk_once("kvm_pmu: event creation failed %ld\n", - PTR_ERR(event)); + pr_debug_ratelimited("kvm_pmu: event creation failed %ld for pmc->idx = %d\n", + PTR_ERR(event), pmc->idx); return; } @@ -206,12 +206,24 @@ void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx) { unsigned en_field = ctrl & 0x3; bool pmi = ctrl & 0x8; + struct kvm_pmu_event_filter *filter; + struct kvm *kvm = pmc->vcpu->kvm; pmc_stop_counter(pmc); if (!en_field || !pmc_is_enabled(pmc)) return; + filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu); + if (filter) { + if (filter->action == KVM_PMU_EVENT_DENY && + test_bit(idx, (ulong *)&filter->fixed_counter_bitmap)) + return; + if (filter->action == KVM_PMU_EVENT_ALLOW && + !test_bit(idx, (ulong *)&filter->fixed_counter_bitmap)) + return; + } + pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE, kvm_x86_ops->pmu_ops->find_fixed_event(idx), !(en_field & 0x2), /* exclude user */ @@ -385,6 +397,9 @@ int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp) tmp.action != KVM_PMU_EVENT_DENY) return -EINVAL; + if (tmp.flags != 0) + return -EINVAL; + if (tmp.nevents > KVM_PMU_EVENT_FILTER_MAX_EVENTS) return -E2BIG; @@ -406,8 +421,8 @@ int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp) mutex_unlock(&kvm->lock); synchronize_srcu_expedited(&kvm->srcu); - r = 0; + r = 0; cleanup: kfree(filter); - return r; + return r; } diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 583b9fa656f3..7eafc6907861 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -2143,12 +2143,20 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) goto out; } + svm->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, + GFP_KERNEL_ACCOUNT); + if (!svm->vcpu.arch.user_fpu) { + printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n"); + err = -ENOMEM; + goto free_partial_svm; + } + svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, GFP_KERNEL_ACCOUNT); if (!svm->vcpu.arch.guest_fpu) { printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); err = -ENOMEM; - goto free_partial_svm; + goto free_user_fpu; } err = kvm_vcpu_init(&svm->vcpu, kvm, id); @@ -2211,6 +2219,8 @@ uninit: kvm_vcpu_uninit(&svm->vcpu); free_svm: kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu); +free_user_fpu: + kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu); free_partial_svm: kmem_cache_free(kvm_vcpu_cache, svm); out: @@ -2241,6 +2251,7 @@ static void svm_free_vcpu(struct kvm_vcpu *vcpu) __free_page(virt_to_page(svm->nested.hsave)); __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); kvm_vcpu_uninit(vcpu); + kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu); kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu); kmem_cache_free(kvm_vcpu_cache, svm); } @@ -7128,13 +7139,41 @@ static int nested_enable_evmcs(struct kvm_vcpu *vcpu, static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) { - bool is_user, smap; - - is_user = svm_get_cpl(vcpu) == 3; - smap = !kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); + unsigned long cr4 = kvm_read_cr4(vcpu); + bool smep = cr4 & X86_CR4_SMEP; + bool smap = cr4 & X86_CR4_SMAP; + bool is_user = svm_get_cpl(vcpu) == 3; /* - * Detect and workaround Errata 1096 Fam_17h_00_0Fh + * Detect and workaround Errata 1096 Fam_17h_00_0Fh. + * + * Errata: + * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is + * possible that CPU microcode implementing DecodeAssist will fail + * to read bytes of instruction which caused #NPF. In this case, + * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly + * return 0 instead of the correct guest instruction bytes. + * + * This happens because CPU microcode reading instruction bytes + * uses a special opcode which attempts to read data using CPL=0 + * priviledges. The microcode reads CS:RIP and if it hits a SMAP + * fault, it gives up and returns no instruction bytes. + * + * Detection: + * We reach here in case CPU supports DecodeAssist, raised #NPF and + * returned 0 in GuestIntrBytes field of the VMCB. + * First, errata can only be triggered in case vCPU CR4.SMAP=1. + * Second, if vCPU CR4.SMEP=1, errata could only be triggered + * in case vCPU CPL==3 (Because otherwise guest would have triggered + * a SMEP fault instead of #NPF). + * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL. + * As most guests enable SMAP if they have also enabled SMEP, use above + * logic in order to attempt minimize false-positive of detecting errata + * while still preserving all cases semantic correctness. + * + * Workaround: + * To determine what instruction the guest was executing, the hypervisor + * will have to decode the instruction at the instruction pointer. * * In non SEV guest, hypervisor will be able to read the guest * memory to decode the instruction pointer when insn_len is zero @@ -7145,11 +7184,11 @@ static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) * instruction pointer so we will not able to workaround it. Lets * print the error and request to kill the guest. */ - if (is_user && smap) { + if (smap && (!smep || is_user)) { if (!sev_guest(vcpu->kvm)) return true; - pr_err_ratelimited("KVM: Guest triggered AMD Erratum 1096\n"); + pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n"); kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); } diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index bb509c254939..ced9fba32598 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -194,6 +194,7 @@ static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) { secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS); vmcs_write64(VMCS_LINK_POINTER, -1ull); + vmx->nested.need_vmcs12_to_shadow_sync = false; } static inline void nested_release_evmcs(struct kvm_vcpu *vcpu) @@ -219,6 +220,8 @@ static void free_nested(struct kvm_vcpu *vcpu) if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) return; + kvm_clear_request(KVM_REQ_GET_VMCS12_PAGES, vcpu); + vmx->nested.vmxon = false; vmx->nested.smm.vmxon = false; free_vpid(vmx->nested.vpid02); @@ -231,7 +234,9 @@ static void free_nested(struct kvm_vcpu *vcpu) vmx->vmcs01.shadow_vmcs = NULL; } kfree(vmx->nested.cached_vmcs12); + vmx->nested.cached_vmcs12 = NULL; kfree(vmx->nested.cached_shadow_vmcs12); + vmx->nested.cached_shadow_vmcs12 = NULL; /* Unpin physical memory we referred to in the vmcs02 */ if (vmx->nested.apic_access_page) { kvm_release_page_dirty(vmx->nested.apic_access_page); @@ -1341,6 +1346,9 @@ static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) unsigned long val; int i; + if (WARN_ON(!shadow_vmcs)) + return; + preempt_disable(); vmcs_load(shadow_vmcs); @@ -1373,6 +1381,9 @@ static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) unsigned long val; int i, q; + if (WARN_ON(!shadow_vmcs)) + return; + vmcs_load(shadow_vmcs); for (q = 0; q < ARRAY_SIZE(fields); q++) { @@ -4194,7 +4205,10 @@ int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, * mode, e.g. a 32-bit address size can yield a 64-bit virtual * address when using FS/GS with a non-zero base. */ - *ret = s.base + off; + if (seg_reg == VCPU_SREG_FS || seg_reg == VCPU_SREG_GS) + *ret = s.base + off; + else + *ret = off; /* Long mode: #GP(0)/#SS(0) if the memory address is in a * non-canonical form. This is the only check on the memory @@ -4433,7 +4447,6 @@ static inline void nested_release_vmcs12(struct kvm_vcpu *vcpu) /* copy to memory all shadowed fields in case they were modified */ copy_shadow_to_vmcs12(vmx); - vmx->nested.need_vmcs12_to_shadow_sync = false; vmx_disable_shadow_vmcs(vmx); } vmx->nested.posted_intr_nv = -1; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 68d231d49c7a..4dea0e0e7e39 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -337,17 +337,22 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) static void intel_pmu_reset(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc = NULL; int i; for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) { - struct kvm_pmc *pmc = &pmu->gp_counters[i]; + pmc = &pmu->gp_counters[i]; pmc_stop_counter(pmc); pmc->counter = pmc->eventsel = 0; } - for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) - pmc_stop_counter(&pmu->fixed_counters[i]); + for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) { + pmc = &pmu->fixed_counters[i]; + + pmc_stop_counter(pmc); + pmc->counter = 0; + } pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status = pmu->global_ovf_ctrl = 0; diff --git a/arch/x86/kvm/vmx/vmenter.S b/arch/x86/kvm/vmx/vmenter.S index d4cb1945b2e3..4010d519eb8c 100644 --- a/arch/x86/kvm/vmx/vmenter.S +++ b/arch/x86/kvm/vmx/vmenter.S @@ -54,9 +54,9 @@ ENTRY(vmx_vmenter) ret 3: cmpb $0, kvm_rebooting - jne 4f - call kvm_spurious_fault -4: ret + je 4f + ret +4: ud2 .pushsection .fixup, "ax" 5: jmp 3b diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 69536553446d..074385c86c09 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -5829,6 +5829,7 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu) } if (unlikely(vmx->fail)) { + dump_vmcs(); vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; vcpu->run->fail_entry.hardware_entry_failure_reason = vmcs_read32(VM_INSTRUCTION_ERROR); @@ -6597,6 +6598,7 @@ static void vmx_free_vcpu(struct kvm_vcpu *vcpu) free_loaded_vmcs(vmx->loaded_vmcs); kfree(vmx->guest_msrs); kvm_vcpu_uninit(vcpu); + kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); kmem_cache_free(kvm_vcpu_cache, vmx); } @@ -6612,12 +6614,20 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) if (!vmx) return ERR_PTR(-ENOMEM); + vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, + GFP_KERNEL_ACCOUNT); + if (!vmx->vcpu.arch.user_fpu) { + printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n"); + err = -ENOMEM; + goto free_partial_vcpu; + } + vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, GFP_KERNEL_ACCOUNT); if (!vmx->vcpu.arch.guest_fpu) { printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); err = -ENOMEM; - goto free_partial_vcpu; + goto free_user_fpu; } vmx->vpid = allocate_vpid(); @@ -6720,6 +6730,8 @@ uninit_vcpu: free_vcpu: free_vpid(vmx->vpid); kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); +free_user_fpu: + kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); free_partial_vcpu: kmem_cache_free(kvm_vcpu_cache, vmx); return ERR_PTR(err); @@ -7064,7 +7076,8 @@ static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; - if (kvm_mwait_in_guest(vcpu->kvm)) + if (kvm_mwait_in_guest(vcpu->kvm) || + kvm_can_post_timer_interrupt(vcpu)) return -EOPNOTSUPP; vmx = to_vmx(vcpu); @@ -7453,7 +7466,7 @@ static int enable_smi_window(struct kvm_vcpu *vcpu) static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) { - return 0; + return false; } static __init int hardware_setup(void) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 4a0b74ecd1de..c6d951cbd76c 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -51,6 +51,7 @@ #include <linux/kvm_irqfd.h> #include <linux/irqbypass.h> #include <linux/sched/stat.h> +#include <linux/sched/isolation.h> #include <linux/mem_encrypt.h> #include <trace/events/kvm.h> @@ -153,6 +154,9 @@ EXPORT_SYMBOL_GPL(enable_vmware_backdoor); static bool __read_mostly force_emulation_prefix = false; module_param(force_emulation_prefix, bool, S_IRUGO); +int __read_mostly pi_inject_timer = -1; +module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); + #define KVM_NR_SHARED_MSRS 16 struct kvm_shared_msrs_global { @@ -1456,12 +1460,8 @@ static void update_pvclock_gtod(struct timekeeper *tk) void kvm_set_pending_timer(struct kvm_vcpu *vcpu) { - /* - * Note: KVM_REQ_PENDING_TIMER is implicitly checked in - * vcpu_enter_guest. This function is only called from - * the physical CPU that is running vcpu. - */ kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); + kvm_vcpu_kick(vcpu); } static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) @@ -1540,9 +1540,6 @@ static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, *pshift = shift; *pmultiplier = div_frac(scaled64, tps32); - - pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", - __func__, base_hz, scaled_hz, shift, *pmultiplier); } #ifdef CONFIG_X86_64 @@ -1785,12 +1782,10 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { if (!kvm_check_tsc_unstable()) { offset = kvm->arch.cur_tsc_offset; - pr_debug("kvm: matched tsc offset for %llu\n", data); } else { u64 delta = nsec_to_cycles(vcpu, elapsed); data += delta; offset = kvm_compute_tsc_offset(vcpu, data); - pr_debug("kvm: adjusted tsc offset by %llu\n", delta); } matched = true; already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); @@ -1809,8 +1804,6 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) kvm->arch.cur_tsc_write = data; kvm->arch.cur_tsc_offset = offset; matched = false; - pr_debug("kvm: new tsc generation %llu, clock %llu\n", - kvm->arch.cur_tsc_generation, data); } /* @@ -3313,6 +3306,10 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_x86_ops->vcpu_load(vcpu, cpu); + fpregs_assert_state_consistent(); + if (test_thread_flag(TIF_NEED_FPU_LOAD)) + switch_fpu_return(); + /* Apply any externally detected TSC adjustments (due to suspend) */ if (unlikely(vcpu->arch.tsc_offset_adjustment)) { adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); @@ -6911,7 +6908,6 @@ static void kvm_timer_init(void) cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, CPUFREQ_TRANSITION_NOTIFIER); } - pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", kvmclock_cpu_online, kvmclock_cpu_down_prep); @@ -7070,6 +7066,8 @@ int kvm_arch_init(void *opaque) host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); kvm_lapic_init(); + if (pi_inject_timer == -1) + pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); #ifdef CONFIG_X86_64 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); @@ -7208,7 +7206,7 @@ static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) rcu_read_unlock(); - if (target) + if (target && READ_ONCE(target->ready)) kvm_vcpu_yield_to(target); } @@ -7248,6 +7246,7 @@ int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) break; case KVM_HC_KICK_CPU: kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); + kvm_sched_yield(vcpu->kvm, a1); ret = 0; break; #ifdef CONFIG_X86_64 @@ -7996,9 +7995,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) trace_kvm_entry(vcpu->vcpu_id); guest_enter_irqoff(); - fpregs_assert_state_consistent(); - if (test_thread_flag(TIF_NEED_FPU_LOAD)) - switch_fpu_return(); + /* The preempt notifier should have taken care of the FPU already. */ + WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD)); if (unlikely(vcpu->arch.switch_db_regs)) { set_debugreg(0, 7); @@ -8276,7 +8274,7 @@ static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) { fpregs_lock(); - copy_fpregs_to_fpstate(¤t->thread.fpu); + copy_fpregs_to_fpstate(vcpu->arch.user_fpu); /* PKRU is separately restored in kvm_x86_ops->run. */ __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, ~XFEATURE_MASK_PKRU); @@ -8293,7 +8291,7 @@ static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) fpregs_lock(); copy_fpregs_to_fpstate(vcpu->arch.guest_fpu); - copy_kernel_to_fpregs(¤t->thread.fpu.state); + copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); fpregs_mark_activate(); fpregs_unlock(); diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index e08a12892e8b..6594020c0691 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -301,6 +301,8 @@ extern unsigned int min_timer_period_us; extern bool enable_vmware_backdoor; +extern int pi_inject_timer; + extern struct static_key kvm_no_apic_vcpu; static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) diff --git a/arch/x86/lib/copy_user_64.S b/arch/x86/lib/copy_user_64.S index 378a1f70ae7d..4fe1601dbc5d 100644 --- a/arch/x86/lib/copy_user_64.S +++ b/arch/x86/lib/copy_user_64.S @@ -239,7 +239,7 @@ copy_user_handle_tail: ret _ASM_EXTABLE_UA(1b, 2b) -ENDPROC(copy_user_handle_tail) +END(copy_user_handle_tail) /* * copy_user_nocache - Uncached memory copy with exception handling diff --git a/arch/x86/lib/getuser.S b/arch/x86/lib/getuser.S index 74fdff968ea3..304f958c27b2 100644 --- a/arch/x86/lib/getuser.S +++ b/arch/x86/lib/getuser.S @@ -115,29 +115,29 @@ ENDPROC(__get_user_8) EXPORT_SYMBOL(__get_user_8) +bad_get_user_clac: + ASM_CLAC bad_get_user: xor %edx,%edx mov $(-EFAULT),%_ASM_AX - ASM_CLAC ret -END(bad_get_user) #ifdef CONFIG_X86_32 +bad_get_user_8_clac: + ASM_CLAC bad_get_user_8: xor %edx,%edx xor %ecx,%ecx mov $(-EFAULT),%_ASM_AX - ASM_CLAC ret -END(bad_get_user_8) #endif - _ASM_EXTABLE_UA(1b, bad_get_user) - _ASM_EXTABLE_UA(2b, bad_get_user) - _ASM_EXTABLE_UA(3b, bad_get_user) + _ASM_EXTABLE_UA(1b, bad_get_user_clac) + _ASM_EXTABLE_UA(2b, bad_get_user_clac) + _ASM_EXTABLE_UA(3b, bad_get_user_clac) #ifdef CONFIG_X86_64 - _ASM_EXTABLE_UA(4b, bad_get_user) + _ASM_EXTABLE_UA(4b, bad_get_user_clac) #else - _ASM_EXTABLE_UA(4b, bad_get_user_8) - _ASM_EXTABLE_UA(5b, bad_get_user_8) + _ASM_EXTABLE_UA(4b, bad_get_user_8_clac) + _ASM_EXTABLE_UA(5b, bad_get_user_8_clac) #endif diff --git a/arch/x86/lib/putuser.S b/arch/x86/lib/putuser.S index d2e5c9c39601..14bf78341d3c 100644 --- a/arch/x86/lib/putuser.S +++ b/arch/x86/lib/putuser.S @@ -32,8 +32,6 @@ */ #define ENTER mov PER_CPU_VAR(current_task), %_ASM_BX -#define EXIT ASM_CLAC ; \ - ret .text ENTRY(__put_user_1) @@ -43,7 +41,8 @@ ENTRY(__put_user_1) ASM_STAC 1: movb %al,(%_ASM_CX) xor %eax,%eax - EXIT + ASM_CLAC + ret ENDPROC(__put_user_1) EXPORT_SYMBOL(__put_user_1) @@ -56,7 +55,8 @@ ENTRY(__put_user_2) ASM_STAC 2: movw %ax,(%_ASM_CX) xor %eax,%eax - EXIT + ASM_CLAC + ret ENDPROC(__put_user_2) EXPORT_SYMBOL(__put_user_2) @@ -69,7 +69,8 @@ ENTRY(__put_user_4) ASM_STAC 3: movl %eax,(%_ASM_CX) xor %eax,%eax - EXIT + ASM_CLAC + ret ENDPROC(__put_user_4) EXPORT_SYMBOL(__put_user_4) @@ -85,19 +86,21 @@ ENTRY(__put_user_8) 5: movl %edx,4(%_ASM_CX) #endif xor %eax,%eax - EXIT + ASM_CLAC + RET ENDPROC(__put_user_8) EXPORT_SYMBOL(__put_user_8) +bad_put_user_clac: + ASM_CLAC bad_put_user: movl $-EFAULT,%eax - EXIT -END(bad_put_user) + RET - _ASM_EXTABLE_UA(1b, bad_put_user) - _ASM_EXTABLE_UA(2b, bad_put_user) - _ASM_EXTABLE_UA(3b, bad_put_user) - _ASM_EXTABLE_UA(4b, bad_put_user) + _ASM_EXTABLE_UA(1b, bad_put_user_clac) + _ASM_EXTABLE_UA(2b, bad_put_user_clac) + _ASM_EXTABLE_UA(3b, bad_put_user_clac) + _ASM_EXTABLE_UA(4b, bad_put_user_clac) #ifdef CONFIG_X86_32 - _ASM_EXTABLE_UA(5b, bad_put_user) + _ASM_EXTABLE_UA(5b, bad_put_user_clac) #endif diff --git a/arch/x86/lib/usercopy_64.c b/arch/x86/lib/usercopy_64.c index e0e006f1624e..fff28c6f73a2 100644 --- a/arch/x86/lib/usercopy_64.c +++ b/arch/x86/lib/usercopy_64.c @@ -60,7 +60,7 @@ EXPORT_SYMBOL(clear_user); * but reuse __memcpy_mcsafe in case a new read error is encountered. * clac() is handled in _copy_to_iter_mcsafe(). */ -__visible unsigned long +__visible notrace unsigned long mcsafe_handle_tail(char *to, char *from, unsigned len) { for (; len; --len, to++, from++) { diff --git a/arch/x86/math-emu/fpu_emu.h b/arch/x86/math-emu/fpu_emu.h index a5a41ec58072..0c122226ca56 100644 --- a/arch/x86/math-emu/fpu_emu.h +++ b/arch/x86/math-emu/fpu_emu.h @@ -177,7 +177,7 @@ static inline void reg_copy(FPU_REG const *x, FPU_REG *y) #define setexponentpos(x,y) { (*(short *)&((x)->exp)) = \ ((y) + EXTENDED_Ebias) & 0x7fff; } #define exponent16(x) (*(short *)&((x)->exp)) -#define setexponent16(x,y) { (*(short *)&((x)->exp)) = (y); } +#define setexponent16(x,y) { (*(short *)&((x)->exp)) = (u16)(y); } #define addexponent(x,y) { (*(short *)&((x)->exp)) += (y); } #define stdexp(x) { (*(short *)&((x)->exp)) += EXTENDED_Ebias; } diff --git a/arch/x86/math-emu/reg_constant.c b/arch/x86/math-emu/reg_constant.c index 8dc9095bab22..742619e94bdf 100644 --- a/arch/x86/math-emu/reg_constant.c +++ b/arch/x86/math-emu/reg_constant.c @@ -18,7 +18,7 @@ #include "control_w.h" #define MAKE_REG(s, e, l, h) { l, h, \ - ((EXTENDED_Ebias+(e)) | ((SIGN_##s != 0)*0x8000)) } + (u16)((EXTENDED_Ebias+(e)) | ((SIGN_##s != 0)*0x8000)) } FPU_REG const CONST_1 = MAKE_REG(POS, 0, 0x00000000, 0x80000000); #if 0 diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index 794f364cb882..6c46095cd0d9 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -46,23 +46,6 @@ kmmio_fault(struct pt_regs *regs, unsigned long addr) return 0; } -static nokprobe_inline int kprobes_fault(struct pt_regs *regs) -{ - if (!kprobes_built_in()) - return 0; - if (user_mode(regs)) - return 0; - /* - * To be potentially processing a kprobe fault and to be allowed to call - * kprobe_running(), we have to be non-preemptible. - */ - if (preemptible()) - return 0; - if (!kprobe_running()) - return 0; - return kprobe_fault_handler(regs, X86_TRAP_PF); -} - /* * Prefetch quirks: * @@ -1282,7 +1265,7 @@ do_kern_addr_fault(struct pt_regs *regs, unsigned long hw_error_code, return; /* kprobes don't want to hook the spurious faults: */ - if (kprobes_fault(regs)) + if (kprobe_page_fault(regs, X86_TRAP_PF)) return; /* @@ -1313,7 +1296,7 @@ void do_user_addr_fault(struct pt_regs *regs, mm = tsk->mm; /* kprobes don't want to hook the spurious faults: */ - if (unlikely(kprobes_fault(regs))) + if (unlikely(kprobe_page_fault(regs, X86_TRAP_PF))) return; /* @@ -1507,9 +1490,8 @@ good_area: NOKPROBE_SYMBOL(do_user_addr_fault); /* - * This routine handles page faults. It determines the address, - * and the problem, and then passes it off to one of the appropriate - * routines. + * Explicitly marked noinline such that the function tracer sees this as the + * page_fault entry point. */ static noinline void __do_page_fault(struct pt_regs *regs, unsigned long hw_error_code, @@ -1528,33 +1510,26 @@ __do_page_fault(struct pt_regs *regs, unsigned long hw_error_code, } NOKPROBE_SYMBOL(__do_page_fault); -static nokprobe_inline void -trace_page_fault_entries(unsigned long address, struct pt_regs *regs, - unsigned long error_code) +static __always_inline void +trace_page_fault_entries(struct pt_regs *regs, unsigned long error_code, + unsigned long address) { + if (!trace_pagefault_enabled()) + return; + if (user_mode(regs)) trace_page_fault_user(address, regs, error_code); else trace_page_fault_kernel(address, regs, error_code); } -/* - * We must have this function blacklisted from kprobes, tagged with notrace - * and call read_cr2() before calling anything else. To avoid calling any - * kind of tracing machinery before we've observed the CR2 value. - * - * exception_{enter,exit}() contains all sorts of tracepoints. - */ -dotraplinkage void notrace -do_page_fault(struct pt_regs *regs, unsigned long error_code) +dotraplinkage void +do_page_fault(struct pt_regs *regs, unsigned long error_code, unsigned long address) { - unsigned long address = read_cr2(); /* Get the faulting address */ enum ctx_state prev_state; prev_state = exception_enter(); - if (trace_pagefault_enabled()) - trace_page_fault_entries(address, regs, error_code); - + trace_page_fault_entries(regs, error_code, address); __do_page_fault(regs, error_code, address); exception_exit(prev_state); } diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c index f265a4316179..4068abb9427f 100644 --- a/arch/x86/mm/init_32.c +++ b/arch/x86/mm/init_32.c @@ -860,7 +860,6 @@ int arch_add_memory(int nid, u64 start, u64 size, return __add_pages(nid, start_pfn, nr_pages, restrictions); } -#ifdef CONFIG_MEMORY_HOTREMOVE void arch_remove_memory(int nid, u64 start, u64 size, struct vmem_altmap *altmap) { @@ -872,7 +871,6 @@ void arch_remove_memory(int nid, u64 start, u64 size, __remove_pages(zone, start_pfn, nr_pages, altmap); } #endif -#endif int kernel_set_to_readonly __read_mostly; diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index 0f01c7b1d217..a6b5c653727b 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -1198,7 +1198,6 @@ void __ref vmemmap_free(unsigned long start, unsigned long end, remove_pagetable(start, end, false, altmap); } -#ifdef CONFIG_MEMORY_HOTREMOVE static void __meminit kernel_physical_mapping_remove(unsigned long start, unsigned long end) { @@ -1213,17 +1212,12 @@ void __ref arch_remove_memory(int nid, u64 start, u64 size, { unsigned long start_pfn = start >> PAGE_SHIFT; unsigned long nr_pages = size >> PAGE_SHIFT; - struct page *page = pfn_to_page(start_pfn); - struct zone *zone; + struct page *page = pfn_to_page(start_pfn) + vmem_altmap_offset(altmap); + struct zone *zone = page_zone(page); - /* With altmap the first mapped page is offset from @start */ - if (altmap) - page += vmem_altmap_offset(altmap); - zone = page_zone(page); __remove_pages(zone, start_pfn, nr_pages, altmap); kernel_physical_mapping_remove(start, start + size); } -#endif #endif /* CONFIG_MEMORY_HOTPLUG */ static struct kcore_list kcore_vsyscall; @@ -1524,7 +1518,9 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, { int err; - if (boot_cpu_has(X86_FEATURE_PSE)) + if (end - start < PAGES_PER_SECTION * sizeof(struct page)) + err = vmemmap_populate_basepages(start, end, node); + else if (boot_cpu_has(X86_FEATURE_PSE)) err = vmemmap_populate_hugepages(start, end, node, altmap); else if (altmap) { pr_err_once("%s: no cpu support for altmap allocations\n", diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index e500f1df1140..63e99f15d7cf 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -459,6 +459,11 @@ void iounmap(volatile void __iomem *addr) } EXPORT_SYMBOL(iounmap); +int __init arch_ioremap_p4d_supported(void) +{ + return 0; +} + int __init arch_ioremap_pud_supported(void) { #ifdef CONFIG_X86_64 diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index e0df96fdfe46..fece30ca8b0c 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -15,6 +15,10 @@ #include <linux/dma-direct.h> #include <linux/swiotlb.h> #include <linux/mem_encrypt.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/bitops.h> +#include <linux/dma-mapping.h> #include <asm/tlbflush.h> #include <asm/fixmap.h> @@ -41,7 +45,7 @@ EXPORT_SYMBOL_GPL(sev_enable_key); bool sev_enabled __section(.data); /* Buffer used for early in-place encryption by BSP, no locking needed */ -static char sme_early_buffer[PAGE_SIZE] __aligned(PAGE_SIZE); +static char sme_early_buffer[PAGE_SIZE] __initdata __aligned(PAGE_SIZE); /* * This routine does not change the underlying encryption setting of the @@ -348,6 +352,32 @@ bool sev_active(void) } EXPORT_SYMBOL(sev_active); +/* Override for DMA direct allocation check - ARCH_HAS_FORCE_DMA_UNENCRYPTED */ +bool force_dma_unencrypted(struct device *dev) +{ + /* + * For SEV, all DMA must be to unencrypted addresses. + */ + if (sev_active()) + return true; + + /* + * For SME, all DMA must be to unencrypted addresses if the + * device does not support DMA to addresses that include the + * encryption mask. + */ + if (sme_active()) { + u64 dma_enc_mask = DMA_BIT_MASK(__ffs64(sme_me_mask)); + u64 dma_dev_mask = min_not_zero(dev->coherent_dma_mask, + dev->bus_dma_mask); + + if (dma_dev_mask <= dma_enc_mask) + return true; + } + + return false; +} + /* Architecture __weak replacement functions */ void __init mem_encrypt_free_decrypted_mem(void) { diff --git a/arch/x86/platform/olpc/olpc.c b/arch/x86/platform/olpc/olpc.c index c85d485eb4f8..ee2beda590d0 100644 --- a/arch/x86/platform/olpc/olpc.c +++ b/arch/x86/platform/olpc/olpc.c @@ -26,9 +26,6 @@ struct olpc_platform_t olpc_platform_info; EXPORT_SYMBOL_GPL(olpc_platform_info); -/* EC event mask to be applied during suspend (defining wakeup sources). */ -static u16 ec_wakeup_mask; - /* what the timeout *should* be (in ms) */ #define EC_BASE_TIMEOUT 20 @@ -182,83 +179,6 @@ err: return ret; } -void olpc_ec_wakeup_set(u16 value) -{ - ec_wakeup_mask |= value; -} -EXPORT_SYMBOL_GPL(olpc_ec_wakeup_set); - -void olpc_ec_wakeup_clear(u16 value) -{ - ec_wakeup_mask &= ~value; -} -EXPORT_SYMBOL_GPL(olpc_ec_wakeup_clear); - -/* - * Returns true if the compile and runtime configurations allow for EC events - * to wake the system. - */ -bool olpc_ec_wakeup_available(void) -{ - if (!machine_is_olpc()) - return false; - - /* - * XO-1 EC wakeups are available when olpc-xo1-sci driver is - * compiled in - */ -#ifdef CONFIG_OLPC_XO1_SCI - if (olpc_platform_info.boardrev < olpc_board_pre(0xd0)) /* XO-1 */ - return true; -#endif - - /* - * XO-1.5 EC wakeups are available when olpc-xo15-sci driver is - * compiled in - */ -#ifdef CONFIG_OLPC_XO15_SCI - if (olpc_platform_info.boardrev >= olpc_board_pre(0xd0)) /* XO-1.5 */ - return true; -#endif - - return false; -} -EXPORT_SYMBOL_GPL(olpc_ec_wakeup_available); - -int olpc_ec_mask_write(u16 bits) -{ - if (olpc_platform_info.flags & OLPC_F_EC_WIDE_SCI) { - __be16 ec_word = cpu_to_be16(bits); - return olpc_ec_cmd(EC_WRITE_EXT_SCI_MASK, (void *) &ec_word, 2, - NULL, 0); - } else { - unsigned char ec_byte = bits & 0xff; - return olpc_ec_cmd(EC_WRITE_SCI_MASK, &ec_byte, 1, NULL, 0); - } -} -EXPORT_SYMBOL_GPL(olpc_ec_mask_write); - -int olpc_ec_sci_query(u16 *sci_value) -{ - int ret; - - if (olpc_platform_info.flags & OLPC_F_EC_WIDE_SCI) { - __be16 ec_word; - ret = olpc_ec_cmd(EC_EXT_SCI_QUERY, - NULL, 0, (void *) &ec_word, 2); - if (ret == 0) - *sci_value = be16_to_cpu(ec_word); - } else { - unsigned char ec_byte; - ret = olpc_ec_cmd(EC_SCI_QUERY, NULL, 0, &ec_byte, 1); - if (ret == 0) - *sci_value = ec_byte; - } - - return ret; -} -EXPORT_SYMBOL_GPL(olpc_ec_sci_query); - static bool __init check_ofw_architecture(struct device_node *root) { const char *olpc_arch; @@ -292,6 +212,10 @@ static bool __init platform_detect(void) if (success) { olpc_platform_info.boardrev = get_board_revision(root); olpc_platform_info.flags |= OLPC_F_PRESENT; + + pr_info("OLPC board revision %s%X\n", + ((olpc_platform_info.boardrev & 0xf) < 8) ? "pre" : "", + olpc_platform_info.boardrev >> 4); } of_node_put(root); @@ -311,27 +235,8 @@ static int __init add_xo1_platform_devices(void) return PTR_ERR_OR_ZERO(pdev); } -static int olpc_xo1_ec_probe(struct platform_device *pdev) -{ - /* get the EC revision */ - olpc_ec_cmd(EC_FIRMWARE_REV, NULL, 0, - (unsigned char *) &olpc_platform_info.ecver, 1); - - /* EC version 0x5f adds support for wide SCI mask */ - if (olpc_platform_info.ecver >= 0x5f) - olpc_platform_info.flags |= OLPC_F_EC_WIDE_SCI; - - pr_info("OLPC board revision %s%X (EC=%x)\n", - ((olpc_platform_info.boardrev & 0xf) < 8) ? "pre" : "", - olpc_platform_info.boardrev >> 4, - olpc_platform_info.ecver); - - return 0; -} static int olpc_xo1_ec_suspend(struct platform_device *pdev) { - olpc_ec_mask_write(ec_wakeup_mask); - /* * Squelch SCIs while suspended. This is a fix for * <http://dev.laptop.org/ticket/1835>. @@ -355,15 +260,27 @@ static int olpc_xo1_ec_resume(struct platform_device *pdev) } static struct olpc_ec_driver ec_xo1_driver = { - .probe = olpc_xo1_ec_probe, .suspend = olpc_xo1_ec_suspend, .resume = olpc_xo1_ec_resume, .ec_cmd = olpc_xo1_ec_cmd, +#ifdef CONFIG_OLPC_XO1_SCI + /* + * XO-1 EC wakeups are available when olpc-xo1-sci driver is + * compiled in + */ + .wakeup_available = true, +#endif }; static struct olpc_ec_driver ec_xo1_5_driver = { - .probe = olpc_xo1_ec_probe, .ec_cmd = olpc_xo1_ec_cmd, +#ifdef CONFIG_OLPC_XO1_5_SCI + /* + * XO-1.5 EC wakeups are available when olpc-xo15-sci driver is + * compiled in + */ + .wakeup_available = true, +#endif }; static int __init olpc_init(void) diff --git a/arch/x86/platform/olpc/olpc_dt.c b/arch/x86/platform/olpc/olpc_dt.c index c78bfc16a3ca..26d1f6693789 100644 --- a/arch/x86/platform/olpc/olpc_dt.c +++ b/arch/x86/platform/olpc/olpc_dt.c @@ -216,7 +216,7 @@ static u32 __init olpc_dt_get_board_revision(void) return be32_to_cpu(rev); } -int olpc_dt_compatible_match(phandle node, const char *compat) +static int __init olpc_dt_compatible_match(phandle node, const char *compat) { char buf[64], *p; int plen, len; diff --git a/arch/x86/xen/enlighten_hvm.c b/arch/x86/xen/enlighten_hvm.c index 0e75642d42a3..e138f7de52d2 100644 --- a/arch/x86/xen/enlighten_hvm.c +++ b/arch/x86/xen/enlighten_hvm.c @@ -210,18 +210,18 @@ static void __init xen_hvm_guest_init(void) #endif } -static bool xen_nopv; static __init int xen_parse_nopv(char *arg) { - xen_nopv = true; - return 0; + pr_notice("\"xen_nopv\" is deprecated, please use \"nopv\" instead\n"); + + if (xen_cpuid_base()) + nopv = true; + return 0; } early_param("xen_nopv", xen_parse_nopv); -bool xen_hvm_need_lapic(void) +bool __init xen_hvm_need_lapic(void) { - if (xen_nopv) - return false; if (xen_pv_domain()) return false; if (!xen_hvm_domain()) @@ -230,15 +230,6 @@ bool xen_hvm_need_lapic(void) return false; return true; } -EXPORT_SYMBOL_GPL(xen_hvm_need_lapic); - -static uint32_t __init xen_platform_hvm(void) -{ - if (xen_pv_domain() || xen_nopv) - return 0; - - return xen_cpuid_base(); -} static __init void xen_hvm_guest_late_init(void) { @@ -251,6 +242,9 @@ static __init void xen_hvm_guest_late_init(void) /* PVH detected. */ xen_pvh = true; + if (nopv) + panic("\"nopv\" and \"xen_nopv\" parameters are unsupported in PVH guest."); + /* Make sure we don't fall back to (default) ACPI_IRQ_MODEL_PIC. */ if (!nr_ioapics && acpi_irq_model == ACPI_IRQ_MODEL_PIC) acpi_irq_model = ACPI_IRQ_MODEL_PLATFORM; @@ -260,7 +254,38 @@ static __init void xen_hvm_guest_late_init(void) #endif } -const __initconst struct hypervisor_x86 x86_hyper_xen_hvm = { +static uint32_t __init xen_platform_hvm(void) +{ + uint32_t xen_domain = xen_cpuid_base(); + struct x86_hyper_init *h = &x86_hyper_xen_hvm.init; + + if (xen_pv_domain()) + return 0; + + if (xen_pvh_domain() && nopv) { + /* Guest booting via the Xen-PVH boot entry goes here */ + pr_info("\"nopv\" parameter is ignored in PVH guest\n"); + nopv = false; + } else if (nopv && xen_domain) { + /* + * Guest booting via normal boot entry (like via grub2) goes + * here. + * + * Use interface functions for bare hardware if nopv, + * xen_hvm_guest_late_init is an exception as we need to + * detect PVH and panic there. + */ + h->init_platform = x86_init_noop; + h->x2apic_available = bool_x86_init_noop; + h->init_mem_mapping = x86_init_noop; + h->init_after_bootmem = x86_init_noop; + h->guest_late_init = xen_hvm_guest_late_init; + x86_hyper_xen_hvm.runtime.pin_vcpu = x86_op_int_noop; + } + return xen_domain; +} + +struct hypervisor_x86 x86_hyper_xen_hvm __initdata = { .name = "Xen HVM", .detect = xen_platform_hvm, .type = X86_HYPER_XEN_HVM, @@ -269,4 +294,5 @@ const __initconst struct hypervisor_x86 x86_hyper_xen_hvm = { .init.init_mem_mapping = xen_hvm_init_mem_mapping, .init.guest_late_init = xen_hvm_guest_late_init, .runtime.pin_vcpu = xen_pin_vcpu, + .ignore_nopv = true, }; diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 4722ba2966ac..7ceb32821093 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -596,12 +596,12 @@ struct trap_array_entry { static struct trap_array_entry trap_array[] = { { debug, xen_xendebug, true }, - { int3, xen_xenint3, true }, { double_fault, xen_double_fault, true }, #ifdef CONFIG_X86_MCE { machine_check, xen_machine_check, true }, #endif { nmi, xen_xennmi, true }, + { int3, xen_int3, false }, { overflow, xen_overflow, false }, #ifdef CONFIG_IA32_EMULATION { entry_INT80_compat, xen_entry_INT80_compat, false }, @@ -998,7 +998,8 @@ void __init xen_setup_vcpu_info_placement(void) __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); - pv_ops.mmu.read_cr2 = xen_read_cr2_direct; + pv_ops.mmu.read_cr2 = + __PV_IS_CALLEE_SAVE(xen_read_cr2_direct); } } @@ -1463,4 +1464,5 @@ const __initconst struct hypervisor_x86 x86_hyper_xen_pv = { .detect = xen_platform_pv, .type = X86_HYPER_XEN_PV, .runtime.pin_vcpu = xen_pin_vcpu, + .ignore_nopv = true, }; diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c index f6e5eeecfc69..26e8b326966d 100644 --- a/arch/x86/xen/mmu_pv.c +++ b/arch/x86/xen/mmu_pv.c @@ -1307,16 +1307,6 @@ static void xen_write_cr2(unsigned long cr2) this_cpu_read(xen_vcpu)->arch.cr2 = cr2; } -static unsigned long xen_read_cr2(void) -{ - return this_cpu_read(xen_vcpu)->arch.cr2; -} - -unsigned long xen_read_cr2_direct(void) -{ - return this_cpu_read(xen_vcpu_info.arch.cr2); -} - static noinline void xen_flush_tlb(void) { struct mmuext_op *op; @@ -2397,7 +2387,7 @@ static void xen_leave_lazy_mmu(void) } static const struct pv_mmu_ops xen_mmu_ops __initconst = { - .read_cr2 = xen_read_cr2, + .read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2), .write_cr2 = xen_write_cr2, .read_cr3 = xen_read_cr3, diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c index 3776122c87cc..6deb49094c60 100644 --- a/arch/x86/xen/spinlock.c +++ b/arch/x86/xen/spinlock.c @@ -68,11 +68,8 @@ void xen_init_lock_cpu(int cpu) int irq; char *name; - if (!xen_pvspin) { - if (cpu == 0) - static_branch_disable(&virt_spin_lock_key); + if (!xen_pvspin) return; - } WARN(per_cpu(lock_kicker_irq, cpu) >= 0, "spinlock on CPU%d exists on IRQ%d!\n", cpu, per_cpu(lock_kicker_irq, cpu)); @@ -124,6 +121,7 @@ void __init xen_init_spinlocks(void) if (!xen_pvspin) { printk(KERN_DEBUG "xen: PV spinlocks disabled\n"); + static_branch_disable(&virt_spin_lock_key); return; } printk(KERN_DEBUG "xen: PV spinlocks enabled\n"); diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S index 8019edd0125c..be104eef80be 100644 --- a/arch/x86/xen/xen-asm.S +++ b/arch/x86/xen/xen-asm.S @@ -10,6 +10,7 @@ #include <asm/percpu.h> #include <asm/processor-flags.h> #include <asm/frame.h> +#include <asm/asm.h> #include <linux/linkage.h> @@ -135,3 +136,18 @@ ENTRY(check_events) FRAME_END ret ENDPROC(check_events) + +ENTRY(xen_read_cr2) + FRAME_BEGIN + _ASM_MOV PER_CPU_VAR(xen_vcpu), %_ASM_AX + _ASM_MOV XEN_vcpu_info_arch_cr2(%_ASM_AX), %_ASM_AX + FRAME_END + ret + ENDPROC(xen_read_cr2); + +ENTRY(xen_read_cr2_direct) + FRAME_BEGIN + _ASM_MOV PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_arch_cr2, %_ASM_AX + FRAME_END + ret + ENDPROC(xen_read_cr2_direct); diff --git a/arch/x86/xen/xen-asm_64.S b/arch/x86/xen/xen-asm_64.S index 1e9ef0ba30a5..ebf610b49c06 100644 --- a/arch/x86/xen/xen-asm_64.S +++ b/arch/x86/xen/xen-asm_64.S @@ -32,7 +32,6 @@ xen_pv_trap divide_error xen_pv_trap debug xen_pv_trap xendebug xen_pv_trap int3 -xen_pv_trap xenint3 xen_pv_trap xennmi xen_pv_trap overflow xen_pv_trap bounds diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h index 2f111f47ba98..45a441c33d6d 100644 --- a/arch/x86/xen/xen-ops.h +++ b/arch/x86/xen/xen-ops.h @@ -134,6 +134,9 @@ __visible void xen_irq_disable_direct(void); __visible unsigned long xen_save_fl_direct(void); __visible void xen_restore_fl_direct(unsigned long); +__visible unsigned long xen_read_cr2(void); +__visible unsigned long xen_read_cr2_direct(void); + /* These are not functions, and cannot be called normally */ __visible void xen_iret(void); __visible void xen_sysret32(void); diff --git a/arch/xtensa/boot/dts/virt.dts b/arch/xtensa/boot/dts/virt.dts new file mode 100644 index 000000000000..6aecbc0f3549 --- /dev/null +++ b/arch/xtensa/boot/dts/virt.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/ { + compatible = "cdns,xtensa-iss"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=ttyS0,115200n8 debug"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x80000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "cdns,xtensa-cpu"; + reg = <0>; + clocks = <&osc>; + }; + }; + + clocks { + osc: osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + + pic: pic { + compatible = "cdns,xtensa-pic"; + /* one cell: internal irq number, + * two cells: second cell == 0: internal irq number + * second cell == 1: external irq number + */ + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + pci { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <0x1>; + + bus-range = <0x0 0x3f>; + reg = <0xc0000000 0x04000000>; + + // BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2) + ranges = <0x01000000 0x0 0xc4000000 0xc4000000 0x0 0x04000000>, + <0x02000000 0x0 0xc8000000 0xc8000000 0x0 0x18000000>; + + // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(2) + interrupt-map = < + 0x0000 0x0 0x0 0x1 &pic 0x0 0x1 + 0x0800 0x0 0x0 0x1 &pic 0x1 0x1 + 0x1000 0x0 0x0 0x1 &pic 0x2 0x1 + 0x1800 0x0 0x0 0x1 &pic 0x3 0x1 + >; + + interrupt-map-mask = <0x1800 0x0 0x0 0x7>; + }; +}; diff --git a/arch/xtensa/configs/virt_defconfig b/arch/xtensa/configs/virt_defconfig new file mode 100644 index 000000000000..bfc45a138e72 --- /dev/null +++ b/arch/xtensa/configs/virt_defconfig @@ -0,0 +1,113 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_MEMCG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PERF_EVENTS=y +CONFIG_XTENSA_VARIANT_DC233C=y +CONFIG_XTENSA_UNALIGNED_USER=y +CONFIG_VECTORS_OFFSET=0x00002000 +CONFIG_XTENSA_KSEG_512M=y +CONFIG_HIGHMEM=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x80000000@0" +CONFIG_USE_OF=y +CONFIG_BUILTIN_DTB_SOURCE="virt" +# CONFIG_PARSE_BOOTPARAM is not set +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPACTION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +# CONFIG_WIRELESS is not set +CONFIG_PCI=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_VIRTIO_BLK=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_VIRTIO_NET=y +# CONFIG_ETHERNET is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_VIRTIO=y +# CONFIG_HWMON is not set +CONFIG_DRM=y +CONFIG_DRM_VGEM=y +CONFIG_DRM_VIRTIO_GPU=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_USB_SUPPORT is not set +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_INPUT=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT3_FS=y +CONFIG_FANOTIFY=y +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_FONTS=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_STACKTRACE=y +CONFIG_RCU_TRACE=y +# CONFIG_FTRACE is not set +# CONFIG_S32C1I_SELFTEST is not set diff --git a/arch/xtensa/include/asm/asmmacro.h b/arch/xtensa/include/asm/asmmacro.h index 8308a9c3abb2..71a7e846bc1f 100644 --- a/arch/xtensa/include/asm/asmmacro.h +++ b/arch/xtensa/include/asm/asmmacro.h @@ -191,4 +191,50 @@ #endif .endm +#define XTENSA_STACK_ALIGNMENT 16 + +#if defined(__XTENSA_WINDOWED_ABI__) +#define XTENSA_FRAME_SIZE_RESERVE 16 +#define XTENSA_SPILL_STACK_RESERVE 32 + +#define abi_entry(frame_size) \ + entry sp, (XTENSA_FRAME_SIZE_RESERVE + \ + (((frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \ + -XTENSA_STACK_ALIGNMENT)) +#define abi_entry_default abi_entry(0) + +#define abi_ret(frame_size) retw +#define abi_ret_default retw + +#elif defined(__XTENSA_CALL0_ABI__) + +#define XTENSA_SPILL_STACK_RESERVE 0 + +#define abi_entry(frame_size) __abi_entry (frame_size) + + .macro __abi_entry frame_size + .ifgt \frame_size + addi sp, sp, -(((\frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \ + -XTENSA_STACK_ALIGNMENT) + .endif + .endm + +#define abi_entry_default + +#define abi_ret(frame_size) __abi_ret (frame_size) + + .macro __abi_ret frame_size + .ifgt \frame_size + addi sp, sp, (((\frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \ + -XTENSA_STACK_ALIGNMENT) + .endif + ret + .endm + +#define abi_ret_default ret + +#else +#error Unsupported Xtensa ABI +#endif + #endif /* _XTENSA_ASMMACRO_H */ diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h index 323d05789159..3b054d2bede0 100644 --- a/arch/xtensa/include/asm/initialize_mmu.h +++ b/arch/xtensa/include/asm/initialize_mmu.h @@ -42,7 +42,7 @@ #if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* * We Have Atomic Operation Control (ATOMCTL) Register; Initialize it. - * For details see Documentation/xtensa/atomctl.txt + * For details see Documentation/xtensa/atomctl.rst */ #if XCHAL_DCACHE_IS_COHERENT movi a3, 0x25 /* For SMP/MX -- internal for writeback, diff --git a/arch/xtensa/include/asm/platform.h b/arch/xtensa/include/asm/platform.h index 560483356a06..913826dfa838 100644 --- a/arch/xtensa/include/asm/platform.h +++ b/arch/xtensa/include/asm/platform.h @@ -55,16 +55,6 @@ extern void platform_idle (void); extern void platform_heartbeat (void); /* - * platform_pcibios_init is called to allow the platform to setup the pci bus. - */ -extern void platform_pcibios_init (void); - -/* - * platform_pcibios_fixup allows to modify the PCI configuration. - */ -extern int platform_pcibios_fixup (void); - -/* * platform_calibrate_ccount calibrates cpu clock freq (CONFIG_XTENSA_CALIBRATE) */ extern void platform_calibrate_ccount (void); diff --git a/arch/xtensa/include/asm/types.h b/arch/xtensa/include/asm/types.h deleted file mode 100644 index 2b410b8c7f79..000000000000 --- a/arch/xtensa/include/asm/types.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * include/asm-xtensa/types.h - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001 - 2005 Tensilica Inc. - */ -#ifndef _XTENSA_TYPES_H -#define _XTENSA_TYPES_H - -#include <uapi/asm/types.h> - -#ifndef __ASSEMBLY__ -/* - * These aren't exported outside the kernel to avoid name space clashes - */ - -#define BITS_PER_LONG 32 - -#endif -#endif /* _XTENSA_TYPES_H */ diff --git a/arch/xtensa/include/uapi/asm/mman.h b/arch/xtensa/include/uapi/asm/mman.h index be726062412b..ebbb48842190 100644 --- a/arch/xtensa/include/uapi/asm/mman.h +++ b/arch/xtensa/include/uapi/asm/mman.h @@ -56,12 +56,8 @@ #define MAP_STACK 0x40000 /* give out an address that is best suited for process/thread stacks */ #define MAP_HUGETLB 0x80000 /* create a huge page mapping */ #define MAP_FIXED_NOREPLACE 0x100000 /* MAP_FIXED which doesn't unmap underlying mapping */ -#ifdef CONFIG_MMAP_ALLOW_UNINITIALIZED -# define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be +#define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be * uninitialized */ -#else -# define MAP_UNINITIALIZED 0x0 /* Don't support this flag */ -#endif /* * Flags for msync diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coprocessor.S index 92bf24a9da92..60c220020054 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -121,7 +121,9 @@ ENTRY(coprocessor_flush) - entry a1, 32 + /* reserve 4 bytes on stack to save a0 */ + abi_entry(4) + s32i a0, a1, 0 movi a0, .Lsave_cp_regs_jump_table addx8 a3, a3, a0 @@ -131,7 +133,8 @@ ENTRY(coprocessor_flush) beqz a3, 1f callx0 a3 1: l32i a0, a1, 0 - retw + + abi_ret(4) ENDPROC(coprocessor_flush) diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S index e54af8b7e0f8..183fa8e0bb5b 100644 --- a/arch/xtensa/kernel/entry.S +++ b/arch/xtensa/kernel/entry.S @@ -1842,7 +1842,8 @@ ENDPROC(fast_store_prohibited) ENTRY(system_call) - entry a1, 32 + /* reserve 4 bytes on stack for function parameter */ + abi_entry(4) /* regs->syscall = regs->areg[2] */ @@ -1892,7 +1893,7 @@ ENTRY(system_call) s32i a6, a2, PT_AREG2 bnez a3, 1f - retw + abi_ret(4) 1: l32i a4, a1, 4 @@ -1901,7 +1902,7 @@ ENTRY(system_call) mov a6, a2 call4 do_syscall_trace_leave s32i a3, a2, PT_SYSCALL - retw + abi_ret(4) ENDPROC(system_call) @@ -1952,7 +1953,7 @@ ENDPROC(system_call) ENTRY(_switch_to) - entry a1, 48 + abi_entry(XTENSA_SPILL_STACK_RESERVE) mov a11, a3 # and 'next' (a3) @@ -2013,7 +2014,7 @@ ENTRY(_switch_to) wsr a14, ps rsync - retw + abi_ret(XTENSA_SPILL_STACK_RESERVE) ENDPROC(_switch_to) diff --git a/arch/xtensa/kernel/mcount.S b/arch/xtensa/kernel/mcount.S index 0eeda2e4a25e..5e4619f52858 100644 --- a/arch/xtensa/kernel/mcount.S +++ b/arch/xtensa/kernel/mcount.S @@ -11,6 +11,7 @@ */ #include <linux/linkage.h> +#include <asm/asmmacro.h> #include <asm/ftrace.h> /* @@ -21,13 +22,13 @@ ENTRY(_mcount) - entry a1, 16 + abi_entry_default movi a4, ftrace_trace_function l32i a4, a4, 0 movi a3, ftrace_stub bne a3, a4, 1f - retw + abi_ret_default 1: xor a7, a2, a1 movi a3, 0x3fffffff @@ -40,11 +41,11 @@ ENTRY(_mcount) addi a6, a6, -MCOUNT_INSN_SIZE callx4 a4 - retw + abi_ret_default ENDPROC(_mcount) ENTRY(ftrace_stub) - entry a1, 16 - retw + abi_entry_default + abi_ret_default ENDPROC(ftrace_stub) diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c index 8b823f94e568..3f32e275997a 100644 --- a/arch/xtensa/kernel/pci.c +++ b/arch/xtensa/kernel/pci.c @@ -24,23 +24,6 @@ #include <asm/pci-bridge.h> #include <asm/platform.h> -/* PCI Controller */ - - -/* - * pcibios_alloc_controller - * pcibios_enable_device - * pcibios_fixups - * pcibios_align_resource - * pcibios_fixup_bus - * pci_bus_add_device - */ - -static struct pci_controller *pci_ctrl_head; -static struct pci_controller **pci_ctrl_tail = &pci_ctrl_head; - -static int pci_bus_count; - /* * We need to avoid collisions with `mirrored' VGA ports * and other strange ISA hardware, so we always want the @@ -75,81 +58,6 @@ pcibios_align_resource(void *data, const struct resource *res, return start; } -static void __init pci_controller_apertures(struct pci_controller *pci_ctrl, - struct list_head *resources) -{ - struct resource *res; - unsigned long io_offset; - int i; - - io_offset = (unsigned long)pci_ctrl->io_space.base; - res = &pci_ctrl->io_resource; - if (!res->flags) { - if (io_offset) - pr_err("I/O resource not set for host bridge %d\n", - pci_ctrl->index); - res->start = 0; - res->end = IO_SPACE_LIMIT; - res->flags = IORESOURCE_IO; - } - res->start += io_offset; - res->end += io_offset; - pci_add_resource_offset(resources, res, io_offset); - - for (i = 0; i < 3; i++) { - res = &pci_ctrl->mem_resources[i]; - if (!res->flags) { - if (i > 0) - continue; - pr_err("Memory resource not set for host bridge %d\n", - pci_ctrl->index); - res->start = 0; - res->end = ~0U; - res->flags = IORESOURCE_MEM; - } - pci_add_resource(resources, res); - } -} - -static int __init pcibios_init(void) -{ - struct pci_controller *pci_ctrl; - struct list_head resources; - struct pci_bus *bus; - int next_busno = 0, ret; - - pr_info("PCI: Probing PCI hardware\n"); - - /* Scan all of the recorded PCI controllers. */ - for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { - pci_ctrl->last_busno = 0xff; - INIT_LIST_HEAD(&resources); - pci_controller_apertures(pci_ctrl, &resources); - bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno, - pci_ctrl->ops, pci_ctrl, &resources); - if (!bus) - continue; - - pci_ctrl->bus = bus; - pci_ctrl->last_busno = bus->busn_res.end; - if (next_busno <= pci_ctrl->last_busno) - next_busno = pci_ctrl->last_busno+1; - } - pci_bus_count = next_busno; - ret = platform_pcibios_fixup(); - if (ret) - return ret; - - for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { - if (pci_ctrl->bus) - pci_bus_add_devices(pci_ctrl->bus); - } - - return 0; -} - -subsys_initcall(pcibios_init); - void pcibios_fixup_bus(struct pci_bus *bus) { if (bus->parent) { @@ -158,38 +66,6 @@ void pcibios_fixup_bus(struct pci_bus *bus) } } -void pcibios_set_master(struct pci_dev *dev) -{ - /* No special bus mastering setup handling */ -} - -int pcibios_enable_device(struct pci_dev *dev, int mask) -{ - u16 cmd, old_cmd; - int idx; - struct resource *r; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - old_cmd = cmd; - for (idx=0; idx<6; idx++) { - r = &dev->resource[idx]; - if (!r->start && r->end) { - pci_err(dev, "can't enable device: resource collisions\n"); - return -EINVAL; - } - if (r->flags & IORESOURCE_IO) - cmd |= PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - cmd |= PCI_COMMAND_MEMORY; - } - if (cmd != old_cmd) { - pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - - return 0; -} - /* * Platform support for /proc/bus/pci/X/Y mmap()s. * -- paulus. diff --git a/arch/xtensa/kernel/platform.c b/arch/xtensa/kernel/platform.c index 1cf008284dd2..a95ba05b0abe 100644 --- a/arch/xtensa/kernel/platform.c +++ b/arch/xtensa/kernel/platform.c @@ -34,8 +34,6 @@ _F(void, halt, (void), { while(1); }); _F(void, power_off, (void), { while(1); }); _F(void, idle, (void), { __asm__ __volatile__ ("waiti 0" ::: "memory"); }); _F(void, heartbeat, (void), { }); -_F(int, pcibios_fixup, (void), { return 0; }); -_F(void, pcibios_init, (void), { }); #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT _F(void, calibrate_ccount, (void), diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c index 176cb46bcf12..5cb8a62e091c 100644 --- a/arch/xtensa/kernel/setup.c +++ b/arch/xtensa/kernel/setup.c @@ -405,10 +405,6 @@ void __init setup_arch(char **cmdline_p) conswitchp = &dummy_con; # endif #endif - -#ifdef CONFIG_PCI - platform_pcibios_init(); -#endif } static DEFINE_PER_CPU(struct cpu, cpu_data); diff --git a/arch/xtensa/lib/checksum.S b/arch/xtensa/lib/checksum.S index c6e73b12e519..4cb9ca58d9ad 100644 --- a/arch/xtensa/lib/checksum.S +++ b/arch/xtensa/lib/checksum.S @@ -43,7 +43,7 @@ ENTRY(csum_partial) * Experiments with Ethernet and SLIP connections show that buf * is aligned on either a 2-byte or 4-byte boundary. */ - entry sp, 32 + abi_entry_default extui a5, a2, 0, 2 bnez a5, 8f /* branch if 2-byte aligned */ /* Fall-through on common case, 4-byte alignment */ @@ -107,7 +107,7 @@ ENTRY(csum_partial) ONES_ADD(a4, a6) 7: mov a2, a4 - retw + abi_ret_default /* uncommon case, buf is 2-byte aligned */ 8: @@ -195,7 +195,7 @@ unsigned int csum_partial_copy_generic (const char *src, char *dst, int len, ENTRY(csum_partial_copy_generic) - entry sp, 32 + abi_entry_default mov a12, a3 mov a11, a4 or a10, a2, a3 @@ -316,7 +316,7 @@ EX(11f) s8i a9, a3, 0 ONES_ADD(a5, a9) 8: mov a2, a5 - retw + abi_ret_default 5: /* Control branch to here when either src or dst is odd. We @@ -383,12 +383,12 @@ ENDPROC(csum_partial_copy_generic) blt a12, a11, .Leloop #endif 2: - retw + abi_ret_default 11: movi a2, -EFAULT s32i a2, a7, 0 /* dst_err_ptr */ movi a2, 0 - retw + abi_ret_default .previous diff --git a/arch/xtensa/lib/memcopy.S b/arch/xtensa/lib/memcopy.S index efecfd7ed8cc..582d817979ed 100644 --- a/arch/xtensa/lib/memcopy.S +++ b/arch/xtensa/lib/memcopy.S @@ -79,7 +79,7 @@ bne a3, a7, .Lnextbyte # continue loop if $a3:src != $a7:src_end #endif /* !XCHAL_HAVE_LOOPS */ .Lbytecopydone: - retw + abi_ret_default /* * Destination is unaligned @@ -112,7 +112,7 @@ ENTRY(__memcpy) WEAK(memcpy) - entry sp, 16 # minimal stack frame + abi_entry_default # a2/ dst, a3/ src, a4/ len mov a5, a2 # copy dst so that a2 is return value .Lcommon: @@ -161,7 +161,7 @@ WEAK(memcpy) bbsi.l a4, 2, .L3 bbsi.l a4, 1, .L4 bbsi.l a4, 0, .L5 - retw + abi_ret_default .L3: # copy 4 bytes l32i a6, a3, 0 @@ -170,7 +170,7 @@ WEAK(memcpy) addi a5, a5, 4 bbsi.l a4, 1, .L4 bbsi.l a4, 0, .L5 - retw + abi_ret_default .L4: # copy 2 bytes l16ui a6, a3, 0 @@ -178,12 +178,12 @@ WEAK(memcpy) s16i a6, a5, 0 addi a5, a5, 2 bbsi.l a4, 0, .L5 - retw + abi_ret_default .L5: # copy 1 byte l8ui a6, a3, 0 s8i a6, a5, 0 - retw + abi_ret_default /* * Destination is aligned, Source is unaligned @@ -255,7 +255,7 @@ WEAK(memcpy) #endif bbsi.l a4, 1, .L14 bbsi.l a4, 0, .L15 -.Ldone: retw +.Ldone: abi_ret_default .L14: # copy 2 bytes l8ui a6, a3, 0 @@ -265,12 +265,12 @@ WEAK(memcpy) s8i a7, a5, 1 addi a5, a5, 2 bbsi.l a4, 0, .L15 - retw + abi_ret_default .L15: # copy 1 byte l8ui a6, a3, 0 s8i a6, a5, 0 - retw + abi_ret_default ENDPROC(__memcpy) @@ -280,7 +280,7 @@ ENDPROC(__memcpy) ENTRY(bcopy) - entry sp, 16 # minimal stack frame + abi_entry_default # a2=src, a3=dst, a4=len mov a5, a3 mov a3, a2 @@ -346,7 +346,7 @@ ENDPROC(bcopy) # $a3:src != $a7:src_start #endif /* !XCHAL_HAVE_LOOPS */ .Lbackbytecopydone: - retw + abi_ret_default /* * Destination is unaligned @@ -380,7 +380,7 @@ ENDPROC(bcopy) ENTRY(__memmove) WEAK(memmove) - entry sp, 16 # minimal stack frame + abi_entry_default # a2/ dst, a3/ src, a4/ len mov a5, a2 # copy dst so that a2 is return value .Lmovecommon: @@ -435,7 +435,7 @@ WEAK(memmove) bbsi.l a4, 2, .Lback3 bbsi.l a4, 1, .Lback4 bbsi.l a4, 0, .Lback5 - retw + abi_ret_default .Lback3: # copy 4 bytes addi a3, a3, -4 @@ -444,7 +444,7 @@ WEAK(memmove) s32i a6, a5, 0 bbsi.l a4, 1, .Lback4 bbsi.l a4, 0, .Lback5 - retw + abi_ret_default .Lback4: # copy 2 bytes addi a3, a3, -2 @@ -452,14 +452,14 @@ WEAK(memmove) addi a5, a5, -2 s16i a6, a5, 0 bbsi.l a4, 0, .Lback5 - retw + abi_ret_default .Lback5: # copy 1 byte addi a3, a3, -1 l8ui a6, a3, 0 addi a5, a5, -1 s8i a6, a5, 0 - retw + abi_ret_default /* * Destination is aligned, Source is unaligned @@ -531,7 +531,7 @@ WEAK(memmove) bbsi.l a4, 1, .Lback14 bbsi.l a4, 0, .Lback15 .Lbackdone: - retw + abi_ret_default .Lback14: # copy 2 bytes addi a3, a3, -2 @@ -541,13 +541,13 @@ WEAK(memmove) s8i a6, a5, 0 s8i a7, a5, 1 bbsi.l a4, 0, .Lback15 - retw + abi_ret_default .Lback15: # copy 1 byte addi a3, a3, -1 addi a5, a5, -1 l8ui a6, a3, 0 s8i a6, a5, 0 - retw + abi_ret_default ENDPROC(__memmove) diff --git a/arch/xtensa/lib/memset.S b/arch/xtensa/lib/memset.S index 8632eacbdc80..59b1524fd601 100644 --- a/arch/xtensa/lib/memset.S +++ b/arch/xtensa/lib/memset.S @@ -34,7 +34,7 @@ ENTRY(__memset) WEAK(memset) - entry sp, 16 # minimal stack frame + abi_entry_default # a2/ dst, a3/ c, a4/ length extui a3, a3, 0, 8 # mask to just 8 bits slli a7, a3, 8 # duplicate character in all bytes of word @@ -48,7 +48,7 @@ WEAK(memset) srli a7, a4, 4 # number of loop iterations with 16B # per iteration bnez a4, .Laligned - retw + abi_ret_default /* * Destination is word-aligned. @@ -95,7 +95,7 @@ EX(10f) s16i a3, a5, 0 EX(10f) s8i a3, a5, 0 .L5: .Lret1: - retw + abi_ret_default /* * Destination is unaligned @@ -139,7 +139,7 @@ EX(10f) s8i a3, a5, 0 blt a5, a6, .Lbyteloop #endif /* !XCHAL_HAVE_LOOPS */ .Lbytesetdone: - retw + abi_ret_default ENDPROC(__memset) @@ -150,4 +150,4 @@ ENDPROC(__memset) 10: movi a2, 0 - retw + abi_ret_default diff --git a/arch/xtensa/lib/strncpy_user.S b/arch/xtensa/lib/strncpy_user.S index c4c6c8578d59..4faf46fe3f38 100644 --- a/arch/xtensa/lib/strncpy_user.S +++ b/arch/xtensa/lib/strncpy_user.S @@ -50,7 +50,7 @@ .text ENTRY(__strncpy_user) - entry sp, 16 # minimal stack frame + abi_entry_default # a2/ dst, a3/ src, a4/ len mov a11, a2 # leave dst in return value register beqz a4, .Lret # if len is zero @@ -93,7 +93,7 @@ EX(10f) s8i a9, a11, 0 # store byte 0 bnez a4, .Lsrcaligned # if len is nonzero .Lret: sub a2, a11, a2 # compute strlen - retw + abi_ret_default /* * dst is word-aligned, src is word-aligned @@ -148,14 +148,14 @@ EX(10f) s8i a9, a11, 0 .Lz3: # byte 3 is zero addi a11, a11, 3 # advance dst pointer sub a2, a11, a2 # compute strlen - retw + abi_ret_default .Lz0: # byte 0 is zero #ifdef __XTENSA_EB__ movi a9, 0 #endif /* __XTENSA_EB__ */ EX(10f) s8i a9, a11, 0 sub a2, a11, a2 # compute strlen - retw + abi_ret_default .Lz1: # byte 1 is zero #ifdef __XTENSA_EB__ extui a9, a9, 16, 16 @@ -163,7 +163,7 @@ EX(10f) s8i a9, a11, 0 EX(10f) s16i a9, a11, 0 addi a11, a11, 1 # advance dst pointer sub a2, a11, a2 # compute strlen - retw + abi_ret_default .Lz2: # byte 2 is zero #ifdef __XTENSA_EB__ extui a9, a9, 16, 16 @@ -173,7 +173,7 @@ EX(10f) s16i a9, a11, 0 EX(10f) s8i a9, a11, 2 addi a11, a11, 2 # advance dst pointer sub a2, a11, a2 # compute strlen - retw + abi_ret_default .align 4 # 1 mod 4 alignment for LOOPNEZ .byte 0 # (0 mod 4 alignment for LBEG) @@ -199,7 +199,7 @@ EX(10f) s8i a9, a11, 0 .Lunalignedend: sub a2, a11, a2 # compute strlen - retw + abi_ret_default ENDPROC(__strncpy_user) @@ -214,4 +214,4 @@ ENDPROC(__strncpy_user) 10: 11: movi a2, -EFAULT - retw + abi_ret_default diff --git a/arch/xtensa/lib/strnlen_user.S b/arch/xtensa/lib/strnlen_user.S index 1f2ca2bb2ab3..3d391dca3efb 100644 --- a/arch/xtensa/lib/strnlen_user.S +++ b/arch/xtensa/lib/strnlen_user.S @@ -45,7 +45,7 @@ .text ENTRY(__strnlen_user) - entry sp, 16 # minimal stack frame + abi_entry_default # a2/ s, a3/ len addi a4, a2, -4 # because we overincrement at the end; # we compensate with load offsets of 4 @@ -96,7 +96,7 @@ EX(10f) l32i a9, a4, 4 # load 4 bytes for remaining checks addi a4, a4, 1 # advance string pointer .L101: sub a2, a4, a2 # compute length - retw + abi_ret_default # NOTE that in several places below, we point to the byte just after # the zero byte in order to include the NULL terminator in the count. @@ -106,15 +106,15 @@ EX(10f) l32i a9, a4, 4 # load 4 bytes for remaining checks .Lz0: # byte 0 is zero addi a4, a4, 1 # point just beyond zero byte sub a2, a4, a2 # subtract to get length - retw + abi_ret_default .Lz1: # byte 1 is zero addi a4, a4, 1+1 # point just beyond zero byte sub a2, a4, a2 # subtract to get length - retw + abi_ret_default .Lz2: # byte 2 is zero addi a4, a4, 2+1 # point just beyond zero byte sub a2, a4, a2 # subtract to get length - retw + abi_ret_default .L1mod2: # address is odd EX(10f) l8ui a9, a4, 4 # get byte 0 @@ -130,7 +130,7 @@ EX(10f) l32i a9, a4, 0 # get word with first two bytes of string # byte 3 is zero addi a4, a4, 3+1 # point just beyond zero byte sub a2, a4, a2 # subtract to get length - retw + abi_ret_default ENDPROC(__strnlen_user) @@ -138,4 +138,4 @@ ENDPROC(__strnlen_user) .align 4 10: movi a2, 0 - retw + abi_ret_default diff --git a/arch/xtensa/lib/usercopy.S b/arch/xtensa/lib/usercopy.S index 228607e30bc2..a0aa4047f94a 100644 --- a/arch/xtensa/lib/usercopy.S +++ b/arch/xtensa/lib/usercopy.S @@ -60,7 +60,7 @@ .text ENTRY(__xtensa_copy_user) - entry sp, 16 # minimal stack frame + abi_entry_default # a2/ dst, a3/ src, a4/ len mov a5, a2 # copy dst so that a2 is return value mov a11, a4 # preserve original len for error case @@ -75,7 +75,7 @@ ENTRY(__xtensa_copy_user) __ssa8 a3 # set shift amount from byte offset bnez a4, .Lsrcunaligned movi a2, 0 # return success for len==0 - retw + abi_ret_default /* * Destination is unaligned @@ -127,7 +127,7 @@ EX(10f) s8i a6, a5, 0 #endif /* !XCHAL_HAVE_LOOPS */ .Lbytecopydone: movi a2, 0 # return success for len bytes copied - retw + abi_ret_default /* * Destination and source are word-aligned. @@ -187,7 +187,7 @@ EX(10f) l8ui a6, a3, 0 EX(10f) s8i a6, a5, 0 .L5: movi a2, 0 # return success for len bytes copied - retw + abi_ret_default /* * Destination is aligned, Source is unaligned @@ -264,7 +264,7 @@ EX(10f) l8ui a6, a3, 0 EX(10f) s8i a6, a5, 0 .L15: movi a2, 0 # return success for len bytes copied - retw + abi_ret_default ENDPROC(__xtensa_copy_user) @@ -281,4 +281,4 @@ ENDPROC(__xtensa_copy_user) 10: sub a2, a5, a2 /* a2 <-- bytes copied */ sub a2, a11, a2 /* a2 <-- bytes not copied */ - retw + abi_ret_default diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c index b51746f2b80b..79467c749416 100644 --- a/arch/xtensa/mm/init.c +++ b/arch/xtensa/mm/init.c @@ -45,10 +45,7 @@ void __init bootmem_init(void) * If PHYS_OFFSET is zero reserve page at address 0: * successfull allocations should never return NULL. */ - if (PHYS_OFFSET) - memblock_reserve(0, PHYS_OFFSET); - else - memblock_reserve(0, 1); + memblock_reserve(0, PHYS_OFFSET ? PHYS_OFFSET : 1); early_init_fdt_scan_reserved_mem(); diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S index 11a01c3e9cea..6aa036c427c3 100644 --- a/arch/xtensa/mm/misc.S +++ b/arch/xtensa/mm/misc.S @@ -30,7 +30,7 @@ ENTRY(clear_page) - entry a1, 16 + abi_entry_default movi a3, 0 __loopi a2, a7, PAGE_SIZE, 32 @@ -44,7 +44,7 @@ ENTRY(clear_page) s32i a3, a2, 28 __endla a2, a7, 32 - retw + abi_ret_default ENDPROC(clear_page) @@ -57,7 +57,7 @@ ENDPROC(clear_page) ENTRY(copy_page) - entry a1, 16 + abi_entry_default __loopi a2, a4, PAGE_SIZE, 32 @@ -86,7 +86,7 @@ ENTRY(copy_page) __endl a2, a4 - retw + abi_ret_default ENDPROC(copy_page) @@ -116,7 +116,7 @@ ENTRY(__tlbtemp_mapping_start) ENTRY(clear_page_alias) - entry a1, 32 + abi_entry_default /* Skip setting up a temporary DTLB if not aliased low page. */ @@ -144,14 +144,14 @@ ENTRY(clear_page_alias) __endla a2, a7, 32 bnez a6, 1f - retw + abi_ret_default /* We need to invalidate the temporary idtlb entry, if any. */ 1: idtlb a4 dsync - retw + abi_ret_default ENDPROC(clear_page_alias) @@ -164,7 +164,7 @@ ENDPROC(clear_page_alias) ENTRY(copy_page_alias) - entry a1, 32 + abi_entry_default /* Skip setting up a temporary DTLB for destination if not aliased. */ @@ -221,19 +221,19 @@ ENTRY(copy_page_alias) bnez a6, 1f bnez a7, 2f - retw + abi_ret_default 1: addi a2, a2, -PAGE_SIZE idtlb a2 dsync bnez a7, 2f - retw + abi_ret_default 2: addi a3, a3, -PAGE_SIZE+1 idtlb a3 dsync - retw + abi_ret_default ENDPROC(copy_page_alias) @@ -248,7 +248,7 @@ ENDPROC(copy_page_alias) ENTRY(__flush_invalidate_dcache_page_alias) - entry sp, 16 + abi_entry_default movi a7, 0 # required for exception handler addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) @@ -261,7 +261,7 @@ ENTRY(__flush_invalidate_dcache_page_alias) idtlb a4 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_page_alias) @@ -272,7 +272,7 @@ ENDPROC(__flush_invalidate_dcache_page_alias) ENTRY(__invalidate_dcache_page_alias) - entry sp, 16 + abi_entry_default movi a7, 0 # required for exception handler addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) @@ -285,7 +285,7 @@ ENTRY(__invalidate_dcache_page_alias) idtlb a4 dsync - retw + abi_ret_default ENDPROC(__invalidate_dcache_page_alias) #endif @@ -296,7 +296,7 @@ ENTRY(__tlbtemp_mapping_itlb) ENTRY(__invalidate_icache_page_alias) - entry sp, 16 + abi_entry_default addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE) mov a4, a2 @@ -307,7 +307,7 @@ ENTRY(__invalidate_icache_page_alias) iitlb a4 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_page_alias) @@ -325,12 +325,12 @@ ENTRY(__tlbtemp_mapping_end) ENTRY(__invalidate_icache_page) - entry sp, 16 + abi_entry_default ___invalidate_icache_page a2 a3 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_page) @@ -340,12 +340,12 @@ ENDPROC(__invalidate_icache_page) ENTRY(__invalidate_dcache_page) - entry sp, 16 + abi_entry_default ___invalidate_dcache_page a2 a3 dsync - retw + abi_ret_default ENDPROC(__invalidate_dcache_page) @@ -355,12 +355,12 @@ ENDPROC(__invalidate_dcache_page) ENTRY(__flush_invalidate_dcache_page) - entry sp, 16 + abi_entry_default ___flush_invalidate_dcache_page a2 a3 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_page) @@ -370,12 +370,12 @@ ENDPROC(__flush_invalidate_dcache_page) ENTRY(__flush_dcache_page) - entry sp, 16 + abi_entry_default ___flush_dcache_page a2 a3 dsync - retw + abi_ret_default ENDPROC(__flush_dcache_page) @@ -385,12 +385,12 @@ ENDPROC(__flush_dcache_page) ENTRY(__invalidate_icache_range) - entry sp, 16 + abi_entry_default ___invalidate_icache_range a2 a3 a4 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_range) @@ -400,12 +400,12 @@ ENDPROC(__invalidate_icache_range) ENTRY(__flush_invalidate_dcache_range) - entry sp, 16 + abi_entry_default ___flush_invalidate_dcache_range a2 a3 a4 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_range) @@ -415,12 +415,12 @@ ENDPROC(__flush_invalidate_dcache_range) ENTRY(__flush_dcache_range) - entry sp, 16 + abi_entry_default ___flush_dcache_range a2 a3 a4 dsync - retw + abi_ret_default ENDPROC(__flush_dcache_range) @@ -430,11 +430,11 @@ ENDPROC(__flush_dcache_range) ENTRY(__invalidate_dcache_range) - entry sp, 16 + abi_entry_default ___invalidate_dcache_range a2 a3 a4 - retw + abi_ret_default ENDPROC(__invalidate_dcache_range) @@ -444,12 +444,12 @@ ENDPROC(__invalidate_dcache_range) ENTRY(__invalidate_icache_all) - entry sp, 16 + abi_entry_default ___invalidate_icache_all a2 a3 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_all) @@ -459,12 +459,12 @@ ENDPROC(__invalidate_icache_all) ENTRY(__flush_invalidate_dcache_all) - entry sp, 16 + abi_entry_default ___flush_invalidate_dcache_all a2 a3 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_all) @@ -474,11 +474,11 @@ ENDPROC(__flush_invalidate_dcache_all) ENTRY(__invalidate_dcache_all) - entry sp, 16 + abi_entry_default ___invalidate_dcache_all a2 a3 dsync - retw + abi_ret_default ENDPROC(__invalidate_dcache_all) |