diff options
Diffstat (limited to 'drivers/clk/hisilicon')
| -rw-r--r-- | drivers/clk/hisilicon/Kconfig | 13 | ||||
| -rw-r--r-- | drivers/clk/hisilicon/crg-hi3798cv200.c | 17 |
2 files changed, 25 insertions, 5 deletions
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index 1bd43550e4c8..becdb1dd21b5 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -44,14 +44,17 @@ config RESET_HISI Build reset controller driver for HiSilicon device chipsets. config STUB_CLK_HI6220 - bool "Hi6220 Stub Clock Driver" - depends on COMMON_CLK_HI6220 && MAILBOX - default ARCH_HISI + bool "Hi6220 Stub Clock Driver" if EXPERT + depends on (COMMON_CLK_HI6220 || COMPILE_TEST) + depends on MAILBOX + default COMMON_CLK_HI6220 help Build the Hisilicon Hi6220 stub clock driver. config STUB_CLK_HI3660 - bool "Hi3660 Stub Clock Driver" - depends on COMMON_CLK_HI3660 && MAILBOX + bool "Hi3660 Stub Clock Driver" if EXPERT + depends on (COMMON_CLK_HI3660 || COMPILE_TEST) + depends on MAILBOX + default COMMON_CLK_HI3660 help Build the Hisilicon Hi3660 stub clock driver. diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index 743eec131528..4fe0b2a9baf1 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -186,6 +186,23 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, + /* USB3 */ + { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL, + CLK_SET_RATE_PARENT, 0xb0, 0, 0 }, + { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL, + CLK_SET_RATE_PARENT, 0xb0, 4, 0 }, + { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL, + CLK_SET_RATE_PARENT, 0xb0, 3, 0 }, + { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL, + CLK_SET_RATE_PARENT, 0xb0, 2, 0 }, + { HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL, + CLK_SET_RATE_PARENT, 0xb0, 16, 0 }, + { HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL, + CLK_SET_RATE_PARENT, 0xb0, 20, 0 }, + { HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL, + CLK_SET_RATE_PARENT, 0xb0, 19, 0 }, + { HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL, + CLK_SET_RATE_PARENT, 0xb0, 18, 0 }, }; static struct hisi_clock_data *hi3798cv200_clk_register( |