diff options
Diffstat (limited to 'drivers/clk/tegra/clk-tegra210.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 499 |
1 files changed, 461 insertions, 38 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 2896d2e783ce..1024e853ea65 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -24,6 +24,8 @@ #include <linux/export.h> #include <linux/clk/tegra.h> #include <dt-bindings/clock/tegra210-car.h> +#include <dt-bindings/reset/tegra210-car.h> +#include <linux/iopoll.h> #include "clk.h" #include "clk-id.h" @@ -155,9 +157,35 @@ #define PMC_PLLM_WB0_OVERRIDE 0x1dc #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 +#define UTMIP_PLL_CFG2 0x488 +#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) +#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) + +#define UTMIP_PLL_CFG1 0x484 +#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) +#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) +#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) +#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) +#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) +#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) +#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) + #define SATA_PLL_CFG0 0x490 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) +#define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4) +#define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5) +#define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6) +#define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7) + #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) @@ -196,6 +224,12 @@ #define CLK_M_DIVISOR_SHIFT 2 #define CLK_M_DIVISOR_MASK 0x3 +#define RST_DFLL_DVCO 0x2f4 +#define DVFS_DFLL_RESET_SHIFT 0 + +#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 +#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac + /* * SDM fractional divisor is 16-bit 2's complement signed number within * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned @@ -454,6 +488,26 @@ void tegra210_sata_pll_hw_sequence_start(void) } EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); +void tegra210_set_sata_pll_seq_sw(bool state) +{ + u32 val; + + val = readl_relaxed(clk_base + SATA_PLL_CFG0); + if (state) { + val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; + val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; + val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; + val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; + } else { + val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; + val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; + val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; + val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; + } + writel_relaxed(val, clk_base + SATA_PLL_CFG0); +} +EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw); + static inline void _pll_misc_chk_default(void __iomem *base, struct tegra_clk_pll_params *params, u8 misc_num, u32 default_val, u32 mask) @@ -501,12 +555,12 @@ static void tegra210_pllcx_set_defaults(const char *name, { pllcx->params->defaults_set = true; - if (readl_relaxed(clk_base + pllcx->params->base_reg) & - PLL_ENABLE) { + if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { /* PLL is ON: only check if defaults already set */ pllcx_check_defaults(pllcx->params); - pr_warn("%s already enabled. Postponing set full defaults\n", - name); + if (!pllcx->params->defaults_set) + pr_warn("%s already enabled. Postponing set full defaults\n", + name); return; } @@ -608,7 +662,6 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) if (readl_relaxed(clk_base + plld->params->base_reg) & PLL_ENABLE) { - pr_warn("PLL_D already enabled. Postponing set full defaults\n"); /* * PLL is ON: check if defaults already set, then set those @@ -625,6 +678,9 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) _pll_misc_chk_default(clk_base, plld->params, 0, val, ~mask & PLLD_MISC0_WRITE_MASK); + if (!plld->params->defaults_set) + pr_warn("PLL_D already enabled. Postponing set full defaults\n"); + /* Enable lock detect */ mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE; val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); @@ -896,7 +952,6 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { - pr_warn("PLL_X already enabled. Postponing set full defaults\n"); /* * PLL is ON: check if defaults already set, then set those @@ -904,6 +959,8 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) */ pllx_check_defaults(pllx); + if (!pllx->params->defaults_set) + pr_warn("PLL_X already enabled. Postponing set full defaults\n"); /* Configure dyn ramp, disable lock override */ writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); @@ -948,7 +1005,6 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) pllmb->params->defaults_set = true; if (val & PLL_ENABLE) { - pr_warn("PLL_MB already enabled. Postponing set full defaults\n"); /* * PLL is ON: check if defaults already set, then set those @@ -959,6 +1015,8 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) _pll_misc_chk_default(clk_base, pllmb->params, 0, val, ~mask & PLLMB_MISC1_WRITE_MASK); + if (!pllmb->params->defaults_set) + pr_warn("PLL_MB already enabled. Postponing set full defaults\n"); /* Enable lock detect */ val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); val &= ~mask; @@ -1008,13 +1066,14 @@ static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) pllp->params->defaults_set = true; if (val & PLL_ENABLE) { - pr_warn("PLL_P already enabled. Postponing set full defaults\n"); /* * PLL is ON: check if defaults already set, then set those * that can be updated in flight. */ pllp_check_defaults(pllp, true); + if (!pllp->params->defaults_set) + pr_warn("PLL_P already enabled. Postponing set full defaults\n"); /* Enable lock detect */ val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); @@ -1046,47 +1105,49 @@ static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz, * respectively. */ -static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control) +static void pllu_check_defaults(struct tegra_clk_pll_params *params, + bool hw_control) { u32 val, mask; /* Ignore lock enable (will be set) and IDDQ if under h/w control */ val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ); mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0); - _pll_misc_chk_default(clk_base, pll->params, 0, val, + _pll_misc_chk_default(clk_base, params, 0, val, ~mask & PLLU_MISC0_WRITE_MASK); val = PLLU_MISC1_DEFAULT_VALUE; mask = PLLU_MISC1_LOCK_OVERRIDE; - _pll_misc_chk_default(clk_base, pll->params, 1, val, + _pll_misc_chk_default(clk_base, params, 1, val, ~mask & PLLU_MISC1_WRITE_MASK); } -static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu) +static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu) { - u32 val = readl_relaxed(clk_base + pllu->params->base_reg); + u32 val = readl_relaxed(clk_base + pllu->base_reg); - pllu->params->defaults_set = true; + pllu->defaults_set = true; if (val & PLL_ENABLE) { - pr_warn("PLL_U already enabled. Postponing set full defaults\n"); /* * PLL is ON: check if defaults already set, then set those * that can be updated in flight. */ pllu_check_defaults(pllu, false); + if (!pllu->defaults_set) + pr_warn("PLL_U already enabled. Postponing set full defaults\n"); /* Enable lock detect */ - val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[0]); + val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); val &= ~PLLU_MISC0_LOCK_ENABLE; val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE; - writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[0]); + writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); - val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[1]); + val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); val &= ~PLLU_MISC1_LOCK_OVERRIDE; val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE; - writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[1]); + writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); udelay(1); return; @@ -1094,9 +1155,9 @@ static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu) /* set IDDQ, enable lock detect */ writel_relaxed(PLLU_MISC0_DEFAULT_VALUE, - clk_base + pllu->params->ext_misc_reg[0]); + clk_base + pllu->ext_misc_reg[0]); writel_relaxed(PLLU_MISC1_DEFAULT_VALUE, - clk_base + pllu->params->ext_misc_reg[1]); + clk_base + pllu->ext_misc_reg[1]); udelay(1); } @@ -1216,6 +1277,7 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, cfg->n = p_rate / cf; cfg->sdm_data = 0; + cfg->output_rate = input_rate; if (params->sdm_ctrl_reg) { unsigned long rem = p_rate - cf * cfg->n; /* If ssc is enabled SDM enabled as well, even for integer n */ @@ -1226,10 +1288,15 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, s -= PLL_SDM_COEFF / 2; cfg->sdm_data = sdin_din_to_data(s); } + cfg->output_rate *= cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 + + sdin_data_to_din(cfg->sdm_data); + cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF; + } else { + cfg->output_rate *= cfg->n; + cfg->output_rate /= p * cfg->m; } cfg->input_rate = input_rate; - cfg->output_rate = rate; return 0; } @@ -1772,7 +1839,7 @@ static struct tegra_clk_pll_params pll_a1_params = { .misc_reg = PLLA1_MISC0, .lock_mask = PLLCX_BASE_LOCK, .lock_delay = 300, - .iddq_reg = PLLA1_MISC0, + .iddq_reg = PLLA1_MISC1, .iddq_bit_idx = PLLCX_IDDQ_BIT, .reset_reg = PLLA1_MISC0, .reset_bit_idx = PLLCX_RESET_BIT, @@ -1987,9 +2054,9 @@ static struct div_nmp pllu_nmp = { }; static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { - { 12000000, 480000000, 40, 1, 1, 0 }, - { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */ - { 38400000, 480000000, 25, 2, 1, 0 }, + { 12000000, 480000000, 40, 1, 0, 0 }, + { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */ + { 38400000, 480000000, 25, 2, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -2013,8 +2080,47 @@ static struct tegra_clk_pll_params pll_u_vco_params = { .div_nmp = &pllu_nmp, .freq_table = pll_u_freq_table, .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, - .set_defaults = tegra210_pllu_set_defaults, - .calc_rate = tegra210_pll_fixed_mdiv_cfg, +}; + +struct utmi_clk_param { + /* Oscillator Frequency in KHz */ + u32 osc_frequency; + /* UTMIP PLL Enable Delay Count */ + u8 enable_delay_count; + /* UTMIP PLL Stable count */ + u16 stable_count; + /* UTMIP PLL Active delay count */ + u8 active_delay_count; + /* UTMIP PLL Xtal frequency count */ + u16 xtal_freq_count; +}; + +static const struct utmi_clk_param utmi_parameters[] = { + { + .osc_frequency = 38400000, .enable_delay_count = 0x0, + .stable_count = 0x0, .active_delay_count = 0x6, + .xtal_freq_count = 0x80 + }, { + .osc_frequency = 13000000, .enable_delay_count = 0x02, + .stable_count = 0x33, .active_delay_count = 0x05, + .xtal_freq_count = 0x7f + }, { + .osc_frequency = 19200000, .enable_delay_count = 0x03, + .stable_count = 0x4b, .active_delay_count = 0x06, + .xtal_freq_count = 0xbb + }, { + .osc_frequency = 12000000, .enable_delay_count = 0x02, + .stable_count = 0x2f, .active_delay_count = 0x08, + .xtal_freq_count = 0x76 + }, { + .osc_frequency = 26000000, .enable_delay_count = 0x04, + .stable_count = 0x66, .active_delay_count = 0x09, + .xtal_freq_count = 0xfe + }, { + .osc_frequency = 16800000, .enable_delay_count = 0x03, + .stable_count = 0x41, .active_delay_count = 0x0a, + .xtal_freq_count = 0xa4 + }, }; static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { @@ -2115,7 +2221,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true }, [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true }, [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true }, - [tegra_clk_pll_m_out1] = { .dt_id = TEGRA210_CLK_PLL_M_OUT1, .present = true }, [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true }, [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true }, @@ -2209,6 +2314,25 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true }, + [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true }, + [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true }, + [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true }, + [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true }, + [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true }, + [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true }, + [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true }, + [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true }, + [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true }, + [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true }, + [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true }, + [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true }, + [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true }, + [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true }, + [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true }, + [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true }, + [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true }, + [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true }, + [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true }, }; static struct tegra_devclk devclks[] __initdata = { @@ -2227,7 +2351,6 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 }, { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 }, { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M }, - { .con_id = "pll_m_out1", .dt_id = TEGRA210_CLK_PLL_M_OUT1 }, { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X }, { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 }, { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U }, @@ -2286,6 +2409,221 @@ static struct tegra_audio_clk_info tegra210_audio_plls[] = { static struct clk **clks; +static const char * const aclk_parents[] = { + "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3", + "clk_m" +}; + +void tegra210_put_utmipll_in_iddq(void) +{ + u32 reg; + + reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); + + if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) { + pr_err("trying to assert IDDQ while UTMIPLL is locked\n"); + return; + } + + reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; + writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); +} +EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq); + +void tegra210_put_utmipll_out_iddq(void) +{ + u32 reg; + + reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); + reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; + writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); +} +EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq); + +static void tegra210_utmi_param_configure(void) +{ + u32 reg; + int i; + + for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { + if (osc_freq == utmi_parameters[i].osc_frequency) + break; + } + + if (i >= ARRAY_SIZE(utmi_parameters)) { + pr_err("%s: Unexpected oscillator freq %lu\n", __func__, + osc_freq); + return; + } + + reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); + reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; + writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); + + udelay(10); + + reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); + + /* Program UTMIP PLL stable and active counts */ + /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ + reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); + reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); + + reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); + + reg |= + UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count); + writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); + + /* Program UTMIP PLL delay and oscillator frequency counts */ + reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); + reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); + + reg |= + UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count); + + reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); + reg |= + UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count); + + reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; + writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); + + /* Remove power downs from UTMIP PLL control bits */ + reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); + reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; + reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; + writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); + udelay(1); + + /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */ + reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); + reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; + reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; + reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; + reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; + reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; + reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; + writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); + + /* Setup HW control of UTMIPLL */ + reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); + reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; + reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; + writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); + + reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); + reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; + reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; + writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); + + udelay(1); + + reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); + reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; + writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); + + udelay(1); + + /* Enable HW control UTMIPLL */ + reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); + reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; + writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); +} + +static int tegra210_enable_pllu(void) +{ + struct tegra_clk_pll_freq_table *fentry; + struct tegra_clk_pll pllu; + u32 reg; + + for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) { + if (fentry->input_rate == pll_ref_freq) + break; + } + + if (!fentry->input_rate) { + pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq); + return -EINVAL; + } + + /* clear IDDQ bit */ + pllu.params = &pll_u_vco_params; + reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); + reg &= ~BIT(pllu.params->iddq_bit_idx); + writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); + + reg = readl_relaxed(clk_base + PLLU_BASE); + reg &= ~GENMASK(20, 0); + reg |= fentry->m; + reg |= fentry->n << 8; + reg |= fentry->p << 16; + writel(reg, clk_base + PLLU_BASE); + reg |= PLL_ENABLE; + writel(reg, clk_base + PLLU_BASE); + + readl_relaxed_poll_timeout(clk_base + PLLU_BASE, reg, + reg & PLL_BASE_LOCK, 2, 1000); + if (!(reg & PLL_BASE_LOCK)) { + pr_err("Timed out waiting for PLL_U to lock\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int tegra210_init_pllu(void) +{ + u32 reg; + int err; + + tegra210_pllu_set_defaults(&pll_u_vco_params); + /* skip initialization when pllu is in hw controlled mode */ + reg = readl_relaxed(clk_base + PLLU_BASE); + if (reg & PLLU_BASE_OVERRIDE) { + if (!(reg & PLL_ENABLE)) { + err = tegra210_enable_pllu(); + if (err < 0) { + WARN_ON(1); + return err; + } + } + /* enable hw controlled mode */ + reg = readl_relaxed(clk_base + PLLU_BASE); + reg &= ~PLLU_BASE_OVERRIDE; + writel(reg, clk_base + PLLU_BASE); + + reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); + reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | + PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | + PLLU_HW_PWRDN_CFG0_USE_LOCKDET; + reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | + PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); + writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); + + reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); + reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; + writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); + udelay(1); + + reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); + reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; + writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); + udelay(1); + + reg = readl_relaxed(clk_base + PLLU_BASE); + reg &= ~PLLU_BASE_CLKENABLE_USB; + writel_relaxed(reg, clk_base + PLLU_BASE); + } + + /* enable UTMIPLL hw control if not yet done by the bootloader */ + reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); + if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE)) + tegra210_utmi_param_configure(); + + return 0; +} + static __init void tegra210_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { @@ -2347,6 +2685,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, clk_register_clkdev(clk, "cml1", NULL); clks[TEGRA210_CLK_CML1] = clk; + clk = tegra_clk_register_super_clk("aclk", aclk_parents, + ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, + 0, NULL); + clks[TEGRA210_CLK_ACLK] = clk; + tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); } @@ -2402,9 +2745,6 @@ static void __init tegra210_pll_init(void __iomem *clk_base, clk_register_clkdev(clk, "pll_mb", NULL); clks[TEGRA210_CLK_PLL_MB] = clk; - clk_register_clkdev(clk, "pll_m_out1", NULL); - clks[TEGRA210_CLK_PLL_M_OUT1] = clk; - /* PLLM_UD */ clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", CLK_SET_RATE_PARENT, 1, 1); @@ -2412,11 +2752,12 @@ static void __init tegra210_pll_init(void __iomem *clk_base, clks[TEGRA210_CLK_PLL_M_UD] = clk; /* PLLU_VCO */ - clk = tegra_clk_register_pllu_tegra210("pll_u_vco", "pll_ref", - clk_base, 0, &pll_u_vco_params, - &pll_u_lock); - clk_register_clkdev(clk, "pll_u_vco", NULL); - clks[TEGRA210_CLK_PLL_U] = clk; + if (!tegra210_init_pllu()) { + clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, + 480*1000*1000); + clk_register_clkdev(clk, "pll_u_vco", NULL); + clks[TEGRA210_CLK_PLL_U] = clk; + } /* PLLU_OUT */ clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0, @@ -2651,6 +2992,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 }, { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 }, { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 }, + /* TODO find a way to enable this on-demand */ + { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 }, { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 }, { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 }, { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 }, @@ -2661,6 +3004,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 }, { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 }, { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 }, + { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 }, + { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 }, /* This MUST be the last entry. */ { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, }; @@ -2679,6 +3024,81 @@ static void __init tegra210_clock_apply_init_table(void) } /** + * tegra210_car_barrier - wait for pending writes to the CAR to complete + * + * Wait for any outstanding writes to the CAR MMIO space from this CPU + * to complete before continuing execution. No return value. + */ +static void tegra210_car_barrier(void) +{ + readl_relaxed(clk_base + RST_DFLL_DVCO); +} + +/** + * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset + * + * Assert the reset line of the DFLL's DVCO. No return value. + */ +static void tegra210_clock_assert_dfll_dvco_reset(void) +{ + u32 v; + + v = readl_relaxed(clk_base + RST_DFLL_DVCO); + v |= (1 << DVFS_DFLL_RESET_SHIFT); + writel_relaxed(v, clk_base + RST_DFLL_DVCO); + tegra210_car_barrier(); +} + +/** + * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset + * + * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to + * operate. No return value. + */ +static void tegra210_clock_deassert_dfll_dvco_reset(void) +{ + u32 v; + + v = readl_relaxed(clk_base + RST_DFLL_DVCO); + v &= ~(1 << DVFS_DFLL_RESET_SHIFT); + writel_relaxed(v, clk_base + RST_DFLL_DVCO); + tegra210_car_barrier(); +} + +static int tegra210_reset_assert(unsigned long id) +{ + if (id == TEGRA210_RST_DFLL_DVCO) + tegra210_clock_assert_dfll_dvco_reset(); + else if (id == TEGRA210_RST_ADSP) + writel(GENMASK(26, 21) | BIT(7), + clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET); + else + return -EINVAL; + + return 0; +} + +static int tegra210_reset_deassert(unsigned long id) +{ + if (id == TEGRA210_RST_DFLL_DVCO) + tegra210_clock_deassert_dfll_dvco_reset(); + else if (id == TEGRA210_RST_ADSP) { + writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); + /* + * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz) + * a delay of 5us ensures that it's at least + * 6 * adsp_cpu_cycle_period long. + */ + udelay(5); + writel(GENMASK(26, 22) | BIT(7), + clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); + } else + return -EINVAL; + + return 0; +} + +/** * tegra210_clock_init - Tegra210-specific clock initialization * @np: struct device_node * of the DT node for the SoC CAR IP block * @@ -2742,6 +3162,9 @@ static void __init tegra210_clock_init(struct device_node *np) tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, &pll_x_params); + tegra_init_special_resets(2, tegra210_reset_assert, + tegra210_reset_deassert); + tegra_add_of_provider(np); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); |