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path: root/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/navi10_ih.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/navi10_ih.c21
1 files changed, 19 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 74b1e7dc49a9..7ba229e43799 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -136,6 +136,9 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device *adev)
}
adev->irq.ih2.enabled = true;
}
+
+ if (adev->irq.ih_soft.ring_size)
+ adev->irq.ih_soft.enabled = true;
}
/**
@@ -314,6 +317,8 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
+ case CHIP_DIMGREY_CAVEFISH:
ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
@@ -440,6 +445,7 @@ static void navi10_ih_irq_disable(struct amdgpu_device *adev)
* navi10_ih_get_wptr - get the IH ring buffer wptr
*
* @adev: amdgpu_device pointer
+ * @ih: IH ring buffer to fetch wptr
*
* Get the IH ring buffer wptr from either the register
* or the writeback memory buffer (NAVI10). Also check for
@@ -500,6 +506,8 @@ out:
* navi10_ih_decode_iv - decode an interrupt vector
*
* @adev: amdgpu_device pointer
+ * @ih: IH ring buffer to decode
+ * @entry: IV entry to place decoded information into
*
* Decodes the interrupt vector at the current rptr
* position and also advance the position.
@@ -543,6 +551,7 @@ static void navi10_ih_decode_iv(struct amdgpu_device *adev,
* navi10_ih_irq_rearm - rearm IRQ if lost
*
* @adev: amdgpu_device pointer
+ * @ih: IH ring to match
*
*/
static void navi10_ih_irq_rearm(struct amdgpu_device *adev,
@@ -576,6 +585,7 @@ static void navi10_ih_irq_rearm(struct amdgpu_device *adev,
*
* @adev: amdgpu_device pointer
*
+ * @ih: IH ring buffer to set rptr
* Set the IH ring buffer rptr.
*/
static void navi10_ih_set_rptr(struct amdgpu_device *adev,
@@ -660,8 +670,11 @@ static int navi10_ih_sw_init(void *handle)
/* use gpu virtual address for ih ring
* until ih_checken is programmed to allow
* use bus address for ih ring by psp bl */
- use_bus_addr =
- (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
+ if ((adev->flags & AMD_IS_APU) ||
+ (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+ use_bus_addr = false;
+ else
+ use_bus_addr = true;
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
if (r)
return r;
@@ -690,6 +703,10 @@ static int navi10_ih_sw_init(void *handle)
(adev->doorbell_index.ih + 2) << 1;
}
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
+ if (r)
+ return r;
+
r = amdgpu_irq_init(adev);
return r;